//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
//
//
//
// Ports:
// Name                         I/O  size props
// RDY_v_mmio_server_0_request_put  O     1 reg
// v_mmio_server_0_response_get   O    65 reg
// RDY_v_mmio_server_0_response_get  O     1 reg
// RDY_v_mmio_server_1_request_put  O     1 reg
// v_mmio_server_1_response_get   O    65 reg
// RDY_v_mmio_server_1_response_get  O     1 reg
// mem_master_awvalid             O     1 reg
// mem_master_awid                O    16 reg
// mem_master_awaddr              O    64 reg
// mem_master_awlen               O     8 reg
// mem_master_awsize              O     3 reg
// mem_master_awburst             O     2 reg
// mem_master_awlock              O     1 reg
// mem_master_awcache             O     4 reg
// mem_master_awprot              O     3 reg
// mem_master_awqos               O     4 reg
// mem_master_awregion            O     4 reg
// mem_master_wvalid              O     1 reg
// mem_master_wdata               O    64 reg
// mem_master_wstrb               O     8 reg
// mem_master_wlast               O     1 reg
// mem_master_bready              O     1 reg
// mem_master_arvalid             O     1 reg
// mem_master_arid                O    16 reg
// mem_master_araddr              O    64 reg
// mem_master_arlen               O     8 reg
// mem_master_arsize              O     3 reg
// mem_master_arburst             O     2 reg
// mem_master_arlock              O     1 reg
// mem_master_arcache             O     4 reg
// mem_master_arprot              O     3 reg
// mem_master_arqos               O     4 reg
// mem_master_arregion            O     4 reg
// mem_master_rready              O     1 reg
// mv_write_error                 O     1 reg
// CLK                            I     1 clock
// RST_N                          I     1 reset
// v_mmio_server_0_request_put    I   131 reg
// v_mmio_server_1_request_put    I   131 reg
// mem_master_awready             I     1
// mem_master_wready              I     1
// mem_master_bvalid              I     1
// mem_master_bid                 I    16 reg
// mem_master_bresp               I     2 reg
// mem_master_arready             I     1
// mem_master_rvalid              I     1
// mem_master_rid                 I    16 reg
// mem_master_rdata               I    64 reg
// mem_master_rresp               I     2 reg
// mem_master_rlast               I     1 reg
// EN_v_mmio_server_0_request_put  I     1
// EN_v_mmio_server_1_request_put  I     1
// EN_v_mmio_server_0_response_get  I     1
// EN_v_mmio_server_1_response_get  I     1
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkMMIO_AXI4_Adapter_2(CLK,
			     RST_N,

			     v_mmio_server_0_request_put,
			     EN_v_mmio_server_0_request_put,
			     RDY_v_mmio_server_0_request_put,

			     EN_v_mmio_server_0_response_get,
			     v_mmio_server_0_response_get,
			     RDY_v_mmio_server_0_response_get,

			     v_mmio_server_1_request_put,
			     EN_v_mmio_server_1_request_put,
			     RDY_v_mmio_server_1_request_put,

			     EN_v_mmio_server_1_response_get,
			     v_mmio_server_1_response_get,
			     RDY_v_mmio_server_1_response_get,

			     mem_master_awvalid,

			     mem_master_awid,

			     mem_master_awaddr,

			     mem_master_awlen,

			     mem_master_awsize,

			     mem_master_awburst,

			     mem_master_awlock,

			     mem_master_awcache,

			     mem_master_awprot,

			     mem_master_awqos,

			     mem_master_awregion,

			     mem_master_awready,

			     mem_master_wvalid,

			     mem_master_wdata,

			     mem_master_wstrb,

			     mem_master_wlast,

			     mem_master_wready,

			     mem_master_bvalid,
			     mem_master_bid,
			     mem_master_bresp,

			     mem_master_bready,

			     mem_master_arvalid,

			     mem_master_arid,

			     mem_master_araddr,

			     mem_master_arlen,

			     mem_master_arsize,

			     mem_master_arburst,

			     mem_master_arlock,

			     mem_master_arcache,

			     mem_master_arprot,

			     mem_master_arqos,

			     mem_master_arregion,

			     mem_master_arready,

			     mem_master_rvalid,
			     mem_master_rid,
			     mem_master_rdata,
			     mem_master_rresp,
			     mem_master_rlast,

			     mem_master_rready,

			     mv_write_error);
  parameter [2 : 0] verbosity = 3'b0;
  input  CLK;
  input  RST_N;

  // action method v_mmio_server_0_request_put
  input  [130 : 0] v_mmio_server_0_request_put;
  input  EN_v_mmio_server_0_request_put;
  output RDY_v_mmio_server_0_request_put;

  // actionvalue method v_mmio_server_0_response_get
  input  EN_v_mmio_server_0_response_get;
  output [64 : 0] v_mmio_server_0_response_get;
  output RDY_v_mmio_server_0_response_get;

  // action method v_mmio_server_1_request_put
  input  [130 : 0] v_mmio_server_1_request_put;
  input  EN_v_mmio_server_1_request_put;
  output RDY_v_mmio_server_1_request_put;

  // actionvalue method v_mmio_server_1_response_get
  input  EN_v_mmio_server_1_response_get;
  output [64 : 0] v_mmio_server_1_response_get;
  output RDY_v_mmio_server_1_response_get;

  // value method mem_master_m_awvalid
  output mem_master_awvalid;

  // value method mem_master_m_awid
  output [15 : 0] mem_master_awid;

  // value method mem_master_m_awaddr
  output [63 : 0] mem_master_awaddr;

  // value method mem_master_m_awlen
  output [7 : 0] mem_master_awlen;

  // value method mem_master_m_awsize
  output [2 : 0] mem_master_awsize;

  // value method mem_master_m_awburst
  output [1 : 0] mem_master_awburst;

  // value method mem_master_m_awlock
  output mem_master_awlock;

  // value method mem_master_m_awcache
  output [3 : 0] mem_master_awcache;

  // value method mem_master_m_awprot
  output [2 : 0] mem_master_awprot;

  // value method mem_master_m_awqos
  output [3 : 0] mem_master_awqos;

  // value method mem_master_m_awregion
  output [3 : 0] mem_master_awregion;

  // value method mem_master_m_awuser

  // action method mem_master_m_awready
  input  mem_master_awready;

  // value method mem_master_m_wvalid
  output mem_master_wvalid;

  // value method mem_master_m_wdata
  output [63 : 0] mem_master_wdata;

  // value method mem_master_m_wstrb
  output [7 : 0] mem_master_wstrb;

  // value method mem_master_m_wlast
  output mem_master_wlast;

  // value method mem_master_m_wuser

  // action method mem_master_m_wready
  input  mem_master_wready;

  // action method mem_master_m_bvalid
  input  mem_master_bvalid;
  input  [15 : 0] mem_master_bid;
  input  [1 : 0] mem_master_bresp;

  // value method mem_master_m_bready
  output mem_master_bready;

  // value method mem_master_m_arvalid
  output mem_master_arvalid;

  // value method mem_master_m_arid
  output [15 : 0] mem_master_arid;

  // value method mem_master_m_araddr
  output [63 : 0] mem_master_araddr;

  // value method mem_master_m_arlen
  output [7 : 0] mem_master_arlen;

  // value method mem_master_m_arsize
  output [2 : 0] mem_master_arsize;

  // value method mem_master_m_arburst
  output [1 : 0] mem_master_arburst;

  // value method mem_master_m_arlock
  output mem_master_arlock;

  // value method mem_master_m_arcache
  output [3 : 0] mem_master_arcache;

  // value method mem_master_m_arprot
  output [2 : 0] mem_master_arprot;

  // value method mem_master_m_arqos
  output [3 : 0] mem_master_arqos;

  // value method mem_master_m_arregion
  output [3 : 0] mem_master_arregion;

  // value method mem_master_m_aruser

  // action method mem_master_m_arready
  input  mem_master_arready;

  // action method mem_master_m_rvalid
  input  mem_master_rvalid;
  input  [15 : 0] mem_master_rid;
  input  [63 : 0] mem_master_rdata;
  input  [1 : 0] mem_master_rresp;
  input  mem_master_rlast;

  // value method mem_master_m_rready
  output mem_master_rready;

  // value method mv_write_error
  output mv_write_error;

  // signals for module outputs
  wire [64 : 0] v_mmio_server_0_response_get, v_mmio_server_1_response_get;
  wire [63 : 0] mem_master_araddr, mem_master_awaddr, mem_master_wdata;
  wire [15 : 0] mem_master_arid, mem_master_awid;
  wire [7 : 0] mem_master_arlen, mem_master_awlen, mem_master_wstrb;
  wire [3 : 0] mem_master_arcache,
	       mem_master_arqos,
	       mem_master_arregion,
	       mem_master_awcache,
	       mem_master_awqos,
	       mem_master_awregion;
  wire [2 : 0] mem_master_arprot,
	       mem_master_arsize,
	       mem_master_awprot,
	       mem_master_awsize;
  wire [1 : 0] mem_master_arburst, mem_master_awburst;
  wire RDY_v_mmio_server_0_request_put,
       RDY_v_mmio_server_0_response_get,
       RDY_v_mmio_server_1_request_put,
       RDY_v_mmio_server_1_response_get,
       mem_master_arlock,
       mem_master_arvalid,
       mem_master_awlock,
       mem_master_awvalid,
       mem_master_bready,
       mem_master_rready,
       mem_master_wlast,
       mem_master_wvalid,
       mv_write_error;

  // register ifc_rg_awlen
  reg [7 : 0] ifc_rg_awlen;
  wire [7 : 0] ifc_rg_awlen$D_IN;
  wire ifc_rg_awlen$EN;

  // register ifc_rg_rd_beat
  reg [7 : 0] ifc_rg_rd_beat;
  wire [7 : 0] ifc_rg_rd_beat$D_IN;
  wire ifc_rg_rd_beat$EN;

  // register ifc_rg_rd_data_buf
  reg [63 : 0] ifc_rg_rd_data_buf;
  wire [63 : 0] ifc_rg_rd_data_buf$D_IN;
  wire ifc_rg_rd_data_buf$EN;

  // register ifc_rg_rd_rsps_pending
  reg [3 : 0] ifc_rg_rd_rsps_pending;
  wire [3 : 0] ifc_rg_rd_rsps_pending$D_IN;
  wire ifc_rg_rd_rsps_pending$EN;

  // register ifc_rg_wr_beat
  reg [7 : 0] ifc_rg_wr_beat;
  wire [7 : 0] ifc_rg_wr_beat$D_IN;
  wire ifc_rg_wr_beat$EN;

  // register ifc_rg_wr_client_id
  reg ifc_rg_wr_client_id;
  wire ifc_rg_wr_client_id$D_IN, ifc_rg_wr_client_id$EN;

  // register ifc_rg_wr_data_buf
  reg [63 : 0] ifc_rg_wr_data_buf;
  reg [63 : 0] ifc_rg_wr_data_buf$D_IN;
  wire ifc_rg_wr_data_buf$EN;

  // register ifc_rg_wr_error
  reg ifc_rg_wr_error;
  wire ifc_rg_wr_error$D_IN, ifc_rg_wr_error$EN;

  // register ifc_rg_wr_rsps_pending
  reg [3 : 0] ifc_rg_wr_rsps_pending;
  wire [3 : 0] ifc_rg_wr_rsps_pending$D_IN;
  wire ifc_rg_wr_rsps_pending$EN;

  // register ifc_rg_wr_strb_buf
  reg [7 : 0] ifc_rg_wr_strb_buf;
  reg [7 : 0] ifc_rg_wr_strb_buf$D_IN;
  wire ifc_rg_wr_strb_buf$EN;

  // ports of submodule ifc_f_rd_rsp_control
  wire [14 : 0] ifc_f_rd_rsp_control$D_IN, ifc_f_rd_rsp_control$D_OUT;
  wire ifc_f_rd_rsp_control$CLR,
       ifc_f_rd_rsp_control$DEQ,
       ifc_f_rd_rsp_control$EMPTY_N,
       ifc_f_rd_rsp_control$ENQ,
       ifc_f_rd_rsp_control$FULL_N;

  // ports of submodule ifc_master_xactor_f_rd_addr
  wire [108 : 0] ifc_master_xactor_f_rd_addr$D_IN,
		 ifc_master_xactor_f_rd_addr$D_OUT;
  wire ifc_master_xactor_f_rd_addr$CLR,
       ifc_master_xactor_f_rd_addr$DEQ,
       ifc_master_xactor_f_rd_addr$EMPTY_N,
       ifc_master_xactor_f_rd_addr$ENQ,
       ifc_master_xactor_f_rd_addr$FULL_N;

  // ports of submodule ifc_master_xactor_f_rd_data
  wire [82 : 0] ifc_master_xactor_f_rd_data$D_IN,
		ifc_master_xactor_f_rd_data$D_OUT;
  wire ifc_master_xactor_f_rd_data$CLR,
       ifc_master_xactor_f_rd_data$DEQ,
       ifc_master_xactor_f_rd_data$EMPTY_N,
       ifc_master_xactor_f_rd_data$ENQ,
       ifc_master_xactor_f_rd_data$FULL_N;

  // ports of submodule ifc_master_xactor_f_wr_addr
  wire [108 : 0] ifc_master_xactor_f_wr_addr$D_IN,
		 ifc_master_xactor_f_wr_addr$D_OUT;
  wire ifc_master_xactor_f_wr_addr$CLR,
       ifc_master_xactor_f_wr_addr$DEQ,
       ifc_master_xactor_f_wr_addr$EMPTY_N,
       ifc_master_xactor_f_wr_addr$ENQ,
       ifc_master_xactor_f_wr_addr$FULL_N;

  // ports of submodule ifc_master_xactor_f_wr_data
  wire [72 : 0] ifc_master_xactor_f_wr_data$D_IN,
		ifc_master_xactor_f_wr_data$D_OUT;
  wire ifc_master_xactor_f_wr_data$CLR,
       ifc_master_xactor_f_wr_data$DEQ,
       ifc_master_xactor_f_wr_data$EMPTY_N,
       ifc_master_xactor_f_wr_data$ENQ,
       ifc_master_xactor_f_wr_data$FULL_N;

  // ports of submodule ifc_master_xactor_f_wr_resp
  wire [17 : 0] ifc_master_xactor_f_wr_resp$D_IN,
		ifc_master_xactor_f_wr_resp$D_OUT;
  wire ifc_master_xactor_f_wr_resp$CLR,
       ifc_master_xactor_f_wr_resp$DEQ,
       ifc_master_xactor_f_wr_resp$EMPTY_N,
       ifc_master_xactor_f_wr_resp$ENQ,
       ifc_master_xactor_f_wr_resp$FULL_N;

  // ports of submodule ifc_v_f_reqs_0
  wire [130 : 0] ifc_v_f_reqs_0$D_IN, ifc_v_f_reqs_0$D_OUT;
  wire ifc_v_f_reqs_0$CLR,
       ifc_v_f_reqs_0$DEQ,
       ifc_v_f_reqs_0$EMPTY_N,
       ifc_v_f_reqs_0$ENQ,
       ifc_v_f_reqs_0$FULL_N;

  // ports of submodule ifc_v_f_reqs_1
  wire [130 : 0] ifc_v_f_reqs_1$D_IN, ifc_v_f_reqs_1$D_OUT;
  wire ifc_v_f_reqs_1$CLR,
       ifc_v_f_reqs_1$DEQ,
       ifc_v_f_reqs_1$EMPTY_N,
       ifc_v_f_reqs_1$ENQ,
       ifc_v_f_reqs_1$FULL_N;

  // ports of submodule ifc_v_f_rsps_0
  wire [64 : 0] ifc_v_f_rsps_0$D_IN, ifc_v_f_rsps_0$D_OUT;
  wire ifc_v_f_rsps_0$CLR,
       ifc_v_f_rsps_0$DEQ,
       ifc_v_f_rsps_0$EMPTY_N,
       ifc_v_f_rsps_0$ENQ,
       ifc_v_f_rsps_0$FULL_N;

  // ports of submodule ifc_v_f_rsps_1
  wire [64 : 0] ifc_v_f_rsps_1$D_IN, ifc_v_f_rsps_1$D_OUT;
  wire ifc_v_f_rsps_1$CLR,
       ifc_v_f_rsps_1$DEQ,
       ifc_v_f_rsps_1$EMPTY_N,
       ifc_v_f_rsps_1$ENQ,
       ifc_v_f_rsps_1$FULL_N;

  // rule scheduling signals
  wire CAN_FIRE_RL_ifc_rl_rd_data,
       CAN_FIRE_RL_ifc_rl_rd_req,
       CAN_FIRE_RL_ifc_rl_rd_req_1,
       CAN_FIRE_RL_ifc_rl_wr_data,
       CAN_FIRE_RL_ifc_rl_wr_req,
       CAN_FIRE_RL_ifc_rl_wr_req_1,
       CAN_FIRE_RL_ifc_rl_wr_rsp,
       CAN_FIRE_mem_master_m_arready,
       CAN_FIRE_mem_master_m_awready,
       CAN_FIRE_mem_master_m_bvalid,
       CAN_FIRE_mem_master_m_rvalid,
       CAN_FIRE_mem_master_m_wready,
       CAN_FIRE_v_mmio_server_0_request_put,
       CAN_FIRE_v_mmio_server_0_response_get,
       CAN_FIRE_v_mmio_server_1_request_put,
       CAN_FIRE_v_mmio_server_1_response_get,
       WILL_FIRE_RL_ifc_rl_rd_data,
       WILL_FIRE_RL_ifc_rl_rd_req,
       WILL_FIRE_RL_ifc_rl_rd_req_1,
       WILL_FIRE_RL_ifc_rl_wr_data,
       WILL_FIRE_RL_ifc_rl_wr_req,
       WILL_FIRE_RL_ifc_rl_wr_req_1,
       WILL_FIRE_RL_ifc_rl_wr_rsp,
       WILL_FIRE_mem_master_m_arready,
       WILL_FIRE_mem_master_m_awready,
       WILL_FIRE_mem_master_m_bvalid,
       WILL_FIRE_mem_master_m_rvalid,
       WILL_FIRE_mem_master_m_wready,
       WILL_FIRE_v_mmio_server_0_request_put,
       WILL_FIRE_v_mmio_server_0_response_get,
       WILL_FIRE_v_mmio_server_1_request_put,
       WILL_FIRE_v_mmio_server_1_response_get;

  // inputs to muxes for submodule ports
  wire [108 : 0] MUX_ifc_master_xactor_f_rd_addr$enq_1__VAL_1,
		 MUX_ifc_master_xactor_f_rd_addr$enq_1__VAL_2;
  wire [63 : 0] MUX_ifc_rg_wr_data_buf$write_1__VAL_1,
		MUX_ifc_rg_wr_data_buf$write_1__VAL_2;
  wire [14 : 0] MUX_ifc_f_rd_rsp_control$enq_1__VAL_1,
		MUX_ifc_f_rd_rsp_control$enq_1__VAL_2;
  wire [7 : 0] MUX_ifc_rg_rd_beat$write_1__VAL_1,
	       MUX_ifc_rg_wr_beat$write_1__VAL_1,
	       MUX_ifc_rg_wr_strb_buf$write_1__VAL_1,
	       MUX_ifc_rg_wr_strb_buf$write_1__VAL_2;
  wire [3 : 0] MUX_ifc_rg_rd_rsps_pending$write_1__VAL_1,
	       MUX_ifc_rg_rd_rsps_pending$write_1__VAL_2,
	       MUX_ifc_rg_wr_rsps_pending$write_1__VAL_1,
	       MUX_ifc_rg_wr_rsps_pending$write_1__VAL_2;
  wire MUX_ifc_rg_rd_beat$write_1__SEL_2,
       MUX_ifc_rg_rd_rsps_pending$write_1__SEL_1,
       MUX_ifc_rg_wr_beat$write_1__SEL_2,
       MUX_ifc_rg_wr_rsps_pending$write_1__SEL_1;

  // declarations used by system tasks
  // synopsys translate_off
  reg [31 : 0] v__h1556;
  reg [31 : 0] v__h2004;
  reg [31 : 0] v__h3783;
  reg [31 : 0] v__h4311;
  reg [31 : 0] v__h2465;
  reg [31 : 0] v__h3074;
  reg [31 : 0] v__h4642;
  reg [31 : 0] v__h4847;
  reg [31 : 0] v__h4942;
  reg [31 : 0] v__h4993;
  reg [31 : 0] v__h1550;
  reg [31 : 0] v__h1998;
  reg [31 : 0] v__h2459;
  reg [31 : 0] v__h3068;
  reg [31 : 0] v__h3777;
  reg [31 : 0] v__h4305;
  reg [31 : 0] v__h4636;
  reg [31 : 0] v__h4841;
  reg [31 : 0] v__h4936;
  reg [31 : 0] v__h4987;
  // synopsys translate_on

  // remaining internal signals
  reg [63 : 0] v__h2409;
  reg [7 : 0] strb__h3334, strb__h3887;
  reg CASE_ifc_f_rd_rsp_controlD_OUT_BIT_14_0_ifc_v_ETC__q1,
      CASE_ifc_rg_wr_client_id_0_ifc_v_f_reqs_0EMPT_ETC__q2;
  wire [63 : 0] v__h2649,
		v__h2664,
		v__h2747,
		word64___1__h2434,
		y_avValue_fst__h3407,
		y_avValue_fst__h3960;
  wire [7 : 0] x__h2999,
	       y_avValue_snd_snd_snd__h3559,
	       y_avValue_snd_snd_snd__h4110;
  wire [5 : 0] v__h2754, x__h3494, x__h4045;
  wire [2 : 0] x__h1718, x__h2140;
  wire ifc_master_xactor_f_rd_data_i_notEmpty__2_AND__ETC___d83,
       ifc_master_xactor_f_wr_data_i_notFull__66_AND__ETC___d172,
       ifc_rg_rd_beat_3_EQ_ifc_f_rd_rsp_control_first_ETC___d76,
       ifc_rg_wr_beat_24_EQ_ifc_rg_awlen_25___d167,
       ifc_rg_wr_beat_24_ULE_ifc_rg_awlen_25___d126;

  // action method v_mmio_server_0_request_put
  assign RDY_v_mmio_server_0_request_put = ifc_v_f_reqs_0$FULL_N ;
  assign CAN_FIRE_v_mmio_server_0_request_put = ifc_v_f_reqs_0$FULL_N ;
  assign WILL_FIRE_v_mmio_server_0_request_put =
	     EN_v_mmio_server_0_request_put ;

  // actionvalue method v_mmio_server_0_response_get
  assign v_mmio_server_0_response_get = ifc_v_f_rsps_0$D_OUT ;
  assign RDY_v_mmio_server_0_response_get = ifc_v_f_rsps_0$EMPTY_N ;
  assign CAN_FIRE_v_mmio_server_0_response_get = ifc_v_f_rsps_0$EMPTY_N ;
  assign WILL_FIRE_v_mmio_server_0_response_get =
	     EN_v_mmio_server_0_response_get ;

  // action method v_mmio_server_1_request_put
  assign RDY_v_mmio_server_1_request_put = ifc_v_f_reqs_1$FULL_N ;
  assign CAN_FIRE_v_mmio_server_1_request_put = ifc_v_f_reqs_1$FULL_N ;
  assign WILL_FIRE_v_mmio_server_1_request_put =
	     EN_v_mmio_server_1_request_put ;

  // actionvalue method v_mmio_server_1_response_get
  assign v_mmio_server_1_response_get = ifc_v_f_rsps_1$D_OUT ;
  assign RDY_v_mmio_server_1_response_get = ifc_v_f_rsps_1$EMPTY_N ;
  assign CAN_FIRE_v_mmio_server_1_response_get = ifc_v_f_rsps_1$EMPTY_N ;
  assign WILL_FIRE_v_mmio_server_1_response_get =
	     EN_v_mmio_server_1_response_get ;

  // value method mem_master_m_awvalid
  assign mem_master_awvalid = ifc_master_xactor_f_wr_addr$EMPTY_N ;

  // value method mem_master_m_awid
  assign mem_master_awid = ifc_master_xactor_f_wr_addr$D_OUT[108:93] ;

  // value method mem_master_m_awaddr
  assign mem_master_awaddr = ifc_master_xactor_f_wr_addr$D_OUT[92:29] ;

  // value method mem_master_m_awlen
  assign mem_master_awlen = ifc_master_xactor_f_wr_addr$D_OUT[28:21] ;

  // value method mem_master_m_awsize
  assign mem_master_awsize = ifc_master_xactor_f_wr_addr$D_OUT[20:18] ;

  // value method mem_master_m_awburst
  assign mem_master_awburst = ifc_master_xactor_f_wr_addr$D_OUT[17:16] ;

  // value method mem_master_m_awlock
  assign mem_master_awlock = ifc_master_xactor_f_wr_addr$D_OUT[15] ;

  // value method mem_master_m_awcache
  assign mem_master_awcache = ifc_master_xactor_f_wr_addr$D_OUT[14:11] ;

  // value method mem_master_m_awprot
  assign mem_master_awprot = ifc_master_xactor_f_wr_addr$D_OUT[10:8] ;

  // value method mem_master_m_awqos
  assign mem_master_awqos = ifc_master_xactor_f_wr_addr$D_OUT[7:4] ;

  // value method mem_master_m_awregion
  assign mem_master_awregion = ifc_master_xactor_f_wr_addr$D_OUT[3:0] ;

  // action method mem_master_m_awready
  assign CAN_FIRE_mem_master_m_awready = 1'd1 ;
  assign WILL_FIRE_mem_master_m_awready = 1'd1 ;

  // value method mem_master_m_wvalid
  assign mem_master_wvalid = ifc_master_xactor_f_wr_data$EMPTY_N ;

  // value method mem_master_m_wdata
  assign mem_master_wdata = ifc_master_xactor_f_wr_data$D_OUT[72:9] ;

  // value method mem_master_m_wstrb
  assign mem_master_wstrb = ifc_master_xactor_f_wr_data$D_OUT[8:1] ;

  // value method mem_master_m_wlast
  assign mem_master_wlast = ifc_master_xactor_f_wr_data$D_OUT[0] ;

  // action method mem_master_m_wready
  assign CAN_FIRE_mem_master_m_wready = 1'd1 ;
  assign WILL_FIRE_mem_master_m_wready = 1'd1 ;

  // action method mem_master_m_bvalid
  assign CAN_FIRE_mem_master_m_bvalid = 1'd1 ;
  assign WILL_FIRE_mem_master_m_bvalid = 1'd1 ;

  // value method mem_master_m_bready
  assign mem_master_bready = ifc_master_xactor_f_wr_resp$FULL_N ;

  // value method mem_master_m_arvalid
  assign mem_master_arvalid = ifc_master_xactor_f_rd_addr$EMPTY_N ;

  // value method mem_master_m_arid
  assign mem_master_arid = ifc_master_xactor_f_rd_addr$D_OUT[108:93] ;

  // value method mem_master_m_araddr
  assign mem_master_araddr = ifc_master_xactor_f_rd_addr$D_OUT[92:29] ;

  // value method mem_master_m_arlen
  assign mem_master_arlen = ifc_master_xactor_f_rd_addr$D_OUT[28:21] ;

  // value method mem_master_m_arsize
  assign mem_master_arsize = ifc_master_xactor_f_rd_addr$D_OUT[20:18] ;

  // value method mem_master_m_arburst
  assign mem_master_arburst = ifc_master_xactor_f_rd_addr$D_OUT[17:16] ;

  // value method mem_master_m_arlock
  assign mem_master_arlock = ifc_master_xactor_f_rd_addr$D_OUT[15] ;

  // value method mem_master_m_arcache
  assign mem_master_arcache = ifc_master_xactor_f_rd_addr$D_OUT[14:11] ;

  // value method mem_master_m_arprot
  assign mem_master_arprot = ifc_master_xactor_f_rd_addr$D_OUT[10:8] ;

  // value method mem_master_m_arqos
  assign mem_master_arqos = ifc_master_xactor_f_rd_addr$D_OUT[7:4] ;

  // value method mem_master_m_arregion
  assign mem_master_arregion = ifc_master_xactor_f_rd_addr$D_OUT[3:0] ;

  // action method mem_master_m_arready
  assign CAN_FIRE_mem_master_m_arready = 1'd1 ;
  assign WILL_FIRE_mem_master_m_arready = 1'd1 ;

  // action method mem_master_m_rvalid
  assign CAN_FIRE_mem_master_m_rvalid = 1'd1 ;
  assign WILL_FIRE_mem_master_m_rvalid = 1'd1 ;

  // value method mem_master_m_rready
  assign mem_master_rready = ifc_master_xactor_f_rd_data$FULL_N ;

  // value method mv_write_error
  assign mv_write_error = ifc_rg_wr_error ;

  // submodule ifc_f_rd_rsp_control
  FIFO2 #(.width(32'd15), .guarded(32'd1)) ifc_f_rd_rsp_control(.RST(RST_N),
								.CLK(CLK),
								.D_IN(ifc_f_rd_rsp_control$D_IN),
								.ENQ(ifc_f_rd_rsp_control$ENQ),
								.DEQ(ifc_f_rd_rsp_control$DEQ),
								.CLR(ifc_f_rd_rsp_control$CLR),
								.D_OUT(ifc_f_rd_rsp_control$D_OUT),
								.FULL_N(ifc_f_rd_rsp_control$FULL_N),
								.EMPTY_N(ifc_f_rd_rsp_control$EMPTY_N));

  // submodule ifc_master_xactor_f_rd_addr
  FIFO2 #(.width(32'd109),
	  .guarded(32'd1)) ifc_master_xactor_f_rd_addr(.RST(RST_N),
						       .CLK(CLK),
						       .D_IN(ifc_master_xactor_f_rd_addr$D_IN),
						       .ENQ(ifc_master_xactor_f_rd_addr$ENQ),
						       .DEQ(ifc_master_xactor_f_rd_addr$DEQ),
						       .CLR(ifc_master_xactor_f_rd_addr$CLR),
						       .D_OUT(ifc_master_xactor_f_rd_addr$D_OUT),
						       .FULL_N(ifc_master_xactor_f_rd_addr$FULL_N),
						       .EMPTY_N(ifc_master_xactor_f_rd_addr$EMPTY_N));

  // submodule ifc_master_xactor_f_rd_data
  FIFO2 #(.width(32'd83),
	  .guarded(32'd1)) ifc_master_xactor_f_rd_data(.RST(RST_N),
						       .CLK(CLK),
						       .D_IN(ifc_master_xactor_f_rd_data$D_IN),
						       .ENQ(ifc_master_xactor_f_rd_data$ENQ),
						       .DEQ(ifc_master_xactor_f_rd_data$DEQ),
						       .CLR(ifc_master_xactor_f_rd_data$CLR),
						       .D_OUT(ifc_master_xactor_f_rd_data$D_OUT),
						       .FULL_N(ifc_master_xactor_f_rd_data$FULL_N),
						       .EMPTY_N(ifc_master_xactor_f_rd_data$EMPTY_N));

  // submodule ifc_master_xactor_f_wr_addr
  FIFO2 #(.width(32'd109),
	  .guarded(32'd1)) ifc_master_xactor_f_wr_addr(.RST(RST_N),
						       .CLK(CLK),
						       .D_IN(ifc_master_xactor_f_wr_addr$D_IN),
						       .ENQ(ifc_master_xactor_f_wr_addr$ENQ),
						       .DEQ(ifc_master_xactor_f_wr_addr$DEQ),
						       .CLR(ifc_master_xactor_f_wr_addr$CLR),
						       .D_OUT(ifc_master_xactor_f_wr_addr$D_OUT),
						       .FULL_N(ifc_master_xactor_f_wr_addr$FULL_N),
						       .EMPTY_N(ifc_master_xactor_f_wr_addr$EMPTY_N));

  // submodule ifc_master_xactor_f_wr_data
  FIFO2 #(.width(32'd73),
	  .guarded(32'd1)) ifc_master_xactor_f_wr_data(.RST(RST_N),
						       .CLK(CLK),
						       .D_IN(ifc_master_xactor_f_wr_data$D_IN),
						       .ENQ(ifc_master_xactor_f_wr_data$ENQ),
						       .DEQ(ifc_master_xactor_f_wr_data$DEQ),
						       .CLR(ifc_master_xactor_f_wr_data$CLR),
						       .D_OUT(ifc_master_xactor_f_wr_data$D_OUT),
						       .FULL_N(ifc_master_xactor_f_wr_data$FULL_N),
						       .EMPTY_N(ifc_master_xactor_f_wr_data$EMPTY_N));

  // submodule ifc_master_xactor_f_wr_resp
  FIFO2 #(.width(32'd18),
	  .guarded(32'd1)) ifc_master_xactor_f_wr_resp(.RST(RST_N),
						       .CLK(CLK),
						       .D_IN(ifc_master_xactor_f_wr_resp$D_IN),
						       .ENQ(ifc_master_xactor_f_wr_resp$ENQ),
						       .DEQ(ifc_master_xactor_f_wr_resp$DEQ),
						       .CLR(ifc_master_xactor_f_wr_resp$CLR),
						       .D_OUT(ifc_master_xactor_f_wr_resp$D_OUT),
						       .FULL_N(ifc_master_xactor_f_wr_resp$FULL_N),
						       .EMPTY_N(ifc_master_xactor_f_wr_resp$EMPTY_N));

  // submodule ifc_v_f_reqs_0
  FIFO2 #(.width(32'd131), .guarded(32'd1)) ifc_v_f_reqs_0(.RST(RST_N),
							   .CLK(CLK),
							   .D_IN(ifc_v_f_reqs_0$D_IN),
							   .ENQ(ifc_v_f_reqs_0$ENQ),
							   .DEQ(ifc_v_f_reqs_0$DEQ),
							   .CLR(ifc_v_f_reqs_0$CLR),
							   .D_OUT(ifc_v_f_reqs_0$D_OUT),
							   .FULL_N(ifc_v_f_reqs_0$FULL_N),
							   .EMPTY_N(ifc_v_f_reqs_0$EMPTY_N));

  // submodule ifc_v_f_reqs_1
  FIFO2 #(.width(32'd131), .guarded(32'd1)) ifc_v_f_reqs_1(.RST(RST_N),
							   .CLK(CLK),
							   .D_IN(ifc_v_f_reqs_1$D_IN),
							   .ENQ(ifc_v_f_reqs_1$ENQ),
							   .DEQ(ifc_v_f_reqs_1$DEQ),
							   .CLR(ifc_v_f_reqs_1$CLR),
							   .D_OUT(ifc_v_f_reqs_1$D_OUT),
							   .FULL_N(ifc_v_f_reqs_1$FULL_N),
							   .EMPTY_N(ifc_v_f_reqs_1$EMPTY_N));

  // submodule ifc_v_f_rsps_0
  FIFO2 #(.width(32'd65), .guarded(32'd1)) ifc_v_f_rsps_0(.RST(RST_N),
							  .CLK(CLK),
							  .D_IN(ifc_v_f_rsps_0$D_IN),
							  .ENQ(ifc_v_f_rsps_0$ENQ),
							  .DEQ(ifc_v_f_rsps_0$DEQ),
							  .CLR(ifc_v_f_rsps_0$CLR),
							  .D_OUT(ifc_v_f_rsps_0$D_OUT),
							  .FULL_N(ifc_v_f_rsps_0$FULL_N),
							  .EMPTY_N(ifc_v_f_rsps_0$EMPTY_N));

  // submodule ifc_v_f_rsps_1
  FIFO2 #(.width(32'd65), .guarded(32'd1)) ifc_v_f_rsps_1(.RST(RST_N),
							  .CLK(CLK),
							  .D_IN(ifc_v_f_rsps_1$D_IN),
							  .ENQ(ifc_v_f_rsps_1$ENQ),
							  .DEQ(ifc_v_f_rsps_1$DEQ),
							  .CLR(ifc_v_f_rsps_1$CLR),
							  .D_OUT(ifc_v_f_rsps_1$D_OUT),
							  .FULL_N(ifc_v_f_rsps_1$FULL_N),
							  .EMPTY_N(ifc_v_f_rsps_1$EMPTY_N));

  // rule RL_ifc_rl_rd_req
  assign CAN_FIRE_RL_ifc_rl_rd_req =
	     ifc_v_f_reqs_0$EMPTY_N && ifc_master_xactor_f_rd_addr$FULL_N &&
	     ifc_f_rd_rsp_control$FULL_N &&
	     ifc_v_f_reqs_0$D_OUT[130] &&
	     ifc_rg_rd_rsps_pending != 4'd15 &&
	     ifc_rg_wr_rsps_pending == 4'd0 ;
  assign WILL_FIRE_RL_ifc_rl_rd_req = CAN_FIRE_RL_ifc_rl_rd_req ;

  // rule RL_ifc_rl_rd_req_1
  assign CAN_FIRE_RL_ifc_rl_rd_req_1 =
	     ifc_master_xactor_f_rd_addr$FULL_N &&
	     ifc_f_rd_rsp_control$FULL_N &&
	     ifc_v_f_reqs_1$EMPTY_N &&
	     ifc_v_f_reqs_1$D_OUT[130] &&
	     ifc_rg_rd_rsps_pending != 4'd15 &&
	     ifc_rg_wr_rsps_pending == 4'd0 ;
  assign WILL_FIRE_RL_ifc_rl_rd_req_1 =
	     CAN_FIRE_RL_ifc_rl_rd_req_1 && !WILL_FIRE_RL_ifc_rl_rd_req ;

  // rule RL_ifc_rl_wr_req
  assign CAN_FIRE_RL_ifc_rl_wr_req =
	     ifc_v_f_reqs_0$EMPTY_N && ifc_master_xactor_f_wr_addr$FULL_N &&
	     !ifc_v_f_reqs_0$D_OUT[130] &&
	     !ifc_rg_wr_beat_24_ULE_ifc_rg_awlen_25___d126 &&
	     ifc_rg_rd_rsps_pending == 4'd0 &&
	     ifc_rg_wr_rsps_pending != 4'd15 ;
  assign WILL_FIRE_RL_ifc_rl_wr_req =
	     CAN_FIRE_RL_ifc_rl_wr_req && !WILL_FIRE_RL_ifc_rl_rd_req_1 ;

  // rule RL_ifc_rl_wr_req_1
  assign CAN_FIRE_RL_ifc_rl_wr_req_1 =
	     ifc_v_f_reqs_1$EMPTY_N && ifc_master_xactor_f_wr_addr$FULL_N &&
	     !ifc_v_f_reqs_1$D_OUT[130] &&
	     !ifc_rg_wr_beat_24_ULE_ifc_rg_awlen_25___d126 &&
	     ifc_rg_rd_rsps_pending == 4'd0 &&
	     ifc_rg_wr_rsps_pending != 4'd15 ;
  assign WILL_FIRE_RL_ifc_rl_wr_req_1 =
	     CAN_FIRE_RL_ifc_rl_wr_req_1 && !WILL_FIRE_RL_ifc_rl_wr_req &&
	     !WILL_FIRE_RL_ifc_rl_rd_req ;

  // rule RL_ifc_rl_rd_data
  assign CAN_FIRE_RL_ifc_rl_rd_data =
	     ifc_f_rd_rsp_control$EMPTY_N &&
	     ifc_master_xactor_f_rd_data_i_notEmpty__2_AND__ETC___d83 &&
	     ifc_rg_rd_beat <= ifc_f_rd_rsp_control$D_OUT[7:0] ;
  assign WILL_FIRE_RL_ifc_rl_rd_data =
	     CAN_FIRE_RL_ifc_rl_rd_data && !WILL_FIRE_RL_ifc_rl_rd_req_1 &&
	     !WILL_FIRE_RL_ifc_rl_rd_req ;

  // rule RL_ifc_rl_wr_data
  assign CAN_FIRE_RL_ifc_rl_wr_data =
	     ifc_master_xactor_f_wr_data_i_notFull__66_AND__ETC___d172 &&
	     ifc_rg_wr_beat_24_ULE_ifc_rg_awlen_25___d126 ;
  assign WILL_FIRE_RL_ifc_rl_wr_data =
	     CAN_FIRE_RL_ifc_rl_wr_data && !WILL_FIRE_RL_ifc_rl_rd_req_1 &&
	     !WILL_FIRE_RL_ifc_rl_rd_req ;

  // rule RL_ifc_rl_wr_rsp
  assign CAN_FIRE_RL_ifc_rl_wr_rsp = ifc_master_xactor_f_wr_resp$EMPTY_N ;
  assign WILL_FIRE_RL_ifc_rl_wr_rsp =
	     ifc_master_xactor_f_wr_resp$EMPTY_N &&
	     !WILL_FIRE_RL_ifc_rl_wr_req_1 &&
	     !WILL_FIRE_RL_ifc_rl_wr_req ;

  // inputs to muxes for submodule ports
  assign MUX_ifc_rg_rd_beat$write_1__SEL_2 =
	     WILL_FIRE_RL_ifc_rl_rd_req_1 || WILL_FIRE_RL_ifc_rl_rd_req ;
  assign MUX_ifc_rg_rd_rsps_pending$write_1__SEL_1 =
	     WILL_FIRE_RL_ifc_rl_rd_data &&
	     ifc_rg_rd_beat_3_EQ_ifc_f_rd_rsp_control_first_ETC___d76 ;
  assign MUX_ifc_rg_wr_beat$write_1__SEL_2 =
	     WILL_FIRE_RL_ifc_rl_wr_req_1 || WILL_FIRE_RL_ifc_rl_wr_req ;
  assign MUX_ifc_rg_wr_rsps_pending$write_1__SEL_1 =
	     WILL_FIRE_RL_ifc_rl_wr_rsp && ifc_rg_wr_rsps_pending != 4'd0 ;
  assign MUX_ifc_f_rd_rsp_control$enq_1__VAL_1 =
	     { 1'd0, x__h1718, ifc_v_f_reqs_0$D_OUT[68:66], 8'd0 } ;
  assign MUX_ifc_f_rd_rsp_control$enq_1__VAL_2 =
	     { 1'd1, x__h2140, ifc_v_f_reqs_1$D_OUT[68:66], 8'd0 } ;
  assign MUX_ifc_master_xactor_f_rd_addr$enq_1__VAL_1 =
	     { 16'd0,
	       ifc_v_f_reqs_1$D_OUT[129:66],
	       8'd0,
	       x__h2140,
	       18'd65536 } ;
  assign MUX_ifc_master_xactor_f_rd_addr$enq_1__VAL_2 =
	     { 16'd0,
	       ifc_v_f_reqs_0$D_OUT[129:66],
	       8'd0,
	       x__h1718,
	       18'd65536 } ;
  assign MUX_ifc_rg_rd_beat$write_1__VAL_1 =
	     ifc_rg_rd_beat_3_EQ_ifc_f_rd_rsp_control_first_ETC___d76 ?
	       8'd0 :
	       x__h2999 ;
  assign MUX_ifc_rg_rd_rsps_pending$write_1__VAL_1 =
	     ifc_rg_rd_rsps_pending - 4'd1 ;
  assign MUX_ifc_rg_rd_rsps_pending$write_1__VAL_2 =
	     ifc_rg_rd_rsps_pending + 4'd1 ;
  assign MUX_ifc_rg_wr_beat$write_1__VAL_1 = ifc_rg_wr_beat + 8'd1 ;
  assign MUX_ifc_rg_wr_data_buf$write_1__VAL_1 =
	     (ifc_v_f_reqs_0$D_OUT[65:64] == 2'd3) ?
	       ifc_v_f_reqs_0$D_OUT[63:0] :
	       y_avValue_fst__h3407 ;
  assign MUX_ifc_rg_wr_data_buf$write_1__VAL_2 =
	     (ifc_v_f_reqs_1$D_OUT[65:64] == 2'd3) ?
	       ifc_v_f_reqs_1$D_OUT[63:0] :
	       y_avValue_fst__h3960 ;
  assign MUX_ifc_rg_wr_rsps_pending$write_1__VAL_1 =
	     ifc_rg_wr_rsps_pending - 4'd1 ;
  assign MUX_ifc_rg_wr_rsps_pending$write_1__VAL_2 =
	     ifc_rg_wr_rsps_pending + 4'd1 ;
  assign MUX_ifc_rg_wr_strb_buf$write_1__VAL_1 =
	     (ifc_v_f_reqs_0$D_OUT[65:64] == 2'd3) ?
	       strb__h3334 :
	       y_avValue_snd_snd_snd__h3559 ;
  assign MUX_ifc_rg_wr_strb_buf$write_1__VAL_2 =
	     (ifc_v_f_reqs_1$D_OUT[65:64] == 2'd3) ?
	       strb__h3887 :
	       y_avValue_snd_snd_snd__h4110 ;

  // register ifc_rg_awlen
  assign ifc_rg_awlen$D_IN = 8'd0 ;
  assign ifc_rg_awlen$EN = MUX_ifc_rg_wr_beat$write_1__SEL_2 ;

  // register ifc_rg_rd_beat
  assign ifc_rg_rd_beat$D_IN =
	     WILL_FIRE_RL_ifc_rl_rd_data ?
	       MUX_ifc_rg_rd_beat$write_1__VAL_1 :
	       8'd0 ;
  assign ifc_rg_rd_beat$EN =
	     WILL_FIRE_RL_ifc_rl_rd_data || WILL_FIRE_RL_ifc_rl_rd_req_1 ||
	     WILL_FIRE_RL_ifc_rl_rd_req ;

  // register ifc_rg_rd_data_buf
  assign ifc_rg_rd_data_buf$D_IN = v__h2409 ;
  assign ifc_rg_rd_data_buf$EN = WILL_FIRE_RL_ifc_rl_rd_data ;

  // register ifc_rg_rd_rsps_pending
  assign ifc_rg_rd_rsps_pending$D_IN =
	     MUX_ifc_rg_rd_rsps_pending$write_1__SEL_1 ?
	       MUX_ifc_rg_rd_rsps_pending$write_1__VAL_1 :
	       MUX_ifc_rg_rd_rsps_pending$write_1__VAL_2 ;
  assign ifc_rg_rd_rsps_pending$EN =
	     WILL_FIRE_RL_ifc_rl_rd_data &&
	     ifc_rg_rd_beat_3_EQ_ifc_f_rd_rsp_control_first_ETC___d76 ||
	     WILL_FIRE_RL_ifc_rl_rd_req_1 ||
	     WILL_FIRE_RL_ifc_rl_rd_req ;

  // register ifc_rg_wr_beat
  assign ifc_rg_wr_beat$D_IN =
	     WILL_FIRE_RL_ifc_rl_wr_data ?
	       MUX_ifc_rg_wr_beat$write_1__VAL_1 :
	       8'd0 ;
  assign ifc_rg_wr_beat$EN =
	     WILL_FIRE_RL_ifc_rl_wr_data || WILL_FIRE_RL_ifc_rl_wr_req_1 ||
	     WILL_FIRE_RL_ifc_rl_wr_req ;

  // register ifc_rg_wr_client_id
  assign ifc_rg_wr_client_id$D_IN = !WILL_FIRE_RL_ifc_rl_wr_req ;
  assign ifc_rg_wr_client_id$EN =
	     WILL_FIRE_RL_ifc_rl_wr_req || WILL_FIRE_RL_ifc_rl_wr_req_1 ;

  // register ifc_rg_wr_data_buf
  always@(WILL_FIRE_RL_ifc_rl_wr_req or
	  MUX_ifc_rg_wr_data_buf$write_1__VAL_1 or
	  WILL_FIRE_RL_ifc_rl_wr_req_1 or
	  MUX_ifc_rg_wr_data_buf$write_1__VAL_2 or
	  WILL_FIRE_RL_ifc_rl_wr_data)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_ifc_rl_wr_req:
	  ifc_rg_wr_data_buf$D_IN = MUX_ifc_rg_wr_data_buf$write_1__VAL_1;
      WILL_FIRE_RL_ifc_rl_wr_req_1:
	  ifc_rg_wr_data_buf$D_IN = MUX_ifc_rg_wr_data_buf$write_1__VAL_2;
      WILL_FIRE_RL_ifc_rl_wr_data: ifc_rg_wr_data_buf$D_IN = 64'd0;
      default: ifc_rg_wr_data_buf$D_IN =
		   64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign ifc_rg_wr_data_buf$EN =
	     WILL_FIRE_RL_ifc_rl_wr_req || WILL_FIRE_RL_ifc_rl_wr_req_1 ||
	     WILL_FIRE_RL_ifc_rl_wr_data ;

  // register ifc_rg_wr_error
  assign ifc_rg_wr_error$D_IN = 1'd1 ;
  assign ifc_rg_wr_error$EN =
	     WILL_FIRE_RL_ifc_rl_wr_rsp &&
	     (ifc_rg_wr_rsps_pending == 4'd0 ||
	      ifc_master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0) ;

  // register ifc_rg_wr_rsps_pending
  assign ifc_rg_wr_rsps_pending$D_IN =
	     MUX_ifc_rg_wr_rsps_pending$write_1__SEL_1 ?
	       MUX_ifc_rg_wr_rsps_pending$write_1__VAL_1 :
	       MUX_ifc_rg_wr_rsps_pending$write_1__VAL_2 ;
  assign ifc_rg_wr_rsps_pending$EN =
	     WILL_FIRE_RL_ifc_rl_wr_rsp && ifc_rg_wr_rsps_pending != 4'd0 ||
	     WILL_FIRE_RL_ifc_rl_wr_req_1 ||
	     WILL_FIRE_RL_ifc_rl_wr_req ;

  // register ifc_rg_wr_strb_buf
  always@(WILL_FIRE_RL_ifc_rl_wr_req or
	  MUX_ifc_rg_wr_strb_buf$write_1__VAL_1 or
	  WILL_FIRE_RL_ifc_rl_wr_req_1 or
	  MUX_ifc_rg_wr_strb_buf$write_1__VAL_2 or
	  WILL_FIRE_RL_ifc_rl_wr_data)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_ifc_rl_wr_req:
	  ifc_rg_wr_strb_buf$D_IN = MUX_ifc_rg_wr_strb_buf$write_1__VAL_1;
      WILL_FIRE_RL_ifc_rl_wr_req_1:
	  ifc_rg_wr_strb_buf$D_IN = MUX_ifc_rg_wr_strb_buf$write_1__VAL_2;
      WILL_FIRE_RL_ifc_rl_wr_data: ifc_rg_wr_strb_buf$D_IN = 8'd0;
      default: ifc_rg_wr_strb_buf$D_IN = 8'b10101010 /* unspecified value */ ;
    endcase
  end
  assign ifc_rg_wr_strb_buf$EN =
	     WILL_FIRE_RL_ifc_rl_wr_req || WILL_FIRE_RL_ifc_rl_wr_req_1 ||
	     WILL_FIRE_RL_ifc_rl_wr_data ;

  // submodule ifc_f_rd_rsp_control
  assign ifc_f_rd_rsp_control$D_IN =
	     WILL_FIRE_RL_ifc_rl_rd_req ?
	       MUX_ifc_f_rd_rsp_control$enq_1__VAL_1 :
	       MUX_ifc_f_rd_rsp_control$enq_1__VAL_2 ;
  assign ifc_f_rd_rsp_control$ENQ =
	     WILL_FIRE_RL_ifc_rl_rd_req || WILL_FIRE_RL_ifc_rl_rd_req_1 ;
  assign ifc_f_rd_rsp_control$DEQ =
	     MUX_ifc_rg_rd_rsps_pending$write_1__SEL_1 ;
  assign ifc_f_rd_rsp_control$CLR = 1'b0 ;

  // submodule ifc_master_xactor_f_rd_addr
  assign ifc_master_xactor_f_rd_addr$D_IN =
	     WILL_FIRE_RL_ifc_rl_rd_req_1 ?
	       MUX_ifc_master_xactor_f_rd_addr$enq_1__VAL_1 :
	       MUX_ifc_master_xactor_f_rd_addr$enq_1__VAL_2 ;
  assign ifc_master_xactor_f_rd_addr$ENQ = MUX_ifc_rg_rd_beat$write_1__SEL_2 ;
  assign ifc_master_xactor_f_rd_addr$DEQ =
	     ifc_master_xactor_f_rd_addr$EMPTY_N && mem_master_arready ;
  assign ifc_master_xactor_f_rd_addr$CLR = 1'b0 ;

  // submodule ifc_master_xactor_f_rd_data
  assign ifc_master_xactor_f_rd_data$D_IN =
	     { mem_master_rid,
	       mem_master_rdata,
	       mem_master_rresp,
	       mem_master_rlast } ;
  assign ifc_master_xactor_f_rd_data$ENQ =
	     mem_master_rvalid && ifc_master_xactor_f_rd_data$FULL_N ;
  assign ifc_master_xactor_f_rd_data$DEQ = WILL_FIRE_RL_ifc_rl_rd_data ;
  assign ifc_master_xactor_f_rd_data$CLR = 1'b0 ;

  // submodule ifc_master_xactor_f_wr_addr
  assign ifc_master_xactor_f_wr_addr$D_IN =
	     WILL_FIRE_RL_ifc_rl_wr_req_1 ?
	       MUX_ifc_master_xactor_f_rd_addr$enq_1__VAL_1 :
	       MUX_ifc_master_xactor_f_rd_addr$enq_1__VAL_2 ;
  assign ifc_master_xactor_f_wr_addr$ENQ = MUX_ifc_rg_wr_beat$write_1__SEL_2 ;
  assign ifc_master_xactor_f_wr_addr$DEQ =
	     ifc_master_xactor_f_wr_addr$EMPTY_N && mem_master_awready ;
  assign ifc_master_xactor_f_wr_addr$CLR = 1'b0 ;

  // submodule ifc_master_xactor_f_wr_data
  assign ifc_master_xactor_f_wr_data$D_IN =
	     { ifc_rg_wr_data_buf,
	       ifc_rg_wr_strb_buf,
	       ifc_rg_wr_beat_24_EQ_ifc_rg_awlen_25___d167 } ;
  assign ifc_master_xactor_f_wr_data$ENQ = WILL_FIRE_RL_ifc_rl_wr_data ;
  assign ifc_master_xactor_f_wr_data$DEQ =
	     ifc_master_xactor_f_wr_data$EMPTY_N && mem_master_wready ;
  assign ifc_master_xactor_f_wr_data$CLR = 1'b0 ;

  // submodule ifc_master_xactor_f_wr_resp
  assign ifc_master_xactor_f_wr_resp$D_IN =
	     { mem_master_bid, mem_master_bresp } ;
  assign ifc_master_xactor_f_wr_resp$ENQ =
	     mem_master_bvalid && ifc_master_xactor_f_wr_resp$FULL_N ;
  assign ifc_master_xactor_f_wr_resp$DEQ = WILL_FIRE_RL_ifc_rl_wr_rsp ;
  assign ifc_master_xactor_f_wr_resp$CLR = 1'b0 ;

  // submodule ifc_v_f_reqs_0
  assign ifc_v_f_reqs_0$D_IN = v_mmio_server_0_request_put ;
  assign ifc_v_f_reqs_0$ENQ = EN_v_mmio_server_0_request_put ;
  assign ifc_v_f_reqs_0$DEQ =
	     WILL_FIRE_RL_ifc_rl_wr_data && ifc_rg_wr_client_id == 1'd0 &&
	     ifc_rg_wr_beat_24_EQ_ifc_rg_awlen_25___d167 ||
	     WILL_FIRE_RL_ifc_rl_rd_req ;
  assign ifc_v_f_reqs_0$CLR = 1'b0 ;

  // submodule ifc_v_f_reqs_1
  assign ifc_v_f_reqs_1$D_IN = v_mmio_server_1_request_put ;
  assign ifc_v_f_reqs_1$ENQ = EN_v_mmio_server_1_request_put ;
  assign ifc_v_f_reqs_1$DEQ =
	     WILL_FIRE_RL_ifc_rl_wr_data && ifc_rg_wr_client_id == 1'd1 &&
	     ifc_rg_wr_beat_24_EQ_ifc_rg_awlen_25___d167 ||
	     WILL_FIRE_RL_ifc_rl_rd_req_1 ;
  assign ifc_v_f_reqs_1$CLR = 1'b0 ;

  // submodule ifc_v_f_rsps_0
  assign ifc_v_f_rsps_0$D_IN =
	     { ifc_master_xactor_f_rd_data$D_OUT[2:1] == 2'b0, v__h2664 } ;
  assign ifc_v_f_rsps_0$ENQ =
	     WILL_FIRE_RL_ifc_rl_rd_data &&
	     ifc_f_rd_rsp_control$D_OUT[14] == 1'd0 &&
	     ifc_rg_rd_beat_3_EQ_ifc_f_rd_rsp_control_first_ETC___d76 ;
  assign ifc_v_f_rsps_0$DEQ = EN_v_mmio_server_0_response_get ;
  assign ifc_v_f_rsps_0$CLR = 1'b0 ;

  // submodule ifc_v_f_rsps_1
  assign ifc_v_f_rsps_1$D_IN =
	     { ifc_master_xactor_f_rd_data$D_OUT[2:1] == 2'b0, v__h2664 } ;
  assign ifc_v_f_rsps_1$ENQ =
	     WILL_FIRE_RL_ifc_rl_rd_data &&
	     ifc_f_rd_rsp_control$D_OUT[14] == 1'd1 &&
	     ifc_rg_rd_beat_3_EQ_ifc_f_rd_rsp_control_first_ETC___d76 ;
  assign ifc_v_f_rsps_1$DEQ = EN_v_mmio_server_1_response_get ;
  assign ifc_v_f_rsps_1$CLR = 1'b0 ;

  // remaining internal signals
  assign ifc_master_xactor_f_rd_data_i_notEmpty__2_AND__ETC___d83 =
	     ifc_master_xactor_f_rd_data$EMPTY_N &&
	     (!ifc_rg_rd_beat_3_EQ_ifc_f_rd_rsp_control_first_ETC___d76 ||
	      CASE_ifc_f_rd_rsp_controlD_OUT_BIT_14_0_ifc_v_ETC__q1) ;
  assign ifc_master_xactor_f_wr_data_i_notFull__66_AND__ETC___d172 =
	     ifc_master_xactor_f_wr_data$FULL_N &&
	     (!ifc_rg_wr_beat_24_EQ_ifc_rg_awlen_25___d167 ||
	      CASE_ifc_rg_wr_client_id_0_ifc_v_f_reqs_0EMPT_ETC__q2) ;
  assign ifc_rg_rd_beat_3_EQ_ifc_f_rd_rsp_control_first_ETC___d76 =
	     ifc_rg_rd_beat == ifc_f_rd_rsp_control$D_OUT[7:0] ;
  assign ifc_rg_wr_beat_24_EQ_ifc_rg_awlen_25___d167 =
	     ifc_rg_wr_beat == ifc_rg_awlen ;
  assign ifc_rg_wr_beat_24_ULE_ifc_rg_awlen_25___d126 =
	     ifc_rg_wr_beat <= ifc_rg_awlen ;
  assign v__h2649 =
	     ifc_rg_rd_beat_3_EQ_ifc_f_rd_rsp_control_first_ETC___d76 ?
	       v__h2664 :
	       v__h2409 ;
  assign v__h2664 =
	     (ifc_f_rd_rsp_control$D_OUT[13:11] == 3'b011) ?
	       v__h2409 :
	       v__h2747 ;
  assign v__h2747 = v__h2409 >> v__h2754 ;
  assign v__h2754 = { ifc_f_rd_rsp_control$D_OUT[10:8], 3'b0 } ;
  assign word64___1__h2434 =
	     { ifc_master_xactor_f_rd_data$D_OUT[34:3],
	       ifc_rg_rd_data_buf[31:0] } ;
  assign x__h1718 = { 1'b0, ifc_v_f_reqs_0$D_OUT[65:64] } ;
  assign x__h2140 = { 1'b0, ifc_v_f_reqs_1$D_OUT[65:64] } ;
  assign x__h2999 = ifc_rg_rd_beat + 8'd1 ;
  assign x__h3494 = { ifc_v_f_reqs_0$D_OUT[68:66], 3'b0 } ;
  assign x__h4045 = { ifc_v_f_reqs_1$D_OUT[68:66], 3'b0 } ;
  assign y_avValue_fst__h3407 = ifc_v_f_reqs_0$D_OUT[63:0] << x__h3494 ;
  assign y_avValue_fst__h3960 = ifc_v_f_reqs_1$D_OUT[63:0] << x__h4045 ;
  assign y_avValue_snd_snd_snd__h3559 =
	     strb__h3334 << ifc_v_f_reqs_0$D_OUT[68:66] ;
  assign y_avValue_snd_snd_snd__h4110 =
	     strb__h3887 << ifc_v_f_reqs_1$D_OUT[68:66] ;
  always@(ifc_v_f_reqs_0$D_OUT)
  begin
    case (ifc_v_f_reqs_0$D_OUT[65:64])
      2'd0: strb__h3334 = 8'h01;
      2'd1: strb__h3334 = 8'h03;
      2'd2: strb__h3334 = 8'h0F;
      2'd3: strb__h3334 = 8'hFF;
    endcase
  end
  always@(ifc_v_f_reqs_1$D_OUT)
  begin
    case (ifc_v_f_reqs_1$D_OUT[65:64])
      2'd0: strb__h3887 = 8'h01;
      2'd1: strb__h3887 = 8'h03;
      2'd2: strb__h3887 = 8'h0F;
      2'd3: strb__h3887 = 8'hFF;
    endcase
  end
  always@(ifc_rg_rd_beat or
	  ifc_rg_rd_data_buf or
	  ifc_master_xactor_f_rd_data$D_OUT or word64___1__h2434)
  begin
    case (ifc_rg_rd_beat)
      8'd0: v__h2409 = ifc_master_xactor_f_rd_data$D_OUT[66:3];
      8'd1: v__h2409 = word64___1__h2434;
      default: v__h2409 = ifc_rg_rd_data_buf;
    endcase
  end
  always@(ifc_f_rd_rsp_control$D_OUT or
	  ifc_v_f_rsps_0$FULL_N or ifc_v_f_rsps_1$FULL_N)
  begin
    case (ifc_f_rd_rsp_control$D_OUT[14])
      1'd0:
	  CASE_ifc_f_rd_rsp_controlD_OUT_BIT_14_0_ifc_v_ETC__q1 =
	      ifc_v_f_rsps_0$FULL_N;
      1'd1:
	  CASE_ifc_f_rd_rsp_controlD_OUT_BIT_14_0_ifc_v_ETC__q1 =
	      ifc_v_f_rsps_1$FULL_N;
    endcase
  end
  always@(ifc_rg_wr_client_id or
	  ifc_v_f_reqs_0$EMPTY_N or ifc_v_f_reqs_1$EMPTY_N)
  begin
    case (ifc_rg_wr_client_id)
      1'd0:
	  CASE_ifc_rg_wr_client_id_0_ifc_v_f_reqs_0EMPT_ETC__q2 =
	      ifc_v_f_reqs_0$EMPTY_N;
      1'd1:
	  CASE_ifc_rg_wr_client_id_0_ifc_v_f_reqs_0EMPT_ETC__q2 =
	      ifc_v_f_reqs_1$EMPTY_N;
    endcase
  end

  // handling of inlined registers

  always@(posedge CLK)
  begin
    if (RST_N == `BSV_RESET_VALUE)
      begin
        ifc_rg_awlen <= `BSV_ASSIGNMENT_DELAY 8'd0;
	ifc_rg_rd_beat <= `BSV_ASSIGNMENT_DELAY 8'd0;
	ifc_rg_rd_rsps_pending <= `BSV_ASSIGNMENT_DELAY 4'd0;
	ifc_rg_wr_beat <= `BSV_ASSIGNMENT_DELAY 8'd1;
	ifc_rg_wr_error <= `BSV_ASSIGNMENT_DELAY 1'd0;
	ifc_rg_wr_rsps_pending <= `BSV_ASSIGNMENT_DELAY 4'd0;
      end
    else
      begin
        if (ifc_rg_awlen$EN)
	  ifc_rg_awlen <= `BSV_ASSIGNMENT_DELAY ifc_rg_awlen$D_IN;
	if (ifc_rg_rd_beat$EN)
	  ifc_rg_rd_beat <= `BSV_ASSIGNMENT_DELAY ifc_rg_rd_beat$D_IN;
	if (ifc_rg_rd_rsps_pending$EN)
	  ifc_rg_rd_rsps_pending <= `BSV_ASSIGNMENT_DELAY
	      ifc_rg_rd_rsps_pending$D_IN;
	if (ifc_rg_wr_beat$EN)
	  ifc_rg_wr_beat <= `BSV_ASSIGNMENT_DELAY ifc_rg_wr_beat$D_IN;
	if (ifc_rg_wr_error$EN)
	  ifc_rg_wr_error <= `BSV_ASSIGNMENT_DELAY ifc_rg_wr_error$D_IN;
	if (ifc_rg_wr_rsps_pending$EN)
	  ifc_rg_wr_rsps_pending <= `BSV_ASSIGNMENT_DELAY
	      ifc_rg_wr_rsps_pending$D_IN;
      end
    if (ifc_rg_rd_data_buf$EN)
      ifc_rg_rd_data_buf <= `BSV_ASSIGNMENT_DELAY ifc_rg_rd_data_buf$D_IN;
    if (ifc_rg_wr_client_id$EN)
      ifc_rg_wr_client_id <= `BSV_ASSIGNMENT_DELAY ifc_rg_wr_client_id$D_IN;
    if (ifc_rg_wr_data_buf$EN)
      ifc_rg_wr_data_buf <= `BSV_ASSIGNMENT_DELAY ifc_rg_wr_data_buf$D_IN;
    if (ifc_rg_wr_strb_buf$EN)
      ifc_rg_wr_strb_buf <= `BSV_ASSIGNMENT_DELAY ifc_rg_wr_strb_buf$D_IN;
  end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    ifc_rg_awlen = 8'hAA;
    ifc_rg_rd_beat = 8'hAA;
    ifc_rg_rd_data_buf = 64'hAAAAAAAAAAAAAAAA;
    ifc_rg_rd_rsps_pending = 4'hA;
    ifc_rg_wr_beat = 8'hAA;
    ifc_rg_wr_client_id = 1'h0;
    ifc_rg_wr_data_buf = 64'hAAAAAAAAAAAAAAAA;
    ifc_rg_wr_error = 1'h0;
    ifc_rg_wr_rsps_pending = 4'hA;
    ifc_rg_wr_strb_buf = 8'hAA;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on

  // handling of system tasks

  // synopsys translate_off
  always@(negedge CLK)
  begin
    #0;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_rd_req && verbosity != 3'd0)
	begin
	  v__h1556 = $stime;
	  #0;
	end
    v__h1550 = v__h1556 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_rd_req && verbosity != 3'd0)
	$display("%0d: %m.rl_rd_req", v__h1550);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_rd_req && verbosity != 3'd0)
	$write("    AXI4_Rd_Addr {araddr %0h arlen %d ",
	       ifc_v_f_reqs_0$D_OUT[129:66],
	       8'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_rd_req && verbosity != 3'd0 &&
	  ifc_v_f_reqs_0$D_OUT[65:64] == 2'd0)
	$write("sz1");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_rd_req && verbosity != 3'd0 &&
	  ifc_v_f_reqs_0$D_OUT[65:64] == 2'd1)
	$write("sz2");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_rd_req && verbosity != 3'd0 &&
	  ifc_v_f_reqs_0$D_OUT[65:64] == 2'd2)
	$write("sz4");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_rd_req && verbosity != 3'd0 &&
	  ifc_v_f_reqs_0$D_OUT[65:64] != 2'd0 &&
	  ifc_v_f_reqs_0$D_OUT[65:64] != 2'd1 &&
	  ifc_v_f_reqs_0$D_OUT[65:64] != 2'd2)
	$write("sz8");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_rd_req && verbosity != 3'd0) $write("}", "\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_rd_req_1 && verbosity != 3'd0)
	begin
	  v__h2004 = $stime;
	  #0;
	end
    v__h1998 = v__h2004 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_rd_req_1 && verbosity != 3'd0)
	$display("%0d: %m.rl_rd_req", v__h1998);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_rd_req_1 && verbosity != 3'd0)
	$write("    AXI4_Rd_Addr {araddr %0h arlen %d ",
	       ifc_v_f_reqs_1$D_OUT[129:66],
	       8'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_rd_req_1 && verbosity != 3'd0 &&
	  ifc_v_f_reqs_1$D_OUT[65:64] == 2'd0)
	$write("sz1");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_rd_req_1 && verbosity != 3'd0 &&
	  ifc_v_f_reqs_1$D_OUT[65:64] == 2'd1)
	$write("sz2");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_rd_req_1 && verbosity != 3'd0 &&
	  ifc_v_f_reqs_1$D_OUT[65:64] == 2'd2)
	$write("sz4");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_rd_req_1 && verbosity != 3'd0 &&
	  ifc_v_f_reqs_1$D_OUT[65:64] != 2'd0 &&
	  ifc_v_f_reqs_1$D_OUT[65:64] != 2'd1 &&
	  ifc_v_f_reqs_1$D_OUT[65:64] != 2'd2)
	$write("sz8");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_rd_req_1 && verbosity != 3'd0)
	$write("}", "\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_req && verbosity != 3'd0)
	begin
	  v__h3783 = $stime;
	  #0;
	end
    v__h3777 = v__h3783 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_req && verbosity != 3'd0)
	$display("%0d: %m.rl_wr_req", v__h3777);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_req && verbosity != 3'd0)
	$write("    AXI4_Wr_Addr{awaddr %0h awlen %0d ",
	       ifc_v_f_reqs_0$D_OUT[129:66],
	       8'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_req && verbosity != 3'd0 &&
	  ifc_v_f_reqs_0$D_OUT[65:64] == 2'd0)
	$write("sz1");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_req && verbosity != 3'd0 &&
	  ifc_v_f_reqs_0$D_OUT[65:64] == 2'd1)
	$write("sz2");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_req && verbosity != 3'd0 &&
	  ifc_v_f_reqs_0$D_OUT[65:64] == 2'd2)
	$write("sz4");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_req && verbosity != 3'd0 &&
	  ifc_v_f_reqs_0$D_OUT[65:64] != 2'd0 &&
	  ifc_v_f_reqs_0$D_OUT[65:64] != 2'd1 &&
	  ifc_v_f_reqs_0$D_OUT[65:64] != 2'd2)
	$write("sz8");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_req && verbosity != 3'd0)
	$write(" incr}", "\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_req_1 && verbosity != 3'd0)
	begin
	  v__h4311 = $stime;
	  #0;
	end
    v__h4305 = v__h4311 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_req_1 && verbosity != 3'd0)
	$display("%0d: %m.rl_wr_req", v__h4305);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_req_1 && verbosity != 3'd0)
	$write("    AXI4_Wr_Addr{awaddr %0h awlen %0d ",
	       ifc_v_f_reqs_1$D_OUT[129:66],
	       8'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_req_1 && verbosity != 3'd0 &&
	  ifc_v_f_reqs_1$D_OUT[65:64] == 2'd0)
	$write("sz1");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_req_1 && verbosity != 3'd0 &&
	  ifc_v_f_reqs_1$D_OUT[65:64] == 2'd1)
	$write("sz2");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_req_1 && verbosity != 3'd0 &&
	  ifc_v_f_reqs_1$D_OUT[65:64] == 2'd2)
	$write("sz4");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_req_1 && verbosity != 3'd0 &&
	  ifc_v_f_reqs_1$D_OUT[65:64] != 2'd0 &&
	  ifc_v_f_reqs_1$D_OUT[65:64] != 2'd1 &&
	  ifc_v_f_reqs_1$D_OUT[65:64] != 2'd2)
	$write("sz8");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_req_1 && verbosity != 3'd0)
	$write(" incr}", "\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_rd_data && ifc_rg_rd_beat != 8'd0 &&
	  ifc_rg_rd_beat != 8'd1)
	begin
	  v__h2465 = $stime;
	  #0;
	end
    v__h2459 = v__h2465 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_rd_data && ifc_rg_rd_beat != 8'd0 &&
	  ifc_rg_rd_beat != 8'd1)
	$display("%0d: INTERNAL ERROR: %m.rl_rd_data", v__h2459);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_rd_data && ifc_rg_rd_beat != 8'd0 &&
	  ifc_rg_rd_beat != 8'd1)
	$display("    Unexpected beat number %0d (can only be 0 or 1)",
		 ifc_rg_rd_beat);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_rd_data && ifc_rg_rd_beat != 8'd0 &&
	  ifc_rg_rd_beat != 8'd1)
	$finish(32'd1);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_rd_data && verbosity != 3'd0)
	begin
	  v__h3074 = $stime;
	  #0;
	end
    v__h3068 = v__h3074 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_rd_data && verbosity != 3'd0)
	$display("%0d: %m.rl_rd_data: ", v__h3068);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_rd_data && verbosity != 3'd0)
	$display("    [%0d] beat %0d data %0h",
		 ifc_f_rd_rsp_control$D_OUT[14],
		 ifc_rg_rd_beat,
		 v__h2649);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_data && verbosity != 3'd0)
	begin
	  v__h4642 = $stime;
	  #0;
	end
    v__h4636 = v__h4642 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_data && verbosity != 3'd0)
	$display("%0d: %m.rl_wr_data", v__h4636);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_data && verbosity != 3'd0)
	$display("    beat %0d/%0d", ifc_rg_wr_beat, ifc_rg_awlen);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_data && verbosity != 3'd0) $write("    ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_data && verbosity != 3'd0)
	$write("AXI4_Wr_Data { ", "wdata: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_data && verbosity != 3'd0)
	$write("'h%h", ifc_rg_wr_data_buf);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_data && verbosity != 3'd0)
	$write(", ", "wstrb: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_data && verbosity != 3'd0)
	$write("'h%h", ifc_rg_wr_strb_buf);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_data && verbosity != 3'd0)
	$write(", ", "wlast: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_data && verbosity != 3'd0 &&
	  ifc_rg_wr_beat_24_EQ_ifc_rg_awlen_25___d167)
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_data && verbosity != 3'd0 &&
	  !ifc_rg_wr_beat_24_EQ_ifc_rg_awlen_25___d167)
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_data && verbosity != 3'd0)
	$write(", ", "wuser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_data && verbosity != 3'd0)
	$write("'h%h", 1'h0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_data && verbosity != 3'd0) $write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_rsp && ifc_rg_wr_rsps_pending == 4'd0)
	begin
	  v__h4847 = $stime;
	  #0;
	end
    v__h4841 = v__h4847 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_rsp && ifc_rg_wr_rsps_pending == 4'd0)
	$display("%0d: %m.rl_wr_rsp: ERROR write-response when not expecting any",
		 v__h4841);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_rsp && ifc_rg_wr_rsps_pending == 4'd0)
	$write("    ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_rsp && ifc_rg_wr_rsps_pending == 4'd0)
	$write("AXI4_Wr_Resp { ", "bid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_rsp && ifc_rg_wr_rsps_pending == 4'd0)
	$write("'h%h", ifc_master_xactor_f_wr_resp$D_OUT[17:2]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_rsp && ifc_rg_wr_rsps_pending == 4'd0)
	$write(", ", "bresp: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_rsp && ifc_rg_wr_rsps_pending == 4'd0)
	$write("'h%h", ifc_master_xactor_f_wr_resp$D_OUT[1:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_rsp && ifc_rg_wr_rsps_pending == 4'd0)
	$write(", ", "buser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_rsp && ifc_rg_wr_rsps_pending == 4'd0)
	$write("'h%h", 1'd0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_rsp && ifc_rg_wr_rsps_pending == 4'd0)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_rsp && ifc_rg_wr_rsps_pending != 4'd0 &&
	  ifc_master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
	  verbosity != 3'd0)
	begin
	  v__h4942 = $stime;
	  #0;
	end
    v__h4936 = v__h4942 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_rsp && ifc_rg_wr_rsps_pending != 4'd0 &&
	  ifc_master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
	  verbosity != 3'd0)
	$write("%0d: %m.rl_wr_rsp: pending=%0d, ",
	       v__h4936,
	       ifc_rg_wr_rsps_pending);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_rsp && ifc_rg_wr_rsps_pending != 4'd0 &&
	  ifc_master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
	  verbosity != 3'd0)
	$write("AXI4_Wr_Resp { ", "bid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_rsp && ifc_rg_wr_rsps_pending != 4'd0 &&
	  ifc_master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
	  verbosity != 3'd0)
	$write("'h%h", ifc_master_xactor_f_wr_resp$D_OUT[17:2]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_rsp && ifc_rg_wr_rsps_pending != 4'd0 &&
	  ifc_master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
	  verbosity != 3'd0)
	$write(", ", "bresp: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_rsp && ifc_rg_wr_rsps_pending != 4'd0 &&
	  ifc_master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
	  verbosity != 3'd0)
	$write("'h%h", ifc_master_xactor_f_wr_resp$D_OUT[1:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_rsp && ifc_rg_wr_rsps_pending != 4'd0 &&
	  ifc_master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
	  verbosity != 3'd0)
	$write(", ", "buser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_rsp && ifc_rg_wr_rsps_pending != 4'd0 &&
	  ifc_master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
	  verbosity != 3'd0)
	$write("'h%h", 1'd0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_rsp && ifc_rg_wr_rsps_pending != 4'd0 &&
	  ifc_master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
	  verbosity != 3'd0)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_rsp && ifc_rg_wr_rsps_pending != 4'd0 &&
	  ifc_master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0 &&
	  verbosity != 3'd0)
	begin
	  v__h4993 = $stime;
	  #0;
	end
    v__h4987 = v__h4993 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_rsp && ifc_rg_wr_rsps_pending != 4'd0 &&
	  ifc_master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0 &&
	  verbosity != 3'd0)
	$display("%0d: %m.rl_wr_rsp: ERROR", v__h4987);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_rsp && ifc_rg_wr_rsps_pending != 4'd0 &&
	  ifc_master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0 &&
	  verbosity != 3'd0)
	$write("    ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_rsp && ifc_rg_wr_rsps_pending != 4'd0 &&
	  ifc_master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0 &&
	  verbosity != 3'd0)
	$write("AXI4_Wr_Resp { ", "bid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_rsp && ifc_rg_wr_rsps_pending != 4'd0 &&
	  ifc_master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0 &&
	  verbosity != 3'd0)
	$write("'h%h", ifc_master_xactor_f_wr_resp$D_OUT[17:2]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_rsp && ifc_rg_wr_rsps_pending != 4'd0 &&
	  ifc_master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0 &&
	  verbosity != 3'd0)
	$write(", ", "bresp: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_rsp && ifc_rg_wr_rsps_pending != 4'd0 &&
	  ifc_master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0 &&
	  verbosity != 3'd0)
	$write("'h%h", ifc_master_xactor_f_wr_resp$D_OUT[1:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_rsp && ifc_rg_wr_rsps_pending != 4'd0 &&
	  ifc_master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0 &&
	  verbosity != 3'd0)
	$write(", ", "buser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_rsp && ifc_rg_wr_rsps_pending != 4'd0 &&
	  ifc_master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0 &&
	  verbosity != 3'd0)
	$write("'h%h", 1'd0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_ifc_rl_wr_rsp && ifc_rg_wr_rsps_pending != 4'd0 &&
	  ifc_master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0 &&
	  verbosity != 3'd0)
	$write("\n");
  end
  // synopsys translate_on
endmodule  // mkMMIO_AXI4_Adapter_2

