//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
//
//
//
// Ports:
// Name                         I/O  size props
// RDY_hart0_server_reset_request_put  O     1 reg
// hart0_server_reset_response_get  O     1 reg
// RDY_hart0_server_reset_response_get  O     1 reg
// imem_master_awvalid            O     1 reg
// imem_master_awid               O     4 reg
// imem_master_awaddr             O    64 reg
// imem_master_awlen              O     8 reg
// imem_master_awsize             O     3 reg
// imem_master_awburst            O     2 reg
// imem_master_awlock             O     1 reg
// imem_master_awcache            O     4 reg
// imem_master_awprot             O     3 reg
// imem_master_awqos              O     4 reg
// imem_master_awregion           O     4 reg
// imem_master_wvalid             O     1 reg
// imem_master_wdata              O    64 reg
// imem_master_wstrb              O     8 reg
// imem_master_wlast              O     1 reg
// imem_master_bready             O     1 reg
// imem_master_arvalid            O     1 reg
// imem_master_arid               O     4 reg
// imem_master_araddr             O    64 reg
// imem_master_arlen              O     8 reg
// imem_master_arsize             O     3 reg
// imem_master_arburst            O     2 reg
// imem_master_arlock             O     1 reg
// imem_master_arcache            O     4 reg
// imem_master_arprot             O     3 reg
// imem_master_arqos              O     4 reg
// imem_master_arregion           O     4 reg
// imem_master_rready             O     1 reg
// dmem_master_awvalid            O     1 reg
// dmem_master_awid               O     4 reg
// dmem_master_awaddr             O    64 reg
// dmem_master_awlen              O     8 reg
// dmem_master_awsize             O     3 reg
// dmem_master_awburst            O     2 reg
// dmem_master_awlock             O     1 reg
// dmem_master_awcache            O     4 reg
// dmem_master_awprot             O     3 reg
// dmem_master_awqos              O     4 reg
// dmem_master_awregion           O     4 reg
// dmem_master_wvalid             O     1 reg
// dmem_master_wdata              O    64 reg
// dmem_master_wstrb              O     8 reg
// dmem_master_wlast              O     1 reg
// dmem_master_bready             O     1 reg
// dmem_master_arvalid            O     1 reg
// dmem_master_arid               O     4 reg
// dmem_master_araddr             O    64 reg
// dmem_master_arlen              O     8 reg
// dmem_master_arsize             O     3 reg
// dmem_master_arburst            O     2 reg
// dmem_master_arlock             O     1 reg
// dmem_master_arcache            O     4 reg
// dmem_master_arprot             O     3 reg
// dmem_master_arqos              O     4 reg
// dmem_master_arregion           O     4 reg
// dmem_master_rready             O     1 reg
// RDY_set_verbosity              O     1 const
// RDY_set_watch_tohost           O     1 const
// CLK                            I     1 clock
// RST_N                          I     1 reset
// hart0_server_reset_request_put  I     1 reg
// imem_master_awready            I     1
// imem_master_wready             I     1
// imem_master_bvalid             I     1
// imem_master_bid                I     4 reg
// imem_master_bresp              I     2 reg
// imem_master_arready            I     1
// imem_master_rvalid             I     1
// imem_master_rid                I     4 reg
// imem_master_rdata              I    64 reg
// imem_master_rresp              I     2 reg
// imem_master_rlast              I     1 reg
// dmem_master_awready            I     1
// dmem_master_wready             I     1
// dmem_master_bvalid             I     1
// dmem_master_bid                I     4 reg
// dmem_master_bresp              I     2 reg
// dmem_master_arready            I     1
// dmem_master_rvalid             I     1
// dmem_master_rid                I     4 reg
// dmem_master_rdata              I    64 reg
// dmem_master_rresp              I     2 reg
// dmem_master_rlast              I     1 reg
// m_external_interrupt_req_set_not_clear  I     1 reg
// s_external_interrupt_req_set_not_clear  I     1 reg
// software_interrupt_req_set_not_clear  I     1 reg
// timer_interrupt_req_set_not_clear  I     1 reg
// nmi_req_set_not_clear          I     1
// set_verbosity_verbosity        I     4 reg
// set_verbosity_logdelay         I    64 reg
// set_watch_tohost_watch_tohost  I     1 unused
// set_watch_tohost_tohost_addr   I    64 unused
// EN_hart0_server_reset_request_put  I     1
// EN_set_verbosity               I     1
// EN_set_watch_tohost            I     1 unused
// EN_hart0_server_reset_response_get  I     1
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkCPU(CLK,
	     RST_N,

	     hart0_server_reset_request_put,
	     EN_hart0_server_reset_request_put,
	     RDY_hart0_server_reset_request_put,

	     EN_hart0_server_reset_response_get,
	     hart0_server_reset_response_get,
	     RDY_hart0_server_reset_response_get,

	     imem_master_awvalid,

	     imem_master_awid,

	     imem_master_awaddr,

	     imem_master_awlen,

	     imem_master_awsize,

	     imem_master_awburst,

	     imem_master_awlock,

	     imem_master_awcache,

	     imem_master_awprot,

	     imem_master_awqos,

	     imem_master_awregion,

	     imem_master_awready,

	     imem_master_wvalid,

	     imem_master_wdata,

	     imem_master_wstrb,

	     imem_master_wlast,

	     imem_master_wready,

	     imem_master_bvalid,
	     imem_master_bid,
	     imem_master_bresp,

	     imem_master_bready,

	     imem_master_arvalid,

	     imem_master_arid,

	     imem_master_araddr,

	     imem_master_arlen,

	     imem_master_arsize,

	     imem_master_arburst,

	     imem_master_arlock,

	     imem_master_arcache,

	     imem_master_arprot,

	     imem_master_arqos,

	     imem_master_arregion,

	     imem_master_arready,

	     imem_master_rvalid,
	     imem_master_rid,
	     imem_master_rdata,
	     imem_master_rresp,
	     imem_master_rlast,

	     imem_master_rready,

	     dmem_master_awvalid,

	     dmem_master_awid,

	     dmem_master_awaddr,

	     dmem_master_awlen,

	     dmem_master_awsize,

	     dmem_master_awburst,

	     dmem_master_awlock,

	     dmem_master_awcache,

	     dmem_master_awprot,

	     dmem_master_awqos,

	     dmem_master_awregion,

	     dmem_master_awready,

	     dmem_master_wvalid,

	     dmem_master_wdata,

	     dmem_master_wstrb,

	     dmem_master_wlast,

	     dmem_master_wready,

	     dmem_master_bvalid,
	     dmem_master_bid,
	     dmem_master_bresp,

	     dmem_master_bready,

	     dmem_master_arvalid,

	     dmem_master_arid,

	     dmem_master_araddr,

	     dmem_master_arlen,

	     dmem_master_arsize,

	     dmem_master_arburst,

	     dmem_master_arlock,

	     dmem_master_arcache,

	     dmem_master_arprot,

	     dmem_master_arqos,

	     dmem_master_arregion,

	     dmem_master_arready,

	     dmem_master_rvalid,
	     dmem_master_rid,
	     dmem_master_rdata,
	     dmem_master_rresp,
	     dmem_master_rlast,

	     dmem_master_rready,

	     m_external_interrupt_req_set_not_clear,

	     s_external_interrupt_req_set_not_clear,

	     software_interrupt_req_set_not_clear,

	     timer_interrupt_req_set_not_clear,

	     nmi_req_set_not_clear,

	     set_verbosity_verbosity,
	     set_verbosity_logdelay,
	     EN_set_verbosity,
	     RDY_set_verbosity,

	     set_watch_tohost_watch_tohost,
	     set_watch_tohost_tohost_addr,
	     EN_set_watch_tohost,
	     RDY_set_watch_tohost);
  input  CLK;
  input  RST_N;

  // action method hart0_server_reset_request_put
  input  hart0_server_reset_request_put;
  input  EN_hart0_server_reset_request_put;
  output RDY_hart0_server_reset_request_put;

  // actionvalue method hart0_server_reset_response_get
  input  EN_hart0_server_reset_response_get;
  output hart0_server_reset_response_get;
  output RDY_hart0_server_reset_response_get;

  // value method imem_master_m_awvalid
  output imem_master_awvalid;

  // value method imem_master_m_awid
  output [3 : 0] imem_master_awid;

  // value method imem_master_m_awaddr
  output [63 : 0] imem_master_awaddr;

  // value method imem_master_m_awlen
  output [7 : 0] imem_master_awlen;

  // value method imem_master_m_awsize
  output [2 : 0] imem_master_awsize;

  // value method imem_master_m_awburst
  output [1 : 0] imem_master_awburst;

  // value method imem_master_m_awlock
  output imem_master_awlock;

  // value method imem_master_m_awcache
  output [3 : 0] imem_master_awcache;

  // value method imem_master_m_awprot
  output [2 : 0] imem_master_awprot;

  // value method imem_master_m_awqos
  output [3 : 0] imem_master_awqos;

  // value method imem_master_m_awregion
  output [3 : 0] imem_master_awregion;

  // value method imem_master_m_awuser

  // action method imem_master_m_awready
  input  imem_master_awready;

  // value method imem_master_m_wvalid
  output imem_master_wvalid;

  // value method imem_master_m_wdata
  output [63 : 0] imem_master_wdata;

  // value method imem_master_m_wstrb
  output [7 : 0] imem_master_wstrb;

  // value method imem_master_m_wlast
  output imem_master_wlast;

  // value method imem_master_m_wuser

  // action method imem_master_m_wready
  input  imem_master_wready;

  // action method imem_master_m_bvalid
  input  imem_master_bvalid;
  input  [3 : 0] imem_master_bid;
  input  [1 : 0] imem_master_bresp;

  // value method imem_master_m_bready
  output imem_master_bready;

  // value method imem_master_m_arvalid
  output imem_master_arvalid;

  // value method imem_master_m_arid
  output [3 : 0] imem_master_arid;

  // value method imem_master_m_araddr
  output [63 : 0] imem_master_araddr;

  // value method imem_master_m_arlen
  output [7 : 0] imem_master_arlen;

  // value method imem_master_m_arsize
  output [2 : 0] imem_master_arsize;

  // value method imem_master_m_arburst
  output [1 : 0] imem_master_arburst;

  // value method imem_master_m_arlock
  output imem_master_arlock;

  // value method imem_master_m_arcache
  output [3 : 0] imem_master_arcache;

  // value method imem_master_m_arprot
  output [2 : 0] imem_master_arprot;

  // value method imem_master_m_arqos
  output [3 : 0] imem_master_arqos;

  // value method imem_master_m_arregion
  output [3 : 0] imem_master_arregion;

  // value method imem_master_m_aruser

  // action method imem_master_m_arready
  input  imem_master_arready;

  // action method imem_master_m_rvalid
  input  imem_master_rvalid;
  input  [3 : 0] imem_master_rid;
  input  [63 : 0] imem_master_rdata;
  input  [1 : 0] imem_master_rresp;
  input  imem_master_rlast;

  // value method imem_master_m_rready
  output imem_master_rready;

  // value method dmem_master_m_awvalid
  output dmem_master_awvalid;

  // value method dmem_master_m_awid
  output [3 : 0] dmem_master_awid;

  // value method dmem_master_m_awaddr
  output [63 : 0] dmem_master_awaddr;

  // value method dmem_master_m_awlen
  output [7 : 0] dmem_master_awlen;

  // value method dmem_master_m_awsize
  output [2 : 0] dmem_master_awsize;

  // value method dmem_master_m_awburst
  output [1 : 0] dmem_master_awburst;

  // value method dmem_master_m_awlock
  output dmem_master_awlock;

  // value method dmem_master_m_awcache
  output [3 : 0] dmem_master_awcache;

  // value method dmem_master_m_awprot
  output [2 : 0] dmem_master_awprot;

  // value method dmem_master_m_awqos
  output [3 : 0] dmem_master_awqos;

  // value method dmem_master_m_awregion
  output [3 : 0] dmem_master_awregion;

  // value method dmem_master_m_awuser

  // action method dmem_master_m_awready
  input  dmem_master_awready;

  // value method dmem_master_m_wvalid
  output dmem_master_wvalid;

  // value method dmem_master_m_wdata
  output [63 : 0] dmem_master_wdata;

  // value method dmem_master_m_wstrb
  output [7 : 0] dmem_master_wstrb;

  // value method dmem_master_m_wlast
  output dmem_master_wlast;

  // value method dmem_master_m_wuser

  // action method dmem_master_m_wready
  input  dmem_master_wready;

  // action method dmem_master_m_bvalid
  input  dmem_master_bvalid;
  input  [3 : 0] dmem_master_bid;
  input  [1 : 0] dmem_master_bresp;

  // value method dmem_master_m_bready
  output dmem_master_bready;

  // value method dmem_master_m_arvalid
  output dmem_master_arvalid;

  // value method dmem_master_m_arid
  output [3 : 0] dmem_master_arid;

  // value method dmem_master_m_araddr
  output [63 : 0] dmem_master_araddr;

  // value method dmem_master_m_arlen
  output [7 : 0] dmem_master_arlen;

  // value method dmem_master_m_arsize
  output [2 : 0] dmem_master_arsize;

  // value method dmem_master_m_arburst
  output [1 : 0] dmem_master_arburst;

  // value method dmem_master_m_arlock
  output dmem_master_arlock;

  // value method dmem_master_m_arcache
  output [3 : 0] dmem_master_arcache;

  // value method dmem_master_m_arprot
  output [2 : 0] dmem_master_arprot;

  // value method dmem_master_m_arqos
  output [3 : 0] dmem_master_arqos;

  // value method dmem_master_m_arregion
  output [3 : 0] dmem_master_arregion;

  // value method dmem_master_m_aruser

  // action method dmem_master_m_arready
  input  dmem_master_arready;

  // action method dmem_master_m_rvalid
  input  dmem_master_rvalid;
  input  [3 : 0] dmem_master_rid;
  input  [63 : 0] dmem_master_rdata;
  input  [1 : 0] dmem_master_rresp;
  input  dmem_master_rlast;

  // value method dmem_master_m_rready
  output dmem_master_rready;

  // action method m_external_interrupt_req
  input  m_external_interrupt_req_set_not_clear;

  // action method s_external_interrupt_req
  input  s_external_interrupt_req_set_not_clear;

  // action method software_interrupt_req
  input  software_interrupt_req_set_not_clear;

  // action method timer_interrupt_req
  input  timer_interrupt_req_set_not_clear;

  // action method nmi_req
  input  nmi_req_set_not_clear;

  // action method set_verbosity
  input  [3 : 0] set_verbosity_verbosity;
  input  [63 : 0] set_verbosity_logdelay;
  input  EN_set_verbosity;
  output RDY_set_verbosity;

  // action method set_watch_tohost
  input  set_watch_tohost_watch_tohost;
  input  [63 : 0] set_watch_tohost_tohost_addr;
  input  EN_set_watch_tohost;
  output RDY_set_watch_tohost;

  // signals for module outputs
  wire [63 : 0] dmem_master_araddr,
		dmem_master_awaddr,
		dmem_master_wdata,
		imem_master_araddr,
		imem_master_awaddr,
		imem_master_wdata;
  wire [7 : 0] dmem_master_arlen,
	       dmem_master_awlen,
	       dmem_master_wstrb,
	       imem_master_arlen,
	       imem_master_awlen,
	       imem_master_wstrb;
  wire [3 : 0] dmem_master_arcache,
	       dmem_master_arid,
	       dmem_master_arqos,
	       dmem_master_arregion,
	       dmem_master_awcache,
	       dmem_master_awid,
	       dmem_master_awqos,
	       dmem_master_awregion,
	       imem_master_arcache,
	       imem_master_arid,
	       imem_master_arqos,
	       imem_master_arregion,
	       imem_master_awcache,
	       imem_master_awid,
	       imem_master_awqos,
	       imem_master_awregion;
  wire [2 : 0] dmem_master_arprot,
	       dmem_master_arsize,
	       dmem_master_awprot,
	       dmem_master_awsize,
	       imem_master_arprot,
	       imem_master_arsize,
	       imem_master_awprot,
	       imem_master_awsize;
  wire [1 : 0] dmem_master_arburst,
	       dmem_master_awburst,
	       imem_master_arburst,
	       imem_master_awburst;
  wire RDY_hart0_server_reset_request_put,
       RDY_hart0_server_reset_response_get,
       RDY_set_verbosity,
       RDY_set_watch_tohost,
       dmem_master_arlock,
       dmem_master_arvalid,
       dmem_master_awlock,
       dmem_master_awvalid,
       dmem_master_bready,
       dmem_master_rready,
       dmem_master_wlast,
       dmem_master_wvalid,
       hart0_server_reset_response_get,
       imem_master_arlock,
       imem_master_arvalid,
       imem_master_awlock,
       imem_master_awvalid,
       imem_master_bready,
       imem_master_rready,
       imem_master_wlast,
       imem_master_wvalid;

  // register cfg_logdelay
  reg [63 : 0] cfg_logdelay;
  wire [63 : 0] cfg_logdelay$D_IN;
  wire cfg_logdelay$EN;

  // register cfg_verbosity
  reg [3 : 0] cfg_verbosity;
  wire [3 : 0] cfg_verbosity$D_IN;
  wire cfg_verbosity$EN;

  // register imem_rg_cache_addr
  reg [31 : 0] imem_rg_cache_addr;
  wire [31 : 0] imem_rg_cache_addr$D_IN;
  wire imem_rg_cache_addr$EN;

  // register imem_rg_cache_b16
  reg [15 : 0] imem_rg_cache_b16;
  wire [15 : 0] imem_rg_cache_b16$D_IN;
  wire imem_rg_cache_b16$EN;

  // register imem_rg_f3
  reg [2 : 0] imem_rg_f3;
  wire [2 : 0] imem_rg_f3$D_IN;
  wire imem_rg_f3$EN;

  // register imem_rg_mstatus_MXR
  reg imem_rg_mstatus_MXR;
  wire imem_rg_mstatus_MXR$D_IN, imem_rg_mstatus_MXR$EN;

  // register imem_rg_pc
  reg [31 : 0] imem_rg_pc;
  reg [31 : 0] imem_rg_pc$D_IN;
  wire imem_rg_pc$EN;

  // register imem_rg_priv
  reg [1 : 0] imem_rg_priv;
  wire [1 : 0] imem_rg_priv$D_IN;
  wire imem_rg_priv$EN;

  // register imem_rg_satp
  reg [31 : 0] imem_rg_satp;
  wire [31 : 0] imem_rg_satp$D_IN;
  wire imem_rg_satp$EN;

  // register imem_rg_sstatus_SUM
  reg imem_rg_sstatus_SUM;
  wire imem_rg_sstatus_SUM$D_IN, imem_rg_sstatus_SUM$EN;

  // register imem_rg_tval
  reg [31 : 0] imem_rg_tval;
  reg [31 : 0] imem_rg_tval$D_IN;
  wire imem_rg_tval$EN;

  // register rg_csr_pc
  reg [31 : 0] rg_csr_pc;
  wire [31 : 0] rg_csr_pc$D_IN;
  wire rg_csr_pc$EN;

  // register rg_csr_val1
  reg [31 : 0] rg_csr_val1;
  wire [31 : 0] rg_csr_val1$D_IN;
  wire rg_csr_val1$EN;

  // register rg_cur_priv
  reg [1 : 0] rg_cur_priv;
  reg [1 : 0] rg_cur_priv$D_IN;
  wire rg_cur_priv$EN;

  // register rg_epoch
  reg [1 : 0] rg_epoch;
  reg [1 : 0] rg_epoch$D_IN;
  wire rg_epoch$EN;

  // register rg_mstatus_MXR
  reg rg_mstatus_MXR;
  wire rg_mstatus_MXR$D_IN, rg_mstatus_MXR$EN;

  // register rg_next_pc
  reg [31 : 0] rg_next_pc;
  reg [31 : 0] rg_next_pc$D_IN;
  wire rg_next_pc$EN;

  // register rg_run_on_reset
  reg rg_run_on_reset;
  wire rg_run_on_reset$D_IN, rg_run_on_reset$EN;

  // register rg_sstatus_SUM
  reg rg_sstatus_SUM;
  wire rg_sstatus_SUM$D_IN, rg_sstatus_SUM$EN;

  // register rg_start_CPI_cycles
  reg [63 : 0] rg_start_CPI_cycles;
  wire [63 : 0] rg_start_CPI_cycles$D_IN;
  wire rg_start_CPI_cycles$EN;

  // register rg_start_CPI_instrs
  reg [63 : 0] rg_start_CPI_instrs;
  wire [63 : 0] rg_start_CPI_instrs$D_IN;
  wire rg_start_CPI_instrs$EN;

  // register rg_state
  reg [3 : 0] rg_state;
  reg [3 : 0] rg_state$D_IN;
  wire rg_state$EN;

  // register rg_trap_info
  reg [67 : 0] rg_trap_info;
  reg [67 : 0] rg_trap_info$D_IN;
  wire rg_trap_info$EN;

  // register rg_trap_instr
  reg [31 : 0] rg_trap_instr;
  wire [31 : 0] rg_trap_instr$D_IN;
  wire rg_trap_instr$EN;

  // register rg_trap_interrupt
  reg rg_trap_interrupt;
  wire rg_trap_interrupt$D_IN, rg_trap_interrupt$EN;

  // register stage1_rg_full
  reg stage1_rg_full;
  reg stage1_rg_full$D_IN;
  wire stage1_rg_full$EN;

  // register stage1_rg_stage_input
  reg [305 : 0] stage1_rg_stage_input;
  wire [305 : 0] stage1_rg_stage_input$D_IN;
  wire stage1_rg_stage_input$EN;

  // register stage2_rg_full
  reg stage2_rg_full;
  reg stage2_rg_full$D_IN;
  wire stage2_rg_full$EN;

  // register stage2_rg_resetting
  reg stage2_rg_resetting;
  wire stage2_rg_resetting$D_IN, stage2_rg_resetting$EN;

  // register stage2_rg_stage2
  reg [169 : 0] stage2_rg_stage2;
  wire [169 : 0] stage2_rg_stage2$D_IN;
  wire stage2_rg_stage2$EN;

  // register stage3_rg_full
  reg stage3_rg_full;
  reg stage3_rg_full$D_IN;
  wire stage3_rg_full$EN;

  // register stage3_rg_stage3
  reg [103 : 0] stage3_rg_stage3;
  wire [103 : 0] stage3_rg_stage3$D_IN;
  wire stage3_rg_stage3$EN;

  // register stageD_rg_data
  reg [137 : 0] stageD_rg_data;
  wire [137 : 0] stageD_rg_data$D_IN;
  wire stageD_rg_data$EN;

  // register stageD_rg_full
  reg stageD_rg_full;
  reg stageD_rg_full$D_IN;
  wire stageD_rg_full$EN;

  // register stageF_rg_epoch
  reg [1 : 0] stageF_rg_epoch;
  reg [1 : 0] stageF_rg_epoch$D_IN;
  wire stageF_rg_epoch$EN;

  // register stageF_rg_full
  reg stageF_rg_full;
  reg stageF_rg_full$D_IN;
  wire stageF_rg_full$EN;

  // register stageF_rg_priv
  reg [1 : 0] stageF_rg_priv;
  wire [1 : 0] stageF_rg_priv$D_IN;
  wire stageF_rg_priv$EN;

  // ports of submodule csr_regfile
  reg [1 : 0] csr_regfile$csr_ret_actions_from_priv;
  wire [97 : 0] csr_regfile$csr_trap_actions;
  wire [65 : 0] csr_regfile$csr_ret_actions;
  wire [63 : 0] csr_regfile$read_csr_mcycle, csr_regfile$read_csr_minstret;
  wire [32 : 0] csr_regfile$read_csr;
  wire [31 : 0] csr_regfile$csr_trap_actions_pc,
		csr_regfile$csr_trap_actions_xtval,
		csr_regfile$mav_csr_write_word,
		csr_regfile$read_mstatus,
		csr_regfile$read_satp;
  wire [27 : 0] csr_regfile$read_misa;
  wire [11 : 0] csr_regfile$access_permitted_1_csr_addr,
		csr_regfile$access_permitted_2_csr_addr,
		csr_regfile$csr_counter_read_fault_csr_addr,
		csr_regfile$mav_csr_write_csr_addr,
		csr_regfile$mav_read_csr_csr_addr,
		csr_regfile$read_csr_csr_addr,
		csr_regfile$read_csr_port2_csr_addr;
  wire [4 : 0] csr_regfile$interrupt_pending;
  wire [3 : 0] csr_regfile$csr_trap_actions_exc_code;
  wire [1 : 0] csr_regfile$access_permitted_1_priv,
	       csr_regfile$access_permitted_2_priv,
	       csr_regfile$csr_counter_read_fault_priv,
	       csr_regfile$csr_trap_actions_from_priv,
	       csr_regfile$interrupt_pending_cur_priv;
  wire csr_regfile$EN_csr_minstret_incr,
       csr_regfile$EN_csr_ret_actions,
       csr_regfile$EN_csr_trap_actions,
       csr_regfile$EN_debug,
       csr_regfile$EN_mav_csr_write,
       csr_regfile$EN_mav_read_csr,
       csr_regfile$EN_server_reset_request_put,
       csr_regfile$EN_server_reset_response_get,
       csr_regfile$RDY_server_reset_request_put,
       csr_regfile$RDY_server_reset_response_get,
       csr_regfile$access_permitted_1,
       csr_regfile$access_permitted_1_read_not_write,
       csr_regfile$access_permitted_2,
       csr_regfile$access_permitted_2_read_not_write,
       csr_regfile$csr_trap_actions_interrupt,
       csr_regfile$csr_trap_actions_nmi,
       csr_regfile$m_external_interrupt_req_set_not_clear,
       csr_regfile$nmi_pending,
       csr_regfile$nmi_req_set_not_clear,
       csr_regfile$s_external_interrupt_req_set_not_clear,
       csr_regfile$software_interrupt_req_set_not_clear,
       csr_regfile$timer_interrupt_req_set_not_clear,
       csr_regfile$wfi_resume;

  // ports of submodule f_reset_reqs
  wire f_reset_reqs$CLR,
       f_reset_reqs$DEQ,
       f_reset_reqs$D_IN,
       f_reset_reqs$D_OUT,
       f_reset_reqs$EMPTY_N,
       f_reset_reqs$ENQ,
       f_reset_reqs$FULL_N;

  // ports of submodule f_reset_rsps
  wire f_reset_rsps$CLR,
       f_reset_rsps$DEQ,
       f_reset_rsps$D_IN,
       f_reset_rsps$D_OUT,
       f_reset_rsps$EMPTY_N,
       f_reset_rsps$ENQ,
       f_reset_rsps$FULL_N;

  // ports of submodule gpr_regfile
  wire [31 : 0] gpr_regfile$read_rs1,
		gpr_regfile$read_rs2,
		gpr_regfile$write_rd_rd_val;
  wire [4 : 0] gpr_regfile$read_rs1_port2_rs1,
	       gpr_regfile$read_rs1_rs1,
	       gpr_regfile$read_rs2_rs2,
	       gpr_regfile$write_rd_rd;
  wire gpr_regfile$EN_server_reset_request_put,
       gpr_regfile$EN_server_reset_response_get,
       gpr_regfile$EN_write_rd,
       gpr_regfile$RDY_server_reset_request_put,
       gpr_regfile$RDY_server_reset_response_get;

  // ports of submodule near_mem
  reg [31 : 0] near_mem$imem_req_addr;
  reg [1 : 0] near_mem$dmem_req_op;
  wire [63 : 0] near_mem$dmem_master_araddr,
		near_mem$dmem_master_awaddr,
		near_mem$dmem_master_rdata,
		near_mem$dmem_master_wdata,
		near_mem$dmem_req_store_value,
		near_mem$dmem_word64,
		near_mem$imem_master_araddr,
		near_mem$imem_master_awaddr,
		near_mem$imem_master_rdata,
		near_mem$imem_master_wdata,
		near_mem$set_watch_tohost_tohost_addr;
  wire [31 : 0] near_mem$dmem_req_addr,
		near_mem$dmem_req_satp,
		near_mem$imem_instr,
		near_mem$imem_pc,
		near_mem$imem_req_satp;
  wire [7 : 0] near_mem$dmem_master_arlen,
	       near_mem$dmem_master_awlen,
	       near_mem$dmem_master_wstrb,
	       near_mem$imem_master_arlen,
	       near_mem$imem_master_awlen,
	       near_mem$imem_master_wstrb,
	       near_mem$server_fence_request_put;
  wire [6 : 0] near_mem$dmem_req_amo_funct7;
  wire [3 : 0] near_mem$dmem_exc_code,
	       near_mem$dmem_master_arcache,
	       near_mem$dmem_master_arid,
	       near_mem$dmem_master_arqos,
	       near_mem$dmem_master_arregion,
	       near_mem$dmem_master_awcache,
	       near_mem$dmem_master_awid,
	       near_mem$dmem_master_awqos,
	       near_mem$dmem_master_awregion,
	       near_mem$dmem_master_bid,
	       near_mem$dmem_master_rid,
	       near_mem$imem_exc_code,
	       near_mem$imem_master_arcache,
	       near_mem$imem_master_arid,
	       near_mem$imem_master_arqos,
	       near_mem$imem_master_arregion,
	       near_mem$imem_master_awcache,
	       near_mem$imem_master_awid,
	       near_mem$imem_master_awqos,
	       near_mem$imem_master_awregion,
	       near_mem$imem_master_bid,
	       near_mem$imem_master_rid;
  wire [2 : 0] near_mem$dmem_master_arprot,
	       near_mem$dmem_master_arsize,
	       near_mem$dmem_master_awprot,
	       near_mem$dmem_master_awsize,
	       near_mem$dmem_req_f3,
	       near_mem$imem_master_arprot,
	       near_mem$imem_master_arsize,
	       near_mem$imem_master_awprot,
	       near_mem$imem_master_awsize,
	       near_mem$imem_req_f3;
  wire [1 : 0] near_mem$dmem_master_arburst,
	       near_mem$dmem_master_awburst,
	       near_mem$dmem_master_bresp,
	       near_mem$dmem_master_rresp,
	       near_mem$dmem_req_priv,
	       near_mem$imem_master_arburst,
	       near_mem$imem_master_awburst,
	       near_mem$imem_master_bresp,
	       near_mem$imem_master_rresp,
	       near_mem$imem_req_priv;
  wire near_mem$EN_dmem_req,
       near_mem$EN_imem_req,
       near_mem$EN_server_fence_i_request_put,
       near_mem$EN_server_fence_i_response_get,
       near_mem$EN_server_fence_request_put,
       near_mem$EN_server_fence_response_get,
       near_mem$EN_server_reset_request_put,
       near_mem$EN_server_reset_response_get,
       near_mem$EN_set_watch_tohost,
       near_mem$RDY_server_fence_i_request_put,
       near_mem$RDY_server_fence_i_response_get,
       near_mem$RDY_server_fence_request_put,
       near_mem$RDY_server_fence_response_get,
       near_mem$RDY_server_reset_request_put,
       near_mem$RDY_server_reset_response_get,
       near_mem$dmem_exc,
       near_mem$dmem_master_arlock,
       near_mem$dmem_master_arready,
       near_mem$dmem_master_arvalid,
       near_mem$dmem_master_awlock,
       near_mem$dmem_master_awready,
       near_mem$dmem_master_awvalid,
       near_mem$dmem_master_bready,
       near_mem$dmem_master_bvalid,
       near_mem$dmem_master_rlast,
       near_mem$dmem_master_rready,
       near_mem$dmem_master_rvalid,
       near_mem$dmem_master_wlast,
       near_mem$dmem_master_wready,
       near_mem$dmem_master_wvalid,
       near_mem$dmem_req_mstatus_MXR,
       near_mem$dmem_req_sstatus_SUM,
       near_mem$dmem_valid,
       near_mem$imem_exc,
       near_mem$imem_is_i32_not_i16,
       near_mem$imem_master_arlock,
       near_mem$imem_master_arready,
       near_mem$imem_master_arvalid,
       near_mem$imem_master_awlock,
       near_mem$imem_master_awready,
       near_mem$imem_master_awvalid,
       near_mem$imem_master_bready,
       near_mem$imem_master_bvalid,
       near_mem$imem_master_rlast,
       near_mem$imem_master_rready,
       near_mem$imem_master_rvalid,
       near_mem$imem_master_wlast,
       near_mem$imem_master_wready,
       near_mem$imem_master_wvalid,
       near_mem$imem_req_mstatus_MXR,
       near_mem$imem_req_sstatus_SUM,
       near_mem$imem_valid,
       near_mem$set_watch_tohost_watch_tohost;

  // ports of submodule soc_map
  wire [63 : 0] soc_map$m_is_IO_addr_addr,
		soc_map$m_is_mem_addr_addr,
		soc_map$m_is_near_mem_IO_addr_addr,
		soc_map$m_pc_reset_value;

  // ports of submodule stage1_f_reset_reqs
  wire stage1_f_reset_reqs$CLR,
       stage1_f_reset_reqs$DEQ,
       stage1_f_reset_reqs$EMPTY_N,
       stage1_f_reset_reqs$ENQ,
       stage1_f_reset_reqs$FULL_N;

  // ports of submodule stage1_f_reset_rsps
  wire stage1_f_reset_rsps$CLR,
       stage1_f_reset_rsps$DEQ,
       stage1_f_reset_rsps$EMPTY_N,
       stage1_f_reset_rsps$ENQ,
       stage1_f_reset_rsps$FULL_N;

  // ports of submodule stage2_f_reset_reqs
  wire stage2_f_reset_reqs$CLR,
       stage2_f_reset_reqs$DEQ,
       stage2_f_reset_reqs$EMPTY_N,
       stage2_f_reset_reqs$ENQ,
       stage2_f_reset_reqs$FULL_N;

  // ports of submodule stage2_f_reset_rsps
  wire stage2_f_reset_rsps$CLR,
       stage2_f_reset_rsps$DEQ,
       stage2_f_reset_rsps$EMPTY_N,
       stage2_f_reset_rsps$ENQ,
       stage2_f_reset_rsps$FULL_N;

  // ports of submodule stage2_mbox
  wire [31 : 0] stage2_mbox$req_v1, stage2_mbox$req_v2, stage2_mbox$word;
  wire [3 : 0] stage2_mbox$set_verbosity_verbosity;
  wire [2 : 0] stage2_mbox$req_f3;
  wire stage2_mbox$EN_req,
       stage2_mbox$EN_req_reset,
       stage2_mbox$EN_rsp_reset,
       stage2_mbox$EN_set_verbosity,
       stage2_mbox$req_is_OP_not_OP_32,
       stage2_mbox$valid;

  // ports of submodule stage3_f_reset_reqs
  wire stage3_f_reset_reqs$CLR,
       stage3_f_reset_reqs$DEQ,
       stage3_f_reset_reqs$EMPTY_N,
       stage3_f_reset_reqs$ENQ,
       stage3_f_reset_reqs$FULL_N;

  // ports of submodule stage3_f_reset_rsps
  wire stage3_f_reset_rsps$CLR,
       stage3_f_reset_rsps$DEQ,
       stage3_f_reset_rsps$EMPTY_N,
       stage3_f_reset_rsps$ENQ,
       stage3_f_reset_rsps$FULL_N;

  // ports of submodule stageD_f_reset_reqs
  wire stageD_f_reset_reqs$CLR,
       stageD_f_reset_reqs$DEQ,
       stageD_f_reset_reqs$EMPTY_N,
       stageD_f_reset_reqs$ENQ,
       stageD_f_reset_reqs$FULL_N;

  // ports of submodule stageD_f_reset_rsps
  wire stageD_f_reset_rsps$CLR,
       stageD_f_reset_rsps$DEQ,
       stageD_f_reset_rsps$EMPTY_N,
       stageD_f_reset_rsps$ENQ,
       stageD_f_reset_rsps$FULL_N;

  // ports of submodule stageF_branch_predictor
  reg [31 : 0] stageF_branch_predictor$predict_req_pc;
  wire [98 : 0] stageF_branch_predictor$bp_train_cf_info;
  wire [31 : 0] stageF_branch_predictor$bp_train_instr,
		stageF_branch_predictor$bp_train_pc,
		stageF_branch_predictor$predict_rsp,
		stageF_branch_predictor$predict_rsp_instr;
  wire stageF_branch_predictor$EN_bp_train,
       stageF_branch_predictor$EN_predict_req,
       stageF_branch_predictor$EN_reset,
       stageF_branch_predictor$RDY_predict_req,
       stageF_branch_predictor$bp_train_is_i32_not_i16,
       stageF_branch_predictor$predict_rsp_is_i32_not_i16;

  // ports of submodule stageF_f_reset_reqs
  wire stageF_f_reset_reqs$CLR,
       stageF_f_reset_reqs$DEQ,
       stageF_f_reset_reqs$EMPTY_N,
       stageF_f_reset_reqs$ENQ,
       stageF_f_reset_reqs$FULL_N;

  // ports of submodule stageF_f_reset_rsps
  wire stageF_f_reset_rsps$CLR,
       stageF_f_reset_rsps$DEQ,
       stageF_f_reset_rsps$EMPTY_N,
       stageF_f_reset_rsps$ENQ,
       stageF_f_reset_rsps$FULL_N;

  // rule scheduling signals
  wire CAN_FIRE_RL_imem_rl_assert_fail,
       CAN_FIRE_RL_imem_rl_fetch_next_32b,
       CAN_FIRE_RL_rl_WFI_resume,
       CAN_FIRE_RL_rl_finish_FENCE,
       CAN_FIRE_RL_rl_finish_FENCE_I,
       CAN_FIRE_RL_rl_pipe,
       CAN_FIRE_RL_rl_reset_complete,
       CAN_FIRE_RL_rl_reset_from_WFI,
       CAN_FIRE_RL_rl_reset_start,
       CAN_FIRE_RL_rl_show_pipe,
       CAN_FIRE_RL_rl_stage1_CSRR_S_or_C,
       CAN_FIRE_RL_rl_stage1_CSRR_S_or_C_2,
       CAN_FIRE_RL_rl_stage1_CSRR_W,
       CAN_FIRE_RL_rl_stage1_CSRR_W_2,
       CAN_FIRE_RL_rl_stage1_FENCE,
       CAN_FIRE_RL_rl_stage1_FENCE_I,
       CAN_FIRE_RL_rl_stage1_WFI,
       CAN_FIRE_RL_rl_stage1_interrupt,
       CAN_FIRE_RL_rl_stage1_restart_after_csrrx,
       CAN_FIRE_RL_rl_stage1_trap,
       CAN_FIRE_RL_rl_stage1_xRET,
       CAN_FIRE_RL_rl_stage2_nonpipe,
       CAN_FIRE_RL_rl_trap,
       CAN_FIRE_RL_rl_trap_fetch,
       CAN_FIRE_RL_stage1_rl_reset,
       CAN_FIRE_RL_stage2_rl_reset_begin,
       CAN_FIRE_RL_stage2_rl_reset_end,
       CAN_FIRE_RL_stage3_rl_reset,
       CAN_FIRE_RL_stageD_rl_reset,
       CAN_FIRE_RL_stageF_rl_reset,
       CAN_FIRE_dmem_master_m_arready,
       CAN_FIRE_dmem_master_m_awready,
       CAN_FIRE_dmem_master_m_bvalid,
       CAN_FIRE_dmem_master_m_rvalid,
       CAN_FIRE_dmem_master_m_wready,
       CAN_FIRE_hart0_server_reset_request_put,
       CAN_FIRE_hart0_server_reset_response_get,
       CAN_FIRE_imem_master_m_arready,
       CAN_FIRE_imem_master_m_awready,
       CAN_FIRE_imem_master_m_bvalid,
       CAN_FIRE_imem_master_m_rvalid,
       CAN_FIRE_imem_master_m_wready,
       CAN_FIRE_m_external_interrupt_req,
       CAN_FIRE_nmi_req,
       CAN_FIRE_s_external_interrupt_req,
       CAN_FIRE_set_verbosity,
       CAN_FIRE_set_watch_tohost,
       CAN_FIRE_software_interrupt_req,
       CAN_FIRE_timer_interrupt_req,
       WILL_FIRE_RL_imem_rl_assert_fail,
       WILL_FIRE_RL_imem_rl_fetch_next_32b,
       WILL_FIRE_RL_rl_WFI_resume,
       WILL_FIRE_RL_rl_finish_FENCE,
       WILL_FIRE_RL_rl_finish_FENCE_I,
       WILL_FIRE_RL_rl_pipe,
       WILL_FIRE_RL_rl_reset_complete,
       WILL_FIRE_RL_rl_reset_from_WFI,
       WILL_FIRE_RL_rl_reset_start,
       WILL_FIRE_RL_rl_show_pipe,
       WILL_FIRE_RL_rl_stage1_CSRR_S_or_C,
       WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2,
       WILL_FIRE_RL_rl_stage1_CSRR_W,
       WILL_FIRE_RL_rl_stage1_CSRR_W_2,
       WILL_FIRE_RL_rl_stage1_FENCE,
       WILL_FIRE_RL_rl_stage1_FENCE_I,
       WILL_FIRE_RL_rl_stage1_WFI,
       WILL_FIRE_RL_rl_stage1_interrupt,
       WILL_FIRE_RL_rl_stage1_restart_after_csrrx,
       WILL_FIRE_RL_rl_stage1_trap,
       WILL_FIRE_RL_rl_stage1_xRET,
       WILL_FIRE_RL_rl_stage2_nonpipe,
       WILL_FIRE_RL_rl_trap,
       WILL_FIRE_RL_rl_trap_fetch,
       WILL_FIRE_RL_stage1_rl_reset,
       WILL_FIRE_RL_stage2_rl_reset_begin,
       WILL_FIRE_RL_stage2_rl_reset_end,
       WILL_FIRE_RL_stage3_rl_reset,
       WILL_FIRE_RL_stageD_rl_reset,
       WILL_FIRE_RL_stageF_rl_reset,
       WILL_FIRE_dmem_master_m_arready,
       WILL_FIRE_dmem_master_m_awready,
       WILL_FIRE_dmem_master_m_bvalid,
       WILL_FIRE_dmem_master_m_rvalid,
       WILL_FIRE_dmem_master_m_wready,
       WILL_FIRE_hart0_server_reset_request_put,
       WILL_FIRE_hart0_server_reset_response_get,
       WILL_FIRE_imem_master_m_arready,
       WILL_FIRE_imem_master_m_awready,
       WILL_FIRE_imem_master_m_bvalid,
       WILL_FIRE_imem_master_m_rvalid,
       WILL_FIRE_imem_master_m_wready,
       WILL_FIRE_m_external_interrupt_req,
       WILL_FIRE_nmi_req,
       WILL_FIRE_s_external_interrupt_req,
       WILL_FIRE_set_verbosity,
       WILL_FIRE_set_watch_tohost,
       WILL_FIRE_software_interrupt_req,
       WILL_FIRE_timer_interrupt_req;

  // inputs to muxes for submodule ports
  reg [31 : 0] MUX_csr_regfile$mav_csr_write_2__VAL_2;
  wire [67 : 0] MUX_rg_trap_info$write_1__VAL_1,
		MUX_rg_trap_info$write_1__VAL_2,
		MUX_rg_trap_info$write_1__VAL_3,
		MUX_rg_trap_info$write_1__VAL_4;
  wire [31 : 0] MUX_imem_rg_tval$write_1__VAL_4,
		MUX_near_mem$imem_req_2__VAL_1,
		MUX_near_mem$imem_req_2__VAL_2,
		MUX_near_mem$imem_req_2__VAL_4,
		MUX_rg_trap_instr$write_1__VAL_1;
  wire [3 : 0] MUX_rg_state$write_1__VAL_2,
	       MUX_rg_state$write_1__VAL_3,
	       MUX_rg_state$write_1__VAL_4;
  wire MUX_csr_regfile$mav_csr_write_1__SEL_1,
       MUX_gpr_regfile$write_rd_1__SEL_3,
       MUX_imem_rg_cache_addr$write_1__SEL_3,
       MUX_imem_rg_f3$write_1__SEL_1,
       MUX_rg_next_pc$write_1__SEL_1,
       MUX_rg_next_pc$write_1__SEL_2,
       MUX_rg_state$write_1__SEL_1,
       MUX_rg_state$write_1__SEL_10,
       MUX_rg_state$write_1__SEL_11,
       MUX_rg_state$write_1__SEL_12,
       MUX_rg_state$write_1__SEL_13,
       MUX_rg_state$write_1__SEL_2,
       MUX_rg_state$write_1__SEL_5,
       MUX_rg_state$write_1__SEL_7,
       MUX_rg_state$write_1__SEL_8,
       MUX_rg_state$write_1__SEL_9,
       MUX_rg_trap_info$write_1__SEL_1,
       MUX_rg_trap_instr$write_1__SEL_1,
       MUX_rg_trap_interrupt$write_1__SEL_1,
       MUX_stage1_rg_full$write_1__VAL_2,
       MUX_stage2_rg_full$write_1__VAL_2,
       MUX_stageD_rg_full$write_1__VAL_2,
       MUX_stageF_rg_full$write_1__VAL_2;

  // declarations used by system tasks
  // synopsys translate_off
  reg [31 : 0] v__h2152;
  reg [31 : 0] v__h2146;
  // synopsys translate_on

  // remaining internal signals
  reg [31 : 0] CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q18,
	       IF_stage1_rg_stage_input_01_BITS_151_TO_145_28_ETC___d729,
	       _theResult_____1_fst__h8745,
	       rs1_val__h22743,
	       x_out_bypass_rd_val__h7432,
	       x_out_cf_info_taken_PC__h9505,
	       x_out_data_to_stage2_addr__h7720,
	       x_out_data_to_stage2_val1__h7721,
	       x_out_data_to_stage3_rd_val__h7093;
  reg [4 : 0] x_out_bypass_rd__h7431, x_out_data_to_stage3_rd__h7092;
  reg [3 : 0] CASE_rg_cur_priv_0b0_8_0b1_9_11__q3,
	      CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q12,
	      CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q13,
	      CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q14,
	      CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q16,
	      CASE_stage1_rg_stage_input_BITS_87_TO_76_0b0_1_ETC__q15,
	      CASE_stage1_rg_stage_input_BITS_87_TO_76_0b0_C_ETC__q4,
	      IF_stage1_rg_stage_input_01_BITS_151_TO_145_28_ETC___d482,
	      IF_stage1_rg_stage_input_01_BITS_151_TO_145_28_ETC___d486,
	      alu_outputs_exc_code__h8321;
  reg [2 : 0] CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q19,
	      CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q20;
  reg [1 : 0] CASE_stage2_rg_stage2_BITS_103_TO_101_0_2_1_IF_ETC__q5,
	      CASE_stage2_rg_stage2_BITS_103_TO_101_0_2_1_IF_ETC__q6,
	      IF_NOT_stage1_rg_full_00_34_OR_NOT_stage1_rg_s_ETC___d571;
  reg CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q10,
      CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q11,
      CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q8,
      CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q9,
      IF_stage1_rg_stage_input_01_BITS_112_TO_110_30_ETC___d276,
      IF_stage1_rg_stage_input_01_BITS_112_TO_110_30_ETC___d370,
      IF_stage2_rg_stage2_7_BITS_103_TO_101_8_EQ_1_0_ETC___d141,
      IF_stage2_rg_stage2_7_BITS_103_TO_101_8_EQ_1_0_ETC___d150;
  wire [127 : 0] csr_regfile_read_csr_mcycle__0_MINUS_rg_start__ETC___d1647;
  wire [63 : 0] _theResult____h21590,
		cpi__h21592,
		cpifrac__h21593,
		delta_CPI_cycles__h21588,
		delta_CPI_instrs___1__h21625,
		delta_CPI_instrs__h21589,
		x__h21591;
  wire [31 : 0] IF_NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem__ETC___d1189,
		IF_csr_regfile_read_csr_rg_trap_instr_644_BITS_ETC___d1697,
		IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1041,
		IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1043,
		IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1045,
		IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1046,
		IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1048,
		IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1049,
		IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1050,
		IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1052,
		IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1053,
		IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1054,
		IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1056,
		IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1057,
		IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1058,
		IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1059,
		IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1060,
		IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1061,
		IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1062,
		IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1063,
		IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1064,
		IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg_p_ETC___d1190,
		IF_stage1_rg_stage_input_01_BITS_151_TO_145_28_ETC___d730,
		SEXT_stage1_rg_stage_input_01_BITS_87_TO_76_48___d599,
		_theResult_____1_fst__h8738,
		_theResult_____1_fst__h8773,
		_theResult____h5124,
		_theResult___snd__h9832,
		addr_of_b32___1__h17454,
		addr_of_b32___1__h20536,
		addr_of_b32___1__h28593,
		addr_of_b32__h17342,
		addr_of_b32__h20424,
		addr_of_b32__h28481,
		alu_outputs___1_addr__h7875,
		alu_outputs___1_addr__h8095,
		alu_outputs___1_val1__h7992,
		alu_outputs___1_val1__h8028,
		alu_outputs___1_val1__h8284,
		alu_outputs___1_val1__h8304,
		alu_outputs_cf_info_fallthru_PC__h9496,
		alu_outputs_cf_info_taken_PC__h9497,
		branch_target__h7852,
		d_instr__h15515,
		data_to_stage2_addr__h7710,
		eaddr__h8065,
		fall_through_pc__h7660,
		instr___1__h10068,
		instr__h10233,
		instr__h10378,
		instr__h10570,
		instr__h10765,
		instr__h10994,
		instr__h11336,
		instr__h11726,
		instr__h11842,
		instr__h11907,
		instr__h12224,
		instr__h12562,
		instr__h12746,
		instr__h12875,
		instr__h13312,
		instr__h13484,
		instr__h13657,
		instr__h13850,
		instr__h14043,
		instr__h14160,
		instr__h14338,
		instr__h14457,
		instr__h14552,
		instr__h14688,
		instr__h14824,
		instr__h14960,
		instr__h15298,
		instr_out___1__h15517,
		instr_out___1__h15539,
		next_pc___1__h9129,
		next_pc__h7661,
		next_pc__h7881,
		next_pc__h7908,
		next_pc__h9126,
		rd_val___1__h8726,
		rd_val___1__h8734,
		rd_val___1__h8741,
		rd_val___1__h8748,
		rd_val___1__h8755,
		rd_val___1__h8762,
		rd_val__h7562,
		rd_val__h7636,
		rd_val__h8035,
		rd_val__h8049,
		rd_val__h9729,
		rd_val__h9780,
		rd_val__h9802,
		rs1_val__h22063,
		rs1_val_bypassed__h4853,
		rs2_val_bypassed__h4859,
		trap_info_tval__h9330,
		val__h7564,
		val__h7638,
		value__h9376,
		x_out_cf_info_fallthru_PC__h9504,
		x_out_data_to_stage1_instr__h10032,
		x_out_data_to_stage2_val2__h7722,
		x_out_next_pc__h7677,
		y__h23012;
  wire [20 : 0] SEXT_stageD_rg_data_23_BIT_44_40_CONCAT_stageD_ETC___d892,
		decoded_instr_imm21_UJ__h19117,
		stage1_rg_stage_input_BITS_30_TO_10__q2;
  wire [19 : 0] imm20__h12614;
  wire [12 : 0] SEXT_stageD_rg_data_23_BIT_44_40_CONCAT_stageD_ETC___d921,
		decoded_instr_imm13_SB__h19115,
		stage1_rg_stage_input_BITS_63_TO_51__q1;
  wire [11 : 0] decoded_instr_imm12_S__h19114,
		imm12__h10234,
		imm12__h10571,
		imm12__h12486,
		imm12__h13110,
		imm12__h13325,
		imm12__h13521,
		imm12__h13866,
		offset__h10941,
		stage1_rg_stage_input_BITS_75_TO_64__q7,
		stage1_rg_stage_input_BITS_87_TO_76__q17;
  wire [9 : 0] decoded_instr_funct10__h19112,
	       nzimm10__h13108,
	       nzimm10__h13323;
  wire [8 : 0] offset__h11851;
  wire [7 : 0] offset__h10106;
  wire [6 : 0] offset__h10513;
  wire [5 : 0] imm6__h12484;
  wire [4 : 0] data_to_stage2_rd__h7709,
	       offset_BITS_4_TO_0___h10502,
	       offset_BITS_4_TO_0___h10933,
	       rd__h10573,
	       rs1__h10572,
	       shamt__h7979,
	       x_out_data_to_stage2_rd__h7719;
  wire [3 : 0] IF_NOT_stage1_rg_stage_input_01_BITS_112_TO_11_ETC___d438,
	       IF_rg_cur_priv_1_EQ_0b11_52_AND_stage1_rg_stag_ETC___d466,
	       IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489,
	       alu_outputs___1_exc_code__h8280,
	       cur_verbosity__h3333,
	       x_exc_code__h28843,
	       x_out_trap_info_exc_code__h9335;
  wire [2 : 0] IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d631;
  wire [1 : 0] IF_NOT_near_mem_dmem_valid__18_37_OR_NOT_near__ETC___d184,
	       IF_near_mem_dmem_valid__18_THEN_IF_near_mem_dm_ETC___d121,
	       IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127,
	       IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d188,
	       IF_stage2_rg_stage2_7_BITS_103_TO_101_8_EQ_3_0_ETC___d124,
	       new_epoch__h16878;
  wire IF_IF_stage1_rg_stage_input_01_BITS_151_TO_145_ETC___d813,
       IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1400,
       IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1403,
       IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1516,
       IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1557,
       IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1564,
       IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1576,
       IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1600,
       IF_NOT_stage1_rg_full_00_34_OR_NOT_stage1_rg_s_ETC___d1432,
       IF_NOT_stage1_rg_full_00_34_OR_NOT_stage1_rg_s_ETC___d1463,
       IF_stage1_rg_stage_input_01_BITS_139_TO_135_04_ETC___d265,
       IF_stage1_rg_stage_input_01_BITS_139_TO_135_04_ETC___d267,
       IF_stage1_rg_stage_input_01_BITS_139_TO_135_04_ETC___d269,
       IF_stage1_rg_stage_input_01_BITS_151_TO_145_28_ETC___d364,
       IF_stage1_rg_stage_input_01_BITS_151_TO_145_28_ETC___d375,
       IF_stage1_rg_stage_input_01_BITS_151_TO_145_28_ETC___d425,
       IF_stage1_rg_stage_input_01_BITS_151_TO_145_28_ETC___d427,
       IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d1385,
       IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d205,
       IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d207,
       IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d430,
       NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49,
       NOT_IF_stage2_rg_full_6_THEN_IF_stage2_rg_stag_ETC___d1393,
       NOT_IF_stage2_rg_full_6_THEN_IF_stage2_rg_stag_ETC___d378,
       NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1392,
       NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1396,
       NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1405,
       NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1407,
       NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1413,
       NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1435,
       NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1453,
       NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1460,
       NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1490,
       NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1513,
       NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1619,
       NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1172,
       NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1186,
       NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1215,
       NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1217,
       NOT_rg_next_pc_708_BITS_1_TO_0_709_EQ_0b0_710__ETC___d1717,
       NOT_soc_map_m_pc_reset_value__362_BITS_1_TO_0__ETC___d1376,
       NOT_stage1_rg_full_00_34_OR_stage1_rg_stage_in_ETC___d1428,
       NOT_stage1_rg_full_00_34_OR_stage1_rg_stage_in_ETC___d1430,
       NOT_stage1_rg_stage_input_01_BITS_112_TO_110_3_ETC___d306,
       NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d1761,
       NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d1765,
       NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d382,
       NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d562,
       NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d574,
       NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d578,
       NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d584,
       NOT_stageF_branch_predictor_predict_rsp_NOT_im_ETC___d1585,
       csr_regfile_RDY_server_reset_request_put__317__ETC___d1329,
       csr_regfile_RDY_server_reset_response_get__336_ETC___d1357,
       csr_regfile_interrupt_pending_rg_cur_priv_1_37_ETC___d1567,
       csr_regfile_interrupt_pending_rg_cur_priv_1_37_ETC___d1571,
       csr_regfile_interrupt_pending_rg_cur_priv_1_37_ETC___d1574,
       csr_regfile_interrupt_pending_rg_cur_priv_1_37_ETC___d1609,
       csr_regfile_read_misa__9_BIT_2_28_AND_stageD_r_ETC___d906,
       csr_regfile_read_misa__9_BIT_2_28_AND_stageD_r_ETC___d912,
       f_reset_rsps_i_notFull__342_AND_NOT_rg_run_on__ETC___d1351,
       imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1204,
       imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1208,
       imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1211,
       imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d1347,
       imem_rg_pc_BITS_31_TO_2_0_EQ_imem_rg_cache_add_ETC___d1164,
       imem_rg_pc_BITS_31_TO_2_0_EQ_near_mem_imem_pc__ETC___d13,
       near_mem_imem_pc__1_EQ_imem_rg_pc_PLUS_2_166___d1167,
       near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d1313,
       rg_cur_priv_1_EQ_0b11_52_OR_rg_cur_priv_1_EQ_0_ETC___d464,
       rg_state_0_EQ_12_7_AND_csr_regfile_wfi_resume__ETC___d1752,
       rg_state_0_EQ_3_415_AND_NOT_csr_regfile_interr_ETC___d1623,
       rg_state_0_EQ_3_415_AND_NOT_csr_regfile_interr_ETC___d1732,
       rg_state_0_EQ_3_415_AND_NOT_csr_regfile_interr_ETC___d1741,
       rg_state_0_EQ_3_415_AND_stage3_rg_full_7_OR_NO_ETC___d1425,
       rg_state_0_EQ_5_756_AND_NOT_stageF_rg_full_194_ETC___d1757,
       rg_state_0_EQ_8_705_AND_NOT_stageF_rg_full_194_ETC___d1706,
       rg_trap_info_633_BITS_67_TO_36_634_EQ_csr_regf_ETC___d1643,
       stage1_rg_full_00_AND_NOT_stage1_rg_stage_inpu_ETC___d433,
       stage1_rg_stage_input_01_BITS_112_TO_110_30_EQ_ETC___d398,
       stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d1388,
       stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203,
       stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d221,
       stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d766,
       stage3_rg_full_7_OR_NOT_IF_stage2_rg_full_6_TH_ETC___d1423,
       stageF_rg_full_194_AND_near_mem_imem_valid_AND_ETC___d1226,
       stageF_rg_full_194_AND_near_mem_imem_valid_AND_ETC___d1232,
       stageF_rg_full_194_AND_near_mem_imem_valid_AND_ETC___d1236,
       stageF_rg_full_194_AND_near_mem_imem_valid_AND_ETC___d1240,
       stageF_rg_full_194_AND_near_mem_imem_valid_AND_ETC___d1244,
       stageF_rg_full_194_AND_near_mem_imem_valid_AND_ETC___d1248,
       stageF_rg_full_194_AND_near_mem_imem_valid_AND_ETC___d1252,
       stageF_rg_full_194_AND_near_mem_imem_valid_AND_ETC___d1256,
       stageF_rg_full_194_AND_near_mem_imem_valid_AND_ETC___d1260,
       stageF_rg_full_194_AND_near_mem_imem_valid_AND_ETC___d1264,
       stageF_rg_full_194_AND_near_mem_imem_valid_AND_ETC___d1268,
       stageF_rg_full_194_AND_near_mem_imem_valid_AND_ETC___d1272,
       stageF_rg_full_194_AND_near_mem_imem_valid_AND_ETC___d1276,
       stageF_rg_full_194_AND_near_mem_imem_valid_AND_ETC___d1280,
       stageF_rg_full_194_AND_near_mem_imem_valid_AND_ETC___d1284;

  // action method hart0_server_reset_request_put
  assign RDY_hart0_server_reset_request_put = f_reset_reqs$FULL_N ;
  assign CAN_FIRE_hart0_server_reset_request_put = f_reset_reqs$FULL_N ;
  assign WILL_FIRE_hart0_server_reset_request_put =
	     EN_hart0_server_reset_request_put ;

  // actionvalue method hart0_server_reset_response_get
  assign hart0_server_reset_response_get = f_reset_rsps$D_OUT ;
  assign RDY_hart0_server_reset_response_get = f_reset_rsps$EMPTY_N ;
  assign CAN_FIRE_hart0_server_reset_response_get = f_reset_rsps$EMPTY_N ;
  assign WILL_FIRE_hart0_server_reset_response_get =
	     EN_hart0_server_reset_response_get ;

  // value method imem_master_m_awvalid
  assign imem_master_awvalid = near_mem$imem_master_awvalid ;

  // value method imem_master_m_awid
  assign imem_master_awid = near_mem$imem_master_awid ;

  // value method imem_master_m_awaddr
  assign imem_master_awaddr = near_mem$imem_master_awaddr ;

  // value method imem_master_m_awlen
  assign imem_master_awlen = near_mem$imem_master_awlen ;

  // value method imem_master_m_awsize
  assign imem_master_awsize = near_mem$imem_master_awsize ;

  // value method imem_master_m_awburst
  assign imem_master_awburst = near_mem$imem_master_awburst ;

  // value method imem_master_m_awlock
  assign imem_master_awlock = near_mem$imem_master_awlock ;

  // value method imem_master_m_awcache
  assign imem_master_awcache = near_mem$imem_master_awcache ;

  // value method imem_master_m_awprot
  assign imem_master_awprot = near_mem$imem_master_awprot ;

  // value method imem_master_m_awqos
  assign imem_master_awqos = near_mem$imem_master_awqos ;

  // value method imem_master_m_awregion
  assign imem_master_awregion = near_mem$imem_master_awregion ;

  // action method imem_master_m_awready
  assign CAN_FIRE_imem_master_m_awready = 1'd1 ;
  assign WILL_FIRE_imem_master_m_awready = 1'd1 ;

  // value method imem_master_m_wvalid
  assign imem_master_wvalid = near_mem$imem_master_wvalid ;

  // value method imem_master_m_wdata
  assign imem_master_wdata = near_mem$imem_master_wdata ;

  // value method imem_master_m_wstrb
  assign imem_master_wstrb = near_mem$imem_master_wstrb ;

  // value method imem_master_m_wlast
  assign imem_master_wlast = near_mem$imem_master_wlast ;

  // action method imem_master_m_wready
  assign CAN_FIRE_imem_master_m_wready = 1'd1 ;
  assign WILL_FIRE_imem_master_m_wready = 1'd1 ;

  // action method imem_master_m_bvalid
  assign CAN_FIRE_imem_master_m_bvalid = 1'd1 ;
  assign WILL_FIRE_imem_master_m_bvalid = 1'd1 ;

  // value method imem_master_m_bready
  assign imem_master_bready = near_mem$imem_master_bready ;

  // value method imem_master_m_arvalid
  assign imem_master_arvalid = near_mem$imem_master_arvalid ;

  // value method imem_master_m_arid
  assign imem_master_arid = near_mem$imem_master_arid ;

  // value method imem_master_m_araddr
  assign imem_master_araddr = near_mem$imem_master_araddr ;

  // value method imem_master_m_arlen
  assign imem_master_arlen = near_mem$imem_master_arlen ;

  // value method imem_master_m_arsize
  assign imem_master_arsize = near_mem$imem_master_arsize ;

  // value method imem_master_m_arburst
  assign imem_master_arburst = near_mem$imem_master_arburst ;

  // value method imem_master_m_arlock
  assign imem_master_arlock = near_mem$imem_master_arlock ;

  // value method imem_master_m_arcache
  assign imem_master_arcache = near_mem$imem_master_arcache ;

  // value method imem_master_m_arprot
  assign imem_master_arprot = near_mem$imem_master_arprot ;

  // value method imem_master_m_arqos
  assign imem_master_arqos = near_mem$imem_master_arqos ;

  // value method imem_master_m_arregion
  assign imem_master_arregion = near_mem$imem_master_arregion ;

  // action method imem_master_m_arready
  assign CAN_FIRE_imem_master_m_arready = 1'd1 ;
  assign WILL_FIRE_imem_master_m_arready = 1'd1 ;

  // action method imem_master_m_rvalid
  assign CAN_FIRE_imem_master_m_rvalid = 1'd1 ;
  assign WILL_FIRE_imem_master_m_rvalid = 1'd1 ;

  // value method imem_master_m_rready
  assign imem_master_rready = near_mem$imem_master_rready ;

  // value method dmem_master_m_awvalid
  assign dmem_master_awvalid = near_mem$dmem_master_awvalid ;

  // value method dmem_master_m_awid
  assign dmem_master_awid = near_mem$dmem_master_awid ;

  // value method dmem_master_m_awaddr
  assign dmem_master_awaddr = near_mem$dmem_master_awaddr ;

  // value method dmem_master_m_awlen
  assign dmem_master_awlen = near_mem$dmem_master_awlen ;

  // value method dmem_master_m_awsize
  assign dmem_master_awsize = near_mem$dmem_master_awsize ;

  // value method dmem_master_m_awburst
  assign dmem_master_awburst = near_mem$dmem_master_awburst ;

  // value method dmem_master_m_awlock
  assign dmem_master_awlock = near_mem$dmem_master_awlock ;

  // value method dmem_master_m_awcache
  assign dmem_master_awcache = near_mem$dmem_master_awcache ;

  // value method dmem_master_m_awprot
  assign dmem_master_awprot = near_mem$dmem_master_awprot ;

  // value method dmem_master_m_awqos
  assign dmem_master_awqos = near_mem$dmem_master_awqos ;

  // value method dmem_master_m_awregion
  assign dmem_master_awregion = near_mem$dmem_master_awregion ;

  // action method dmem_master_m_awready
  assign CAN_FIRE_dmem_master_m_awready = 1'd1 ;
  assign WILL_FIRE_dmem_master_m_awready = 1'd1 ;

  // value method dmem_master_m_wvalid
  assign dmem_master_wvalid = near_mem$dmem_master_wvalid ;

  // value method dmem_master_m_wdata
  assign dmem_master_wdata = near_mem$dmem_master_wdata ;

  // value method dmem_master_m_wstrb
  assign dmem_master_wstrb = near_mem$dmem_master_wstrb ;

  // value method dmem_master_m_wlast
  assign dmem_master_wlast = near_mem$dmem_master_wlast ;

  // action method dmem_master_m_wready
  assign CAN_FIRE_dmem_master_m_wready = 1'd1 ;
  assign WILL_FIRE_dmem_master_m_wready = 1'd1 ;

  // action method dmem_master_m_bvalid
  assign CAN_FIRE_dmem_master_m_bvalid = 1'd1 ;
  assign WILL_FIRE_dmem_master_m_bvalid = 1'd1 ;

  // value method dmem_master_m_bready
  assign dmem_master_bready = near_mem$dmem_master_bready ;

  // value method dmem_master_m_arvalid
  assign dmem_master_arvalid = near_mem$dmem_master_arvalid ;

  // value method dmem_master_m_arid
  assign dmem_master_arid = near_mem$dmem_master_arid ;

  // value method dmem_master_m_araddr
  assign dmem_master_araddr = near_mem$dmem_master_araddr ;

  // value method dmem_master_m_arlen
  assign dmem_master_arlen = near_mem$dmem_master_arlen ;

  // value method dmem_master_m_arsize
  assign dmem_master_arsize = near_mem$dmem_master_arsize ;

  // value method dmem_master_m_arburst
  assign dmem_master_arburst = near_mem$dmem_master_arburst ;

  // value method dmem_master_m_arlock
  assign dmem_master_arlock = near_mem$dmem_master_arlock ;

  // value method dmem_master_m_arcache
  assign dmem_master_arcache = near_mem$dmem_master_arcache ;

  // value method dmem_master_m_arprot
  assign dmem_master_arprot = near_mem$dmem_master_arprot ;

  // value method dmem_master_m_arqos
  assign dmem_master_arqos = near_mem$dmem_master_arqos ;

  // value method dmem_master_m_arregion
  assign dmem_master_arregion = near_mem$dmem_master_arregion ;

  // action method dmem_master_m_arready
  assign CAN_FIRE_dmem_master_m_arready = 1'd1 ;
  assign WILL_FIRE_dmem_master_m_arready = 1'd1 ;

  // action method dmem_master_m_rvalid
  assign CAN_FIRE_dmem_master_m_rvalid = 1'd1 ;
  assign WILL_FIRE_dmem_master_m_rvalid = 1'd1 ;

  // value method dmem_master_m_rready
  assign dmem_master_rready = near_mem$dmem_master_rready ;

  // action method m_external_interrupt_req
  assign CAN_FIRE_m_external_interrupt_req = 1'd1 ;
  assign WILL_FIRE_m_external_interrupt_req = 1'd1 ;

  // action method s_external_interrupt_req
  assign CAN_FIRE_s_external_interrupt_req = 1'd1 ;
  assign WILL_FIRE_s_external_interrupt_req = 1'd1 ;

  // action method software_interrupt_req
  assign CAN_FIRE_software_interrupt_req = 1'd1 ;
  assign WILL_FIRE_software_interrupt_req = 1'd1 ;

  // action method timer_interrupt_req
  assign CAN_FIRE_timer_interrupt_req = 1'd1 ;
  assign WILL_FIRE_timer_interrupt_req = 1'd1 ;

  // action method nmi_req
  assign CAN_FIRE_nmi_req = 1'd1 ;
  assign WILL_FIRE_nmi_req = 1'd1 ;

  // action method set_verbosity
  assign RDY_set_verbosity = 1'd1 ;
  assign CAN_FIRE_set_verbosity = 1'd1 ;
  assign WILL_FIRE_set_verbosity = EN_set_verbosity ;

  // action method set_watch_tohost
  assign RDY_set_watch_tohost = 1'd1 ;
  assign CAN_FIRE_set_watch_tohost = 1'd1 ;
  assign WILL_FIRE_set_watch_tohost = EN_set_watch_tohost ;

  // submodule csr_regfile
  mkCSR_RegFile csr_regfile(.CLK(CLK),
			    .RST_N(RST_N),
			    .access_permitted_1_csr_addr(csr_regfile$access_permitted_1_csr_addr),
			    .access_permitted_1_priv(csr_regfile$access_permitted_1_priv),
			    .access_permitted_1_read_not_write(csr_regfile$access_permitted_1_read_not_write),
			    .access_permitted_2_csr_addr(csr_regfile$access_permitted_2_csr_addr),
			    .access_permitted_2_priv(csr_regfile$access_permitted_2_priv),
			    .access_permitted_2_read_not_write(csr_regfile$access_permitted_2_read_not_write),
			    .csr_counter_read_fault_csr_addr(csr_regfile$csr_counter_read_fault_csr_addr),
			    .csr_counter_read_fault_priv(csr_regfile$csr_counter_read_fault_priv),
			    .csr_ret_actions_from_priv(csr_regfile$csr_ret_actions_from_priv),
			    .csr_trap_actions_exc_code(csr_regfile$csr_trap_actions_exc_code),
			    .csr_trap_actions_from_priv(csr_regfile$csr_trap_actions_from_priv),
			    .csr_trap_actions_interrupt(csr_regfile$csr_trap_actions_interrupt),
			    .csr_trap_actions_nmi(csr_regfile$csr_trap_actions_nmi),
			    .csr_trap_actions_pc(csr_regfile$csr_trap_actions_pc),
			    .csr_trap_actions_xtval(csr_regfile$csr_trap_actions_xtval),
			    .interrupt_pending_cur_priv(csr_regfile$interrupt_pending_cur_priv),
			    .m_external_interrupt_req_set_not_clear(csr_regfile$m_external_interrupt_req_set_not_clear),
			    .mav_csr_write_csr_addr(csr_regfile$mav_csr_write_csr_addr),
			    .mav_csr_write_word(csr_regfile$mav_csr_write_word),
			    .mav_read_csr_csr_addr(csr_regfile$mav_read_csr_csr_addr),
			    .nmi_req_set_not_clear(csr_regfile$nmi_req_set_not_clear),
			    .read_csr_csr_addr(csr_regfile$read_csr_csr_addr),
			    .read_csr_port2_csr_addr(csr_regfile$read_csr_port2_csr_addr),
			    .s_external_interrupt_req_set_not_clear(csr_regfile$s_external_interrupt_req_set_not_clear),
			    .software_interrupt_req_set_not_clear(csr_regfile$software_interrupt_req_set_not_clear),
			    .timer_interrupt_req_set_not_clear(csr_regfile$timer_interrupt_req_set_not_clear),
			    .EN_server_reset_request_put(csr_regfile$EN_server_reset_request_put),
			    .EN_server_reset_response_get(csr_regfile$EN_server_reset_response_get),
			    .EN_mav_read_csr(csr_regfile$EN_mav_read_csr),
			    .EN_mav_csr_write(csr_regfile$EN_mav_csr_write),
			    .EN_csr_trap_actions(csr_regfile$EN_csr_trap_actions),
			    .EN_csr_ret_actions(csr_regfile$EN_csr_ret_actions),
			    .EN_csr_minstret_incr(csr_regfile$EN_csr_minstret_incr),
			    .EN_debug(csr_regfile$EN_debug),
			    .RDY_server_reset_request_put(csr_regfile$RDY_server_reset_request_put),
			    .RDY_server_reset_response_get(csr_regfile$RDY_server_reset_response_get),
			    .read_csr(csr_regfile$read_csr),
			    .read_csr_port2(),
			    .mav_read_csr(),
			    .mav_csr_write(),
			    .read_misa(csr_regfile$read_misa),
			    .read_mstatus(csr_regfile$read_mstatus),
			    .read_ustatus(),
			    .read_satp(csr_regfile$read_satp),
			    .csr_trap_actions(csr_regfile$csr_trap_actions),
			    .RDY_csr_trap_actions(),
			    .csr_ret_actions(csr_regfile$csr_ret_actions),
			    .RDY_csr_ret_actions(),
			    .read_csr_minstret(csr_regfile$read_csr_minstret),
			    .read_csr_mcycle(csr_regfile$read_csr_mcycle),
			    .read_csr_mtime(),
			    .access_permitted_1(csr_regfile$access_permitted_1),
			    .access_permitted_2(csr_regfile$access_permitted_2),
			    .csr_counter_read_fault(),
			    .csr_mip_read(),
			    .interrupt_pending(csr_regfile$interrupt_pending),
			    .wfi_resume(csr_regfile$wfi_resume),
			    .nmi_pending(csr_regfile$nmi_pending),
			    .RDY_debug());

  // submodule f_reset_reqs
  FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_reqs(.RST(RST_N),
						       .CLK(CLK),
						       .D_IN(f_reset_reqs$D_IN),
						       .ENQ(f_reset_reqs$ENQ),
						       .DEQ(f_reset_reqs$DEQ),
						       .CLR(f_reset_reqs$CLR),
						       .D_OUT(f_reset_reqs$D_OUT),
						       .FULL_N(f_reset_reqs$FULL_N),
						       .EMPTY_N(f_reset_reqs$EMPTY_N));

  // submodule f_reset_rsps
  FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_rsps(.RST(RST_N),
						       .CLK(CLK),
						       .D_IN(f_reset_rsps$D_IN),
						       .ENQ(f_reset_rsps$ENQ),
						       .DEQ(f_reset_rsps$DEQ),
						       .CLR(f_reset_rsps$CLR),
						       .D_OUT(f_reset_rsps$D_OUT),
						       .FULL_N(f_reset_rsps$FULL_N),
						       .EMPTY_N(f_reset_rsps$EMPTY_N));

  // submodule gpr_regfile
  mkGPR_RegFile gpr_regfile(.CLK(CLK),
			    .RST_N(RST_N),
			    .read_rs1_port2_rs1(gpr_regfile$read_rs1_port2_rs1),
			    .read_rs1_rs1(gpr_regfile$read_rs1_rs1),
			    .read_rs2_rs2(gpr_regfile$read_rs2_rs2),
			    .write_rd_rd(gpr_regfile$write_rd_rd),
			    .write_rd_rd_val(gpr_regfile$write_rd_rd_val),
			    .EN_server_reset_request_put(gpr_regfile$EN_server_reset_request_put),
			    .EN_server_reset_response_get(gpr_regfile$EN_server_reset_response_get),
			    .EN_write_rd(gpr_regfile$EN_write_rd),
			    .RDY_server_reset_request_put(gpr_regfile$RDY_server_reset_request_put),
			    .RDY_server_reset_response_get(gpr_regfile$RDY_server_reset_response_get),
			    .read_rs1(gpr_regfile$read_rs1),
			    .read_rs1_port2(),
			    .read_rs2(gpr_regfile$read_rs2));

  // submodule near_mem
  mkNear_Mem near_mem(.CLK(CLK),
		      .RST_N(RST_N),
		      .dmem_master_arready(near_mem$dmem_master_arready),
		      .dmem_master_awready(near_mem$dmem_master_awready),
		      .dmem_master_bid(near_mem$dmem_master_bid),
		      .dmem_master_bresp(near_mem$dmem_master_bresp),
		      .dmem_master_bvalid(near_mem$dmem_master_bvalid),
		      .dmem_master_rdata(near_mem$dmem_master_rdata),
		      .dmem_master_rid(near_mem$dmem_master_rid),
		      .dmem_master_rlast(near_mem$dmem_master_rlast),
		      .dmem_master_rresp(near_mem$dmem_master_rresp),
		      .dmem_master_rvalid(near_mem$dmem_master_rvalid),
		      .dmem_master_wready(near_mem$dmem_master_wready),
		      .dmem_req_addr(near_mem$dmem_req_addr),
		      .dmem_req_amo_funct7(near_mem$dmem_req_amo_funct7),
		      .dmem_req_f3(near_mem$dmem_req_f3),
		      .dmem_req_mstatus_MXR(near_mem$dmem_req_mstatus_MXR),
		      .dmem_req_op(near_mem$dmem_req_op),
		      .dmem_req_priv(near_mem$dmem_req_priv),
		      .dmem_req_satp(near_mem$dmem_req_satp),
		      .dmem_req_sstatus_SUM(near_mem$dmem_req_sstatus_SUM),
		      .dmem_req_store_value(near_mem$dmem_req_store_value),
		      .imem_master_arready(near_mem$imem_master_arready),
		      .imem_master_awready(near_mem$imem_master_awready),
		      .imem_master_bid(near_mem$imem_master_bid),
		      .imem_master_bresp(near_mem$imem_master_bresp),
		      .imem_master_bvalid(near_mem$imem_master_bvalid),
		      .imem_master_rdata(near_mem$imem_master_rdata),
		      .imem_master_rid(near_mem$imem_master_rid),
		      .imem_master_rlast(near_mem$imem_master_rlast),
		      .imem_master_rresp(near_mem$imem_master_rresp),
		      .imem_master_rvalid(near_mem$imem_master_rvalid),
		      .imem_master_wready(near_mem$imem_master_wready),
		      .imem_req_addr(near_mem$imem_req_addr),
		      .imem_req_f3(near_mem$imem_req_f3),
		      .imem_req_mstatus_MXR(near_mem$imem_req_mstatus_MXR),
		      .imem_req_priv(near_mem$imem_req_priv),
		      .imem_req_satp(near_mem$imem_req_satp),
		      .imem_req_sstatus_SUM(near_mem$imem_req_sstatus_SUM),
		      .server_fence_request_put(near_mem$server_fence_request_put),
		      .set_watch_tohost_tohost_addr(near_mem$set_watch_tohost_tohost_addr),
		      .set_watch_tohost_watch_tohost(near_mem$set_watch_tohost_watch_tohost),
		      .EN_server_reset_request_put(near_mem$EN_server_reset_request_put),
		      .EN_server_reset_response_get(near_mem$EN_server_reset_response_get),
		      .EN_imem_req(near_mem$EN_imem_req),
		      .EN_dmem_req(near_mem$EN_dmem_req),
		      .EN_server_fence_i_request_put(near_mem$EN_server_fence_i_request_put),
		      .EN_server_fence_i_response_get(near_mem$EN_server_fence_i_response_get),
		      .EN_server_fence_request_put(near_mem$EN_server_fence_request_put),
		      .EN_server_fence_response_get(near_mem$EN_server_fence_response_get),
		      .EN_set_watch_tohost(near_mem$EN_set_watch_tohost),
		      .RDY_server_reset_request_put(near_mem$RDY_server_reset_request_put),
		      .RDY_server_reset_response_get(near_mem$RDY_server_reset_response_get),
		      .imem_valid(near_mem$imem_valid),
		      .imem_is_i32_not_i16(near_mem$imem_is_i32_not_i16),
		      .imem_pc(near_mem$imem_pc),
		      .imem_instr(near_mem$imem_instr),
		      .imem_exc(near_mem$imem_exc),
		      .imem_exc_code(near_mem$imem_exc_code),
		      .imem_tval(),
		      .imem_master_awvalid(near_mem$imem_master_awvalid),
		      .imem_master_awid(near_mem$imem_master_awid),
		      .imem_master_awaddr(near_mem$imem_master_awaddr),
		      .imem_master_awlen(near_mem$imem_master_awlen),
		      .imem_master_awsize(near_mem$imem_master_awsize),
		      .imem_master_awburst(near_mem$imem_master_awburst),
		      .imem_master_awlock(near_mem$imem_master_awlock),
		      .imem_master_awcache(near_mem$imem_master_awcache),
		      .imem_master_awprot(near_mem$imem_master_awprot),
		      .imem_master_awqos(near_mem$imem_master_awqos),
		      .imem_master_awregion(near_mem$imem_master_awregion),
		      .imem_master_wvalid(near_mem$imem_master_wvalid),
		      .imem_master_wdata(near_mem$imem_master_wdata),
		      .imem_master_wstrb(near_mem$imem_master_wstrb),
		      .imem_master_wlast(near_mem$imem_master_wlast),
		      .imem_master_bready(near_mem$imem_master_bready),
		      .imem_master_arvalid(near_mem$imem_master_arvalid),
		      .imem_master_arid(near_mem$imem_master_arid),
		      .imem_master_araddr(near_mem$imem_master_araddr),
		      .imem_master_arlen(near_mem$imem_master_arlen),
		      .imem_master_arsize(near_mem$imem_master_arsize),
		      .imem_master_arburst(near_mem$imem_master_arburst),
		      .imem_master_arlock(near_mem$imem_master_arlock),
		      .imem_master_arcache(near_mem$imem_master_arcache),
		      .imem_master_arprot(near_mem$imem_master_arprot),
		      .imem_master_arqos(near_mem$imem_master_arqos),
		      .imem_master_arregion(near_mem$imem_master_arregion),
		      .imem_master_rready(near_mem$imem_master_rready),
		      .dmem_valid(near_mem$dmem_valid),
		      .dmem_word64(near_mem$dmem_word64),
		      .dmem_st_amo_val(),
		      .dmem_exc(near_mem$dmem_exc),
		      .dmem_exc_code(near_mem$dmem_exc_code),
		      .dmem_master_awvalid(near_mem$dmem_master_awvalid),
		      .dmem_master_awid(near_mem$dmem_master_awid),
		      .dmem_master_awaddr(near_mem$dmem_master_awaddr),
		      .dmem_master_awlen(near_mem$dmem_master_awlen),
		      .dmem_master_awsize(near_mem$dmem_master_awsize),
		      .dmem_master_awburst(near_mem$dmem_master_awburst),
		      .dmem_master_awlock(near_mem$dmem_master_awlock),
		      .dmem_master_awcache(near_mem$dmem_master_awcache),
		      .dmem_master_awprot(near_mem$dmem_master_awprot),
		      .dmem_master_awqos(near_mem$dmem_master_awqos),
		      .dmem_master_awregion(near_mem$dmem_master_awregion),
		      .dmem_master_wvalid(near_mem$dmem_master_wvalid),
		      .dmem_master_wdata(near_mem$dmem_master_wdata),
		      .dmem_master_wstrb(near_mem$dmem_master_wstrb),
		      .dmem_master_wlast(near_mem$dmem_master_wlast),
		      .dmem_master_bready(near_mem$dmem_master_bready),
		      .dmem_master_arvalid(near_mem$dmem_master_arvalid),
		      .dmem_master_arid(near_mem$dmem_master_arid),
		      .dmem_master_araddr(near_mem$dmem_master_araddr),
		      .dmem_master_arlen(near_mem$dmem_master_arlen),
		      .dmem_master_arsize(near_mem$dmem_master_arsize),
		      .dmem_master_arburst(near_mem$dmem_master_arburst),
		      .dmem_master_arlock(near_mem$dmem_master_arlock),
		      .dmem_master_arcache(near_mem$dmem_master_arcache),
		      .dmem_master_arprot(near_mem$dmem_master_arprot),
		      .dmem_master_arqos(near_mem$dmem_master_arqos),
		      .dmem_master_arregion(near_mem$dmem_master_arregion),
		      .dmem_master_rready(near_mem$dmem_master_rready),
		      .RDY_server_fence_i_request_put(near_mem$RDY_server_fence_i_request_put),
		      .RDY_server_fence_i_response_get(near_mem$RDY_server_fence_i_response_get),
		      .RDY_server_fence_request_put(near_mem$RDY_server_fence_request_put),
		      .RDY_server_fence_response_get(near_mem$RDY_server_fence_response_get),
		      .RDY_set_watch_tohost());

  // submodule soc_map
  mkSoC_Map soc_map(.CLK(CLK),
		    .RST_N(RST_N),
		    .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr),
		    .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr),
		    .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr),
		    .m_near_mem_io_addr_base(),
		    .m_near_mem_io_addr_size(),
		    .m_near_mem_io_addr_lim(),
		    .m_plic_addr_base(),
		    .m_plic_addr_size(),
		    .m_plic_addr_lim(),
		    .m_uart0_addr_base(),
		    .m_uart0_addr_size(),
		    .m_uart0_addr_lim(),
		    .m_boot_rom_addr_base(),
		    .m_boot_rom_addr_size(),
		    .m_boot_rom_addr_lim(),
		    .m_mem0_controller_addr_base(),
		    .m_mem0_controller_addr_size(),
		    .m_mem0_controller_addr_lim(),
		    .m_tcm_addr_base(),
		    .m_tcm_addr_size(),
		    .m_tcm_addr_lim(),
		    .m_is_mem_addr(),
		    .m_is_IO_addr(),
		    .m_is_near_mem_IO_addr(),
		    .m_pc_reset_value(soc_map$m_pc_reset_value),
		    .m_mtvec_reset_value(),
		    .m_nmivec_reset_value());

  // submodule stage1_f_reset_reqs
  FIFO20 #(.guarded(32'd1)) stage1_f_reset_reqs(.RST(RST_N),
						.CLK(CLK),
						.ENQ(stage1_f_reset_reqs$ENQ),
						.DEQ(stage1_f_reset_reqs$DEQ),
						.CLR(stage1_f_reset_reqs$CLR),
						.FULL_N(stage1_f_reset_reqs$FULL_N),
						.EMPTY_N(stage1_f_reset_reqs$EMPTY_N));

  // submodule stage1_f_reset_rsps
  FIFO20 #(.guarded(32'd1)) stage1_f_reset_rsps(.RST(RST_N),
						.CLK(CLK),
						.ENQ(stage1_f_reset_rsps$ENQ),
						.DEQ(stage1_f_reset_rsps$DEQ),
						.CLR(stage1_f_reset_rsps$CLR),
						.FULL_N(stage1_f_reset_rsps$FULL_N),
						.EMPTY_N(stage1_f_reset_rsps$EMPTY_N));

  // submodule stage2_f_reset_reqs
  FIFO20 #(.guarded(32'd1)) stage2_f_reset_reqs(.RST(RST_N),
						.CLK(CLK),
						.ENQ(stage2_f_reset_reqs$ENQ),
						.DEQ(stage2_f_reset_reqs$DEQ),
						.CLR(stage2_f_reset_reqs$CLR),
						.FULL_N(stage2_f_reset_reqs$FULL_N),
						.EMPTY_N(stage2_f_reset_reqs$EMPTY_N));

  // submodule stage2_f_reset_rsps
  FIFO20 #(.guarded(32'd1)) stage2_f_reset_rsps(.RST(RST_N),
						.CLK(CLK),
						.ENQ(stage2_f_reset_rsps$ENQ),
						.DEQ(stage2_f_reset_rsps$DEQ),
						.CLR(stage2_f_reset_rsps$CLR),
						.FULL_N(stage2_f_reset_rsps$FULL_N),
						.EMPTY_N(stage2_f_reset_rsps$EMPTY_N));

  // submodule stage2_mbox
  mkRISCV_MBox stage2_mbox(.CLK(CLK),
			   .RST_N(RST_N),
			   .req_f3(stage2_mbox$req_f3),
			   .req_is_OP_not_OP_32(stage2_mbox$req_is_OP_not_OP_32),
			   .req_v1(stage2_mbox$req_v1),
			   .req_v2(stage2_mbox$req_v2),
			   .set_verbosity_verbosity(stage2_mbox$set_verbosity_verbosity),
			   .EN_set_verbosity(stage2_mbox$EN_set_verbosity),
			   .EN_req_reset(stage2_mbox$EN_req_reset),
			   .EN_rsp_reset(stage2_mbox$EN_rsp_reset),
			   .EN_req(stage2_mbox$EN_req),
			   .RDY_set_verbosity(),
			   .RDY_req_reset(),
			   .RDY_rsp_reset(),
			   .valid(stage2_mbox$valid),
			   .word(stage2_mbox$word));

  // submodule stage3_f_reset_reqs
  FIFO20 #(.guarded(32'd1)) stage3_f_reset_reqs(.RST(RST_N),
						.CLK(CLK),
						.ENQ(stage3_f_reset_reqs$ENQ),
						.DEQ(stage3_f_reset_reqs$DEQ),
						.CLR(stage3_f_reset_reqs$CLR),
						.FULL_N(stage3_f_reset_reqs$FULL_N),
						.EMPTY_N(stage3_f_reset_reqs$EMPTY_N));

  // submodule stage3_f_reset_rsps
  FIFO20 #(.guarded(32'd1)) stage3_f_reset_rsps(.RST(RST_N),
						.CLK(CLK),
						.ENQ(stage3_f_reset_rsps$ENQ),
						.DEQ(stage3_f_reset_rsps$DEQ),
						.CLR(stage3_f_reset_rsps$CLR),
						.FULL_N(stage3_f_reset_rsps$FULL_N),
						.EMPTY_N(stage3_f_reset_rsps$EMPTY_N));

  // submodule stageD_f_reset_reqs
  FIFO20 #(.guarded(32'd1)) stageD_f_reset_reqs(.RST(RST_N),
						.CLK(CLK),
						.ENQ(stageD_f_reset_reqs$ENQ),
						.DEQ(stageD_f_reset_reqs$DEQ),
						.CLR(stageD_f_reset_reqs$CLR),
						.FULL_N(stageD_f_reset_reqs$FULL_N),
						.EMPTY_N(stageD_f_reset_reqs$EMPTY_N));

  // submodule stageD_f_reset_rsps
  FIFO20 #(.guarded(32'd1)) stageD_f_reset_rsps(.RST(RST_N),
						.CLK(CLK),
						.ENQ(stageD_f_reset_rsps$ENQ),
						.DEQ(stageD_f_reset_rsps$DEQ),
						.CLR(stageD_f_reset_rsps$CLR),
						.FULL_N(stageD_f_reset_rsps$FULL_N),
						.EMPTY_N(stageD_f_reset_rsps$EMPTY_N));

  // submodule stageF_branch_predictor
  mkBranch_Predictor stageF_branch_predictor(.CLK(CLK),
					     .RST_N(RST_N),
					     .bp_train_cf_info(stageF_branch_predictor$bp_train_cf_info),
					     .bp_train_instr(stageF_branch_predictor$bp_train_instr),
					     .bp_train_is_i32_not_i16(stageF_branch_predictor$bp_train_is_i32_not_i16),
					     .bp_train_pc(stageF_branch_predictor$bp_train_pc),
					     .predict_req_pc(stageF_branch_predictor$predict_req_pc),
					     .predict_rsp_instr(stageF_branch_predictor$predict_rsp_instr),
					     .predict_rsp_is_i32_not_i16(stageF_branch_predictor$predict_rsp_is_i32_not_i16),
					     .EN_reset(stageF_branch_predictor$EN_reset),
					     .EN_predict_req(stageF_branch_predictor$EN_predict_req),
					     .EN_bp_train(stageF_branch_predictor$EN_bp_train),
					     .RDY_reset(),
					     .RDY_predict_req(stageF_branch_predictor$RDY_predict_req),
					     .predict_rsp(stageF_branch_predictor$predict_rsp),
					     .RDY_bp_train());

  // submodule stageF_f_reset_reqs
  FIFO20 #(.guarded(32'd1)) stageF_f_reset_reqs(.RST(RST_N),
						.CLK(CLK),
						.ENQ(stageF_f_reset_reqs$ENQ),
						.DEQ(stageF_f_reset_reqs$DEQ),
						.CLR(stageF_f_reset_reqs$CLR),
						.FULL_N(stageF_f_reset_reqs$FULL_N),
						.EMPTY_N(stageF_f_reset_reqs$EMPTY_N));

  // submodule stageF_f_reset_rsps
  FIFO20 #(.guarded(32'd1)) stageF_f_reset_rsps(.RST(RST_N),
						.CLK(CLK),
						.ENQ(stageF_f_reset_rsps$ENQ),
						.DEQ(stageF_f_reset_rsps$DEQ),
						.CLR(stageF_f_reset_rsps$CLR),
						.FULL_N(stageF_f_reset_rsps$FULL_N),
						.EMPTY_N(stageF_f_reset_rsps$EMPTY_N));

  // rule RL_rl_show_pipe
  assign CAN_FIRE_RL_rl_show_pipe =
	     NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49 &&
	     rg_state != 4'd0 &&
	     rg_state != 4'd1 &&
	     rg_state != 4'd12 ;
  assign WILL_FIRE_RL_rl_show_pipe = CAN_FIRE_RL_rl_show_pipe ;

  // rule RL_rl_stage2_nonpipe
  assign CAN_FIRE_RL_rl_stage2_nonpipe =
	     rg_state == 4'd3 && !stage3_rg_full &&
	     IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 ==
	     2'd3 ;
  assign WILL_FIRE_RL_rl_stage2_nonpipe = CAN_FIRE_RL_rl_stage2_nonpipe ;

  // rule RL_rl_stage1_trap
  assign CAN_FIRE_RL_rl_stage1_trap =
	     rg_state_0_EQ_3_415_AND_NOT_csr_regfile_interr_ETC___d1623 &&
	     IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 ==
	     4'd12 &&
	     (!stageF_rg_full ||
	      near_mem$imem_valid &&
	      NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1217) ;
  assign WILL_FIRE_RL_rl_stage1_trap = CAN_FIRE_RL_rl_stage1_trap ;

  // rule RL_rl_trap
  assign CAN_FIRE_RL_rl_trap =
	     rg_state == 4'd4 &&
	     (!stageF_rg_full ||
	      near_mem$imem_valid &&
	      NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1217) ;
  assign WILL_FIRE_RL_rl_trap = CAN_FIRE_RL_rl_trap ;

  // rule RL_rl_stage1_CSRR_W
  assign CAN_FIRE_RL_rl_stage1_CSRR_W = MUX_rg_state$write_1__SEL_10 ;
  assign WILL_FIRE_RL_rl_stage1_CSRR_W = MUX_rg_state$write_1__SEL_10 ;

  // rule RL_rl_stage1_CSRR_W_2
  assign CAN_FIRE_RL_rl_stage1_CSRR_W_2 = rg_state == 4'd6 ;
  assign WILL_FIRE_RL_rl_stage1_CSRR_W_2 = rg_state == 4'd6 ;

  // rule RL_rl_stage1_CSRR_S_or_C
  assign CAN_FIRE_RL_rl_stage1_CSRR_S_or_C = MUX_rg_state$write_1__SEL_11 ;
  assign WILL_FIRE_RL_rl_stage1_CSRR_S_or_C = MUX_rg_state$write_1__SEL_11 ;

  // rule RL_rl_stage1_CSRR_S_or_C_2
  assign CAN_FIRE_RL_rl_stage1_CSRR_S_or_C_2 = rg_state == 4'd7 ;
  assign WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 = rg_state == 4'd7 ;

  // rule RL_rl_stage1_restart_after_csrrx
  assign CAN_FIRE_RL_rl_stage1_restart_after_csrrx =
	     imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d1347 &&
	     stageF_branch_predictor$RDY_predict_req &&
	     rg_state_0_EQ_8_705_AND_NOT_stageF_rg_full_194_ETC___d1706 ;
  assign WILL_FIRE_RL_rl_stage1_restart_after_csrrx =
	     CAN_FIRE_RL_rl_stage1_restart_after_csrrx ;

  // rule RL_rl_stage1_xRET
  assign CAN_FIRE_RL_rl_stage1_xRET =
	     rg_state_0_EQ_3_415_AND_NOT_csr_regfile_interr_ETC___d1623 &&
	     (IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 ==
	      4'd8 ||
	      IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 ==
	      4'd9 ||
	      IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 ==
	      4'd10) &&
	     (!stageF_rg_full ||
	      near_mem$imem_valid &&
	      NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1217) ;
  assign WILL_FIRE_RL_rl_stage1_xRET = CAN_FIRE_RL_rl_stage1_xRET ;

  // rule RL_rl_stage1_FENCE_I
  assign CAN_FIRE_RL_rl_stage1_FENCE_I = MUX_rg_state$write_1__SEL_12 ;
  assign WILL_FIRE_RL_rl_stage1_FENCE_I = MUX_rg_state$write_1__SEL_12 ;

  // rule RL_rl_finish_FENCE_I
  assign CAN_FIRE_RL_rl_finish_FENCE_I =
	     imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d1347 &&
	     stageF_branch_predictor$RDY_predict_req &&
	     near_mem$RDY_server_fence_i_response_get &&
	     rg_state == 4'd9 ;
  assign WILL_FIRE_RL_rl_finish_FENCE_I = CAN_FIRE_RL_rl_finish_FENCE_I ;

  // rule RL_rl_stage1_FENCE
  assign CAN_FIRE_RL_rl_stage1_FENCE = MUX_rg_state$write_1__SEL_13 ;
  assign WILL_FIRE_RL_rl_stage1_FENCE = MUX_rg_state$write_1__SEL_13 ;

  // rule RL_rl_finish_FENCE
  assign CAN_FIRE_RL_rl_finish_FENCE =
	     imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d1347 &&
	     stageF_branch_predictor$RDY_predict_req &&
	     near_mem$RDY_server_fence_response_get &&
	     rg_state == 4'd10 ;
  assign WILL_FIRE_RL_rl_finish_FENCE = CAN_FIRE_RL_rl_finish_FENCE ;

  // rule RL_rl_stage1_WFI
  assign CAN_FIRE_RL_rl_stage1_WFI =
	     rg_state_0_EQ_3_415_AND_NOT_csr_regfile_interr_ETC___d1623 &&
	     IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 ==
	     4'd11 &&
	     (!stageF_rg_full ||
	      near_mem$imem_valid &&
	      NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1217) ;
  assign WILL_FIRE_RL_rl_stage1_WFI = CAN_FIRE_RL_rl_stage1_WFI ;

  // rule RL_rl_WFI_resume
  assign CAN_FIRE_RL_rl_WFI_resume =
	     imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d1347 &&
	     stageF_branch_predictor$RDY_predict_req &&
	     rg_state_0_EQ_12_7_AND_csr_regfile_wfi_resume__ETC___d1752 ;
  assign WILL_FIRE_RL_rl_WFI_resume = CAN_FIRE_RL_rl_WFI_resume ;

  // rule RL_rl_reset_from_WFI
  assign CAN_FIRE_RL_rl_reset_from_WFI =
	     rg_state == 4'd12 && f_reset_reqs$EMPTY_N ;
  assign WILL_FIRE_RL_rl_reset_from_WFI = MUX_rg_state$write_1__SEL_5 ;

  // rule RL_rl_trap_fetch
  assign CAN_FIRE_RL_rl_trap_fetch =
	     imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d1347 &&
	     stageF_branch_predictor$RDY_predict_req &&
	     rg_state_0_EQ_5_756_AND_NOT_stageF_rg_full_194_ETC___d1757 ;
  assign WILL_FIRE_RL_rl_trap_fetch = CAN_FIRE_RL_rl_trap_fetch ;

  // rule RL_rl_stage1_interrupt
  assign CAN_FIRE_RL_rl_stage1_interrupt =
	     (csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) &&
	     rg_state == 4'd3 &&
	     NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d1765 &&
	     (!stageF_rg_full ||
	      near_mem$imem_valid &&
	      NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1217) ;
  assign WILL_FIRE_RL_rl_stage1_interrupt = CAN_FIRE_RL_rl_stage1_interrupt ;

  // rule RL_imem_rl_assert_fail
  assign CAN_FIRE_RL_imem_rl_assert_fail = !near_mem$imem_is_i32_not_i16 ;
  assign WILL_FIRE_RL_imem_rl_assert_fail = CAN_FIRE_RL_imem_rl_assert_fail ;

  // rule RL_rl_reset_complete
  assign CAN_FIRE_RL_rl_reset_complete =
	     gpr_regfile$RDY_server_reset_response_get &&
	     near_mem$RDY_server_reset_response_get &&
	     csr_regfile_RDY_server_reset_response_get__336_ETC___d1357 &&
	     rg_state == 4'd1 ;
  assign WILL_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_2 ;

  // rule RL_rl_pipe
  assign CAN_FIRE_RL_rl_pipe =
	     (IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1403 ||
	      NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1413) &&
	     rg_state_0_EQ_3_415_AND_stage3_rg_full_7_OR_NO_ETC___d1425 &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1435 ;
  assign WILL_FIRE_RL_rl_pipe =
	     CAN_FIRE_RL_rl_pipe && !WILL_FIRE_RL_imem_rl_fetch_next_32b ;

  // rule RL_rl_reset_start
  assign CAN_FIRE_RL_rl_reset_start =
	     gpr_regfile$RDY_server_reset_request_put &&
	     near_mem$RDY_server_reset_request_put &&
	     csr_regfile_RDY_server_reset_request_put__317__ETC___d1329 &&
	     rg_state == 4'd0 ;
  assign WILL_FIRE_RL_rl_reset_start = CAN_FIRE_RL_rl_reset_start ;

  // rule RL_imem_rl_fetch_next_32b
  assign CAN_FIRE_RL_imem_rl_fetch_next_32b =
	     near_mem$imem_valid && imem_rg_pc[1:0] != 2'b0 &&
	     imem_rg_pc_BITS_31_TO_2_0_EQ_near_mem_imem_pc__ETC___d13 &&
	     near_mem$imem_instr[17:16] == 2'b11 ;
  assign WILL_FIRE_RL_imem_rl_fetch_next_32b =
	     CAN_FIRE_RL_imem_rl_fetch_next_32b ;

  // rule RL_stage3_rl_reset
  assign CAN_FIRE_RL_stage3_rl_reset =
	     stage3_f_reset_reqs$EMPTY_N && stage3_f_reset_rsps$FULL_N ;
  assign WILL_FIRE_RL_stage3_rl_reset = CAN_FIRE_RL_stage3_rl_reset ;

  // rule RL_stage2_rl_reset_end
  assign CAN_FIRE_RL_stage2_rl_reset_end =
	     stage2_f_reset_rsps$FULL_N && stage2_rg_resetting ;
  assign WILL_FIRE_RL_stage2_rl_reset_end = CAN_FIRE_RL_stage2_rl_reset_end ;

  // rule RL_stage2_rl_reset_begin
  assign CAN_FIRE_RL_stage2_rl_reset_begin = stage2_f_reset_reqs$EMPTY_N ;
  assign WILL_FIRE_RL_stage2_rl_reset_begin = stage2_f_reset_reqs$EMPTY_N ;

  // rule RL_stage1_rl_reset
  assign CAN_FIRE_RL_stage1_rl_reset =
	     stage1_f_reset_reqs$EMPTY_N && stage1_f_reset_rsps$FULL_N ;
  assign WILL_FIRE_RL_stage1_rl_reset = CAN_FIRE_RL_stage1_rl_reset ;

  // rule RL_stageD_rl_reset
  assign CAN_FIRE_RL_stageD_rl_reset =
	     stageD_f_reset_reqs$EMPTY_N && stageD_f_reset_rsps$FULL_N ;
  assign WILL_FIRE_RL_stageD_rl_reset = CAN_FIRE_RL_stageD_rl_reset ;

  // rule RL_stageF_rl_reset
  assign CAN_FIRE_RL_stageF_rl_reset =
	     stageF_f_reset_reqs$EMPTY_N && stageF_f_reset_rsps$FULL_N ;
  assign WILL_FIRE_RL_stageF_rl_reset = CAN_FIRE_RL_stageF_rl_reset ;

  // inputs to muxes for submodule ports
  assign MUX_csr_regfile$mav_csr_write_1__SEL_1 =
	     WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
	     csr_regfile$access_permitted_1 ;
  assign MUX_gpr_regfile$write_rd_1__SEL_3 =
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
	     csr_regfile$access_permitted_2 ;
  assign MUX_imem_rg_cache_addr$write_1__SEL_3 =
	     WILL_FIRE_RL_rl_pipe &&
	     IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1576 ;
  assign MUX_imem_rg_f3$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ;
  assign MUX_rg_next_pc$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_pipe &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1513 ;
  assign MUX_rg_next_pc$write_1__SEL_2 =
	     WILL_FIRE_RL_rl_stage1_WFI || WILL_FIRE_RL_rl_stage1_FENCE ||
	     WILL_FIRE_RL_rl_stage1_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W ;
  assign MUX_rg_state$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_pipe &&
	     IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1564 ;
  assign MUX_rg_state$write_1__SEL_2 =
	     CAN_FIRE_RL_rl_reset_complete &&
	     !WILL_FIRE_RL_imem_rl_fetch_next_32b ;
  assign MUX_rg_state$write_1__SEL_5 =
	     CAN_FIRE_RL_rl_reset_from_WFI && !WILL_FIRE_RL_rl_WFI_resume ;
  assign MUX_rg_state$write_1__SEL_7 =
	     WILL_FIRE_RL_rl_trap_fetch || WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
  assign MUX_rg_state$write_1__SEL_8 =
	     WILL_FIRE_RL_rl_stage1_interrupt ||
	     WILL_FIRE_RL_rl_stage1_trap ||
	     WILL_FIRE_RL_rl_stage2_nonpipe ;
  assign MUX_rg_state$write_1__SEL_9 =
	     WILL_FIRE_RL_rl_stage1_xRET || WILL_FIRE_RL_rl_trap ;
  assign MUX_rg_state$write_1__SEL_10 =
	     rg_state_0_EQ_3_415_AND_NOT_csr_regfile_interr_ETC___d1623 &&
	     IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 ==
	     4'd3 ;
  assign MUX_rg_state$write_1__SEL_11 =
	     rg_state_0_EQ_3_415_AND_NOT_csr_regfile_interr_ETC___d1623 &&
	     IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 ==
	     4'd4 ;
  assign MUX_rg_state$write_1__SEL_12 =
	     near_mem$RDY_server_fence_i_request_put &&
	     rg_state_0_EQ_3_415_AND_NOT_csr_regfile_interr_ETC___d1732 ;
  assign MUX_rg_state$write_1__SEL_13 =
	     near_mem$RDY_server_fence_request_put &&
	     rg_state_0_EQ_3_415_AND_NOT_csr_regfile_interr_ETC___d1741 ;
  assign MUX_rg_trap_info$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W ;
  assign MUX_rg_trap_instr$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_stage1_interrupt ||
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W ||
	     WILL_FIRE_RL_rl_stage1_trap ;
  assign MUX_rg_trap_interrupt$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W ||
	     WILL_FIRE_RL_rl_stage1_trap ||
	     WILL_FIRE_RL_rl_stage2_nonpipe ;
  always@(rg_trap_instr or
	  csr_regfile$read_csr or
	  y__h23012 or
	  IF_csr_regfile_read_csr_rg_trap_instr_644_BITS_ETC___d1697)
  begin
    case (rg_trap_instr[14:12])
      3'b010, 3'b110:
	  MUX_csr_regfile$mav_csr_write_2__VAL_2 =
	      IF_csr_regfile_read_csr_rg_trap_instr_644_BITS_ETC___d1697;
      default: MUX_csr_regfile$mav_csr_write_2__VAL_2 =
		   csr_regfile$read_csr[31:0] & y__h23012;
    endcase
  end
  assign MUX_imem_rg_tval$write_1__VAL_4 = near_mem$imem_pc + 32'd4 ;
  assign MUX_near_mem$imem_req_2__VAL_1 =
	     NOT_soc_map_m_pc_reset_value__362_BITS_1_TO_0__ETC___d1376 ?
	       addr_of_b32___1__h17454 :
	       addr_of_b32__h17342 ;
  assign MUX_near_mem$imem_req_2__VAL_2 =
	     NOT_stageF_branch_predictor_predict_rsp_NOT_im_ETC___d1585 ?
	       addr_of_b32___1__h20536 :
	       addr_of_b32__h20424 ;
  assign MUX_near_mem$imem_req_2__VAL_4 =
	     NOT_rg_next_pc_708_BITS_1_TO_0_709_EQ_0b0_710__ETC___d1717 ?
	       addr_of_b32___1__h28593 :
	       addr_of_b32__h28481 ;
  assign MUX_rg_state$write_1__VAL_2 = rg_run_on_reset ? 4'd3 : 4'd2 ;
  assign MUX_rg_state$write_1__VAL_3 =
	     csr_regfile$access_permitted_1 ? 4'd8 : 4'd4 ;
  assign MUX_rg_state$write_1__VAL_4 =
	     csr_regfile$access_permitted_2 ? 4'd8 : 4'd4 ;
  assign MUX_rg_trap_info$write_1__VAL_1 =
	     { stage1_rg_stage_input[305:274], 4'd2, value__h9376 } ;
  assign MUX_rg_trap_info$write_1__VAL_2 =
	     { stage2_rg_stage2[167:136],
	       near_mem$dmem_exc_code,
	       stage2_rg_stage2[95:64] } ;
  assign MUX_rg_trap_info$write_1__VAL_3 =
	     { stage1_rg_stage_input[305:274],
	       stage1_rg_stage_input[268] ?
		 stage1_rg_stage_input[267:232] :
		 { alu_outputs_exc_code__h8321, trap_info_tval__h9330 } } ;
  assign MUX_rg_trap_info$write_1__VAL_4 =
	     { stage1_rg_stage_input[305:274], x_exc_code__h28843, 32'd0 } ;
  assign MUX_rg_trap_instr$write_1__VAL_1 = stage1_rg_stage_input[231:200] ;
  assign MUX_stage1_rg_full$write_1__VAL_2 =
	     IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1516 &&
	     stageD_rg_full ||
	     IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1600 ;
  assign MUX_stage2_rg_full$write_1__VAL_2 =
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1396 ?
	       IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 !=
	       4'd0 &&
	       IF_NOT_stage1_rg_full_00_34_OR_NOT_stage1_rg_s_ETC___d1463 :
	       IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 !=
	       2'd2 &&
	       IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 !=
	       2'd0 ;
  assign MUX_stageD_rg_full$write_1__VAL_2 =
	     IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1557 ||
	     IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1400 &&
	     stageD_rg_full ;
  assign MUX_stageF_rg_full$write_1__VAL_2 =
	     IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1557 ?
	       csr_regfile_interrupt_pending_rg_cur_priv_1_37_ETC___d1609 :
	       (IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1400 &&
		stageD_rg_full ||
		!near_mem$imem_valid ||
		imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1211) &&
	       stageF_rg_full ;

  // register cfg_logdelay
  assign cfg_logdelay$D_IN = set_verbosity_logdelay ;
  assign cfg_logdelay$EN = EN_set_verbosity ;

  // register cfg_verbosity
  assign cfg_verbosity$D_IN = set_verbosity_verbosity ;
  assign cfg_verbosity$EN = EN_set_verbosity ;

  // register imem_rg_cache_addr
  assign imem_rg_cache_addr$D_IN = near_mem$imem_pc ;
  assign imem_rg_cache_addr$EN =
	     MUX_rg_state$write_1__SEL_7 && near_mem$imem_valid ||
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset &&
	     near_mem$imem_valid ||
	     WILL_FIRE_RL_rl_pipe &&
	     IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1576 ||
	     WILL_FIRE_RL_imem_rl_fetch_next_32b ;

  // register imem_rg_cache_b16
  assign imem_rg_cache_b16$D_IN = near_mem$imem_instr[31:16] ;
  assign imem_rg_cache_b16$EN =
	     MUX_rg_state$write_1__SEL_7 && near_mem$imem_valid ||
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset &&
	     near_mem$imem_valid ||
	     WILL_FIRE_RL_rl_pipe &&
	     IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1576 ||
	     WILL_FIRE_RL_imem_rl_fetch_next_32b ;

  // register imem_rg_f3
  assign imem_rg_f3$D_IN = 3'b010 ;
  assign imem_rg_f3$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe &&
	     IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1576 ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;

  // register imem_rg_mstatus_MXR
  assign imem_rg_mstatus_MXR$D_IN = csr_regfile$read_mstatus[19] ;
  assign imem_rg_mstatus_MXR$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe &&
	     IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1576 ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;

  // register imem_rg_pc
  always@(MUX_imem_rg_f3$write_1__SEL_1 or
	  soc_map$m_pc_reset_value or
	  MUX_imem_rg_cache_addr$write_1__SEL_3 or
	  stageF_branch_predictor$predict_rsp or
	  MUX_rg_state$write_1__SEL_7 or rg_next_pc)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_imem_rg_f3$write_1__SEL_1:
	  imem_rg_pc$D_IN = soc_map$m_pc_reset_value[31:0];
      MUX_imem_rg_cache_addr$write_1__SEL_3:
	  imem_rg_pc$D_IN = stageF_branch_predictor$predict_rsp;
      MUX_rg_state$write_1__SEL_7: imem_rg_pc$D_IN = rg_next_pc;
      default: imem_rg_pc$D_IN = 32'hAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign imem_rg_pc$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe &&
	     IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1576 ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;

  // register imem_rg_priv
  assign imem_rg_priv$D_IN = rg_cur_priv ;
  assign imem_rg_priv$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe &&
	     IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1576 ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;

  // register imem_rg_satp
  assign imem_rg_satp$D_IN = csr_regfile$read_satp ;
  assign imem_rg_satp$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe &&
	     IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1576 ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;

  // register imem_rg_sstatus_SUM
  assign imem_rg_sstatus_SUM$D_IN = 1'd0 ;
  assign imem_rg_sstatus_SUM$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe &&
	     IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1576 ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;

  // register imem_rg_tval
  always@(MUX_imem_rg_f3$write_1__SEL_1 or
	  soc_map$m_pc_reset_value or
	  MUX_imem_rg_cache_addr$write_1__SEL_3 or
	  stageF_branch_predictor$predict_rsp or
	  MUX_rg_state$write_1__SEL_7 or
	  rg_next_pc or
	  WILL_FIRE_RL_imem_rl_fetch_next_32b or
	  MUX_imem_rg_tval$write_1__VAL_4)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_imem_rg_f3$write_1__SEL_1:
	  imem_rg_tval$D_IN = soc_map$m_pc_reset_value[31:0];
      MUX_imem_rg_cache_addr$write_1__SEL_3:
	  imem_rg_tval$D_IN = stageF_branch_predictor$predict_rsp;
      MUX_rg_state$write_1__SEL_7: imem_rg_tval$D_IN = rg_next_pc;
      WILL_FIRE_RL_imem_rl_fetch_next_32b:
	  imem_rg_tval$D_IN = MUX_imem_rg_tval$write_1__VAL_4;
      default: imem_rg_tval$D_IN = 32'hAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign imem_rg_tval$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe &&
	     IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1576 ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
	     WILL_FIRE_RL_imem_rl_fetch_next_32b ;

  // register rg_csr_pc
  assign rg_csr_pc$D_IN = stage1_rg_stage_input[305:274] ;
  assign rg_csr_pc$EN = MUX_rg_trap_info$write_1__SEL_1 ;

  // register rg_csr_val1
  assign rg_csr_val1$D_IN = x_out_data_to_stage2_val1__h7721 ;
  assign rg_csr_val1$EN = MUX_rg_trap_info$write_1__SEL_1 ;

  // register rg_cur_priv
  always@(WILL_FIRE_RL_rl_trap or
	  csr_regfile$csr_trap_actions or
	  WILL_FIRE_RL_rl_stage1_xRET or
	  csr_regfile$csr_ret_actions or WILL_FIRE_RL_rl_reset_start)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_rl_trap:
	  rg_cur_priv$D_IN = csr_regfile$csr_trap_actions[1:0];
      WILL_FIRE_RL_rl_stage1_xRET:
	  rg_cur_priv$D_IN = csr_regfile$csr_ret_actions[33:32];
      WILL_FIRE_RL_rl_reset_start: rg_cur_priv$D_IN = 2'b11;
      default: rg_cur_priv$D_IN = 2'b10 /* unspecified value */ ;
    endcase
  end
  assign rg_cur_priv$EN =
	     WILL_FIRE_RL_rl_trap || WILL_FIRE_RL_rl_stage1_xRET ||
	     WILL_FIRE_RL_rl_reset_start ;

  // register rg_epoch
  always@(MUX_imem_rg_f3$write_1__SEL_1 or
	  new_epoch__h16878 or
	  MUX_rg_state$write_1__SEL_7 or WILL_FIRE_RL_rl_reset_start)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_imem_rg_f3$write_1__SEL_1: rg_epoch$D_IN = new_epoch__h16878;
      MUX_rg_state$write_1__SEL_7: rg_epoch$D_IN = new_epoch__h16878;
      WILL_FIRE_RL_rl_reset_start: rg_epoch$D_IN = 2'd0;
      default: rg_epoch$D_IN = 2'b10 /* unspecified value */ ;
    endcase
  end
  assign rg_epoch$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
	     WILL_FIRE_RL_rl_reset_start ;

  // register rg_mstatus_MXR
  assign rg_mstatus_MXR$D_IN = csr_regfile$read_mstatus[19] ;
  assign rg_mstatus_MXR$EN = MUX_rg_state$write_1__SEL_9 ;

  // register rg_next_pc
  always@(MUX_rg_next_pc$write_1__SEL_1 or
	  x_out_next_pc__h7677 or
	  MUX_rg_next_pc$write_1__SEL_2 or
	  WILL_FIRE_RL_rl_trap or
	  csr_regfile$csr_trap_actions or
	  WILL_FIRE_RL_rl_stage1_xRET or csr_regfile$csr_ret_actions)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_rg_next_pc$write_1__SEL_1: rg_next_pc$D_IN = x_out_next_pc__h7677;
      MUX_rg_next_pc$write_1__SEL_2: rg_next_pc$D_IN = x_out_next_pc__h7677;
      WILL_FIRE_RL_rl_trap:
	  rg_next_pc$D_IN = csr_regfile$csr_trap_actions[97:66];
      WILL_FIRE_RL_rl_stage1_xRET:
	  rg_next_pc$D_IN = csr_regfile$csr_ret_actions[65:34];
      default: rg_next_pc$D_IN = 32'hAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign rg_next_pc$EN =
	     WILL_FIRE_RL_rl_pipe &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1513 ||
	     WILL_FIRE_RL_rl_stage1_WFI ||
	     WILL_FIRE_RL_rl_stage1_FENCE ||
	     WILL_FIRE_RL_rl_stage1_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W ||
	     WILL_FIRE_RL_rl_trap ||
	     WILL_FIRE_RL_rl_stage1_xRET ;

  // register rg_run_on_reset
  assign rg_run_on_reset$D_IN = f_reset_reqs$D_OUT ;
  assign rg_run_on_reset$EN = CAN_FIRE_RL_rl_reset_start ;

  // register rg_sstatus_SUM
  assign rg_sstatus_SUM$D_IN = 1'd0 ;
  assign rg_sstatus_SUM$EN = MUX_rg_state$write_1__SEL_9 ;

  // register rg_start_CPI_cycles
  assign rg_start_CPI_cycles$D_IN = csr_regfile$read_csr_mcycle ;
  assign rg_start_CPI_cycles$EN = MUX_imem_rg_f3$write_1__SEL_1 ;

  // register rg_start_CPI_instrs
  assign rg_start_CPI_instrs$D_IN = csr_regfile$read_csr_minstret ;
  assign rg_start_CPI_instrs$EN = MUX_imem_rg_f3$write_1__SEL_1 ;

  // register rg_state
  always@(WILL_FIRE_RL_rl_reset_complete or
	  MUX_rg_state$write_1__VAL_2 or
	  WILL_FIRE_RL_rl_stage1_CSRR_W_2 or
	  MUX_rg_state$write_1__VAL_3 or
	  WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 or
	  MUX_rg_state$write_1__VAL_4 or
	  WILL_FIRE_RL_rl_reset_from_WFI or
	  WILL_FIRE_RL_rl_reset_start or
	  MUX_rg_state$write_1__SEL_7 or
	  MUX_rg_state$write_1__SEL_8 or
	  MUX_rg_state$write_1__SEL_1 or
	  MUX_rg_state$write_1__SEL_9 or
	  WILL_FIRE_RL_rl_stage1_CSRR_W or
	  WILL_FIRE_RL_rl_stage1_CSRR_S_or_C or
	  WILL_FIRE_RL_rl_stage1_FENCE_I or
	  WILL_FIRE_RL_rl_stage1_FENCE or WILL_FIRE_RL_rl_stage1_WFI)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_rl_reset_complete:
	  rg_state$D_IN = MUX_rg_state$write_1__VAL_2;
      WILL_FIRE_RL_rl_stage1_CSRR_W_2:
	  rg_state$D_IN = MUX_rg_state$write_1__VAL_3;
      WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2:
	  rg_state$D_IN = MUX_rg_state$write_1__VAL_4;
      WILL_FIRE_RL_rl_reset_from_WFI: rg_state$D_IN = 4'd0;
      WILL_FIRE_RL_rl_reset_start: rg_state$D_IN = 4'd1;
      MUX_rg_state$write_1__SEL_7: rg_state$D_IN = 4'd3;
      MUX_rg_state$write_1__SEL_8: rg_state$D_IN = 4'd4;
      MUX_rg_state$write_1__SEL_1 || MUX_rg_state$write_1__SEL_9:
	  rg_state$D_IN = 4'd5;
      WILL_FIRE_RL_rl_stage1_CSRR_W: rg_state$D_IN = 4'd6;
      WILL_FIRE_RL_rl_stage1_CSRR_S_or_C: rg_state$D_IN = 4'd7;
      WILL_FIRE_RL_rl_stage1_FENCE_I: rg_state$D_IN = 4'd9;
      WILL_FIRE_RL_rl_stage1_FENCE: rg_state$D_IN = 4'd10;
      WILL_FIRE_RL_rl_stage1_WFI: rg_state$D_IN = 4'd12;
      default: rg_state$D_IN = 4'b1010 /* unspecified value */ ;
    endcase
  end
  assign rg_state$EN =
	     WILL_FIRE_RL_rl_pipe &&
	     IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1564 ||
	     WILL_FIRE_RL_rl_reset_complete ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W_2 ||
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 ||
	     WILL_FIRE_RL_rl_reset_from_WFI ||
	     WILL_FIRE_RL_rl_reset_start ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
	     WILL_FIRE_RL_rl_stage1_interrupt ||
	     WILL_FIRE_RL_rl_stage1_trap ||
	     WILL_FIRE_RL_rl_stage2_nonpipe ||
	     WILL_FIRE_RL_rl_stage1_xRET ||
	     WILL_FIRE_RL_rl_trap ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W ||
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
	     WILL_FIRE_RL_rl_stage1_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_FENCE ||
	     WILL_FIRE_RL_rl_stage1_WFI ;

  // register rg_trap_info
  always@(MUX_rg_trap_info$write_1__SEL_1 or
	  MUX_rg_trap_info$write_1__VAL_1 or
	  WILL_FIRE_RL_rl_stage2_nonpipe or
	  MUX_rg_trap_info$write_1__VAL_2 or
	  WILL_FIRE_RL_rl_stage1_trap or
	  MUX_rg_trap_info$write_1__VAL_3 or
	  WILL_FIRE_RL_rl_stage1_interrupt or MUX_rg_trap_info$write_1__VAL_4)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_rg_trap_info$write_1__SEL_1:
	  rg_trap_info$D_IN = MUX_rg_trap_info$write_1__VAL_1;
      WILL_FIRE_RL_rl_stage2_nonpipe:
	  rg_trap_info$D_IN = MUX_rg_trap_info$write_1__VAL_2;
      WILL_FIRE_RL_rl_stage1_trap:
	  rg_trap_info$D_IN = MUX_rg_trap_info$write_1__VAL_3;
      WILL_FIRE_RL_rl_stage1_interrupt:
	  rg_trap_info$D_IN = MUX_rg_trap_info$write_1__VAL_4;
      default: rg_trap_info$D_IN =
		   68'hAAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign rg_trap_info$EN =
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W ||
	     WILL_FIRE_RL_rl_stage2_nonpipe ||
	     WILL_FIRE_RL_rl_stage1_trap ||
	     WILL_FIRE_RL_rl_stage1_interrupt ;

  // register rg_trap_instr
  assign rg_trap_instr$D_IN =
	     MUX_rg_trap_instr$write_1__SEL_1 ?
	       stage1_rg_stage_input[231:200] :
	       stage2_rg_stage2[135:104] ;
  assign rg_trap_instr$EN =
	     WILL_FIRE_RL_rl_stage1_interrupt ||
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W ||
	     WILL_FIRE_RL_rl_stage1_trap ||
	     WILL_FIRE_RL_rl_stage2_nonpipe ;

  // register rg_trap_interrupt
  assign rg_trap_interrupt$D_IN = !MUX_rg_trap_interrupt$write_1__SEL_1 ;
  assign rg_trap_interrupt$EN =
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W ||
	     WILL_FIRE_RL_rl_stage1_trap ||
	     WILL_FIRE_RL_rl_stage2_nonpipe ||
	     WILL_FIRE_RL_rl_stage1_interrupt ;

  // register stage1_rg_full
  always@(WILL_FIRE_RL_stage1_rl_reset or
	  WILL_FIRE_RL_rl_pipe or
	  MUX_stage1_rg_full$write_1__VAL_2 or
	  MUX_imem_rg_f3$write_1__SEL_1 or
	  WILL_FIRE_RL_rl_stage1_WFI or
	  WILL_FIRE_RL_rl_finish_FENCE or
	  WILL_FIRE_RL_rl_finish_FENCE_I or
	  WILL_FIRE_RL_rl_stage1_xRET or
	  WILL_FIRE_RL_rl_stage1_restart_after_csrrx or WILL_FIRE_RL_rl_trap)
  case (1'b1)
    WILL_FIRE_RL_stage1_rl_reset: stage1_rg_full$D_IN = 1'd0;
    WILL_FIRE_RL_rl_pipe:
	stage1_rg_full$D_IN = MUX_stage1_rg_full$write_1__VAL_2;
    MUX_imem_rg_f3$write_1__SEL_1 || WILL_FIRE_RL_rl_stage1_WFI ||
    WILL_FIRE_RL_rl_finish_FENCE ||
    WILL_FIRE_RL_rl_finish_FENCE_I ||
    WILL_FIRE_RL_rl_stage1_xRET ||
    WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
    WILL_FIRE_RL_rl_trap:
	stage1_rg_full$D_IN = 1'd0;
    default: stage1_rg_full$D_IN = 1'b0 /* unspecified value */ ;
  endcase
  assign stage1_rg_full$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe ||
	     WILL_FIRE_RL_rl_stage1_WFI ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_xRET ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
	     WILL_FIRE_RL_rl_trap ||
	     WILL_FIRE_RL_stage1_rl_reset ;

  // register stage1_rg_stage_input
  assign stage1_rg_stage_input$D_IN =
	     { stageD_rg_data[137:106],
	       stageD_rg_data[103:102],
	       stageD_rg_data[105:104],
	       stageD_rg_data[101:64],
	       _theResult____h5124,
	       stageD_rg_data[47:0],
	       _theResult____h5124[6:0],
	       _theResult____h5124[11:7],
	       _theResult____h5124[19:15],
	       _theResult____h5124[24:20],
	       _theResult____h5124[31:27],
	       _theResult____h5124[31:20],
	       _theResult____h5124[14:12],
	       _theResult____h5124[31:27],
	       _theResult____h5124[31:25],
	       decoded_instr_funct10__h19112,
	       _theResult____h5124[31:20],
	       decoded_instr_imm12_S__h19114,
	       decoded_instr_imm13_SB__h19115,
	       _theResult____h5124[31:12],
	       decoded_instr_imm21_UJ__h19117,
	       _theResult____h5124[27:20],
	       _theResult____h5124[26:25] } ;
  assign stage1_rg_stage_input$EN =
	     WILL_FIRE_RL_rl_pipe &&
	     IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1516 &&
	     stageD_rg_full ;

  // register stage2_rg_full
  always@(stage2_f_reset_reqs$EMPTY_N or
	  WILL_FIRE_RL_rl_pipe or
	  MUX_stage2_rg_full$write_1__VAL_2 or
	  MUX_imem_rg_f3$write_1__SEL_1 or WILL_FIRE_RL_rl_trap)
  case (1'b1)
    stage2_f_reset_reqs$EMPTY_N: stage2_rg_full$D_IN = 1'd0;
    WILL_FIRE_RL_rl_pipe:
	stage2_rg_full$D_IN = MUX_stage2_rg_full$write_1__VAL_2;
    MUX_imem_rg_f3$write_1__SEL_1 || WILL_FIRE_RL_rl_trap:
	stage2_rg_full$D_IN = 1'd0;
    default: stage2_rg_full$D_IN = 1'b0 /* unspecified value */ ;
  endcase
  assign stage2_rg_full$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe ||
	     WILL_FIRE_RL_rl_trap ||
	     stage2_f_reset_reqs$EMPTY_N ;

  // register stage2_rg_resetting
  assign stage2_rg_resetting$D_IN = stage2_f_reset_reqs$EMPTY_N ;
  assign stage2_rg_resetting$EN =
	     WILL_FIRE_RL_stage2_rl_reset_end || stage2_f_reset_reqs$EMPTY_N ;

  // register stage2_rg_stage2
  assign stage2_rg_stage2$D_IN =
	     { rg_cur_priv,
	       stage1_rg_stage_input[305:274],
	       stage1_rg_stage_input[231:200],
	       IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d631,
	       x_out_data_to_stage2_rd__h7719,
	       x_out_data_to_stage2_addr__h7720,
	       x_out_data_to_stage2_val1__h7721,
	       x_out_data_to_stage2_val2__h7722 } ;
  assign stage2_rg_stage2$EN =
	     WILL_FIRE_RL_rl_pipe &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1460 &&
	     IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 !=
	     4'd0 &&
	     IF_NOT_stage1_rg_full_00_34_OR_NOT_stage1_rg_s_ETC___d1463 ;

  // register stage3_rg_full
  always@(WILL_FIRE_RL_stage3_rl_reset or
	  WILL_FIRE_RL_rl_pipe or
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 or
	  MUX_imem_rg_f3$write_1__SEL_1)
  case (1'b1)
    WILL_FIRE_RL_stage3_rl_reset: stage3_rg_full$D_IN = 1'd0;
    WILL_FIRE_RL_rl_pipe:
	stage3_rg_full$D_IN =
	    IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd2;
    MUX_imem_rg_f3$write_1__SEL_1: stage3_rg_full$D_IN = 1'd0;
    default: stage3_rg_full$D_IN = 1'b0 /* unspecified value */ ;
  endcase
  assign stage3_rg_full$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe ||
	     WILL_FIRE_RL_stage3_rl_reset ;

  // register stage3_rg_stage3
  assign stage3_rg_stage3$D_IN =
	     { stage2_rg_stage2[167:104],
	       stage2_rg_stage2[169:168],
	       stage2_rg_stage2[103:101] == 3'd0 ||
	       IF_stage2_rg_stage2_7_BITS_103_TO_101_8_EQ_1_0_ETC___d150,
	       x_out_data_to_stage3_rd__h7092,
	       x_out_data_to_stage3_rd_val__h7093 } ;
  assign stage3_rg_stage3$EN =
	     WILL_FIRE_RL_rl_pipe &&
	     IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 ==
	     2'd2 ;

  // register stageD_rg_data
  assign stageD_rg_data$D_IN =
	     { imem_rg_pc,
	       stageF_rg_epoch,
	       stageF_rg_priv,
	       NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1215,
	       near_mem$imem_exc,
	       near_mem$imem_exc_code,
	       imem_rg_tval,
	       d_instr__h15515,
	       stageF_branch_predictor$predict_rsp } ;
  assign stageD_rg_data$EN =
	     WILL_FIRE_RL_rl_pipe &&
	     IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1557 ;

  // register stageD_rg_full
  always@(WILL_FIRE_RL_stageD_rl_reset or
	  WILL_FIRE_RL_rl_pipe or
	  MUX_stageD_rg_full$write_1__VAL_2 or
	  MUX_imem_rg_f3$write_1__SEL_1 or
	  WILL_FIRE_RL_rl_trap_fetch or
	  WILL_FIRE_RL_rl_WFI_resume or
	  WILL_FIRE_RL_rl_stage1_WFI or
	  WILL_FIRE_RL_rl_finish_FENCE or
	  WILL_FIRE_RL_rl_finish_FENCE_I or
	  WILL_FIRE_RL_rl_stage1_xRET or
	  WILL_FIRE_RL_rl_stage1_restart_after_csrrx or WILL_FIRE_RL_rl_trap)
  case (1'b1)
    WILL_FIRE_RL_stageD_rl_reset: stageD_rg_full$D_IN = 1'd0;
    WILL_FIRE_RL_rl_pipe:
	stageD_rg_full$D_IN = MUX_stageD_rg_full$write_1__VAL_2;
    MUX_imem_rg_f3$write_1__SEL_1 || WILL_FIRE_RL_rl_trap_fetch ||
    WILL_FIRE_RL_rl_WFI_resume ||
    WILL_FIRE_RL_rl_stage1_WFI ||
    WILL_FIRE_RL_rl_finish_FENCE ||
    WILL_FIRE_RL_rl_finish_FENCE_I ||
    WILL_FIRE_RL_rl_stage1_xRET ||
    WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
    WILL_FIRE_RL_rl_trap:
	stageD_rg_full$D_IN = 1'd0;
    default: stageD_rg_full$D_IN = 1'b0 /* unspecified value */ ;
  endcase
  assign stageD_rg_full$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_stage1_WFI ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_xRET ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
	     WILL_FIRE_RL_rl_trap ||
	     WILL_FIRE_RL_stageD_rl_reset ;

  // register stageF_rg_epoch
  always@(WILL_FIRE_RL_stageF_rl_reset or
	  MUX_imem_rg_cache_addr$write_1__SEL_3 or
	  stageF_rg_epoch or
	  MUX_imem_rg_f3$write_1__SEL_1 or
	  new_epoch__h16878 or
	  WILL_FIRE_RL_rl_trap_fetch or
	  WILL_FIRE_RL_rl_WFI_resume or
	  WILL_FIRE_RL_rl_finish_FENCE or
	  WILL_FIRE_RL_rl_finish_FENCE_I or
	  WILL_FIRE_RL_rl_stage1_restart_after_csrrx)
  case (1'b1)
    WILL_FIRE_RL_stageF_rl_reset: stageF_rg_epoch$D_IN = 2'd0;
    MUX_imem_rg_cache_addr$write_1__SEL_3:
	stageF_rg_epoch$D_IN = stageF_rg_epoch;
    MUX_imem_rg_f3$write_1__SEL_1: stageF_rg_epoch$D_IN = new_epoch__h16878;
    WILL_FIRE_RL_rl_trap_fetch: stageF_rg_epoch$D_IN = new_epoch__h16878;
    WILL_FIRE_RL_rl_WFI_resume: stageF_rg_epoch$D_IN = new_epoch__h16878;
    WILL_FIRE_RL_rl_finish_FENCE: stageF_rg_epoch$D_IN = new_epoch__h16878;
    WILL_FIRE_RL_rl_finish_FENCE_I: stageF_rg_epoch$D_IN = new_epoch__h16878;
    WILL_FIRE_RL_rl_stage1_restart_after_csrrx:
	stageF_rg_epoch$D_IN = new_epoch__h16878;
    default: stageF_rg_epoch$D_IN = 2'b10 /* unspecified value */ ;
  endcase
  assign stageF_rg_epoch$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe &&
	     IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1576 ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
	     WILL_FIRE_RL_stageF_rl_reset ;

  // register stageF_rg_full
  always@(WILL_FIRE_RL_stageF_rl_reset or
	  WILL_FIRE_RL_rl_pipe or
	  MUX_stageF_rg_full$write_1__VAL_2 or
	  MUX_imem_rg_f3$write_1__SEL_1 or
	  WILL_FIRE_RL_rl_trap_fetch or
	  WILL_FIRE_RL_rl_WFI_resume or
	  WILL_FIRE_RL_rl_finish_FENCE or
	  WILL_FIRE_RL_rl_finish_FENCE_I or
	  WILL_FIRE_RL_rl_stage1_restart_after_csrrx)
  case (1'b1)
    WILL_FIRE_RL_stageF_rl_reset: stageF_rg_full$D_IN = 1'd0;
    WILL_FIRE_RL_rl_pipe:
	stageF_rg_full$D_IN = MUX_stageF_rg_full$write_1__VAL_2;
    MUX_imem_rg_f3$write_1__SEL_1 || WILL_FIRE_RL_rl_trap_fetch ||
    WILL_FIRE_RL_rl_WFI_resume ||
    WILL_FIRE_RL_rl_finish_FENCE ||
    WILL_FIRE_RL_rl_finish_FENCE_I ||
    WILL_FIRE_RL_rl_stage1_restart_after_csrrx:
	stageF_rg_full$D_IN = 1'd1;
    default: stageF_rg_full$D_IN = 1'b0 /* unspecified value */ ;
  endcase
  assign stageF_rg_full$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe ||
	     WILL_FIRE_RL_stageF_rl_reset ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;

  // register stageF_rg_priv
  assign stageF_rg_priv$D_IN = rg_cur_priv ;
  assign stageF_rg_priv$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe &&
	     IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1576 ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;

  // submodule csr_regfile
  assign csr_regfile$access_permitted_1_csr_addr = rg_trap_instr[31:20] ;
  assign csr_regfile$access_permitted_1_priv = rg_cur_priv ;
  assign csr_regfile$access_permitted_1_read_not_write = 1'd0 ;
  assign csr_regfile$access_permitted_2_csr_addr = rg_trap_instr[31:20] ;
  assign csr_regfile$access_permitted_2_priv = rg_cur_priv ;
  assign csr_regfile$access_permitted_2_read_not_write =
	     rs1_val__h22743 == 32'd0 ;
  assign csr_regfile$csr_counter_read_fault_csr_addr = 12'h0 ;
  assign csr_regfile$csr_counter_read_fault_priv = 2'h0 ;
  always@(IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489)
  begin
    case (IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489)
      4'd8: csr_regfile$csr_ret_actions_from_priv = 2'b11;
      4'd9: csr_regfile$csr_ret_actions_from_priv = 2'b01;
      default: csr_regfile$csr_ret_actions_from_priv = 2'b0;
    endcase
  end
  assign csr_regfile$csr_trap_actions_exc_code = rg_trap_info[35:32] ;
  assign csr_regfile$csr_trap_actions_from_priv = rg_cur_priv ;
  assign csr_regfile$csr_trap_actions_interrupt =
	     rg_trap_interrupt && !csr_regfile$nmi_pending ;
  assign csr_regfile$csr_trap_actions_nmi =
	     rg_trap_interrupt && csr_regfile$nmi_pending ;
  assign csr_regfile$csr_trap_actions_pc = rg_trap_info[67:36] ;
  assign csr_regfile$csr_trap_actions_xtval = rg_trap_info[31:0] ;
  assign csr_regfile$interrupt_pending_cur_priv = rg_cur_priv ;
  assign csr_regfile$m_external_interrupt_req_set_not_clear =
	     m_external_interrupt_req_set_not_clear ;
  assign csr_regfile$mav_csr_write_csr_addr = rg_trap_instr[31:20] ;
  assign csr_regfile$mav_csr_write_word =
	     MUX_csr_regfile$mav_csr_write_1__SEL_1 ?
	       rs1_val__h22063 :
	       MUX_csr_regfile$mav_csr_write_2__VAL_2 ;
  assign csr_regfile$mav_read_csr_csr_addr = 12'h0 ;
  assign csr_regfile$nmi_req_set_not_clear = nmi_req_set_not_clear ;
  assign csr_regfile$read_csr_csr_addr = rg_trap_instr[31:20] ;
  assign csr_regfile$read_csr_port2_csr_addr = 12'h0 ;
  assign csr_regfile$s_external_interrupt_req_set_not_clear =
	     s_external_interrupt_req_set_not_clear ;
  assign csr_regfile$software_interrupt_req_set_not_clear =
	     software_interrupt_req_set_not_clear ;
  assign csr_regfile$timer_interrupt_req_set_not_clear =
	     timer_interrupt_req_set_not_clear ;
  assign csr_regfile$EN_server_reset_request_put =
	     CAN_FIRE_RL_rl_reset_start ;
  assign csr_regfile$EN_server_reset_response_get =
	     MUX_rg_state$write_1__SEL_2 ;
  assign csr_regfile$EN_mav_read_csr = 1'b0 ;
  assign csr_regfile$EN_mav_csr_write =
	     WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
	     csr_regfile$access_permitted_1 ||
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
	     csr_regfile$access_permitted_2 &&
	     rg_trap_instr[19:15] != 5'd0 ;
  assign csr_regfile$EN_csr_trap_actions = CAN_FIRE_RL_rl_trap ;
  assign csr_regfile$EN_csr_ret_actions = CAN_FIRE_RL_rl_stage1_xRET ;
  assign csr_regfile$EN_csr_minstret_incr =
	     WILL_FIRE_RL_rl_pipe &&
	     IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 ==
	     2'd2 ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
	     csr_regfile$access_permitted_1 ||
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
	     csr_regfile$access_permitted_2 ||
	     WILL_FIRE_RL_rl_stage1_WFI ||
	     WILL_FIRE_RL_rl_stage1_FENCE ||
	     WILL_FIRE_RL_rl_stage1_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_xRET ;
  assign csr_regfile$EN_debug = 1'b0 ;

  // submodule f_reset_reqs
  assign f_reset_reqs$D_IN = hart0_server_reset_request_put ;
  assign f_reset_reqs$ENQ = EN_hart0_server_reset_request_put ;
  assign f_reset_reqs$DEQ =
	     gpr_regfile$RDY_server_reset_request_put &&
	     near_mem$RDY_server_reset_request_put &&
	     csr_regfile_RDY_server_reset_request_put__317__ETC___d1329 &&
	     rg_state == 4'd0 ;
  assign f_reset_reqs$CLR = 1'b0 ;

  // submodule f_reset_rsps
  assign f_reset_rsps$D_IN = rg_run_on_reset ;
  assign f_reset_rsps$ENQ = MUX_rg_state$write_1__SEL_2 ;
  assign f_reset_rsps$DEQ = EN_hart0_server_reset_response_get ;
  assign f_reset_rsps$CLR = 1'b0 ;

  // submodule gpr_regfile
  assign gpr_regfile$read_rs1_port2_rs1 = 5'h0 ;
  assign gpr_regfile$read_rs1_rs1 = stage1_rg_stage_input[139:135] ;
  assign gpr_regfile$read_rs2_rs2 = stage1_rg_stage_input[134:130] ;
  assign gpr_regfile$write_rd_rd =
	     (MUX_csr_regfile$mav_csr_write_1__SEL_1 ||
	      MUX_gpr_regfile$write_rd_1__SEL_3) ?
	       rg_trap_instr[11:7] :
	       stage3_rg_stage3[36:32] ;
  assign gpr_regfile$write_rd_rd_val =
	     (MUX_csr_regfile$mav_csr_write_1__SEL_1 ||
	      MUX_gpr_regfile$write_rd_1__SEL_3) ?
	       csr_regfile$read_csr[31:0] :
	       stage3_rg_stage3[31:0] ;
  assign gpr_regfile$EN_server_reset_request_put =
	     CAN_FIRE_RL_rl_reset_start ;
  assign gpr_regfile$EN_server_reset_response_get =
	     MUX_rg_state$write_1__SEL_2 ;
  assign gpr_regfile$EN_write_rd =
	     WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[37] ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
	     csr_regfile$access_permitted_1 ||
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
	     csr_regfile$access_permitted_2 ;

  // submodule near_mem
  assign near_mem$dmem_master_arready = dmem_master_arready ;
  assign near_mem$dmem_master_awready = dmem_master_awready ;
  assign near_mem$dmem_master_bid = dmem_master_bid ;
  assign near_mem$dmem_master_bresp = dmem_master_bresp ;
  assign near_mem$dmem_master_bvalid = dmem_master_bvalid ;
  assign near_mem$dmem_master_rdata = dmem_master_rdata ;
  assign near_mem$dmem_master_rid = dmem_master_rid ;
  assign near_mem$dmem_master_rlast = dmem_master_rlast ;
  assign near_mem$dmem_master_rresp = dmem_master_rresp ;
  assign near_mem$dmem_master_rvalid = dmem_master_rvalid ;
  assign near_mem$dmem_master_wready = dmem_master_wready ;
  assign near_mem$dmem_req_addr = x_out_data_to_stage2_addr__h7720 ;
  assign near_mem$dmem_req_amo_funct7 =
	     x_out_data_to_stage2_val1__h7721[6:0] ;
  assign near_mem$dmem_req_f3 = MUX_rg_trap_instr$write_1__VAL_1[14:12] ;
  assign near_mem$dmem_req_mstatus_MXR = csr_regfile$read_mstatus[19] ;
  always@(IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d631)
  begin
    case (IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d631)
      3'd1: near_mem$dmem_req_op = 2'd0;
      3'd2: near_mem$dmem_req_op = 2'd1;
      default: near_mem$dmem_req_op = 2'd2;
    endcase
  end
  assign near_mem$dmem_req_priv =
	     csr_regfile$read_mstatus[17] ?
	       csr_regfile$read_mstatus[12:11] :
	       rg_cur_priv ;
  assign near_mem$dmem_req_satp = csr_regfile$read_satp ;
  assign near_mem$dmem_req_sstatus_SUM = 1'd0 ;
  assign near_mem$dmem_req_store_value =
	     { 32'd0, x_out_data_to_stage2_val2__h7722 } ;
  assign near_mem$imem_master_arready = imem_master_arready ;
  assign near_mem$imem_master_awready = imem_master_awready ;
  assign near_mem$imem_master_bid = imem_master_bid ;
  assign near_mem$imem_master_bresp = imem_master_bresp ;
  assign near_mem$imem_master_bvalid = imem_master_bvalid ;
  assign near_mem$imem_master_rdata = imem_master_rdata ;
  assign near_mem$imem_master_rid = imem_master_rid ;
  assign near_mem$imem_master_rlast = imem_master_rlast ;
  assign near_mem$imem_master_rresp = imem_master_rresp ;
  assign near_mem$imem_master_rvalid = imem_master_rvalid ;
  assign near_mem$imem_master_wready = imem_master_wready ;
  always@(MUX_imem_rg_f3$write_1__SEL_1 or
	  MUX_near_mem$imem_req_2__VAL_1 or
	  MUX_imem_rg_cache_addr$write_1__SEL_3 or
	  MUX_near_mem$imem_req_2__VAL_2 or
	  WILL_FIRE_RL_imem_rl_fetch_next_32b or
	  MUX_imem_rg_tval$write_1__VAL_4 or
	  MUX_rg_state$write_1__SEL_7 or MUX_near_mem$imem_req_2__VAL_4)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_imem_rg_f3$write_1__SEL_1:
	  near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_1;
      MUX_imem_rg_cache_addr$write_1__SEL_3:
	  near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_2;
      WILL_FIRE_RL_imem_rl_fetch_next_32b:
	  near_mem$imem_req_addr = MUX_imem_rg_tval$write_1__VAL_4;
      MUX_rg_state$write_1__SEL_7:
	  near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_4;
      default: near_mem$imem_req_addr = 32'hAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign near_mem$imem_req_f3 =
	     WILL_FIRE_RL_imem_rl_fetch_next_32b ? imem_rg_f3 : 3'b010 ;
  assign near_mem$imem_req_mstatus_MXR =
	     (MUX_imem_rg_f3$write_1__SEL_1 ||
	      MUX_imem_rg_cache_addr$write_1__SEL_3 ||
	      MUX_rg_state$write_1__SEL_7) ?
	       csr_regfile$read_mstatus[19] :
	       imem_rg_mstatus_MXR ;
  assign near_mem$imem_req_priv =
	     (MUX_imem_rg_f3$write_1__SEL_1 ||
	      MUX_imem_rg_cache_addr$write_1__SEL_3 ||
	      MUX_rg_state$write_1__SEL_7) ?
	       rg_cur_priv :
	       imem_rg_priv ;
  assign near_mem$imem_req_satp =
	     WILL_FIRE_RL_imem_rl_fetch_next_32b ?
	       imem_rg_satp :
	       csr_regfile$read_satp ;
  assign near_mem$imem_req_sstatus_SUM =
	     WILL_FIRE_RL_imem_rl_fetch_next_32b && imem_rg_sstatus_SUM ;
  assign near_mem$server_fence_request_put =
	     8'b10101010 /* unspecified value */  ;
  assign near_mem$set_watch_tohost_tohost_addr =
	     set_watch_tohost_tohost_addr ;
  assign near_mem$set_watch_tohost_watch_tohost =
	     set_watch_tohost_watch_tohost ;
  assign near_mem$EN_server_reset_request_put = CAN_FIRE_RL_rl_reset_start ;
  assign near_mem$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_2 ;
  assign near_mem$EN_imem_req =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe &&
	     IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1576 ||
	     WILL_FIRE_RL_imem_rl_fetch_next_32b ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
  assign near_mem$EN_dmem_req =
	     WILL_FIRE_RL_rl_pipe &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1460 &&
	     IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 !=
	     4'd0 &&
	     IF_NOT_stage1_rg_full_00_34_OR_NOT_stage1_rg_s_ETC___d1463 &&
	     (IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d631 ==
	      3'd1 ||
	      IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d631 ==
	      3'd2 ||
	      IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d631 ==
	      3'd4) ;
  assign near_mem$EN_server_fence_i_request_put =
	     MUX_rg_state$write_1__SEL_12 ;
  assign near_mem$EN_server_fence_i_response_get =
	     CAN_FIRE_RL_rl_finish_FENCE_I ;
  assign near_mem$EN_server_fence_request_put = MUX_rg_state$write_1__SEL_13 ;
  assign near_mem$EN_server_fence_response_get = CAN_FIRE_RL_rl_finish_FENCE ;
  assign near_mem$EN_set_watch_tohost = EN_set_watch_tohost ;

  // submodule soc_map
  assign soc_map$m_is_IO_addr_addr = 64'h0 ;
  assign soc_map$m_is_mem_addr_addr = 64'h0 ;
  assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ;

  // submodule stage1_f_reset_reqs
  assign stage1_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ;
  assign stage1_f_reset_reqs$DEQ = CAN_FIRE_RL_stage1_rl_reset ;
  assign stage1_f_reset_reqs$CLR = 1'b0 ;

  // submodule stage1_f_reset_rsps
  assign stage1_f_reset_rsps$ENQ = CAN_FIRE_RL_stage1_rl_reset ;
  assign stage1_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_2 ;
  assign stage1_f_reset_rsps$CLR = 1'b0 ;

  // submodule stage2_f_reset_reqs
  assign stage2_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ;
  assign stage2_f_reset_reqs$DEQ = stage2_f_reset_reqs$EMPTY_N ;
  assign stage2_f_reset_reqs$CLR = 1'b0 ;

  // submodule stage2_f_reset_rsps
  assign stage2_f_reset_rsps$ENQ = CAN_FIRE_RL_stage2_rl_reset_end ;
  assign stage2_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_2 ;
  assign stage2_f_reset_rsps$CLR = 1'b0 ;

  // submodule stage2_mbox
  assign stage2_mbox$req_f3 = MUX_rg_trap_instr$write_1__VAL_1[14:12] ;
  assign stage2_mbox$req_is_OP_not_OP_32 =
	     !MUX_rg_trap_instr$write_1__VAL_1[3] ;
  assign stage2_mbox$req_v1 = x_out_data_to_stage2_val1__h7721 ;
  assign stage2_mbox$req_v2 = x_out_data_to_stage2_val2__h7722 ;
  assign stage2_mbox$set_verbosity_verbosity = 4'h0 ;
  assign stage2_mbox$EN_set_verbosity = 1'b0 ;
  assign stage2_mbox$EN_req_reset = 1'b0 ;
  assign stage2_mbox$EN_rsp_reset = 1'b0 ;
  assign stage2_mbox$EN_req =
	     WILL_FIRE_RL_rl_pipe &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1460 &&
	     IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 !=
	     4'd0 &&
	     IF_NOT_stage1_rg_full_00_34_OR_NOT_stage1_rg_s_ETC___d1463 &&
	     IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d631 ==
	     3'd3 ;

  // submodule stage3_f_reset_reqs
  assign stage3_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ;
  assign stage3_f_reset_reqs$DEQ = CAN_FIRE_RL_stage3_rl_reset ;
  assign stage3_f_reset_reqs$CLR = 1'b0 ;

  // submodule stage3_f_reset_rsps
  assign stage3_f_reset_rsps$ENQ = CAN_FIRE_RL_stage3_rl_reset ;
  assign stage3_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_2 ;
  assign stage3_f_reset_rsps$CLR = 1'b0 ;

  // submodule stageD_f_reset_reqs
  assign stageD_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ;
  assign stageD_f_reset_reqs$DEQ = CAN_FIRE_RL_stageD_rl_reset ;
  assign stageD_f_reset_reqs$CLR = 1'b0 ;

  // submodule stageD_f_reset_rsps
  assign stageD_f_reset_rsps$ENQ = CAN_FIRE_RL_stageD_rl_reset ;
  assign stageD_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_2 ;
  assign stageD_f_reset_rsps$CLR = 1'b0 ;

  // submodule stageF_branch_predictor
  assign stageF_branch_predictor$bp_train_cf_info =
	     (stage1_rg_full &&
	      (!stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 ||
	       NOT_IF_stage2_rg_full_6_THEN_IF_stage2_rg_stag_ETC___d1393) &&
	      IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 !=
	      4'd0) ?
	       { IF_NOT_stage1_rg_full_00_34_OR_NOT_stage1_rg_s_ETC___d571,
		 stage1_rg_stage_input[305:274],
		 stage1_rg_stage_input[151:145] != 7'b1100011 ||
		 IF_stage1_rg_stage_input_01_BITS_112_TO_110_30_ETC___d276,
		 alu_outputs_cf_info_fallthru_PC__h9496,
		 alu_outputs_cf_info_taken_PC__h9497 } :
	       99'h6AAAAAAAAAAAAAAAAAAAAAAAA ;
  assign stageF_branch_predictor$bp_train_instr = d_instr__h15515 ;
  assign stageF_branch_predictor$bp_train_is_i32_not_i16 =
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1215 ;
  assign stageF_branch_predictor$bp_train_pc = imem_rg_pc ;
  always@(MUX_imem_rg_f3$write_1__SEL_1 or
	  soc_map$m_pc_reset_value or
	  MUX_imem_rg_cache_addr$write_1__SEL_3 or
	  stageF_branch_predictor$predict_rsp or
	  MUX_rg_state$write_1__SEL_7 or rg_next_pc)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_imem_rg_f3$write_1__SEL_1:
	  stageF_branch_predictor$predict_req_pc =
	      soc_map$m_pc_reset_value[31:0];
      MUX_imem_rg_cache_addr$write_1__SEL_3:
	  stageF_branch_predictor$predict_req_pc =
	      stageF_branch_predictor$predict_rsp;
      MUX_rg_state$write_1__SEL_7:
	  stageF_branch_predictor$predict_req_pc = rg_next_pc;
      default: stageF_branch_predictor$predict_req_pc =
		   32'hAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign stageF_branch_predictor$predict_rsp_instr = d_instr__h15515 ;
  assign stageF_branch_predictor$predict_rsp_is_i32_not_i16 =
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1215 ;
  assign stageF_branch_predictor$EN_reset = 1'b0 ;
  assign stageF_branch_predictor$EN_predict_req =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe &&
	     IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1576 ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
  assign stageF_branch_predictor$EN_bp_train =
	     WILL_FIRE_RL_rl_pipe &&
	     IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1557 ;

  // submodule stageF_f_reset_reqs
  assign stageF_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ;
  assign stageF_f_reset_reqs$DEQ = CAN_FIRE_RL_stageF_rl_reset ;
  assign stageF_f_reset_reqs$CLR = 1'b0 ;

  // submodule stageF_f_reset_rsps
  assign stageF_f_reset_rsps$ENQ = CAN_FIRE_RL_stageF_rl_reset ;
  assign stageF_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_2 ;
  assign stageF_f_reset_rsps$CLR = 1'b0 ;

  // remaining internal signals
  assign IF_IF_stage1_rg_stage_input_01_BITS_151_TO_145_ETC___d813 =
	     next_pc__h7661 == stage1_rg_stage_input[183:152] ;
  assign IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1400 =
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1396 ?
	       IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 !=
	       4'd0 &&
	       !IF_IF_stage1_rg_stage_input_01_BITS_151_TO_145_ETC___d813 &&
	       stageF_rg_full &&
	       (!near_mem$imem_valid ||
		imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1211) :
	       stage1_rg_full ;
  assign IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1403 =
	     IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1400 &&
	     stageD_rg_full ||
	     !stageF_rg_full ||
	     !near_mem$imem_valid ||
	     imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1211 ;
  assign IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1516 =
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1396 ?
	       IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 ==
	       4'd0 ||
	       IF_IF_stage1_rg_stage_input_01_BITS_151_TO_145_ETC___d813 ||
	       !stageF_rg_full ||
	       near_mem$imem_valid &&
	       NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1217 :
	       !stage1_rg_full ;
  assign IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1557 =
	     (IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1516 ||
	      !stageD_rg_full) &&
	     stageF_rg_full &&
	     near_mem$imem_valid &&
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1217 ;
  assign IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1564 =
	     IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1557 &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1407 &&
	     IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 !=
	     4'd0 &&
	     !IF_IF_stage1_rg_stage_input_01_BITS_151_TO_145_ETC___d813 ;
  assign IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1576 =
	     IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1557 &&
	     (csr_regfile_interrupt_pending_rg_cur_priv_1_37_ETC___d1571 ||
	      IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 ==
	      4'd0 ||
	      IF_IF_stage1_rg_stage_input_01_BITS_151_TO_145_ETC___d813) ;
  assign IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1600 =
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1396 ?
	       IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 !=
	       4'd0 &&
	       IF_NOT_stage1_rg_full_00_34_OR_NOT_stage1_rg_s_ETC___d1432 :
	       stage1_rg_full ;
  assign IF_NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem__ETC___d1189 =
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1186 ?
	       { 16'b0,
		 imem_rg_pc_BITS_31_TO_2_0_EQ_near_mem_imem_pc__ETC___d13 ?
		   near_mem$imem_instr[31:16] :
		   imem_rg_cache_b16 } :
	       near_mem$imem_instr ;
  assign IF_NOT_near_mem_dmem_valid__18_37_OR_NOT_near__ETC___d184 =
	     (!near_mem$dmem_valid || !near_mem$dmem_exc) ?
	       ((stage2_rg_stage2[100:96] == 5'd0) ? 2'd0 : 2'd1) :
	       2'd0 ;
  assign IF_NOT_stage1_rg_full_00_34_OR_NOT_stage1_rg_s_ETC___d1432 =
	     !IF_IF_stage1_rg_stage_input_01_BITS_151_TO_145_ETC___d813 &&
	     stageF_rg_full &&
	     (!near_mem$imem_valid ||
	      imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1211) ;
  assign IF_NOT_stage1_rg_full_00_34_OR_NOT_stage1_rg_s_ETC___d1463 =
	     IF_IF_stage1_rg_stage_input_01_BITS_151_TO_145_ETC___d813 ||
	     !stageF_rg_full ||
	     near_mem$imem_valid &&
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1217 ;
  assign IF_NOT_stage1_rg_stage_input_01_BITS_112_TO_11_ETC___d438 =
	     NOT_stage1_rg_stage_input_01_BITS_112_TO_110_3_ETC___d306 ?
	       4'd12 :
	       4'd1 ;
  assign IF_csr_regfile_read_csr_rg_trap_instr_644_BITS_ETC___d1697 =
	     csr_regfile$read_csr[31:0] | rs1_val__h22743 ;
  assign IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1041 =
	     (csr_regfile$read_misa[2] && stageD_rg_data[33:32] == 2'b01 &&
	      stageD_rg_data[47:42] == 6'b100011 &&
	      stageD_rg_data[38:37] == 2'b0) ?
	       instr__h14960 :
	       ((csr_regfile$read_misa[2] && stageD_rg_data[33:32] == 2'b10 &&
		 stageD_rg_data[47:44] == 4'b1001 &&
		 stageD_rg_data[43:39] == 5'd0 &&
		 stageD_rg_data[38:34] == 5'd0) ?
		  instr__h15298 :
		  32'h0) ;
  assign IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1043 =
	     (csr_regfile$read_misa[2] && stageD_rg_data[33:32] == 2'b01 &&
	      stageD_rg_data[47:42] == 6'b100011 &&
	      stageD_rg_data[38:37] == 2'b10) ?
	       instr__h14688 :
	       ((csr_regfile$read_misa[2] && stageD_rg_data[33:32] == 2'b01 &&
		 stageD_rg_data[47:42] == 6'b100011 &&
		 stageD_rg_data[38:37] == 2'b01) ?
		  instr__h14824 :
		  IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1041) ;
  assign IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1045 =
	     (csr_regfile_read_misa__9_BIT_2_28_AND_stageD_r_ETC___d912 &&
	      stageD_rg_data[38:34] != 5'd0) ?
	       instr__h14457 :
	       ((csr_regfile$read_misa[2] && stageD_rg_data[33:32] == 2'b01 &&
		 stageD_rg_data[47:42] == 6'b100011 &&
		 stageD_rg_data[38:37] == 2'b11) ?
		  instr__h14552 :
		  IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1043) ;
  assign IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1046 =
	     (csr_regfile_read_misa__9_BIT_2_28_AND_stageD_r_ETC___d906 &&
	      stageD_rg_data[38:34] != 5'd0) ?
	       instr__h14338 :
	       IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1045 ;
  assign IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1048 =
	     (csr_regfile$read_misa[2] && stageD_rg_data[33:32] == 2'b01 &&
	      stageD_rg_data[47:45] == 3'b100 &&
	      stageD_rg_data[43:42] == 2'b01 &&
	      imm6__h12484 != 6'd0 &&
	      !stageD_rg_data[44]) ?
	       instr__h14043 :
	       ((csr_regfile$read_misa[2] && stageD_rg_data[33:32] == 2'b01 &&
		 stageD_rg_data[47:45] == 3'b100 &&
		 stageD_rg_data[43:42] == 2'b10) ?
		  instr__h14160 :
		  IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1046) ;
  assign IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1049 =
	     (csr_regfile$read_misa[2] && stageD_rg_data[33:32] == 2'b01 &&
	      stageD_rg_data[47:45] == 3'b100 &&
	      stageD_rg_data[43:42] == 2'b0 &&
	      imm6__h12484 != 6'd0 &&
	      !stageD_rg_data[44]) ?
	       instr__h13850 :
	       IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1048 ;
  assign IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1050 =
	     (csr_regfile$read_misa[2] && stageD_rg_data[33:32] == 2'b10 &&
	      stageD_rg_data[47:45] == 3'b0 &&
	      stageD_rg_data[43:39] != 5'd0 &&
	      imm6__h12484 != 6'd0 &&
	      !stageD_rg_data[44]) ?
	       instr__h13657 :
	       IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1049 ;
  assign IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1052 =
	     (csr_regfile$read_misa[2] && stageD_rg_data[33:32] == 2'b01 &&
	      stageD_rg_data[47:45] == 3'b011 &&
	      stageD_rg_data[43:39] == 5'd2 &&
	      nzimm10__h13108 != 10'd0) ?
	       instr__h13312 :
	       ((csr_regfile$read_misa[2] && stageD_rg_data[33:32] == 2'b0 &&
		 stageD_rg_data[47:45] == 3'b0 &&
		 nzimm10__h13323 != 10'd0) ?
		  instr__h13484 :
		  IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1050) ;
  assign IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1053 =
	     (csr_regfile$read_misa[2] && stageD_rg_data[33:32] == 2'b01 &&
	      stageD_rg_data[47:45] == 3'b0 &&
	      stageD_rg_data[43:39] != 5'd0 &&
	      imm6__h12484 != 6'd0 ||
	      csr_regfile$read_misa[2] && stageD_rg_data[33:32] == 2'b01 &&
	      stageD_rg_data[47:45] == 3'b0 &&
	      stageD_rg_data[43:39] == 5'd0 &&
	      imm6__h12484 == 6'd0) ?
	       instr__h12875 :
	       IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1052 ;
  assign IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1054 =
	     (csr_regfile$read_misa[2] && stageD_rg_data[33:32] == 2'b01 &&
	      stageD_rg_data[47:45] == 3'b011 &&
	      stageD_rg_data[43:39] != 5'd0 &&
	      stageD_rg_data[43:39] != 5'd2 &&
	      imm6__h12484 != 6'd0) ?
	       instr__h12746 :
	       IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1053 ;
  assign IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1056 =
	     (csr_regfile$read_misa[2] && stageD_rg_data[33:32] == 2'b01 &&
	      stageD_rg_data[47:45] == 3'b111) ?
	       instr__h12224 :
	       ((csr_regfile$read_misa[2] && stageD_rg_data[33:32] == 2'b01 &&
		 stageD_rg_data[47:45] == 3'b010 &&
		 stageD_rg_data[43:39] != 5'd0) ?
		  instr__h12562 :
		  IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1054) ;
  assign IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1057 =
	     (csr_regfile$read_misa[2] && stageD_rg_data[33:32] == 2'b01 &&
	      stageD_rg_data[47:45] == 3'b110) ?
	       instr__h11907 :
	       IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1056 ;
  assign IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1058 =
	     (csr_regfile_read_misa__9_BIT_2_28_AND_stageD_r_ETC___d912 &&
	      stageD_rg_data[38:34] == 5'd0) ?
	       instr__h11842 :
	       IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1057 ;
  assign IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1059 =
	     (csr_regfile_read_misa__9_BIT_2_28_AND_stageD_r_ETC___d906 &&
	      stageD_rg_data[38:34] == 5'd0) ?
	       instr__h11726 :
	       IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1058 ;
  assign IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1060 =
	     (csr_regfile$read_misa[2] && stageD_rg_data[33:32] == 2'b01 &&
	      stageD_rg_data[47:45] == 3'b001) ?
	       instr__h11336 :
	       IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1059 ;
  assign IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1061 =
	     (csr_regfile$read_misa[2] && stageD_rg_data[33:32] == 2'b01 &&
	      stageD_rg_data[47:45] == 3'b101) ?
	       instr__h10994 :
	       IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1060 ;
  assign IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1062 =
	     (csr_regfile$read_misa[2] && stageD_rg_data[33:32] == 2'b0 &&
	      stageD_rg_data[47:45] == 3'b110) ?
	       instr__h10765 :
	       IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1061 ;
  assign IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1063 =
	     (csr_regfile$read_misa[2] && stageD_rg_data[33:32] == 2'b0 &&
	      stageD_rg_data[47:45] == 3'b010) ?
	       instr__h10570 :
	       IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1062 ;
  assign IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1064 =
	     (csr_regfile$read_misa[2] && stageD_rg_data[33:32] == 2'b10 &&
	      stageD_rg_data[47:45] == 3'b110) ?
	       instr__h10378 :
	       IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1063 ;
  assign IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg_p_ETC___d1190 =
	     (imem_rg_pc[1:0] == 2'b0 &&
	      imem_rg_pc_BITS_31_TO_2_0_EQ_near_mem_imem_pc__ETC___d13 &&
	      near_mem$imem_instr[1:0] != 2'b11) ?
	       instr_out___1__h15539 :
	       IF_NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem__ETC___d1189 ;
  assign IF_near_mem_dmem_valid__18_THEN_IF_near_mem_dm_ETC___d121 =
	     near_mem$dmem_valid ? (near_mem$dmem_exc ? 2'd3 : 2'd2) : 2'd1 ;
  assign IF_rg_cur_priv_1_EQ_0b11_52_AND_stage1_rg_stag_ETC___d466 =
	     (rg_cur_priv == 2'b11 &&
	      stage1_rg_stage_input[87:76] == 12'b001100000010) ?
	       4'd8 :
	       (rg_cur_priv_1_EQ_0b11_52_OR_rg_cur_priv_1_EQ_0_ETC___d464 ?
		  4'd11 :
		  4'd12) ;
  assign IF_stage1_rg_stage_input_01_BITS_139_TO_135_04_ETC___d265 =
	     rs1_val_bypassed__h4853 == rs2_val_bypassed__h4859 ;
  assign IF_stage1_rg_stage_input_01_BITS_139_TO_135_04_ETC___d267 =
	     (rs1_val_bypassed__h4853 ^ 32'h80000000) <
	     (rs2_val_bypassed__h4859 ^ 32'h80000000) ;
  assign IF_stage1_rg_stage_input_01_BITS_139_TO_135_04_ETC___d269 =
	     rs1_val_bypassed__h4853 < rs2_val_bypassed__h4859 ;
  assign IF_stage1_rg_stage_input_01_BITS_151_TO_145_28_ETC___d364 =
	     (stage1_rg_stage_input[151:145] == 7'b1100011) ?
	       stage1_rg_stage_input[112:110] != 3'b0 &&
	       stage1_rg_stage_input[112:110] != 3'b001 &&
	       stage1_rg_stage_input[112:110] != 3'b100 &&
	       stage1_rg_stage_input[112:110] != 3'b101 &&
	       stage1_rg_stage_input[112:110] != 3'b110 &&
	       stage1_rg_stage_input[112:110] != 3'b111 ||
	       IF_stage1_rg_stage_input_01_BITS_112_TO_110_30_ETC___d276 :
	       (stage1_rg_stage_input[151:145] != 7'b0110011 ||
		stage1_rg_stage_input[104:98] != 7'b0000001) &&
	       (((stage1_rg_stage_input[151:145] == 7'b0010011 ||
		  stage1_rg_stage_input[151:145] == 7'b0110011) &&
		 (stage1_rg_stage_input[112:110] == 3'b001 ||
		  stage1_rg_stage_input[112:110] == 3'b101)) ?
		  stage1_rg_stage_input[81] :
		  CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q9) ;
  assign IF_stage1_rg_stage_input_01_BITS_151_TO_145_28_ETC___d375 =
	     (stage1_rg_stage_input[151:145] == 7'b1100011) ?
	       stage1_rg_stage_input[112:110] != 3'b0 &&
	       stage1_rg_stage_input[112:110] != 3'b001 &&
	       stage1_rg_stage_input[112:110] != 3'b100 &&
	       stage1_rg_stage_input[112:110] != 3'b101 &&
	       stage1_rg_stage_input[112:110] != 3'b110 &&
	       stage1_rg_stage_input[112:110] != 3'b111 ||
	       IF_stage1_rg_stage_input_01_BITS_112_TO_110_30_ETC___d370 :
	       stage1_rg_stage_input[151:145] != 7'b1101111 &&
	       stage1_rg_stage_input[151:145] != 7'b1100111 ;
  assign IF_stage1_rg_stage_input_01_BITS_151_TO_145_28_ETC___d425 =
	     (stage1_rg_stage_input[151:145] == 7'b1100011) ?
	       (stage1_rg_stage_input[112:110] == 3'b0 ||
		stage1_rg_stage_input[112:110] == 3'b001 ||
		stage1_rg_stage_input[112:110] == 3'b100 ||
		stage1_rg_stage_input[112:110] == 3'b101 ||
		stage1_rg_stage_input[112:110] == 3'b110 ||
		stage1_rg_stage_input[112:110] == 3'b111) &&
	       IF_stage1_rg_stage_input_01_BITS_112_TO_110_30_ETC___d370 :
	       stage1_rg_stage_input[151:145] == 7'b0110011 &&
	       stage1_rg_stage_input[104:98] == 7'b0000001 ||
	       (((stage1_rg_stage_input[151:145] == 7'b0010011 ||
		  stage1_rg_stage_input[151:145] == 7'b0110011) &&
		 (stage1_rg_stage_input[112:110] == 3'b001 ||
		  stage1_rg_stage_input[112:110] == 3'b101)) ?
		  !stage1_rg_stage_input[81] :
		  CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q11) ;
  assign IF_stage1_rg_stage_input_01_BITS_151_TO_145_28_ETC___d427 =
	     (stage1_rg_stage_input[151:145] == 7'b1100011) ?
	       (stage1_rg_stage_input[112:110] == 3'b0 ||
		stage1_rg_stage_input[112:110] == 3'b001 ||
		stage1_rg_stage_input[112:110] == 3'b100 ||
		stage1_rg_stage_input[112:110] == 3'b101 ||
		stage1_rg_stage_input[112:110] == 3'b110 ||
		stage1_rg_stage_input[112:110] == 3'b111) &&
	       IF_stage1_rg_stage_input_01_BITS_112_TO_110_30_ETC___d276 :
	       stage1_rg_stage_input[151:145] == 7'b1101111 ||
	       stage1_rg_stage_input[151:145] == 7'b1100111 ;
  assign IF_stage1_rg_stage_input_01_BITS_151_TO_145_28_ETC___d730 =
	     ((stage1_rg_stage_input[151:145] == 7'b0010011 ||
	       stage1_rg_stage_input[151:145] == 7'b0110011) &&
	      (stage1_rg_stage_input[112:110] == 3'b001 ||
	       stage1_rg_stage_input[112:110] == 3'b101)) ?
	       alu_outputs___1_val1__h7992 :
	       IF_stage1_rg_stage_input_01_BITS_151_TO_145_28_ETC___d729 ;
  assign IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 =
	     stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 ?
	       (stage1_rg_stage_input[268] ?
		  4'd12 :
		  IF_stage1_rg_stage_input_01_BITS_151_TO_145_28_ETC___d486) :
	       4'd0 ;
  assign IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d631 =
	     stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 ?
	       CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q20 :
	       3'd0 ;
  assign IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 =
	     stage2_rg_full ?
	       CASE_stage2_rg_stage2_BITS_103_TO_101_0_2_1_IF_ETC__q5 :
	       2'd0 ;
  assign IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d1385 =
	     IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d188 ==
	     2'd1 &&
	     (IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d205 ||
	      IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d207) ||
	     stage1_rg_stage_input[268] ||
	     IF_stage1_rg_stage_input_01_BITS_151_TO_145_28_ETC___d364 &&
	     IF_stage1_rg_stage_input_01_BITS_151_TO_145_28_ETC___d375 ;
  assign IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d188 =
	     stage2_rg_full ?
	       CASE_stage2_rg_stage2_BITS_103_TO_101_0_2_1_IF_ETC__q6 :
	       2'd0 ;
  assign IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d205 =
	     x_out_bypass_rd__h7431 == stage1_rg_stage_input[139:135] ;
  assign IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d207 =
	     x_out_bypass_rd__h7431 == stage1_rg_stage_input[134:130] ;
  assign IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d430 =
	     IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d188 ==
	     2'd1 &&
	     (IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d205 ||
	      IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d207) ||
	     !stage1_rg_stage_input[268] &&
	     (IF_stage1_rg_stage_input_01_BITS_151_TO_145_28_ETC___d425 ||
	      IF_stage1_rg_stage_input_01_BITS_151_TO_145_28_ETC___d427) ;
  assign IF_stage2_rg_stage2_7_BITS_103_TO_101_8_EQ_3_0_ETC___d124 =
	     stage2_mbox$valid ? 2'd2 : 2'd1 ;
  assign NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49 =
	     cur_verbosity__h3333 > 4'd1 ;
  assign NOT_IF_stage2_rg_full_6_THEN_IF_stage2_rg_stag_ETC___d1393 =
	     (IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d188 !=
	      2'd1 ||
	      !IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d205 &&
	      !IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d207) &&
	     !stage1_rg_stage_input[268] &&
	     (IF_stage1_rg_stage_input_01_BITS_151_TO_145_28_ETC___d425 ||
	      IF_stage1_rg_stage_input_01_BITS_151_TO_145_28_ETC___d427) ;
  assign NOT_IF_stage2_rg_full_6_THEN_IF_stage2_rg_stag_ETC___d378 =
	     (IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d188 !=
	      2'd1 ||
	      !IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d205 &&
	      !IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d207) &&
	     (stage1_rg_stage_input[268] ||
	      IF_stage1_rg_stage_input_01_BITS_151_TO_145_28_ETC___d364 &&
	      IF_stage1_rg_stage_input_01_BITS_151_TO_145_28_ETC___d375) ;
  assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1392 =
	     (!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
	      stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d1388) &&
	     (IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 ==
	      2'd2 ||
	      IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 ==
	      2'd0) ;
  assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1396 =
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1392 &&
	     stage1_rg_full &&
	     (!stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 ||
	      NOT_IF_stage2_rg_full_6_THEN_IF_stage2_rg_stag_ETC___d1393) ;
  assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1405 =
	     !csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
	     stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 &&
	     IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d1385 &&
	     IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d430 ;
  assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1407 =
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1405 &&
	     (IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 ==
	      2'd2 ||
	      IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 ==
	      2'd0) &&
	     stage1_rg_full &&
	     (!stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 ||
	      NOT_IF_stage2_rg_full_6_THEN_IF_stage2_rg_stag_ETC___d1393) ;
  assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1413 =
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1407 &&
	     IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 !=
	     4'd0 &&
	     !IF_IF_stage1_rg_stage_input_01_BITS_151_TO_145_ETC___d813 ||
	     (imem_rg_pc[1:0] == 2'b0 ||
	      !imem_rg_pc_BITS_31_TO_2_0_EQ_near_mem_imem_pc__ETC___d13 ||
	      near_mem$imem_instr[17:16] != 2'b11) &&
	     stageF_branch_predictor$RDY_predict_req ;
  assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1435 =
	     !csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
	     NOT_stage1_rg_full_00_34_OR_stage1_rg_stage_in_ETC___d1428 ||
	     NOT_stage1_rg_full_00_34_OR_stage1_rg_stage_in_ETC___d1430 ||
	     IF_NOT_stage1_rg_full_00_34_OR_NOT_stage1_rg_s_ETC___d1432 ||
	     IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 !=
	     2'd0 ||
	     stage3_rg_full ;
  assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1453 =
	     (!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
	      !stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 ||
	      IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d430) &&
	     (IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 ==
	      2'd2 ||
	      IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 ==
	      2'd0) ;
  assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1460 =
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1405 &&
	     (IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 ==
	      2'd2 ||
	      IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 ==
	      2'd0) &&
	     stage1_rg_full &&
	     (!stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 ||
	      NOT_IF_stage2_rg_full_6_THEN_IF_stage2_rg_stag_ETC___d1393) ;
  assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1490 =
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1460 &&
	     IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 !=
	     4'd0 &&
	     IF_NOT_stage1_rg_full_00_34_OR_NOT_stage1_rg_s_ETC___d1463 &&
	     NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49 ;
  assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1513 =
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1460 &&
	     IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 !=
	     4'd0 &&
	     IF_NOT_stage1_rg_full_00_34_OR_NOT_stage1_rg_s_ETC___d1463 &&
	     !IF_IF_stage1_rg_stage_input_01_BITS_151_TO_145_ETC___d813 ;
  assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1619 =
	     !csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
	     !stage1_rg_stage_input[268] &&
	     (IF_stage1_rg_stage_input_01_BITS_151_TO_145_28_ETC___d425 ||
	      IF_stage1_rg_stage_input_01_BITS_151_TO_145_28_ETC___d427) ;
  assign NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1172 =
	     imem_rg_pc[1:0] != 2'b0 &&
	     imem_rg_pc_BITS_31_TO_2_0_EQ_imem_rg_cache_add_ETC___d1164 &&
	     near_mem_imem_pc__1_EQ_imem_rg_pc_PLUS_2_166___d1167 &&
	     imem_rg_cache_b16[1:0] == 2'b11 ;
  assign NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1186 =
	     imem_rg_pc[1:0] != 2'b0 &&
	     (imem_rg_pc_BITS_31_TO_2_0_EQ_near_mem_imem_pc__ETC___d13 &&
	      near_mem$imem_instr[17:16] != 2'b11 ||
	      imem_rg_pc_BITS_31_TO_2_0_EQ_imem_rg_cache_add_ETC___d1164 &&
	      imem_rg_cache_b16[1:0] != 2'b11) ;
  assign NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1215 =
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1172 ||
	     imem_rg_pc[1:0] == 2'b0 &&
	     imem_rg_pc_BITS_31_TO_2_0_EQ_near_mem_imem_pc__ETC___d13 &&
	     near_mem$imem_instr[1:0] == 2'b11 ;
  assign NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1217 =
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1215 ||
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1186 ||
	     imem_rg_pc[1:0] == 2'b0 &&
	     imem_rg_pc_BITS_31_TO_2_0_EQ_near_mem_imem_pc__ETC___d13 &&
	     near_mem$imem_instr[1:0] != 2'b11 ;
  assign NOT_rg_next_pc_708_BITS_1_TO_0_709_EQ_0b0_710__ETC___d1717 =
	     rg_next_pc[1:0] != 2'b0 && near_mem$imem_valid &&
	     addr_of_b32__h28481 == near_mem$imem_pc &&
	     near_mem$imem_instr[17:16] == 2'b11 ;
  assign NOT_soc_map_m_pc_reset_value__362_BITS_1_TO_0__ETC___d1376 =
	     soc_map$m_pc_reset_value[1:0] != 2'b0 && near_mem$imem_valid &&
	     addr_of_b32__h17342 == near_mem$imem_pc &&
	     near_mem$imem_instr[17:16] == 2'b11 ;
  assign NOT_stage1_rg_full_00_34_OR_stage1_rg_stage_in_ETC___d1428 =
	     (!stage1_rg_full ||
	      stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 &&
	      IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d1385 ||
	      IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 ==
	      4'd0) &&
	     (!stage1_rg_full ||
	      !stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 ||
	      IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d430) ;
  assign NOT_stage1_rg_full_00_34_OR_stage1_rg_stage_in_ETC___d1430 =
	     (!stage1_rg_full ||
	      stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 &&
	      IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d1385) &&
	     (!stage1_rg_full ||
	      !stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 ||
	      IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d430) ;
  assign NOT_stage1_rg_stage_input_01_BITS_112_TO_110_3_ETC___d306 =
	     (stage1_rg_stage_input[112:110] != 3'b0 ||
	      stage1_rg_stage_input[151:145] == 7'b0110011 &&
	      stage1_rg_stage_input[230]) &&
	     (stage1_rg_stage_input[112:110] != 3'b0 ||
	      stage1_rg_stage_input[151:145] != 7'b0110011 ||
	      !stage1_rg_stage_input[230]) &&
	     stage1_rg_stage_input[112:110] != 3'b010 &&
	     stage1_rg_stage_input[112:110] != 3'b011 &&
	     stage1_rg_stage_input[112:110] != 3'b100 &&
	     stage1_rg_stage_input[112:110] != 3'b110 &&
	     stage1_rg_stage_input[112:110] != 3'b111 ;
  assign NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d1761 =
	     (!stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 ||
	      NOT_IF_stage2_rg_full_6_THEN_IF_stage2_rg_stag_ETC___d1393) &&
	     IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 !=
	     4'd0 ||
	     stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 &&
	     NOT_IF_stage2_rg_full_6_THEN_IF_stage2_rg_stag_ETC___d378 ;
  assign NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d1765 =
	     NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d1761 &&
	     stage1_rg_full &&
	     (!stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 ||
	      NOT_IF_stage2_rg_full_6_THEN_IF_stage2_rg_stag_ETC___d1393 ||
	      NOT_IF_stage2_rg_full_6_THEN_IF_stage2_rg_stag_ETC___d378) &&
	     IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 ==
	     2'd0 &&
	     !stage3_rg_full ;
  assign NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d382 =
	     !stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 ||
	     IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d188 !=
	     2'd1 ||
	     !IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d205 &&
	     !IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d207 ;
  assign NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d562 =
	     (!stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 ||
	      IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d430) &&
	     IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 !=
	     4'd0 &&
	     IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 !=
	     4'd1 &&
	     IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 !=
	     4'd2 &&
	     IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 !=
	     4'd3 &&
	     IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 !=
	     4'd4 &&
	     IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 !=
	     4'd5 &&
	     IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 !=
	     4'd6 &&
	     IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 !=
	     4'd7 &&
	     IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 !=
	     4'd8 &&
	     IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 !=
	     4'd9 &&
	     IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 !=
	     4'd10 &&
	     IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 !=
	     4'd11 ;
  assign NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d574 =
	     NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d382 &&
	     (!stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 ||
	      IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d430) &&
	     IF_NOT_stage1_rg_full_00_34_OR_NOT_stage1_rg_s_ETC___d571 ==
	     2'd3 ;
  assign NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d578 =
	     NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d382 &&
	     (!stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 ||
	      IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d430) &&
	     IF_NOT_stage1_rg_full_00_34_OR_NOT_stage1_rg_s_ETC___d571 ==
	     2'd0 ;
  assign NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d584 =
	     NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d382 &&
	     (!stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 ||
	      IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d430) &&
	     IF_NOT_stage1_rg_full_00_34_OR_NOT_stage1_rg_s_ETC___d571 !=
	     2'd3 &&
	     IF_NOT_stage1_rg_full_00_34_OR_NOT_stage1_rg_s_ETC___d571 !=
	     2'd0 ;
  assign NOT_stageF_branch_predictor_predict_rsp_NOT_im_ETC___d1585 =
	     stageF_branch_predictor$predict_rsp[1:0] != 2'b0 &&
	     near_mem$imem_valid &&
	     addr_of_b32__h20424 == near_mem$imem_pc &&
	     near_mem$imem_instr[17:16] == 2'b11 ;
  assign SEXT_stage1_rg_stage_input_01_BITS_87_TO_76_48___d599 =
	     { {20{stage1_rg_stage_input_BITS_87_TO_76__q17[11]}},
	       stage1_rg_stage_input_BITS_87_TO_76__q17 } ;
  assign SEXT_stageD_rg_data_23_BIT_44_40_CONCAT_stageD_ETC___d892 =
	     { {9{offset__h10941[11]}}, offset__h10941 } ;
  assign SEXT_stageD_rg_data_23_BIT_44_40_CONCAT_stageD_ETC___d921 =
	     { {4{offset__h11851[8]}}, offset__h11851 } ;
  assign _theResult_____1_fst__h8738 =
	     (stage1_rg_stage_input[112:110] == 3'b0 &&
	      stage1_rg_stage_input[151:145] == 7'b0110011 &&
	      stage1_rg_stage_input[230]) ?
	       rd_val___1__h8734 :
	       _theResult_____1_fst__h8745 ;
  assign _theResult_____1_fst__h8773 =
	     rs1_val_bypassed__h4853 & _theResult___snd__h9832 ;
  assign _theResult____h21590 =
	     (delta_CPI_instrs__h21589 == 64'd0) ?
	       delta_CPI_instrs___1__h21625 :
	       delta_CPI_instrs__h21589 ;
  assign _theResult____h5124 = x_out_data_to_stage1_instr__h10032 ;
  assign _theResult___snd__h9832 =
	     (stage1_rg_stage_input[151:145] == 7'b0010011) ?
	       SEXT_stage1_rg_stage_input_01_BITS_87_TO_76_48___d599 :
	       rs2_val_bypassed__h4859 ;
  assign addr_of_b32___1__h17454 = addr_of_b32__h17342 + 32'd4 ;
  assign addr_of_b32___1__h20536 = addr_of_b32__h20424 + 32'd4 ;
  assign addr_of_b32___1__h28593 = addr_of_b32__h28481 + 32'd4 ;
  assign addr_of_b32__h17342 = { soc_map$m_pc_reset_value[31:2], 2'd0 } ;
  assign addr_of_b32__h20424 =
	     { stageF_branch_predictor$predict_rsp[31:2], 2'd0 } ;
  assign addr_of_b32__h28481 = { rg_next_pc[31:2], 2'd0 } ;
  assign alu_outputs___1_addr__h7875 =
	     IF_stage1_rg_stage_input_01_BITS_112_TO_110_30_ETC___d276 ?
	       branch_target__h7852 :
	       x_out_cf_info_fallthru_PC__h9504 ;
  assign alu_outputs___1_addr__h8095 =
	     rs1_val_bypassed__h4853 +
	     { {20{stage1_rg_stage_input_BITS_75_TO_64__q7[11]}},
	       stage1_rg_stage_input_BITS_75_TO_64__q7 } ;
  assign alu_outputs___1_exc_code__h8280 =
	     (stage1_rg_stage_input[112:110] == 3'b0) ?
	       ((stage1_rg_stage_input[144:140] == 5'd0 &&
		 stage1_rg_stage_input[139:135] == 5'd0) ?
		  CASE_stage1_rg_stage_input_BITS_87_TO_76_0b0_C_ETC__q4 :
		  4'd2) :
	       4'd2 ;
  assign alu_outputs___1_val1__h7992 =
	     (stage1_rg_stage_input[112:110] == 3'b001) ?
	       rd_val__h9729 :
	       (stage1_rg_stage_input[230] ? rd_val__h9802 : rd_val__h9780) ;
  assign alu_outputs___1_val1__h8028 =
	     (stage1_rg_stage_input[112:110] == 3'b0 &&
	      (stage1_rg_stage_input[151:145] != 7'b0110011 ||
	       !stage1_rg_stage_input[230])) ?
	       rd_val___1__h8726 :
	       _theResult_____1_fst__h8738 ;
  assign alu_outputs___1_val1__h8284 =
	     stage1_rg_stage_input[112] ?
	       { 27'd0, stage1_rg_stage_input[139:135] } :
	       rs1_val_bypassed__h4853 ;
  assign alu_outputs___1_val1__h8304 =
	     { 25'd0, stage1_rg_stage_input[104:98] } ;
  assign alu_outputs_cf_info_fallthru_PC__h9496 =
	     x_out_cf_info_fallthru_PC__h9504 ;
  assign alu_outputs_cf_info_taken_PC__h9497 = x_out_cf_info_taken_PC__h9505 ;
  assign branch_target__h7852 =
	     stage1_rg_stage_input[305:274] +
	     { {19{stage1_rg_stage_input_BITS_63_TO_51__q1[12]}},
	       stage1_rg_stage_input_BITS_63_TO_51__q1 } ;
  assign cpi__h21592 = x__h21591 / 64'd10 ;
  assign cpifrac__h21593 = x__h21591 % 64'd10 ;
  assign csr_regfile_RDY_server_reset_request_put__317__ETC___d1329 =
	     csr_regfile$RDY_server_reset_request_put &&
	     f_reset_reqs$EMPTY_N &&
	     stageF_f_reset_reqs$FULL_N &&
	     stageD_f_reset_reqs$FULL_N &&
	     stage1_f_reset_reqs$FULL_N &&
	     stage2_f_reset_reqs$FULL_N &&
	     stage3_f_reset_reqs$FULL_N ;
  assign csr_regfile_RDY_server_reset_response_get__336_ETC___d1357 =
	     csr_regfile$RDY_server_reset_response_get &&
	     stageF_f_reset_rsps$EMPTY_N &&
	     stageD_f_reset_rsps$EMPTY_N &&
	     stage1_f_reset_rsps$EMPTY_N &&
	     stage2_f_reset_rsps$EMPTY_N &&
	     stage3_f_reset_rsps$EMPTY_N &&
	     f_reset_rsps_i_notFull__342_AND_NOT_rg_run_on__ETC___d1351 ;
  assign csr_regfile_interrupt_pending_rg_cur_priv_1_37_ETC___d1567 =
	     (csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) &&
	     (!stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 ||
	      NOT_IF_stage2_rg_full_6_THEN_IF_stage2_rg_stag_ETC___d1393 ||
	      NOT_IF_stage2_rg_full_6_THEN_IF_stage2_rg_stag_ETC___d378) ;
  assign csr_regfile_interrupt_pending_rg_cur_priv_1_37_ETC___d1571 =
	     csr_regfile_interrupt_pending_rg_cur_priv_1_37_ETC___d1567 ||
	     IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 !=
	     2'd2 &&
	     IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 !=
	     2'd0 ||
	     !stage1_rg_full ||
	     stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 &&
	     IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d1385 ;
  assign csr_regfile_interrupt_pending_rg_cur_priv_1_37_ETC___d1574 =
	     (csr_regfile_interrupt_pending_rg_cur_priv_1_37_ETC___d1571 ||
	      IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 ==
	      4'd0 ||
	      IF_IF_stage1_rg_stage_input_01_BITS_151_TO_145_ETC___d813) &&
	     NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49 ;
  assign csr_regfile_interrupt_pending_rg_cur_priv_1_37_ETC___d1609 =
	     csr_regfile_interrupt_pending_rg_cur_priv_1_37_ETC___d1571 ||
	     IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 ==
	     4'd0 ||
	     IF_IF_stage1_rg_stage_input_01_BITS_151_TO_145_ETC___d813 ||
	     IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1400 &&
	     stageD_rg_full ;
  assign csr_regfile_read_csr_mcycle__0_MINUS_rg_start__ETC___d1647 =
	     delta_CPI_cycles__h21588 * 64'd10 ;
  assign csr_regfile_read_misa__9_BIT_2_28_AND_stageD_r_ETC___d906 =
	     csr_regfile$read_misa[2] && stageD_rg_data[33:32] == 2'b10 &&
	     stageD_rg_data[47:44] == 4'b1000 &&
	     stageD_rg_data[43:39] != 5'd0 ;
  assign csr_regfile_read_misa__9_BIT_2_28_AND_stageD_r_ETC___d912 =
	     csr_regfile$read_misa[2] && stageD_rg_data[33:32] == 2'b10 &&
	     stageD_rg_data[47:44] == 4'b1001 &&
	     stageD_rg_data[43:39] != 5'd0 ;
  assign cur_verbosity__h3333 =
	     (csr_regfile$read_csr_minstret < cfg_logdelay) ?
	       4'd0 :
	       cfg_verbosity ;
  assign d_instr__h15515 =
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1172 ?
	       instr_out___1__h15517 :
	       IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg_p_ETC___d1190 ;
  assign data_to_stage2_addr__h7710 = x_out_data_to_stage2_addr__h7720 ;
  assign data_to_stage2_rd__h7709 =
	     (stage1_rg_stage_input[151:145] == 7'b1100011) ?
	       5'd0 :
	       stage1_rg_stage_input[144:140] ;
  assign decoded_instr_funct10__h19112 =
	     { _theResult____h5124[31:25], _theResult____h5124[14:12] } ;
  assign decoded_instr_imm12_S__h19114 =
	     { _theResult____h5124[31:25], _theResult____h5124[11:7] } ;
  assign decoded_instr_imm13_SB__h19115 =
	     { _theResult____h5124[31],
	       _theResult____h5124[7],
	       _theResult____h5124[30:25],
	       _theResult____h5124[11:8],
	       1'b0 } ;
  assign decoded_instr_imm21_UJ__h19117 =
	     { _theResult____h5124[31],
	       _theResult____h5124[19:12],
	       _theResult____h5124[20],
	       _theResult____h5124[30:21],
	       1'b0 } ;
  assign delta_CPI_cycles__h21588 =
	     csr_regfile$read_csr_mcycle - rg_start_CPI_cycles ;
  assign delta_CPI_instrs___1__h21625 = delta_CPI_instrs__h21589 + 64'd1 ;
  assign delta_CPI_instrs__h21589 =
	     csr_regfile$read_csr_minstret - rg_start_CPI_instrs ;
  assign eaddr__h8065 =
	     rs1_val_bypassed__h4853 +
	     SEXT_stage1_rg_stage_input_01_BITS_87_TO_76_48___d599 ;
  assign f_reset_rsps_i_notFull__342_AND_NOT_rg_run_on__ETC___d1351 =
	     f_reset_rsps$FULL_N &&
	     (!rg_run_on_reset ||
	      imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d1347 &&
	      stageF_branch_predictor$RDY_predict_req) ;
  assign fall_through_pc__h7660 =
	     stage1_rg_stage_input[305:274] +
	     (stage1_rg_stage_input[269] ? 32'd4 : 32'd2) ;
  assign imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1204 =
	     (imem_rg_pc[1:0] == 2'b0 ||
	      !imem_rg_pc_BITS_31_TO_2_0_EQ_imem_rg_cache_add_ETC___d1164 ||
	      !near_mem_imem_pc__1_EQ_imem_rg_pc_PLUS_2_166___d1167 ||
	      imem_rg_cache_b16[1:0] != 2'b11) &&
	     (imem_rg_pc[1:0] != 2'b0 ||
	      !imem_rg_pc_BITS_31_TO_2_0_EQ_near_mem_imem_pc__ETC___d13 ||
	      near_mem$imem_instr[1:0] != 2'b11) ;
  assign imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1208 =
	     imem_rg_pc[1:0] == 2'b0 ||
	     (!imem_rg_pc_BITS_31_TO_2_0_EQ_near_mem_imem_pc__ETC___d13 ||
	      near_mem$imem_instr[17:16] == 2'b11) &&
	     (!imem_rg_pc_BITS_31_TO_2_0_EQ_imem_rg_cache_add_ETC___d1164 ||
	      imem_rg_cache_b16[1:0] == 2'b11) ;
  assign imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1211 =
	     imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1204 &&
	     imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1208 &&
	     (imem_rg_pc[1:0] != 2'b0 ||
	      !imem_rg_pc_BITS_31_TO_2_0_EQ_near_mem_imem_pc__ETC___d13 ||
	      near_mem$imem_instr[1:0] == 2'b11) ;
  assign imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d1347 =
	     imem_rg_pc[1:0] == 2'b0 || !near_mem$imem_valid ||
	     !imem_rg_pc_BITS_31_TO_2_0_EQ_near_mem_imem_pc__ETC___d13 ||
	     near_mem$imem_instr[17:16] != 2'b11 ;
  assign imem_rg_pc_BITS_31_TO_2_0_EQ_imem_rg_cache_add_ETC___d1164 =
	     imem_rg_pc[31:2] == imem_rg_cache_addr[31:2] ;
  assign imem_rg_pc_BITS_31_TO_2_0_EQ_near_mem_imem_pc__ETC___d13 =
	     imem_rg_pc[31:2] == near_mem$imem_pc[31:2] ;
  assign imm12__h10234 = { 4'd0, offset__h10106 } ;
  assign imm12__h10571 = { 5'd0, offset__h10513 } ;
  assign imm12__h12486 = { {6{imm6__h12484[5]}}, imm6__h12484 } ;
  assign imm12__h13110 = { {2{nzimm10__h13108[9]}}, nzimm10__h13108 } ;
  assign imm12__h13325 = { 2'd0, nzimm10__h13323 } ;
  assign imm12__h13521 = { 7'b0, stageD_rg_data[38:34] } ;
  assign imm12__h13866 = { 7'b0100000, stageD_rg_data[38:34] } ;
  assign imm20__h12614 = { {14{imm6__h12484[5]}}, imm6__h12484 } ;
  assign imm6__h12484 = { stageD_rg_data[44], stageD_rg_data[38:34] } ;
  assign instr___1__h10068 =
	     (csr_regfile$read_misa[2] && stageD_rg_data[33:32] == 2'b10 &&
	      stageD_rg_data[43:39] != 5'd0 &&
	      stageD_rg_data[47:45] == 3'b010) ?
	       instr__h10233 :
	       IF_csr_regfile_read_misa__9_BIT_2_28_AND_stage_ETC___d1064 ;
  assign instr__h10233 =
	     { imm12__h10234, 8'd18, stageD_rg_data[43:39], 7'b0000011 } ;
  assign instr__h10378 =
	     { 4'd0,
	       stageD_rg_data[40:39],
	       stageD_rg_data[44],
	       stageD_rg_data[38:34],
	       8'd18,
	       offset_BITS_4_TO_0___h10502,
	       7'b0100011 } ;
  assign instr__h10570 =
	     { imm12__h10571, rs1__h10572, 3'b010, rd__h10573, 7'b0000011 } ;
  assign instr__h10765 =
	     { 5'd0,
	       stageD_rg_data[37],
	       stageD_rg_data[44],
	       rd__h10573,
	       rs1__h10572,
	       3'b010,
	       offset_BITS_4_TO_0___h10933,
	       7'b0100011 } ;
  assign instr__h10994 =
	     { SEXT_stageD_rg_data_23_BIT_44_40_CONCAT_stageD_ETC___d892[20],
	       SEXT_stageD_rg_data_23_BIT_44_40_CONCAT_stageD_ETC___d892[10:1],
	       SEXT_stageD_rg_data_23_BIT_44_40_CONCAT_stageD_ETC___d892[11],
	       SEXT_stageD_rg_data_23_BIT_44_40_CONCAT_stageD_ETC___d892[19:12],
	       12'd111 } ;
  assign instr__h11336 =
	     { SEXT_stageD_rg_data_23_BIT_44_40_CONCAT_stageD_ETC___d892[20],
	       SEXT_stageD_rg_data_23_BIT_44_40_CONCAT_stageD_ETC___d892[10:1],
	       SEXT_stageD_rg_data_23_BIT_44_40_CONCAT_stageD_ETC___d892[11],
	       SEXT_stageD_rg_data_23_BIT_44_40_CONCAT_stageD_ETC___d892[19:12],
	       12'd239 } ;
  assign instr__h11726 = { 12'd0, stageD_rg_data[43:39], 15'd103 } ;
  assign instr__h11842 = { 12'd0, stageD_rg_data[43:39], 15'd231 } ;
  assign instr__h11907 =
	     { SEXT_stageD_rg_data_23_BIT_44_40_CONCAT_stageD_ETC___d921[12],
	       SEXT_stageD_rg_data_23_BIT_44_40_CONCAT_stageD_ETC___d921[10:5],
	       5'd0,
	       rs1__h10572,
	       3'b0,
	       SEXT_stageD_rg_data_23_BIT_44_40_CONCAT_stageD_ETC___d921[4:1],
	       SEXT_stageD_rg_data_23_BIT_44_40_CONCAT_stageD_ETC___d921[11],
	       7'b1100011 } ;
  assign instr__h12224 =
	     { SEXT_stageD_rg_data_23_BIT_44_40_CONCAT_stageD_ETC___d921[12],
	       SEXT_stageD_rg_data_23_BIT_44_40_CONCAT_stageD_ETC___d921[10:5],
	       5'd0,
	       rs1__h10572,
	       3'b001,
	       SEXT_stageD_rg_data_23_BIT_44_40_CONCAT_stageD_ETC___d921[4:1],
	       SEXT_stageD_rg_data_23_BIT_44_40_CONCAT_stageD_ETC___d921[11],
	       7'b1100011 } ;
  assign instr__h12562 =
	     { imm12__h12486, 8'd0, stageD_rg_data[43:39], 7'b0010011 } ;
  assign instr__h12746 =
	     { imm20__h12614, stageD_rg_data[43:39], 7'b0110111 } ;
  assign instr__h12875 =
	     { imm12__h12486,
	       stageD_rg_data[43:39],
	       3'b0,
	       stageD_rg_data[43:39],
	       7'b0010011 } ;
  assign instr__h13312 =
	     { imm12__h13110,
	       stageD_rg_data[43:39],
	       3'b0,
	       stageD_rg_data[43:39],
	       7'b0010011 } ;
  assign instr__h13484 = { imm12__h13325, 8'd16, rd__h10573, 7'b0010011 } ;
  assign instr__h13657 =
	     { imm12__h13521,
	       stageD_rg_data[43:39],
	       3'b001,
	       stageD_rg_data[43:39],
	       7'b0010011 } ;
  assign instr__h13850 =
	     { imm12__h13521, rs1__h10572, 3'b101, rs1__h10572, 7'b0010011 } ;
  assign instr__h14043 =
	     { imm12__h13866, rs1__h10572, 3'b101, rs1__h10572, 7'b0010011 } ;
  assign instr__h14160 =
	     { imm12__h12486, rs1__h10572, 3'b111, rs1__h10572, 7'b0010011 } ;
  assign instr__h14338 =
	     { 7'b0,
	       stageD_rg_data[38:34],
	       8'd0,
	       stageD_rg_data[43:39],
	       7'b0110011 } ;
  assign instr__h14457 =
	     { 7'b0,
	       stageD_rg_data[38:34],
	       stageD_rg_data[43:39],
	       3'b0,
	       stageD_rg_data[43:39],
	       7'b0110011 } ;
  assign instr__h14552 =
	     { 7'b0,
	       rd__h10573,
	       rs1__h10572,
	       3'b111,
	       rs1__h10572,
	       7'b0110011 } ;
  assign instr__h14688 =
	     { 7'b0,
	       rd__h10573,
	       rs1__h10572,
	       3'b110,
	       rs1__h10572,
	       7'b0110011 } ;
  assign instr__h14824 =
	     { 7'b0,
	       rd__h10573,
	       rs1__h10572,
	       3'b100,
	       rs1__h10572,
	       7'b0110011 } ;
  assign instr__h14960 =
	     { 7'b0100000,
	       rd__h10573,
	       rs1__h10572,
	       3'b0,
	       rs1__h10572,
	       7'b0110011 } ;
  assign instr__h15298 =
	     { 12'b000000000001,
	       stageD_rg_data[43:39],
	       3'b0,
	       stageD_rg_data[43:39],
	       7'b1110011 } ;
  assign instr_out___1__h15517 =
	     { near_mem$imem_instr[15:0], imem_rg_cache_b16 } ;
  assign instr_out___1__h15539 = { 16'b0, near_mem$imem_instr[15:0] } ;
  assign near_mem_imem_pc__1_EQ_imem_rg_pc_PLUS_2_166___d1167 =
	     near_mem$imem_pc == imem_rg_pc + 32'd2 ;
  assign near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d1313 =
	     near_mem$imem_valid &&
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1217 &&
	     near_mem$imem_exc &&
	     near_mem$imem_exc_code != 4'd0 &&
	     near_mem$imem_exc_code != 4'd1 &&
	     near_mem$imem_exc_code != 4'd2 &&
	     near_mem$imem_exc_code != 4'd3 &&
	     near_mem$imem_exc_code != 4'd4 &&
	     near_mem$imem_exc_code != 4'd5 &&
	     near_mem$imem_exc_code != 4'd6 &&
	     near_mem$imem_exc_code != 4'd7 &&
	     near_mem$imem_exc_code != 4'd8 &&
	     near_mem$imem_exc_code != 4'd9 &&
	     near_mem$imem_exc_code != 4'd11 &&
	     near_mem$imem_exc_code != 4'd12 &&
	     near_mem$imem_exc_code != 4'd13 &&
	     near_mem$imem_exc_code != 4'd15 ;
  assign new_epoch__h16878 = rg_epoch + 2'd1 ;
  assign next_pc___1__h9129 = stage1_rg_stage_input[305:274] + 32'd2 ;
  assign next_pc__h7661 = x_out_next_pc__h7677 ;
  assign next_pc__h7881 =
	     stage1_rg_stage_input[305:274] +
	     { {11{stage1_rg_stage_input_BITS_30_TO_10__q2[20]}},
	       stage1_rg_stage_input_BITS_30_TO_10__q2 } ;
  assign next_pc__h7908 = { eaddr__h8065[31:1], 1'd0 } ;
  assign next_pc__h9126 = stage1_rg_stage_input[305:274] + 32'd4 ;
  assign nzimm10__h13108 =
	     { stageD_rg_data[44],
	       stageD_rg_data[36:35],
	       stageD_rg_data[37],
	       stageD_rg_data[34],
	       stageD_rg_data[38],
	       4'b0 } ;
  assign nzimm10__h13323 =
	     { stageD_rg_data[42:39],
	       stageD_rg_data[44:43],
	       stageD_rg_data[37],
	       stageD_rg_data[38],
	       2'b0 } ;
  assign offset_BITS_4_TO_0___h10502 = { stageD_rg_data[43:41], 2'b0 } ;
  assign offset_BITS_4_TO_0___h10933 =
	     { stageD_rg_data[43:42], stageD_rg_data[38], 2'b0 } ;
  assign offset__h10106 =
	     { stageD_rg_data[35:34],
	       stageD_rg_data[44],
	       stageD_rg_data[38:36],
	       2'b0 } ;
  assign offset__h10513 =
	     { stageD_rg_data[37],
	       stageD_rg_data[44:42],
	       stageD_rg_data[38],
	       2'b0 } ;
  assign offset__h10941 =
	     { stageD_rg_data[44],
	       stageD_rg_data[40],
	       stageD_rg_data[42:41],
	       stageD_rg_data[38],
	       stageD_rg_data[39],
	       stageD_rg_data[34],
	       stageD_rg_data[43],
	       stageD_rg_data[37:35],
	       1'b0 } ;
  assign offset__h11851 =
	     { stageD_rg_data[44],
	       stageD_rg_data[38:37],
	       stageD_rg_data[34],
	       stageD_rg_data[43:42],
	       stageD_rg_data[36:35],
	       1'b0 } ;
  assign rd__h10573 = { 2'b01, stageD_rg_data[36:34] } ;
  assign rd_val___1__h8726 =
	     rs1_val_bypassed__h4853 + _theResult___snd__h9832 ;
  assign rd_val___1__h8734 =
	     rs1_val_bypassed__h4853 - _theResult___snd__h9832 ;
  assign rd_val___1__h8741 =
	     ((rs1_val_bypassed__h4853 ^ 32'h80000000) <
	      (_theResult___snd__h9832 ^ 32'h80000000)) ?
	       32'd1 :
	       32'd0 ;
  assign rd_val___1__h8748 =
	     (rs1_val_bypassed__h4853 < _theResult___snd__h9832) ?
	       32'd1 :
	       32'd0 ;
  assign rd_val___1__h8755 =
	     rs1_val_bypassed__h4853 ^ _theResult___snd__h9832 ;
  assign rd_val___1__h8762 =
	     rs1_val_bypassed__h4853 | _theResult___snd__h9832 ;
  assign rd_val__h7562 =
	     (stage3_rg_full && stage3_rg_stage3[37] &&
	      stage3_rg_stage3[36:32] == stage1_rg_stage_input[139:135]) ?
	       stage3_rg_stage3[31:0] :
	       gpr_regfile$read_rs1 ;
  assign rd_val__h7636 =
	     (stage3_rg_full && stage3_rg_stage3[37] &&
	      stage3_rg_stage3[36:32] == stage1_rg_stage_input[134:130]) ?
	       stage3_rg_stage3[31:0] :
	       gpr_regfile$read_rs2 ;
  assign rd_val__h8035 = { stage1_rg_stage_input[50:31], 12'h0 } ;
  assign rd_val__h8049 = stage1_rg_stage_input[305:274] + rd_val__h8035 ;
  assign rd_val__h9729 = rs1_val_bypassed__h4853 << shamt__h7979 ;
  assign rd_val__h9780 = rs1_val_bypassed__h4853 >> shamt__h7979 ;
  assign rd_val__h9802 =
	     rs1_val_bypassed__h4853 >> shamt__h7979 |
	     ~(32'hFFFFFFFF >> shamt__h7979) &
	     {32{rs1_val_bypassed__h4853[31]}} ;
  assign rg_cur_priv_1_EQ_0b11_52_OR_rg_cur_priv_1_EQ_0_ETC___d464 =
	     (rg_cur_priv == 2'b11 ||
	      rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[21] ||
	      rg_cur_priv == 2'b0 && csr_regfile$read_misa[13]) &&
	     stage1_rg_stage_input[87:76] == 12'b000100000101 ;
  assign rg_state_0_EQ_12_7_AND_csr_regfile_wfi_resume__ETC___d1752 =
	     rg_state == 4'd12 && csr_regfile$wfi_resume &&
	     (!stageF_rg_full ||
	      near_mem$imem_valid &&
	      NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1217) ;
  assign rg_state_0_EQ_3_415_AND_NOT_csr_regfile_interr_ETC___d1623 =
	     rg_state == 4'd3 &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1619 &&
	     !stage3_rg_full &&
	     IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 ==
	     2'd0 &&
	     stage1_rg_full &&
	     stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 &&
	     NOT_IF_stage2_rg_full_6_THEN_IF_stage2_rg_stag_ETC___d378 ;
  assign rg_state_0_EQ_3_415_AND_NOT_csr_regfile_interr_ETC___d1732 =
	     rg_state_0_EQ_3_415_AND_NOT_csr_regfile_interr_ETC___d1623 &&
	     IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 ==
	     4'd6 &&
	     (!stageF_rg_full ||
	      near_mem$imem_valid &&
	      NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1217) ;
  assign rg_state_0_EQ_3_415_AND_NOT_csr_regfile_interr_ETC___d1741 =
	     rg_state_0_EQ_3_415_AND_NOT_csr_regfile_interr_ETC___d1623 &&
	     IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 ==
	     4'd5 &&
	     (!stageF_rg_full ||
	      near_mem$imem_valid &&
	      NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1217) ;
  assign rg_state_0_EQ_3_415_AND_stage3_rg_full_7_OR_NO_ETC___d1425 =
	     rg_state == 4'd3 &&
	     (stage3_rg_full ||
	      IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 !=
	      2'd0 ||
	      stage1_rg_full ||
	      stageD_rg_full ||
	      stageF_rg_full) &&
	     (stage3_rg_full ||
	      IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 !=
	      2'd3) &&
	     stage3_rg_full_7_OR_NOT_IF_stage2_rg_full_6_TH_ETC___d1423 ;
  assign rg_state_0_EQ_5_756_AND_NOT_stageF_rg_full_194_ETC___d1757 =
	     rg_state == 4'd5 &&
	     (!stageF_rg_full ||
	      near_mem$imem_valid &&
	      NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1217) ;
  assign rg_state_0_EQ_8_705_AND_NOT_stageF_rg_full_194_ETC___d1706 =
	     rg_state == 4'd8 &&
	     (!stageF_rg_full ||
	      near_mem$imem_valid &&
	      NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1217) ;
  assign rg_trap_info_633_BITS_67_TO_36_634_EQ_csr_regf_ETC___d1643 =
	     rg_trap_info[67:36] == csr_regfile$csr_trap_actions[97:66] ;
  assign rs1__h10572 = { 2'b01, stageD_rg_data[41:39] } ;
  assign rs1_val__h22063 =
	     (rg_trap_instr[14:12] == 3'b001) ?
	       rg_csr_val1 :
	       { 27'd0, rg_trap_instr[19:15] } ;
  assign rs1_val_bypassed__h4853 =
	     (stage1_rg_stage_input[139:135] == 5'd0) ? 32'd0 : val__h7564 ;
  assign rs2_val_bypassed__h4859 =
	     (stage1_rg_stage_input[134:130] == 5'd0) ? 32'd0 : val__h7638 ;
  assign shamt__h7979 =
	     (stage1_rg_stage_input[151:145] == 7'b0010011) ?
	       stage1_rg_stage_input[80:76] :
	       rs2_val_bypassed__h4859[4:0] ;
  assign stage1_rg_full_00_AND_NOT_stage1_rg_stage_inpu_ETC___d433 =
	     stage1_rg_full &&
	     NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d382 &&
	     (!stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 ||
	      IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d430) ;
  assign stage1_rg_stage_input_01_BITS_112_TO_110_30_EQ_ETC___d398 =
	     stage1_rg_stage_input[112:110] == 3'b0 &&
	     (stage1_rg_stage_input[151:145] != 7'b0110011 ||
	      !stage1_rg_stage_input[230]) ||
	     stage1_rg_stage_input[112:110] == 3'b0 &&
	     stage1_rg_stage_input[151:145] == 7'b0110011 &&
	     stage1_rg_stage_input[230] ||
	     stage1_rg_stage_input[112:110] == 3'b010 ||
	     stage1_rg_stage_input[112:110] == 3'b011 ||
	     stage1_rg_stage_input[112:110] == 3'b100 ||
	     stage1_rg_stage_input[112:110] == 3'b110 ||
	     stage1_rg_stage_input[112:110] == 3'b111 ;
  assign stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d1388 =
	     (stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 &&
	      IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d1385 ||
	      IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 ==
	      4'd0) &&
	     (!stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 ||
	      IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d430) ;
  assign stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 =
	     stage1_rg_stage_input[271:270] == rg_epoch ;
  assign stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d221 =
	     stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 &&
	     IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d188 ==
	     2'd1 &&
	     (IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d205 ||
	      IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d207) ;
  assign stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d766 =
	     stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 &&
	     NOT_IF_stage2_rg_full_6_THEN_IF_stage2_rg_stag_ETC___d378 &&
	     IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 !=
	     4'd0 &&
	     IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 !=
	     4'd1 &&
	     IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 !=
	     4'd2 &&
	     IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 !=
	     4'd3 &&
	     IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 !=
	     4'd4 &&
	     IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 !=
	     4'd5 &&
	     IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 !=
	     4'd6 &&
	     IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 !=
	     4'd7 &&
	     IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 !=
	     4'd8 &&
	     IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 !=
	     4'd9 &&
	     IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 !=
	     4'd10 &&
	     IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 !=
	     4'd11 ;
  assign stage1_rg_stage_input_BITS_30_TO_10__q2 =
	     stage1_rg_stage_input[30:10] ;
  assign stage1_rg_stage_input_BITS_63_TO_51__q1 =
	     stage1_rg_stage_input[63:51] ;
  assign stage1_rg_stage_input_BITS_75_TO_64__q7 =
	     stage1_rg_stage_input[75:64] ;
  assign stage1_rg_stage_input_BITS_87_TO_76__q17 =
	     stage1_rg_stage_input[87:76] ;
  assign stage3_rg_full_7_OR_NOT_IF_stage2_rg_full_6_TH_ETC___d1423 =
	     stage3_rg_full ||
	     IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 !=
	     2'd0 ||
	     !stage1_rg_full ||
	     !stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 ||
	     IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d430 ;
  assign stageF_rg_full_194_AND_near_mem_imem_valid_AND_ETC___d1226 =
	     stageF_rg_full && near_mem$imem_valid &&
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1217 &&
	     !near_mem$imem_exc ;
  assign stageF_rg_full_194_AND_near_mem_imem_valid_AND_ETC___d1232 =
	     stageF_rg_full && near_mem$imem_valid &&
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1217 &&
	     near_mem$imem_exc &&
	     near_mem$imem_exc_code == 4'd0 ;
  assign stageF_rg_full_194_AND_near_mem_imem_valid_AND_ETC___d1236 =
	     stageF_rg_full && near_mem$imem_valid &&
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1217 &&
	     near_mem$imem_exc &&
	     near_mem$imem_exc_code == 4'd1 ;
  assign stageF_rg_full_194_AND_near_mem_imem_valid_AND_ETC___d1240 =
	     stageF_rg_full && near_mem$imem_valid &&
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1217 &&
	     near_mem$imem_exc &&
	     near_mem$imem_exc_code == 4'd2 ;
  assign stageF_rg_full_194_AND_near_mem_imem_valid_AND_ETC___d1244 =
	     stageF_rg_full && near_mem$imem_valid &&
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1217 &&
	     near_mem$imem_exc &&
	     near_mem$imem_exc_code == 4'd3 ;
  assign stageF_rg_full_194_AND_near_mem_imem_valid_AND_ETC___d1248 =
	     stageF_rg_full && near_mem$imem_valid &&
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1217 &&
	     near_mem$imem_exc &&
	     near_mem$imem_exc_code == 4'd4 ;
  assign stageF_rg_full_194_AND_near_mem_imem_valid_AND_ETC___d1252 =
	     stageF_rg_full && near_mem$imem_valid &&
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1217 &&
	     near_mem$imem_exc &&
	     near_mem$imem_exc_code == 4'd5 ;
  assign stageF_rg_full_194_AND_near_mem_imem_valid_AND_ETC___d1256 =
	     stageF_rg_full && near_mem$imem_valid &&
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1217 &&
	     near_mem$imem_exc &&
	     near_mem$imem_exc_code == 4'd6 ;
  assign stageF_rg_full_194_AND_near_mem_imem_valid_AND_ETC___d1260 =
	     stageF_rg_full && near_mem$imem_valid &&
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1217 &&
	     near_mem$imem_exc &&
	     near_mem$imem_exc_code == 4'd7 ;
  assign stageF_rg_full_194_AND_near_mem_imem_valid_AND_ETC___d1264 =
	     stageF_rg_full && near_mem$imem_valid &&
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1217 &&
	     near_mem$imem_exc &&
	     near_mem$imem_exc_code == 4'd8 ;
  assign stageF_rg_full_194_AND_near_mem_imem_valid_AND_ETC___d1268 =
	     stageF_rg_full && near_mem$imem_valid &&
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1217 &&
	     near_mem$imem_exc &&
	     near_mem$imem_exc_code == 4'd9 ;
  assign stageF_rg_full_194_AND_near_mem_imem_valid_AND_ETC___d1272 =
	     stageF_rg_full && near_mem$imem_valid &&
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1217 &&
	     near_mem$imem_exc &&
	     near_mem$imem_exc_code == 4'd11 ;
  assign stageF_rg_full_194_AND_near_mem_imem_valid_AND_ETC___d1276 =
	     stageF_rg_full && near_mem$imem_valid &&
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1217 &&
	     near_mem$imem_exc &&
	     near_mem$imem_exc_code == 4'd12 ;
  assign stageF_rg_full_194_AND_near_mem_imem_valid_AND_ETC___d1280 =
	     stageF_rg_full && near_mem$imem_valid &&
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1217 &&
	     near_mem$imem_exc &&
	     near_mem$imem_exc_code == 4'd13 ;
  assign stageF_rg_full_194_AND_near_mem_imem_valid_AND_ETC___d1284 =
	     stageF_rg_full && near_mem$imem_valid &&
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1217 &&
	     near_mem$imem_exc &&
	     near_mem$imem_exc_code == 4'd15 ;
  assign trap_info_tval__h9330 =
	     (stage1_rg_stage_input[151:145] != 7'b1101111 &&
	      stage1_rg_stage_input[151:145] != 7'b1100111 &&
	      (stage1_rg_stage_input[151:145] != 7'b1110011 ||
	       stage1_rg_stage_input[112:110] != 3'b0 ||
	       stage1_rg_stage_input[144:140] != 5'd0 ||
	       stage1_rg_stage_input[139:135] != 5'd0 ||
	       stage1_rg_stage_input[87:76] != 12'b0 &&
	       stage1_rg_stage_input[87:76] != 12'b000000000001)) ?
	       (stage1_rg_stage_input[269] ?
		  stage1_rg_stage_input[231:200] :
		  { 16'd0, stage1_rg_stage_input[199:184] }) :
	       CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q18 ;
  assign val__h7564 =
	     (IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d188 ==
	      2'd2 &&
	      IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d205) ?
	       x_out_bypass_rd_val__h7432 :
	       rd_val__h7562 ;
  assign val__h7638 =
	     (IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d188 ==
	      2'd2 &&
	      IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d207) ?
	       x_out_bypass_rd_val__h7432 :
	       rd_val__h7636 ;
  assign value__h9376 =
	     stage1_rg_stage_input[268] ?
	       stage1_rg_stage_input[263:232] :
	       trap_info_tval__h9330 ;
  assign x__h21591 =
	     csr_regfile_read_csr_mcycle__0_MINUS_rg_start__ETC___d1647[63:0] /
	     _theResult____h21590 ;
  assign x_exc_code__h28843 =
	     (csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending) ?
	       csr_regfile$interrupt_pending[3:0] :
	       4'd0 ;
  assign x_out_cf_info_fallthru_PC__h9504 =
	     stage1_rg_stage_input[269] ?
	       next_pc__h9126 :
	       next_pc___1__h9129 ;
  assign x_out_data_to_stage1_instr__h10032 =
	     stageD_rg_data[101] ? stageD_rg_data[63:32] : instr___1__h10068 ;
  assign x_out_data_to_stage2_rd__h7719 =
	     stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 ?
	       data_to_stage2_rd__h7709 :
	       5'd0 ;
  assign x_out_data_to_stage2_val2__h7722 =
	     (stage1_rg_stage_input[151:145] == 7'b1100011) ?
	       branch_target__h7852 :
	       rs2_val_bypassed__h4859 ;
  assign x_out_next_pc__h7677 =
	     IF_stage1_rg_stage_input_01_BITS_151_TO_145_28_ETC___d427 ?
	       data_to_stage2_addr__h7710 :
	       fall_through_pc__h7660 ;
  assign x_out_trap_info_exc_code__h9335 =
	     stage1_rg_stage_input[268] ?
	       stage1_rg_stage_input[267:264] :
	       alu_outputs_exc_code__h8321 ;
  assign y__h23012 = ~rs1_val__h22743 ;
  always@(stage2_rg_stage2)
  begin
    case (stage2_rg_stage2[103:101])
      3'd0, 3'd1, 3'd4:
	  x_out_data_to_stage3_rd__h7092 = stage2_rg_stage2[100:96];
      3'd2: x_out_data_to_stage3_rd__h7092 = 5'd0;
      default: x_out_data_to_stage3_rd__h7092 = stage2_rg_stage2[100:96];
    endcase
  end
  always@(stage2_rg_stage2 or stage2_mbox$word or near_mem$dmem_word64)
  begin
    case (stage2_rg_stage2[103:101])
      3'd0, 3'd2:
	  x_out_data_to_stage3_rd_val__h7093 = stage2_rg_stage2[63:32];
      3'd1, 3'd4:
	  x_out_data_to_stage3_rd_val__h7093 = near_mem$dmem_word64[31:0];
      default: x_out_data_to_stage3_rd_val__h7093 = stage2_mbox$word;
    endcase
  end
  always@(stage2_rg_stage2)
  begin
    case (stage2_rg_stage2[103:101])
      3'd0, 3'd1, 3'd4: x_out_bypass_rd__h7431 = stage2_rg_stage2[100:96];
      default: x_out_bypass_rd__h7431 = stage2_rg_stage2[100:96];
    endcase
  end
  always@(stage2_rg_stage2 or stage2_mbox$word)
  begin
    case (stage2_rg_stage2[103:101])
      3'd0, 3'd1, 3'd4: x_out_bypass_rd_val__h7432 = stage2_rg_stage2[63:32];
      default: x_out_bypass_rd_val__h7432 = stage2_mbox$word;
    endcase
  end
  always@(rg_trap_instr or rg_csr_val1)
  begin
    case (rg_trap_instr[14:12])
      3'b010, 3'b011: rs1_val__h22743 = rg_csr_val1;
      default: rs1_val__h22743 = { 27'd0, rg_trap_instr[19:15] };
    endcase
  end
  always@(rg_cur_priv)
  begin
    case (rg_cur_priv)
      2'b0: CASE_rg_cur_priv_0b0_8_0b1_9_11__q3 = 4'd8;
      2'b01: CASE_rg_cur_priv_0b0_8_0b1_9_11__q3 = 4'd9;
      default: CASE_rg_cur_priv_0b0_8_0b1_9_11__q3 = 4'd11;
    endcase
  end
  always@(stage1_rg_stage_input or CASE_rg_cur_priv_0b0_8_0b1_9_11__q3)
  begin
    case (stage1_rg_stage_input[87:76])
      12'b0:
	  CASE_stage1_rg_stage_input_BITS_87_TO_76_0b0_C_ETC__q4 =
	      CASE_rg_cur_priv_0b0_8_0b1_9_11__q3;
      12'b000000000001:
	  CASE_stage1_rg_stage_input_BITS_87_TO_76_0b0_C_ETC__q4 = 4'd3;
      default: CASE_stage1_rg_stage_input_BITS_87_TO_76_0b0_C_ETC__q4 = 4'd2;
    endcase
  end
  always@(stage1_rg_stage_input or alu_outputs___1_exc_code__h8280)
  begin
    case (stage1_rg_stage_input[151:145])
      7'b0000011,
      7'b0001111,
      7'b0010011,
      7'b0010111,
      7'b0100011,
      7'b0110011,
      7'b0110111,
      7'b1100011:
	  alu_outputs_exc_code__h8321 = 4'd2;
      7'b1100111, 7'b1101111: alu_outputs_exc_code__h8321 = 4'd0;
      7'b1110011:
	  alu_outputs_exc_code__h8321 = alu_outputs___1_exc_code__h8280;
      default: alu_outputs_exc_code__h8321 = 4'd2;
    endcase
  end
  always@(stage2_rg_stage2 or
	  IF_stage2_rg_stage2_7_BITS_103_TO_101_8_EQ_3_0_ETC___d124 or
	  IF_near_mem_dmem_valid__18_THEN_IF_near_mem_dm_ETC___d121)
  begin
    case (stage2_rg_stage2[103:101])
      3'd0: CASE_stage2_rg_stage2_BITS_103_TO_101_0_2_1_IF_ETC__q5 = 2'd2;
      3'd1, 3'd2, 3'd4:
	  CASE_stage2_rg_stage2_BITS_103_TO_101_0_2_1_IF_ETC__q5 =
	      IF_near_mem_dmem_valid__18_THEN_IF_near_mem_dm_ETC___d121;
      default: CASE_stage2_rg_stage2_BITS_103_TO_101_0_2_1_IF_ETC__q5 =
		   IF_stage2_rg_stage2_7_BITS_103_TO_101_8_EQ_3_0_ETC___d124;
    endcase
  end
  always@(stage2_rg_stage2 or
	  stage2_mbox$valid or near_mem$dmem_valid or near_mem$dmem_exc)
  begin
    case (stage2_rg_stage2[103:101])
      3'd1, 3'd2, 3'd4:
	  IF_stage2_rg_stage2_7_BITS_103_TO_101_8_EQ_1_0_ETC___d141 =
	      !near_mem$dmem_valid || near_mem$dmem_exc;
      default: IF_stage2_rg_stage2_7_BITS_103_TO_101_8_EQ_1_0_ETC___d141 =
		   !stage2_mbox$valid;
    endcase
  end
  always@(stage2_rg_stage2 or
	  stage2_mbox$valid or near_mem$dmem_valid or near_mem$dmem_exc)
  begin
    case (stage2_rg_stage2[103:101])
      3'd1, 3'd2, 3'd4:
	  IF_stage2_rg_stage2_7_BITS_103_TO_101_8_EQ_1_0_ETC___d150 =
	      near_mem$dmem_valid && !near_mem$dmem_exc;
      default: IF_stage2_rg_stage2_7_BITS_103_TO_101_8_EQ_1_0_ETC___d150 =
		   stage2_mbox$valid;
    endcase
  end
  always@(stage2_rg_stage2 or
	  IF_stage2_rg_stage2_7_BITS_103_TO_101_8_EQ_3_0_ETC___d124 or
	  IF_NOT_near_mem_dmem_valid__18_37_OR_NOT_near__ETC___d184)
  begin
    case (stage2_rg_stage2[103:101])
      3'd0: CASE_stage2_rg_stage2_BITS_103_TO_101_0_2_1_IF_ETC__q6 = 2'd2;
      3'd1, 3'd4:
	  CASE_stage2_rg_stage2_BITS_103_TO_101_0_2_1_IF_ETC__q6 =
	      IF_NOT_near_mem_dmem_valid__18_37_OR_NOT_near__ETC___d184;
      3'd2: CASE_stage2_rg_stage2_BITS_103_TO_101_0_2_1_IF_ETC__q6 = 2'd0;
      default: CASE_stage2_rg_stage2_BITS_103_TO_101_0_2_1_IF_ETC__q6 =
		   IF_stage2_rg_stage2_7_BITS_103_TO_101_8_EQ_3_0_ETC___d124;
    endcase
  end
  always@(stage1_rg_stage_input or
	  IF_stage1_rg_stage_input_01_BITS_139_TO_135_04_ETC___d269 or
	  IF_stage1_rg_stage_input_01_BITS_139_TO_135_04_ETC___d265 or
	  IF_stage1_rg_stage_input_01_BITS_139_TO_135_04_ETC___d267)
  begin
    case (stage1_rg_stage_input[112:110])
      3'b0:
	  IF_stage1_rg_stage_input_01_BITS_112_TO_110_30_ETC___d370 =
	      !IF_stage1_rg_stage_input_01_BITS_139_TO_135_04_ETC___d265;
      3'b001:
	  IF_stage1_rg_stage_input_01_BITS_112_TO_110_30_ETC___d370 =
	      IF_stage1_rg_stage_input_01_BITS_139_TO_135_04_ETC___d265;
      3'b100:
	  IF_stage1_rg_stage_input_01_BITS_112_TO_110_30_ETC___d370 =
	      !IF_stage1_rg_stage_input_01_BITS_139_TO_135_04_ETC___d267;
      3'b101:
	  IF_stage1_rg_stage_input_01_BITS_112_TO_110_30_ETC___d370 =
	      IF_stage1_rg_stage_input_01_BITS_139_TO_135_04_ETC___d267;
      3'b110:
	  IF_stage1_rg_stage_input_01_BITS_112_TO_110_30_ETC___d370 =
	      !IF_stage1_rg_stage_input_01_BITS_139_TO_135_04_ETC___d269;
      default: IF_stage1_rg_stage_input_01_BITS_112_TO_110_30_ETC___d370 =
		   stage1_rg_stage_input[112:110] != 3'b111 ||
		   IF_stage1_rg_stage_input_01_BITS_139_TO_135_04_ETC___d269;
    endcase
  end
  always@(stage1_rg_stage_input or
	  IF_stage1_rg_stage_input_01_BITS_139_TO_135_04_ETC___d269 or
	  IF_stage1_rg_stage_input_01_BITS_139_TO_135_04_ETC___d265 or
	  IF_stage1_rg_stage_input_01_BITS_139_TO_135_04_ETC___d267)
  begin
    case (stage1_rg_stage_input[112:110])
      3'b0:
	  IF_stage1_rg_stage_input_01_BITS_112_TO_110_30_ETC___d276 =
	      IF_stage1_rg_stage_input_01_BITS_139_TO_135_04_ETC___d265;
      3'b001:
	  IF_stage1_rg_stage_input_01_BITS_112_TO_110_30_ETC___d276 =
	      !IF_stage1_rg_stage_input_01_BITS_139_TO_135_04_ETC___d265;
      3'b100:
	  IF_stage1_rg_stage_input_01_BITS_112_TO_110_30_ETC___d276 =
	      IF_stage1_rg_stage_input_01_BITS_139_TO_135_04_ETC___d267;
      3'b101:
	  IF_stage1_rg_stage_input_01_BITS_112_TO_110_30_ETC___d276 =
	      !IF_stage1_rg_stage_input_01_BITS_139_TO_135_04_ETC___d267;
      3'b110:
	  IF_stage1_rg_stage_input_01_BITS_112_TO_110_30_ETC___d276 =
	      IF_stage1_rg_stage_input_01_BITS_139_TO_135_04_ETC___d269;
      default: IF_stage1_rg_stage_input_01_BITS_112_TO_110_30_ETC___d276 =
		   stage1_rg_stage_input[112:110] == 3'b111 &&
		   !IF_stage1_rg_stage_input_01_BITS_139_TO_135_04_ETC___d269;
    endcase
  end
  always@(stage1_rg_stage_input)
  begin
    case (stage1_rg_stage_input[151:145])
      7'b0000011:
	  CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q8 =
	      stage1_rg_stage_input[112:110] != 3'b0 &&
	      stage1_rg_stage_input[112:110] != 3'b100 &&
	      stage1_rg_stage_input[112:110] != 3'b001 &&
	      stage1_rg_stage_input[112:110] != 3'b101 &&
	      stage1_rg_stage_input[112:110] != 3'b010;
      7'b0100011:
	  CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q8 =
	      stage1_rg_stage_input[112:110] != 3'b0 &&
	      stage1_rg_stage_input[112:110] != 3'b001 &&
	      stage1_rg_stage_input[112:110] != 3'b010;
      default: CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q8 =
		   stage1_rg_stage_input[151:145] != 7'b0101111 ||
		   stage1_rg_stage_input[109:105] != 5'b00010 &&
		   stage1_rg_stage_input[109:105] != 5'b00011 &&
		   stage1_rg_stage_input[109:105] != 5'b0 &&
		   stage1_rg_stage_input[109:105] != 5'b00001 &&
		   stage1_rg_stage_input[109:105] != 5'b01100 &&
		   stage1_rg_stage_input[109:105] != 5'b01000 &&
		   stage1_rg_stage_input[109:105] != 5'b00100 &&
		   stage1_rg_stage_input[109:105] != 5'b10000 &&
		   stage1_rg_stage_input[109:105] != 5'b11000 &&
		   stage1_rg_stage_input[109:105] != 5'b10100 &&
		   stage1_rg_stage_input[109:105] != 5'b11100 ||
		   stage1_rg_stage_input[112:110] != 3'b010;
    endcase
  end
  always@(stage1_rg_stage_input or
	  CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q8 or
	  NOT_stage1_rg_stage_input_01_BITS_112_TO_110_3_ETC___d306)
  begin
    case (stage1_rg_stage_input[151:145])
      7'b0010011, 7'b0110011:
	  CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q9 =
	      NOT_stage1_rg_stage_input_01_BITS_112_TO_110_3_ETC___d306;
      default: CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q9 =
		   stage1_rg_stage_input[151:145] != 7'b0110111 &&
		   stage1_rg_stage_input[151:145] != 7'b0010111 &&
		   CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q8;
    endcase
  end
  always@(stage1_rg_stage_input)
  begin
    case (stage1_rg_stage_input[151:145])
      7'b0000011:
	  CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q10 =
	      stage1_rg_stage_input[112:110] == 3'b0 ||
	      stage1_rg_stage_input[112:110] == 3'b100 ||
	      stage1_rg_stage_input[112:110] == 3'b001 ||
	      stage1_rg_stage_input[112:110] == 3'b101 ||
	      stage1_rg_stage_input[112:110] == 3'b010;
      7'b0100011:
	  CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q10 =
	      stage1_rg_stage_input[112:110] == 3'b0 ||
	      stage1_rg_stage_input[112:110] == 3'b001 ||
	      stage1_rg_stage_input[112:110] == 3'b010;
      default: CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q10 =
		   stage1_rg_stage_input[151:145] == 7'b0101111 &&
		   (stage1_rg_stage_input[109:105] == 5'b00010 ||
		    stage1_rg_stage_input[109:105] == 5'b00011 ||
		    stage1_rg_stage_input[109:105] == 5'b0 ||
		    stage1_rg_stage_input[109:105] == 5'b00001 ||
		    stage1_rg_stage_input[109:105] == 5'b01100 ||
		    stage1_rg_stage_input[109:105] == 5'b01000 ||
		    stage1_rg_stage_input[109:105] == 5'b00100 ||
		    stage1_rg_stage_input[109:105] == 5'b10000 ||
		    stage1_rg_stage_input[109:105] == 5'b11000 ||
		    stage1_rg_stage_input[109:105] == 5'b10100 ||
		    stage1_rg_stage_input[109:105] == 5'b11100) &&
		   stage1_rg_stage_input[112:110] == 3'b010;
    endcase
  end
  always@(stage1_rg_stage_input or
	  CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q10 or
	  stage1_rg_stage_input_01_BITS_112_TO_110_30_EQ_ETC___d398)
  begin
    case (stage1_rg_stage_input[151:145])
      7'b0010011, 7'b0110011:
	  CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q11 =
	      stage1_rg_stage_input_01_BITS_112_TO_110_30_EQ_ETC___d398;
      default: CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q11 =
		   stage1_rg_stage_input[151:145] == 7'b0110111 ||
		   stage1_rg_stage_input[151:145] == 7'b0010111 ||
		   CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q10;
    endcase
  end
  always@(stage1_rg_stage_input)
  begin
    case (stage1_rg_stage_input[112:110])
      3'b0, 3'b001, 3'b010, 3'b100, 3'b101:
	  CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q12 = 4'd1;
      default: CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q12 =
		   4'd12;
    endcase
  end
  always@(stage1_rg_stage_input)
  begin
    case (stage1_rg_stage_input[112:110])
      3'b0: CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q13 = 4'd5;
      3'b001: CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q13 = 4'd6;
      default: CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q13 =
		   4'd12;
    endcase
  end
  always@(stage1_rg_stage_input)
  begin
    case (stage1_rg_stage_input[112:110])
      3'b0, 3'b001, 3'b010:
	  CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q14 = 4'd1;
      default: CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q14 =
		   4'd12;
    endcase
  end
  always@(stage1_rg_stage_input or
	  IF_rg_cur_priv_1_EQ_0b11_52_AND_stage1_rg_stag_ETC___d466)
  begin
    case (stage1_rg_stage_input[87:76])
      12'b0, 12'b000000000001:
	  CASE_stage1_rg_stage_input_BITS_87_TO_76_0b0_1_ETC__q15 = 4'd12;
      default: CASE_stage1_rg_stage_input_BITS_87_TO_76_0b0_1_ETC__q15 =
		   IF_rg_cur_priv_1_EQ_0b11_52_AND_stage1_rg_stag_ETC___d466;
    endcase
  end
  always@(stage1_rg_stage_input or
	  CASE_stage1_rg_stage_input_BITS_87_TO_76_0b0_1_ETC__q15)
  begin
    case (stage1_rg_stage_input[112:110])
      3'b0:
	  CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q16 =
	      (stage1_rg_stage_input[144:140] == 5'd0 &&
	       stage1_rg_stage_input[139:135] == 5'd0) ?
		CASE_stage1_rg_stage_input_BITS_87_TO_76_0b0_1_ETC__q15 :
		4'd12;
      3'b001, 3'b101:
	  CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q16 = 4'd3;
      3'b010, 3'b011, 3'b110, 3'b111:
	  CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q16 = 4'd4;
      3'd4: CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q16 = 4'd12;
    endcase
  end
  always@(stage1_rg_stage_input or
	  CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q12 or
	  CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q13 or
	  IF_NOT_stage1_rg_stage_input_01_BITS_112_TO_11_ETC___d438 or
	  CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q14 or
	  CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q16)
  begin
    case (stage1_rg_stage_input[151:145])
      7'b0000011:
	  IF_stage1_rg_stage_input_01_BITS_151_TO_145_28_ETC___d482 =
	      CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q12;
      7'b0001111:
	  IF_stage1_rg_stage_input_01_BITS_151_TO_145_28_ETC___d482 =
	      CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q13;
      7'b0010011, 7'b0110011:
	  IF_stage1_rg_stage_input_01_BITS_151_TO_145_28_ETC___d482 =
	      IF_NOT_stage1_rg_stage_input_01_BITS_112_TO_11_ETC___d438;
      7'b0010111, 7'b0110111:
	  IF_stage1_rg_stage_input_01_BITS_151_TO_145_28_ETC___d482 = 4'd1;
      7'b0100011:
	  IF_stage1_rg_stage_input_01_BITS_151_TO_145_28_ETC___d482 =
	      CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q14;
      7'b0101111:
	  IF_stage1_rg_stage_input_01_BITS_151_TO_145_28_ETC___d482 =
	      ((stage1_rg_stage_input[109:105] == 5'b00010 ||
		stage1_rg_stage_input[109:105] == 5'b00011 ||
		stage1_rg_stage_input[109:105] == 5'b0 ||
		stage1_rg_stage_input[109:105] == 5'b00001 ||
		stage1_rg_stage_input[109:105] == 5'b01100 ||
		stage1_rg_stage_input[109:105] == 5'b01000 ||
		stage1_rg_stage_input[109:105] == 5'b00100 ||
		stage1_rg_stage_input[109:105] == 5'b10000 ||
		stage1_rg_stage_input[109:105] == 5'b11000 ||
		stage1_rg_stage_input[109:105] == 5'b10100 ||
		stage1_rg_stage_input[109:105] == 5'b11100) &&
	       stage1_rg_stage_input[112:110] == 3'b010) ?
		4'd1 :
		4'd12;
      7'b1110011:
	  IF_stage1_rg_stage_input_01_BITS_151_TO_145_28_ETC___d482 =
	      CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q16;
      default: IF_stage1_rg_stage_input_01_BITS_151_TO_145_28_ETC___d482 =
		   4'd12;
    endcase
  end
  always@(stage1_rg_stage_input or
	  IF_stage1_rg_stage_input_01_BITS_151_TO_145_28_ETC___d482 or
	  IF_stage1_rg_stage_input_01_BITS_112_TO_110_30_ETC___d276)
  begin
    case (stage1_rg_stage_input[151:145])
      7'b1100011:
	  IF_stage1_rg_stage_input_01_BITS_151_TO_145_28_ETC___d486 =
	      (stage1_rg_stage_input[112:110] != 3'b0 &&
	       stage1_rg_stage_input[112:110] != 3'b001 &&
	       stage1_rg_stage_input[112:110] != 3'b100 &&
	       stage1_rg_stage_input[112:110] != 3'b101 &&
	       stage1_rg_stage_input[112:110] != 3'b110 &&
	       stage1_rg_stage_input[112:110] != 3'b111) ?
		4'd12 :
		(IF_stage1_rg_stage_input_01_BITS_112_TO_110_30_ETC___d276 ?
		   4'd2 :
		   4'd1);
      7'b1100111, 7'b1101111:
	  IF_stage1_rg_stage_input_01_BITS_151_TO_145_28_ETC___d486 = 4'd2;
      default: IF_stage1_rg_stage_input_01_BITS_151_TO_145_28_ETC___d486 =
		   (stage1_rg_stage_input[151:145] == 7'b0110011 &&
		    stage1_rg_stage_input[104:98] == 7'b0000001) ?
		     4'd1 :
		     (((stage1_rg_stage_input[151:145] == 7'b0010011 ||
			stage1_rg_stage_input[151:145] == 7'b0110011) &&
		       (stage1_rg_stage_input[112:110] == 3'b001 ||
			stage1_rg_stage_input[112:110] == 3'b101)) ?
			(stage1_rg_stage_input[81] ? 4'd12 : 4'd1) :
			IF_stage1_rg_stage_input_01_BITS_151_TO_145_28_ETC___d482);
    endcase
  end
  always@(stage1_rg_stage_input)
  begin
    case (stage1_rg_stage_input[151:145])
      7'b1100011:
	  IF_NOT_stage1_rg_full_00_34_OR_NOT_stage1_rg_s_ETC___d571 = 2'd0;
      7'b1100111:
	  IF_NOT_stage1_rg_full_00_34_OR_NOT_stage1_rg_s_ETC___d571 = 2'd2;
      7'b1101111:
	  IF_NOT_stage1_rg_full_00_34_OR_NOT_stage1_rg_s_ETC___d571 = 2'd1;
      default: IF_NOT_stage1_rg_full_00_34_OR_NOT_stage1_rg_s_ETC___d571 =
		   2'd3;
    endcase
  end
  always@(stage1_rg_stage_input or
	  rs1_val_bypassed__h4853 or
	  eaddr__h8065 or
	  alu_outputs___1_addr__h8095 or
	  alu_outputs___1_addr__h7875 or next_pc__h7908 or next_pc__h7881)
  begin
    case (stage1_rg_stage_input[151:145])
      7'b0000011: x_out_data_to_stage2_addr__h7720 = eaddr__h8065;
      7'b0100011:
	  x_out_data_to_stage2_addr__h7720 = alu_outputs___1_addr__h8095;
      7'b1100011:
	  x_out_data_to_stage2_addr__h7720 = alu_outputs___1_addr__h7875;
      7'b1100111: x_out_data_to_stage2_addr__h7720 = next_pc__h7908;
      7'b1101111: x_out_data_to_stage2_addr__h7720 = next_pc__h7881;
      default: x_out_data_to_stage2_addr__h7720 = rs1_val_bypassed__h4853;
    endcase
  end
  always@(stage1_rg_stage_input or
	  next_pc__h7908 or branch_target__h7852 or next_pc__h7881)
  begin
    case (stage1_rg_stage_input[151:145])
      7'b1100011: x_out_cf_info_taken_PC__h9505 = branch_target__h7852;
      7'b1101111: x_out_cf_info_taken_PC__h9505 = next_pc__h7881;
      default: x_out_cf_info_taken_PC__h9505 = next_pc__h7908;
    endcase
  end
  always@(stage1_rg_stage_input or data_to_stage2_addr__h7710)
  begin
    case (stage1_rg_stage_input[151:145])
      7'b1100111, 7'b1101111:
	  CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q18 =
	      data_to_stage2_addr__h7710;
      default: CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q18 =
		   (stage1_rg_stage_input[151:145] == 7'b1110011 &&
		    stage1_rg_stage_input[112:110] == 3'b0 &&
		    stage1_rg_stage_input[144:140] == 5'd0 &&
		    stage1_rg_stage_input[139:135] == 5'd0 &&
		    stage1_rg_stage_input[87:76] == 12'b000000000001) ?
		     stage1_rg_stage_input[305:274] :
		     32'd0;
    endcase
  end
  always@(stage1_rg_stage_input or
	  _theResult_____1_fst__h8773 or
	  rd_val___1__h8741 or
	  rd_val___1__h8748 or rd_val___1__h8755 or rd_val___1__h8762)
  begin
    case (stage1_rg_stage_input[112:110])
      3'b010: _theResult_____1_fst__h8745 = rd_val___1__h8741;
      3'b011: _theResult_____1_fst__h8745 = rd_val___1__h8748;
      3'b100: _theResult_____1_fst__h8745 = rd_val___1__h8755;
      3'b110: _theResult_____1_fst__h8745 = rd_val___1__h8762;
      default: _theResult_____1_fst__h8745 = _theResult_____1_fst__h8773;
    endcase
  end
  always@(stage1_rg_stage_input)
  begin
    case (stage1_rg_stage_input[151:145])
      7'b0000011:
	  CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q19 = 3'd1;
      7'b0010011, 7'b0010111, 7'b0110011, 7'b0110111:
	  CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q19 = 3'd0;
      7'b0100011:
	  CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q19 = 3'd2;
      default: CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q19 = 3'd4;
    endcase
  end
  always@(stage1_rg_stage_input or
	  CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q19)
  begin
    case (stage1_rg_stage_input[151:145])
      7'b1100011, 7'b1100111, 7'b1101111:
	  CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q20 = 3'd0;
      default: CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q20 =
		   (stage1_rg_stage_input[151:145] == 7'b0110011 &&
		    stage1_rg_stage_input[104:98] == 7'b0000001) ?
		     3'd3 :
		     CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q19;
    endcase
  end
  always@(stage1_rg_stage_input or
	  alu_outputs___1_val1__h8304 or
	  alu_outputs___1_val1__h8028 or
	  rd_val__h8049 or rd_val__h8035 or alu_outputs___1_val1__h8284)
  begin
    case (stage1_rg_stage_input[151:145])
      7'b0010011, 7'b0110011:
	  IF_stage1_rg_stage_input_01_BITS_151_TO_145_28_ETC___d729 =
	      alu_outputs___1_val1__h8028;
      7'b0010111:
	  IF_stage1_rg_stage_input_01_BITS_151_TO_145_28_ETC___d729 =
	      rd_val__h8049;
      7'b0110111:
	  IF_stage1_rg_stage_input_01_BITS_151_TO_145_28_ETC___d729 =
	      rd_val__h8035;
      7'b1110011:
	  IF_stage1_rg_stage_input_01_BITS_151_TO_145_28_ETC___d729 =
	      alu_outputs___1_val1__h8284;
      default: IF_stage1_rg_stage_input_01_BITS_151_TO_145_28_ETC___d729 =
		   alu_outputs___1_val1__h8304;
    endcase
  end
  always@(stage1_rg_stage_input or
	  rs1_val_bypassed__h4853 or
	  IF_stage1_rg_stage_input_01_BITS_151_TO_145_28_ETC___d730 or
	  x_out_cf_info_fallthru_PC__h9504)
  begin
    case (stage1_rg_stage_input[151:145])
      7'b1100111, 7'b1101111:
	  x_out_data_to_stage2_val1__h7721 = x_out_cf_info_fallthru_PC__h9504;
      default: x_out_data_to_stage2_val1__h7721 =
		   (stage1_rg_stage_input[151:145] == 7'b0110011 &&
		    stage1_rg_stage_input[104:98] == 7'b0000001) ?
		     rs1_val_bypassed__h4853 :
		     IF_stage1_rg_stage_input_01_BITS_151_TO_145_28_ETC___d730;
    endcase
  end

  // handling of inlined registers

  always@(posedge CLK)
  begin
    if (RST_N == `BSV_RESET_VALUE)
      begin
        cfg_logdelay <= `BSV_ASSIGNMENT_DELAY 64'd0;
	cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
	imem_rg_cache_addr <= `BSV_ASSIGNMENT_DELAY 32'hFFFFFFFF;
	rg_cur_priv <= `BSV_ASSIGNMENT_DELAY 2'b11;
	rg_run_on_reset <= `BSV_ASSIGNMENT_DELAY 1'd0;
	rg_state <= `BSV_ASSIGNMENT_DELAY 4'd0;
	stage1_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
	stage2_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
	stage2_rg_resetting <= `BSV_ASSIGNMENT_DELAY 1'd0;
	stage3_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
	stageD_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
	stageF_rg_epoch <= `BSV_ASSIGNMENT_DELAY 2'd0;
	stageF_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
      end
    else
      begin
        if (cfg_logdelay$EN)
	  cfg_logdelay <= `BSV_ASSIGNMENT_DELAY cfg_logdelay$D_IN;
	if (cfg_verbosity$EN)
	  cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN;
	if (imem_rg_cache_addr$EN)
	  imem_rg_cache_addr <= `BSV_ASSIGNMENT_DELAY imem_rg_cache_addr$D_IN;
	if (rg_cur_priv$EN)
	  rg_cur_priv <= `BSV_ASSIGNMENT_DELAY rg_cur_priv$D_IN;
	if (rg_run_on_reset$EN)
	  rg_run_on_reset <= `BSV_ASSIGNMENT_DELAY rg_run_on_reset$D_IN;
	if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN;
	if (stage1_rg_full$EN)
	  stage1_rg_full <= `BSV_ASSIGNMENT_DELAY stage1_rg_full$D_IN;
	if (stage2_rg_full$EN)
	  stage2_rg_full <= `BSV_ASSIGNMENT_DELAY stage2_rg_full$D_IN;
	if (stage2_rg_resetting$EN)
	  stage2_rg_resetting <= `BSV_ASSIGNMENT_DELAY
	      stage2_rg_resetting$D_IN;
	if (stage3_rg_full$EN)
	  stage3_rg_full <= `BSV_ASSIGNMENT_DELAY stage3_rg_full$D_IN;
	if (stageD_rg_full$EN)
	  stageD_rg_full <= `BSV_ASSIGNMENT_DELAY stageD_rg_full$D_IN;
	if (stageF_rg_epoch$EN)
	  stageF_rg_epoch <= `BSV_ASSIGNMENT_DELAY stageF_rg_epoch$D_IN;
	if (stageF_rg_full$EN)
	  stageF_rg_full <= `BSV_ASSIGNMENT_DELAY stageF_rg_full$D_IN;
      end
    if (imem_rg_cache_b16$EN)
      imem_rg_cache_b16 <= `BSV_ASSIGNMENT_DELAY imem_rg_cache_b16$D_IN;
    if (imem_rg_f3$EN) imem_rg_f3 <= `BSV_ASSIGNMENT_DELAY imem_rg_f3$D_IN;
    if (imem_rg_mstatus_MXR$EN)
      imem_rg_mstatus_MXR <= `BSV_ASSIGNMENT_DELAY imem_rg_mstatus_MXR$D_IN;
    if (imem_rg_pc$EN) imem_rg_pc <= `BSV_ASSIGNMENT_DELAY imem_rg_pc$D_IN;
    if (imem_rg_priv$EN)
      imem_rg_priv <= `BSV_ASSIGNMENT_DELAY imem_rg_priv$D_IN;
    if (imem_rg_satp$EN)
      imem_rg_satp <= `BSV_ASSIGNMENT_DELAY imem_rg_satp$D_IN;
    if (imem_rg_sstatus_SUM$EN)
      imem_rg_sstatus_SUM <= `BSV_ASSIGNMENT_DELAY imem_rg_sstatus_SUM$D_IN;
    if (imem_rg_tval$EN)
      imem_rg_tval <= `BSV_ASSIGNMENT_DELAY imem_rg_tval$D_IN;
    if (rg_csr_pc$EN) rg_csr_pc <= `BSV_ASSIGNMENT_DELAY rg_csr_pc$D_IN;
    if (rg_csr_val1$EN) rg_csr_val1 <= `BSV_ASSIGNMENT_DELAY rg_csr_val1$D_IN;
    if (rg_epoch$EN) rg_epoch <= `BSV_ASSIGNMENT_DELAY rg_epoch$D_IN;
    if (rg_mstatus_MXR$EN)
      rg_mstatus_MXR <= `BSV_ASSIGNMENT_DELAY rg_mstatus_MXR$D_IN;
    if (rg_next_pc$EN) rg_next_pc <= `BSV_ASSIGNMENT_DELAY rg_next_pc$D_IN;
    if (rg_sstatus_SUM$EN)
      rg_sstatus_SUM <= `BSV_ASSIGNMENT_DELAY rg_sstatus_SUM$D_IN;
    if (rg_start_CPI_cycles$EN)
      rg_start_CPI_cycles <= `BSV_ASSIGNMENT_DELAY rg_start_CPI_cycles$D_IN;
    if (rg_start_CPI_instrs$EN)
      rg_start_CPI_instrs <= `BSV_ASSIGNMENT_DELAY rg_start_CPI_instrs$D_IN;
    if (rg_trap_info$EN)
      rg_trap_info <= `BSV_ASSIGNMENT_DELAY rg_trap_info$D_IN;
    if (rg_trap_instr$EN)
      rg_trap_instr <= `BSV_ASSIGNMENT_DELAY rg_trap_instr$D_IN;
    if (rg_trap_interrupt$EN)
      rg_trap_interrupt <= `BSV_ASSIGNMENT_DELAY rg_trap_interrupt$D_IN;
    if (stage1_rg_stage_input$EN)
      stage1_rg_stage_input <= `BSV_ASSIGNMENT_DELAY
	  stage1_rg_stage_input$D_IN;
    if (stage2_rg_stage2$EN)
      stage2_rg_stage2 <= `BSV_ASSIGNMENT_DELAY stage2_rg_stage2$D_IN;
    if (stage3_rg_stage3$EN)
      stage3_rg_stage3 <= `BSV_ASSIGNMENT_DELAY stage3_rg_stage3$D_IN;
    if (stageD_rg_data$EN)
      stageD_rg_data <= `BSV_ASSIGNMENT_DELAY stageD_rg_data$D_IN;
    if (stageF_rg_priv$EN)
      stageF_rg_priv <= `BSV_ASSIGNMENT_DELAY stageF_rg_priv$D_IN;
  end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    cfg_logdelay = 64'hAAAAAAAAAAAAAAAA;
    cfg_verbosity = 4'hA;
    imem_rg_cache_addr = 32'hAAAAAAAA;
    imem_rg_cache_b16 = 16'hAAAA;
    imem_rg_f3 = 3'h2;
    imem_rg_mstatus_MXR = 1'h0;
    imem_rg_pc = 32'hAAAAAAAA;
    imem_rg_priv = 2'h2;
    imem_rg_satp = 32'hAAAAAAAA;
    imem_rg_sstatus_SUM = 1'h0;
    imem_rg_tval = 32'hAAAAAAAA;
    rg_csr_pc = 32'hAAAAAAAA;
    rg_csr_val1 = 32'hAAAAAAAA;
    rg_cur_priv = 2'h2;
    rg_epoch = 2'h2;
    rg_mstatus_MXR = 1'h0;
    rg_next_pc = 32'hAAAAAAAA;
    rg_run_on_reset = 1'h0;
    rg_sstatus_SUM = 1'h0;
    rg_start_CPI_cycles = 64'hAAAAAAAAAAAAAAAA;
    rg_start_CPI_instrs = 64'hAAAAAAAAAAAAAAAA;
    rg_state = 4'hA;
    rg_trap_info = 68'hAAAAAAAAAAAAAAAAA;
    rg_trap_instr = 32'hAAAAAAAA;
    rg_trap_interrupt = 1'h0;
    stage1_rg_full = 1'h0;
    stage1_rg_stage_input =
	306'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    stage2_rg_full = 1'h0;
    stage2_rg_resetting = 1'h0;
    stage2_rg_stage2 = 170'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    stage3_rg_full = 1'h0;
    stage3_rg_stage3 = 104'hAAAAAAAAAAAAAAAAAAAAAAAAAA;
    stageD_rg_data = 138'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    stageD_rg_full = 1'h0;
    stageF_rg_epoch = 2'h2;
    stageF_rg_full = 1'h0;
    stageF_rg_priv = 2'h2;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on

  // handling of system tasks

  // synopsys translate_off
  always@(negedge CLK)
  begin
    #0;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$display("================================================================");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$display("%0d: Pipeline State:  minstret:%0d  cur_priv:%0d  mstatus:%0x  epoch:%0d",
		 csr_regfile$read_csr_mcycle,
		 csr_regfile$read_csr_minstret,
		 rg_cur_priv,
		 csr_regfile$read_mstatus,
		 rg_epoch);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("    ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write("MStatus{",
	       "sd:%0d",
	       csr_regfile$read_mstatus[14:13] == 2'h3 ||
	       csr_regfile$read_mstatus[16:15] == 2'h3);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && csr_regfile$read_misa[27:26] == 2'd2)
	$write(" sxl:%0d uxl:%0d", 2'd0, 2'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && csr_regfile$read_misa[27:26] != 2'd2)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" tsr:%0d", csr_regfile$read_mstatus[22]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" tw:%0d", csr_regfile$read_mstatus[21]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" tvm:%0d", csr_regfile$read_mstatus[20]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" mxr:%0d", csr_regfile$read_mstatus[19]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" sum:%0d", csr_regfile$read_mstatus[18]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" mprv:%0d", csr_regfile$read_mstatus[17]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" xs:%0d", csr_regfile$read_mstatus[16:15]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" fs:%0d", csr_regfile$read_mstatus[14:13]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" mpp:%0d", csr_regfile$read_mstatus[12:11]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" spp:%0d", csr_regfile$read_mstatus[8]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" pies:%0d_%0d%0d",
	       csr_regfile$read_mstatus[7],
	       csr_regfile$read_mstatus[5],
	       csr_regfile$read_mstatus[4]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" ies:%0d_%0d%0d",
	       csr_regfile$read_mstatus[3],
	       csr_regfile$read_mstatus[1],
	       csr_regfile$read_mstatus[0]);
    if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("    Stage3: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("Output_Stage3");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage3_rg_full) $write(" PIPE");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage3_rg_full) $write(" EMPTY");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("        Bypass  to Stage1: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("Bypass {");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  (!stage3_rg_full || !stage3_rg_stage3[37]))
	$write("Rd -");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage3_rg_full && stage3_rg_stage3[37])
	$write("Rd %0d ",
	       stage3_rg_stage3[36:32],
	       "rd_val:%h",
	       stage3_rg_stage3[31:0]);
    if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$display("    Stage2: pc 0x%08h instr 0x%08h priv %0d",
		 stage2_rg_stage2[167:136],
		 stage2_rg_stage2[135:104],
		 stage2_rg_stage2[169:168]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("        ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd0)
	$write("Output_Stage2", " EMPTY");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd1)
	$write("Output_Stage2", " BUSY: pc:%0h", stage2_rg_stage2[167:136]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd3)
	$write("Output_Stage2", " NONPIPE: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd0 &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd1 &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd3)
	$write("Output_Stage2", " PIPE: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd0 &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd1 &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd3)
	$write("data_to_Stage3 {pc:%h  instr:%h  priv:%0d\n",
	       stage2_rg_stage2[167:136],
	       stage2_rg_stage2[135:104],
	       stage2_rg_stage2[169:168]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd0 &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd1 &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd3)
	$write("        rd_valid:");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd0 &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd1 &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd3 &&
	  stage2_rg_stage2[103:101] != 3'd0 &&
	  IF_stage2_rg_stage2_7_BITS_103_TO_101_8_EQ_1_0_ETC___d141)
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd0 &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd1 &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd3 &&
	  (stage2_rg_stage2[103:101] == 3'd0 ||
	   IF_stage2_rg_stage2_7_BITS_103_TO_101_8_EQ_1_0_ETC___d150))
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd0 &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd1 &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd3)
	$write("  grd:%0d  rd_val:%h\n",
	       x_out_data_to_stage3_rd__h7092,
	       x_out_data_to_stage3_rd_val__h7093);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd3)
	$write("Trap_Info { ", "epc: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd0 &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd1 &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd3)
	$write("'h%h", stage2_rg_stage2[167:136]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd0 &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd1 &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd3)
	$write(", ", "exc_code: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd0 &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd1 &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd3)
	$write("'h%h", near_mem$dmem_exc_code);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd0 &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd1 &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd3)
	$write(", ", "tval: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd0 &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd1 &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd3)
	$write("'h%h", stage2_rg_stage2[95:64], " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd0 &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd1 &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd3)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd0 &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd1 &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd3)
	$write("Trap_Info { ", "epc: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd0 &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd1 &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd3)
	$write("'h%h", stage2_rg_stage2[167:136]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd0 &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd1 &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd3)
	$write(", ", "exc_code: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd0 &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd1 &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd3)
	$write("'h%h", near_mem$dmem_exc_code);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd0 &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd1 &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd3)
	$write(", ", "tval: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd0 &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd1 &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd3)
	$write("'h%h", stage2_rg_stage2[95:64], " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd0 &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd1 &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("        Bypass  to Stage1: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("Bypass {");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d188 == 2'd0)
	$write("Rd -");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d188 != 2'd0)
	$write("Rd %0d ", x_out_bypass_rd__h7431);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d188 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d188 == 2'd1)
	$write("-");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d188 != 2'd0 &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d188 != 2'd1)
	$write("rd_val:%h", x_out_bypass_rd_val__h7432);
    if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$display("    Stage1: pc 0x%08h instr 0x%08h priv %0d",
		 stage1_rg_stage_input[305:274],
		 stage1_rg_stage_input[231:200],
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("        ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d221)
	$write("Output_Stage1",
	       " BUSY pc:%h",
	       stage1_rg_stage_input[305:274]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 &&
	  NOT_IF_stage2_rg_full_6_THEN_IF_stage2_rg_stag_ETC___d378)
	$write("Output_Stage1",
	       " NONPIPE: pc:%h",
	       stage1_rg_stage_input[305:274]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_00_AND_NOT_stage1_rg_stage_inpu_ETC___d433)
	$write("Output_Stage1");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full)
	$write("Output_Stage1", " EMPTY");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d221)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 &&
	  NOT_IF_stage2_rg_full_6_THEN_IF_stage2_rg_stag_ETC___d378)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_00_AND_NOT_stage1_rg_stage_inpu_ETC___d433)
	$write(" PIPE: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d221)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 &&
	  NOT_IF_stage2_rg_full_6_THEN_IF_stage2_rg_stag_ETC___d378)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d382 &&
	  (!stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 ||
	   IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d430) &&
	  IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 == 4'd0)
	$write("CONTROL_DISCARD");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d382 &&
	  (!stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 ||
	   IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d430) &&
	  IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 == 4'd1)
	$write("CONTROL_STRAIGHT");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d382 &&
	  (!stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 ||
	   IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d430) &&
	  IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 == 4'd2)
	$write("CONTROL_BRANCH");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d382 &&
	  (!stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 ||
	   IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d430) &&
	  IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 == 4'd3)
	$write("CONTROL_CSRR_W");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d382 &&
	  (!stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 ||
	   IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d430) &&
	  IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 == 4'd4)
	$write("CONTROL_CSRR_S_or_C");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d382 &&
	  (!stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 ||
	   IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d430) &&
	  IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 == 4'd5)
	$write("CONTROL_FENCE");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d382 &&
	  (!stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 ||
	   IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d430) &&
	  IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 == 4'd6)
	$write("CONTROL_FENCE_I");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d382 &&
	  (!stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 ||
	   IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d430) &&
	  IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 == 4'd7)
	$write("CONTROL_SFENCE_VMA");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d382 &&
	  (!stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 ||
	   IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d430) &&
	  IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 == 4'd8)
	$write("CONTROL_MRET");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d382 &&
	  (!stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 ||
	   IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d430) &&
	  IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 == 4'd9)
	$write("CONTROL_SRET");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d382 &&
	  (!stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 ||
	   IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d430) &&
	  IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 == 4'd10)
	$write("CONTROL_URET");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d382 &&
	  (!stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 ||
	   IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d430) &&
	  IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 == 4'd11)
	$write("CONTROL_WFI");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d382 &&
	  NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d562)
	$write("CONTROL_TRAP");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d221)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 &&
	  NOT_IF_stage2_rg_full_6_THEN_IF_stage2_rg_stag_ETC___d378)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_00_AND_NOT_stage1_rg_stage_inpu_ETC___d433)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d221)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 &&
	  NOT_IF_stage2_rg_full_6_THEN_IF_stage2_rg_stag_ETC___d378)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d574)
	$write("{", "CF_None");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d578)
	$write("{", "BR ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d584)
	$write("{");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d221)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 &&
	  NOT_IF_stage2_rg_full_6_THEN_IF_stage2_rg_stag_ETC___d378)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d574)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d578)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d382 &&
	  (!stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 ||
	   IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d430) &&
	  IF_NOT_stage1_rg_full_00_34_OR_NOT_stage1_rg_s_ETC___d571 == 2'd1)
	$write("JAL [%h->%h/%h]",
	       stage1_rg_stage_input[305:274],
	       x_out_cf_info_taken_PC__h9505,
	       x_out_cf_info_fallthru_PC__h9504);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d382 &&
	  (!stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 ||
	   IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d430) &&
	  IF_NOT_stage1_rg_full_00_34_OR_NOT_stage1_rg_s_ETC___d571 == 2'd2)
	$write("JALR [%h->%h/%h]",
	       stage1_rg_stage_input[305:274],
	       x_out_cf_info_taken_PC__h9505,
	       x_out_cf_info_fallthru_PC__h9504);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d221)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 &&
	  NOT_IF_stage2_rg_full_6_THEN_IF_stage2_rg_stag_ETC___d378)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d574)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d578)
	if (stage1_rg_stage_input[151:145] != 7'b1100011 ||
	    IF_stage1_rg_stage_input_01_BITS_112_TO_110_30_ETC___d276)
	  $write("taken ");
	else
	  $write("fallthru ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d584)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d221)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 &&
	  NOT_IF_stage2_rg_full_6_THEN_IF_stage2_rg_stag_ETC___d378)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d574)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d578)
	$write("[%h->%h %h]",
	       stage1_rg_stage_input[305:274],
	       x_out_cf_info_fallthru_PC__h9504,
	       x_out_cf_info_taken_PC__h9505);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d584)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d221)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 &&
	  NOT_IF_stage2_rg_full_6_THEN_IF_stage2_rg_stag_ETC___d378)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_00_AND_NOT_stage1_rg_stage_inpu_ETC___d433)
	$write("}");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d221)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 &&
	  NOT_IF_stage2_rg_full_6_THEN_IF_stage2_rg_stag_ETC___d378)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_00_AND_NOT_stage1_rg_stage_inpu_ETC___d433)
	$write("data_to_Stage 2 {pc:%h  instr:%h  priv:%0d\n",
	       stage1_rg_stage_input[305:274],
	       stage1_rg_stage_input[231:200],
	       rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d221)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 &&
	  NOT_IF_stage2_rg_full_6_THEN_IF_stage2_rg_stag_ETC___d378)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_00_AND_NOT_stage1_rg_stage_inpu_ETC___d433)
	$write("            op_stage2:");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d221)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 &&
	  NOT_IF_stage2_rg_full_6_THEN_IF_stage2_rg_stag_ETC___d378)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d382 &&
	  (!stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 ||
	   IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d430) &&
	  IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d631 == 3'd0)
	$write("OP_Stage2_ALU");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d382 &&
	  (!stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 ||
	   IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d430) &&
	  IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d631 == 3'd1)
	$write("OP_Stage2_LD");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d382 &&
	  (!stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 ||
	   IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d430) &&
	  IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d631 == 3'd2)
	$write("OP_Stage2_ST");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d382 &&
	  (!stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 ||
	   IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d430) &&
	  IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d631 == 3'd3)
	$write("OP_Stage2_M");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d382 &&
	  (!stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 ||
	   IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d430) &&
	  IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d631 != 3'd0 &&
	  IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d631 != 3'd1 &&
	  IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d631 != 3'd2 &&
	  IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d631 != 3'd3)
	$write("OP_Stage2_AMO");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d221)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 &&
	  NOT_IF_stage2_rg_full_6_THEN_IF_stage2_rg_stag_ETC___d378)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_00_AND_NOT_stage1_rg_stage_inpu_ETC___d433)
	$write("  rd:%0d\n", x_out_data_to_stage2_rd__h7719);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d221)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 &&
	  NOT_IF_stage2_rg_full_6_THEN_IF_stage2_rg_stag_ETC___d378)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_00_AND_NOT_stage1_rg_stage_inpu_ETC___d433)
	$write("            addr:%h  val1:%h  val2:%h}",
	       x_out_data_to_stage2_addr__h7720,
	       x_out_data_to_stage2_val1__h7721,
	       x_out_data_to_stage2_val2__h7722);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d221)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 &&
	  NOT_IF_stage2_rg_full_6_THEN_IF_stage2_rg_stag_ETC___d378)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_00_AND_NOT_stage1_rg_stage_inpu_ETC___d433)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d221)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 &&
	  NOT_IF_stage2_rg_full_6_THEN_IF_stage2_rg_stag_ETC___d378 &&
	  IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 == 4'd0)
	$write("CONTROL_DISCARD");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 &&
	  NOT_IF_stage2_rg_full_6_THEN_IF_stage2_rg_stag_ETC___d378 &&
	  IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 == 4'd1)
	$write("CONTROL_STRAIGHT");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 &&
	  NOT_IF_stage2_rg_full_6_THEN_IF_stage2_rg_stag_ETC___d378 &&
	  IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 == 4'd2)
	$write("CONTROL_BRANCH");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 &&
	  NOT_IF_stage2_rg_full_6_THEN_IF_stage2_rg_stag_ETC___d378 &&
	  IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 == 4'd3)
	$write("CONTROL_CSRR_W");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 &&
	  NOT_IF_stage2_rg_full_6_THEN_IF_stage2_rg_stag_ETC___d378 &&
	  IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 == 4'd4)
	$write("CONTROL_CSRR_S_or_C");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 &&
	  NOT_IF_stage2_rg_full_6_THEN_IF_stage2_rg_stag_ETC___d378 &&
	  IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 == 4'd5)
	$write("CONTROL_FENCE");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 &&
	  NOT_IF_stage2_rg_full_6_THEN_IF_stage2_rg_stag_ETC___d378 &&
	  IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 == 4'd6)
	$write("CONTROL_FENCE_I");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 &&
	  NOT_IF_stage2_rg_full_6_THEN_IF_stage2_rg_stag_ETC___d378 &&
	  IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 == 4'd7)
	$write("CONTROL_SFENCE_VMA");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 &&
	  NOT_IF_stage2_rg_full_6_THEN_IF_stage2_rg_stag_ETC___d378 &&
	  IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 == 4'd8)
	$write("CONTROL_MRET");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 &&
	  NOT_IF_stage2_rg_full_6_THEN_IF_stage2_rg_stag_ETC___d378 &&
	  IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 == 4'd9)
	$write("CONTROL_SRET");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 &&
	  NOT_IF_stage2_rg_full_6_THEN_IF_stage2_rg_stag_ETC___d378 &&
	  IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 == 4'd10)
	$write("CONTROL_URET");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 &&
	  NOT_IF_stage2_rg_full_6_THEN_IF_stage2_rg_stag_ETC___d378 &&
	  IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 == 4'd11)
	$write("CONTROL_WFI");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d766)
	$write("CONTROL_TRAP");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_00_AND_NOT_stage1_rg_stage_inpu_ETC___d433)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d221)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 &&
	  NOT_IF_stage2_rg_full_6_THEN_IF_stage2_rg_stag_ETC___d378)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_00_AND_NOT_stage1_rg_stage_inpu_ETC___d433)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d221)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 &&
	  NOT_IF_stage2_rg_full_6_THEN_IF_stage2_rg_stag_ETC___d378)
	$write("Trap_Info { ", "epc: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_00_AND_NOT_stage1_rg_stage_inpu_ETC___d433)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d221)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 &&
	  NOT_IF_stage2_rg_full_6_THEN_IF_stage2_rg_stag_ETC___d378)
	$write("'h%h", stage1_rg_stage_input[305:274]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_00_AND_NOT_stage1_rg_stage_inpu_ETC___d433)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d221)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 &&
	  NOT_IF_stage2_rg_full_6_THEN_IF_stage2_rg_stag_ETC___d378)
	$write(", ", "exc_code: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_00_AND_NOT_stage1_rg_stage_inpu_ETC___d433)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d221)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 &&
	  NOT_IF_stage2_rg_full_6_THEN_IF_stage2_rg_stag_ETC___d378)
	$write("'h%h", x_out_trap_info_exc_code__h9335);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_00_AND_NOT_stage1_rg_stage_inpu_ETC___d433)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d221)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 &&
	  NOT_IF_stage2_rg_full_6_THEN_IF_stage2_rg_stag_ETC___d378)
	$write(", ", "tval: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_00_AND_NOT_stage1_rg_stage_inpu_ETC___d433)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d221)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 &&
	  NOT_IF_stage2_rg_full_6_THEN_IF_stage2_rg_stag_ETC___d378)
	$write("'h%h", value__h9376, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_00_AND_NOT_stage1_rg_stage_inpu_ETC___d433)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d221)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d382 &&
	  !IF_IF_stage1_rg_stage_input_01_BITS_151_TO_145_ETC___d813)
	$write("\n        redirect next_pc:%h", x_out_next_pc__h7677);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_stage1_rg_stage_input_01_BITS_271_TO_270_0_ETC___d382 &&
	  IF_IF_stage1_rg_stage_input_01_BITS_151_TO_145_ETC___d813)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$display("    StageD: pc 0x%08h instr 0x%08h priv %0d epoch %0d",
		 stageD_rg_data[137:106],
		 x_out_data_to_stage1_instr__h10032,
		 stageD_rg_data[103:102],
		 stageD_rg_data[105:104]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("        ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("Output_StageD");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full) $write(" PIPE: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write(" EMPTY");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && stageD_rg_data[100])
	$write("data_to_Stage1 {pc:%0h  priv:%0d  epoch:%0d",
	       stageD_rg_data[137:106],
	       stageD_rg_data[103:102],
	       stageD_rg_data[105:104]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && !stageD_rg_data[100])
	$write("data_to_Stage1 {pc:%0h  priv:%0d  epoch:%0d",
	       stageD_rg_data[137:106],
	       stageD_rg_data[103:102],
	       stageD_rg_data[105:104]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && stageD_rg_data[100])
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
	  !stageD_rg_data[100] &&
	  stageD_rg_data[101])
	$write("  instr_C:%0h", stageD_rg_data[47:32]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
	  !stageD_rg_data[100] &&
	  !stageD_rg_data[101])
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && stageD_rg_data[100])
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && !stageD_rg_data[100])
	$write("  instr:%0h  pred_pc:%0h",
	       x_out_data_to_stage1_instr__h10032,
	       stageD_rg_data[31:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && stageD_rg_data[100])
	$write("  ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && !stageD_rg_data[100])
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
	  stageD_rg_data[100] &&
	  stageD_rg_data[99:96] == 4'd0)
	$write("INSTRUCTION_ADDR_MISALIGNED");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
	  stageD_rg_data[100] &&
	  stageD_rg_data[99:96] == 4'd1)
	$write("INSTRUCTION_ACCESS_FAULT");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
	  stageD_rg_data[100] &&
	  stageD_rg_data[99:96] == 4'd2)
	$write("ILLEGAL_INSTRUCTION");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
	  stageD_rg_data[100] &&
	  stageD_rg_data[99:96] == 4'd3)
	$write("BREAKPOINT");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
	  stageD_rg_data[100] &&
	  stageD_rg_data[99:96] == 4'd4)
	$write("LOAD_ADDR_MISALIGNED");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
	  stageD_rg_data[100] &&
	  stageD_rg_data[99:96] == 4'd5)
	$write("LOAD_ACCESS_FAULT");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
	  stageD_rg_data[100] &&
	  stageD_rg_data[99:96] == 4'd6)
	$write("STORE_AMO_ADDR_MISALIGNED");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
	  stageD_rg_data[100] &&
	  stageD_rg_data[99:96] == 4'd7)
	$write("STORE_AMO_ACCESS_FAULT");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
	  stageD_rg_data[100] &&
	  stageD_rg_data[99:96] == 4'd8)
	$write("ECALL_FROM_U");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
	  stageD_rg_data[100] &&
	  stageD_rg_data[99:96] == 4'd9)
	$write("ECALL_FROM_S");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
	  stageD_rg_data[100] &&
	  stageD_rg_data[99:96] == 4'd11)
	$write("ECALL_FROM_M");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
	  stageD_rg_data[100] &&
	  stageD_rg_data[99:96] == 4'd12)
	$write("INSTRUCTION_PAGE_FAULT");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
	  stageD_rg_data[100] &&
	  stageD_rg_data[99:96] == 4'd13)
	$write("LOAD_PAGE_FAULT");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
	  stageD_rg_data[100] &&
	  stageD_rg_data[99:96] == 4'd15)
	$write("STORE_AMO_PAGE_FAULT");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
	  stageD_rg_data[100] &&
	  stageD_rg_data[99:96] != 4'd0 &&
	  stageD_rg_data[99:96] != 4'd1 &&
	  stageD_rg_data[99:96] != 4'd2 &&
	  stageD_rg_data[99:96] != 4'd3 &&
	  stageD_rg_data[99:96] != 4'd4 &&
	  stageD_rg_data[99:96] != 4'd5 &&
	  stageD_rg_data[99:96] != 4'd6 &&
	  stageD_rg_data[99:96] != 4'd7 &&
	  stageD_rg_data[99:96] != 4'd8 &&
	  stageD_rg_data[99:96] != 4'd9 &&
	  stageD_rg_data[99:96] != 4'd11 &&
	  stageD_rg_data[99:96] != 4'd12 &&
	  stageD_rg_data[99:96] != 4'd13 &&
	  stageD_rg_data[99:96] != 4'd15)
	$write("unknown trap Exc_Code %d", stageD_rg_data[99:96]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && !stageD_rg_data[100])
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && stageD_rg_data[100])
	$write(" tval %0h", stageD_rg_data[95:64]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && !stageD_rg_data[100])
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full) $write("}");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$display("    StageF: pc 0x%08h instr 0x%08h priv %0d epoch %0d",
		 imem_rg_pc,
		 d_instr__h15515,
		 stageF_rg_priv,
		 stageF_rg_epoch);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("        ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("Output_StageF");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
	  (!near_mem$imem_valid ||
	   imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1211))
	$write(" BUSY: pc:%h", imem_rg_pc);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
	  near_mem$imem_valid &&
	  NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1217)
	$write(" PIPE: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stageF_rg_full) $write(" EMPTY");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
	  (!near_mem$imem_valid ||
	   imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1211))
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
	  near_mem$imem_valid &&
	  NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1217)
	$write("data_to_StageD {pc:%h  priv:%0d  epoch:%0d",
	       imem_rg_pc,
	       stageF_rg_priv,
	       stageF_rg_epoch);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stageF_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
	  (!near_mem$imem_valid ||
	   imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1211))
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
	  near_mem$imem_valid &&
	  NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1217 &&
	  near_mem$imem_exc)
	$write("  ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stageF_rg_full_194_AND_near_mem_imem_valid_AND_ETC___d1226)
	$write("  instr:%h  pred_pc:%h",
	       d_instr__h15515,
	       stageF_branch_predictor$predict_rsp);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stageF_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
	  (!near_mem$imem_valid ||
	   imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1211))
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stageF_rg_full_194_AND_near_mem_imem_valid_AND_ETC___d1232)
	$write("INSTRUCTION_ADDR_MISALIGNED");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stageF_rg_full_194_AND_near_mem_imem_valid_AND_ETC___d1236)
	$write("INSTRUCTION_ACCESS_FAULT");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stageF_rg_full_194_AND_near_mem_imem_valid_AND_ETC___d1240)
	$write("ILLEGAL_INSTRUCTION");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stageF_rg_full_194_AND_near_mem_imem_valid_AND_ETC___d1244)
	$write("BREAKPOINT");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stageF_rg_full_194_AND_near_mem_imem_valid_AND_ETC___d1248)
	$write("LOAD_ADDR_MISALIGNED");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stageF_rg_full_194_AND_near_mem_imem_valid_AND_ETC___d1252)
	$write("LOAD_ACCESS_FAULT");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stageF_rg_full_194_AND_near_mem_imem_valid_AND_ETC___d1256)
	$write("STORE_AMO_ADDR_MISALIGNED");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stageF_rg_full_194_AND_near_mem_imem_valid_AND_ETC___d1260)
	$write("STORE_AMO_ACCESS_FAULT");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stageF_rg_full_194_AND_near_mem_imem_valid_AND_ETC___d1264)
	$write("ECALL_FROM_U");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stageF_rg_full_194_AND_near_mem_imem_valid_AND_ETC___d1268)
	$write("ECALL_FROM_S");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stageF_rg_full_194_AND_near_mem_imem_valid_AND_ETC___d1272)
	$write("ECALL_FROM_M");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stageF_rg_full_194_AND_near_mem_imem_valid_AND_ETC___d1276)
	$write("INSTRUCTION_PAGE_FAULT");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stageF_rg_full_194_AND_near_mem_imem_valid_AND_ETC___d1280)
	$write("LOAD_PAGE_FAULT");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stageF_rg_full_194_AND_near_mem_imem_valid_AND_ETC___d1284)
	$write("STORE_AMO_PAGE_FAULT");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d1313)
	$write("unknown trap Exc_Code %d", near_mem$imem_exc_code);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stageF_rg_full_194_AND_near_mem_imem_valid_AND_ETC___d1226)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stageF_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
	  (!near_mem$imem_valid ||
	   imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1211))
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
	  near_mem$imem_valid &&
	  NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1217)
	$write("}");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stageF_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $display("----------------");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage2_nonpipe &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$display("%0d: %m.rl_stage2_nonpipe", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_trap &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$display("%0d: %m.rl_stage1_trap", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_trap &&
	  rg_trap_info_633_BITS_67_TO_36_634_EQ_csr_regf_ETC___d1643)
	$display("%0d: %m.rl_stage1_trap: Tight infinite trap loop: pc 0x%0x instr 0x%08x",
		 csr_regfile$read_csr_mcycle,
		 csr_regfile$csr_trap_actions[97:66],
		 rg_trap_instr);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_trap &&
	  rg_trap_info_633_BITS_67_TO_36_634_EQ_csr_regf_ETC___d1643)
	$display("CPI: %0d.%0d = (%0d/%0d) since last 'continue'",
		 cpi__h21592,
		 cpifrac__h21593,
		 delta_CPI_cycles__h21588,
		 _theResult____h21590);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_trap &&
	  rg_trap_info_633_BITS_67_TO_36_634_EQ_csr_regf_ETC___d1643)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_trap && cur_verbosity__h3333 != 4'd0)
	$display("instret:%0d  PC:0x%0h  instr:0x%0h  priv:%0d",
		 csr_regfile$read_csr_minstret,
		 rg_trap_info[67:36],
		 rg_trap_instr,
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_trap && cur_verbosity__h3333 != 4'd0)
	$display("    mcause:0x%0h  epc 0x%0h  tval:0x%0h  next_pc 0x%0h, new_priv %0d new_mstatus 0x%0h",
		 csr_regfile$csr_trap_actions[33:2],
		 rg_trap_info[67:36],
		 rg_trap_info[31:0],
		 csr_regfile$csr_trap_actions[97:66],
		 csr_regfile$csr_trap_actions[1:0],
		 csr_regfile$csr_trap_actions[65:34]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_CSRR_W &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$display("%0d: %m.rl_stage1_CSRR_W", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$display("%0d: %m.rl_stage1_CSRR_W_2", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_CSRR_W_2 && csr_regfile$access_permitted_1 &&
	  cur_verbosity__h3333 != 4'd0)
	$display("instret:%0d  PC:0x%0h  instr:0x%0h  priv:%0d",
		 csr_regfile$read_csr_minstret,
		 rg_csr_pc,
		 rg_trap_instr,
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_CSRR_W_2 && csr_regfile$access_permitted_1 &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$display("    S1: write CSRRW/CSRRWI Rs1 %0d Rs1_val 0x%0h csr 0x%0h csr_val 0x%0h Rd %0d",
		 rg_trap_instr[19:15],
		 rs1_val__h22063,
		 rg_trap_instr[31:20],
		 csr_regfile$read_csr[31:0],
		 rg_trap_instr[11:7]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
	  !csr_regfile$access_permitted_1 &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$display("    Trap on CSR permissions: Rs1 %0d Rs1_val 0x%0h csr 0x%0h Rd %0d",
		 rg_trap_instr[19:15],
		 rs1_val__h22063,
		 rg_trap_instr[31:20],
		 rg_trap_instr[11:7]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$display("%0d: %m.rl_stage1_CSRR_S_or_C",
		 csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$display("%0d: %m.rl_stage1_CSRR_S_or_C_2",
		 csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
	  csr_regfile$access_permitted_2 &&
	  cur_verbosity__h3333 != 4'd0)
	$display("instret:%0d  PC:0x%0h  instr:0x%0h  priv:%0d",
		 csr_regfile$read_csr_minstret,
		 rg_csr_pc,
		 rg_trap_instr,
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
	  csr_regfile$access_permitted_2 &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$display("    S1: write CSRR_S_or_C: Rs1 %0d Rs1_val 0x%0h csr 0x%0h csr_val 0x%0h Rd %0d",
		 rg_trap_instr[19:15],
		 rs1_val__h22743,
		 rg_trap_instr[31:20],
		 csr_regfile$read_csr[31:0],
		 rg_trap_instr[11:7]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
	  !csr_regfile$access_permitted_2 &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$display("    Trap on CSR permissions: Rs1 %0d Rs1_val 0x%0h csr 0x%0h Rd %0d",
		 rg_trap_instr[19:15],
		 rs1_val__h22743,
		 rg_trap_instr[31:20],
		 rg_trap_instr[11:7]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$display("%0d: %m.rl_stage1_restart_after_csrrx",
		 csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$write("    %m.enq:  pc:0x%0h  epoch:%0d  priv:%0d",
	       rg_next_pc,
	       new_epoch__h16878,
	       rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$write("  sstatus_SUM:%0d  mstatus_MXR:%0d  satp:0x%0h",
	       1'd0,
	       csr_regfile$read_mstatus[19],
	       csr_regfile$read_satp);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$display("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$display("    fa_stageF_redirect: minstret:%0d  new_pc:%0x  cur_priv:%0d, epoch %0d->%0d",
		 csr_regfile$read_csr_minstret,
		 rg_next_pc,
		 rg_cur_priv,
		 rg_epoch,
		 new_epoch__h16878);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_xRET &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$display("%0d: %m.rl_stage1_xRET", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_xRET && cur_verbosity__h3333 != 4'd0)
	$display("instret:%0d  PC:0x%0h  instr:0x%0h  priv:%0d",
		 csr_regfile$read_csr_minstret,
		 stage1_rg_stage_input[305:274],
		 stage1_rg_stage_input[231:200],
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_xRET && cur_verbosity__h3333 != 4'd0)
	$display("    xRET: next_pc:0x%0h  new mstatus:0x%0h  new priv:%0d",
		 csr_regfile$csr_ret_actions[65:34],
		 csr_regfile$csr_ret_actions[31:0],
		 csr_regfile$csr_ret_actions[33:32]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_FENCE_I &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$display("%0d: %m.rl_stage1_FENCE_I", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_FENCE_I && cur_verbosity__h3333 != 4'd0)
	$display("instret:%0d  PC:0x%0h  instr:0x%0h  priv:%0d",
		 csr_regfile$read_csr_minstret,
		 stage1_rg_stage_input[305:274],
		 stage1_rg_stage_input[231:200],
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_FENCE_I &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$display("%0d: %m.rl_stage1_FENCE_I", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_FENCE_I &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$display("%0d: %m.rl_finish_FENCE_I", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_FENCE_I &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$write("    %m.enq:  pc:0x%0h  epoch:%0d  priv:%0d",
	       rg_next_pc,
	       new_epoch__h16878,
	       rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_FENCE_I &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$write("  sstatus_SUM:%0d  mstatus_MXR:%0d  satp:0x%0h",
	       1'd0,
	       csr_regfile$read_mstatus[19],
	       csr_regfile$read_satp);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_FENCE_I &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$display("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_FENCE_I &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$display("    fa_stageF_redirect: minstret:%0d  new_pc:%0x  cur_priv:%0d, epoch %0d->%0d",
		 csr_regfile$read_csr_minstret,
		 rg_next_pc,
		 rg_cur_priv,
		 rg_epoch,
		 new_epoch__h16878);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_FENCE_I &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$display("    CPU.rl_finish_FENCE_I");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_FENCE &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$display("%0d: %m.rl_stage1_FENCE", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_FENCE && cur_verbosity__h3333 != 4'd0)
	$display("instret:%0d  PC:0x%0h  instr:0x%0h  priv:%0d",
		 csr_regfile$read_csr_minstret,
		 stage1_rg_stage_input[305:274],
		 stage1_rg_stage_input[231:200],
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_FENCE &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$display("%0d: %m.rl_stage1_FENCE", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_FENCE &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$display("%0d: %m.rl_finish_FENCE", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_FENCE &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$write("    %m.enq:  pc:0x%0h  epoch:%0d  priv:%0d",
	       rg_next_pc,
	       new_epoch__h16878,
	       rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_FENCE &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$write("  sstatus_SUM:%0d  mstatus_MXR:%0d  satp:0x%0h",
	       1'd0,
	       csr_regfile$read_mstatus[19],
	       csr_regfile$read_satp);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_FENCE &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$display("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_FENCE &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$display("    fa_stageF_redirect: minstret:%0d  new_pc:%0x  cur_priv:%0d, epoch %0d->%0d",
		 csr_regfile$read_csr_minstret,
		 rg_next_pc,
		 rg_cur_priv,
		 rg_epoch,
		 new_epoch__h16878);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_FENCE &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$display("    CPU.rl_finish_FENCE");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_WFI &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$display("%0d: %m.rl_stage1_WFI", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_WFI && cur_verbosity__h3333 != 4'd0)
	$display("instret:%0d  PC:0x%0h  instr:0x%0h  priv:%0d",
		 csr_regfile$read_csr_minstret,
		 stage1_rg_stage_input[305:274],
		 stage1_rg_stage_input[231:200],
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_WFI &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$display("    CPU.rl_stage1_WFI");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_WFI_resume &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$display("%0d: %m.rl_WFI_resume", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_WFI_resume &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$write("    %m.enq:  pc:0x%0h  epoch:%0d  priv:%0d",
	       rg_next_pc,
	       new_epoch__h16878,
	       rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_WFI_resume &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$write("  sstatus_SUM:%0d  mstatus_MXR:%0d  satp:0x%0h",
	       1'd0,
	       csr_regfile$read_mstatus[19],
	       csr_regfile$read_satp);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_WFI_resume &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$display("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_WFI_resume &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$display("    fa_stageF_redirect: minstret:%0d  new_pc:%0x  cur_priv:%0d, epoch %0d->%0d",
		 csr_regfile$read_csr_minstret,
		 rg_next_pc,
		 rg_cur_priv,
		 rg_epoch,
		 new_epoch__h16878);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_from_WFI &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$display("%0d: %m.rl_reset_from_WFI", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_trap_fetch &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$write("    %m.enq:  pc:0x%0h  epoch:%0d  priv:%0d",
	       rg_next_pc,
	       new_epoch__h16878,
	       rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_trap_fetch &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$write("  sstatus_SUM:%0d  mstatus_MXR:%0d  satp:0x%0h",
	       1'd0,
	       csr_regfile$read_mstatus[19],
	       csr_regfile$read_satp);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_trap_fetch &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$display("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_trap_fetch &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$display("    fa_stageF_redirect: minstret:%0d  new_pc:%0x  cur_priv:%0d, epoch %0d->%0d",
		 csr_regfile$read_csr_minstret,
		 rg_next_pc,
		 rg_cur_priv,
		 rg_epoch,
		 new_epoch__h16878);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_interrupt &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$display("%0d: %m.rl_stage1_interrupt", csr_regfile$read_csr_mcycle);
    if (WILL_FIRE_RL_imem_rl_assert_fail)
      begin
        v__h2152 = $stime;
	#0;
      end
    v__h2146 = v__h2152 / 32'd10;
    if (WILL_FIRE_RL_imem_rl_assert_fail)
      $display("%0d: ERROR: CPU_Fetch_C: imem32.is_i32_not_i16 is False",
	       v__h2146);
    if (WILL_FIRE_RL_imem_rl_assert_fail) $finish(32'd1);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset)
	$display("%0d: %m.rl_reset_complete: restart at PC = 0x%0h",
		 csr_regfile$read_csr_mcycle,
		 soc_map$m_pc_reset_value[31:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$write("    %m.enq:  pc:0x%0h  epoch:%0d  priv:%0d",
	       soc_map$m_pc_reset_value[31:0],
	       new_epoch__h16878,
	       rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$write("  sstatus_SUM:%0d  mstatus_MXR:%0d  satp:0x%0h",
	       1'd0,
	       csr_regfile$read_mstatus[19],
	       csr_regfile$read_satp);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$display("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$display("    fa_stageF_redirect: minstret:%0d  new_pc:%0x  cur_priv:%0d, epoch %0d->%0d",
		 csr_regfile$read_csr_minstret,
		 soc_map$m_pc_reset_value[31:0],
		 rg_cur_priv,
		 rg_epoch,
		 new_epoch__h16878);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_complete && !rg_run_on_reset)
	$display("%0d: %m.rl_reset_complete: entering DEBUG_MODE",
		 csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$display("%0d: %m.rl_pipe", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[37] &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$display("    S3.fa_deq: write GRd 0x%0h, rd_val 0x%0h",
		 stage3_rg_stage3[36:32],
		 stage3_rg_stage3[31:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd2 &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$write("    S3.enq: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd2 &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$write("data_to_Stage3 {pc:%h  instr:%h  priv:%0d\n",
	       stage2_rg_stage2[167:136],
	       stage2_rg_stage2[135:104],
	       stage2_rg_stage2[169:168]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd2 &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$write("        rd_valid:");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd2 &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49 &&
	  stage2_rg_stage2[103:101] != 3'd0 &&
	  IF_stage2_rg_stage2_7_BITS_103_TO_101_8_EQ_1_0_ETC___d141)
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd2 &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49 &&
	  (stage2_rg_stage2[103:101] == 3'd0 ||
	   IF_stage2_rg_stage2_7_BITS_103_TO_101_8_EQ_1_0_ETC___d150))
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd2 &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$write("  grd:%0d  rd_val:%h\n",
	       x_out_data_to_stage3_rd__h7092,
	       x_out_data_to_stage3_rd_val__h7093);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd2 &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  IF_stage2_rg_full_6_THEN_IF_stage2_rg_stage2_7_ETC___d127 == 2'd2 &&
	  cur_verbosity__h3333 != 4'd0)
	$display("instret:%0d  PC:0x%0h  instr:0x%0h  priv:%0d",
		 csr_regfile$read_csr_minstret,
		 stage2_rg_stage2[167:136],
		 stage2_rg_stage2[135:104],
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1453 &&
	  stage1_rg_full &&
	  (!stage1_rg_stage_input_01_BITS_271_TO_270_02_EQ_ETC___d203 ||
	   NOT_IF_stage2_rg_full_6_THEN_IF_stage2_rg_stag_ETC___d1393) &&
	  IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 == 4'd0 &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$display("    rl_pipe: Discarding stage1 due to redirection");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1490)
	$write("    CPU_Stage2.enq (Data_Stage1_to_Stage2) ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1490)
	$write("data_to_Stage 2 {pc:%h  instr:%h  priv:%0d\n",
	       stage1_rg_stage_input[305:274],
	       stage1_rg_stage_input[231:200],
	       rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1490)
	$write("            op_stage2:");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1460 &&
	  IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 != 4'd0 &&
	  IF_NOT_stage1_rg_full_00_34_OR_NOT_stage1_rg_s_ETC___d1463 &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49 &&
	  IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d631 == 3'd0)
	$write("OP_Stage2_ALU");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1460 &&
	  IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 != 4'd0 &&
	  IF_NOT_stage1_rg_full_00_34_OR_NOT_stage1_rg_s_ETC___d1463 &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49 &&
	  IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d631 == 3'd1)
	$write("OP_Stage2_LD");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1460 &&
	  IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 != 4'd0 &&
	  IF_NOT_stage1_rg_full_00_34_OR_NOT_stage1_rg_s_ETC___d1463 &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49 &&
	  IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d631 == 3'd2)
	$write("OP_Stage2_ST");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1460 &&
	  IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 != 4'd0 &&
	  IF_NOT_stage1_rg_full_00_34_OR_NOT_stage1_rg_s_ETC___d1463 &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49 &&
	  IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d631 == 3'd3)
	$write("OP_Stage2_M");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1460 &&
	  IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d489 != 4'd0 &&
	  IF_NOT_stage1_rg_full_00_34_OR_NOT_stage1_rg_s_ETC___d1463 &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49 &&
	  IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d631 != 3'd0 &&
	  IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d631 != 3'd1 &&
	  IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d631 != 3'd2 &&
	  IF_stage1_rg_stage_input_01_BITS_271_TO_270_02_ETC___d631 != 3'd3)
	$write("OP_Stage2_AMO");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1490)
	$write("  rd:%0d\n", x_out_data_to_stage2_rd__h7719);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1490)
	$write("            addr:%h  val1:%h  val2:%h}",
	       x_out_data_to_stage2_addr__h7720,
	       x_out_data_to_stage2_val1__h7721,
	       x_out_data_to_stage2_val2__h7722);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1490)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1516 &&
	  stageD_rg_full &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$display("    CPU_Stage1.enq: 0x%08h", stageD_rg_data[137:106]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1557 &&
	  NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
	$display("    CPU_StageD.enq (Data_StageF_to_StageD)");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1557 &&
	  csr_regfile_interrupt_pending_rg_cur_priv_1_37_ETC___d1574)
	$write("    %m.enq:  pc:0x%0h  epoch:%0d  priv:%0d",
	       stageF_branch_predictor$predict_rsp,
	       stageF_rg_epoch,
	       rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1557 &&
	  csr_regfile_interrupt_pending_rg_cur_priv_1_37_ETC___d1574)
	$write("  sstatus_SUM:%0d  mstatus_MXR:%0d  satp:0x%0h",
	       1'd0,
	       csr_regfile$read_mstatus[19],
	       csr_regfile$read_satp);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1557 &&
	  csr_regfile_interrupt_pending_rg_cur_priv_1_37_ETC___d1574)
	$display("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_start)
	$display("================================================================");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_start)
	$write("CPU: Bluespec  RISC-V  Flute  v3.0");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_start) $display(" (RV32)");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_start)
	$display("Copyright (c) 2016-2020 Bluespec, Inc. All Rights Reserved.");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_start)
	$display("================================================================");
  end
  // synopsys translate_on
endmodule  // mkCPU

