//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
//
//
//
// Ports:
// Name                         I/O  size props
// RDY_reset                      O     1 const
// av_read                        O    32
// RDY_av_read                    O     1 const
// RDY_write                      O     1 const
// hart0_gpr_mem_client_request_get  O    70 reg
// RDY_hart0_gpr_mem_client_request_get  O     1 reg
// RDY_hart0_gpr_mem_client_response_put  O     1 reg
// hart0_fpr_mem_client_request_get  O    70 reg
// RDY_hart0_fpr_mem_client_request_get  O     1 reg
// RDY_hart0_fpr_mem_client_response_put  O     1 reg
// hart0_csr_mem_client_request_get  O    77 reg
// RDY_hart0_csr_mem_client_request_get  O     1 reg
// RDY_hart0_csr_mem_client_response_put  O     1 reg
// CLK                            I     1 clock
// RST_N                          I     1 reset
// av_read_dm_addr                I     7
// write_dm_addr                  I     7
// write_dm_word                  I    32
// hart0_gpr_mem_client_response_put  I    65 reg
// hart0_fpr_mem_client_response_put  I    65 reg
// hart0_csr_mem_client_response_put  I    65 reg
// EN_reset                       I     1
// EN_write                       I     1
// EN_hart0_gpr_mem_client_response_put  I     1
// EN_hart0_fpr_mem_client_response_put  I     1
// EN_hart0_csr_mem_client_response_put  I     1
// EN_av_read                     I     1 unused
// EN_hart0_gpr_mem_client_request_get  I     1
// EN_hart0_fpr_mem_client_request_get  I     1
// EN_hart0_csr_mem_client_request_get  I     1
//
// Combinational paths from inputs to outputs:
//   av_read_dm_addr -> av_read
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkDM_Abstract_Commands(CLK,
			      RST_N,

			      EN_reset,
			      RDY_reset,

			      av_read_dm_addr,
			      EN_av_read,
			      av_read,
			      RDY_av_read,

			      write_dm_addr,
			      write_dm_word,
			      EN_write,
			      RDY_write,

			      EN_hart0_gpr_mem_client_request_get,
			      hart0_gpr_mem_client_request_get,
			      RDY_hart0_gpr_mem_client_request_get,

			      hart0_gpr_mem_client_response_put,
			      EN_hart0_gpr_mem_client_response_put,
			      RDY_hart0_gpr_mem_client_response_put,

			      EN_hart0_fpr_mem_client_request_get,
			      hart0_fpr_mem_client_request_get,
			      RDY_hart0_fpr_mem_client_request_get,

			      hart0_fpr_mem_client_response_put,
			      EN_hart0_fpr_mem_client_response_put,
			      RDY_hart0_fpr_mem_client_response_put,

			      EN_hart0_csr_mem_client_request_get,
			      hart0_csr_mem_client_request_get,
			      RDY_hart0_csr_mem_client_request_get,

			      hart0_csr_mem_client_response_put,
			      EN_hart0_csr_mem_client_response_put,
			      RDY_hart0_csr_mem_client_response_put);
  input  CLK;
  input  RST_N;

  // action method reset
  input  EN_reset;
  output RDY_reset;

  // actionvalue method av_read
  input  [6 : 0] av_read_dm_addr;
  input  EN_av_read;
  output [31 : 0] av_read;
  output RDY_av_read;

  // action method write
  input  [6 : 0] write_dm_addr;
  input  [31 : 0] write_dm_word;
  input  EN_write;
  output RDY_write;

  // actionvalue method hart0_gpr_mem_client_request_get
  input  EN_hart0_gpr_mem_client_request_get;
  output [69 : 0] hart0_gpr_mem_client_request_get;
  output RDY_hart0_gpr_mem_client_request_get;

  // action method hart0_gpr_mem_client_response_put
  input  [64 : 0] hart0_gpr_mem_client_response_put;
  input  EN_hart0_gpr_mem_client_response_put;
  output RDY_hart0_gpr_mem_client_response_put;

  // actionvalue method hart0_fpr_mem_client_request_get
  input  EN_hart0_fpr_mem_client_request_get;
  output [69 : 0] hart0_fpr_mem_client_request_get;
  output RDY_hart0_fpr_mem_client_request_get;

  // action method hart0_fpr_mem_client_response_put
  input  [64 : 0] hart0_fpr_mem_client_response_put;
  input  EN_hart0_fpr_mem_client_response_put;
  output RDY_hart0_fpr_mem_client_response_put;

  // actionvalue method hart0_csr_mem_client_request_get
  input  EN_hart0_csr_mem_client_request_get;
  output [76 : 0] hart0_csr_mem_client_request_get;
  output RDY_hart0_csr_mem_client_request_get;

  // action method hart0_csr_mem_client_response_put
  input  [64 : 0] hart0_csr_mem_client_response_put;
  input  EN_hart0_csr_mem_client_response_put;
  output RDY_hart0_csr_mem_client_response_put;

  // signals for module outputs
  reg [31 : 0] av_read;
  wire [76 : 0] hart0_csr_mem_client_request_get;
  wire [69 : 0] hart0_fpr_mem_client_request_get,
		hart0_gpr_mem_client_request_get;
  wire RDY_av_read,
       RDY_hart0_csr_mem_client_request_get,
       RDY_hart0_csr_mem_client_response_put,
       RDY_hart0_fpr_mem_client_request_get,
       RDY_hart0_fpr_mem_client_response_put,
       RDY_hart0_gpr_mem_client_request_get,
       RDY_hart0_gpr_mem_client_response_put,
       RDY_reset,
       RDY_write;

  // register rg_abstractcs_busy
  reg rg_abstractcs_busy;
  reg rg_abstractcs_busy$D_IN;
  wire rg_abstractcs_busy$EN;

  // register rg_abstractcs_cmderr
  reg [2 : 0] rg_abstractcs_cmderr;
  reg [2 : 0] rg_abstractcs_cmderr$D_IN;
  wire rg_abstractcs_cmderr$EN;

  // register rg_command_access_reg_regno
  reg [12 : 0] rg_command_access_reg_regno;
  wire [12 : 0] rg_command_access_reg_regno$D_IN;
  wire rg_command_access_reg_regno$EN;

  // register rg_command_access_reg_write
  reg rg_command_access_reg_write;
  wire rg_command_access_reg_write$D_IN, rg_command_access_reg_write$EN;

  // register rg_data0
  reg [31 : 0] rg_data0;
  reg [31 : 0] rg_data0$D_IN;
  wire rg_data0$EN;

  // register rg_data1
  reg [31 : 0] rg_data1;
  reg [31 : 0] rg_data1$D_IN;
  wire rg_data1$EN;

  // register rg_start_reg_access
  reg rg_start_reg_access;
  reg rg_start_reg_access$D_IN;
  wire rg_start_reg_access$EN;

  // ports of submodule f_hart0_csr_reqs
  wire [76 : 0] f_hart0_csr_reqs$D_IN, f_hart0_csr_reqs$D_OUT;
  wire f_hart0_csr_reqs$CLR,
       f_hart0_csr_reqs$DEQ,
       f_hart0_csr_reqs$EMPTY_N,
       f_hart0_csr_reqs$ENQ,
       f_hart0_csr_reqs$FULL_N;

  // ports of submodule f_hart0_csr_rsps
  wire [64 : 0] f_hart0_csr_rsps$D_IN, f_hart0_csr_rsps$D_OUT;
  wire f_hart0_csr_rsps$CLR,
       f_hart0_csr_rsps$DEQ,
       f_hart0_csr_rsps$EMPTY_N,
       f_hart0_csr_rsps$ENQ,
       f_hart0_csr_rsps$FULL_N;

  // ports of submodule f_hart0_fpr_reqs
  wire [69 : 0] f_hart0_fpr_reqs$D_IN, f_hart0_fpr_reqs$D_OUT;
  wire f_hart0_fpr_reqs$CLR,
       f_hart0_fpr_reqs$DEQ,
       f_hart0_fpr_reqs$EMPTY_N,
       f_hart0_fpr_reqs$ENQ,
       f_hart0_fpr_reqs$FULL_N;

  // ports of submodule f_hart0_fpr_rsps
  wire [64 : 0] f_hart0_fpr_rsps$D_IN, f_hart0_fpr_rsps$D_OUT;
  wire f_hart0_fpr_rsps$CLR,
       f_hart0_fpr_rsps$DEQ,
       f_hart0_fpr_rsps$EMPTY_N,
       f_hart0_fpr_rsps$ENQ,
       f_hart0_fpr_rsps$FULL_N;

  // ports of submodule f_hart0_gpr_reqs
  wire [69 : 0] f_hart0_gpr_reqs$D_IN, f_hart0_gpr_reqs$D_OUT;
  wire f_hart0_gpr_reqs$CLR,
       f_hart0_gpr_reqs$DEQ,
       f_hart0_gpr_reqs$EMPTY_N,
       f_hart0_gpr_reqs$ENQ,
       f_hart0_gpr_reqs$FULL_N;

  // ports of submodule f_hart0_gpr_rsps
  wire [64 : 0] f_hart0_gpr_rsps$D_IN, f_hart0_gpr_rsps$D_OUT;
  wire f_hart0_gpr_rsps$CLR,
       f_hart0_gpr_rsps$DEQ,
       f_hart0_gpr_rsps$EMPTY_N,
       f_hart0_gpr_rsps$ENQ,
       f_hart0_gpr_rsps$FULL_N;

  // rule scheduling signals
  wire CAN_FIRE_RL_rl_csr_read_finish,
       CAN_FIRE_RL_rl_csr_read_start,
       CAN_FIRE_RL_rl_csr_write_finish,
       CAN_FIRE_RL_rl_csr_write_start,
       CAN_FIRE_RL_rl_fpr_read_finish,
       CAN_FIRE_RL_rl_fpr_read_start,
       CAN_FIRE_RL_rl_fpr_write_finish,
       CAN_FIRE_RL_rl_fpr_write_start,
       CAN_FIRE_RL_rl_gpr_read_finish,
       CAN_FIRE_RL_rl_gpr_read_start,
       CAN_FIRE_RL_rl_gpr_write_finish,
       CAN_FIRE_RL_rl_gpr_write_start,
       CAN_FIRE_RL_rl_unknown_read_start,
       CAN_FIRE_RL_rl_unknown_write_start,
       CAN_FIRE_av_read,
       CAN_FIRE_hart0_csr_mem_client_request_get,
       CAN_FIRE_hart0_csr_mem_client_response_put,
       CAN_FIRE_hart0_fpr_mem_client_request_get,
       CAN_FIRE_hart0_fpr_mem_client_response_put,
       CAN_FIRE_hart0_gpr_mem_client_request_get,
       CAN_FIRE_hart0_gpr_mem_client_response_put,
       CAN_FIRE_reset,
       CAN_FIRE_write,
       WILL_FIRE_RL_rl_csr_read_finish,
       WILL_FIRE_RL_rl_csr_read_start,
       WILL_FIRE_RL_rl_csr_write_finish,
       WILL_FIRE_RL_rl_csr_write_start,
       WILL_FIRE_RL_rl_fpr_read_finish,
       WILL_FIRE_RL_rl_fpr_read_start,
       WILL_FIRE_RL_rl_fpr_write_finish,
       WILL_FIRE_RL_rl_fpr_write_start,
       WILL_FIRE_RL_rl_gpr_read_finish,
       WILL_FIRE_RL_rl_gpr_read_start,
       WILL_FIRE_RL_rl_gpr_write_finish,
       WILL_FIRE_RL_rl_gpr_write_start,
       WILL_FIRE_RL_rl_unknown_read_start,
       WILL_FIRE_RL_rl_unknown_write_start,
       WILL_FIRE_av_read,
       WILL_FIRE_hart0_csr_mem_client_request_get,
       WILL_FIRE_hart0_csr_mem_client_response_put,
       WILL_FIRE_hart0_fpr_mem_client_request_get,
       WILL_FIRE_hart0_fpr_mem_client_response_put,
       WILL_FIRE_hart0_gpr_mem_client_request_get,
       WILL_FIRE_hart0_gpr_mem_client_response_put,
       WILL_FIRE_reset,
       WILL_FIRE_write;

  // inputs to muxes for submodule ports
  reg [2 : 0] MUX_rg_abstractcs_cmderr$write_1__VAL_5;
  wire [76 : 0] MUX_f_hart0_csr_reqs$enq_1__VAL_1,
		MUX_f_hart0_csr_reqs$enq_1__VAL_2;
  wire [69 : 0] MUX_f_hart0_fpr_reqs$enq_1__VAL_1,
		MUX_f_hart0_fpr_reqs$enq_1__VAL_2,
		MUX_f_hart0_gpr_reqs$enq_1__VAL_1,
		MUX_f_hart0_gpr_reqs$enq_1__VAL_2;
  wire [2 : 0] MUX_rg_abstractcs_cmderr$write_1__VAL_4,
	       MUX_rg_abstractcs_cmderr$write_1__VAL_7,
	       MUX_rg_abstractcs_cmderr$write_1__VAL_9;
  wire MUX_rg_abstractcs_busy$write_1__SEL_5,
       MUX_rg_abstractcs_cmderr$write_1__SEL_5,
       MUX_rg_data0$write_1__SEL_3,
       MUX_rg_data1$write_1__SEL_3;

  // declarations used by system tasks
  // synopsys translate_off
  reg [31 : 0] v__h2853;
  reg [31 : 0] v__h3092;
  reg [31 : 0] v__h3217;
  reg [31 : 0] v__h3544;
  reg [31 : 0] v__h3661;
  reg [31 : 0] v__h3374;
  reg [31 : 0] v__h4152;
  reg [31 : 0] v__h2847;
  reg [31 : 0] v__h3086;
  reg [31 : 0] v__h3211;
  reg [31 : 0] v__h3368;
  reg [31 : 0] v__h3538;
  reg [31 : 0] v__h3655;
  reg [31 : 0] v__h4146;
  // synopsys translate_on

  // remaining internal signals
  wire [63 : 0] req_data__h896;
  wire [31 : 0] virt_rg_abstractcs__h742, virt_rg_command__h806;
  wire [15 : 0] regno__h2677;
  wire [12 : 0] x__h1357, x__h1782;
  wire rg_abstractcs_busy_AND_rg_start_reg_access_AND_ETC___d38,
       rg_abstractcs_busy_AND_rg_start_reg_access_AND_ETC___d49,
       rg_abstractcs_busy_AND_rg_start_reg_access_AND_ETC___d61,
       rg_abstractcs_busy_AND_rg_start_reg_access_AND_ETC___d72,
       rg_abstractcs_cmderr_1_EQ_0_07_AND_write_dm_ad_ETC___d142,
       rg_abstractcs_cmderr_1_EQ_0_07_AND_write_dm_ad_ETC___d174,
       rg_command_access_reg_regno_ULE_0x101F___d36,
       rg_command_access_reg_regno_ULE_0x103F___d59,
       rg_command_access_reg_regno_ULE_0xFFF___d8,
       rg_command_access_reg_regno_ULT_0x1000___d34,
       rg_command_access_reg_regno_ULT_0x1020___d57,
       write_dm_addr_EQ_0x16_00_AND_rg_abstractcs_bus_ETC___d117,
       write_dm_addr_EQ_0x17_08_AND_NOT_rg_abstractcs_ETC___d149,
       write_dm_addr_EQ_0x17_08_AND_NOT_rg_abstractcs_ETC___d158,
       write_dm_addr_EQ_0x17_08_AND_NOT_rg_abstractcs_ETC___d167,
       write_dm_addr_EQ_0x17_08_AND_NOT_rg_abstractcs_ETC___d221;

  // action method reset
  assign RDY_reset = 1'd1 ;
  assign CAN_FIRE_reset = 1'd1 ;
  assign WILL_FIRE_reset = EN_reset ;

  // actionvalue method av_read
  always@(av_read_dm_addr or
	  rg_data1 or
	  rg_data0 or virt_rg_abstractcs__h742 or virt_rg_command__h806)
  begin
    case (av_read_dm_addr)
      7'h04: av_read = rg_data0;
      7'h16: av_read = virt_rg_abstractcs__h742;
      7'h17: av_read = virt_rg_command__h806;
      default: av_read = rg_data1;
    endcase
  end
  assign RDY_av_read = 1'd1 ;
  assign CAN_FIRE_av_read = 1'd1 ;
  assign WILL_FIRE_av_read = EN_av_read ;

  // action method write
  assign RDY_write = 1'd1 ;
  assign CAN_FIRE_write = 1'd1 ;
  assign WILL_FIRE_write = EN_write ;

  // actionvalue method hart0_gpr_mem_client_request_get
  assign hart0_gpr_mem_client_request_get = f_hart0_gpr_reqs$D_OUT ;
  assign RDY_hart0_gpr_mem_client_request_get = f_hart0_gpr_reqs$EMPTY_N ;
  assign CAN_FIRE_hart0_gpr_mem_client_request_get =
	     f_hart0_gpr_reqs$EMPTY_N ;
  assign WILL_FIRE_hart0_gpr_mem_client_request_get =
	     EN_hart0_gpr_mem_client_request_get ;

  // action method hart0_gpr_mem_client_response_put
  assign RDY_hart0_gpr_mem_client_response_put = f_hart0_gpr_rsps$FULL_N ;
  assign CAN_FIRE_hart0_gpr_mem_client_response_put =
	     f_hart0_gpr_rsps$FULL_N ;
  assign WILL_FIRE_hart0_gpr_mem_client_response_put =
	     EN_hart0_gpr_mem_client_response_put ;

  // actionvalue method hart0_fpr_mem_client_request_get
  assign hart0_fpr_mem_client_request_get = f_hart0_fpr_reqs$D_OUT ;
  assign RDY_hart0_fpr_mem_client_request_get = f_hart0_fpr_reqs$EMPTY_N ;
  assign CAN_FIRE_hart0_fpr_mem_client_request_get =
	     f_hart0_fpr_reqs$EMPTY_N ;
  assign WILL_FIRE_hart0_fpr_mem_client_request_get =
	     EN_hart0_fpr_mem_client_request_get ;

  // action method hart0_fpr_mem_client_response_put
  assign RDY_hart0_fpr_mem_client_response_put = f_hart0_fpr_rsps$FULL_N ;
  assign CAN_FIRE_hart0_fpr_mem_client_response_put =
	     f_hart0_fpr_rsps$FULL_N ;
  assign WILL_FIRE_hart0_fpr_mem_client_response_put =
	     EN_hart0_fpr_mem_client_response_put ;

  // actionvalue method hart0_csr_mem_client_request_get
  assign hart0_csr_mem_client_request_get = f_hart0_csr_reqs$D_OUT ;
  assign RDY_hart0_csr_mem_client_request_get = f_hart0_csr_reqs$EMPTY_N ;
  assign CAN_FIRE_hart0_csr_mem_client_request_get =
	     f_hart0_csr_reqs$EMPTY_N ;
  assign WILL_FIRE_hart0_csr_mem_client_request_get =
	     EN_hart0_csr_mem_client_request_get ;

  // action method hart0_csr_mem_client_response_put
  assign RDY_hart0_csr_mem_client_response_put = f_hart0_csr_rsps$FULL_N ;
  assign CAN_FIRE_hart0_csr_mem_client_response_put =
	     f_hart0_csr_rsps$FULL_N ;
  assign WILL_FIRE_hart0_csr_mem_client_response_put =
	     EN_hart0_csr_mem_client_response_put ;

  // submodule f_hart0_csr_reqs
  FIFO2 #(.width(32'd77), .guarded(32'd1)) f_hart0_csr_reqs(.RST(RST_N),
							    .CLK(CLK),
							    .D_IN(f_hart0_csr_reqs$D_IN),
							    .ENQ(f_hart0_csr_reqs$ENQ),
							    .DEQ(f_hart0_csr_reqs$DEQ),
							    .CLR(f_hart0_csr_reqs$CLR),
							    .D_OUT(f_hart0_csr_reqs$D_OUT),
							    .FULL_N(f_hart0_csr_reqs$FULL_N),
							    .EMPTY_N(f_hart0_csr_reqs$EMPTY_N));

  // submodule f_hart0_csr_rsps
  FIFO2 #(.width(32'd65), .guarded(32'd1)) f_hart0_csr_rsps(.RST(RST_N),
							    .CLK(CLK),
							    .D_IN(f_hart0_csr_rsps$D_IN),
							    .ENQ(f_hart0_csr_rsps$ENQ),
							    .DEQ(f_hart0_csr_rsps$DEQ),
							    .CLR(f_hart0_csr_rsps$CLR),
							    .D_OUT(f_hart0_csr_rsps$D_OUT),
							    .FULL_N(f_hart0_csr_rsps$FULL_N),
							    .EMPTY_N(f_hart0_csr_rsps$EMPTY_N));

  // submodule f_hart0_fpr_reqs
  FIFO2 #(.width(32'd70), .guarded(32'd1)) f_hart0_fpr_reqs(.RST(RST_N),
							    .CLK(CLK),
							    .D_IN(f_hart0_fpr_reqs$D_IN),
							    .ENQ(f_hart0_fpr_reqs$ENQ),
							    .DEQ(f_hart0_fpr_reqs$DEQ),
							    .CLR(f_hart0_fpr_reqs$CLR),
							    .D_OUT(f_hart0_fpr_reqs$D_OUT),
							    .FULL_N(f_hart0_fpr_reqs$FULL_N),
							    .EMPTY_N(f_hart0_fpr_reqs$EMPTY_N));

  // submodule f_hart0_fpr_rsps
  FIFO2 #(.width(32'd65), .guarded(32'd1)) f_hart0_fpr_rsps(.RST(RST_N),
							    .CLK(CLK),
							    .D_IN(f_hart0_fpr_rsps$D_IN),
							    .ENQ(f_hart0_fpr_rsps$ENQ),
							    .DEQ(f_hart0_fpr_rsps$DEQ),
							    .CLR(f_hart0_fpr_rsps$CLR),
							    .D_OUT(f_hart0_fpr_rsps$D_OUT),
							    .FULL_N(f_hart0_fpr_rsps$FULL_N),
							    .EMPTY_N(f_hart0_fpr_rsps$EMPTY_N));

  // submodule f_hart0_gpr_reqs
  FIFO2 #(.width(32'd70), .guarded(32'd1)) f_hart0_gpr_reqs(.RST(RST_N),
							    .CLK(CLK),
							    .D_IN(f_hart0_gpr_reqs$D_IN),
							    .ENQ(f_hart0_gpr_reqs$ENQ),
							    .DEQ(f_hart0_gpr_reqs$DEQ),
							    .CLR(f_hart0_gpr_reqs$CLR),
							    .D_OUT(f_hart0_gpr_reqs$D_OUT),
							    .FULL_N(f_hart0_gpr_reqs$FULL_N),
							    .EMPTY_N(f_hart0_gpr_reqs$EMPTY_N));

  // submodule f_hart0_gpr_rsps
  FIFO2 #(.width(32'd65), .guarded(32'd1)) f_hart0_gpr_rsps(.RST(RST_N),
							    .CLK(CLK),
							    .D_IN(f_hart0_gpr_rsps$D_IN),
							    .ENQ(f_hart0_gpr_rsps$ENQ),
							    .DEQ(f_hart0_gpr_rsps$DEQ),
							    .CLR(f_hart0_gpr_rsps$CLR),
							    .D_OUT(f_hart0_gpr_rsps$D_OUT),
							    .FULL_N(f_hart0_gpr_rsps$FULL_N),
							    .EMPTY_N(f_hart0_gpr_rsps$EMPTY_N));

  // rule RL_rl_csr_write_start
  assign CAN_FIRE_RL_rl_csr_write_start =
	     f_hart0_csr_reqs$FULL_N && rg_abstractcs_busy &&
	     rg_start_reg_access &&
	     rg_command_access_reg_write &&
	     rg_command_access_reg_regno_ULE_0xFFF___d8 ;
  assign WILL_FIRE_RL_rl_csr_write_start = CAN_FIRE_RL_rl_csr_write_start ;

  // rule RL_rl_csr_write_finish
  assign CAN_FIRE_RL_rl_csr_write_finish =
	     f_hart0_csr_rsps$EMPTY_N && rg_abstractcs_busy &&
	     rg_command_access_reg_write &&
	     rg_command_access_reg_regno_ULE_0xFFF___d8 ;
  assign WILL_FIRE_RL_rl_csr_write_finish =
	     CAN_FIRE_RL_rl_csr_write_finish && !EN_write ;

  // rule RL_rl_csr_read_start
  assign CAN_FIRE_RL_rl_csr_read_start =
	     f_hart0_csr_reqs$FULL_N && rg_abstractcs_busy &&
	     rg_start_reg_access &&
	     !rg_command_access_reg_write &&
	     rg_command_access_reg_regno_ULE_0xFFF___d8 ;
  assign WILL_FIRE_RL_rl_csr_read_start = CAN_FIRE_RL_rl_csr_read_start ;

  // rule RL_rl_csr_read_finish
  assign CAN_FIRE_RL_rl_csr_read_finish =
	     f_hart0_csr_rsps$EMPTY_N && rg_abstractcs_busy &&
	     !rg_command_access_reg_write &&
	     rg_command_access_reg_regno_ULE_0xFFF___d8 ;
  assign WILL_FIRE_RL_rl_csr_read_finish =
	     CAN_FIRE_RL_rl_csr_read_finish && !EN_write ;

  // rule RL_rl_gpr_write_start
  assign CAN_FIRE_RL_rl_gpr_write_start =
	     f_hart0_gpr_reqs$FULL_N &&
	     rg_abstractcs_busy_AND_rg_start_reg_access_AND_ETC___d38 ;
  assign WILL_FIRE_RL_rl_gpr_write_start = CAN_FIRE_RL_rl_gpr_write_start ;

  // rule RL_rl_gpr_write_finish
  assign CAN_FIRE_RL_rl_gpr_write_finish =
	     f_hart0_gpr_rsps$EMPTY_N && rg_abstractcs_busy &&
	     rg_command_access_reg_write &&
	     !rg_command_access_reg_regno_ULT_0x1000___d34 &&
	     rg_command_access_reg_regno_ULE_0x101F___d36 ;
  assign WILL_FIRE_RL_rl_gpr_write_finish =
	     CAN_FIRE_RL_rl_gpr_write_finish && !EN_write ;

  // rule RL_rl_gpr_read_start
  assign CAN_FIRE_RL_rl_gpr_read_start =
	     f_hart0_gpr_reqs$FULL_N &&
	     rg_abstractcs_busy_AND_rg_start_reg_access_AND_ETC___d49 ;
  assign WILL_FIRE_RL_rl_gpr_read_start = CAN_FIRE_RL_rl_gpr_read_start ;

  // rule RL_rl_gpr_read_finish
  assign CAN_FIRE_RL_rl_gpr_read_finish =
	     f_hart0_gpr_rsps$EMPTY_N && rg_abstractcs_busy &&
	     !rg_command_access_reg_write &&
	     !rg_command_access_reg_regno_ULT_0x1000___d34 &&
	     rg_command_access_reg_regno_ULE_0x101F___d36 ;
  assign WILL_FIRE_RL_rl_gpr_read_finish =
	     CAN_FIRE_RL_rl_gpr_read_finish && !EN_write ;

  // rule RL_rl_fpr_write_start
  assign CAN_FIRE_RL_rl_fpr_write_start =
	     f_hart0_fpr_reqs$FULL_N &&
	     rg_abstractcs_busy_AND_rg_start_reg_access_AND_ETC___d61 ;
  assign WILL_FIRE_RL_rl_fpr_write_start = CAN_FIRE_RL_rl_fpr_write_start ;

  // rule RL_rl_fpr_write_finish
  assign CAN_FIRE_RL_rl_fpr_write_finish =
	     f_hart0_fpr_rsps$EMPTY_N && rg_abstractcs_busy &&
	     rg_command_access_reg_write &&
	     !rg_command_access_reg_regno_ULT_0x1020___d57 &&
	     rg_command_access_reg_regno_ULE_0x103F___d59 ;
  assign WILL_FIRE_RL_rl_fpr_write_finish =
	     CAN_FIRE_RL_rl_fpr_write_finish && !EN_write ;

  // rule RL_rl_fpr_read_start
  assign CAN_FIRE_RL_rl_fpr_read_start =
	     f_hart0_fpr_reqs$FULL_N &&
	     rg_abstractcs_busy_AND_rg_start_reg_access_AND_ETC___d72 ;
  assign WILL_FIRE_RL_rl_fpr_read_start = CAN_FIRE_RL_rl_fpr_read_start ;

  // rule RL_rl_fpr_read_finish
  assign CAN_FIRE_RL_rl_fpr_read_finish =
	     f_hart0_fpr_rsps$EMPTY_N && rg_abstractcs_busy &&
	     !rg_command_access_reg_write &&
	     !rg_command_access_reg_regno_ULT_0x1020___d57 &&
	     rg_command_access_reg_regno_ULE_0x103F___d59 ;
  assign WILL_FIRE_RL_rl_fpr_read_finish =
	     CAN_FIRE_RL_rl_fpr_read_finish && !EN_write ;

  // rule RL_rl_unknown_write_start
  assign CAN_FIRE_RL_rl_unknown_write_start =
	     rg_abstractcs_busy && rg_start_reg_access &&
	     rg_command_access_reg_write &&
	     !rg_command_access_reg_regno_ULE_0xFFF___d8 &&
	     (rg_command_access_reg_regno_ULT_0x1000___d34 ||
	      !rg_command_access_reg_regno_ULE_0x101F___d36) &&
	     (rg_command_access_reg_regno_ULT_0x1020___d57 ||
	      !rg_command_access_reg_regno_ULE_0x103F___d59) ;
  assign WILL_FIRE_RL_rl_unknown_write_start =
	     CAN_FIRE_RL_rl_unknown_write_start && !EN_write ;

  // rule RL_rl_unknown_read_start
  assign CAN_FIRE_RL_rl_unknown_read_start =
	     rg_abstractcs_busy && rg_start_reg_access &&
	     !rg_command_access_reg_write &&
	     !rg_command_access_reg_regno_ULE_0xFFF___d8 &&
	     (rg_command_access_reg_regno_ULT_0x1000___d34 ||
	      !rg_command_access_reg_regno_ULE_0x101F___d36) &&
	     (rg_command_access_reg_regno_ULT_0x1020___d57 ||
	      !rg_command_access_reg_regno_ULE_0x103F___d59) ;
  assign WILL_FIRE_RL_rl_unknown_read_start =
	     CAN_FIRE_RL_rl_unknown_read_start && !EN_write ;

  // inputs to muxes for submodule ports
  assign MUX_rg_abstractcs_busy$write_1__SEL_5 =
	     EN_write && rg_abstractcs_cmderr == 3'd0 &&
	     write_dm_addr_EQ_0x17_08_AND_NOT_rg_abstractcs_ETC___d158 ;
  assign MUX_rg_abstractcs_cmderr$write_1__SEL_5 =
	     EN_write &&
	     write_dm_addr_EQ_0x16_00_AND_rg_abstractcs_bus_ETC___d117 ;
  assign MUX_rg_data0$write_1__SEL_3 =
	     EN_write && rg_abstractcs_cmderr == 3'd0 &&
	     write_dm_addr == 7'h04 ;
  assign MUX_rg_data1$write_1__SEL_3 =
	     EN_write && rg_abstractcs_cmderr == 3'd0 &&
	     write_dm_addr == 7'h05 ;
  assign MUX_f_hart0_csr_reqs$enq_1__VAL_1 =
	     { 1'd1, rg_command_access_reg_regno[11:0], req_data__h896 } ;
  assign MUX_f_hart0_csr_reqs$enq_1__VAL_2 =
	     { 1'd0,
	       rg_command_access_reg_regno[11:0],
	       64'hAAAAAAAAAAAAAAAA } ;
  assign MUX_f_hart0_fpr_reqs$enq_1__VAL_1 =
	     { 1'd1, x__h1782[4:0], req_data__h896 } ;
  assign MUX_f_hart0_fpr_reqs$enq_1__VAL_2 =
	     { 1'd0, x__h1782[4:0], 64'hAAAAAAAAAAAAAAAA } ;
  assign MUX_f_hart0_gpr_reqs$enq_1__VAL_1 =
	     { 1'd1, x__h1357[4:0], req_data__h896 } ;
  assign MUX_f_hart0_gpr_reqs$enq_1__VAL_2 =
	     { 1'd0, x__h1357[4:0], 64'hAAAAAAAAAAAAAAAA } ;
  assign MUX_rg_abstractcs_cmderr$write_1__VAL_4 =
	     f_hart0_fpr_rsps$D_OUT[64] ? 3'd0 : 3'd4 ;
  always@(write_dm_addr or rg_abstractcs_busy or write_dm_word)
  begin
    case (write_dm_addr)
      7'h16:
	  MUX_rg_abstractcs_cmderr$write_1__VAL_5 =
	      rg_abstractcs_busy ? 3'd1 : 3'd0;
      7'h17:
	  MUX_rg_abstractcs_cmderr$write_1__VAL_5 =
	      rg_abstractcs_busy ?
		3'd1 :
		((write_dm_word[24] || write_dm_word[22:20] != 3'd3 ||
		  write_dm_word[18]) ?
		   3'd2 :
		   (write_dm_word[17] ? 3'd0 : 3'd2));
      default: MUX_rg_abstractcs_cmderr$write_1__VAL_5 = 3'd2;
    endcase
  end
  assign MUX_rg_abstractcs_cmderr$write_1__VAL_7 =
	     f_hart0_gpr_rsps$D_OUT[64] ? 3'd0 : 3'd4 ;
  assign MUX_rg_abstractcs_cmderr$write_1__VAL_9 =
	     f_hart0_csr_rsps$D_OUT[64] ? 3'd0 : 3'd4 ;

  // register rg_abstractcs_busy
  always@(EN_reset or
	  WILL_FIRE_RL_rl_unknown_read_start or
	  WILL_FIRE_RL_rl_unknown_write_start or
	  WILL_FIRE_RL_rl_fpr_read_finish or
	  MUX_rg_abstractcs_busy$write_1__SEL_5 or
	  WILL_FIRE_RL_rl_fpr_write_finish or
	  WILL_FIRE_RL_rl_gpr_read_finish or
	  WILL_FIRE_RL_rl_gpr_write_finish or
	  WILL_FIRE_RL_rl_csr_read_finish or WILL_FIRE_RL_rl_csr_write_finish)
  case (1'b1)
    EN_reset || WILL_FIRE_RL_rl_unknown_read_start ||
    WILL_FIRE_RL_rl_unknown_write_start ||
    WILL_FIRE_RL_rl_fpr_read_finish:
	rg_abstractcs_busy$D_IN = 1'd0;
    MUX_rg_abstractcs_busy$write_1__SEL_5: rg_abstractcs_busy$D_IN = 1'd1;
    WILL_FIRE_RL_rl_fpr_write_finish || WILL_FIRE_RL_rl_gpr_read_finish ||
    WILL_FIRE_RL_rl_gpr_write_finish ||
    WILL_FIRE_RL_rl_csr_read_finish ||
    WILL_FIRE_RL_rl_csr_write_finish:
	rg_abstractcs_busy$D_IN = 1'd0;
    default: rg_abstractcs_busy$D_IN = 1'b0 /* unspecified value */ ;
  endcase
  assign rg_abstractcs_busy$EN =
	     EN_write && rg_abstractcs_cmderr == 3'd0 &&
	     write_dm_addr_EQ_0x17_08_AND_NOT_rg_abstractcs_ETC___d158 ||
	     WILL_FIRE_RL_rl_unknown_read_start ||
	     WILL_FIRE_RL_rl_unknown_write_start ||
	     WILL_FIRE_RL_rl_fpr_read_finish ||
	     WILL_FIRE_RL_rl_fpr_write_finish ||
	     WILL_FIRE_RL_rl_gpr_read_finish ||
	     WILL_FIRE_RL_rl_gpr_write_finish ||
	     WILL_FIRE_RL_rl_csr_read_finish ||
	     WILL_FIRE_RL_rl_csr_write_finish ||
	     EN_reset ;

  // register rg_abstractcs_cmderr
  always@(EN_reset or
	  WILL_FIRE_RL_rl_unknown_read_start or
	  WILL_FIRE_RL_rl_unknown_write_start or
	  WILL_FIRE_RL_rl_fpr_read_finish or
	  MUX_rg_abstractcs_cmderr$write_1__VAL_4 or
	  MUX_rg_abstractcs_cmderr$write_1__SEL_5 or
	  MUX_rg_abstractcs_cmderr$write_1__VAL_5 or
	  WILL_FIRE_RL_rl_fpr_write_finish or
	  WILL_FIRE_RL_rl_gpr_read_finish or
	  MUX_rg_abstractcs_cmderr$write_1__VAL_7 or
	  WILL_FIRE_RL_rl_gpr_write_finish or
	  WILL_FIRE_RL_rl_csr_read_finish or
	  MUX_rg_abstractcs_cmderr$write_1__VAL_9 or
	  WILL_FIRE_RL_rl_csr_write_finish)
  case (1'b1)
    EN_reset: rg_abstractcs_cmderr$D_IN = 3'd0;
    WILL_FIRE_RL_rl_unknown_read_start || WILL_FIRE_RL_rl_unknown_write_start:
	rg_abstractcs_cmderr$D_IN = 3'd7;
    WILL_FIRE_RL_rl_fpr_read_finish:
	rg_abstractcs_cmderr$D_IN = MUX_rg_abstractcs_cmderr$write_1__VAL_4;
    MUX_rg_abstractcs_cmderr$write_1__SEL_5:
	rg_abstractcs_cmderr$D_IN = MUX_rg_abstractcs_cmderr$write_1__VAL_5;
    WILL_FIRE_RL_rl_fpr_write_finish:
	rg_abstractcs_cmderr$D_IN = MUX_rg_abstractcs_cmderr$write_1__VAL_4;
    WILL_FIRE_RL_rl_gpr_read_finish:
	rg_abstractcs_cmderr$D_IN = MUX_rg_abstractcs_cmderr$write_1__VAL_7;
    WILL_FIRE_RL_rl_gpr_write_finish:
	rg_abstractcs_cmderr$D_IN = MUX_rg_abstractcs_cmderr$write_1__VAL_7;
    WILL_FIRE_RL_rl_csr_read_finish:
	rg_abstractcs_cmderr$D_IN = MUX_rg_abstractcs_cmderr$write_1__VAL_9;
    WILL_FIRE_RL_rl_csr_write_finish:
	rg_abstractcs_cmderr$D_IN = MUX_rg_abstractcs_cmderr$write_1__VAL_9;
    default: rg_abstractcs_cmderr$D_IN = 3'b010 /* unspecified value */ ;
  endcase
  assign rg_abstractcs_cmderr$EN =
	     EN_write &&
	     write_dm_addr_EQ_0x16_00_AND_rg_abstractcs_bus_ETC___d117 ||
	     WILL_FIRE_RL_rl_csr_read_finish ||
	     WILL_FIRE_RL_rl_csr_write_finish ||
	     WILL_FIRE_RL_rl_gpr_read_finish ||
	     WILL_FIRE_RL_rl_gpr_write_finish ||
	     WILL_FIRE_RL_rl_fpr_read_finish ||
	     WILL_FIRE_RL_rl_fpr_write_finish ||
	     EN_reset ||
	     WILL_FIRE_RL_rl_unknown_read_start ||
	     WILL_FIRE_RL_rl_unknown_write_start ;

  // register rg_command_access_reg_regno
  assign rg_command_access_reg_regno$D_IN =
	     EN_reset ? 13'h1000 : write_dm_word[12:0] ;
  assign rg_command_access_reg_regno$EN =
	     EN_write && rg_abstractcs_cmderr == 3'd0 &&
	     write_dm_addr_EQ_0x17_08_AND_NOT_rg_abstractcs_ETC___d158 ||
	     EN_reset ;

  // register rg_command_access_reg_write
  assign rg_command_access_reg_write$D_IN = !EN_reset && write_dm_word[16] ;
  assign rg_command_access_reg_write$EN =
	     EN_write && rg_abstractcs_cmderr == 3'd0 &&
	     write_dm_addr_EQ_0x17_08_AND_NOT_rg_abstractcs_ETC___d158 ||
	     EN_reset ;

  // register rg_data0
  always@(EN_reset or
	  WILL_FIRE_RL_rl_fpr_read_finish or
	  f_hart0_fpr_rsps$D_OUT or
	  MUX_rg_data0$write_1__SEL_3 or
	  write_dm_word or
	  WILL_FIRE_RL_rl_gpr_read_finish or
	  f_hart0_gpr_rsps$D_OUT or
	  WILL_FIRE_RL_rl_csr_read_finish or f_hart0_csr_rsps$D_OUT)
  case (1'b1)
    EN_reset: rg_data0$D_IN = 32'd0;
    WILL_FIRE_RL_rl_fpr_read_finish:
	rg_data0$D_IN = f_hart0_fpr_rsps$D_OUT[31:0];
    MUX_rg_data0$write_1__SEL_3: rg_data0$D_IN = write_dm_word;
    WILL_FIRE_RL_rl_gpr_read_finish:
	rg_data0$D_IN = f_hart0_gpr_rsps$D_OUT[31:0];
    WILL_FIRE_RL_rl_csr_read_finish:
	rg_data0$D_IN = f_hart0_csr_rsps$D_OUT[31:0];
    default: rg_data0$D_IN = 32'hAAAAAAAA /* unspecified value */ ;
  endcase
  assign rg_data0$EN =
	     EN_write && rg_abstractcs_cmderr == 3'd0 &&
	     write_dm_addr == 7'h04 ||
	     WILL_FIRE_RL_rl_csr_read_finish ||
	     WILL_FIRE_RL_rl_gpr_read_finish ||
	     WILL_FIRE_RL_rl_fpr_read_finish ||
	     EN_reset ;

  // register rg_data1
  always@(EN_reset or
	  WILL_FIRE_RL_rl_fpr_read_finish or
	  f_hart0_fpr_rsps$D_OUT or
	  MUX_rg_data1$write_1__SEL_3 or
	  write_dm_word or
	  WILL_FIRE_RL_rl_gpr_read_finish or
	  f_hart0_gpr_rsps$D_OUT or
	  WILL_FIRE_RL_rl_csr_read_finish or f_hart0_csr_rsps$D_OUT)
  case (1'b1)
    EN_reset: rg_data1$D_IN = 32'd0;
    WILL_FIRE_RL_rl_fpr_read_finish:
	rg_data1$D_IN = f_hart0_fpr_rsps$D_OUT[63:32];
    MUX_rg_data1$write_1__SEL_3: rg_data1$D_IN = write_dm_word;
    WILL_FIRE_RL_rl_gpr_read_finish:
	rg_data1$D_IN = f_hart0_gpr_rsps$D_OUT[63:32];
    WILL_FIRE_RL_rl_csr_read_finish:
	rg_data1$D_IN = f_hart0_csr_rsps$D_OUT[63:32];
    default: rg_data1$D_IN = 32'hAAAAAAAA /* unspecified value */ ;
  endcase
  assign rg_data1$EN =
	     EN_write && rg_abstractcs_cmderr == 3'd0 &&
	     write_dm_addr == 7'h05 ||
	     WILL_FIRE_RL_rl_csr_read_finish ||
	     WILL_FIRE_RL_rl_gpr_read_finish ||
	     WILL_FIRE_RL_rl_fpr_read_finish ||
	     EN_reset ;

  // register rg_start_reg_access
  always@(EN_reset or
	  WILL_FIRE_RL_rl_unknown_read_start or
	  WILL_FIRE_RL_rl_unknown_write_start or
	  MUX_rg_abstractcs_busy$write_1__SEL_5 or
	  WILL_FIRE_RL_rl_fpr_read_start or
	  WILL_FIRE_RL_rl_fpr_write_start or
	  WILL_FIRE_RL_rl_gpr_read_start or
	  WILL_FIRE_RL_rl_gpr_write_start or
	  WILL_FIRE_RL_rl_csr_read_start or WILL_FIRE_RL_rl_csr_write_start)
  case (1'b1)
    EN_reset || WILL_FIRE_RL_rl_unknown_read_start ||
    WILL_FIRE_RL_rl_unknown_write_start:
	rg_start_reg_access$D_IN = 1'd0;
    MUX_rg_abstractcs_busy$write_1__SEL_5: rg_start_reg_access$D_IN = 1'd1;
    WILL_FIRE_RL_rl_fpr_read_start || WILL_FIRE_RL_rl_fpr_write_start ||
    WILL_FIRE_RL_rl_gpr_read_start ||
    WILL_FIRE_RL_rl_gpr_write_start ||
    WILL_FIRE_RL_rl_csr_read_start ||
    WILL_FIRE_RL_rl_csr_write_start:
	rg_start_reg_access$D_IN = 1'd0;
    default: rg_start_reg_access$D_IN = 1'b0 /* unspecified value */ ;
  endcase
  assign rg_start_reg_access$EN =
	     EN_write && rg_abstractcs_cmderr == 3'd0 &&
	     write_dm_addr_EQ_0x17_08_AND_NOT_rg_abstractcs_ETC___d158 ||
	     WILL_FIRE_RL_rl_unknown_read_start ||
	     WILL_FIRE_RL_rl_unknown_write_start ||
	     WILL_FIRE_RL_rl_fpr_read_start ||
	     WILL_FIRE_RL_rl_fpr_write_start ||
	     WILL_FIRE_RL_rl_gpr_read_start ||
	     WILL_FIRE_RL_rl_gpr_write_start ||
	     WILL_FIRE_RL_rl_csr_read_start ||
	     WILL_FIRE_RL_rl_csr_write_start ||
	     EN_reset ;

  // submodule f_hart0_csr_reqs
  assign f_hart0_csr_reqs$D_IN =
	     WILL_FIRE_RL_rl_csr_write_start ?
	       MUX_f_hart0_csr_reqs$enq_1__VAL_1 :
	       MUX_f_hart0_csr_reqs$enq_1__VAL_2 ;
  assign f_hart0_csr_reqs$ENQ =
	     WILL_FIRE_RL_rl_csr_write_start ||
	     WILL_FIRE_RL_rl_csr_read_start ;
  assign f_hart0_csr_reqs$DEQ = EN_hart0_csr_mem_client_request_get ;
  assign f_hart0_csr_reqs$CLR = EN_reset ;

  // submodule f_hart0_csr_rsps
  assign f_hart0_csr_rsps$D_IN = hart0_csr_mem_client_response_put ;
  assign f_hart0_csr_rsps$ENQ = EN_hart0_csr_mem_client_response_put ;
  assign f_hart0_csr_rsps$DEQ =
	     WILL_FIRE_RL_rl_csr_read_finish ||
	     WILL_FIRE_RL_rl_csr_write_finish ;
  assign f_hart0_csr_rsps$CLR = EN_reset ;

  // submodule f_hart0_fpr_reqs
  assign f_hart0_fpr_reqs$D_IN =
	     WILL_FIRE_RL_rl_fpr_write_start ?
	       MUX_f_hart0_fpr_reqs$enq_1__VAL_1 :
	       MUX_f_hart0_fpr_reqs$enq_1__VAL_2 ;
  assign f_hart0_fpr_reqs$ENQ =
	     WILL_FIRE_RL_rl_fpr_write_start ||
	     WILL_FIRE_RL_rl_fpr_read_start ;
  assign f_hart0_fpr_reqs$DEQ = EN_hart0_fpr_mem_client_request_get ;
  assign f_hart0_fpr_reqs$CLR = 1'b0 ;

  // submodule f_hart0_fpr_rsps
  assign f_hart0_fpr_rsps$D_IN = hart0_fpr_mem_client_response_put ;
  assign f_hart0_fpr_rsps$ENQ = EN_hart0_fpr_mem_client_response_put ;
  assign f_hart0_fpr_rsps$DEQ =
	     WILL_FIRE_RL_rl_fpr_read_finish ||
	     WILL_FIRE_RL_rl_fpr_write_finish ;
  assign f_hart0_fpr_rsps$CLR = 1'b0 ;

  // submodule f_hart0_gpr_reqs
  assign f_hart0_gpr_reqs$D_IN =
	     WILL_FIRE_RL_rl_gpr_write_start ?
	       MUX_f_hart0_gpr_reqs$enq_1__VAL_1 :
	       MUX_f_hart0_gpr_reqs$enq_1__VAL_2 ;
  assign f_hart0_gpr_reqs$ENQ =
	     WILL_FIRE_RL_rl_gpr_write_start ||
	     WILL_FIRE_RL_rl_gpr_read_start ;
  assign f_hart0_gpr_reqs$DEQ = EN_hart0_gpr_mem_client_request_get ;
  assign f_hart0_gpr_reqs$CLR = EN_reset ;

  // submodule f_hart0_gpr_rsps
  assign f_hart0_gpr_rsps$D_IN = hart0_gpr_mem_client_response_put ;
  assign f_hart0_gpr_rsps$ENQ = EN_hart0_gpr_mem_client_response_put ;
  assign f_hart0_gpr_rsps$DEQ =
	     WILL_FIRE_RL_rl_gpr_read_finish ||
	     WILL_FIRE_RL_rl_gpr_write_finish ;
  assign f_hart0_gpr_rsps$CLR = EN_reset ;

  // remaining internal signals
  assign regno__h2677 = { 3'd0, rg_command_access_reg_regno } ;
  assign req_data__h896 = { rg_data1, rg_data0 } ;
  assign rg_abstractcs_busy_AND_rg_start_reg_access_AND_ETC___d38 =
	     rg_abstractcs_busy && rg_start_reg_access &&
	     rg_command_access_reg_write &&
	     !rg_command_access_reg_regno_ULT_0x1000___d34 &&
	     rg_command_access_reg_regno_ULE_0x101F___d36 ;
  assign rg_abstractcs_busy_AND_rg_start_reg_access_AND_ETC___d49 =
	     rg_abstractcs_busy && rg_start_reg_access &&
	     !rg_command_access_reg_write &&
	     !rg_command_access_reg_regno_ULT_0x1000___d34 &&
	     rg_command_access_reg_regno_ULE_0x101F___d36 ;
  assign rg_abstractcs_busy_AND_rg_start_reg_access_AND_ETC___d61 =
	     rg_abstractcs_busy && rg_start_reg_access &&
	     rg_command_access_reg_write &&
	     !rg_command_access_reg_regno_ULT_0x1020___d57 &&
	     rg_command_access_reg_regno_ULE_0x103F___d59 ;
  assign rg_abstractcs_busy_AND_rg_start_reg_access_AND_ETC___d72 =
	     rg_abstractcs_busy && rg_start_reg_access &&
	     !rg_command_access_reg_write &&
	     !rg_command_access_reg_regno_ULT_0x1020___d57 &&
	     rg_command_access_reg_regno_ULE_0x103F___d59 ;
  assign rg_abstractcs_cmderr_1_EQ_0_07_AND_write_dm_ad_ETC___d142 =
	     rg_abstractcs_cmderr == 3'd0 && write_dm_addr == 7'h17 &&
	     !rg_abstractcs_busy &&
	     write_dm_word[24] ;
  assign rg_abstractcs_cmderr_1_EQ_0_07_AND_write_dm_ad_ETC___d174 =
	     rg_abstractcs_cmderr == 3'd0 && write_dm_addr == 7'h17 &&
	     !rg_abstractcs_busy &&
	     !write_dm_word[24] &&
	     write_dm_word[22:20] != 3'd3 ;
  assign rg_command_access_reg_regno_ULE_0x101F___d36 =
	     rg_command_access_reg_regno <= 13'h101F ;
  assign rg_command_access_reg_regno_ULE_0x103F___d59 =
	     rg_command_access_reg_regno <= 13'h103F ;
  assign rg_command_access_reg_regno_ULE_0xFFF___d8 =
	     rg_command_access_reg_regno <= 13'h0FFF ;
  assign rg_command_access_reg_regno_ULT_0x1000___d34 =
	     rg_command_access_reg_regno < 13'h1000 ;
  assign rg_command_access_reg_regno_ULT_0x1020___d57 =
	     rg_command_access_reg_regno < 13'h1020 ;
  assign virt_rg_abstractcs__h742 =
	     { 19'd0, rg_abstractcs_busy, 1'b0, rg_abstractcs_cmderr, 8'd2 } ;
  assign virt_rg_command__h806 =
	     { 15'd17, rg_command_access_reg_write, regno__h2677 } ;
  assign write_dm_addr_EQ_0x16_00_AND_rg_abstractcs_bus_ETC___d117 =
	     write_dm_addr == 7'h16 &&
	     (rg_abstractcs_busy || write_dm_word[10:8] != 3'd0) ||
	     write_dm_addr != 7'h16 && rg_abstractcs_cmderr == 3'd0 &&
	     write_dm_addr != 7'h04 &&
	     write_dm_addr != 7'h05 ;
  assign write_dm_addr_EQ_0x17_08_AND_NOT_rg_abstractcs_ETC___d149 =
	     write_dm_addr == 7'h17 && !rg_abstractcs_busy &&
	     !write_dm_word[24] &&
	     write_dm_word[22:20] == 3'd3 &&
	     write_dm_word[18] ;
  assign write_dm_addr_EQ_0x17_08_AND_NOT_rg_abstractcs_ETC___d158 =
	     write_dm_addr == 7'h17 && !rg_abstractcs_busy &&
	     !write_dm_word[24] &&
	     write_dm_word[22:20] == 3'd3 &&
	     !write_dm_word[18] &&
	     write_dm_word[17] ;
  assign write_dm_addr_EQ_0x17_08_AND_NOT_rg_abstractcs_ETC___d167 =
	     write_dm_addr == 7'h17 && !rg_abstractcs_busy &&
	     !write_dm_word[24] &&
	     write_dm_word[22:20] == 3'd3 &&
	     !write_dm_word[18] &&
	     !write_dm_word[17] ;
  assign write_dm_addr_EQ_0x17_08_AND_NOT_rg_abstractcs_ETC___d221 =
	     write_dm_addr == 7'h17 && !rg_abstractcs_busy &&
	     !write_dm_word[24] &&
	     write_dm_word[22:20] != 3'd3 &&
	     write_dm_word[22:20] != 3'd0 &&
	     write_dm_word[22:20] != 3'd1 &&
	     write_dm_word[22:20] != 3'd2 &&
	     write_dm_word[22:20] != 3'd4 &&
	     write_dm_word[22:20] != 3'd5 &&
	     write_dm_word[22:20] != 3'd6 ;
  assign x__h1357 = rg_command_access_reg_regno - 13'h1000 ;
  assign x__h1782 = rg_command_access_reg_regno - 13'h1020 ;

  // handling of inlined registers

  always@(posedge CLK)
  begin
    if (RST_N == `BSV_RESET_VALUE)
      begin
        rg_start_reg_access <= `BSV_ASSIGNMENT_DELAY 1'd0;
      end
    else
      begin
        if (rg_start_reg_access$EN)
	  rg_start_reg_access <= `BSV_ASSIGNMENT_DELAY
	      rg_start_reg_access$D_IN;
      end
    if (rg_abstractcs_busy$EN)
      rg_abstractcs_busy <= `BSV_ASSIGNMENT_DELAY rg_abstractcs_busy$D_IN;
    if (rg_abstractcs_cmderr$EN)
      rg_abstractcs_cmderr <= `BSV_ASSIGNMENT_DELAY rg_abstractcs_cmderr$D_IN;
    if (rg_command_access_reg_regno$EN)
      rg_command_access_reg_regno <= `BSV_ASSIGNMENT_DELAY
	  rg_command_access_reg_regno$D_IN;
    if (rg_command_access_reg_write$EN)
      rg_command_access_reg_write <= `BSV_ASSIGNMENT_DELAY
	  rg_command_access_reg_write$D_IN;
    if (rg_data0$EN) rg_data0 <= `BSV_ASSIGNMENT_DELAY rg_data0$D_IN;
    if (rg_data1$EN) rg_data1 <= `BSV_ASSIGNMENT_DELAY rg_data1$D_IN;
  end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    rg_abstractcs_busy = 1'h0;
    rg_abstractcs_cmderr = 3'h2;
    rg_command_access_reg_regno = 13'h0AAA;
    rg_command_access_reg_write = 1'h0;
    rg_data0 = 32'hAAAAAAAA;
    rg_data1 = 32'hAAAAAAAA;
    rg_start_reg_access = 1'h0;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on

  // handling of system tasks

  // synopsys translate_off
  always@(negedge CLK)
  begin
    #0;
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && write_dm_addr == 7'h16 && rg_abstractcs_busy)
	begin
	  v__h2853 = $stime;
	  #0;
	end
    v__h2847 = v__h2853 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && write_dm_addr == 7'h16 && rg_abstractcs_busy)
	$display("%0d: DM_Abstract_Commands.write: [abstractcs] <= 0x%08h: ERROR",
		 v__h2847,
		 write_dm_word);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && write_dm_addr == 7'h16 && rg_abstractcs_busy)
	$display("    DM is busy with a previous abstract command");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && rg_abstractcs_cmderr == 3'd0 &&
	  write_dm_addr == 7'h17 &&
	  rg_abstractcs_busy)
	begin
	  v__h3092 = $stime;
	  #0;
	end
    v__h3086 = v__h3092 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && rg_abstractcs_cmderr == 3'd0 &&
	  write_dm_addr == 7'h17 &&
	  rg_abstractcs_busy)
	$display("%0d: DM_Abstract_Commands.write: [command] <= 0x%08h: ERROR",
		 v__h3086,
		 write_dm_word);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && rg_abstractcs_cmderr == 3'd0 &&
	  write_dm_addr == 7'h17 &&
	  rg_abstractcs_busy)
	$display("    DM is busy with a previous abstract command");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write &&
	  rg_abstractcs_cmderr_1_EQ_0_07_AND_write_dm_ad_ETC___d142)
	begin
	  v__h3217 = $stime;
	  #0;
	end
    v__h3211 = v__h3217 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write &&
	  rg_abstractcs_cmderr_1_EQ_0_07_AND_write_dm_ad_ETC___d142)
	$display("%0d: DM_Abstract_Commands.write: [command] <= 0x%08h: ERROR",
		 v__h3211,
		 write_dm_word);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write &&
	  rg_abstractcs_cmderr_1_EQ_0_07_AND_write_dm_ad_ETC___d142)
	$write("    ");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write &&
	  rg_abstractcs_cmderr_1_EQ_0_07_AND_write_dm_ad_ETC___d142)
	$write("DM_COMMAND_CMDTYPE_QUICK_ACCESS");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write &&
	  rg_abstractcs_cmderr_1_EQ_0_07_AND_write_dm_ad_ETC___d142)
	$write(" not supported", "\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && rg_abstractcs_cmderr == 3'd0 &&
	  write_dm_addr_EQ_0x17_08_AND_NOT_rg_abstractcs_ETC___d149)
	begin
	  v__h3544 = $stime;
	  #0;
	end
    v__h3538 = v__h3544 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && rg_abstractcs_cmderr == 3'd0 &&
	  write_dm_addr_EQ_0x17_08_AND_NOT_rg_abstractcs_ETC___d149)
	$display("%0d: DM_Abstract_Commands.write: [command] <= 0x%08h: ERROR",
		 v__h3538,
		 write_dm_word);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && rg_abstractcs_cmderr == 3'd0 &&
	  write_dm_addr_EQ_0x17_08_AND_NOT_rg_abstractcs_ETC___d149)
	$display("    For DM_COMMAND_CMDTYPE_ACCESS_REG, postexec not supported");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && rg_abstractcs_cmderr == 3'd0 &&
	  write_dm_addr_EQ_0x17_08_AND_NOT_rg_abstractcs_ETC___d167)
	begin
	  v__h3661 = $stime;
	  #0;
	end
    v__h3655 = v__h3661 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && rg_abstractcs_cmderr == 3'd0 &&
	  write_dm_addr_EQ_0x17_08_AND_NOT_rg_abstractcs_ETC___d167)
	$display("%0d: DM_Abstract_Commands.write: [command] <= 0x%08h: ERROR",
		 v__h3655,
		 write_dm_word);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && rg_abstractcs_cmderr == 3'd0 &&
	  write_dm_addr_EQ_0x17_08_AND_NOT_rg_abstractcs_ETC___d167)
	$display("    For DM_COMMAND_CMDTYPE_ACCESS_REG, no-transfer not supported");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write &&
	  rg_abstractcs_cmderr_1_EQ_0_07_AND_write_dm_ad_ETC___d174)
	begin
	  v__h3374 = $stime;
	  #0;
	end
    v__h3368 = v__h3374 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write &&
	  rg_abstractcs_cmderr_1_EQ_0_07_AND_write_dm_ad_ETC___d174)
	$display("%0d: DM_Abstract_Commands.write: [command] <= 0x%08h: ERROR",
		 v__h3368,
		 write_dm_word);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write &&
	  rg_abstractcs_cmderr_1_EQ_0_07_AND_write_dm_ad_ETC___d174)
	$write("    For DM_COMMAND_CMDTYPE_ACCESS_REG, ");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && rg_abstractcs_cmderr == 3'd0 &&
	  write_dm_addr == 7'h17 &&
	  !rg_abstractcs_busy &&
	  !write_dm_word[24] &&
	  write_dm_word[22:20] == 3'd0)
	$write("DM_COMMAND_ACCESS_REG_SIZE_UNDEF0");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && rg_abstractcs_cmderr == 3'd0 &&
	  write_dm_addr == 7'h17 &&
	  !rg_abstractcs_busy &&
	  !write_dm_word[24] &&
	  write_dm_word[22:20] == 3'd1)
	$write("DM_COMMAND_ACCESS_REG_SIZE_UNDEF1");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && rg_abstractcs_cmderr == 3'd0 &&
	  write_dm_addr == 7'h17 &&
	  !rg_abstractcs_busy &&
	  !write_dm_word[24] &&
	  write_dm_word[22:20] == 3'd2)
	$write("DM_COMMAND_ACCESS_REG_SIZE_LOWER32");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && rg_abstractcs_cmderr == 3'd0 &&
	  write_dm_addr == 7'h17 &&
	  !rg_abstractcs_busy &&
	  !write_dm_word[24] &&
	  write_dm_word[22:20] == 3'd4)
	$write("DM_COMMAND_ACCESS_REG_SIZE_LOWER128");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && rg_abstractcs_cmderr == 3'd0 &&
	  write_dm_addr == 7'h17 &&
	  !rg_abstractcs_busy &&
	  !write_dm_word[24] &&
	  write_dm_word[22:20] == 3'd5)
	$write("DM_COMMAND_ACCESS_REG_SIZE_UNDEF5");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && rg_abstractcs_cmderr == 3'd0 &&
	  write_dm_addr == 7'h17 &&
	  !rg_abstractcs_busy &&
	  !write_dm_word[24] &&
	  write_dm_word[22:20] == 3'd6)
	$write("DM_COMMAND_ACCESS_REG_SIZE_UNDEF6");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && rg_abstractcs_cmderr == 3'd0 &&
	  write_dm_addr_EQ_0x17_08_AND_NOT_rg_abstractcs_ETC___d221)
	$write("DM_COMMAND_ACCESS_REG_SIZE_UNDEF7");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write &&
	  rg_abstractcs_cmderr_1_EQ_0_07_AND_write_dm_ad_ETC___d174)
	$write(" not supported in RV64 mode", "\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && write_dm_addr != 7'h16 &&
	  rg_abstractcs_cmderr == 3'd0 &&
	  write_dm_addr != 7'h17 &&
	  write_dm_addr != 7'h04 &&
	  write_dm_addr != 7'h05)
	begin
	  v__h4152 = $stime;
	  #0;
	end
    v__h4146 = v__h4152 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && write_dm_addr != 7'h16 &&
	  rg_abstractcs_cmderr == 3'd0 &&
	  write_dm_addr != 7'h17 &&
	  write_dm_addr != 7'h04 &&
	  write_dm_addr != 7'h05)
	$write("%0d: DM_Abstract_Commands.write: [", v__h4146);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr == 7'h10)
	$write("dm_addr_dmcontrol");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr == 7'h11)
	$write("dm_addr_dmstatus");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr == 7'h12)
	$write("dm_addr_hartinfo");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr == 7'h13)
	$write("dm_addr_haltsum");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr == 7'h14)
	$write("dm_addr_hawindowsel");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr == 7'h15)
	$write("dm_addr_hawindow");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr == 7'h19)
	$write("dm_addr_devtreeaddr0");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr == 7'h30)
	$write("dm_addr_authdata");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr == 7'h40)
	$write("dm_addr_haltregion0");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr == 7'h5F)
	$write("dm_addr_haltregion31");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr == 7'h60)
	$write("dm_addr_verbosity");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr == 7'h06)
	$write("dm_addr_data2");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr == 7'h07)
	$write("dm_addr_data3");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr == 7'h08)
	$write("dm_addr_data4");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr == 7'h09)
	$write("dm_addr_data5");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr == 7'h0A)
	$write("dm_addr_data6");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr == 7'h0B)
	$write("dm_addr_data7");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr == 7'h0C)
	$write("dm_addr_data8");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr == 7'h0D)
	$write("dm_addr_data9");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr == 7'h0F)
	$write("dm_addr_data11");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr == 7'h18)
	$write("dm_addr_abstractauto");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr == 7'h20)
	$write("dm_addr_progbuf0");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr == 7'h38)
	$write("dm_addr_sbcs");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr == 7'h39)
	$write("dm_addr_sbaddress0");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr == 7'h3A)
	$write("dm_addr_sbaddress1");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr == 7'h3B)
	$write("dm_addr_sbaddress2");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr == 7'h3C)
	$write("dm_addr_sbdata0");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr == 7'h3D)
	$write("dm_addr_sbdata1");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr == 7'h3E)
	$write("dm_addr_sbdata2");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && rg_abstractcs_cmderr == 3'd0 && write_dm_addr == 7'h3F)
	$write("dm_addr_sbdata3");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && write_dm_addr != 7'h16 &&
	  rg_abstractcs_cmderr == 3'd0 &&
	  write_dm_addr != 7'h17 &&
	  write_dm_addr != 7'h04 &&
	  write_dm_addr != 7'h05 &&
	  write_dm_addr != 7'h10 &&
	  write_dm_addr != 7'h11 &&
	  write_dm_addr != 7'h12 &&
	  write_dm_addr != 7'h13 &&
	  write_dm_addr != 7'h14 &&
	  write_dm_addr != 7'h15 &&
	  write_dm_addr != 7'h19 &&
	  write_dm_addr != 7'h30 &&
	  write_dm_addr != 7'h40 &&
	  write_dm_addr != 7'h5F &&
	  write_dm_addr != 7'h60 &&
	  write_dm_addr != 7'h06 &&
	  write_dm_addr != 7'h07 &&
	  write_dm_addr != 7'h08 &&
	  write_dm_addr != 7'h09 &&
	  write_dm_addr != 7'h0A &&
	  write_dm_addr != 7'h0B &&
	  write_dm_addr != 7'h0C &&
	  write_dm_addr != 7'h0D &&
	  write_dm_addr != 7'h0F &&
	  write_dm_addr != 7'h18 &&
	  write_dm_addr != 7'h20 &&
	  write_dm_addr != 7'h38 &&
	  write_dm_addr != 7'h39 &&
	  write_dm_addr != 7'h3A &&
	  write_dm_addr != 7'h3B &&
	  write_dm_addr != 7'h3C &&
	  write_dm_addr != 7'h3D &&
	  write_dm_addr != 7'h3E &&
	  write_dm_addr != 7'h3F)
	$write("<Unknown dm_abstract_command dm_addr 0x%0h>", write_dm_addr);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_write && write_dm_addr != 7'h16 &&
	  rg_abstractcs_cmderr == 3'd0 &&
	  write_dm_addr != 7'h17 &&
	  write_dm_addr != 7'h04 &&
	  write_dm_addr != 7'h05)
	$write("] <= 0x%08h: ERROR: not supported", write_dm_word, "\n");
  end
  // synopsys translate_on
endmodule  // mkDM_Abstract_Commands

