// -----------------------------------------------------------------------------
// Auto-Generated by:        __   _ __      _  __
//                          / /  (_) /____ | |/_/
//                         / /__/ / __/ -_)>  <
//                        /____/_/\__/\__/_/|_|
//                     Build your hardware, easily!
//                   https://github.com/enjoy-digital/litex
//
// Filename   : litedram_core.v
// Device     : 
// LiteX sha1 : 0d1484dd4
// Date       : 2025-06-25 17:27:29
//------------------------------------------------------------------------------

`timescale 1ns / 1ps

//------------------------------------------------------------------------------
// Module
//------------------------------------------------------------------------------

module litedram_core (
    input  wire          clk,
    output wire   [14:0] ddram_a,
    output wire    [2:0] ddram_ba,
    output wire          ddram_cas_n,
    output wire          ddram_cke,
    output wire          ddram_clk_n,
    output wire          ddram_clk_p,
    output wire          ddram_cs_n,
    output wire    [3:0] ddram_dm,
    inout  wire   [31:0] ddram_dq,
    inout  wire    [3:0] ddram_dqs_n,
    inout  wire    [3:0] ddram_dqs_p,
    output wire          ddram_odt,
    output wire          ddram_ras_n,
    output wire          ddram_reset_n,
    output wire          ddram_we_n,
    output wire          init_done,
    output wire          init_error,
    output wire          pll_locked,
    input  wire          rst,
    input  wire          uart_rx,
    output reg           uart_tx,
    output wire          user_clk,
    output wire          user_port_wishbone_0_ack,
    input  wire   [27:0] user_port_wishbone_0_adr,
    input  wire          user_port_wishbone_0_cyc,
    output wire   [31:0] user_port_wishbone_0_dat_r,
    input  wire   [31:0] user_port_wishbone_0_dat_w,
    output wire          user_port_wishbone_0_err,
    input  wire    [3:0] user_port_wishbone_0_sel,
    input  wire          user_port_wishbone_0_stb,
    input  wire          user_port_wishbone_0_we,
    output wire          user_rst
);


//------------------------------------------------------------------------------
// Hierarchy
//------------------------------------------------------------------------------

/*
LiteDRAMCore
└─── bus (SoCBusHandler)
│    └─── _interconnect (InterconnectShared)
│    │    └─── arbiter (Arbiter)
│    │    │    └─── rr (RoundRobin)
│    │    └─── decoder (Decoder)
│    │    └─── timeout (Timeout)
│    │    │    └─── waittimer_0* (WaitTimer)
└─── csr (SoCCSRHandler)
└─── irq (SoCIRQHandler)
└─── ctrl (SoCController)
└─── cpu (VexRiscv)
│    └─── [VexRiscv]
└─── rom (SRAM)
└─── sram (SRAM)
└─── timer0 (Timer)
│    └─── ev (EventManager)
│    │    └─── eventsourceprocess_0* (EventSourceProcess)
└─── uart_phy (RS232PHY)
│    └─── tx (RS232PHYTX)
│    │    └─── clk_phase_accum (RS232ClkPhaseAccum)
│    │    └─── fsm (FSM)
│    └─── rx (RS232PHYRX)
│    │    └─── clk_phase_accum (RS232ClkPhaseAccum)
│    │    └─── fsm (FSM)
└─── uart (UART)
│    └─── ev (EventManager)
│    │    └─── eventsourceprocess_0* (EventSourceProcess)
│    │    └─── eventsourceprocess_1* (EventSourceProcess)
│    └─── tx_fifo (SyncFIFO)
│    │    └─── fifo (SyncFIFOBuffered)
│    │    │    └─── fifo (SyncFIFO)
│    └─── rx_fifo (SyncFIFO)
│    │    └─── fifo (SyncFIFOBuffered)
│    │    │    └─── fifo (SyncFIFO)
└─── crg (LiteDRAMS7DDRPHYCRG)
│    └─── pll (S7PLL)
│    │    └─── [FDCE]
│    │    └─── [FDCE]
│    │    └─── [FDCE]
│    │    └─── [FDCE]
│    │    └─── [FDCE]
│    │    └─── [FDCE]
│    │    └─── [FDCE]
│    │    └─── [FDCE]
│    │    └─── [PLLE2_ADV]
│    │    └─── [BUFG]
│    │    └─── [BUFG]
│    │    └─── [BUFG]
│    │    └─── [BUFG]
│    └─── idelayctrl (S7IDELAYCTRL)
│    │    └─── [IDELAYCTRL]
└─── ddrphy (K7DDRPHY)
│    └─── tappeddelayline_0* (TappedDelayLine)
│    └─── dqspattern_0* (DQSPattern)
│    └─── bitslip_0* (BitSlip)
│    └─── bitslip_1* (BitSlip)
│    └─── bitslip_2* (BitSlip)
│    └─── bitslip_3* (BitSlip)
│    └─── bitslip_4* (BitSlip)
│    └─── bitslip_5* (BitSlip)
│    └─── bitslip_6* (BitSlip)
│    └─── bitslip_7* (BitSlip)
│    └─── tappeddelayline_1* (TappedDelayLine)
│    └─── bitslip_8* (BitSlip)
│    └─── bitslip_9* (BitSlip)
│    └─── bitslip_10* (BitSlip)
│    └─── bitslip_11* (BitSlip)
│    └─── bitslip_12* (BitSlip)
│    └─── bitslip_13* (BitSlip)
│    └─── bitslip_14* (BitSlip)
│    └─── bitslip_15* (BitSlip)
│    └─── bitslip_16* (BitSlip)
│    └─── bitslip_17* (BitSlip)
│    └─── bitslip_18* (BitSlip)
│    └─── bitslip_19* (BitSlip)
│    └─── bitslip_20* (BitSlip)
│    └─── bitslip_21* (BitSlip)
│    └─── bitslip_22* (BitSlip)
│    └─── bitslip_23* (BitSlip)
│    └─── bitslip_24* (BitSlip)
│    └─── bitslip_25* (BitSlip)
│    └─── bitslip_26* (BitSlip)
│    └─── bitslip_27* (BitSlip)
│    └─── bitslip_28* (BitSlip)
│    └─── bitslip_29* (BitSlip)
│    └─── bitslip_30* (BitSlip)
│    └─── bitslip_31* (BitSlip)
│    └─── bitslip_32* (BitSlip)
│    └─── bitslip_33* (BitSlip)
│    └─── bitslip_34* (BitSlip)
│    └─── bitslip_35* (BitSlip)
│    └─── bitslip_36* (BitSlip)
│    └─── bitslip_37* (BitSlip)
│    └─── bitslip_38* (BitSlip)
│    └─── bitslip_39* (BitSlip)
│    └─── bitslip_40* (BitSlip)
│    └─── bitslip_41* (BitSlip)
│    └─── bitslip_42* (BitSlip)
│    └─── bitslip_43* (BitSlip)
│    └─── bitslip_44* (BitSlip)
│    └─── bitslip_45* (BitSlip)
│    └─── bitslip_46* (BitSlip)
│    └─── bitslip_47* (BitSlip)
│    └─── bitslip_48* (BitSlip)
│    └─── bitslip_49* (BitSlip)
│    └─── bitslip_50* (BitSlip)
│    └─── bitslip_51* (BitSlip)
│    └─── bitslip_52* (BitSlip)
│    └─── bitslip_53* (BitSlip)
│    └─── bitslip_54* (BitSlip)
│    └─── bitslip_55* (BitSlip)
│    └─── bitslip_56* (BitSlip)
│    └─── bitslip_57* (BitSlip)
│    └─── bitslip_58* (BitSlip)
│    └─── bitslip_59* (BitSlip)
│    └─── bitslip_60* (BitSlip)
│    └─── bitslip_61* (BitSlip)
│    └─── bitslip_62* (BitSlip)
│    └─── bitslip_63* (BitSlip)
│    └─── bitslip_64* (BitSlip)
│    └─── bitslip_65* (BitSlip)
│    └─── bitslip_66* (BitSlip)
│    └─── bitslip_67* (BitSlip)
│    └─── bitslip_68* (BitSlip)
│    └─── bitslip_69* (BitSlip)
│    └─── bitslip_70* (BitSlip)
│    └─── bitslip_71* (BitSlip)
│    └─── tappeddelayline_2* (TappedDelayLine)
│    └─── tappeddelayline_3* (TappedDelayLine)
│    └─── [IDELAYE2]
│    └─── [IOBUF]
│    └─── [OSERDESE2]
│    └─── [ISERDESE2]
│    └─── [ODELAYE2]
│    └─── [IDELAYE2]
│    └─── [IOBUF]
│    └─── [OSERDESE2]
│    └─── [ISERDESE2]
│    └─── [ODELAYE2]
│    └─── [IDELAYE2]
│    └─── [IOBUF]
│    └─── [OSERDESE2]
│    └─── [ISERDESE2]
│    └─── [ODELAYE2]
│    └─── [IDELAYE2]
│    └─── [IOBUF]
│    └─── [OSERDESE2]
│    └─── [ISERDESE2]
│    └─── [ODELAYE2]
│    └─── [IDELAYE2]
│    └─── [IOBUF]
│    └─── [OSERDESE2]
│    └─── [ISERDESE2]
│    └─── [ODELAYE2]
│    └─── [IDELAYE2]
│    └─── [IOBUF]
│    └─── [OSERDESE2]
│    └─── [ISERDESE2]
│    └─── [ODELAYE2]
│    └─── [IDELAYE2]
│    └─── [IOBUF]
│    └─── [OSERDESE2]
│    └─── [ISERDESE2]
│    └─── [ODELAYE2]
│    └─── [IDELAYE2]
│    └─── [IOBUF]
│    └─── [OSERDESE2]
│    └─── [ISERDESE2]
│    └─── [ODELAYE2]
│    └─── [IDELAYE2]
│    └─── [IOBUF]
│    └─── [OSERDESE2]
│    └─── [ISERDESE2]
│    └─── [ODELAYE2]
│    └─── [IDELAYE2]
│    └─── [IOBUF]
│    └─── [OSERDESE2]
│    └─── [ISERDESE2]
│    └─── [ODELAYE2]
│    └─── [IDELAYE2]
│    └─── [IOBUF]
│    └─── [OSERDESE2]
│    └─── [ISERDESE2]
│    └─── [ODELAYE2]
│    └─── [IDELAYE2]
│    └─── [IOBUF]
│    └─── [OSERDESE2]
│    └─── [ISERDESE2]
│    └─── [ODELAYE2]
│    └─── [IDELAYE2]
│    └─── [IOBUF]
│    └─── [OSERDESE2]
│    └─── [ISERDESE2]
│    └─── [ODELAYE2]
│    └─── [IDELAYE2]
│    └─── [IOBUF]
│    └─── [OSERDESE2]
│    └─── [ISERDESE2]
│    └─── [ODELAYE2]
│    └─── [IDELAYE2]
│    └─── [IOBUF]
│    └─── [IDELAYE2]
│    └─── [IOBUF]
│    └─── [OSERDESE2]
│    └─── [ISERDESE2]
│    └─── [ODELAYE2]
│    └─── [IDELAYE2]
│    └─── [IOBUF]
│    └─── [OSERDESE2]
│    └─── [ISERDESE2]
│    └─── [ODELAYE2]
│    └─── [IDELAYE2]
│    └─── [IOBUF]
│    └─── [OSERDESE2]
│    └─── [ISERDESE2]
│    └─── [ODELAYE2]
│    └─── [IDELAYE2]
│    └─── [IOBUF]
│    └─── [OSERDESE2]
│    └─── [ISERDESE2]
│    └─── [ODELAYE2]
│    └─── [IDELAYE2]
│    └─── [IOBUF]
│    └─── [OSERDESE2]
│    └─── [ISERDESE2]
│    └─── [ODELAYE2]
│    └─── [IDELAYE2]
│    └─── [IOBUF]
│    └─── [OSERDESE2]
│    └─── [ISERDESE2]
│    └─── [ODELAYE2]
│    └─── [IDELAYE2]
│    └─── [IOBUF]
│    └─── [OSERDESE2]
│    └─── [ISERDESE2]
│    └─── [ODELAYE2]
│    └─── [IDELAYE2]
│    └─── [IOBUF]
│    └─── [OSERDESE2]
│    └─── [ISERDESE2]
│    └─── [ODELAYE2]
│    └─── [IDELAYE2]
│    └─── [IOBUF]
│    └─── [OSERDESE2]
│    └─── [ISERDESE2]
│    └─── [ODELAYE2]
│    └─── [IDELAYE2]
│    └─── [IOBUF]
│    └─── [OSERDESE2]
│    └─── [ISERDESE2]
│    └─── [ODELAYE2]
│    └─── [IDELAYE2]
│    └─── [IOBUF]
│    └─── [OSERDESE2]
│    └─── [ISERDESE2]
│    └─── [ODELAYE2]
│    └─── [ODELAYE2]
│    └─── [OBUFDS]
│    └─── [OSERDESE2]
│    └─── [ODELAYE2]
│    └─── [OSERDESE2]
│    └─── [ODELAYE2]
│    └─── [OSERDESE2]
│    └─── [ODELAYE2]
│    └─── [OSERDESE2]
│    └─── [ODELAYE2]
│    └─── [OSERDESE2]
│    └─── [ODELAYE2]
│    └─── [OSERDESE2]
│    └─── [ODELAYE2]
│    └─── [OSERDESE2]
│    └─── [ODELAYE2]
│    └─── [OSERDESE2]
│    └─── [ODELAYE2]
│    └─── [OSERDESE2]
│    └─── [ODELAYE2]
│    └─── [OSERDESE2]
│    └─── [ODELAYE2]
│    └─── [OSERDESE2]
│    └─── [ODELAYE2]
│    └─── [OSERDESE2]
│    └─── [ODELAYE2]
│    └─── [OSERDESE2]
│    └─── [ODELAYE2]
│    └─── [OSERDESE2]
│    └─── [ODELAYE2]
│    └─── [OSERDESE2]
│    └─── [ODELAYE2]
│    └─── [OSERDESE2]
│    └─── [ODELAYE2]
│    └─── [OSERDESE2]
│    └─── [ODELAYE2]
│    └─── [OSERDESE2]
│    └─── [OSERDESE2]
│    └─── [ODELAYE2]
│    └─── [ODELAYE2]
│    └─── [OSERDESE2]
│    └─── [OSERDESE2]
│    └─── [ODELAYE2]
│    └─── [OSERDESE2]
│    └─── [ODELAYE2]
│    └─── [IOBUFDS]
│    └─── [OSERDESE2]
│    └─── [ODELAYE2]
│    └─── [IOBUFDS]
│    └─── [OSERDESE2]
│    └─── [ODELAYE2]
│    └─── [IOBUFDS]
│    └─── [OSERDESE2]
│    └─── [ODELAYE2]
│    └─── [IOBUFDS]
│    └─── [OSERDESE2]
│    └─── [ODELAYE2]
│    └─── [OSERDESE2]
│    └─── [ODELAYE2]
│    └─── [ISERDESE2]
│    └─── [OSERDESE2]
│    └─── [ODELAYE2]
│    └─── [OSERDESE2]
│    └─── [ODELAYE2]
│    └─── [OSERDESE2]
│    └─── [ISERDESE2]
│    └─── [ODELAYE2]
│    └─── [ODELAYE2]
│    └─── [IDELAYE2]
│    └─── [IOBUF]
│    └─── [OSERDESE2]
│    └─── [ISERDESE2]
│    └─── [IDELAYE2]
│    └─── [IOBUF]
│    └─── [OSERDESE2]
│    └─── [ODELAYE2]
│    └─── [IDELAYE2]
│    └─── [IOBUF]
│    └─── [OSERDESE2]
│    └─── [ISERDESE2]
│    └─── [ODELAYE2]
│    └─── [IDELAYE2]
│    └─── [IOBUF]
│    └─── [OSERDESE2]
│    └─── [ISERDESE2]
│    └─── [ODELAYE2]
│    └─── [IDELAYE2]
│    └─── [IOBUF]
│    └─── [OSERDESE2]
│    └─── [ISERDESE2]
│    └─── [ODELAYE2]
│    └─── [IDELAYE2]
│    └─── [IOBUF]
│    └─── [OSERDESE2]
│    └─── [ISERDESE2]
│    └─── [ODELAYE2]
│    └─── [OSERDESE2]
│    └─── [ODELAYE2]
│    └─── [ODELAYE2]
│    └─── [OSERDESE2]
│    └─── [OSERDESE2]
│    └─── [ODELAYE2]
│    └─── [ODELAYE2]
│    └─── [OSERDESE2]
│    └─── [ODELAYE2]
│    └─── [OSERDESE2]
└─── sdram (LiteDRAMCore)
│    └─── dfii (DFIInjector)
│    │    └─── pi0 (PhaseInjector)
│    │    └─── pi1 (PhaseInjector)
│    │    └─── pi2 (PhaseInjector)
│    │    └─── pi3 (PhaseInjector)
│    └─── controller (LiteDRAMController)
│    │    └─── refresher (Refresher)
│    │    │    └─── timer (RefreshTimer)
│    │    │    └─── postponer (RefreshPostponer)
│    │    │    └─── sequencer (RefreshSequencer)
│    │    │    │    └─── refreshexecuter_0* (RefreshExecuter)
│    │    │    └─── zqcs_timer (RefreshTimer)
│    │    │    └─── zqs_executer (ZQCSExecuter)
│    │    │    └─── fsm (FSM)
│    │    └─── bankmachine_0* (BankMachine)
│    │    │    └─── syncfifo_0* (SyncFIFO)
│    │    │    │    └─── fifo (SyncFIFO)
│    │    │    └─── buffer_0* (Buffer)
│    │    │    │    └─── pipe_valid (PipeValid)
│    │    │    │    └─── pipeline (Pipeline)
│    │    │    └─── twtpcon (tXXDController)
│    │    │    └─── trccon (tXXDController)
│    │    │    └─── trascon (tXXDController)
│    │    │    └─── fsm (FSM)
│    │    └─── bankmachine_1* (BankMachine)
│    │    │    └─── syncfifo_0* (SyncFIFO)
│    │    │    │    └─── fifo (SyncFIFO)
│    │    │    └─── buffer_0* (Buffer)
│    │    │    │    └─── pipe_valid (PipeValid)
│    │    │    │    └─── pipeline (Pipeline)
│    │    │    └─── twtpcon (tXXDController)
│    │    │    └─── trccon (tXXDController)
│    │    │    └─── trascon (tXXDController)
│    │    │    └─── fsm (FSM)
│    │    └─── bankmachine_2* (BankMachine)
│    │    │    └─── syncfifo_0* (SyncFIFO)
│    │    │    │    └─── fifo (SyncFIFO)
│    │    │    └─── buffer_0* (Buffer)
│    │    │    │    └─── pipe_valid (PipeValid)
│    │    │    │    └─── pipeline (Pipeline)
│    │    │    └─── twtpcon (tXXDController)
│    │    │    └─── trccon (tXXDController)
│    │    │    └─── trascon (tXXDController)
│    │    │    └─── fsm (FSM)
│    │    └─── bankmachine_3* (BankMachine)
│    │    │    └─── syncfifo_0* (SyncFIFO)
│    │    │    │    └─── fifo (SyncFIFO)
│    │    │    └─── buffer_0* (Buffer)
│    │    │    │    └─── pipe_valid (PipeValid)
│    │    │    │    └─── pipeline (Pipeline)
│    │    │    └─── twtpcon (tXXDController)
│    │    │    └─── trccon (tXXDController)
│    │    │    └─── trascon (tXXDController)
│    │    │    └─── fsm (FSM)
│    │    └─── bankmachine_4* (BankMachine)
│    │    │    └─── syncfifo_0* (SyncFIFO)
│    │    │    │    └─── fifo (SyncFIFO)
│    │    │    └─── buffer_0* (Buffer)
│    │    │    │    └─── pipe_valid (PipeValid)
│    │    │    │    └─── pipeline (Pipeline)
│    │    │    └─── twtpcon (tXXDController)
│    │    │    └─── trccon (tXXDController)
│    │    │    └─── trascon (tXXDController)
│    │    │    └─── fsm (FSM)
│    │    └─── bankmachine_5* (BankMachine)
│    │    │    └─── syncfifo_0* (SyncFIFO)
│    │    │    │    └─── fifo (SyncFIFO)
│    │    │    └─── buffer_0* (Buffer)
│    │    │    │    └─── pipe_valid (PipeValid)
│    │    │    │    └─── pipeline (Pipeline)
│    │    │    └─── twtpcon (tXXDController)
│    │    │    └─── trccon (tXXDController)
│    │    │    └─── trascon (tXXDController)
│    │    │    └─── fsm (FSM)
│    │    └─── bankmachine_6* (BankMachine)
│    │    │    └─── syncfifo_0* (SyncFIFO)
│    │    │    │    └─── fifo (SyncFIFO)
│    │    │    └─── buffer_0* (Buffer)
│    │    │    │    └─── pipe_valid (PipeValid)
│    │    │    │    └─── pipeline (Pipeline)
│    │    │    └─── twtpcon (tXXDController)
│    │    │    └─── trccon (tXXDController)
│    │    │    └─── trascon (tXXDController)
│    │    │    └─── fsm (FSM)
│    │    └─── bankmachine_7* (BankMachine)
│    │    │    └─── syncfifo_0* (SyncFIFO)
│    │    │    │    └─── fifo (SyncFIFO)
│    │    │    └─── buffer_0* (Buffer)
│    │    │    │    └─── pipe_valid (PipeValid)
│    │    │    │    └─── pipeline (Pipeline)
│    │    │    └─── twtpcon (tXXDController)
│    │    │    └─── trccon (tXXDController)
│    │    │    └─── trascon (tXXDController)
│    │    │    └─── fsm (FSM)
│    │    └─── multiplexer (Multiplexer)
│    │    │    └─── choose_cmd (_CommandChooser)
│    │    │    │    └─── roundrobin_0* (RoundRobin)
│    │    │    └─── choose_req (_CommandChooser)
│    │    │    │    └─── roundrobin_0* (RoundRobin)
│    │    │    └─── _steerer_0* (_Steerer)
│    │    │    └─── trrdcon (tXXDController)
│    │    │    └─── tfawcon (tFAWController)
│    │    │    └─── tccdcon (tXXDController)
│    │    │    └─── twtrcon (tXXDController)
│    │    │    └─── fsm (FSM)
│    └─── crossbar (LiteDRAMCrossbar)
│    │    └─── litedramnativeportconverter_0* (LiteDRAMNativePortConverter)
│    │    │    └─── converter (LiteDRAMNativePortUpConverter)
│    │    │    │    └─── syncfifo_0* (SyncFIFO)
│    │    │    │    └─── fsm (FSM)
│    │    │    │    └─── syncfifo_1* (SyncFIFO)
│    │    │    │    │    └─── fifo (SyncFIFO)
│    │    │    │    └─── strideconverter_0* (StrideConverter)
│    │    │    │    │    └─── converter_0* (Converter)
│    │    │    │    │    │    └─── _downconverter_0* (_DownConverter)
│    │    │    │    └─── strideconverter_1* (StrideConverter)
│    │    │    │    │    └─── converter_0* (Converter)
│    │    │    │    │    │    └─── _upconverter_0* (_UpConverter)
│    │    │    │    └─── syncfifo_2* (SyncFIFO)
│    │    │    │    │    └─── fifo (SyncFIFO)
│    │    │    │    └─── syncfifo_3* (SyncFIFO)
│    │    │    │    │    └─── buffer_0* (Buffer)
│    │    │    │    │    │    └─── pipe_valid (PipeValid)
│    │    │    │    │    │    └─── pipeline (Pipeline)
│    │    └─── roundrobin_0* (RoundRobin)
│    │    └─── roundrobin_1* (RoundRobin)
│    │    └─── roundrobin_2* (RoundRobin)
│    │    └─── roundrobin_3* (RoundRobin)
│    │    └─── roundrobin_4* (RoundRobin)
│    │    └─── roundrobin_5* (RoundRobin)
│    │    └─── roundrobin_6* (RoundRobin)
│    │    └─── roundrobin_7* (RoundRobin)
└─── l2_cache (Cache)
│    └─── fsm (FSM)
└─── wishbone_bridge (LiteDRAMWishbone2Native)
│    └─── fsm (FSM)
└─── ddrctrl (LiteDRAMCoreControl)
└─── litedramwishbone2native_0* (LiteDRAMWishbone2Native)
│    └─── fsm (FSM)
└─── csr_bridge (Wishbone2CSR)
│    └─── fsm (FSM)
└─── csr_bankarray (CSRBankArray)
│    └─── csrbank_0* (CSRBank)
│    │    └─── csrstorage_0* (CSRStorage)
│    │    └─── csrstorage_1* (CSRStorage)
│    │    └─── csrstatus_0* (CSRStatus)
│    └─── csrbank_1* (CSRBank)
│    │    └─── csrstorage_0* (CSRStorage)
│    │    └─── csrstorage_1* (CSRStorage)
│    └─── csrbank_2* (CSRBank)
│    │    └─── csrstorage_0* (CSRStorage)
│    │    └─── csrstorage_1* (CSRStorage)
│    │    └─── csrstorage_2* (CSRStorage)
│    │    └─── csrstorage_3* (CSRStorage)
│    │    └─── csrstorage_4* (CSRStorage)
│    │    └─── csrstorage_5* (CSRStorage)
│    └─── csrbank_3* (CSRBank)
│    │    └─── csrstorage_0* (CSRStorage)
│    │    └─── csrstorage_1* (CSRStorage)
│    │    └─── csrstorage_2* (CSRStorage)
│    │    └─── csrstorage_3* (CSRStorage)
│    │    └─── csrstorage_4* (CSRStorage)
│    │    └─── csrstatus_0* (CSRStatus)
│    │    └─── csrstorage_5* (CSRStorage)
│    │    └─── csrstorage_6* (CSRStorage)
│    │    └─── csrstorage_7* (CSRStorage)
│    │    └─── csrstorage_8* (CSRStorage)
│    │    └─── csrstatus_1* (CSRStatus)
│    │    └─── csrstorage_9* (CSRStorage)
│    │    └─── csrstorage_10* (CSRStorage)
│    │    └─── csrstorage_11* (CSRStorage)
│    │    └─── csrstorage_12* (CSRStorage)
│    │    └─── csrstatus_2* (CSRStatus)
│    │    └─── csrstorage_13* (CSRStorage)
│    │    └─── csrstorage_14* (CSRStorage)
│    │    └─── csrstorage_15* (CSRStorage)
│    │    └─── csrstorage_16* (CSRStorage)
│    │    └─── csrstatus_3* (CSRStatus)
│    └─── csrbank_4* (CSRBank)
│    │    └─── csrstorage_0* (CSRStorage)
│    │    └─── csrstorage_1* (CSRStorage)
│    │    └─── csrstorage_2* (CSRStorage)
│    │    └─── csrstorage_3* (CSRStorage)
│    │    └─── csrstatus_0* (CSRStatus)
│    │    └─── csrstatus_1* (CSRStatus)
│    │    └─── csrstatus_2* (CSRStatus)
│    │    └─── csrstorage_4* (CSRStorage)
│    └─── csrbank_5* (CSRBank)
│    │    └─── csrstatus_0* (CSRStatus)
│    │    └─── csrstatus_1* (CSRStatus)
│    │    └─── csrstatus_2* (CSRStatus)
│    │    └─── csrstatus_3* (CSRStatus)
│    │    └─── csrstorage_0* (CSRStorage)
│    │    └─── csrstatus_4* (CSRStatus)
│    │    └─── csrstatus_5* (CSRStatus)
└─── csr_interconnect (InterconnectShared)
└─── [FDPE]
└─── [FDPE]
└─── [FDPE]
└─── [FDPE]
└─── [FDPE]
└─── [FDPE]
└─── [FDPE]
└─── [FDPE]
* : Generated name.
[]: BlackBox.
*/

//------------------------------------------------------------------------------
// Signals
//------------------------------------------------------------------------------

wire   [13:0] adr;
reg    [19:0] count = 20'd1000000;
wire          crg_clkin;
wire          crg_clkout0;
wire          crg_clkout1;
wire          crg_clkout2;
wire          crg_clkout3;
wire          crg_clkout_buf0;
wire          crg_clkout_buf1;
wire          crg_clkout_buf2;
wire          crg_clkout_buf3;
reg           crg_ic_reset = 1'd1;
wire          crg_locked;
reg           crg_power_down = 1'd0;
wire          crg_reset;
reg     [3:0] crg_reset_counter = 4'd15;
reg           crg_rst = 1'd0;
wire   [31:0] csrbank0_bus_errors_r;
reg           csrbank0_bus_errors_re = 1'd0;
wire   [31:0] csrbank0_bus_errors_w;
reg           csrbank0_bus_errors_we = 1'd0;
wire    [1:0] csrbank0_reset0_r;
reg           csrbank0_reset0_re = 1'd0;
wire    [1:0] csrbank0_reset0_w;
reg           csrbank0_reset0_we = 1'd0;
wire   [31:0] csrbank0_scratch0_r;
reg           csrbank0_scratch0_re = 1'd0;
wire   [31:0] csrbank0_scratch0_w;
reg           csrbank0_scratch0_we = 1'd0;
wire          csrbank0_sel;
wire          csrbank1_init_done0_r;
reg           csrbank1_init_done0_re = 1'd0;
wire          csrbank1_init_done0_w;
reg           csrbank1_init_done0_we = 1'd0;
wire          csrbank1_init_error0_r;
reg           csrbank1_init_error0_re = 1'd0;
wire          csrbank1_init_error0_w;
reg           csrbank1_init_error0_we = 1'd0;
wire          csrbank1_sel;
wire    [3:0] csrbank2_dly_sel0_r;
reg           csrbank2_dly_sel0_re = 1'd0;
wire    [3:0] csrbank2_dly_sel0_w;
reg           csrbank2_dly_sel0_we = 1'd0;
wire    [4:0] csrbank2_half_sys8x_taps0_r;
reg           csrbank2_half_sys8x_taps0_re = 1'd0;
wire    [4:0] csrbank2_half_sys8x_taps0_w;
reg           csrbank2_half_sys8x_taps0_we = 1'd0;
wire    [1:0] csrbank2_rdphase0_r;
reg           csrbank2_rdphase0_re = 1'd0;
wire    [1:0] csrbank2_rdphase0_w;
reg           csrbank2_rdphase0_we = 1'd0;
wire          csrbank2_rst0_r;
reg           csrbank2_rst0_re = 1'd0;
wire          csrbank2_rst0_w;
reg           csrbank2_rst0_we = 1'd0;
wire          csrbank2_sel;
wire          csrbank2_wlevel_en0_r;
reg           csrbank2_wlevel_en0_re = 1'd0;
wire          csrbank2_wlevel_en0_w;
reg           csrbank2_wlevel_en0_we = 1'd0;
wire    [1:0] csrbank2_wrphase0_r;
reg           csrbank2_wrphase0_re = 1'd0;
wire    [1:0] csrbank2_wrphase0_w;
reg           csrbank2_wrphase0_we = 1'd0;
wire    [3:0] csrbank3_dfii_control0_r;
reg           csrbank3_dfii_control0_re = 1'd0;
wire    [3:0] csrbank3_dfii_control0_w;
reg           csrbank3_dfii_control0_we = 1'd0;
wire   [14:0] csrbank3_dfii_pi0_address0_r;
reg           csrbank3_dfii_pi0_address0_re = 1'd0;
wire   [14:0] csrbank3_dfii_pi0_address0_w;
reg           csrbank3_dfii_pi0_address0_we = 1'd0;
wire    [2:0] csrbank3_dfii_pi0_baddress0_r;
reg           csrbank3_dfii_pi0_baddress0_re = 1'd0;
wire    [2:0] csrbank3_dfii_pi0_baddress0_w;
reg           csrbank3_dfii_pi0_baddress0_we = 1'd0;
wire    [7:0] csrbank3_dfii_pi0_command0_r;
reg           csrbank3_dfii_pi0_command0_re = 1'd0;
wire    [7:0] csrbank3_dfii_pi0_command0_w;
reg           csrbank3_dfii_pi0_command0_we = 1'd0;
wire   [31:0] csrbank3_dfii_pi0_rddata0_r;
reg           csrbank3_dfii_pi0_rddata0_re = 1'd0;
wire   [31:0] csrbank3_dfii_pi0_rddata0_w;
reg           csrbank3_dfii_pi0_rddata0_we = 1'd0;
wire   [31:0] csrbank3_dfii_pi0_rddata1_r;
reg           csrbank3_dfii_pi0_rddata1_re = 1'd0;
wire   [31:0] csrbank3_dfii_pi0_rddata1_w;
reg           csrbank3_dfii_pi0_rddata1_we = 1'd0;
wire   [31:0] csrbank3_dfii_pi0_wrdata0_r;
reg           csrbank3_dfii_pi0_wrdata0_re = 1'd0;
wire   [31:0] csrbank3_dfii_pi0_wrdata0_w;
reg           csrbank3_dfii_pi0_wrdata0_we = 1'd0;
wire   [31:0] csrbank3_dfii_pi0_wrdata1_r;
reg           csrbank3_dfii_pi0_wrdata1_re = 1'd0;
wire   [31:0] csrbank3_dfii_pi0_wrdata1_w;
reg           csrbank3_dfii_pi0_wrdata1_we = 1'd0;
wire   [14:0] csrbank3_dfii_pi1_address0_r;
reg           csrbank3_dfii_pi1_address0_re = 1'd0;
wire   [14:0] csrbank3_dfii_pi1_address0_w;
reg           csrbank3_dfii_pi1_address0_we = 1'd0;
wire    [2:0] csrbank3_dfii_pi1_baddress0_r;
reg           csrbank3_dfii_pi1_baddress0_re = 1'd0;
wire    [2:0] csrbank3_dfii_pi1_baddress0_w;
reg           csrbank3_dfii_pi1_baddress0_we = 1'd0;
wire    [7:0] csrbank3_dfii_pi1_command0_r;
reg           csrbank3_dfii_pi1_command0_re = 1'd0;
wire    [7:0] csrbank3_dfii_pi1_command0_w;
reg           csrbank3_dfii_pi1_command0_we = 1'd0;
wire   [31:0] csrbank3_dfii_pi1_rddata0_r;
reg           csrbank3_dfii_pi1_rddata0_re = 1'd0;
wire   [31:0] csrbank3_dfii_pi1_rddata0_w;
reg           csrbank3_dfii_pi1_rddata0_we = 1'd0;
wire   [31:0] csrbank3_dfii_pi1_rddata1_r;
reg           csrbank3_dfii_pi1_rddata1_re = 1'd0;
wire   [31:0] csrbank3_dfii_pi1_rddata1_w;
reg           csrbank3_dfii_pi1_rddata1_we = 1'd0;
wire   [31:0] csrbank3_dfii_pi1_wrdata0_r;
reg           csrbank3_dfii_pi1_wrdata0_re = 1'd0;
wire   [31:0] csrbank3_dfii_pi1_wrdata0_w;
reg           csrbank3_dfii_pi1_wrdata0_we = 1'd0;
wire   [31:0] csrbank3_dfii_pi1_wrdata1_r;
reg           csrbank3_dfii_pi1_wrdata1_re = 1'd0;
wire   [31:0] csrbank3_dfii_pi1_wrdata1_w;
reg           csrbank3_dfii_pi1_wrdata1_we = 1'd0;
wire   [14:0] csrbank3_dfii_pi2_address0_r;
reg           csrbank3_dfii_pi2_address0_re = 1'd0;
wire   [14:0] csrbank3_dfii_pi2_address0_w;
reg           csrbank3_dfii_pi2_address0_we = 1'd0;
wire    [2:0] csrbank3_dfii_pi2_baddress0_r;
reg           csrbank3_dfii_pi2_baddress0_re = 1'd0;
wire    [2:0] csrbank3_dfii_pi2_baddress0_w;
reg           csrbank3_dfii_pi2_baddress0_we = 1'd0;
wire    [7:0] csrbank3_dfii_pi2_command0_r;
reg           csrbank3_dfii_pi2_command0_re = 1'd0;
wire    [7:0] csrbank3_dfii_pi2_command0_w;
reg           csrbank3_dfii_pi2_command0_we = 1'd0;
wire   [31:0] csrbank3_dfii_pi2_rddata0_r;
reg           csrbank3_dfii_pi2_rddata0_re = 1'd0;
wire   [31:0] csrbank3_dfii_pi2_rddata0_w;
reg           csrbank3_dfii_pi2_rddata0_we = 1'd0;
wire   [31:0] csrbank3_dfii_pi2_rddata1_r;
reg           csrbank3_dfii_pi2_rddata1_re = 1'd0;
wire   [31:0] csrbank3_dfii_pi2_rddata1_w;
reg           csrbank3_dfii_pi2_rddata1_we = 1'd0;
wire   [31:0] csrbank3_dfii_pi2_wrdata0_r;
reg           csrbank3_dfii_pi2_wrdata0_re = 1'd0;
wire   [31:0] csrbank3_dfii_pi2_wrdata0_w;
reg           csrbank3_dfii_pi2_wrdata0_we = 1'd0;
wire   [31:0] csrbank3_dfii_pi2_wrdata1_r;
reg           csrbank3_dfii_pi2_wrdata1_re = 1'd0;
wire   [31:0] csrbank3_dfii_pi2_wrdata1_w;
reg           csrbank3_dfii_pi2_wrdata1_we = 1'd0;
wire   [14:0] csrbank3_dfii_pi3_address0_r;
reg           csrbank3_dfii_pi3_address0_re = 1'd0;
wire   [14:0] csrbank3_dfii_pi3_address0_w;
reg           csrbank3_dfii_pi3_address0_we = 1'd0;
wire    [2:0] csrbank3_dfii_pi3_baddress0_r;
reg           csrbank3_dfii_pi3_baddress0_re = 1'd0;
wire    [2:0] csrbank3_dfii_pi3_baddress0_w;
reg           csrbank3_dfii_pi3_baddress0_we = 1'd0;
wire    [7:0] csrbank3_dfii_pi3_command0_r;
reg           csrbank3_dfii_pi3_command0_re = 1'd0;
wire    [7:0] csrbank3_dfii_pi3_command0_w;
reg           csrbank3_dfii_pi3_command0_we = 1'd0;
wire   [31:0] csrbank3_dfii_pi3_rddata0_r;
reg           csrbank3_dfii_pi3_rddata0_re = 1'd0;
wire   [31:0] csrbank3_dfii_pi3_rddata0_w;
reg           csrbank3_dfii_pi3_rddata0_we = 1'd0;
wire   [31:0] csrbank3_dfii_pi3_rddata1_r;
reg           csrbank3_dfii_pi3_rddata1_re = 1'd0;
wire   [31:0] csrbank3_dfii_pi3_rddata1_w;
reg           csrbank3_dfii_pi3_rddata1_we = 1'd0;
wire   [31:0] csrbank3_dfii_pi3_wrdata0_r;
reg           csrbank3_dfii_pi3_wrdata0_re = 1'd0;
wire   [31:0] csrbank3_dfii_pi3_wrdata0_w;
reg           csrbank3_dfii_pi3_wrdata0_we = 1'd0;
wire   [31:0] csrbank3_dfii_pi3_wrdata1_r;
reg           csrbank3_dfii_pi3_wrdata1_re = 1'd0;
wire   [31:0] csrbank3_dfii_pi3_wrdata1_w;
reg           csrbank3_dfii_pi3_wrdata1_we = 1'd0;
wire          csrbank3_sel;
wire          csrbank4_en0_r;
reg           csrbank4_en0_re = 1'd0;
wire          csrbank4_en0_w;
reg           csrbank4_en0_we = 1'd0;
wire          csrbank4_ev_enable0_r;
reg           csrbank4_ev_enable0_re = 1'd0;
wire          csrbank4_ev_enable0_w;
reg           csrbank4_ev_enable0_we = 1'd0;
wire          csrbank4_ev_pending_r;
reg           csrbank4_ev_pending_re = 1'd0;
wire          csrbank4_ev_pending_w;
reg           csrbank4_ev_pending_we = 1'd0;
wire          csrbank4_ev_status_r;
reg           csrbank4_ev_status_re = 1'd0;
wire          csrbank4_ev_status_w;
reg           csrbank4_ev_status_we = 1'd0;
wire   [31:0] csrbank4_load0_r;
reg           csrbank4_load0_re = 1'd0;
wire   [31:0] csrbank4_load0_w;
reg           csrbank4_load0_we = 1'd0;
wire   [31:0] csrbank4_reload0_r;
reg           csrbank4_reload0_re = 1'd0;
wire   [31:0] csrbank4_reload0_w;
reg           csrbank4_reload0_we = 1'd0;
wire          csrbank4_sel;
wire          csrbank4_update_value0_r;
reg           csrbank4_update_value0_re = 1'd0;
wire          csrbank4_update_value0_w;
reg           csrbank4_update_value0_we = 1'd0;
wire   [31:0] csrbank4_value_r;
reg           csrbank4_value_re = 1'd0;
wire   [31:0] csrbank4_value_w;
reg           csrbank4_value_we = 1'd0;
wire    [1:0] csrbank5_ev_enable0_r;
reg           csrbank5_ev_enable0_re = 1'd0;
wire    [1:0] csrbank5_ev_enable0_w;
reg           csrbank5_ev_enable0_we = 1'd0;
wire    [1:0] csrbank5_ev_pending_r;
reg           csrbank5_ev_pending_re = 1'd0;
wire    [1:0] csrbank5_ev_pending_w;
reg           csrbank5_ev_pending_we = 1'd0;
wire    [1:0] csrbank5_ev_status_r;
reg           csrbank5_ev_status_re = 1'd0;
wire    [1:0] csrbank5_ev_status_w;
reg           csrbank5_ev_status_we = 1'd0;
wire          csrbank5_rxempty_r;
reg           csrbank5_rxempty_re = 1'd0;
wire          csrbank5_rxempty_w;
reg           csrbank5_rxempty_we = 1'd0;
wire          csrbank5_rxfull_r;
reg           csrbank5_rxfull_re = 1'd0;
wire          csrbank5_rxfull_w;
reg           csrbank5_rxfull_we = 1'd0;
wire          csrbank5_sel;
wire          csrbank5_txempty_r;
reg           csrbank5_txempty_re = 1'd0;
wire          csrbank5_txempty_w;
reg           csrbank5_txempty_we = 1'd0;
wire          csrbank5_txfull_r;
reg           csrbank5_txfull_re = 1'd0;
wire          csrbank5_txfull_w;
reg           csrbank5_txfull_we = 1'd0;
wire   [31:0] dat_r;
wire   [31:0] dat_w;
wire          done;
reg           error = 1'd0;
reg     [1:0] fullmemorywe_next_state = 2'd0;
reg     [1:0] fullmemorywe_state = 2'd0;
reg           grant = 1'd0;
reg           init_done_re = 1'd0;
reg           init_done_storage = 1'd0;
reg           init_error_re = 1'd0;
reg           init_error_storage = 1'd0;
reg           interface0_ack = 1'd0;
wire   [29:0] interface0_adr;
wire   [13:0] interface0_bank_bus_adr;
reg    [31:0] interface0_bank_bus_dat_r = 32'd0;
wire   [31:0] interface0_bank_bus_dat_w;
wire          interface0_bank_bus_re;
wire          interface0_bank_bus_we;
wire    [1:0] interface0_bte;
wire    [2:0] interface0_cti;
wire          interface0_cyc;
reg    [31:0] interface0_dat_r = 32'd0;
wire   [31:0] interface0_dat_w;
reg           interface0_err = 1'd0;
wire    [3:0] interface0_sel;
wire          interface0_stb;
wire          interface0_we;
reg    [13:0] interface1_adr = 14'd0;
reg    [13:0] interface1_adr_wishbone2csr_next_value1 = 14'd0;
reg           interface1_adr_wishbone2csr_next_value_ce1 = 1'd0;
wire   [13:0] interface1_bank_bus_adr;
reg    [31:0] interface1_bank_bus_dat_r = 32'd0;
wire   [31:0] interface1_bank_bus_dat_w;
wire          interface1_bank_bus_re;
wire          interface1_bank_bus_we;
wire   [31:0] interface1_dat_r;
reg    [31:0] interface1_dat_w = 32'd0;
reg    [31:0] interface1_dat_w_wishbone2csr_next_value0 = 32'd0;
reg           interface1_dat_w_wishbone2csr_next_value_ce0 = 1'd0;
reg           interface1_re = 1'd0;
reg           interface1_re_wishbone2csr_next_value2 = 1'd0;
reg           interface1_re_wishbone2csr_next_value_ce2 = 1'd0;
reg           interface1_we = 1'd0;
reg           interface1_we_wishbone2csr_next_value3 = 1'd0;
reg           interface1_we_wishbone2csr_next_value_ce3 = 1'd0;
wire   [13:0] interface2_bank_bus_adr;
reg    [31:0] interface2_bank_bus_dat_r = 32'd0;
wire   [31:0] interface2_bank_bus_dat_w;
wire          interface2_bank_bus_re;
wire          interface2_bank_bus_we;
wire   [13:0] interface3_bank_bus_adr;
reg    [31:0] interface3_bank_bus_dat_r = 32'd0;
wire   [31:0] interface3_bank_bus_dat_w;
wire          interface3_bank_bus_re;
wire          interface3_bank_bus_we;
wire   [13:0] interface4_bank_bus_adr;
reg    [31:0] interface4_bank_bus_dat_r = 32'd0;
wire   [31:0] interface4_bank_bus_dat_w;
wire          interface4_bank_bus_re;
wire          interface4_bank_bus_we;
wire   [13:0] interface5_bank_bus_adr;
reg    [31:0] interface5_bank_bus_dat_r = 32'd0;
wire   [31:0] interface5_bank_bus_dat_w;
wire          interface5_bank_bus_re;
wire          interface5_bank_bus_we;
wire          iodelay_clk;
wire          iodelay_rst;
wire          k7ddrphy0;
wire          k7ddrphy1;
wire          k7ddrphy2;
wire          k7ddrphy3;
reg     [7:0] k7ddrphy_bitslip00 = 8'd0;
reg     [7:0] k7ddrphy_bitslip01 = 8'd0;
reg     [7:0] k7ddrphy_bitslip02 = 8'd0;
wire    [7:0] k7ddrphy_bitslip03;
reg     [7:0] k7ddrphy_bitslip04 = 8'd0;
reg    [15:0] k7ddrphy_bitslip0_r0 = 16'd0;
reg    [15:0] k7ddrphy_bitslip0_r1 = 16'd0;
reg    [15:0] k7ddrphy_bitslip0_r2 = 16'd0;
reg    [15:0] k7ddrphy_bitslip0_r3 = 16'd0;
reg     [2:0] k7ddrphy_bitslip0_value0 = 3'd7;
reg     [2:0] k7ddrphy_bitslip0_value1 = 3'd7;
reg     [2:0] k7ddrphy_bitslip0_value2 = 3'd7;
reg     [2:0] k7ddrphy_bitslip0_value3 = 3'd7;
reg     [7:0] k7ddrphy_bitslip10 = 8'd0;
reg     [7:0] k7ddrphy_bitslip100 = 8'd0;
wire    [7:0] k7ddrphy_bitslip101;
reg     [7:0] k7ddrphy_bitslip102 = 8'd0;
reg    [15:0] k7ddrphy_bitslip10_r0 = 16'd0;
reg    [15:0] k7ddrphy_bitslip10_r1 = 16'd0;
reg     [2:0] k7ddrphy_bitslip10_value0 = 3'd7;
reg     [2:0] k7ddrphy_bitslip10_value1 = 3'd7;
reg     [7:0] k7ddrphy_bitslip11 = 8'd0;
reg     [7:0] k7ddrphy_bitslip110 = 8'd0;
wire    [7:0] k7ddrphy_bitslip111;
reg     [7:0] k7ddrphy_bitslip112 = 8'd0;
reg    [15:0] k7ddrphy_bitslip11_r0 = 16'd0;
reg    [15:0] k7ddrphy_bitslip11_r1 = 16'd0;
reg     [2:0] k7ddrphy_bitslip11_value0 = 3'd7;
reg     [2:0] k7ddrphy_bitslip11_value1 = 3'd7;
reg     [7:0] k7ddrphy_bitslip12 = 8'd0;
reg     [7:0] k7ddrphy_bitslip120 = 8'd0;
wire    [7:0] k7ddrphy_bitslip121;
reg     [7:0] k7ddrphy_bitslip122 = 8'd0;
reg    [15:0] k7ddrphy_bitslip12_r0 = 16'd0;
reg    [15:0] k7ddrphy_bitslip12_r1 = 16'd0;
reg     [2:0] k7ddrphy_bitslip12_value0 = 3'd7;
reg     [2:0] k7ddrphy_bitslip12_value1 = 3'd7;
wire    [7:0] k7ddrphy_bitslip13;
reg     [7:0] k7ddrphy_bitslip130 = 8'd0;
wire    [7:0] k7ddrphy_bitslip131;
reg     [7:0] k7ddrphy_bitslip132 = 8'd0;
reg    [15:0] k7ddrphy_bitslip13_r0 = 16'd0;
reg    [15:0] k7ddrphy_bitslip13_r1 = 16'd0;
reg     [2:0] k7ddrphy_bitslip13_value0 = 3'd7;
reg     [2:0] k7ddrphy_bitslip13_value1 = 3'd7;
reg     [7:0] k7ddrphy_bitslip14 = 8'd0;
reg     [7:0] k7ddrphy_bitslip140 = 8'd0;
wire    [7:0] k7ddrphy_bitslip141;
reg     [7:0] k7ddrphy_bitslip142 = 8'd0;
reg    [15:0] k7ddrphy_bitslip14_r0 = 16'd0;
reg    [15:0] k7ddrphy_bitslip14_r1 = 16'd0;
reg     [2:0] k7ddrphy_bitslip14_value0 = 3'd7;
reg     [2:0] k7ddrphy_bitslip14_value1 = 3'd7;
reg     [7:0] k7ddrphy_bitslip150 = 8'd0;
wire    [7:0] k7ddrphy_bitslip151;
reg     [7:0] k7ddrphy_bitslip152 = 8'd0;
reg    [15:0] k7ddrphy_bitslip15_r0 = 16'd0;
reg    [15:0] k7ddrphy_bitslip15_r1 = 16'd0;
reg     [2:0] k7ddrphy_bitslip15_value0 = 3'd7;
reg     [2:0] k7ddrphy_bitslip15_value1 = 3'd7;
reg     [7:0] k7ddrphy_bitslip160 = 8'd0;
wire    [7:0] k7ddrphy_bitslip161;
reg     [7:0] k7ddrphy_bitslip162 = 8'd0;
reg    [15:0] k7ddrphy_bitslip16_r0 = 16'd0;
reg    [15:0] k7ddrphy_bitslip16_r1 = 16'd0;
reg     [2:0] k7ddrphy_bitslip16_value0 = 3'd7;
reg     [2:0] k7ddrphy_bitslip16_value1 = 3'd7;
reg     [7:0] k7ddrphy_bitslip170 = 8'd0;
wire    [7:0] k7ddrphy_bitslip171;
reg     [7:0] k7ddrphy_bitslip172 = 8'd0;
reg    [15:0] k7ddrphy_bitslip17_r0 = 16'd0;
reg    [15:0] k7ddrphy_bitslip17_r1 = 16'd0;
reg     [2:0] k7ddrphy_bitslip17_value0 = 3'd7;
reg     [2:0] k7ddrphy_bitslip17_value1 = 3'd7;
reg     [7:0] k7ddrphy_bitslip180 = 8'd0;
wire    [7:0] k7ddrphy_bitslip181;
reg     [7:0] k7ddrphy_bitslip182 = 8'd0;
reg    [15:0] k7ddrphy_bitslip18_r0 = 16'd0;
reg    [15:0] k7ddrphy_bitslip18_r1 = 16'd0;
reg     [2:0] k7ddrphy_bitslip18_value0 = 3'd7;
reg     [2:0] k7ddrphy_bitslip18_value1 = 3'd7;
reg     [7:0] k7ddrphy_bitslip190 = 8'd0;
wire    [7:0] k7ddrphy_bitslip191;
reg     [7:0] k7ddrphy_bitslip192 = 8'd0;
reg    [15:0] k7ddrphy_bitslip19_r0 = 16'd0;
reg    [15:0] k7ddrphy_bitslip19_r1 = 16'd0;
reg     [2:0] k7ddrphy_bitslip19_value0 = 3'd7;
reg     [2:0] k7ddrphy_bitslip19_value1 = 3'd7;
reg    [15:0] k7ddrphy_bitslip1_r0 = 16'd0;
reg    [15:0] k7ddrphy_bitslip1_r1 = 16'd0;
reg    [15:0] k7ddrphy_bitslip1_r2 = 16'd0;
reg    [15:0] k7ddrphy_bitslip1_r3 = 16'd0;
reg     [2:0] k7ddrphy_bitslip1_value0 = 3'd7;
reg     [2:0] k7ddrphy_bitslip1_value1 = 3'd7;
reg     [2:0] k7ddrphy_bitslip1_value2 = 3'd7;
reg     [2:0] k7ddrphy_bitslip1_value3 = 3'd7;
reg     [7:0] k7ddrphy_bitslip20 = 8'd0;
reg     [7:0] k7ddrphy_bitslip200 = 8'd0;
wire    [7:0] k7ddrphy_bitslip201;
reg     [7:0] k7ddrphy_bitslip202 = 8'd0;
reg    [15:0] k7ddrphy_bitslip20_r0 = 16'd0;
reg    [15:0] k7ddrphy_bitslip20_r1 = 16'd0;
reg     [2:0] k7ddrphy_bitslip20_value0 = 3'd7;
reg     [2:0] k7ddrphy_bitslip20_value1 = 3'd7;
reg     [7:0] k7ddrphy_bitslip21 = 8'd0;
reg     [7:0] k7ddrphy_bitslip210 = 8'd0;
wire    [7:0] k7ddrphy_bitslip211;
reg     [7:0] k7ddrphy_bitslip212 = 8'd0;
reg    [15:0] k7ddrphy_bitslip21_r0 = 16'd0;
reg    [15:0] k7ddrphy_bitslip21_r1 = 16'd0;
reg     [2:0] k7ddrphy_bitslip21_value0 = 3'd7;
reg     [2:0] k7ddrphy_bitslip21_value1 = 3'd7;
reg     [7:0] k7ddrphy_bitslip22 = 8'd0;
reg     [7:0] k7ddrphy_bitslip220 = 8'd0;
wire    [7:0] k7ddrphy_bitslip221;
reg     [7:0] k7ddrphy_bitslip222 = 8'd0;
reg    [15:0] k7ddrphy_bitslip22_r0 = 16'd0;
reg    [15:0] k7ddrphy_bitslip22_r1 = 16'd0;
reg     [2:0] k7ddrphy_bitslip22_value0 = 3'd7;
reg     [2:0] k7ddrphy_bitslip22_value1 = 3'd7;
wire    [7:0] k7ddrphy_bitslip23;
reg     [7:0] k7ddrphy_bitslip230 = 8'd0;
wire    [7:0] k7ddrphy_bitslip231;
reg     [7:0] k7ddrphy_bitslip232 = 8'd0;
reg    [15:0] k7ddrphy_bitslip23_r0 = 16'd0;
reg    [15:0] k7ddrphy_bitslip23_r1 = 16'd0;
reg     [2:0] k7ddrphy_bitslip23_value0 = 3'd7;
reg     [2:0] k7ddrphy_bitslip23_value1 = 3'd7;
reg     [7:0] k7ddrphy_bitslip24 = 8'd0;
reg     [7:0] k7ddrphy_bitslip240 = 8'd0;
wire    [7:0] k7ddrphy_bitslip241;
reg     [7:0] k7ddrphy_bitslip242 = 8'd0;
reg    [15:0] k7ddrphy_bitslip24_r0 = 16'd0;
reg    [15:0] k7ddrphy_bitslip24_r1 = 16'd0;
reg     [2:0] k7ddrphy_bitslip24_value0 = 3'd7;
reg     [2:0] k7ddrphy_bitslip24_value1 = 3'd7;
reg     [7:0] k7ddrphy_bitslip250 = 8'd0;
wire    [7:0] k7ddrphy_bitslip251;
reg     [7:0] k7ddrphy_bitslip252 = 8'd0;
reg    [15:0] k7ddrphy_bitslip25_r0 = 16'd0;
reg    [15:0] k7ddrphy_bitslip25_r1 = 16'd0;
reg     [2:0] k7ddrphy_bitslip25_value0 = 3'd7;
reg     [2:0] k7ddrphy_bitslip25_value1 = 3'd7;
reg     [7:0] k7ddrphy_bitslip260 = 8'd0;
wire    [7:0] k7ddrphy_bitslip261;
reg     [7:0] k7ddrphy_bitslip262 = 8'd0;
reg    [15:0] k7ddrphy_bitslip26_r0 = 16'd0;
reg    [15:0] k7ddrphy_bitslip26_r1 = 16'd0;
reg     [2:0] k7ddrphy_bitslip26_value0 = 3'd7;
reg     [2:0] k7ddrphy_bitslip26_value1 = 3'd7;
reg     [7:0] k7ddrphy_bitslip270 = 8'd0;
wire    [7:0] k7ddrphy_bitslip271;
reg     [7:0] k7ddrphy_bitslip272 = 8'd0;
reg    [15:0] k7ddrphy_bitslip27_r0 = 16'd0;
reg    [15:0] k7ddrphy_bitslip27_r1 = 16'd0;
reg     [2:0] k7ddrphy_bitslip27_value0 = 3'd7;
reg     [2:0] k7ddrphy_bitslip27_value1 = 3'd7;
reg     [7:0] k7ddrphy_bitslip280 = 8'd0;
wire    [7:0] k7ddrphy_bitslip281;
reg     [7:0] k7ddrphy_bitslip282 = 8'd0;
reg    [15:0] k7ddrphy_bitslip28_r0 = 16'd0;
reg    [15:0] k7ddrphy_bitslip28_r1 = 16'd0;
reg     [2:0] k7ddrphy_bitslip28_value0 = 3'd7;
reg     [2:0] k7ddrphy_bitslip28_value1 = 3'd7;
reg     [7:0] k7ddrphy_bitslip290 = 8'd0;
wire    [7:0] k7ddrphy_bitslip291;
reg     [7:0] k7ddrphy_bitslip292 = 8'd0;
reg    [15:0] k7ddrphy_bitslip29_r0 = 16'd0;
reg    [15:0] k7ddrphy_bitslip29_r1 = 16'd0;
reg     [2:0] k7ddrphy_bitslip29_value0 = 3'd7;
reg     [2:0] k7ddrphy_bitslip29_value1 = 3'd7;
reg    [15:0] k7ddrphy_bitslip2_r0 = 16'd0;
reg    [15:0] k7ddrphy_bitslip2_r1 = 16'd0;
reg    [15:0] k7ddrphy_bitslip2_r2 = 16'd0;
reg    [15:0] k7ddrphy_bitslip2_r3 = 16'd0;
reg     [2:0] k7ddrphy_bitslip2_value0 = 3'd7;
reg     [2:0] k7ddrphy_bitslip2_value1 = 3'd7;
reg     [2:0] k7ddrphy_bitslip2_value2 = 3'd7;
reg     [2:0] k7ddrphy_bitslip2_value3 = 3'd7;
reg     [7:0] k7ddrphy_bitslip30 = 8'd0;
reg     [7:0] k7ddrphy_bitslip300 = 8'd0;
wire    [7:0] k7ddrphy_bitslip301;
reg     [7:0] k7ddrphy_bitslip302 = 8'd0;
reg    [15:0] k7ddrphy_bitslip30_r0 = 16'd0;
reg    [15:0] k7ddrphy_bitslip30_r1 = 16'd0;
reg     [2:0] k7ddrphy_bitslip30_value0 = 3'd7;
reg     [2:0] k7ddrphy_bitslip30_value1 = 3'd7;
reg     [7:0] k7ddrphy_bitslip31 = 8'd0;
reg     [7:0] k7ddrphy_bitslip310 = 8'd0;
wire    [7:0] k7ddrphy_bitslip311;
reg     [7:0] k7ddrphy_bitslip312 = 8'd0;
reg    [15:0] k7ddrphy_bitslip31_r0 = 16'd0;
reg    [15:0] k7ddrphy_bitslip31_r1 = 16'd0;
reg     [2:0] k7ddrphy_bitslip31_value0 = 3'd7;
reg     [2:0] k7ddrphy_bitslip31_value1 = 3'd7;
reg     [7:0] k7ddrphy_bitslip32 = 8'd0;
wire    [7:0] k7ddrphy_bitslip33;
reg     [7:0] k7ddrphy_bitslip34 = 8'd0;
reg    [15:0] k7ddrphy_bitslip3_r0 = 16'd0;
reg    [15:0] k7ddrphy_bitslip3_r1 = 16'd0;
reg    [15:0] k7ddrphy_bitslip3_r2 = 16'd0;
reg    [15:0] k7ddrphy_bitslip3_r3 = 16'd0;
reg     [2:0] k7ddrphy_bitslip3_value0 = 3'd7;
reg     [2:0] k7ddrphy_bitslip3_value1 = 3'd7;
reg     [2:0] k7ddrphy_bitslip3_value2 = 3'd7;
reg     [2:0] k7ddrphy_bitslip3_value3 = 3'd7;
reg     [7:0] k7ddrphy_bitslip40 = 8'd0;
wire    [7:0] k7ddrphy_bitslip41;
reg     [7:0] k7ddrphy_bitslip42 = 8'd0;
reg    [15:0] k7ddrphy_bitslip4_r0 = 16'd0;
reg    [15:0] k7ddrphy_bitslip4_r1 = 16'd0;
reg     [2:0] k7ddrphy_bitslip4_value0 = 3'd7;
reg     [2:0] k7ddrphy_bitslip4_value1 = 3'd7;
reg     [7:0] k7ddrphy_bitslip50 = 8'd0;
wire    [7:0] k7ddrphy_bitslip51;
reg     [7:0] k7ddrphy_bitslip52 = 8'd0;
reg    [15:0] k7ddrphy_bitslip5_r0 = 16'd0;
reg    [15:0] k7ddrphy_bitslip5_r1 = 16'd0;
reg     [2:0] k7ddrphy_bitslip5_value0 = 3'd7;
reg     [2:0] k7ddrphy_bitslip5_value1 = 3'd7;
reg     [7:0] k7ddrphy_bitslip60 = 8'd0;
wire    [7:0] k7ddrphy_bitslip61;
reg     [7:0] k7ddrphy_bitslip62 = 8'd0;
reg    [15:0] k7ddrphy_bitslip6_r0 = 16'd0;
reg    [15:0] k7ddrphy_bitslip6_r1 = 16'd0;
reg     [2:0] k7ddrphy_bitslip6_value0 = 3'd7;
reg     [2:0] k7ddrphy_bitslip6_value1 = 3'd7;
reg     [7:0] k7ddrphy_bitslip70 = 8'd0;
wire    [7:0] k7ddrphy_bitslip71;
reg     [7:0] k7ddrphy_bitslip72 = 8'd0;
reg    [15:0] k7ddrphy_bitslip7_r0 = 16'd0;
reg    [15:0] k7ddrphy_bitslip7_r1 = 16'd0;
reg     [2:0] k7ddrphy_bitslip7_value0 = 3'd7;
reg     [2:0] k7ddrphy_bitslip7_value1 = 3'd7;
reg     [7:0] k7ddrphy_bitslip80 = 8'd0;
wire    [7:0] k7ddrphy_bitslip81;
reg     [7:0] k7ddrphy_bitslip82 = 8'd0;
reg    [15:0] k7ddrphy_bitslip8_r0 = 16'd0;
reg    [15:0] k7ddrphy_bitslip8_r1 = 16'd0;
reg     [2:0] k7ddrphy_bitslip8_value0 = 3'd7;
reg     [2:0] k7ddrphy_bitslip8_value1 = 3'd7;
reg     [7:0] k7ddrphy_bitslip90 = 8'd0;
wire    [7:0] k7ddrphy_bitslip91;
reg     [7:0] k7ddrphy_bitslip92 = 8'd0;
reg    [15:0] k7ddrphy_bitslip9_r0 = 16'd0;
reg    [15:0] k7ddrphy_bitslip9_r1 = 16'd0;
reg     [2:0] k7ddrphy_bitslip9_value0 = 3'd7;
reg     [2:0] k7ddrphy_bitslip9_value1 = 3'd7;
wire          k7ddrphy_cdly_inc_r;
reg           k7ddrphy_cdly_inc_re = 1'd0;
reg           k7ddrphy_cdly_inc_w = 1'd0;
reg           k7ddrphy_cdly_inc_we = 1'd0;
wire          k7ddrphy_cdly_rst_r;
reg           k7ddrphy_cdly_rst_re = 1'd0;
reg           k7ddrphy_cdly_rst_w = 1'd0;
reg           k7ddrphy_cdly_rst_we = 1'd0;
wire          k7ddrphy_dfi_p0_act_n;
wire   [14:0] k7ddrphy_dfi_p0_address;
wire    [2:0] k7ddrphy_dfi_p0_bank;
wire          k7ddrphy_dfi_p0_cas_n;
wire          k7ddrphy_dfi_p0_cke;
wire          k7ddrphy_dfi_p0_cs_n;
wire          k7ddrphy_dfi_p0_odt;
wire          k7ddrphy_dfi_p0_ras_n;
reg    [63:0] k7ddrphy_dfi_p0_rddata = 64'd0;
wire          k7ddrphy_dfi_p0_rddata_en;
wire          k7ddrphy_dfi_p0_rddata_valid;
wire          k7ddrphy_dfi_p0_reset_n;
wire          k7ddrphy_dfi_p0_we_n;
wire   [63:0] k7ddrphy_dfi_p0_wrdata;
wire          k7ddrphy_dfi_p0_wrdata_en;
wire    [7:0] k7ddrphy_dfi_p0_wrdata_mask;
wire          k7ddrphy_dfi_p1_act_n;
wire   [14:0] k7ddrphy_dfi_p1_address;
wire    [2:0] k7ddrphy_dfi_p1_bank;
wire          k7ddrphy_dfi_p1_cas_n;
wire          k7ddrphy_dfi_p1_cke;
wire          k7ddrphy_dfi_p1_cs_n;
wire          k7ddrphy_dfi_p1_odt;
wire          k7ddrphy_dfi_p1_ras_n;
reg    [63:0] k7ddrphy_dfi_p1_rddata = 64'd0;
wire          k7ddrphy_dfi_p1_rddata_en;
wire          k7ddrphy_dfi_p1_rddata_valid;
wire          k7ddrphy_dfi_p1_reset_n;
wire          k7ddrphy_dfi_p1_we_n;
wire   [63:0] k7ddrphy_dfi_p1_wrdata;
wire          k7ddrphy_dfi_p1_wrdata_en;
wire    [7:0] k7ddrphy_dfi_p1_wrdata_mask;
wire          k7ddrphy_dfi_p2_act_n;
wire   [14:0] k7ddrphy_dfi_p2_address;
wire    [2:0] k7ddrphy_dfi_p2_bank;
wire          k7ddrphy_dfi_p2_cas_n;
wire          k7ddrphy_dfi_p2_cke;
wire          k7ddrphy_dfi_p2_cs_n;
wire          k7ddrphy_dfi_p2_odt;
wire          k7ddrphy_dfi_p2_ras_n;
reg    [63:0] k7ddrphy_dfi_p2_rddata = 64'd0;
wire          k7ddrphy_dfi_p2_rddata_en;
wire          k7ddrphy_dfi_p2_rddata_valid;
wire          k7ddrphy_dfi_p2_reset_n;
wire          k7ddrphy_dfi_p2_we_n;
wire   [63:0] k7ddrphy_dfi_p2_wrdata;
wire          k7ddrphy_dfi_p2_wrdata_en;
wire    [7:0] k7ddrphy_dfi_p2_wrdata_mask;
wire          k7ddrphy_dfi_p3_act_n;
wire   [14:0] k7ddrphy_dfi_p3_address;
wire    [2:0] k7ddrphy_dfi_p3_bank;
wire          k7ddrphy_dfi_p3_cas_n;
wire          k7ddrphy_dfi_p3_cke;
wire          k7ddrphy_dfi_p3_cs_n;
wire          k7ddrphy_dfi_p3_odt;
wire          k7ddrphy_dfi_p3_ras_n;
reg    [63:0] k7ddrphy_dfi_p3_rddata = 64'd0;
wire          k7ddrphy_dfi_p3_rddata_en;
wire          k7ddrphy_dfi_p3_rddata_valid;
wire          k7ddrphy_dfi_p3_reset_n;
wire          k7ddrphy_dfi_p3_we_n;
wire   [63:0] k7ddrphy_dfi_p3_wrdata;
wire          k7ddrphy_dfi_p3_wrdata_en;
wire    [7:0] k7ddrphy_dfi_p3_wrdata_mask;
reg           k7ddrphy_dly_sel_re = 1'd0;
reg     [3:0] k7ddrphy_dly_sel_storage = 4'd0;
wire          k7ddrphy_dm_o_nodelay0;
wire          k7ddrphy_dm_o_nodelay1;
wire          k7ddrphy_dm_o_nodelay2;
wire          k7ddrphy_dm_o_nodelay3;
wire          k7ddrphy_dq_i_delayed0;
wire          k7ddrphy_dq_i_delayed1;
wire          k7ddrphy_dq_i_delayed10;
wire          k7ddrphy_dq_i_delayed11;
wire          k7ddrphy_dq_i_delayed12;
wire          k7ddrphy_dq_i_delayed13;
wire          k7ddrphy_dq_i_delayed14;
wire          k7ddrphy_dq_i_delayed15;
wire          k7ddrphy_dq_i_delayed16;
wire          k7ddrphy_dq_i_delayed17;
wire          k7ddrphy_dq_i_delayed18;
wire          k7ddrphy_dq_i_delayed19;
wire          k7ddrphy_dq_i_delayed2;
wire          k7ddrphy_dq_i_delayed20;
wire          k7ddrphy_dq_i_delayed21;
wire          k7ddrphy_dq_i_delayed22;
wire          k7ddrphy_dq_i_delayed23;
wire          k7ddrphy_dq_i_delayed24;
wire          k7ddrphy_dq_i_delayed25;
wire          k7ddrphy_dq_i_delayed26;
wire          k7ddrphy_dq_i_delayed27;
wire          k7ddrphy_dq_i_delayed28;
wire          k7ddrphy_dq_i_delayed29;
wire          k7ddrphy_dq_i_delayed3;
wire          k7ddrphy_dq_i_delayed30;
wire          k7ddrphy_dq_i_delayed31;
wire          k7ddrphy_dq_i_delayed4;
wire          k7ddrphy_dq_i_delayed5;
wire          k7ddrphy_dq_i_delayed6;
wire          k7ddrphy_dq_i_delayed7;
wire          k7ddrphy_dq_i_delayed8;
wire          k7ddrphy_dq_i_delayed9;
wire          k7ddrphy_dq_i_nodelay0;
wire          k7ddrphy_dq_i_nodelay1;
wire          k7ddrphy_dq_i_nodelay10;
wire          k7ddrphy_dq_i_nodelay11;
wire          k7ddrphy_dq_i_nodelay12;
wire          k7ddrphy_dq_i_nodelay13;
wire          k7ddrphy_dq_i_nodelay14;
wire          k7ddrphy_dq_i_nodelay15;
wire          k7ddrphy_dq_i_nodelay16;
wire          k7ddrphy_dq_i_nodelay17;
wire          k7ddrphy_dq_i_nodelay18;
wire          k7ddrphy_dq_i_nodelay19;
wire          k7ddrphy_dq_i_nodelay2;
wire          k7ddrphy_dq_i_nodelay20;
wire          k7ddrphy_dq_i_nodelay21;
wire          k7ddrphy_dq_i_nodelay22;
wire          k7ddrphy_dq_i_nodelay23;
wire          k7ddrphy_dq_i_nodelay24;
wire          k7ddrphy_dq_i_nodelay25;
wire          k7ddrphy_dq_i_nodelay26;
wire          k7ddrphy_dq_i_nodelay27;
wire          k7ddrphy_dq_i_nodelay28;
wire          k7ddrphy_dq_i_nodelay29;
wire          k7ddrphy_dq_i_nodelay3;
wire          k7ddrphy_dq_i_nodelay30;
wire          k7ddrphy_dq_i_nodelay31;
wire          k7ddrphy_dq_i_nodelay4;
wire          k7ddrphy_dq_i_nodelay5;
wire          k7ddrphy_dq_i_nodelay6;
wire          k7ddrphy_dq_i_nodelay7;
wire          k7ddrphy_dq_i_nodelay8;
wire          k7ddrphy_dq_i_nodelay9;
wire          k7ddrphy_dq_o_delayed0;
wire          k7ddrphy_dq_o_delayed1;
wire          k7ddrphy_dq_o_delayed10;
wire          k7ddrphy_dq_o_delayed11;
wire          k7ddrphy_dq_o_delayed12;
wire          k7ddrphy_dq_o_delayed13;
wire          k7ddrphy_dq_o_delayed14;
wire          k7ddrphy_dq_o_delayed15;
wire          k7ddrphy_dq_o_delayed16;
wire          k7ddrphy_dq_o_delayed17;
wire          k7ddrphy_dq_o_delayed18;
wire          k7ddrphy_dq_o_delayed19;
wire          k7ddrphy_dq_o_delayed2;
wire          k7ddrphy_dq_o_delayed20;
wire          k7ddrphy_dq_o_delayed21;
wire          k7ddrphy_dq_o_delayed22;
wire          k7ddrphy_dq_o_delayed23;
wire          k7ddrphy_dq_o_delayed24;
wire          k7ddrphy_dq_o_delayed25;
wire          k7ddrphy_dq_o_delayed26;
wire          k7ddrphy_dq_o_delayed27;
wire          k7ddrphy_dq_o_delayed28;
wire          k7ddrphy_dq_o_delayed29;
wire          k7ddrphy_dq_o_delayed3;
wire          k7ddrphy_dq_o_delayed30;
wire          k7ddrphy_dq_o_delayed31;
wire          k7ddrphy_dq_o_delayed4;
wire          k7ddrphy_dq_o_delayed5;
wire          k7ddrphy_dq_o_delayed6;
wire          k7ddrphy_dq_o_delayed7;
wire          k7ddrphy_dq_o_delayed8;
wire          k7ddrphy_dq_o_delayed9;
wire          k7ddrphy_dq_o_nodelay0;
wire          k7ddrphy_dq_o_nodelay1;
wire          k7ddrphy_dq_o_nodelay10;
wire          k7ddrphy_dq_o_nodelay11;
wire          k7ddrphy_dq_o_nodelay12;
wire          k7ddrphy_dq_o_nodelay13;
wire          k7ddrphy_dq_o_nodelay14;
wire          k7ddrphy_dq_o_nodelay15;
wire          k7ddrphy_dq_o_nodelay16;
wire          k7ddrphy_dq_o_nodelay17;
wire          k7ddrphy_dq_o_nodelay18;
wire          k7ddrphy_dq_o_nodelay19;
wire          k7ddrphy_dq_o_nodelay2;
wire          k7ddrphy_dq_o_nodelay20;
wire          k7ddrphy_dq_o_nodelay21;
wire          k7ddrphy_dq_o_nodelay22;
wire          k7ddrphy_dq_o_nodelay23;
wire          k7ddrphy_dq_o_nodelay24;
wire          k7ddrphy_dq_o_nodelay25;
wire          k7ddrphy_dq_o_nodelay26;
wire          k7ddrphy_dq_o_nodelay27;
wire          k7ddrphy_dq_o_nodelay28;
wire          k7ddrphy_dq_o_nodelay29;
wire          k7ddrphy_dq_o_nodelay3;
wire          k7ddrphy_dq_o_nodelay30;
wire          k7ddrphy_dq_o_nodelay31;
wire          k7ddrphy_dq_o_nodelay4;
wire          k7ddrphy_dq_o_nodelay5;
wire          k7ddrphy_dq_o_nodelay6;
wire          k7ddrphy_dq_o_nodelay7;
wire          k7ddrphy_dq_o_nodelay8;
wire          k7ddrphy_dq_o_nodelay9;
wire          k7ddrphy_dq_oe;
wire          k7ddrphy_dq_oe_delay_tappeddelayline;
reg           k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
reg           k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
wire          k7ddrphy_dq_t0;
wire          k7ddrphy_dq_t1;
wire          k7ddrphy_dq_t10;
wire          k7ddrphy_dq_t11;
wire          k7ddrphy_dq_t12;
wire          k7ddrphy_dq_t13;
wire          k7ddrphy_dq_t14;
wire          k7ddrphy_dq_t15;
wire          k7ddrphy_dq_t16;
wire          k7ddrphy_dq_t17;
wire          k7ddrphy_dq_t18;
wire          k7ddrphy_dq_t19;
wire          k7ddrphy_dq_t2;
wire          k7ddrphy_dq_t20;
wire          k7ddrphy_dq_t21;
wire          k7ddrphy_dq_t22;
wire          k7ddrphy_dq_t23;
wire          k7ddrphy_dq_t24;
wire          k7ddrphy_dq_t25;
wire          k7ddrphy_dq_t26;
wire          k7ddrphy_dq_t27;
wire          k7ddrphy_dq_t28;
wire          k7ddrphy_dq_t29;
wire          k7ddrphy_dq_t3;
wire          k7ddrphy_dq_t30;
wire          k7ddrphy_dq_t31;
wire          k7ddrphy_dq_t4;
wire          k7ddrphy_dq_t5;
wire          k7ddrphy_dq_t6;
wire          k7ddrphy_dq_t7;
wire          k7ddrphy_dq_t8;
wire          k7ddrphy_dq_t9;
wire          k7ddrphy_dqs_o_delayed0;
wire          k7ddrphy_dqs_o_delayed1;
wire          k7ddrphy_dqs_o_delayed2;
wire          k7ddrphy_dqs_o_delayed3;
wire          k7ddrphy_dqs_o_no_delay0;
wire          k7ddrphy_dqs_o_no_delay1;
wire          k7ddrphy_dqs_o_no_delay2;
wire          k7ddrphy_dqs_o_no_delay3;
reg           k7ddrphy_dqs_oe = 1'd0;
wire          k7ddrphy_dqs_oe_delay_tappeddelayline;
reg           k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
reg           k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
wire          k7ddrphy_dqs_postamble;
wire          k7ddrphy_dqs_preamble;
wire          k7ddrphy_dqs_t0;
wire          k7ddrphy_dqs_t1;
wire          k7ddrphy_dqs_t2;
wire          k7ddrphy_dqs_t3;
reg           k7ddrphy_dqspattern0 = 1'd0;
reg           k7ddrphy_dqspattern1 = 1'd0;
reg     [7:0] k7ddrphy_dqspattern_o = 8'd0;
reg           k7ddrphy_half_sys8x_taps_re = 1'd0;
reg     [4:0] k7ddrphy_half_sys8x_taps_storage = 5'd4;
wire          k7ddrphy_oq0;
wire          k7ddrphy_oq1;
wire          k7ddrphy_oq10;
wire          k7ddrphy_oq11;
wire          k7ddrphy_oq12;
wire          k7ddrphy_oq13;
wire          k7ddrphy_oq14;
wire          k7ddrphy_oq15;
wire          k7ddrphy_oq16;
wire          k7ddrphy_oq17;
wire          k7ddrphy_oq18;
wire          k7ddrphy_oq19;
wire          k7ddrphy_oq2;
wire          k7ddrphy_oq20;
wire          k7ddrphy_oq21;
wire          k7ddrphy_oq22;
wire          k7ddrphy_oq23;
wire          k7ddrphy_oq24;
wire          k7ddrphy_oq3;
wire          k7ddrphy_oq4;
wire          k7ddrphy_oq5;
wire          k7ddrphy_oq6;
wire          k7ddrphy_oq7;
wire          k7ddrphy_oq8;
wire          k7ddrphy_oq9;
wire    [2:0] k7ddrphy_pads_ba;
reg           k7ddrphy_rddata_en_tappeddelayline0 = 1'd0;
reg           k7ddrphy_rddata_en_tappeddelayline1 = 1'd0;
reg           k7ddrphy_rddata_en_tappeddelayline2 = 1'd0;
reg           k7ddrphy_rddata_en_tappeddelayline3 = 1'd0;
reg           k7ddrphy_rddata_en_tappeddelayline4 = 1'd0;
reg           k7ddrphy_rddata_en_tappeddelayline5 = 1'd0;
reg           k7ddrphy_rddata_en_tappeddelayline6 = 1'd0;
reg           k7ddrphy_rddata_en_tappeddelayline7 = 1'd0;
reg           k7ddrphy_rddata_en_tappeddelayline8 = 1'd0;
wire          k7ddrphy_rdly_dq_bitslip_r;
reg           k7ddrphy_rdly_dq_bitslip_re = 1'd0;
wire          k7ddrphy_rdly_dq_bitslip_rst_r;
reg           k7ddrphy_rdly_dq_bitslip_rst_re = 1'd0;
reg           k7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
reg           k7ddrphy_rdly_dq_bitslip_rst_we = 1'd0;
reg           k7ddrphy_rdly_dq_bitslip_w = 1'd0;
reg           k7ddrphy_rdly_dq_bitslip_we = 1'd0;
wire          k7ddrphy_rdly_dq_inc_r;
reg           k7ddrphy_rdly_dq_inc_re = 1'd0;
reg           k7ddrphy_rdly_dq_inc_w = 1'd0;
reg           k7ddrphy_rdly_dq_inc_we = 1'd0;
wire          k7ddrphy_rdly_dq_rst_r;
reg           k7ddrphy_rdly_dq_rst_re = 1'd0;
reg           k7ddrphy_rdly_dq_rst_w = 1'd0;
reg           k7ddrphy_rdly_dq_rst_we = 1'd0;
reg           k7ddrphy_rdphase_re = 1'd0;
reg     [1:0] k7ddrphy_rdphase_storage = 2'd0;
reg           k7ddrphy_rst_re = 1'd0;
reg           k7ddrphy_rst_storage = 1'd0;
wire          k7ddrphy_sd_clk_se_delayed;
wire          k7ddrphy_sd_clk_se_nodelay;
wire          k7ddrphy_wdly_dq_bitslip_r;
reg           k7ddrphy_wdly_dq_bitslip_re = 1'd0;
wire          k7ddrphy_wdly_dq_bitslip_rst_r;
reg           k7ddrphy_wdly_dq_bitslip_rst_re = 1'd0;
reg           k7ddrphy_wdly_dq_bitslip_rst_w = 1'd0;
reg           k7ddrphy_wdly_dq_bitslip_rst_we = 1'd0;
reg           k7ddrphy_wdly_dq_bitslip_w = 1'd0;
reg           k7ddrphy_wdly_dq_bitslip_we = 1'd0;
wire          k7ddrphy_wdly_dq_inc_r;
reg           k7ddrphy_wdly_dq_inc_re = 1'd0;
reg           k7ddrphy_wdly_dq_inc_w = 1'd0;
reg           k7ddrphy_wdly_dq_inc_we = 1'd0;
wire          k7ddrphy_wdly_dq_rst_r;
reg           k7ddrphy_wdly_dq_rst_re = 1'd0;
reg           k7ddrphy_wdly_dq_rst_w = 1'd0;
reg           k7ddrphy_wdly_dq_rst_we = 1'd0;
wire          k7ddrphy_wdly_dqs_inc_r;
reg           k7ddrphy_wdly_dqs_inc_re = 1'd0;
reg           k7ddrphy_wdly_dqs_inc_w = 1'd0;
reg           k7ddrphy_wdly_dqs_inc_we = 1'd0;
wire          k7ddrphy_wdly_dqs_rst_r;
reg           k7ddrphy_wdly_dqs_rst_re = 1'd0;
reg           k7ddrphy_wdly_dqs_rst_w = 1'd0;
reg           k7ddrphy_wdly_dqs_rst_we = 1'd0;
reg           k7ddrphy_wlevel_en_re = 1'd0;
reg           k7ddrphy_wlevel_en_storage = 1'd0;
wire          k7ddrphy_wlevel_strobe_r;
reg           k7ddrphy_wlevel_strobe_re = 1'd0;
reg           k7ddrphy_wlevel_strobe_w = 1'd0;
reg           k7ddrphy_wlevel_strobe_we = 1'd0;
reg           k7ddrphy_wrdata_en_tappeddelayline0 = 1'd0;
reg           k7ddrphy_wrdata_en_tappeddelayline1 = 1'd0;
reg           k7ddrphy_wrdata_en_tappeddelayline2 = 1'd0;
reg           k7ddrphy_wrphase_re = 1'd0;
reg     [1:0] k7ddrphy_wrphase_storage = -2'd1;
reg           litedramcore_aborted = 1'd0;
reg           litedramcore_aborted_litedramwishbone2native0_next_value = 1'd0;
reg           litedramcore_aborted_litedramwishbone2native0_next_value_ce = 1'd0;
reg     [2:0] litedramcore_adr_offset_r = 3'd0;
reg     [3:0] litedramcore_bankmachine0_next_state = 4'd0;
reg     [3:0] litedramcore_bankmachine0_state = 4'd0;
reg     [3:0] litedramcore_bankmachine1_next_state = 4'd0;
reg     [3:0] litedramcore_bankmachine1_state = 4'd0;
reg     [3:0] litedramcore_bankmachine2_next_state = 4'd0;
reg     [3:0] litedramcore_bankmachine2_state = 4'd0;
reg     [3:0] litedramcore_bankmachine3_next_state = 4'd0;
reg     [3:0] litedramcore_bankmachine3_state = 4'd0;
reg     [3:0] litedramcore_bankmachine4_next_state = 4'd0;
reg     [3:0] litedramcore_bankmachine4_state = 4'd0;
reg     [3:0] litedramcore_bankmachine5_next_state = 4'd0;
reg     [3:0] litedramcore_bankmachine5_state = 4'd0;
reg     [3:0] litedramcore_bankmachine6_next_state = 4'd0;
reg     [3:0] litedramcore_bankmachine6_state = 4'd0;
reg     [3:0] litedramcore_bankmachine7_next_state = 4'd0;
reg     [3:0] litedramcore_bankmachine7_state = 4'd0;
wire          litedramcore_bus_error;
reg    [31:0] litedramcore_bus_errors = 32'd0;
reg           litedramcore_bus_errors_re = 1'd0;
wire   [31:0] litedramcore_bus_errors_status;
wire          litedramcore_bus_errors_we;
wire          litedramcore_cpu_rst;
wire          litedramcore_data_port_adr;
wire  [255:0] litedramcore_data_port_dat_r;
reg   [255:0] litedramcore_data_port_dat_w = 256'd0;
reg    [31:0] litedramcore_data_port_we = 32'd0;
wire          litedramcore_dbus_ack;
wire   [29:0] litedramcore_dbus_adr;
wire    [1:0] litedramcore_dbus_bte;
wire    [2:0] litedramcore_dbus_cti;
wire          litedramcore_dbus_cyc;
wire   [31:0] litedramcore_dbus_dat_r;
wire   [31:0] litedramcore_dbus_dat_w;
wire          litedramcore_dbus_err;
wire    [3:0] litedramcore_dbus_sel;
wire          litedramcore_dbus_stb;
wire          litedramcore_dbus_we;
reg           litedramcore_en_re = 1'd0;
reg           litedramcore_en_storage = 1'd0;
reg           litedramcore_enable_re = 1'd0;
reg           litedramcore_enable_storage = 1'd0;
wire          litedramcore_ibus_ack;
wire   [29:0] litedramcore_ibus_adr;
wire    [1:0] litedramcore_ibus_bte;
wire    [2:0] litedramcore_ibus_cti;
wire          litedramcore_ibus_cyc;
wire   [31:0] litedramcore_ibus_dat_r;
wire   [31:0] litedramcore_ibus_dat_w;
wire          litedramcore_ibus_err;
wire    [3:0] litedramcore_ibus_sel;
wire          litedramcore_ibus_stb;
wire          litedramcore_ibus_we;
reg           litedramcore_interface_ack = 1'd0;
wire   [26:0] litedramcore_interface_adr;
reg           litedramcore_interface_cyc = 1'd0;
reg   [255:0] litedramcore_interface_dat_r = 256'd0;
wire  [255:0] litedramcore_interface_dat_w;
wire   [31:0] litedramcore_interface_sel;
reg           litedramcore_interface_stb = 1'd0;
reg           litedramcore_interface_we = 1'd0;
reg    [31:0] litedramcore_interrupt = 32'd0;
wire          litedramcore_irq;
reg           litedramcore_is_ongoing = 1'd0;
wire   [13:0] litedramcore_litedramcore_adr;
reg           litedramcore_litedramcore_adr_burst = 1'd0;
wire   [31:0] litedramcore_litedramcore_dat_r;
reg           litedramcore_litedramcore_ram_bus_ack = 1'd0;
wire   [29:0] litedramcore_litedramcore_ram_bus_adr;
wire    [1:0] litedramcore_litedramcore_ram_bus_bte;
wire    [2:0] litedramcore_litedramcore_ram_bus_cti;
wire          litedramcore_litedramcore_ram_bus_cyc;
wire   [31:0] litedramcore_litedramcore_ram_bus_dat_r;
wire   [31:0] litedramcore_litedramcore_ram_bus_dat_w;
reg           litedramcore_litedramcore_ram_bus_err = 1'd0;
wire    [3:0] litedramcore_litedramcore_ram_bus_sel;
wire          litedramcore_litedramcore_ram_bus_stb;
wire          litedramcore_litedramcore_ram_bus_we;
reg           litedramcore_load_re = 1'd0;
reg    [31:0] litedramcore_load_storage = 32'd0;
reg           litedramcore_locked0 = 1'd0;
reg           litedramcore_locked1 = 1'd0;
reg           litedramcore_locked10 = 1'd0;
reg           litedramcore_locked11 = 1'd0;
reg           litedramcore_locked12 = 1'd0;
reg           litedramcore_locked13 = 1'd0;
reg           litedramcore_locked14 = 1'd0;
reg           litedramcore_locked15 = 1'd0;
reg           litedramcore_locked2 = 1'd0;
reg           litedramcore_locked3 = 1'd0;
reg           litedramcore_locked4 = 1'd0;
reg           litedramcore_locked5 = 1'd0;
reg           litedramcore_locked6 = 1'd0;
reg           litedramcore_locked7 = 1'd0;
reg           litedramcore_locked8 = 1'd0;
reg           litedramcore_locked9 = 1'd0;
reg     [3:0] litedramcore_multiplexer_next_state = 4'd0;
reg     [3:0] litedramcore_multiplexer_state = 4'd0;
reg           litedramcore_new_master_rdata_valid0 = 1'd0;
reg           litedramcore_new_master_rdata_valid1 = 1'd0;
reg           litedramcore_new_master_rdata_valid10 = 1'd0;
reg           litedramcore_new_master_rdata_valid11 = 1'd0;
reg           litedramcore_new_master_rdata_valid12 = 1'd0;
reg           litedramcore_new_master_rdata_valid13 = 1'd0;
reg           litedramcore_new_master_rdata_valid14 = 1'd0;
reg           litedramcore_new_master_rdata_valid15 = 1'd0;
reg           litedramcore_new_master_rdata_valid16 = 1'd0;
reg           litedramcore_new_master_rdata_valid17 = 1'd0;
reg           litedramcore_new_master_rdata_valid18 = 1'd0;
reg           litedramcore_new_master_rdata_valid19 = 1'd0;
reg           litedramcore_new_master_rdata_valid2 = 1'd0;
reg           litedramcore_new_master_rdata_valid3 = 1'd0;
reg           litedramcore_new_master_rdata_valid4 = 1'd0;
reg           litedramcore_new_master_rdata_valid5 = 1'd0;
reg           litedramcore_new_master_rdata_valid6 = 1'd0;
reg           litedramcore_new_master_rdata_valid7 = 1'd0;
reg           litedramcore_new_master_rdata_valid8 = 1'd0;
reg           litedramcore_new_master_rdata_valid9 = 1'd0;
reg           litedramcore_new_master_wdata_ready0 = 1'd0;
reg           litedramcore_new_master_wdata_ready1 = 1'd0;
reg           litedramcore_new_master_wdata_ready2 = 1'd0;
reg           litedramcore_new_master_wdata_ready3 = 1'd0;
reg     [1:0] litedramcore_next_state = 2'd0;
reg           litedramcore_pending_r = 1'd0;
reg           litedramcore_pending_re = 1'd0;
wire          litedramcore_pending_status;
wire          litedramcore_pending_we;
wire          litedramcore_port_cmd_last;
wire   [24:0] litedramcore_port_cmd_payload_addr;
wire          litedramcore_port_cmd_payload_we;
wire          litedramcore_port_cmd_ready;
reg           litedramcore_port_cmd_valid = 1'd0;
wire          litedramcore_port_flush;
wire  [255:0] litedramcore_port_rdata_payload_data;
wire          litedramcore_port_rdata_ready;
wire          litedramcore_port_rdata_valid;
wire  [255:0] litedramcore_port_wdata_payload_data;
wire   [31:0] litedramcore_port_wdata_payload_we;
wire          litedramcore_port_wdata_ready;
reg           litedramcore_port_wdata_valid = 1'd0;
wire   [10:0] litedramcore_ram_adr;
reg           litedramcore_ram_adr_burst = 1'd0;
reg           litedramcore_ram_bus_ram_bus_ack = 1'd0;
wire   [29:0] litedramcore_ram_bus_ram_bus_adr;
wire    [1:0] litedramcore_ram_bus_ram_bus_bte;
wire    [2:0] litedramcore_ram_bus_ram_bus_cti;
wire          litedramcore_ram_bus_ram_bus_cyc;
wire   [31:0] litedramcore_ram_bus_ram_bus_dat_r;
wire   [31:0] litedramcore_ram_bus_ram_bus_dat_w;
reg           litedramcore_ram_bus_ram_bus_err = 1'd0;
wire    [3:0] litedramcore_ram_bus_ram_bus_sel;
wire          litedramcore_ram_bus_ram_bus_stb;
wire          litedramcore_ram_bus_ram_bus_we;
wire   [31:0] litedramcore_ram_dat_r;
wire   [31:0] litedramcore_ram_dat_w;
reg     [3:0] litedramcore_ram_we = 4'd0;
reg     [1:0] litedramcore_refresher_next_state = 2'd0;
reg     [1:0] litedramcore_refresher_state = 2'd0;
reg           litedramcore_reload_re = 1'd0;
reg    [31:0] litedramcore_reload_storage = 32'd0;
wire          litedramcore_reset;
reg           litedramcore_reset_re = 1'd0;
reg     [1:0] litedramcore_reset_storage = 2'd0;
wire          litedramcore_roundrobin0_ce;
reg           litedramcore_roundrobin0_grant = 1'd0;
wire    [1:0] litedramcore_roundrobin0_request;
wire          litedramcore_roundrobin1_ce;
reg           litedramcore_roundrobin1_grant = 1'd0;
wire    [1:0] litedramcore_roundrobin1_request;
wire          litedramcore_roundrobin2_ce;
reg           litedramcore_roundrobin2_grant = 1'd0;
wire    [1:0] litedramcore_roundrobin2_request;
wire          litedramcore_roundrobin3_ce;
reg           litedramcore_roundrobin3_grant = 1'd0;
wire    [1:0] litedramcore_roundrobin3_request;
wire          litedramcore_roundrobin4_ce;
reg           litedramcore_roundrobin4_grant = 1'd0;
wire    [1:0] litedramcore_roundrobin4_request;
wire          litedramcore_roundrobin5_ce;
reg           litedramcore_roundrobin5_grant = 1'd0;
wire    [1:0] litedramcore_roundrobin5_request;
wire          litedramcore_roundrobin6_ce;
reg           litedramcore_roundrobin6_grant = 1'd0;
wire    [1:0] litedramcore_roundrobin6_request;
wire          litedramcore_roundrobin7_ce;
reg           litedramcore_roundrobin7_grant = 1'd0;
wire    [1:0] litedramcore_roundrobin7_request;
reg           litedramcore_scratch_re = 1'd0;
reg    [31:0] litedramcore_scratch_storage = 32'd305419896;
reg           litedramcore_sdram_bankmachine0_auto_precharge = 1'd0;
reg    [14:0] litedramcore_sdram_bankmachine0_cmd_payload_a = 15'd0;
wire    [2:0] litedramcore_sdram_bankmachine0_cmd_payload_ba;
reg           litedramcore_sdram_bankmachine0_cmd_payload_cas = 1'd0;
reg           litedramcore_sdram_bankmachine0_cmd_payload_is_cmd = 1'd0;
reg           litedramcore_sdram_bankmachine0_cmd_payload_is_read = 1'd0;
reg           litedramcore_sdram_bankmachine0_cmd_payload_is_write = 1'd0;
reg           litedramcore_sdram_bankmachine0_cmd_payload_ras = 1'd0;
reg           litedramcore_sdram_bankmachine0_cmd_payload_we = 1'd0;
reg           litedramcore_sdram_bankmachine0_cmd_ready = 1'd0;
reg           litedramcore_sdram_bankmachine0_cmd_valid = 1'd0;
reg     [3:0] litedramcore_sdram_bankmachine0_consume = 4'd0;
wire          litedramcore_sdram_bankmachine0_do_read;
wire          litedramcore_sdram_bankmachine0_fifo_in_first;
wire          litedramcore_sdram_bankmachine0_fifo_in_last;
wire   [21:0] litedramcore_sdram_bankmachine0_fifo_in_payload_addr;
wire          litedramcore_sdram_bankmachine0_fifo_in_payload_we;
wire          litedramcore_sdram_bankmachine0_fifo_out_first;
wire          litedramcore_sdram_bankmachine0_fifo_out_last;
wire   [21:0] litedramcore_sdram_bankmachine0_fifo_out_payload_addr;
wire          litedramcore_sdram_bankmachine0_fifo_out_payload_we;
reg     [4:0] litedramcore_sdram_bankmachine0_level = 5'd0;
wire          litedramcore_sdram_bankmachine0_pipe_valid_sink_first;
wire          litedramcore_sdram_bankmachine0_pipe_valid_sink_last;
wire   [21:0] litedramcore_sdram_bankmachine0_pipe_valid_sink_payload_addr;
wire          litedramcore_sdram_bankmachine0_pipe_valid_sink_payload_we;
wire          litedramcore_sdram_bankmachine0_pipe_valid_sink_ready;
wire          litedramcore_sdram_bankmachine0_pipe_valid_sink_valid;
reg           litedramcore_sdram_bankmachine0_pipe_valid_source_first = 1'd0;
reg           litedramcore_sdram_bankmachine0_pipe_valid_source_last = 1'd0;
reg    [21:0] litedramcore_sdram_bankmachine0_pipe_valid_source_payload_addr = 22'd0;
reg           litedramcore_sdram_bankmachine0_pipe_valid_source_payload_we = 1'd0;
wire          litedramcore_sdram_bankmachine0_pipe_valid_source_ready;
reg           litedramcore_sdram_bankmachine0_pipe_valid_source_valid = 1'd0;
reg     [3:0] litedramcore_sdram_bankmachine0_produce = 4'd0;
wire    [3:0] litedramcore_sdram_bankmachine0_rdport_adr;
wire   [24:0] litedramcore_sdram_bankmachine0_rdport_dat_r;
reg           litedramcore_sdram_bankmachine0_refresh_gnt = 1'd0;
wire          litedramcore_sdram_bankmachine0_refresh_req;
reg           litedramcore_sdram_bankmachine0_replace = 1'd0;
wire   [21:0] litedramcore_sdram_bankmachine0_req_addr;
wire          litedramcore_sdram_bankmachine0_req_lock;
reg           litedramcore_sdram_bankmachine0_req_rdata_valid = 1'd0;
wire          litedramcore_sdram_bankmachine0_req_ready;
wire          litedramcore_sdram_bankmachine0_req_valid;
reg           litedramcore_sdram_bankmachine0_req_wdata_ready = 1'd0;
wire          litedramcore_sdram_bankmachine0_req_we;
reg    [14:0] litedramcore_sdram_bankmachine0_row = 15'd0;
reg           litedramcore_sdram_bankmachine0_row_close = 1'd0;
reg           litedramcore_sdram_bankmachine0_row_col_n_addr_sel = 1'd0;
wire          litedramcore_sdram_bankmachine0_row_hit;
reg           litedramcore_sdram_bankmachine0_row_open = 1'd0;
reg           litedramcore_sdram_bankmachine0_row_opened = 1'd0;
reg           litedramcore_sdram_bankmachine0_sink_first = 1'd0;
reg           litedramcore_sdram_bankmachine0_sink_last = 1'd0;
wire   [21:0] litedramcore_sdram_bankmachine0_sink_payload_addr;
wire          litedramcore_sdram_bankmachine0_sink_payload_we;
wire          litedramcore_sdram_bankmachine0_sink_ready;
wire          litedramcore_sdram_bankmachine0_sink_sink_first;
wire          litedramcore_sdram_bankmachine0_sink_sink_last;
wire   [21:0] litedramcore_sdram_bankmachine0_sink_sink_payload_addr;
wire          litedramcore_sdram_bankmachine0_sink_sink_payload_we;
wire          litedramcore_sdram_bankmachine0_sink_sink_ready;
wire          litedramcore_sdram_bankmachine0_sink_sink_valid;
wire          litedramcore_sdram_bankmachine0_sink_valid;
wire          litedramcore_sdram_bankmachine0_source_first;
wire          litedramcore_sdram_bankmachine0_source_last;
wire   [21:0] litedramcore_sdram_bankmachine0_source_payload_addr;
wire          litedramcore_sdram_bankmachine0_source_payload_we;
wire          litedramcore_sdram_bankmachine0_source_ready;
wire          litedramcore_sdram_bankmachine0_source_source_first;
wire          litedramcore_sdram_bankmachine0_source_source_last;
wire   [21:0] litedramcore_sdram_bankmachine0_source_source_payload_addr;
wire          litedramcore_sdram_bankmachine0_source_source_payload_we;
wire          litedramcore_sdram_bankmachine0_source_source_ready;
wire          litedramcore_sdram_bankmachine0_source_source_valid;
wire          litedramcore_sdram_bankmachine0_source_valid;
wire   [24:0] litedramcore_sdram_bankmachine0_syncfifo0_din;
wire   [24:0] litedramcore_sdram_bankmachine0_syncfifo0_dout;
wire          litedramcore_sdram_bankmachine0_syncfifo0_re;
wire          litedramcore_sdram_bankmachine0_syncfifo0_readable;
wire          litedramcore_sdram_bankmachine0_syncfifo0_we;
wire          litedramcore_sdram_bankmachine0_syncfifo0_writable;
reg     [2:0] litedramcore_sdram_bankmachine0_trascon_count = 3'd0;
(* dont_touch = "true" *)
reg           litedramcore_sdram_bankmachine0_trascon_ready = 1'd0;
wire          litedramcore_sdram_bankmachine0_trascon_valid;
reg     [3:0] litedramcore_sdram_bankmachine0_trccon_count = 4'd0;
(* dont_touch = "true" *)
reg           litedramcore_sdram_bankmachine0_trccon_ready = 1'd0;
wire          litedramcore_sdram_bankmachine0_trccon_valid;
reg     [2:0] litedramcore_sdram_bankmachine0_twtpcon_count = 3'd0;
(* dont_touch = "true" *)
reg           litedramcore_sdram_bankmachine0_twtpcon_ready = 1'd0;
wire          litedramcore_sdram_bankmachine0_twtpcon_valid;
reg     [3:0] litedramcore_sdram_bankmachine0_wrport_adr = 4'd0;
wire   [24:0] litedramcore_sdram_bankmachine0_wrport_dat_r;
wire   [24:0] litedramcore_sdram_bankmachine0_wrport_dat_w;
wire          litedramcore_sdram_bankmachine0_wrport_we;
reg           litedramcore_sdram_bankmachine1_auto_precharge = 1'd0;
reg    [14:0] litedramcore_sdram_bankmachine1_cmd_payload_a = 15'd0;
wire    [2:0] litedramcore_sdram_bankmachine1_cmd_payload_ba;
reg           litedramcore_sdram_bankmachine1_cmd_payload_cas = 1'd0;
reg           litedramcore_sdram_bankmachine1_cmd_payload_is_cmd = 1'd0;
reg           litedramcore_sdram_bankmachine1_cmd_payload_is_read = 1'd0;
reg           litedramcore_sdram_bankmachine1_cmd_payload_is_write = 1'd0;
reg           litedramcore_sdram_bankmachine1_cmd_payload_ras = 1'd0;
reg           litedramcore_sdram_bankmachine1_cmd_payload_we = 1'd0;
reg           litedramcore_sdram_bankmachine1_cmd_ready = 1'd0;
reg           litedramcore_sdram_bankmachine1_cmd_valid = 1'd0;
reg     [3:0] litedramcore_sdram_bankmachine1_consume = 4'd0;
wire          litedramcore_sdram_bankmachine1_do_read;
wire          litedramcore_sdram_bankmachine1_fifo_in_first;
wire          litedramcore_sdram_bankmachine1_fifo_in_last;
wire   [21:0] litedramcore_sdram_bankmachine1_fifo_in_payload_addr;
wire          litedramcore_sdram_bankmachine1_fifo_in_payload_we;
wire          litedramcore_sdram_bankmachine1_fifo_out_first;
wire          litedramcore_sdram_bankmachine1_fifo_out_last;
wire   [21:0] litedramcore_sdram_bankmachine1_fifo_out_payload_addr;
wire          litedramcore_sdram_bankmachine1_fifo_out_payload_we;
reg     [4:0] litedramcore_sdram_bankmachine1_level = 5'd0;
wire          litedramcore_sdram_bankmachine1_pipe_valid_sink_first;
wire          litedramcore_sdram_bankmachine1_pipe_valid_sink_last;
wire   [21:0] litedramcore_sdram_bankmachine1_pipe_valid_sink_payload_addr;
wire          litedramcore_sdram_bankmachine1_pipe_valid_sink_payload_we;
wire          litedramcore_sdram_bankmachine1_pipe_valid_sink_ready;
wire          litedramcore_sdram_bankmachine1_pipe_valid_sink_valid;
reg           litedramcore_sdram_bankmachine1_pipe_valid_source_first = 1'd0;
reg           litedramcore_sdram_bankmachine1_pipe_valid_source_last = 1'd0;
reg    [21:0] litedramcore_sdram_bankmachine1_pipe_valid_source_payload_addr = 22'd0;
reg           litedramcore_sdram_bankmachine1_pipe_valid_source_payload_we = 1'd0;
wire          litedramcore_sdram_bankmachine1_pipe_valid_source_ready;
reg           litedramcore_sdram_bankmachine1_pipe_valid_source_valid = 1'd0;
reg     [3:0] litedramcore_sdram_bankmachine1_produce = 4'd0;
wire    [3:0] litedramcore_sdram_bankmachine1_rdport_adr;
wire   [24:0] litedramcore_sdram_bankmachine1_rdport_dat_r;
reg           litedramcore_sdram_bankmachine1_refresh_gnt = 1'd0;
wire          litedramcore_sdram_bankmachine1_refresh_req;
reg           litedramcore_sdram_bankmachine1_replace = 1'd0;
wire   [21:0] litedramcore_sdram_bankmachine1_req_addr;
wire          litedramcore_sdram_bankmachine1_req_lock;
reg           litedramcore_sdram_bankmachine1_req_rdata_valid = 1'd0;
wire          litedramcore_sdram_bankmachine1_req_ready;
wire          litedramcore_sdram_bankmachine1_req_valid;
reg           litedramcore_sdram_bankmachine1_req_wdata_ready = 1'd0;
wire          litedramcore_sdram_bankmachine1_req_we;
reg    [14:0] litedramcore_sdram_bankmachine1_row = 15'd0;
reg           litedramcore_sdram_bankmachine1_row_close = 1'd0;
reg           litedramcore_sdram_bankmachine1_row_col_n_addr_sel = 1'd0;
wire          litedramcore_sdram_bankmachine1_row_hit;
reg           litedramcore_sdram_bankmachine1_row_open = 1'd0;
reg           litedramcore_sdram_bankmachine1_row_opened = 1'd0;
reg           litedramcore_sdram_bankmachine1_sink_first = 1'd0;
reg           litedramcore_sdram_bankmachine1_sink_last = 1'd0;
wire   [21:0] litedramcore_sdram_bankmachine1_sink_payload_addr;
wire          litedramcore_sdram_bankmachine1_sink_payload_we;
wire          litedramcore_sdram_bankmachine1_sink_ready;
wire          litedramcore_sdram_bankmachine1_sink_sink_first;
wire          litedramcore_sdram_bankmachine1_sink_sink_last;
wire   [21:0] litedramcore_sdram_bankmachine1_sink_sink_payload_addr;
wire          litedramcore_sdram_bankmachine1_sink_sink_payload_we;
wire          litedramcore_sdram_bankmachine1_sink_sink_ready;
wire          litedramcore_sdram_bankmachine1_sink_sink_valid;
wire          litedramcore_sdram_bankmachine1_sink_valid;
wire          litedramcore_sdram_bankmachine1_source_first;
wire          litedramcore_sdram_bankmachine1_source_last;
wire   [21:0] litedramcore_sdram_bankmachine1_source_payload_addr;
wire          litedramcore_sdram_bankmachine1_source_payload_we;
wire          litedramcore_sdram_bankmachine1_source_ready;
wire          litedramcore_sdram_bankmachine1_source_source_first;
wire          litedramcore_sdram_bankmachine1_source_source_last;
wire   [21:0] litedramcore_sdram_bankmachine1_source_source_payload_addr;
wire          litedramcore_sdram_bankmachine1_source_source_payload_we;
wire          litedramcore_sdram_bankmachine1_source_source_ready;
wire          litedramcore_sdram_bankmachine1_source_source_valid;
wire          litedramcore_sdram_bankmachine1_source_valid;
wire   [24:0] litedramcore_sdram_bankmachine1_syncfifo1_din;
wire   [24:0] litedramcore_sdram_bankmachine1_syncfifo1_dout;
wire          litedramcore_sdram_bankmachine1_syncfifo1_re;
wire          litedramcore_sdram_bankmachine1_syncfifo1_readable;
wire          litedramcore_sdram_bankmachine1_syncfifo1_we;
wire          litedramcore_sdram_bankmachine1_syncfifo1_writable;
reg     [2:0] litedramcore_sdram_bankmachine1_trascon_count = 3'd0;
(* dont_touch = "true" *)
reg           litedramcore_sdram_bankmachine1_trascon_ready = 1'd0;
wire          litedramcore_sdram_bankmachine1_trascon_valid;
reg     [3:0] litedramcore_sdram_bankmachine1_trccon_count = 4'd0;
(* dont_touch = "true" *)
reg           litedramcore_sdram_bankmachine1_trccon_ready = 1'd0;
wire          litedramcore_sdram_bankmachine1_trccon_valid;
reg     [2:0] litedramcore_sdram_bankmachine1_twtpcon_count = 3'd0;
(* dont_touch = "true" *)
reg           litedramcore_sdram_bankmachine1_twtpcon_ready = 1'd0;
wire          litedramcore_sdram_bankmachine1_twtpcon_valid;
reg     [3:0] litedramcore_sdram_bankmachine1_wrport_adr = 4'd0;
wire   [24:0] litedramcore_sdram_bankmachine1_wrport_dat_r;
wire   [24:0] litedramcore_sdram_bankmachine1_wrport_dat_w;
wire          litedramcore_sdram_bankmachine1_wrport_we;
reg           litedramcore_sdram_bankmachine2_auto_precharge = 1'd0;
reg    [14:0] litedramcore_sdram_bankmachine2_cmd_payload_a = 15'd0;
wire    [2:0] litedramcore_sdram_bankmachine2_cmd_payload_ba;
reg           litedramcore_sdram_bankmachine2_cmd_payload_cas = 1'd0;
reg           litedramcore_sdram_bankmachine2_cmd_payload_is_cmd = 1'd0;
reg           litedramcore_sdram_bankmachine2_cmd_payload_is_read = 1'd0;
reg           litedramcore_sdram_bankmachine2_cmd_payload_is_write = 1'd0;
reg           litedramcore_sdram_bankmachine2_cmd_payload_ras = 1'd0;
reg           litedramcore_sdram_bankmachine2_cmd_payload_we = 1'd0;
reg           litedramcore_sdram_bankmachine2_cmd_ready = 1'd0;
reg           litedramcore_sdram_bankmachine2_cmd_valid = 1'd0;
reg     [3:0] litedramcore_sdram_bankmachine2_consume = 4'd0;
wire          litedramcore_sdram_bankmachine2_do_read;
wire          litedramcore_sdram_bankmachine2_fifo_in_first;
wire          litedramcore_sdram_bankmachine2_fifo_in_last;
wire   [21:0] litedramcore_sdram_bankmachine2_fifo_in_payload_addr;
wire          litedramcore_sdram_bankmachine2_fifo_in_payload_we;
wire          litedramcore_sdram_bankmachine2_fifo_out_first;
wire          litedramcore_sdram_bankmachine2_fifo_out_last;
wire   [21:0] litedramcore_sdram_bankmachine2_fifo_out_payload_addr;
wire          litedramcore_sdram_bankmachine2_fifo_out_payload_we;
reg     [4:0] litedramcore_sdram_bankmachine2_level = 5'd0;
wire          litedramcore_sdram_bankmachine2_pipe_valid_sink_first;
wire          litedramcore_sdram_bankmachine2_pipe_valid_sink_last;
wire   [21:0] litedramcore_sdram_bankmachine2_pipe_valid_sink_payload_addr;
wire          litedramcore_sdram_bankmachine2_pipe_valid_sink_payload_we;
wire          litedramcore_sdram_bankmachine2_pipe_valid_sink_ready;
wire          litedramcore_sdram_bankmachine2_pipe_valid_sink_valid;
reg           litedramcore_sdram_bankmachine2_pipe_valid_source_first = 1'd0;
reg           litedramcore_sdram_bankmachine2_pipe_valid_source_last = 1'd0;
reg    [21:0] litedramcore_sdram_bankmachine2_pipe_valid_source_payload_addr = 22'd0;
reg           litedramcore_sdram_bankmachine2_pipe_valid_source_payload_we = 1'd0;
wire          litedramcore_sdram_bankmachine2_pipe_valid_source_ready;
reg           litedramcore_sdram_bankmachine2_pipe_valid_source_valid = 1'd0;
reg     [3:0] litedramcore_sdram_bankmachine2_produce = 4'd0;
wire    [3:0] litedramcore_sdram_bankmachine2_rdport_adr;
wire   [24:0] litedramcore_sdram_bankmachine2_rdport_dat_r;
reg           litedramcore_sdram_bankmachine2_refresh_gnt = 1'd0;
wire          litedramcore_sdram_bankmachine2_refresh_req;
reg           litedramcore_sdram_bankmachine2_replace = 1'd0;
wire   [21:0] litedramcore_sdram_bankmachine2_req_addr;
wire          litedramcore_sdram_bankmachine2_req_lock;
reg           litedramcore_sdram_bankmachine2_req_rdata_valid = 1'd0;
wire          litedramcore_sdram_bankmachine2_req_ready;
wire          litedramcore_sdram_bankmachine2_req_valid;
reg           litedramcore_sdram_bankmachine2_req_wdata_ready = 1'd0;
wire          litedramcore_sdram_bankmachine2_req_we;
reg    [14:0] litedramcore_sdram_bankmachine2_row = 15'd0;
reg           litedramcore_sdram_bankmachine2_row_close = 1'd0;
reg           litedramcore_sdram_bankmachine2_row_col_n_addr_sel = 1'd0;
wire          litedramcore_sdram_bankmachine2_row_hit;
reg           litedramcore_sdram_bankmachine2_row_open = 1'd0;
reg           litedramcore_sdram_bankmachine2_row_opened = 1'd0;
reg           litedramcore_sdram_bankmachine2_sink_first = 1'd0;
reg           litedramcore_sdram_bankmachine2_sink_last = 1'd0;
wire   [21:0] litedramcore_sdram_bankmachine2_sink_payload_addr;
wire          litedramcore_sdram_bankmachine2_sink_payload_we;
wire          litedramcore_sdram_bankmachine2_sink_ready;
wire          litedramcore_sdram_bankmachine2_sink_sink_first;
wire          litedramcore_sdram_bankmachine2_sink_sink_last;
wire   [21:0] litedramcore_sdram_bankmachine2_sink_sink_payload_addr;
wire          litedramcore_sdram_bankmachine2_sink_sink_payload_we;
wire          litedramcore_sdram_bankmachine2_sink_sink_ready;
wire          litedramcore_sdram_bankmachine2_sink_sink_valid;
wire          litedramcore_sdram_bankmachine2_sink_valid;
wire          litedramcore_sdram_bankmachine2_source_first;
wire          litedramcore_sdram_bankmachine2_source_last;
wire   [21:0] litedramcore_sdram_bankmachine2_source_payload_addr;
wire          litedramcore_sdram_bankmachine2_source_payload_we;
wire          litedramcore_sdram_bankmachine2_source_ready;
wire          litedramcore_sdram_bankmachine2_source_source_first;
wire          litedramcore_sdram_bankmachine2_source_source_last;
wire   [21:0] litedramcore_sdram_bankmachine2_source_source_payload_addr;
wire          litedramcore_sdram_bankmachine2_source_source_payload_we;
wire          litedramcore_sdram_bankmachine2_source_source_ready;
wire          litedramcore_sdram_bankmachine2_source_source_valid;
wire          litedramcore_sdram_bankmachine2_source_valid;
wire   [24:0] litedramcore_sdram_bankmachine2_syncfifo2_din;
wire   [24:0] litedramcore_sdram_bankmachine2_syncfifo2_dout;
wire          litedramcore_sdram_bankmachine2_syncfifo2_re;
wire          litedramcore_sdram_bankmachine2_syncfifo2_readable;
wire          litedramcore_sdram_bankmachine2_syncfifo2_we;
wire          litedramcore_sdram_bankmachine2_syncfifo2_writable;
reg     [2:0] litedramcore_sdram_bankmachine2_trascon_count = 3'd0;
(* dont_touch = "true" *)
reg           litedramcore_sdram_bankmachine2_trascon_ready = 1'd0;
wire          litedramcore_sdram_bankmachine2_trascon_valid;
reg     [3:0] litedramcore_sdram_bankmachine2_trccon_count = 4'd0;
(* dont_touch = "true" *)
reg           litedramcore_sdram_bankmachine2_trccon_ready = 1'd0;
wire          litedramcore_sdram_bankmachine2_trccon_valid;
reg     [2:0] litedramcore_sdram_bankmachine2_twtpcon_count = 3'd0;
(* dont_touch = "true" *)
reg           litedramcore_sdram_bankmachine2_twtpcon_ready = 1'd0;
wire          litedramcore_sdram_bankmachine2_twtpcon_valid;
reg     [3:0] litedramcore_sdram_bankmachine2_wrport_adr = 4'd0;
wire   [24:0] litedramcore_sdram_bankmachine2_wrport_dat_r;
wire   [24:0] litedramcore_sdram_bankmachine2_wrport_dat_w;
wire          litedramcore_sdram_bankmachine2_wrport_we;
reg           litedramcore_sdram_bankmachine3_auto_precharge = 1'd0;
reg    [14:0] litedramcore_sdram_bankmachine3_cmd_payload_a = 15'd0;
wire    [2:0] litedramcore_sdram_bankmachine3_cmd_payload_ba;
reg           litedramcore_sdram_bankmachine3_cmd_payload_cas = 1'd0;
reg           litedramcore_sdram_bankmachine3_cmd_payload_is_cmd = 1'd0;
reg           litedramcore_sdram_bankmachine3_cmd_payload_is_read = 1'd0;
reg           litedramcore_sdram_bankmachine3_cmd_payload_is_write = 1'd0;
reg           litedramcore_sdram_bankmachine3_cmd_payload_ras = 1'd0;
reg           litedramcore_sdram_bankmachine3_cmd_payload_we = 1'd0;
reg           litedramcore_sdram_bankmachine3_cmd_ready = 1'd0;
reg           litedramcore_sdram_bankmachine3_cmd_valid = 1'd0;
reg     [3:0] litedramcore_sdram_bankmachine3_consume = 4'd0;
wire          litedramcore_sdram_bankmachine3_do_read;
wire          litedramcore_sdram_bankmachine3_fifo_in_first;
wire          litedramcore_sdram_bankmachine3_fifo_in_last;
wire   [21:0] litedramcore_sdram_bankmachine3_fifo_in_payload_addr;
wire          litedramcore_sdram_bankmachine3_fifo_in_payload_we;
wire          litedramcore_sdram_bankmachine3_fifo_out_first;
wire          litedramcore_sdram_bankmachine3_fifo_out_last;
wire   [21:0] litedramcore_sdram_bankmachine3_fifo_out_payload_addr;
wire          litedramcore_sdram_bankmachine3_fifo_out_payload_we;
reg     [4:0] litedramcore_sdram_bankmachine3_level = 5'd0;
wire          litedramcore_sdram_bankmachine3_pipe_valid_sink_first;
wire          litedramcore_sdram_bankmachine3_pipe_valid_sink_last;
wire   [21:0] litedramcore_sdram_bankmachine3_pipe_valid_sink_payload_addr;
wire          litedramcore_sdram_bankmachine3_pipe_valid_sink_payload_we;
wire          litedramcore_sdram_bankmachine3_pipe_valid_sink_ready;
wire          litedramcore_sdram_bankmachine3_pipe_valid_sink_valid;
reg           litedramcore_sdram_bankmachine3_pipe_valid_source_first = 1'd0;
reg           litedramcore_sdram_bankmachine3_pipe_valid_source_last = 1'd0;
reg    [21:0] litedramcore_sdram_bankmachine3_pipe_valid_source_payload_addr = 22'd0;
reg           litedramcore_sdram_bankmachine3_pipe_valid_source_payload_we = 1'd0;
wire          litedramcore_sdram_bankmachine3_pipe_valid_source_ready;
reg           litedramcore_sdram_bankmachine3_pipe_valid_source_valid = 1'd0;
reg     [3:0] litedramcore_sdram_bankmachine3_produce = 4'd0;
wire    [3:0] litedramcore_sdram_bankmachine3_rdport_adr;
wire   [24:0] litedramcore_sdram_bankmachine3_rdport_dat_r;
reg           litedramcore_sdram_bankmachine3_refresh_gnt = 1'd0;
wire          litedramcore_sdram_bankmachine3_refresh_req;
reg           litedramcore_sdram_bankmachine3_replace = 1'd0;
wire   [21:0] litedramcore_sdram_bankmachine3_req_addr;
wire          litedramcore_sdram_bankmachine3_req_lock;
reg           litedramcore_sdram_bankmachine3_req_rdata_valid = 1'd0;
wire          litedramcore_sdram_bankmachine3_req_ready;
wire          litedramcore_sdram_bankmachine3_req_valid;
reg           litedramcore_sdram_bankmachine3_req_wdata_ready = 1'd0;
wire          litedramcore_sdram_bankmachine3_req_we;
reg    [14:0] litedramcore_sdram_bankmachine3_row = 15'd0;
reg           litedramcore_sdram_bankmachine3_row_close = 1'd0;
reg           litedramcore_sdram_bankmachine3_row_col_n_addr_sel = 1'd0;
wire          litedramcore_sdram_bankmachine3_row_hit;
reg           litedramcore_sdram_bankmachine3_row_open = 1'd0;
reg           litedramcore_sdram_bankmachine3_row_opened = 1'd0;
reg           litedramcore_sdram_bankmachine3_sink_first = 1'd0;
reg           litedramcore_sdram_bankmachine3_sink_last = 1'd0;
wire   [21:0] litedramcore_sdram_bankmachine3_sink_payload_addr;
wire          litedramcore_sdram_bankmachine3_sink_payload_we;
wire          litedramcore_sdram_bankmachine3_sink_ready;
wire          litedramcore_sdram_bankmachine3_sink_sink_first;
wire          litedramcore_sdram_bankmachine3_sink_sink_last;
wire   [21:0] litedramcore_sdram_bankmachine3_sink_sink_payload_addr;
wire          litedramcore_sdram_bankmachine3_sink_sink_payload_we;
wire          litedramcore_sdram_bankmachine3_sink_sink_ready;
wire          litedramcore_sdram_bankmachine3_sink_sink_valid;
wire          litedramcore_sdram_bankmachine3_sink_valid;
wire          litedramcore_sdram_bankmachine3_source_first;
wire          litedramcore_sdram_bankmachine3_source_last;
wire   [21:0] litedramcore_sdram_bankmachine3_source_payload_addr;
wire          litedramcore_sdram_bankmachine3_source_payload_we;
wire          litedramcore_sdram_bankmachine3_source_ready;
wire          litedramcore_sdram_bankmachine3_source_source_first;
wire          litedramcore_sdram_bankmachine3_source_source_last;
wire   [21:0] litedramcore_sdram_bankmachine3_source_source_payload_addr;
wire          litedramcore_sdram_bankmachine3_source_source_payload_we;
wire          litedramcore_sdram_bankmachine3_source_source_ready;
wire          litedramcore_sdram_bankmachine3_source_source_valid;
wire          litedramcore_sdram_bankmachine3_source_valid;
wire   [24:0] litedramcore_sdram_bankmachine3_syncfifo3_din;
wire   [24:0] litedramcore_sdram_bankmachine3_syncfifo3_dout;
wire          litedramcore_sdram_bankmachine3_syncfifo3_re;
wire          litedramcore_sdram_bankmachine3_syncfifo3_readable;
wire          litedramcore_sdram_bankmachine3_syncfifo3_we;
wire          litedramcore_sdram_bankmachine3_syncfifo3_writable;
reg     [2:0] litedramcore_sdram_bankmachine3_trascon_count = 3'd0;
(* dont_touch = "true" *)
reg           litedramcore_sdram_bankmachine3_trascon_ready = 1'd0;
wire          litedramcore_sdram_bankmachine3_trascon_valid;
reg     [3:0] litedramcore_sdram_bankmachine3_trccon_count = 4'd0;
(* dont_touch = "true" *)
reg           litedramcore_sdram_bankmachine3_trccon_ready = 1'd0;
wire          litedramcore_sdram_bankmachine3_trccon_valid;
reg     [2:0] litedramcore_sdram_bankmachine3_twtpcon_count = 3'd0;
(* dont_touch = "true" *)
reg           litedramcore_sdram_bankmachine3_twtpcon_ready = 1'd0;
wire          litedramcore_sdram_bankmachine3_twtpcon_valid;
reg     [3:0] litedramcore_sdram_bankmachine3_wrport_adr = 4'd0;
wire   [24:0] litedramcore_sdram_bankmachine3_wrport_dat_r;
wire   [24:0] litedramcore_sdram_bankmachine3_wrport_dat_w;
wire          litedramcore_sdram_bankmachine3_wrport_we;
reg           litedramcore_sdram_bankmachine4_auto_precharge = 1'd0;
reg    [14:0] litedramcore_sdram_bankmachine4_cmd_payload_a = 15'd0;
wire    [2:0] litedramcore_sdram_bankmachine4_cmd_payload_ba;
reg           litedramcore_sdram_bankmachine4_cmd_payload_cas = 1'd0;
reg           litedramcore_sdram_bankmachine4_cmd_payload_is_cmd = 1'd0;
reg           litedramcore_sdram_bankmachine4_cmd_payload_is_read = 1'd0;
reg           litedramcore_sdram_bankmachine4_cmd_payload_is_write = 1'd0;
reg           litedramcore_sdram_bankmachine4_cmd_payload_ras = 1'd0;
reg           litedramcore_sdram_bankmachine4_cmd_payload_we = 1'd0;
reg           litedramcore_sdram_bankmachine4_cmd_ready = 1'd0;
reg           litedramcore_sdram_bankmachine4_cmd_valid = 1'd0;
reg     [3:0] litedramcore_sdram_bankmachine4_consume = 4'd0;
wire          litedramcore_sdram_bankmachine4_do_read;
wire          litedramcore_sdram_bankmachine4_fifo_in_first;
wire          litedramcore_sdram_bankmachine4_fifo_in_last;
wire   [21:0] litedramcore_sdram_bankmachine4_fifo_in_payload_addr;
wire          litedramcore_sdram_bankmachine4_fifo_in_payload_we;
wire          litedramcore_sdram_bankmachine4_fifo_out_first;
wire          litedramcore_sdram_bankmachine4_fifo_out_last;
wire   [21:0] litedramcore_sdram_bankmachine4_fifo_out_payload_addr;
wire          litedramcore_sdram_bankmachine4_fifo_out_payload_we;
reg     [4:0] litedramcore_sdram_bankmachine4_level = 5'd0;
wire          litedramcore_sdram_bankmachine4_pipe_valid_sink_first;
wire          litedramcore_sdram_bankmachine4_pipe_valid_sink_last;
wire   [21:0] litedramcore_sdram_bankmachine4_pipe_valid_sink_payload_addr;
wire          litedramcore_sdram_bankmachine4_pipe_valid_sink_payload_we;
wire          litedramcore_sdram_bankmachine4_pipe_valid_sink_ready;
wire          litedramcore_sdram_bankmachine4_pipe_valid_sink_valid;
reg           litedramcore_sdram_bankmachine4_pipe_valid_source_first = 1'd0;
reg           litedramcore_sdram_bankmachine4_pipe_valid_source_last = 1'd0;
reg    [21:0] litedramcore_sdram_bankmachine4_pipe_valid_source_payload_addr = 22'd0;
reg           litedramcore_sdram_bankmachine4_pipe_valid_source_payload_we = 1'd0;
wire          litedramcore_sdram_bankmachine4_pipe_valid_source_ready;
reg           litedramcore_sdram_bankmachine4_pipe_valid_source_valid = 1'd0;
reg     [3:0] litedramcore_sdram_bankmachine4_produce = 4'd0;
wire    [3:0] litedramcore_sdram_bankmachine4_rdport_adr;
wire   [24:0] litedramcore_sdram_bankmachine4_rdport_dat_r;
reg           litedramcore_sdram_bankmachine4_refresh_gnt = 1'd0;
wire          litedramcore_sdram_bankmachine4_refresh_req;
reg           litedramcore_sdram_bankmachine4_replace = 1'd0;
wire   [21:0] litedramcore_sdram_bankmachine4_req_addr;
wire          litedramcore_sdram_bankmachine4_req_lock;
reg           litedramcore_sdram_bankmachine4_req_rdata_valid = 1'd0;
wire          litedramcore_sdram_bankmachine4_req_ready;
wire          litedramcore_sdram_bankmachine4_req_valid;
reg           litedramcore_sdram_bankmachine4_req_wdata_ready = 1'd0;
wire          litedramcore_sdram_bankmachine4_req_we;
reg    [14:0] litedramcore_sdram_bankmachine4_row = 15'd0;
reg           litedramcore_sdram_bankmachine4_row_close = 1'd0;
reg           litedramcore_sdram_bankmachine4_row_col_n_addr_sel = 1'd0;
wire          litedramcore_sdram_bankmachine4_row_hit;
reg           litedramcore_sdram_bankmachine4_row_open = 1'd0;
reg           litedramcore_sdram_bankmachine4_row_opened = 1'd0;
reg           litedramcore_sdram_bankmachine4_sink_first = 1'd0;
reg           litedramcore_sdram_bankmachine4_sink_last = 1'd0;
wire   [21:0] litedramcore_sdram_bankmachine4_sink_payload_addr;
wire          litedramcore_sdram_bankmachine4_sink_payload_we;
wire          litedramcore_sdram_bankmachine4_sink_ready;
wire          litedramcore_sdram_bankmachine4_sink_sink_first;
wire          litedramcore_sdram_bankmachine4_sink_sink_last;
wire   [21:0] litedramcore_sdram_bankmachine4_sink_sink_payload_addr;
wire          litedramcore_sdram_bankmachine4_sink_sink_payload_we;
wire          litedramcore_sdram_bankmachine4_sink_sink_ready;
wire          litedramcore_sdram_bankmachine4_sink_sink_valid;
wire          litedramcore_sdram_bankmachine4_sink_valid;
wire          litedramcore_sdram_bankmachine4_source_first;
wire          litedramcore_sdram_bankmachine4_source_last;
wire   [21:0] litedramcore_sdram_bankmachine4_source_payload_addr;
wire          litedramcore_sdram_bankmachine4_source_payload_we;
wire          litedramcore_sdram_bankmachine4_source_ready;
wire          litedramcore_sdram_bankmachine4_source_source_first;
wire          litedramcore_sdram_bankmachine4_source_source_last;
wire   [21:0] litedramcore_sdram_bankmachine4_source_source_payload_addr;
wire          litedramcore_sdram_bankmachine4_source_source_payload_we;
wire          litedramcore_sdram_bankmachine4_source_source_ready;
wire          litedramcore_sdram_bankmachine4_source_source_valid;
wire          litedramcore_sdram_bankmachine4_source_valid;
wire   [24:0] litedramcore_sdram_bankmachine4_syncfifo4_din;
wire   [24:0] litedramcore_sdram_bankmachine4_syncfifo4_dout;
wire          litedramcore_sdram_bankmachine4_syncfifo4_re;
wire          litedramcore_sdram_bankmachine4_syncfifo4_readable;
wire          litedramcore_sdram_bankmachine4_syncfifo4_we;
wire          litedramcore_sdram_bankmachine4_syncfifo4_writable;
reg     [2:0] litedramcore_sdram_bankmachine4_trascon_count = 3'd0;
(* dont_touch = "true" *)
reg           litedramcore_sdram_bankmachine4_trascon_ready = 1'd0;
wire          litedramcore_sdram_bankmachine4_trascon_valid;
reg     [3:0] litedramcore_sdram_bankmachine4_trccon_count = 4'd0;
(* dont_touch = "true" *)
reg           litedramcore_sdram_bankmachine4_trccon_ready = 1'd0;
wire          litedramcore_sdram_bankmachine4_trccon_valid;
reg     [2:0] litedramcore_sdram_bankmachine4_twtpcon_count = 3'd0;
(* dont_touch = "true" *)
reg           litedramcore_sdram_bankmachine4_twtpcon_ready = 1'd0;
wire          litedramcore_sdram_bankmachine4_twtpcon_valid;
reg     [3:0] litedramcore_sdram_bankmachine4_wrport_adr = 4'd0;
wire   [24:0] litedramcore_sdram_bankmachine4_wrport_dat_r;
wire   [24:0] litedramcore_sdram_bankmachine4_wrport_dat_w;
wire          litedramcore_sdram_bankmachine4_wrport_we;
reg           litedramcore_sdram_bankmachine5_auto_precharge = 1'd0;
reg    [14:0] litedramcore_sdram_bankmachine5_cmd_payload_a = 15'd0;
wire    [2:0] litedramcore_sdram_bankmachine5_cmd_payload_ba;
reg           litedramcore_sdram_bankmachine5_cmd_payload_cas = 1'd0;
reg           litedramcore_sdram_bankmachine5_cmd_payload_is_cmd = 1'd0;
reg           litedramcore_sdram_bankmachine5_cmd_payload_is_read = 1'd0;
reg           litedramcore_sdram_bankmachine5_cmd_payload_is_write = 1'd0;
reg           litedramcore_sdram_bankmachine5_cmd_payload_ras = 1'd0;
reg           litedramcore_sdram_bankmachine5_cmd_payload_we = 1'd0;
reg           litedramcore_sdram_bankmachine5_cmd_ready = 1'd0;
reg           litedramcore_sdram_bankmachine5_cmd_valid = 1'd0;
reg     [3:0] litedramcore_sdram_bankmachine5_consume = 4'd0;
wire          litedramcore_sdram_bankmachine5_do_read;
wire          litedramcore_sdram_bankmachine5_fifo_in_first;
wire          litedramcore_sdram_bankmachine5_fifo_in_last;
wire   [21:0] litedramcore_sdram_bankmachine5_fifo_in_payload_addr;
wire          litedramcore_sdram_bankmachine5_fifo_in_payload_we;
wire          litedramcore_sdram_bankmachine5_fifo_out_first;
wire          litedramcore_sdram_bankmachine5_fifo_out_last;
wire   [21:0] litedramcore_sdram_bankmachine5_fifo_out_payload_addr;
wire          litedramcore_sdram_bankmachine5_fifo_out_payload_we;
reg     [4:0] litedramcore_sdram_bankmachine5_level = 5'd0;
wire          litedramcore_sdram_bankmachine5_pipe_valid_sink_first;
wire          litedramcore_sdram_bankmachine5_pipe_valid_sink_last;
wire   [21:0] litedramcore_sdram_bankmachine5_pipe_valid_sink_payload_addr;
wire          litedramcore_sdram_bankmachine5_pipe_valid_sink_payload_we;
wire          litedramcore_sdram_bankmachine5_pipe_valid_sink_ready;
wire          litedramcore_sdram_bankmachine5_pipe_valid_sink_valid;
reg           litedramcore_sdram_bankmachine5_pipe_valid_source_first = 1'd0;
reg           litedramcore_sdram_bankmachine5_pipe_valid_source_last = 1'd0;
reg    [21:0] litedramcore_sdram_bankmachine5_pipe_valid_source_payload_addr = 22'd0;
reg           litedramcore_sdram_bankmachine5_pipe_valid_source_payload_we = 1'd0;
wire          litedramcore_sdram_bankmachine5_pipe_valid_source_ready;
reg           litedramcore_sdram_bankmachine5_pipe_valid_source_valid = 1'd0;
reg     [3:0] litedramcore_sdram_bankmachine5_produce = 4'd0;
wire    [3:0] litedramcore_sdram_bankmachine5_rdport_adr;
wire   [24:0] litedramcore_sdram_bankmachine5_rdport_dat_r;
reg           litedramcore_sdram_bankmachine5_refresh_gnt = 1'd0;
wire          litedramcore_sdram_bankmachine5_refresh_req;
reg           litedramcore_sdram_bankmachine5_replace = 1'd0;
wire   [21:0] litedramcore_sdram_bankmachine5_req_addr;
wire          litedramcore_sdram_bankmachine5_req_lock;
reg           litedramcore_sdram_bankmachine5_req_rdata_valid = 1'd0;
wire          litedramcore_sdram_bankmachine5_req_ready;
wire          litedramcore_sdram_bankmachine5_req_valid;
reg           litedramcore_sdram_bankmachine5_req_wdata_ready = 1'd0;
wire          litedramcore_sdram_bankmachine5_req_we;
reg    [14:0] litedramcore_sdram_bankmachine5_row = 15'd0;
reg           litedramcore_sdram_bankmachine5_row_close = 1'd0;
reg           litedramcore_sdram_bankmachine5_row_col_n_addr_sel = 1'd0;
wire          litedramcore_sdram_bankmachine5_row_hit;
reg           litedramcore_sdram_bankmachine5_row_open = 1'd0;
reg           litedramcore_sdram_bankmachine5_row_opened = 1'd0;
reg           litedramcore_sdram_bankmachine5_sink_first = 1'd0;
reg           litedramcore_sdram_bankmachine5_sink_last = 1'd0;
wire   [21:0] litedramcore_sdram_bankmachine5_sink_payload_addr;
wire          litedramcore_sdram_bankmachine5_sink_payload_we;
wire          litedramcore_sdram_bankmachine5_sink_ready;
wire          litedramcore_sdram_bankmachine5_sink_sink_first;
wire          litedramcore_sdram_bankmachine5_sink_sink_last;
wire   [21:0] litedramcore_sdram_bankmachine5_sink_sink_payload_addr;
wire          litedramcore_sdram_bankmachine5_sink_sink_payload_we;
wire          litedramcore_sdram_bankmachine5_sink_sink_ready;
wire          litedramcore_sdram_bankmachine5_sink_sink_valid;
wire          litedramcore_sdram_bankmachine5_sink_valid;
wire          litedramcore_sdram_bankmachine5_source_first;
wire          litedramcore_sdram_bankmachine5_source_last;
wire   [21:0] litedramcore_sdram_bankmachine5_source_payload_addr;
wire          litedramcore_sdram_bankmachine5_source_payload_we;
wire          litedramcore_sdram_bankmachine5_source_ready;
wire          litedramcore_sdram_bankmachine5_source_source_first;
wire          litedramcore_sdram_bankmachine5_source_source_last;
wire   [21:0] litedramcore_sdram_bankmachine5_source_source_payload_addr;
wire          litedramcore_sdram_bankmachine5_source_source_payload_we;
wire          litedramcore_sdram_bankmachine5_source_source_ready;
wire          litedramcore_sdram_bankmachine5_source_source_valid;
wire          litedramcore_sdram_bankmachine5_source_valid;
wire   [24:0] litedramcore_sdram_bankmachine5_syncfifo5_din;
wire   [24:0] litedramcore_sdram_bankmachine5_syncfifo5_dout;
wire          litedramcore_sdram_bankmachine5_syncfifo5_re;
wire          litedramcore_sdram_bankmachine5_syncfifo5_readable;
wire          litedramcore_sdram_bankmachine5_syncfifo5_we;
wire          litedramcore_sdram_bankmachine5_syncfifo5_writable;
reg     [2:0] litedramcore_sdram_bankmachine5_trascon_count = 3'd0;
(* dont_touch = "true" *)
reg           litedramcore_sdram_bankmachine5_trascon_ready = 1'd0;
wire          litedramcore_sdram_bankmachine5_trascon_valid;
reg     [3:0] litedramcore_sdram_bankmachine5_trccon_count = 4'd0;
(* dont_touch = "true" *)
reg           litedramcore_sdram_bankmachine5_trccon_ready = 1'd0;
wire          litedramcore_sdram_bankmachine5_trccon_valid;
reg     [2:0] litedramcore_sdram_bankmachine5_twtpcon_count = 3'd0;
(* dont_touch = "true" *)
reg           litedramcore_sdram_bankmachine5_twtpcon_ready = 1'd0;
wire          litedramcore_sdram_bankmachine5_twtpcon_valid;
reg     [3:0] litedramcore_sdram_bankmachine5_wrport_adr = 4'd0;
wire   [24:0] litedramcore_sdram_bankmachine5_wrport_dat_r;
wire   [24:0] litedramcore_sdram_bankmachine5_wrport_dat_w;
wire          litedramcore_sdram_bankmachine5_wrport_we;
reg           litedramcore_sdram_bankmachine6_auto_precharge = 1'd0;
reg    [14:0] litedramcore_sdram_bankmachine6_cmd_payload_a = 15'd0;
wire    [2:0] litedramcore_sdram_bankmachine6_cmd_payload_ba;
reg           litedramcore_sdram_bankmachine6_cmd_payload_cas = 1'd0;
reg           litedramcore_sdram_bankmachine6_cmd_payload_is_cmd = 1'd0;
reg           litedramcore_sdram_bankmachine6_cmd_payload_is_read = 1'd0;
reg           litedramcore_sdram_bankmachine6_cmd_payload_is_write = 1'd0;
reg           litedramcore_sdram_bankmachine6_cmd_payload_ras = 1'd0;
reg           litedramcore_sdram_bankmachine6_cmd_payload_we = 1'd0;
reg           litedramcore_sdram_bankmachine6_cmd_ready = 1'd0;
reg           litedramcore_sdram_bankmachine6_cmd_valid = 1'd0;
reg     [3:0] litedramcore_sdram_bankmachine6_consume = 4'd0;
wire          litedramcore_sdram_bankmachine6_do_read;
wire          litedramcore_sdram_bankmachine6_fifo_in_first;
wire          litedramcore_sdram_bankmachine6_fifo_in_last;
wire   [21:0] litedramcore_sdram_bankmachine6_fifo_in_payload_addr;
wire          litedramcore_sdram_bankmachine6_fifo_in_payload_we;
wire          litedramcore_sdram_bankmachine6_fifo_out_first;
wire          litedramcore_sdram_bankmachine6_fifo_out_last;
wire   [21:0] litedramcore_sdram_bankmachine6_fifo_out_payload_addr;
wire          litedramcore_sdram_bankmachine6_fifo_out_payload_we;
reg     [4:0] litedramcore_sdram_bankmachine6_level = 5'd0;
wire          litedramcore_sdram_bankmachine6_pipe_valid_sink_first;
wire          litedramcore_sdram_bankmachine6_pipe_valid_sink_last;
wire   [21:0] litedramcore_sdram_bankmachine6_pipe_valid_sink_payload_addr;
wire          litedramcore_sdram_bankmachine6_pipe_valid_sink_payload_we;
wire          litedramcore_sdram_bankmachine6_pipe_valid_sink_ready;
wire          litedramcore_sdram_bankmachine6_pipe_valid_sink_valid;
reg           litedramcore_sdram_bankmachine6_pipe_valid_source_first = 1'd0;
reg           litedramcore_sdram_bankmachine6_pipe_valid_source_last = 1'd0;
reg    [21:0] litedramcore_sdram_bankmachine6_pipe_valid_source_payload_addr = 22'd0;
reg           litedramcore_sdram_bankmachine6_pipe_valid_source_payload_we = 1'd0;
wire          litedramcore_sdram_bankmachine6_pipe_valid_source_ready;
reg           litedramcore_sdram_bankmachine6_pipe_valid_source_valid = 1'd0;
reg     [3:0] litedramcore_sdram_bankmachine6_produce = 4'd0;
wire    [3:0] litedramcore_sdram_bankmachine6_rdport_adr;
wire   [24:0] litedramcore_sdram_bankmachine6_rdport_dat_r;
reg           litedramcore_sdram_bankmachine6_refresh_gnt = 1'd0;
wire          litedramcore_sdram_bankmachine6_refresh_req;
reg           litedramcore_sdram_bankmachine6_replace = 1'd0;
wire   [21:0] litedramcore_sdram_bankmachine6_req_addr;
wire          litedramcore_sdram_bankmachine6_req_lock;
reg           litedramcore_sdram_bankmachine6_req_rdata_valid = 1'd0;
wire          litedramcore_sdram_bankmachine6_req_ready;
wire          litedramcore_sdram_bankmachine6_req_valid;
reg           litedramcore_sdram_bankmachine6_req_wdata_ready = 1'd0;
wire          litedramcore_sdram_bankmachine6_req_we;
reg    [14:0] litedramcore_sdram_bankmachine6_row = 15'd0;
reg           litedramcore_sdram_bankmachine6_row_close = 1'd0;
reg           litedramcore_sdram_bankmachine6_row_col_n_addr_sel = 1'd0;
wire          litedramcore_sdram_bankmachine6_row_hit;
reg           litedramcore_sdram_bankmachine6_row_open = 1'd0;
reg           litedramcore_sdram_bankmachine6_row_opened = 1'd0;
reg           litedramcore_sdram_bankmachine6_sink_first = 1'd0;
reg           litedramcore_sdram_bankmachine6_sink_last = 1'd0;
wire   [21:0] litedramcore_sdram_bankmachine6_sink_payload_addr;
wire          litedramcore_sdram_bankmachine6_sink_payload_we;
wire          litedramcore_sdram_bankmachine6_sink_ready;
wire          litedramcore_sdram_bankmachine6_sink_sink_first;
wire          litedramcore_sdram_bankmachine6_sink_sink_last;
wire   [21:0] litedramcore_sdram_bankmachine6_sink_sink_payload_addr;
wire          litedramcore_sdram_bankmachine6_sink_sink_payload_we;
wire          litedramcore_sdram_bankmachine6_sink_sink_ready;
wire          litedramcore_sdram_bankmachine6_sink_sink_valid;
wire          litedramcore_sdram_bankmachine6_sink_valid;
wire          litedramcore_sdram_bankmachine6_source_first;
wire          litedramcore_sdram_bankmachine6_source_last;
wire   [21:0] litedramcore_sdram_bankmachine6_source_payload_addr;
wire          litedramcore_sdram_bankmachine6_source_payload_we;
wire          litedramcore_sdram_bankmachine6_source_ready;
wire          litedramcore_sdram_bankmachine6_source_source_first;
wire          litedramcore_sdram_bankmachine6_source_source_last;
wire   [21:0] litedramcore_sdram_bankmachine6_source_source_payload_addr;
wire          litedramcore_sdram_bankmachine6_source_source_payload_we;
wire          litedramcore_sdram_bankmachine6_source_source_ready;
wire          litedramcore_sdram_bankmachine6_source_source_valid;
wire          litedramcore_sdram_bankmachine6_source_valid;
wire   [24:0] litedramcore_sdram_bankmachine6_syncfifo6_din;
wire   [24:0] litedramcore_sdram_bankmachine6_syncfifo6_dout;
wire          litedramcore_sdram_bankmachine6_syncfifo6_re;
wire          litedramcore_sdram_bankmachine6_syncfifo6_readable;
wire          litedramcore_sdram_bankmachine6_syncfifo6_we;
wire          litedramcore_sdram_bankmachine6_syncfifo6_writable;
reg     [2:0] litedramcore_sdram_bankmachine6_trascon_count = 3'd0;
(* dont_touch = "true" *)
reg           litedramcore_sdram_bankmachine6_trascon_ready = 1'd0;
wire          litedramcore_sdram_bankmachine6_trascon_valid;
reg     [3:0] litedramcore_sdram_bankmachine6_trccon_count = 4'd0;
(* dont_touch = "true" *)
reg           litedramcore_sdram_bankmachine6_trccon_ready = 1'd0;
wire          litedramcore_sdram_bankmachine6_trccon_valid;
reg     [2:0] litedramcore_sdram_bankmachine6_twtpcon_count = 3'd0;
(* dont_touch = "true" *)
reg           litedramcore_sdram_bankmachine6_twtpcon_ready = 1'd0;
wire          litedramcore_sdram_bankmachine6_twtpcon_valid;
reg     [3:0] litedramcore_sdram_bankmachine6_wrport_adr = 4'd0;
wire   [24:0] litedramcore_sdram_bankmachine6_wrport_dat_r;
wire   [24:0] litedramcore_sdram_bankmachine6_wrport_dat_w;
wire          litedramcore_sdram_bankmachine6_wrport_we;
reg           litedramcore_sdram_bankmachine7_auto_precharge = 1'd0;
reg    [14:0] litedramcore_sdram_bankmachine7_cmd_payload_a = 15'd0;
wire    [2:0] litedramcore_sdram_bankmachine7_cmd_payload_ba;
reg           litedramcore_sdram_bankmachine7_cmd_payload_cas = 1'd0;
reg           litedramcore_sdram_bankmachine7_cmd_payload_is_cmd = 1'd0;
reg           litedramcore_sdram_bankmachine7_cmd_payload_is_read = 1'd0;
reg           litedramcore_sdram_bankmachine7_cmd_payload_is_write = 1'd0;
reg           litedramcore_sdram_bankmachine7_cmd_payload_ras = 1'd0;
reg           litedramcore_sdram_bankmachine7_cmd_payload_we = 1'd0;
reg           litedramcore_sdram_bankmachine7_cmd_ready = 1'd0;
reg           litedramcore_sdram_bankmachine7_cmd_valid = 1'd0;
reg     [3:0] litedramcore_sdram_bankmachine7_consume = 4'd0;
wire          litedramcore_sdram_bankmachine7_do_read;
wire          litedramcore_sdram_bankmachine7_fifo_in_first;
wire          litedramcore_sdram_bankmachine7_fifo_in_last;
wire   [21:0] litedramcore_sdram_bankmachine7_fifo_in_payload_addr;
wire          litedramcore_sdram_bankmachine7_fifo_in_payload_we;
wire          litedramcore_sdram_bankmachine7_fifo_out_first;
wire          litedramcore_sdram_bankmachine7_fifo_out_last;
wire   [21:0] litedramcore_sdram_bankmachine7_fifo_out_payload_addr;
wire          litedramcore_sdram_bankmachine7_fifo_out_payload_we;
reg     [4:0] litedramcore_sdram_bankmachine7_level = 5'd0;
wire          litedramcore_sdram_bankmachine7_pipe_valid_sink_first;
wire          litedramcore_sdram_bankmachine7_pipe_valid_sink_last;
wire   [21:0] litedramcore_sdram_bankmachine7_pipe_valid_sink_payload_addr;
wire          litedramcore_sdram_bankmachine7_pipe_valid_sink_payload_we;
wire          litedramcore_sdram_bankmachine7_pipe_valid_sink_ready;
wire          litedramcore_sdram_bankmachine7_pipe_valid_sink_valid;
reg           litedramcore_sdram_bankmachine7_pipe_valid_source_first = 1'd0;
reg           litedramcore_sdram_bankmachine7_pipe_valid_source_last = 1'd0;
reg    [21:0] litedramcore_sdram_bankmachine7_pipe_valid_source_payload_addr = 22'd0;
reg           litedramcore_sdram_bankmachine7_pipe_valid_source_payload_we = 1'd0;
wire          litedramcore_sdram_bankmachine7_pipe_valid_source_ready;
reg           litedramcore_sdram_bankmachine7_pipe_valid_source_valid = 1'd0;
reg     [3:0] litedramcore_sdram_bankmachine7_produce = 4'd0;
wire    [3:0] litedramcore_sdram_bankmachine7_rdport_adr;
wire   [24:0] litedramcore_sdram_bankmachine7_rdport_dat_r;
reg           litedramcore_sdram_bankmachine7_refresh_gnt = 1'd0;
wire          litedramcore_sdram_bankmachine7_refresh_req;
reg           litedramcore_sdram_bankmachine7_replace = 1'd0;
wire   [21:0] litedramcore_sdram_bankmachine7_req_addr;
wire          litedramcore_sdram_bankmachine7_req_lock;
reg           litedramcore_sdram_bankmachine7_req_rdata_valid = 1'd0;
wire          litedramcore_sdram_bankmachine7_req_ready;
wire          litedramcore_sdram_bankmachine7_req_valid;
reg           litedramcore_sdram_bankmachine7_req_wdata_ready = 1'd0;
wire          litedramcore_sdram_bankmachine7_req_we;
reg    [14:0] litedramcore_sdram_bankmachine7_row = 15'd0;
reg           litedramcore_sdram_bankmachine7_row_close = 1'd0;
reg           litedramcore_sdram_bankmachine7_row_col_n_addr_sel = 1'd0;
wire          litedramcore_sdram_bankmachine7_row_hit;
reg           litedramcore_sdram_bankmachine7_row_open = 1'd0;
reg           litedramcore_sdram_bankmachine7_row_opened = 1'd0;
reg           litedramcore_sdram_bankmachine7_sink_first = 1'd0;
reg           litedramcore_sdram_bankmachine7_sink_last = 1'd0;
wire   [21:0] litedramcore_sdram_bankmachine7_sink_payload_addr;
wire          litedramcore_sdram_bankmachine7_sink_payload_we;
wire          litedramcore_sdram_bankmachine7_sink_ready;
wire          litedramcore_sdram_bankmachine7_sink_sink_first;
wire          litedramcore_sdram_bankmachine7_sink_sink_last;
wire   [21:0] litedramcore_sdram_bankmachine7_sink_sink_payload_addr;
wire          litedramcore_sdram_bankmachine7_sink_sink_payload_we;
wire          litedramcore_sdram_bankmachine7_sink_sink_ready;
wire          litedramcore_sdram_bankmachine7_sink_sink_valid;
wire          litedramcore_sdram_bankmachine7_sink_valid;
wire          litedramcore_sdram_bankmachine7_source_first;
wire          litedramcore_sdram_bankmachine7_source_last;
wire   [21:0] litedramcore_sdram_bankmachine7_source_payload_addr;
wire          litedramcore_sdram_bankmachine7_source_payload_we;
wire          litedramcore_sdram_bankmachine7_source_ready;
wire          litedramcore_sdram_bankmachine7_source_source_first;
wire          litedramcore_sdram_bankmachine7_source_source_last;
wire   [21:0] litedramcore_sdram_bankmachine7_source_source_payload_addr;
wire          litedramcore_sdram_bankmachine7_source_source_payload_we;
wire          litedramcore_sdram_bankmachine7_source_source_ready;
wire          litedramcore_sdram_bankmachine7_source_source_valid;
wire          litedramcore_sdram_bankmachine7_source_valid;
wire   [24:0] litedramcore_sdram_bankmachine7_syncfifo7_din;
wire   [24:0] litedramcore_sdram_bankmachine7_syncfifo7_dout;
wire          litedramcore_sdram_bankmachine7_syncfifo7_re;
wire          litedramcore_sdram_bankmachine7_syncfifo7_readable;
wire          litedramcore_sdram_bankmachine7_syncfifo7_we;
wire          litedramcore_sdram_bankmachine7_syncfifo7_writable;
reg     [2:0] litedramcore_sdram_bankmachine7_trascon_count = 3'd0;
(* dont_touch = "true" *)
reg           litedramcore_sdram_bankmachine7_trascon_ready = 1'd0;
wire          litedramcore_sdram_bankmachine7_trascon_valid;
reg     [3:0] litedramcore_sdram_bankmachine7_trccon_count = 4'd0;
(* dont_touch = "true" *)
reg           litedramcore_sdram_bankmachine7_trccon_ready = 1'd0;
wire          litedramcore_sdram_bankmachine7_trccon_valid;
reg     [2:0] litedramcore_sdram_bankmachine7_twtpcon_count = 3'd0;
(* dont_touch = "true" *)
reg           litedramcore_sdram_bankmachine7_twtpcon_ready = 1'd0;
wire          litedramcore_sdram_bankmachine7_twtpcon_valid;
reg     [3:0] litedramcore_sdram_bankmachine7_wrport_adr = 4'd0;
wire   [24:0] litedramcore_sdram_bankmachine7_wrport_dat_r;
wire   [24:0] litedramcore_sdram_bankmachine7_wrport_dat_w;
wire          litedramcore_sdram_bankmachine7_wrport_we;
wire          litedramcore_sdram_cas_allowed;
wire          litedramcore_sdram_choose_cmd_ce;
wire   [14:0] litedramcore_sdram_choose_cmd_cmd_payload_a;
wire    [2:0] litedramcore_sdram_choose_cmd_cmd_payload_ba;
reg           litedramcore_sdram_choose_cmd_cmd_payload_cas = 1'd0;
wire          litedramcore_sdram_choose_cmd_cmd_payload_is_cmd;
wire          litedramcore_sdram_choose_cmd_cmd_payload_is_read;
wire          litedramcore_sdram_choose_cmd_cmd_payload_is_write;
reg           litedramcore_sdram_choose_cmd_cmd_payload_ras = 1'd0;
reg           litedramcore_sdram_choose_cmd_cmd_payload_we = 1'd0;
reg           litedramcore_sdram_choose_cmd_cmd_ready = 1'd0;
wire          litedramcore_sdram_choose_cmd_cmd_valid;
reg     [2:0] litedramcore_sdram_choose_cmd_grant = 3'd0;
wire    [7:0] litedramcore_sdram_choose_cmd_request;
reg     [7:0] litedramcore_sdram_choose_cmd_valids = 8'd0;
reg           litedramcore_sdram_choose_cmd_want_activates = 1'd0;
reg           litedramcore_sdram_choose_cmd_want_cmds = 1'd0;
reg           litedramcore_sdram_choose_cmd_want_reads = 1'd0;
reg           litedramcore_sdram_choose_cmd_want_writes = 1'd0;
wire          litedramcore_sdram_choose_req_ce;
wire   [14:0] litedramcore_sdram_choose_req_cmd_payload_a;
wire    [2:0] litedramcore_sdram_choose_req_cmd_payload_ba;
reg           litedramcore_sdram_choose_req_cmd_payload_cas = 1'd0;
wire          litedramcore_sdram_choose_req_cmd_payload_is_cmd;
wire          litedramcore_sdram_choose_req_cmd_payload_is_read;
wire          litedramcore_sdram_choose_req_cmd_payload_is_write;
reg           litedramcore_sdram_choose_req_cmd_payload_ras = 1'd0;
reg           litedramcore_sdram_choose_req_cmd_payload_we = 1'd0;
reg           litedramcore_sdram_choose_req_cmd_ready = 1'd0;
wire          litedramcore_sdram_choose_req_cmd_valid;
reg     [2:0] litedramcore_sdram_choose_req_grant = 3'd0;
wire    [7:0] litedramcore_sdram_choose_req_request;
reg     [7:0] litedramcore_sdram_choose_req_valids = 8'd0;
reg           litedramcore_sdram_choose_req_want_activates = 1'd0;
reg           litedramcore_sdram_choose_req_want_cmds = 1'd0;
reg           litedramcore_sdram_choose_req_want_reads = 1'd0;
reg           litedramcore_sdram_choose_req_want_writes = 1'd0;
wire          litedramcore_sdram_cke;
reg           litedramcore_sdram_cmd_last = 1'd0;
reg    [14:0] litedramcore_sdram_cmd_payload_a = 15'd0;
reg     [2:0] litedramcore_sdram_cmd_payload_ba = 3'd0;
reg           litedramcore_sdram_cmd_payload_cas = 1'd0;
reg           litedramcore_sdram_cmd_payload_is_read = 1'd0;
reg           litedramcore_sdram_cmd_payload_is_write = 1'd0;
reg           litedramcore_sdram_cmd_payload_ras = 1'd0;
reg           litedramcore_sdram_cmd_payload_we = 1'd0;
reg           litedramcore_sdram_cmd_ready = 1'd0;
reg           litedramcore_sdram_cmd_valid = 1'd0;
reg           litedramcore_sdram_csr_dfi_p0_act_n = 1'd1;
wire   [14:0] litedramcore_sdram_csr_dfi_p0_address;
wire    [2:0] litedramcore_sdram_csr_dfi_p0_bank;
reg           litedramcore_sdram_csr_dfi_p0_cas_n = 1'd1;
wire          litedramcore_sdram_csr_dfi_p0_cke;
reg           litedramcore_sdram_csr_dfi_p0_cs_n = 1'd1;
wire          litedramcore_sdram_csr_dfi_p0_odt;
reg           litedramcore_sdram_csr_dfi_p0_ras_n = 1'd1;
reg    [63:0] litedramcore_sdram_csr_dfi_p0_rddata = 64'd0;
wire          litedramcore_sdram_csr_dfi_p0_rddata_en;
reg           litedramcore_sdram_csr_dfi_p0_rddata_valid = 1'd0;
wire          litedramcore_sdram_csr_dfi_p0_reset_n;
reg           litedramcore_sdram_csr_dfi_p0_we_n = 1'd1;
wire   [63:0] litedramcore_sdram_csr_dfi_p0_wrdata;
wire          litedramcore_sdram_csr_dfi_p0_wrdata_en;
wire    [7:0] litedramcore_sdram_csr_dfi_p0_wrdata_mask;
reg           litedramcore_sdram_csr_dfi_p1_act_n = 1'd1;
wire   [14:0] litedramcore_sdram_csr_dfi_p1_address;
wire    [2:0] litedramcore_sdram_csr_dfi_p1_bank;
reg           litedramcore_sdram_csr_dfi_p1_cas_n = 1'd1;
wire          litedramcore_sdram_csr_dfi_p1_cke;
reg           litedramcore_sdram_csr_dfi_p1_cs_n = 1'd1;
wire          litedramcore_sdram_csr_dfi_p1_odt;
reg           litedramcore_sdram_csr_dfi_p1_ras_n = 1'd1;
reg    [63:0] litedramcore_sdram_csr_dfi_p1_rddata = 64'd0;
wire          litedramcore_sdram_csr_dfi_p1_rddata_en;
reg           litedramcore_sdram_csr_dfi_p1_rddata_valid = 1'd0;
wire          litedramcore_sdram_csr_dfi_p1_reset_n;
reg           litedramcore_sdram_csr_dfi_p1_we_n = 1'd1;
wire   [63:0] litedramcore_sdram_csr_dfi_p1_wrdata;
wire          litedramcore_sdram_csr_dfi_p1_wrdata_en;
wire    [7:0] litedramcore_sdram_csr_dfi_p1_wrdata_mask;
reg           litedramcore_sdram_csr_dfi_p2_act_n = 1'd1;
wire   [14:0] litedramcore_sdram_csr_dfi_p2_address;
wire    [2:0] litedramcore_sdram_csr_dfi_p2_bank;
reg           litedramcore_sdram_csr_dfi_p2_cas_n = 1'd1;
wire          litedramcore_sdram_csr_dfi_p2_cke;
reg           litedramcore_sdram_csr_dfi_p2_cs_n = 1'd1;
wire          litedramcore_sdram_csr_dfi_p2_odt;
reg           litedramcore_sdram_csr_dfi_p2_ras_n = 1'd1;
reg    [63:0] litedramcore_sdram_csr_dfi_p2_rddata = 64'd0;
wire          litedramcore_sdram_csr_dfi_p2_rddata_en;
reg           litedramcore_sdram_csr_dfi_p2_rddata_valid = 1'd0;
wire          litedramcore_sdram_csr_dfi_p2_reset_n;
reg           litedramcore_sdram_csr_dfi_p2_we_n = 1'd1;
wire   [63:0] litedramcore_sdram_csr_dfi_p2_wrdata;
wire          litedramcore_sdram_csr_dfi_p2_wrdata_en;
wire    [7:0] litedramcore_sdram_csr_dfi_p2_wrdata_mask;
reg           litedramcore_sdram_csr_dfi_p3_act_n = 1'd1;
wire   [14:0] litedramcore_sdram_csr_dfi_p3_address;
wire    [2:0] litedramcore_sdram_csr_dfi_p3_bank;
reg           litedramcore_sdram_csr_dfi_p3_cas_n = 1'd1;
wire          litedramcore_sdram_csr_dfi_p3_cke;
reg           litedramcore_sdram_csr_dfi_p3_cs_n = 1'd1;
wire          litedramcore_sdram_csr_dfi_p3_odt;
reg           litedramcore_sdram_csr_dfi_p3_ras_n = 1'd1;
reg    [63:0] litedramcore_sdram_csr_dfi_p3_rddata = 64'd0;
wire          litedramcore_sdram_csr_dfi_p3_rddata_en;
reg           litedramcore_sdram_csr_dfi_p3_rddata_valid = 1'd0;
wire          litedramcore_sdram_csr_dfi_p3_reset_n;
reg           litedramcore_sdram_csr_dfi_p3_we_n = 1'd1;
wire   [63:0] litedramcore_sdram_csr_dfi_p3_wrdata;
wire          litedramcore_sdram_csr_dfi_p3_wrdata_en;
wire    [7:0] litedramcore_sdram_csr_dfi_p3_wrdata_mask;
reg           litedramcore_sdram_dfi_p0_act_n = 1'd1;
reg    [14:0] litedramcore_sdram_dfi_p0_address = 15'd0;
reg     [2:0] litedramcore_sdram_dfi_p0_bank = 3'd0;
reg           litedramcore_sdram_dfi_p0_cas_n = 1'd1;
wire          litedramcore_sdram_dfi_p0_cke;
reg           litedramcore_sdram_dfi_p0_cs_n = 1'd1;
wire          litedramcore_sdram_dfi_p0_odt;
reg           litedramcore_sdram_dfi_p0_ras_n = 1'd1;
wire   [63:0] litedramcore_sdram_dfi_p0_rddata;
reg           litedramcore_sdram_dfi_p0_rddata_en = 1'd0;
wire          litedramcore_sdram_dfi_p0_rddata_valid;
wire          litedramcore_sdram_dfi_p0_reset_n;
reg           litedramcore_sdram_dfi_p0_we_n = 1'd1;
wire   [63:0] litedramcore_sdram_dfi_p0_wrdata;
reg           litedramcore_sdram_dfi_p0_wrdata_en = 1'd0;
wire    [7:0] litedramcore_sdram_dfi_p0_wrdata_mask;
reg           litedramcore_sdram_dfi_p1_act_n = 1'd1;
reg    [14:0] litedramcore_sdram_dfi_p1_address = 15'd0;
reg     [2:0] litedramcore_sdram_dfi_p1_bank = 3'd0;
reg           litedramcore_sdram_dfi_p1_cas_n = 1'd1;
wire          litedramcore_sdram_dfi_p1_cke;
reg           litedramcore_sdram_dfi_p1_cs_n = 1'd1;
wire          litedramcore_sdram_dfi_p1_odt;
reg           litedramcore_sdram_dfi_p1_ras_n = 1'd1;
wire   [63:0] litedramcore_sdram_dfi_p1_rddata;
reg           litedramcore_sdram_dfi_p1_rddata_en = 1'd0;
wire          litedramcore_sdram_dfi_p1_rddata_valid;
wire          litedramcore_sdram_dfi_p1_reset_n;
reg           litedramcore_sdram_dfi_p1_we_n = 1'd1;
wire   [63:0] litedramcore_sdram_dfi_p1_wrdata;
reg           litedramcore_sdram_dfi_p1_wrdata_en = 1'd0;
wire    [7:0] litedramcore_sdram_dfi_p1_wrdata_mask;
reg           litedramcore_sdram_dfi_p2_act_n = 1'd1;
reg    [14:0] litedramcore_sdram_dfi_p2_address = 15'd0;
reg     [2:0] litedramcore_sdram_dfi_p2_bank = 3'd0;
reg           litedramcore_sdram_dfi_p2_cas_n = 1'd1;
wire          litedramcore_sdram_dfi_p2_cke;
reg           litedramcore_sdram_dfi_p2_cs_n = 1'd1;
wire          litedramcore_sdram_dfi_p2_odt;
reg           litedramcore_sdram_dfi_p2_ras_n = 1'd1;
wire   [63:0] litedramcore_sdram_dfi_p2_rddata;
reg           litedramcore_sdram_dfi_p2_rddata_en = 1'd0;
wire          litedramcore_sdram_dfi_p2_rddata_valid;
wire          litedramcore_sdram_dfi_p2_reset_n;
reg           litedramcore_sdram_dfi_p2_we_n = 1'd1;
wire   [63:0] litedramcore_sdram_dfi_p2_wrdata;
reg           litedramcore_sdram_dfi_p2_wrdata_en = 1'd0;
wire    [7:0] litedramcore_sdram_dfi_p2_wrdata_mask;
reg           litedramcore_sdram_dfi_p3_act_n = 1'd1;
reg    [14:0] litedramcore_sdram_dfi_p3_address = 15'd0;
reg     [2:0] litedramcore_sdram_dfi_p3_bank = 3'd0;
reg           litedramcore_sdram_dfi_p3_cas_n = 1'd1;
wire          litedramcore_sdram_dfi_p3_cke;
reg           litedramcore_sdram_dfi_p3_cs_n = 1'd1;
wire          litedramcore_sdram_dfi_p3_odt;
reg           litedramcore_sdram_dfi_p3_ras_n = 1'd1;
wire   [63:0] litedramcore_sdram_dfi_p3_rddata;
reg           litedramcore_sdram_dfi_p3_rddata_en = 1'd0;
wire          litedramcore_sdram_dfi_p3_rddata_valid;
wire          litedramcore_sdram_dfi_p3_reset_n;
reg           litedramcore_sdram_dfi_p3_we_n = 1'd1;
wire   [63:0] litedramcore_sdram_dfi_p3_wrdata;
reg           litedramcore_sdram_dfi_p3_wrdata_en = 1'd0;
wire    [7:0] litedramcore_sdram_dfi_p3_wrdata_mask;
reg           litedramcore_sdram_en0 = 1'd0;
reg           litedramcore_sdram_en1 = 1'd0;
reg           litedramcore_sdram_ext_dfi_p0_act_n = 1'd1;
reg    [14:0] litedramcore_sdram_ext_dfi_p0_address = 15'd0;
reg     [2:0] litedramcore_sdram_ext_dfi_p0_bank = 3'd0;
reg           litedramcore_sdram_ext_dfi_p0_cas_n = 1'd1;
reg           litedramcore_sdram_ext_dfi_p0_cke = 1'd0;
reg           litedramcore_sdram_ext_dfi_p0_cs_n = 1'd1;
reg           litedramcore_sdram_ext_dfi_p0_odt = 1'd0;
reg           litedramcore_sdram_ext_dfi_p0_ras_n = 1'd1;
reg    [63:0] litedramcore_sdram_ext_dfi_p0_rddata = 64'd0;
reg           litedramcore_sdram_ext_dfi_p0_rddata_en = 1'd0;
reg           litedramcore_sdram_ext_dfi_p0_rddata_valid = 1'd0;
reg           litedramcore_sdram_ext_dfi_p0_reset_n = 1'd0;
reg           litedramcore_sdram_ext_dfi_p0_we_n = 1'd1;
reg    [63:0] litedramcore_sdram_ext_dfi_p0_wrdata = 64'd0;
reg           litedramcore_sdram_ext_dfi_p0_wrdata_en = 1'd0;
reg     [7:0] litedramcore_sdram_ext_dfi_p0_wrdata_mask = 8'd0;
reg           litedramcore_sdram_ext_dfi_p1_act_n = 1'd1;
reg    [14:0] litedramcore_sdram_ext_dfi_p1_address = 15'd0;
reg     [2:0] litedramcore_sdram_ext_dfi_p1_bank = 3'd0;
reg           litedramcore_sdram_ext_dfi_p1_cas_n = 1'd1;
reg           litedramcore_sdram_ext_dfi_p1_cke = 1'd0;
reg           litedramcore_sdram_ext_dfi_p1_cs_n = 1'd1;
reg           litedramcore_sdram_ext_dfi_p1_odt = 1'd0;
reg           litedramcore_sdram_ext_dfi_p1_ras_n = 1'd1;
reg    [63:0] litedramcore_sdram_ext_dfi_p1_rddata = 64'd0;
reg           litedramcore_sdram_ext_dfi_p1_rddata_en = 1'd0;
reg           litedramcore_sdram_ext_dfi_p1_rddata_valid = 1'd0;
reg           litedramcore_sdram_ext_dfi_p1_reset_n = 1'd0;
reg           litedramcore_sdram_ext_dfi_p1_we_n = 1'd1;
reg    [63:0] litedramcore_sdram_ext_dfi_p1_wrdata = 64'd0;
reg           litedramcore_sdram_ext_dfi_p1_wrdata_en = 1'd0;
reg     [7:0] litedramcore_sdram_ext_dfi_p1_wrdata_mask = 8'd0;
reg           litedramcore_sdram_ext_dfi_p2_act_n = 1'd1;
reg    [14:0] litedramcore_sdram_ext_dfi_p2_address = 15'd0;
reg     [2:0] litedramcore_sdram_ext_dfi_p2_bank = 3'd0;
reg           litedramcore_sdram_ext_dfi_p2_cas_n = 1'd1;
reg           litedramcore_sdram_ext_dfi_p2_cke = 1'd0;
reg           litedramcore_sdram_ext_dfi_p2_cs_n = 1'd1;
reg           litedramcore_sdram_ext_dfi_p2_odt = 1'd0;
reg           litedramcore_sdram_ext_dfi_p2_ras_n = 1'd1;
reg    [63:0] litedramcore_sdram_ext_dfi_p2_rddata = 64'd0;
reg           litedramcore_sdram_ext_dfi_p2_rddata_en = 1'd0;
reg           litedramcore_sdram_ext_dfi_p2_rddata_valid = 1'd0;
reg           litedramcore_sdram_ext_dfi_p2_reset_n = 1'd0;
reg           litedramcore_sdram_ext_dfi_p2_we_n = 1'd1;
reg    [63:0] litedramcore_sdram_ext_dfi_p2_wrdata = 64'd0;
reg           litedramcore_sdram_ext_dfi_p2_wrdata_en = 1'd0;
reg     [7:0] litedramcore_sdram_ext_dfi_p2_wrdata_mask = 8'd0;
reg           litedramcore_sdram_ext_dfi_p3_act_n = 1'd1;
reg    [14:0] litedramcore_sdram_ext_dfi_p3_address = 15'd0;
reg     [2:0] litedramcore_sdram_ext_dfi_p3_bank = 3'd0;
reg           litedramcore_sdram_ext_dfi_p3_cas_n = 1'd1;
reg           litedramcore_sdram_ext_dfi_p3_cke = 1'd0;
reg           litedramcore_sdram_ext_dfi_p3_cs_n = 1'd1;
reg           litedramcore_sdram_ext_dfi_p3_odt = 1'd0;
reg           litedramcore_sdram_ext_dfi_p3_ras_n = 1'd1;
reg    [63:0] litedramcore_sdram_ext_dfi_p3_rddata = 64'd0;
reg           litedramcore_sdram_ext_dfi_p3_rddata_en = 1'd0;
reg           litedramcore_sdram_ext_dfi_p3_rddata_valid = 1'd0;
reg           litedramcore_sdram_ext_dfi_p3_reset_n = 1'd0;
reg           litedramcore_sdram_ext_dfi_p3_we_n = 1'd1;
reg    [63:0] litedramcore_sdram_ext_dfi_p3_wrdata = 64'd0;
reg           litedramcore_sdram_ext_dfi_p3_wrdata_en = 1'd0;
reg     [7:0] litedramcore_sdram_ext_dfi_p3_wrdata_mask = 8'd0;
reg           litedramcore_sdram_ext_dfi_sel = 1'd0;
wire          litedramcore_sdram_go_to_refresh;
wire   [21:0] litedramcore_sdram_interface_bank0_addr;
wire          litedramcore_sdram_interface_bank0_lock;
wire          litedramcore_sdram_interface_bank0_rdata_valid;
wire          litedramcore_sdram_interface_bank0_ready;
wire          litedramcore_sdram_interface_bank0_valid;
wire          litedramcore_sdram_interface_bank0_wdata_ready;
wire          litedramcore_sdram_interface_bank0_we;
wire   [21:0] litedramcore_sdram_interface_bank1_addr;
wire          litedramcore_sdram_interface_bank1_lock;
wire          litedramcore_sdram_interface_bank1_rdata_valid;
wire          litedramcore_sdram_interface_bank1_ready;
wire          litedramcore_sdram_interface_bank1_valid;
wire          litedramcore_sdram_interface_bank1_wdata_ready;
wire          litedramcore_sdram_interface_bank1_we;
wire   [21:0] litedramcore_sdram_interface_bank2_addr;
wire          litedramcore_sdram_interface_bank2_lock;
wire          litedramcore_sdram_interface_bank2_rdata_valid;
wire          litedramcore_sdram_interface_bank2_ready;
wire          litedramcore_sdram_interface_bank2_valid;
wire          litedramcore_sdram_interface_bank2_wdata_ready;
wire          litedramcore_sdram_interface_bank2_we;
wire   [21:0] litedramcore_sdram_interface_bank3_addr;
wire          litedramcore_sdram_interface_bank3_lock;
wire          litedramcore_sdram_interface_bank3_rdata_valid;
wire          litedramcore_sdram_interface_bank3_ready;
wire          litedramcore_sdram_interface_bank3_valid;
wire          litedramcore_sdram_interface_bank3_wdata_ready;
wire          litedramcore_sdram_interface_bank3_we;
wire   [21:0] litedramcore_sdram_interface_bank4_addr;
wire          litedramcore_sdram_interface_bank4_lock;
wire          litedramcore_sdram_interface_bank4_rdata_valid;
wire          litedramcore_sdram_interface_bank4_ready;
wire          litedramcore_sdram_interface_bank4_valid;
wire          litedramcore_sdram_interface_bank4_wdata_ready;
wire          litedramcore_sdram_interface_bank4_we;
wire   [21:0] litedramcore_sdram_interface_bank5_addr;
wire          litedramcore_sdram_interface_bank5_lock;
wire          litedramcore_sdram_interface_bank5_rdata_valid;
wire          litedramcore_sdram_interface_bank5_ready;
wire          litedramcore_sdram_interface_bank5_valid;
wire          litedramcore_sdram_interface_bank5_wdata_ready;
wire          litedramcore_sdram_interface_bank5_we;
wire   [21:0] litedramcore_sdram_interface_bank6_addr;
wire          litedramcore_sdram_interface_bank6_lock;
wire          litedramcore_sdram_interface_bank6_rdata_valid;
wire          litedramcore_sdram_interface_bank6_ready;
wire          litedramcore_sdram_interface_bank6_valid;
wire          litedramcore_sdram_interface_bank6_wdata_ready;
wire          litedramcore_sdram_interface_bank6_we;
wire   [21:0] litedramcore_sdram_interface_bank7_addr;
wire          litedramcore_sdram_interface_bank7_lock;
wire          litedramcore_sdram_interface_bank7_rdata_valid;
wire          litedramcore_sdram_interface_bank7_ready;
wire          litedramcore_sdram_interface_bank7_valid;
wire          litedramcore_sdram_interface_bank7_wdata_ready;
wire          litedramcore_sdram_interface_bank7_we;
wire  [255:0] litedramcore_sdram_interface_rdata;
reg   [255:0] litedramcore_sdram_interface_wdata = 256'd0;
reg    [31:0] litedramcore_sdram_interface_wdata_we = 32'd0;
reg           litedramcore_sdram_master_p0_act_n = 1'd1;
reg    [14:0] litedramcore_sdram_master_p0_address = 15'd0;
reg     [2:0] litedramcore_sdram_master_p0_bank = 3'd0;
reg           litedramcore_sdram_master_p0_cas_n = 1'd1;
reg           litedramcore_sdram_master_p0_cke = 1'd0;
reg           litedramcore_sdram_master_p0_cs_n = 1'd1;
reg           litedramcore_sdram_master_p0_odt = 1'd0;
reg           litedramcore_sdram_master_p0_ras_n = 1'd1;
wire   [63:0] litedramcore_sdram_master_p0_rddata;
reg           litedramcore_sdram_master_p0_rddata_en = 1'd0;
wire          litedramcore_sdram_master_p0_rddata_valid;
reg           litedramcore_sdram_master_p0_reset_n = 1'd0;
reg           litedramcore_sdram_master_p0_we_n = 1'd1;
reg    [63:0] litedramcore_sdram_master_p0_wrdata = 64'd0;
reg           litedramcore_sdram_master_p0_wrdata_en = 1'd0;
reg     [7:0] litedramcore_sdram_master_p0_wrdata_mask = 8'd0;
reg           litedramcore_sdram_master_p1_act_n = 1'd1;
reg    [14:0] litedramcore_sdram_master_p1_address = 15'd0;
reg     [2:0] litedramcore_sdram_master_p1_bank = 3'd0;
reg           litedramcore_sdram_master_p1_cas_n = 1'd1;
reg           litedramcore_sdram_master_p1_cke = 1'd0;
reg           litedramcore_sdram_master_p1_cs_n = 1'd1;
reg           litedramcore_sdram_master_p1_odt = 1'd0;
reg           litedramcore_sdram_master_p1_ras_n = 1'd1;
wire   [63:0] litedramcore_sdram_master_p1_rddata;
reg           litedramcore_sdram_master_p1_rddata_en = 1'd0;
wire          litedramcore_sdram_master_p1_rddata_valid;
reg           litedramcore_sdram_master_p1_reset_n = 1'd0;
reg           litedramcore_sdram_master_p1_we_n = 1'd1;
reg    [63:0] litedramcore_sdram_master_p1_wrdata = 64'd0;
reg           litedramcore_sdram_master_p1_wrdata_en = 1'd0;
reg     [7:0] litedramcore_sdram_master_p1_wrdata_mask = 8'd0;
reg           litedramcore_sdram_master_p2_act_n = 1'd1;
reg    [14:0] litedramcore_sdram_master_p2_address = 15'd0;
reg     [2:0] litedramcore_sdram_master_p2_bank = 3'd0;
reg           litedramcore_sdram_master_p2_cas_n = 1'd1;
reg           litedramcore_sdram_master_p2_cke = 1'd0;
reg           litedramcore_sdram_master_p2_cs_n = 1'd1;
reg           litedramcore_sdram_master_p2_odt = 1'd0;
reg           litedramcore_sdram_master_p2_ras_n = 1'd1;
wire   [63:0] litedramcore_sdram_master_p2_rddata;
reg           litedramcore_sdram_master_p2_rddata_en = 1'd0;
wire          litedramcore_sdram_master_p2_rddata_valid;
reg           litedramcore_sdram_master_p2_reset_n = 1'd0;
reg           litedramcore_sdram_master_p2_we_n = 1'd1;
reg    [63:0] litedramcore_sdram_master_p2_wrdata = 64'd0;
reg           litedramcore_sdram_master_p2_wrdata_en = 1'd0;
reg     [7:0] litedramcore_sdram_master_p2_wrdata_mask = 8'd0;
reg           litedramcore_sdram_master_p3_act_n = 1'd1;
reg    [14:0] litedramcore_sdram_master_p3_address = 15'd0;
reg     [2:0] litedramcore_sdram_master_p3_bank = 3'd0;
reg           litedramcore_sdram_master_p3_cas_n = 1'd1;
reg           litedramcore_sdram_master_p3_cke = 1'd0;
reg           litedramcore_sdram_master_p3_cs_n = 1'd1;
reg           litedramcore_sdram_master_p3_odt = 1'd0;
reg           litedramcore_sdram_master_p3_ras_n = 1'd1;
wire   [63:0] litedramcore_sdram_master_p3_rddata;
reg           litedramcore_sdram_master_p3_rddata_en = 1'd0;
wire          litedramcore_sdram_master_p3_rddata_valid;
reg           litedramcore_sdram_master_p3_reset_n = 1'd0;
reg           litedramcore_sdram_master_p3_we_n = 1'd1;
reg    [63:0] litedramcore_sdram_master_p3_wrdata = 64'd0;
reg           litedramcore_sdram_master_p3_wrdata_en = 1'd0;
reg     [7:0] litedramcore_sdram_master_p3_wrdata_mask = 8'd0;
wire          litedramcore_sdram_max_time0;
wire          litedramcore_sdram_max_time1;
reg    [14:0] litedramcore_sdram_nop_a = 15'd0;
reg     [2:0] litedramcore_sdram_nop_ba = 3'd0;
wire    [1:0] litedramcore_sdram_nphases;
wire          litedramcore_sdram_odt;
reg           litedramcore_sdram_phaseinjector0_address_re = 1'd0;
reg    [14:0] litedramcore_sdram_phaseinjector0_address_storage = 15'd0;
reg           litedramcore_sdram_phaseinjector0_baddress_re = 1'd0;
reg     [2:0] litedramcore_sdram_phaseinjector0_baddress_storage = 3'd0;
wire          litedramcore_sdram_phaseinjector0_command_issue_r;
reg           litedramcore_sdram_phaseinjector0_command_issue_re = 1'd0;
reg           litedramcore_sdram_phaseinjector0_command_issue_w = 1'd0;
reg           litedramcore_sdram_phaseinjector0_command_issue_we = 1'd0;
reg           litedramcore_sdram_phaseinjector0_command_re = 1'd0;
reg     [7:0] litedramcore_sdram_phaseinjector0_command_storage = 8'd0;
wire          litedramcore_sdram_phaseinjector0_csrfield_cas;
wire          litedramcore_sdram_phaseinjector0_csrfield_cs;
wire          litedramcore_sdram_phaseinjector0_csrfield_cs_bottom;
wire          litedramcore_sdram_phaseinjector0_csrfield_cs_top;
wire          litedramcore_sdram_phaseinjector0_csrfield_ras;
wire          litedramcore_sdram_phaseinjector0_csrfield_rden;
wire          litedramcore_sdram_phaseinjector0_csrfield_we;
wire          litedramcore_sdram_phaseinjector0_csrfield_wren;
reg           litedramcore_sdram_phaseinjector0_rddata_re = 1'd0;
reg    [63:0] litedramcore_sdram_phaseinjector0_rddata_status = 64'd0;
wire          litedramcore_sdram_phaseinjector0_rddata_we;
reg           litedramcore_sdram_phaseinjector0_wrdata_re = 1'd0;
reg    [63:0] litedramcore_sdram_phaseinjector0_wrdata_storage = 64'd0;
reg           litedramcore_sdram_phaseinjector1_address_re = 1'd0;
reg    [14:0] litedramcore_sdram_phaseinjector1_address_storage = 15'd0;
reg           litedramcore_sdram_phaseinjector1_baddress_re = 1'd0;
reg     [2:0] litedramcore_sdram_phaseinjector1_baddress_storage = 3'd0;
wire          litedramcore_sdram_phaseinjector1_command_issue_r;
reg           litedramcore_sdram_phaseinjector1_command_issue_re = 1'd0;
reg           litedramcore_sdram_phaseinjector1_command_issue_w = 1'd0;
reg           litedramcore_sdram_phaseinjector1_command_issue_we = 1'd0;
reg           litedramcore_sdram_phaseinjector1_command_re = 1'd0;
reg     [7:0] litedramcore_sdram_phaseinjector1_command_storage = 8'd0;
wire          litedramcore_sdram_phaseinjector1_csrfield_cas;
wire          litedramcore_sdram_phaseinjector1_csrfield_cs;
wire          litedramcore_sdram_phaseinjector1_csrfield_cs_bottom;
wire          litedramcore_sdram_phaseinjector1_csrfield_cs_top;
wire          litedramcore_sdram_phaseinjector1_csrfield_ras;
wire          litedramcore_sdram_phaseinjector1_csrfield_rden;
wire          litedramcore_sdram_phaseinjector1_csrfield_we;
wire          litedramcore_sdram_phaseinjector1_csrfield_wren;
reg           litedramcore_sdram_phaseinjector1_rddata_re = 1'd0;
reg    [63:0] litedramcore_sdram_phaseinjector1_rddata_status = 64'd0;
wire          litedramcore_sdram_phaseinjector1_rddata_we;
reg           litedramcore_sdram_phaseinjector1_wrdata_re = 1'd0;
reg    [63:0] litedramcore_sdram_phaseinjector1_wrdata_storage = 64'd0;
reg           litedramcore_sdram_phaseinjector2_address_re = 1'd0;
reg    [14:0] litedramcore_sdram_phaseinjector2_address_storage = 15'd0;
reg           litedramcore_sdram_phaseinjector2_baddress_re = 1'd0;
reg     [2:0] litedramcore_sdram_phaseinjector2_baddress_storage = 3'd0;
wire          litedramcore_sdram_phaseinjector2_command_issue_r;
reg           litedramcore_sdram_phaseinjector2_command_issue_re = 1'd0;
reg           litedramcore_sdram_phaseinjector2_command_issue_w = 1'd0;
reg           litedramcore_sdram_phaseinjector2_command_issue_we = 1'd0;
reg           litedramcore_sdram_phaseinjector2_command_re = 1'd0;
reg     [7:0] litedramcore_sdram_phaseinjector2_command_storage = 8'd0;
wire          litedramcore_sdram_phaseinjector2_csrfield_cas;
wire          litedramcore_sdram_phaseinjector2_csrfield_cs;
wire          litedramcore_sdram_phaseinjector2_csrfield_cs_bottom;
wire          litedramcore_sdram_phaseinjector2_csrfield_cs_top;
wire          litedramcore_sdram_phaseinjector2_csrfield_ras;
wire          litedramcore_sdram_phaseinjector2_csrfield_rden;
wire          litedramcore_sdram_phaseinjector2_csrfield_we;
wire          litedramcore_sdram_phaseinjector2_csrfield_wren;
reg           litedramcore_sdram_phaseinjector2_rddata_re = 1'd0;
reg    [63:0] litedramcore_sdram_phaseinjector2_rddata_status = 64'd0;
wire          litedramcore_sdram_phaseinjector2_rddata_we;
reg           litedramcore_sdram_phaseinjector2_wrdata_re = 1'd0;
reg    [63:0] litedramcore_sdram_phaseinjector2_wrdata_storage = 64'd0;
reg           litedramcore_sdram_phaseinjector3_address_re = 1'd0;
reg    [14:0] litedramcore_sdram_phaseinjector3_address_storage = 15'd0;
reg           litedramcore_sdram_phaseinjector3_baddress_re = 1'd0;
reg     [2:0] litedramcore_sdram_phaseinjector3_baddress_storage = 3'd0;
wire          litedramcore_sdram_phaseinjector3_command_issue_r;
reg           litedramcore_sdram_phaseinjector3_command_issue_re = 1'd0;
reg           litedramcore_sdram_phaseinjector3_command_issue_w = 1'd0;
reg           litedramcore_sdram_phaseinjector3_command_issue_we = 1'd0;
reg           litedramcore_sdram_phaseinjector3_command_re = 1'd0;
reg     [7:0] litedramcore_sdram_phaseinjector3_command_storage = 8'd0;
wire          litedramcore_sdram_phaseinjector3_csrfield_cas;
wire          litedramcore_sdram_phaseinjector3_csrfield_cs;
wire          litedramcore_sdram_phaseinjector3_csrfield_cs_bottom;
wire          litedramcore_sdram_phaseinjector3_csrfield_cs_top;
wire          litedramcore_sdram_phaseinjector3_csrfield_ras;
wire          litedramcore_sdram_phaseinjector3_csrfield_rden;
wire          litedramcore_sdram_phaseinjector3_csrfield_we;
wire          litedramcore_sdram_phaseinjector3_csrfield_wren;
reg           litedramcore_sdram_phaseinjector3_rddata_re = 1'd0;
reg    [63:0] litedramcore_sdram_phaseinjector3_rddata_status = 64'd0;
wire          litedramcore_sdram_phaseinjector3_rddata_we;
reg           litedramcore_sdram_phaseinjector3_wrdata_re = 1'd0;
reg    [63:0] litedramcore_sdram_phaseinjector3_wrdata_storage = 64'd0;
reg           litedramcore_sdram_postponer_count = 1'd0;
wire          litedramcore_sdram_postponer_req_i;
reg           litedramcore_sdram_postponer_req_o = 1'd0;
wire          litedramcore_sdram_ras_allowed;
wire    [1:0] litedramcore_sdram_rdphase;
reg           litedramcore_sdram_re = 1'd0;
wire          litedramcore_sdram_read_available;
wire          litedramcore_sdram_reset_n;
wire          litedramcore_sdram_sel;
reg           litedramcore_sdram_sequencer_count = 1'd0;
wire          litedramcore_sdram_sequencer_done0;
reg           litedramcore_sdram_sequencer_done1 = 1'd0;
reg           litedramcore_sdram_sequencer_start0 = 1'd0;
wire          litedramcore_sdram_sequencer_start1;
reg     [5:0] litedramcore_sdram_sequencer_trigger = 6'd0;
wire          litedramcore_sdram_slave_p0_act_n;
wire   [14:0] litedramcore_sdram_slave_p0_address;
wire    [2:0] litedramcore_sdram_slave_p0_bank;
wire          litedramcore_sdram_slave_p0_cas_n;
wire          litedramcore_sdram_slave_p0_cke;
wire          litedramcore_sdram_slave_p0_cs_n;
wire          litedramcore_sdram_slave_p0_odt;
wire          litedramcore_sdram_slave_p0_ras_n;
reg    [63:0] litedramcore_sdram_slave_p0_rddata = 64'd0;
wire          litedramcore_sdram_slave_p0_rddata_en;
reg           litedramcore_sdram_slave_p0_rddata_valid = 1'd0;
wire          litedramcore_sdram_slave_p0_reset_n;
wire          litedramcore_sdram_slave_p0_we_n;
wire   [63:0] litedramcore_sdram_slave_p0_wrdata;
wire          litedramcore_sdram_slave_p0_wrdata_en;
wire    [7:0] litedramcore_sdram_slave_p0_wrdata_mask;
wire          litedramcore_sdram_slave_p1_act_n;
wire   [14:0] litedramcore_sdram_slave_p1_address;
wire    [2:0] litedramcore_sdram_slave_p1_bank;
wire          litedramcore_sdram_slave_p1_cas_n;
wire          litedramcore_sdram_slave_p1_cke;
wire          litedramcore_sdram_slave_p1_cs_n;
wire          litedramcore_sdram_slave_p1_odt;
wire          litedramcore_sdram_slave_p1_ras_n;
reg    [63:0] litedramcore_sdram_slave_p1_rddata = 64'd0;
wire          litedramcore_sdram_slave_p1_rddata_en;
reg           litedramcore_sdram_slave_p1_rddata_valid = 1'd0;
wire          litedramcore_sdram_slave_p1_reset_n;
wire          litedramcore_sdram_slave_p1_we_n;
wire   [63:0] litedramcore_sdram_slave_p1_wrdata;
wire          litedramcore_sdram_slave_p1_wrdata_en;
wire    [7:0] litedramcore_sdram_slave_p1_wrdata_mask;
wire          litedramcore_sdram_slave_p2_act_n;
wire   [14:0] litedramcore_sdram_slave_p2_address;
wire    [2:0] litedramcore_sdram_slave_p2_bank;
wire          litedramcore_sdram_slave_p2_cas_n;
wire          litedramcore_sdram_slave_p2_cke;
wire          litedramcore_sdram_slave_p2_cs_n;
wire          litedramcore_sdram_slave_p2_odt;
wire          litedramcore_sdram_slave_p2_ras_n;
reg    [63:0] litedramcore_sdram_slave_p2_rddata = 64'd0;
wire          litedramcore_sdram_slave_p2_rddata_en;
reg           litedramcore_sdram_slave_p2_rddata_valid = 1'd0;
wire          litedramcore_sdram_slave_p2_reset_n;
wire          litedramcore_sdram_slave_p2_we_n;
wire   [63:0] litedramcore_sdram_slave_p2_wrdata;
wire          litedramcore_sdram_slave_p2_wrdata_en;
wire    [7:0] litedramcore_sdram_slave_p2_wrdata_mask;
wire          litedramcore_sdram_slave_p3_act_n;
wire   [14:0] litedramcore_sdram_slave_p3_address;
wire    [2:0] litedramcore_sdram_slave_p3_bank;
wire          litedramcore_sdram_slave_p3_cas_n;
wire          litedramcore_sdram_slave_p3_cke;
wire          litedramcore_sdram_slave_p3_cs_n;
wire          litedramcore_sdram_slave_p3_odt;
wire          litedramcore_sdram_slave_p3_ras_n;
reg    [63:0] litedramcore_sdram_slave_p3_rddata = 64'd0;
wire          litedramcore_sdram_slave_p3_rddata_en;
reg           litedramcore_sdram_slave_p3_rddata_valid = 1'd0;
wire          litedramcore_sdram_slave_p3_reset_n;
wire          litedramcore_sdram_slave_p3_we_n;
wire   [63:0] litedramcore_sdram_slave_p3_wrdata;
wire          litedramcore_sdram_slave_p3_wrdata_en;
wire    [7:0] litedramcore_sdram_slave_p3_wrdata_mask;
reg     [1:0] litedramcore_sdram_steerer0 = 2'd0;
reg     [1:0] litedramcore_sdram_steerer1 = 2'd0;
reg           litedramcore_sdram_steerer10 = 1'd1;
reg           litedramcore_sdram_steerer11 = 1'd1;
reg     [1:0] litedramcore_sdram_steerer2 = 2'd0;
reg     [1:0] litedramcore_sdram_steerer3 = 2'd0;
reg           litedramcore_sdram_steerer4 = 1'd1;
reg           litedramcore_sdram_steerer5 = 1'd1;
reg           litedramcore_sdram_steerer6 = 1'd1;
reg           litedramcore_sdram_steerer7 = 1'd1;
reg           litedramcore_sdram_steerer8 = 1'd1;
reg           litedramcore_sdram_steerer9 = 1'd1;
reg     [3:0] litedramcore_sdram_storage = 4'd1;
reg           litedramcore_sdram_tccdcon_count = 1'd0;
(* dont_touch = "true" *)
reg           litedramcore_sdram_tccdcon_ready = 1'd0;
wire          litedramcore_sdram_tccdcon_valid;
wire    [3:0] litedramcore_sdram_tfawcon_count;
(* dont_touch = "true" *)
reg           litedramcore_sdram_tfawcon_ready = 1'd1;
wire          litedramcore_sdram_tfawcon_valid;
reg     [8:0] litedramcore_sdram_tfawcon_window = 9'd0;
reg     [4:0] litedramcore_sdram_time0 = 5'd0;
reg     [3:0] litedramcore_sdram_time1 = 4'd0;
wire   [10:0] litedramcore_sdram_timer_count0;
reg    [10:0] litedramcore_sdram_timer_count1 = 11'd1562;
wire          litedramcore_sdram_timer_done0;
wire          litedramcore_sdram_timer_done1;
wire          litedramcore_sdram_timer_wait;
reg     [1:0] litedramcore_sdram_trrdcon_count = 2'd0;
(* dont_touch = "true" *)
reg           litedramcore_sdram_trrdcon_ready = 1'd0;
wire          litedramcore_sdram_trrdcon_valid;
reg     [2:0] litedramcore_sdram_twtrcon_count = 3'd0;
(* dont_touch = "true" *)
reg           litedramcore_sdram_twtrcon_ready = 1'd0;
wire          litedramcore_sdram_twtrcon_valid;
wire          litedramcore_sdram_wants_refresh;
wire          litedramcore_sdram_wants_zqcs;
wire          litedramcore_sdram_write_available;
reg           litedramcore_sdram_zqcs_executer_done = 1'd0;
reg           litedramcore_sdram_zqcs_executer_start = 1'd0;
reg     [4:0] litedramcore_sdram_zqcs_executer_trigger = 5'd0;
wire   [27:0] litedramcore_sdram_zqcs_timer_count0;
reg    [27:0] litedramcore_sdram_zqcs_timer_count1 = 28'd199999999;
wire          litedramcore_sdram_zqcs_timer_done0;
wire          litedramcore_sdram_zqcs_timer_done1;
wire          litedramcore_sdram_zqcs_timer_wait;
reg           litedramcore_soc_rst = 1'd0;
reg     [1:0] litedramcore_state = 2'd0;
reg           litedramcore_status_re = 1'd0;
wire          litedramcore_status_status;
wire          litedramcore_status_we;
reg           litedramcore_tag_di_dirty = 1'd0;
wire   [28:0] litedramcore_tag_di_tag;
wire          litedramcore_tag_do_dirty;
wire   [28:0] litedramcore_tag_do_tag;
wire          litedramcore_tag_port_adr;
wire   [29:0] litedramcore_tag_port_dat_r;
wire   [29:0] litedramcore_tag_port_dat_w;
reg           litedramcore_tag_port_we = 1'd0;
reg           litedramcore_update_value_re = 1'd0;
reg           litedramcore_update_value_storage = 1'd0;
reg    [31:0] litedramcore_value = 32'd0;
reg           litedramcore_value_re = 1'd0;
reg    [31:0] litedramcore_value_status = 32'd0;
wire          litedramcore_value_we;
reg    [31:0] litedramcore_vexriscv = 32'd0;
reg           litedramcore_wb_sdram_ack = 1'd0;
wire   [29:0] litedramcore_wb_sdram_adr;
wire    [1:0] litedramcore_wb_sdram_bte;
wire    [2:0] litedramcore_wb_sdram_cti;
wire          litedramcore_wb_sdram_cyc;
reg    [31:0] litedramcore_wb_sdram_dat_r = 32'd0;
wire   [31:0] litedramcore_wb_sdram_dat_w;
reg           litedramcore_wb_sdram_err = 1'd0;
wire    [3:0] litedramcore_wb_sdram_sel;
wire          litedramcore_wb_sdram_stb;
wire          litedramcore_wb_sdram_we;
reg           litedramcore_word_clr = 1'd0;
reg           litedramcore_word_inc = 1'd0;
reg           litedramcore_write_from_slave = 1'd0;
wire          litedramcore_zero0;
wire          litedramcore_zero1;
wire          litedramcore_zero2;
reg           litedramcore_zero_clear = 1'd0;
reg           litedramcore_zero_pending = 1'd0;
wire          litedramcore_zero_status;
wire          litedramcore_zero_trigger;
reg           litedramcore_zero_trigger_d = 1'd0;
reg     [1:0] litedramwishbone2native0_next_state = 2'd0;
reg     [1:0] litedramwishbone2native0_state = 2'd0;
reg     [1:0] litedramwishbone2native1_next_state = 2'd0;
reg     [1:0] litedramwishbone2native1_state = 2'd0;
reg           obj_uart_tx_rs232phytx_next_value1 = 1'd0;
reg           obj_uart_tx_rs232phytx_next_value_ce1 = 1'd0;
wire          pll_fb;
wire          re;
wire    [1:0] request;
wire          reset0;
wire          reset1;
wire          reset2;
wire          reset3;
wire          reset4;
wire          reset5;
wire          reset6;
wire          reset7;
reg    [29:0] rhs_self0 = 30'd0;
reg    [31:0] rhs_self1 = 32'd0;
reg     [2:0] rhs_self10 = 3'd0;
reg           rhs_self11 = 1'd0;
reg           rhs_self12 = 1'd0;
reg           rhs_self13 = 1'd0;
reg           rhs_self14 = 1'd0;
reg    [14:0] rhs_self15 = 15'd0;
reg     [2:0] rhs_self16 = 3'd0;
reg           rhs_self17 = 1'd0;
reg           rhs_self18 = 1'd0;
reg           rhs_self19 = 1'd0;
reg     [3:0] rhs_self2 = 4'd0;
reg    [21:0] rhs_self20 = 22'd0;
reg           rhs_self21 = 1'd0;
reg           rhs_self22 = 1'd0;
reg    [21:0] rhs_self23 = 22'd0;
reg           rhs_self24 = 1'd0;
reg           rhs_self25 = 1'd0;
reg    [21:0] rhs_self26 = 22'd0;
reg           rhs_self27 = 1'd0;
reg           rhs_self28 = 1'd0;
reg    [21:0] rhs_self29 = 22'd0;
reg           rhs_self3 = 1'd0;
reg           rhs_self30 = 1'd0;
reg           rhs_self31 = 1'd0;
reg    [21:0] rhs_self32 = 22'd0;
reg           rhs_self33 = 1'd0;
reg           rhs_self34 = 1'd0;
reg    [21:0] rhs_self35 = 22'd0;
reg           rhs_self36 = 1'd0;
reg           rhs_self37 = 1'd0;
reg    [21:0] rhs_self38 = 22'd0;
reg           rhs_self39 = 1'd0;
reg           rhs_self4 = 1'd0;
reg           rhs_self40 = 1'd0;
reg    [21:0] rhs_self41 = 22'd0;
reg           rhs_self42 = 1'd0;
reg           rhs_self43 = 1'd0;
reg           rhs_self5 = 1'd0;
reg     [2:0] rhs_self6 = 3'd0;
reg     [1:0] rhs_self7 = 2'd0;
reg           rhs_self8 = 1'd0;
reg    [14:0] rhs_self9 = 15'd0;
reg           rs232phyrx_next_state = 1'd0;
reg           rs232phyrx_state = 1'd0;
reg           rs232phytx_next_state = 1'd0;
reg           rs232phytx_state = 1'd0;
reg     [3:0] rx_count = 4'd0;
reg     [3:0] rx_count_rs232phyrx_next_value0 = 4'd0;
reg           rx_count_rs232phyrx_next_value_ce0 = 1'd0;
reg     [7:0] rx_data = 8'd0;
reg     [7:0] rx_data_rs232phyrx_next_value1 = 8'd0;
reg           rx_data_rs232phyrx_next_value_ce1 = 1'd0;
reg           rx_enable = 1'd0;
reg    [31:0] rx_phase = 32'd0;
wire          rx_rx;
reg           rx_rx_d = 1'd0;
reg           rx_source_first = 1'd0;
reg           rx_source_last = 1'd0;
reg     [7:0] rx_source_payload_data = 8'd0;
wire          rx_source_ready;
reg           rx_source_valid = 1'd0;
reg           rx_tick = 1'd0;
reg     [2:0] self0 = 3'd0;
reg    [14:0] self1 = 15'd0;
reg           self10 = 1'd0;
reg           self11 = 1'd0;
reg           self12 = 1'd0;
reg           self13 = 1'd0;
reg     [2:0] self14 = 3'd0;
reg    [14:0] self15 = 15'd0;
reg           self16 = 1'd0;
reg           self17 = 1'd0;
reg           self18 = 1'd0;
reg           self19 = 1'd0;
reg           self2 = 1'd0;
reg           self20 = 1'd0;
reg     [2:0] self21 = 3'd0;
reg    [14:0] self22 = 15'd0;
reg           self23 = 1'd0;
reg           self24 = 1'd0;
reg           self25 = 1'd0;
reg           self26 = 1'd0;
reg           self27 = 1'd0;
reg           self3 = 1'd0;
reg           self4 = 1'd0;
reg           self5 = 1'd0;
reg           self6 = 1'd0;
reg     [2:0] self7 = 3'd0;
reg    [14:0] self8 = 15'd0;
reg           self9 = 1'd0;
reg           shared_ack = 1'd0;
wire   [29:0] shared_adr;
wire    [1:0] shared_bte;
wire    [2:0] shared_cti;
wire          shared_cyc;
reg    [31:0] shared_dat_r = 32'd0;
wire   [31:0] shared_dat_w;
wire          shared_err;
wire    [3:0] shared_sel;
wire          shared_stb;
wire          shared_we;
reg     [3:0] slave_sel = 4'd0;
reg     [3:0] slave_sel_r = 4'd0;
wire          sys4x_clk;
wire          sys4x_dqs_clk;
wire          sys_clk;
wire          sys_rst;
reg           t_self0 = 1'd0;
reg           t_self1 = 1'd0;
reg           t_self2 = 1'd0;
reg           t_self3 = 1'd0;
reg           t_self4 = 1'd0;
reg           t_self5 = 1'd0;
reg     [3:0] tx_count = 4'd0;
reg     [3:0] tx_count_rs232phytx_next_value0 = 4'd0;
reg           tx_count_rs232phytx_next_value_ce0 = 1'd0;
reg     [7:0] tx_data = 8'd0;
reg     [7:0] tx_data_rs232phytx_next_value2 = 8'd0;
reg           tx_data_rs232phytx_next_value_ce2 = 1'd0;
reg           tx_enable = 1'd0;
reg    [31:0] tx_phase = 32'd0;
wire          tx_sink_first;
wire          tx_sink_last;
wire    [7:0] tx_sink_payload_data;
reg           tx_sink_ready = 1'd0;
wire          tx_sink_valid;
reg           tx_tick = 1'd0;
reg           uart_enable_re = 1'd0;
reg     [1:0] uart_enable_storage = 2'd0;
wire          uart_irq;
reg     [1:0] uart_pending_r = 2'd0;
reg           uart_pending_re = 1'd0;
reg     [1:0] uart_pending_status = 2'd0;
wire          uart_pending_we;
wire          uart_rx0;
wire          uart_rx1;
wire          uart_rx2;
reg           uart_rx_clear = 1'd0;
reg     [3:0] uart_rx_fifo_consume = 4'd0;
wire          uart_rx_fifo_do_read;
wire          uart_rx_fifo_fifo_in_first;
wire          uart_rx_fifo_fifo_in_last;
wire    [7:0] uart_rx_fifo_fifo_in_payload_data;
wire          uart_rx_fifo_fifo_out_first;
wire          uart_rx_fifo_fifo_out_last;
wire    [7:0] uart_rx_fifo_fifo_out_payload_data;
reg     [4:0] uart_rx_fifo_level0 = 5'd0;
wire    [4:0] uart_rx_fifo_level1;
reg     [3:0] uart_rx_fifo_produce = 4'd0;
wire    [3:0] uart_rx_fifo_rdport_adr;
wire    [9:0] uart_rx_fifo_rdport_dat_r;
wire          uart_rx_fifo_rdport_re;
wire          uart_rx_fifo_re;
reg           uart_rx_fifo_readable = 1'd0;
reg           uart_rx_fifo_replace = 1'd0;
wire          uart_rx_fifo_sink_first;
wire          uart_rx_fifo_sink_last;
wire    [7:0] uart_rx_fifo_sink_payload_data;
wire          uart_rx_fifo_sink_ready;
wire          uart_rx_fifo_sink_valid;
wire          uart_rx_fifo_source_first;
wire          uart_rx_fifo_source_last;
wire    [7:0] uart_rx_fifo_source_payload_data;
wire          uart_rx_fifo_source_ready;
wire          uart_rx_fifo_source_valid;
wire    [9:0] uart_rx_fifo_syncfifo_din;
wire    [9:0] uart_rx_fifo_syncfifo_dout;
wire          uart_rx_fifo_syncfifo_re;
wire          uart_rx_fifo_syncfifo_readable;
wire          uart_rx_fifo_syncfifo_we;
wire          uart_rx_fifo_syncfifo_writable;
reg     [3:0] uart_rx_fifo_wrport_adr = 4'd0;
wire    [9:0] uart_rx_fifo_wrport_dat_r;
wire    [9:0] uart_rx_fifo_wrport_dat_w;
wire          uart_rx_fifo_wrport_we;
reg           uart_rx_pending = 1'd0;
wire          uart_rx_status;
wire          uart_rx_trigger;
reg           uart_rx_trigger_d = 1'd0;
reg           uart_rxempty_re = 1'd0;
wire          uart_rxempty_status;
wire          uart_rxempty_we;
reg           uart_rxfull_re = 1'd0;
wire          uart_rxfull_status;
wire          uart_rxfull_we;
wire    [7:0] uart_rxtx_r;
reg           uart_rxtx_re = 1'd0;
wire    [7:0] uart_rxtx_w;
reg           uart_rxtx_we = 1'd0;
reg           uart_status_re = 1'd0;
reg     [1:0] uart_status_status = 2'd0;
wire          uart_status_we;
wire          uart_tx0;
wire          uart_tx1;
wire          uart_tx2;
reg           uart_tx_clear = 1'd0;
reg     [3:0] uart_tx_fifo_consume = 4'd0;
wire          uart_tx_fifo_do_read;
wire          uart_tx_fifo_fifo_in_first;
wire          uart_tx_fifo_fifo_in_last;
wire    [7:0] uart_tx_fifo_fifo_in_payload_data;
wire          uart_tx_fifo_fifo_out_first;
wire          uart_tx_fifo_fifo_out_last;
wire    [7:0] uart_tx_fifo_fifo_out_payload_data;
reg     [4:0] uart_tx_fifo_level0 = 5'd0;
wire    [4:0] uart_tx_fifo_level1;
reg     [3:0] uart_tx_fifo_produce = 4'd0;
wire    [3:0] uart_tx_fifo_rdport_adr;
wire    [9:0] uart_tx_fifo_rdport_dat_r;
wire          uart_tx_fifo_rdport_re;
wire          uart_tx_fifo_re;
reg           uart_tx_fifo_readable = 1'd0;
reg           uart_tx_fifo_replace = 1'd0;
reg           uart_tx_fifo_sink_first = 1'd0;
reg           uart_tx_fifo_sink_last = 1'd0;
wire    [7:0] uart_tx_fifo_sink_payload_data;
wire          uart_tx_fifo_sink_ready;
wire          uart_tx_fifo_sink_valid;
wire          uart_tx_fifo_source_first;
wire          uart_tx_fifo_source_last;
wire    [7:0] uart_tx_fifo_source_payload_data;
wire          uart_tx_fifo_source_ready;
wire          uart_tx_fifo_source_valid;
wire    [9:0] uart_tx_fifo_syncfifo_din;
wire    [9:0] uart_tx_fifo_syncfifo_dout;
wire          uart_tx_fifo_syncfifo_re;
wire          uart_tx_fifo_syncfifo_readable;
wire          uart_tx_fifo_syncfifo_we;
wire          uart_tx_fifo_syncfifo_writable;
reg     [3:0] uart_tx_fifo_wrport_adr = 4'd0;
wire    [9:0] uart_tx_fifo_wrport_dat_r;
wire    [9:0] uart_tx_fifo_wrport_dat_w;
wire          uart_tx_fifo_wrport_we;
reg           uart_tx_pending = 1'd0;
wire          uart_tx_status;
wire          uart_tx_trigger;
reg           uart_tx_trigger_d = 1'd0;
reg           uart_txempty_re = 1'd0;
wire          uart_txempty_status;
wire          uart_txempty_we;
reg           uart_txfull_re = 1'd0;
wire          uart_txfull_status;
wire          uart_txfull_we;
wire          uart_uart_sink_first;
wire          uart_uart_sink_last;
wire    [7:0] uart_uart_sink_payload_data;
wire          uart_uart_sink_ready;
wire          uart_uart_sink_valid;
wire          uart_uart_source_first;
wire          uart_uart_source_last;
wire    [7:0] uart_uart_source_payload_data;
wire          uart_uart_source_ready;
wire          uart_uart_source_valid;
reg           user_enable = 1'd0;
wire          user_port_litedramnativeportconverter_addr_changed;
reg    [27:0] user_port_litedramnativeportconverter_cmd_addr = 28'd0;
reg    [27:0] user_port_litedramnativeportconverter_cmd_addr_litedramcore_next_value0 = 28'd0;
reg           user_port_litedramnativeportconverter_cmd_addr_litedramcore_next_value_ce0 = 1'd0;
reg           user_port_litedramnativeportconverter_cmd_buffer_sink_first = 1'd0;
reg           user_port_litedramnativeportconverter_cmd_buffer_sink_last = 1'd0;
reg     [7:0] user_port_litedramnativeportconverter_cmd_buffer_sink_payload_sel = 8'd0;
reg           user_port_litedramnativeportconverter_cmd_buffer_sink_payload_we = 1'd0;
wire          user_port_litedramnativeportconverter_cmd_buffer_sink_ready;
reg           user_port_litedramnativeportconverter_cmd_buffer_sink_valid = 1'd0;
wire          user_port_litedramnativeportconverter_cmd_buffer_source_first;
wire          user_port_litedramnativeportconverter_cmd_buffer_source_last;
wire    [7:0] user_port_litedramnativeportconverter_cmd_buffer_source_payload_sel;
wire          user_port_litedramnativeportconverter_cmd_buffer_source_payload_we;
wire          user_port_litedramnativeportconverter_cmd_buffer_source_ready;
wire          user_port_litedramnativeportconverter_cmd_buffer_source_valid;
reg           user_port_litedramnativeportconverter_cmd_last = 1'd0;
reg           user_port_litedramnativeportconverter_cmd_last_litedramcore_next_value2 = 1'd0;
reg           user_port_litedramnativeportconverter_cmd_last_litedramcore_next_value_ce2 = 1'd0;
reg           user_port_litedramnativeportconverter_cmd_we = 1'd0;
reg           user_port_litedramnativeportconverter_cmd_we_litedramcore_next_value1 = 1'd0;
reg           user_port_litedramnativeportconverter_cmd_we_litedramcore_next_value_ce1 = 1'd0;
wire          user_port_litedramnativeportconverter_next_cmd;
reg     [7:0] user_port_litedramnativeportconverter_rdata_chunk = 8'd1;
wire          user_port_litedramnativeportconverter_rdata_chunk_valid;
wire          user_port_litedramnativeportconverter_rdata_converter_converter_first;
wire          user_port_litedramnativeportconverter_rdata_converter_converter_last;
reg     [2:0] user_port_litedramnativeportconverter_rdata_converter_converter_mux = 3'd0;
wire          user_port_litedramnativeportconverter_rdata_converter_converter_sink_first;
wire          user_port_litedramnativeportconverter_rdata_converter_converter_sink_last;
reg   [255:0] user_port_litedramnativeportconverter_rdata_converter_converter_sink_payload_data = 256'd0;
wire          user_port_litedramnativeportconverter_rdata_converter_converter_sink_ready;
wire          user_port_litedramnativeportconverter_rdata_converter_converter_sink_valid;
wire          user_port_litedramnativeportconverter_rdata_converter_converter_source_first;
wire          user_port_litedramnativeportconverter_rdata_converter_converter_source_last;
reg    [31:0] user_port_litedramnativeportconverter_rdata_converter_converter_source_payload_data = 32'd0;
wire          user_port_litedramnativeportconverter_rdata_converter_converter_source_payload_valid_token_count;
wire          user_port_litedramnativeportconverter_rdata_converter_converter_source_ready;
wire          user_port_litedramnativeportconverter_rdata_converter_converter_source_valid;
wire          user_port_litedramnativeportconverter_rdata_converter_sink_first;
wire          user_port_litedramnativeportconverter_rdata_converter_sink_last;
wire  [255:0] user_port_litedramnativeportconverter_rdata_converter_sink_payload_data;
wire          user_port_litedramnativeportconverter_rdata_converter_sink_ready;
wire          user_port_litedramnativeportconverter_rdata_converter_sink_valid;
wire          user_port_litedramnativeportconverter_rdata_converter_source_first;
wire          user_port_litedramnativeportconverter_rdata_converter_source_last;
wire   [31:0] user_port_litedramnativeportconverter_rdata_converter_source_payload_data;
reg           user_port_litedramnativeportconverter_rdata_converter_source_ready = 1'd0;
wire          user_port_litedramnativeportconverter_rdata_converter_source_source_first;
wire          user_port_litedramnativeportconverter_rdata_converter_source_source_last;
wire   [31:0] user_port_litedramnativeportconverter_rdata_converter_source_source_payload_data;
wire          user_port_litedramnativeportconverter_rdata_converter_source_source_ready;
wire          user_port_litedramnativeportconverter_rdata_converter_source_source_valid;
wire          user_port_litedramnativeportconverter_rdata_converter_source_valid;
reg     [2:0] user_port_litedramnativeportconverter_rdata_fifo_consume = 3'd0;
wire          user_port_litedramnativeportconverter_rdata_fifo_do_read;
wire          user_port_litedramnativeportconverter_rdata_fifo_fifo_in_first;
wire          user_port_litedramnativeportconverter_rdata_fifo_fifo_in_last;
wire  [255:0] user_port_litedramnativeportconverter_rdata_fifo_fifo_in_payload_data;
wire          user_port_litedramnativeportconverter_rdata_fifo_fifo_out_first;
wire          user_port_litedramnativeportconverter_rdata_fifo_fifo_out_last;
wire  [255:0] user_port_litedramnativeportconverter_rdata_fifo_fifo_out_payload_data;
reg     [2:0] user_port_litedramnativeportconverter_rdata_fifo_level = 3'd0;
reg     [2:0] user_port_litedramnativeportconverter_rdata_fifo_produce = 3'd0;
wire    [2:0] user_port_litedramnativeportconverter_rdata_fifo_rdport_adr;
wire  [257:0] user_port_litedramnativeportconverter_rdata_fifo_rdport_dat_r;
reg           user_port_litedramnativeportconverter_rdata_fifo_replace = 1'd0;
wire          user_port_litedramnativeportconverter_rdata_fifo_sink_first;
wire          user_port_litedramnativeportconverter_rdata_fifo_sink_last;
wire  [255:0] user_port_litedramnativeportconverter_rdata_fifo_sink_payload_data;
wire          user_port_litedramnativeportconverter_rdata_fifo_sink_ready;
wire          user_port_litedramnativeportconverter_rdata_fifo_sink_valid;
wire          user_port_litedramnativeportconverter_rdata_fifo_source_first;
wire          user_port_litedramnativeportconverter_rdata_fifo_source_last;
wire  [255:0] user_port_litedramnativeportconverter_rdata_fifo_source_payload_data;
wire          user_port_litedramnativeportconverter_rdata_fifo_source_ready;
wire          user_port_litedramnativeportconverter_rdata_fifo_source_valid;
wire  [257:0] user_port_litedramnativeportconverter_rdata_fifo_syncfifo_din;
wire  [257:0] user_port_litedramnativeportconverter_rdata_fifo_syncfifo_dout;
wire          user_port_litedramnativeportconverter_rdata_fifo_syncfifo_re;
wire          user_port_litedramnativeportconverter_rdata_fifo_syncfifo_readable;
wire          user_port_litedramnativeportconverter_rdata_fifo_syncfifo_we;
wire          user_port_litedramnativeportconverter_rdata_fifo_syncfifo_writable;
reg     [2:0] user_port_litedramnativeportconverter_rdata_fifo_wrport_adr = 3'd0;
wire  [257:0] user_port_litedramnativeportconverter_rdata_fifo_wrport_dat_r;
wire  [257:0] user_port_litedramnativeportconverter_rdata_fifo_wrport_dat_w;
wire          user_port_litedramnativeportconverter_rdata_fifo_wrport_we;
reg           user_port_litedramnativeportconverter_rdata_finished = 1'd0;
reg           user_port_litedramnativeportconverter_read_lock = 1'd0;
reg           user_port_litedramnativeportconverter_read_unlocked = 1'd0;
wire          user_port_litedramnativeportconverter_rw_collision;
reg     [7:0] user_port_litedramnativeportconverter_sel = 8'd0;
reg     [7:0] user_port_litedramnativeportconverter_sel_litedramcore_next_value3 = 8'd0;
reg           user_port_litedramnativeportconverter_sel_litedramcore_next_value_ce3 = 1'd0;
wire          user_port_litedramnativeportconverter_wdata_buffer_pipe_valid_sink_first;
wire          user_port_litedramnativeportconverter_wdata_buffer_pipe_valid_sink_last;
wire  [255:0] user_port_litedramnativeportconverter_wdata_buffer_pipe_valid_sink_payload_data;
wire   [31:0] user_port_litedramnativeportconverter_wdata_buffer_pipe_valid_sink_payload_we;
wire          user_port_litedramnativeportconverter_wdata_buffer_pipe_valid_sink_ready;
wire          user_port_litedramnativeportconverter_wdata_buffer_pipe_valid_sink_valid;
reg           user_port_litedramnativeportconverter_wdata_buffer_pipe_valid_source_first = 1'd0;
reg           user_port_litedramnativeportconverter_wdata_buffer_pipe_valid_source_last = 1'd0;
reg   [255:0] user_port_litedramnativeportconverter_wdata_buffer_pipe_valid_source_payload_data = 256'd0;
reg    [31:0] user_port_litedramnativeportconverter_wdata_buffer_pipe_valid_source_payload_we = 32'd0;
wire          user_port_litedramnativeportconverter_wdata_buffer_pipe_valid_source_ready;
reg           user_port_litedramnativeportconverter_wdata_buffer_pipe_valid_source_valid = 1'd0;
reg           user_port_litedramnativeportconverter_wdata_buffer_sink_sink_first = 1'd0;
reg           user_port_litedramnativeportconverter_wdata_buffer_sink_sink_last = 1'd0;
wire  [255:0] user_port_litedramnativeportconverter_wdata_buffer_sink_sink_payload_data;
wire   [31:0] user_port_litedramnativeportconverter_wdata_buffer_sink_sink_payload_we;
wire          user_port_litedramnativeportconverter_wdata_buffer_sink_sink_ready;
wire          user_port_litedramnativeportconverter_wdata_buffer_sink_sink_valid;
wire          user_port_litedramnativeportconverter_wdata_buffer_source_source_first;
wire          user_port_litedramnativeportconverter_wdata_buffer_source_source_last;
wire  [255:0] user_port_litedramnativeportconverter_wdata_buffer_source_source_payload_data;
wire   [31:0] user_port_litedramnativeportconverter_wdata_buffer_source_source_payload_we;
wire          user_port_litedramnativeportconverter_wdata_buffer_source_source_ready;
wire          user_port_litedramnativeportconverter_wdata_buffer_source_source_valid;
reg     [7:0] user_port_litedramnativeportconverter_wdata_chunk = 8'd1;
wire          user_port_litedramnativeportconverter_wdata_chunk_valid;
reg     [2:0] user_port_litedramnativeportconverter_wdata_converter_converter_demux = 3'd0;
wire          user_port_litedramnativeportconverter_wdata_converter_converter_load_part;
wire          user_port_litedramnativeportconverter_wdata_converter_converter_sink_first;
wire          user_port_litedramnativeportconverter_wdata_converter_converter_sink_last;
wire   [35:0] user_port_litedramnativeportconverter_wdata_converter_converter_sink_payload_data;
wire          user_port_litedramnativeportconverter_wdata_converter_converter_sink_ready;
wire          user_port_litedramnativeportconverter_wdata_converter_converter_sink_valid;
reg           user_port_litedramnativeportconverter_wdata_converter_converter_source_first = 1'd0;
reg           user_port_litedramnativeportconverter_wdata_converter_converter_source_last = 1'd0;
reg   [287:0] user_port_litedramnativeportconverter_wdata_converter_converter_source_payload_data = 288'd0;
reg     [3:0] user_port_litedramnativeportconverter_wdata_converter_converter_source_payload_valid_token_count = 4'd0;
wire          user_port_litedramnativeportconverter_wdata_converter_converter_source_ready;
wire          user_port_litedramnativeportconverter_wdata_converter_converter_source_valid;
reg           user_port_litedramnativeportconverter_wdata_converter_converter_strobe_all = 1'd0;
reg           user_port_litedramnativeportconverter_wdata_converter_sink_first = 1'd0;
reg           user_port_litedramnativeportconverter_wdata_converter_sink_last = 1'd0;
reg    [31:0] user_port_litedramnativeportconverter_wdata_converter_sink_payload_data = 32'd0;
reg     [3:0] user_port_litedramnativeportconverter_wdata_converter_sink_payload_we = 4'd0;
wire          user_port_litedramnativeportconverter_wdata_converter_sink_ready;
reg           user_port_litedramnativeportconverter_wdata_converter_sink_valid = 1'd0;
wire          user_port_litedramnativeportconverter_wdata_converter_source_first;
wire          user_port_litedramnativeportconverter_wdata_converter_source_last;
reg   [255:0] user_port_litedramnativeportconverter_wdata_converter_source_payload_data = 256'd0;
reg    [31:0] user_port_litedramnativeportconverter_wdata_converter_source_payload_we = 32'd0;
wire          user_port_litedramnativeportconverter_wdata_converter_source_ready;
wire          user_port_litedramnativeportconverter_wdata_converter_source_source_first;
wire          user_port_litedramnativeportconverter_wdata_converter_source_source_last;
wire  [287:0] user_port_litedramnativeportconverter_wdata_converter_source_source_payload_data;
wire          user_port_litedramnativeportconverter_wdata_converter_source_source_ready;
wire          user_port_litedramnativeportconverter_wdata_converter_source_source_valid;
wire          user_port_litedramnativeportconverter_wdata_converter_source_valid;
reg     [2:0] user_port_litedramnativeportconverter_wdata_fifo_consume = 3'd0;
wire          user_port_litedramnativeportconverter_wdata_fifo_do_read;
wire          user_port_litedramnativeportconverter_wdata_fifo_fifo_in_first;
wire          user_port_litedramnativeportconverter_wdata_fifo_fifo_in_last;
wire   [31:0] user_port_litedramnativeportconverter_wdata_fifo_fifo_in_payload_data;
wire    [3:0] user_port_litedramnativeportconverter_wdata_fifo_fifo_in_payload_we;
wire          user_port_litedramnativeportconverter_wdata_fifo_fifo_out_first;
wire          user_port_litedramnativeportconverter_wdata_fifo_fifo_out_last;
wire   [31:0] user_port_litedramnativeportconverter_wdata_fifo_fifo_out_payload_data;
wire    [3:0] user_port_litedramnativeportconverter_wdata_fifo_fifo_out_payload_we;
reg     [2:0] user_port_litedramnativeportconverter_wdata_fifo_level = 3'd0;
reg     [2:0] user_port_litedramnativeportconverter_wdata_fifo_produce = 3'd0;
wire    [2:0] user_port_litedramnativeportconverter_wdata_fifo_rdport_adr;
wire   [37:0] user_port_litedramnativeportconverter_wdata_fifo_rdport_dat_r;
reg           user_port_litedramnativeportconverter_wdata_fifo_replace = 1'd0;
wire          user_port_litedramnativeportconverter_wdata_fifo_sink_first;
wire          user_port_litedramnativeportconverter_wdata_fifo_sink_last;
wire   [31:0] user_port_litedramnativeportconverter_wdata_fifo_sink_payload_data;
wire    [3:0] user_port_litedramnativeportconverter_wdata_fifo_sink_payload_we;
wire          user_port_litedramnativeportconverter_wdata_fifo_sink_ready;
wire          user_port_litedramnativeportconverter_wdata_fifo_sink_valid;
wire          user_port_litedramnativeportconverter_wdata_fifo_source_first;
wire          user_port_litedramnativeportconverter_wdata_fifo_source_last;
wire   [31:0] user_port_litedramnativeportconverter_wdata_fifo_source_payload_data;
wire    [3:0] user_port_litedramnativeportconverter_wdata_fifo_source_payload_we;
reg           user_port_litedramnativeportconverter_wdata_fifo_source_ready = 1'd0;
wire          user_port_litedramnativeportconverter_wdata_fifo_source_valid;
wire   [37:0] user_port_litedramnativeportconverter_wdata_fifo_syncfifo_din;
wire   [37:0] user_port_litedramnativeportconverter_wdata_fifo_syncfifo_dout;
wire          user_port_litedramnativeportconverter_wdata_fifo_syncfifo_re;
wire          user_port_litedramnativeportconverter_wdata_fifo_syncfifo_readable;
wire          user_port_litedramnativeportconverter_wdata_fifo_syncfifo_we;
wire          user_port_litedramnativeportconverter_wdata_fifo_syncfifo_writable;
reg     [2:0] user_port_litedramnativeportconverter_wdata_fifo_wrport_adr = 3'd0;
wire   [37:0] user_port_litedramnativeportconverter_wdata_fifo_wrport_dat_r;
wire   [37:0] user_port_litedramnativeportconverter_wdata_fifo_wrport_dat_w;
wire          user_port_litedramnativeportconverter_wdata_fifo_wrport_we;
wire          user_port_litedramnativeportconverter_wdata_finished;
reg    [31:0] user_port_litedramnativeportconverter_wdata_sel = 32'd0;
wire          user_port_new_port_cmd_last;
wire   [27:0] user_port_new_port_cmd_payload_addr;
wire          user_port_new_port_cmd_payload_we;
reg           user_port_new_port_cmd_ready = 1'd0;
reg           user_port_new_port_cmd_valid = 1'd0;
wire          user_port_new_port_flush;
reg    [31:0] user_port_new_port_rdata_payload_data = 32'd0;
wire          user_port_new_port_rdata_ready;
reg           user_port_new_port_rdata_valid = 1'd0;
reg           user_port_new_port_wdata_first = 1'd0;
reg           user_port_new_port_wdata_last = 1'd0;
wire   [31:0] user_port_new_port_wdata_payload_data;
wire    [3:0] user_port_new_port_wdata_payload_we;
wire          user_port_new_port_wdata_ready;
reg           user_port_new_port_wdata_valid = 1'd0;
reg    [24:0] user_port_port_cmd_payload_addr = 25'd0;
reg           user_port_port_cmd_payload_we = 1'd0;
wire          user_port_port_cmd_ready;
reg           user_port_port_cmd_valid = 1'd0;
reg           user_port_port_rdata_first = 1'd0;
reg           user_port_port_rdata_last = 1'd0;
wire  [255:0] user_port_port_rdata_payload_data;
wire          user_port_port_rdata_ready;
wire          user_port_port_rdata_valid;
wire          user_port_port_wdata_first;
wire          user_port_port_wdata_last;
wire  [255:0] user_port_port_wdata_payload_data;
wire   [31:0] user_port_port_wdata_payload_we;
wire          user_port_port_wdata_ready;
wire          user_port_port_wdata_valid;
wire          wait_1;
reg           wb_port_ack = 1'd0;
wire   [27:0] wb_port_adr;
wire          wb_port_cyc;
reg    [31:0] wb_port_dat_r = 32'd0;
wire   [31:0] wb_port_dat_w;
reg           wb_port_err = 1'd0;
wire    [3:0] wb_port_sel;
wire          wb_port_stb;
wire          wb_port_we;
wire          we;
reg     [1:0] wishbone2csr_next_state = 2'd0;
reg     [1:0] wishbone2csr_state = 2'd0;
reg           wishbone2native_aborted = 1'd0;
reg           wishbone2native_aborted_litedramwishbone2native1_next_value = 1'd0;
reg           wishbone2native_aborted_litedramwishbone2native1_next_value_ce = 1'd0;
reg           wishbone2native_is_ongoing = 1'd0;
wire          xilinxasyncresetsynchronizerimpl0;
wire          xilinxasyncresetsynchronizerimpl0_rst_meta;
wire          xilinxasyncresetsynchronizerimpl1;
wire          xilinxasyncresetsynchronizerimpl1_rst_meta;
wire          xilinxasyncresetsynchronizerimpl2;
wire          xilinxasyncresetsynchronizerimpl2_expr;
wire          xilinxasyncresetsynchronizerimpl2_rst_meta;
wire          xilinxasyncresetsynchronizerimpl3;
wire          xilinxasyncresetsynchronizerimpl3_expr;
wire          xilinxasyncresetsynchronizerimpl3_rst_meta;
(* async_reg = "true", mr_ff = "true", dont_touch = "true" *)
reg           xilinxmultiregimpl0 = 1'd0;
(* async_reg = "true", dont_touch = "true" *)
reg           xilinxmultiregimpl1 = 1'd0;

//------------------------------------------------------------------------------
// Combinatorial Logic
//------------------------------------------------------------------------------

assign litedramcore_reset = (litedramcore_soc_rst | litedramcore_cpu_rst);
assign init_done = init_done_storage;
assign init_error = init_error_storage;
assign user_clk = sys_clk;
assign user_rst = sys_rst;
assign wb_port_adr = user_port_wishbone_0_adr;
assign wb_port_dat_w = user_port_wishbone_0_dat_w;
assign user_port_wishbone_0_dat_r = wb_port_dat_r;
assign wb_port_sel = user_port_wishbone_0_sel;
assign wb_port_cyc = (user_port_wishbone_0_cyc & user_enable);
assign wb_port_stb = (user_port_wishbone_0_stb & user_enable);
assign user_port_wishbone_0_ack = (wb_port_ack & user_enable);
assign wb_port_we = user_port_wishbone_0_we;
assign user_port_wishbone_0_err = wb_port_err;
always @(*) begin
    crg_rst <= 1'd0;
    if (litedramcore_soc_rst) begin
        crg_rst <= 1'd1;
    end
end
assign litedramcore_bus_error = error;
always @(*) begin
    litedramcore_interrupt <= 32'd0;
    litedramcore_interrupt[0] <= litedramcore_irq;
    litedramcore_interrupt[1] <= uart_irq;
end
assign shared_adr = rhs_self0;
assign shared_dat_w = rhs_self1;
assign shared_sel = rhs_self2;
assign shared_cyc = rhs_self3;
assign shared_stb = rhs_self4;
assign shared_we = rhs_self5;
assign shared_cti = rhs_self6;
assign shared_bte = rhs_self7;
assign litedramcore_ibus_dat_r = shared_dat_r;
assign litedramcore_dbus_dat_r = shared_dat_r;
assign litedramcore_ibus_ack = (shared_ack & (grant == 1'd0));
assign litedramcore_dbus_ack = (shared_ack & (grant == 1'd1));
assign litedramcore_ibus_err = (shared_err & (grant == 1'd0));
assign litedramcore_dbus_err = (shared_err & (grant == 1'd1));
assign request = {litedramcore_dbus_cyc, litedramcore_ibus_cyc};
always @(*) begin
    slave_sel <= 4'd0;
    slave_sel[0] <= (shared_adr[29:14] == 1'd0);
    slave_sel[1] <= (shared_adr[29:11] == 16'd32768);
    slave_sel[2] <= (shared_adr[29:22] == 7'd64);
    slave_sel[3] <= (shared_adr[29:14] == 16'd61440);
end
assign litedramcore_litedramcore_ram_bus_adr = shared_adr;
assign litedramcore_litedramcore_ram_bus_dat_w = shared_dat_w;
assign litedramcore_litedramcore_ram_bus_sel = shared_sel;
assign litedramcore_litedramcore_ram_bus_stb = shared_stb;
assign litedramcore_litedramcore_ram_bus_we = shared_we;
assign litedramcore_litedramcore_ram_bus_cti = shared_cti;
assign litedramcore_litedramcore_ram_bus_bte = shared_bte;
assign litedramcore_ram_bus_ram_bus_adr = shared_adr;
assign litedramcore_ram_bus_ram_bus_dat_w = shared_dat_w;
assign litedramcore_ram_bus_ram_bus_sel = shared_sel;
assign litedramcore_ram_bus_ram_bus_stb = shared_stb;
assign litedramcore_ram_bus_ram_bus_we = shared_we;
assign litedramcore_ram_bus_ram_bus_cti = shared_cti;
assign litedramcore_ram_bus_ram_bus_bte = shared_bte;
assign litedramcore_wb_sdram_adr = shared_adr;
assign litedramcore_wb_sdram_dat_w = shared_dat_w;
assign litedramcore_wb_sdram_sel = shared_sel;
assign litedramcore_wb_sdram_stb = shared_stb;
assign litedramcore_wb_sdram_we = shared_we;
assign litedramcore_wb_sdram_cti = shared_cti;
assign litedramcore_wb_sdram_bte = shared_bte;
assign interface0_adr = shared_adr;
assign interface0_dat_w = shared_dat_w;
assign interface0_sel = shared_sel;
assign interface0_stb = shared_stb;
assign interface0_we = shared_we;
assign interface0_cti = shared_cti;
assign interface0_bte = shared_bte;
assign litedramcore_litedramcore_ram_bus_cyc = (shared_cyc & slave_sel[0]);
assign litedramcore_ram_bus_ram_bus_cyc = (shared_cyc & slave_sel[1]);
assign litedramcore_wb_sdram_cyc = (shared_cyc & slave_sel[2]);
assign interface0_cyc = (shared_cyc & slave_sel[3]);
always @(*) begin
    shared_ack <= 1'd0;
    shared_ack <= (((litedramcore_litedramcore_ram_bus_ack | litedramcore_ram_bus_ram_bus_ack) | litedramcore_wb_sdram_ack) | interface0_ack);
    if (done) begin
        shared_ack <= 1'd1;
    end
end
assign shared_err = (((litedramcore_litedramcore_ram_bus_err | litedramcore_ram_bus_ram_bus_err) | litedramcore_wb_sdram_err) | interface0_err);
always @(*) begin
    shared_dat_r <= 32'd0;
    shared_dat_r <= (((({32{slave_sel_r[0]}} & litedramcore_litedramcore_ram_bus_dat_r) | ({32{slave_sel_r[1]}} & litedramcore_ram_bus_ram_bus_dat_r)) | ({32{slave_sel_r[2]}} & litedramcore_wb_sdram_dat_r)) | ({32{slave_sel_r[3]}} & interface0_dat_r));
    if (done) begin
        shared_dat_r <= 32'd4294967295;
    end
end
assign wait_1 = ((shared_stb & shared_cyc) & (~shared_ack));
always @(*) begin
    error <= 1'd0;
    if (done) begin
        error <= 1'd1;
    end
end
assign done = (count == 1'd0);
assign litedramcore_bus_errors_status = litedramcore_bus_errors;
assign litedramcore_litedramcore_adr = litedramcore_litedramcore_ram_bus_adr[13:0];
assign litedramcore_litedramcore_ram_bus_dat_r = litedramcore_litedramcore_dat_r;
always @(*) begin
    litedramcore_ram_we <= 4'd0;
    litedramcore_ram_we[0] <= (((litedramcore_ram_bus_ram_bus_cyc & litedramcore_ram_bus_ram_bus_stb) & litedramcore_ram_bus_ram_bus_we) & litedramcore_ram_bus_ram_bus_sel[0]);
    litedramcore_ram_we[1] <= (((litedramcore_ram_bus_ram_bus_cyc & litedramcore_ram_bus_ram_bus_stb) & litedramcore_ram_bus_ram_bus_we) & litedramcore_ram_bus_ram_bus_sel[1]);
    litedramcore_ram_we[2] <= (((litedramcore_ram_bus_ram_bus_cyc & litedramcore_ram_bus_ram_bus_stb) & litedramcore_ram_bus_ram_bus_we) & litedramcore_ram_bus_ram_bus_sel[2]);
    litedramcore_ram_we[3] <= (((litedramcore_ram_bus_ram_bus_cyc & litedramcore_ram_bus_ram_bus_stb) & litedramcore_ram_bus_ram_bus_we) & litedramcore_ram_bus_ram_bus_sel[3]);
end
assign litedramcore_ram_adr = litedramcore_ram_bus_ram_bus_adr[10:0];
assign litedramcore_ram_bus_ram_bus_dat_r = litedramcore_ram_dat_r;
assign litedramcore_ram_dat_w = litedramcore_ram_bus_ram_bus_dat_w;
assign litedramcore_zero_trigger = (litedramcore_value == 1'd0);
assign litedramcore_zero0 = litedramcore_zero_status;
assign litedramcore_zero1 = litedramcore_zero_pending;
always @(*) begin
    litedramcore_zero_clear <= 1'd0;
    if ((litedramcore_pending_re & litedramcore_pending_r)) begin
        litedramcore_zero_clear <= 1'd1;
    end
end
assign litedramcore_irq = (litedramcore_pending_status & litedramcore_enable_storage);
assign litedramcore_zero_status = litedramcore_zero_trigger;
always @(*) begin
    rs232phytx_next_state <= 1'd0;
    rs232phytx_next_state <= rs232phytx_state;
    case (rs232phytx_state)
        1'd1: begin
            if (tx_tick) begin
                if ((tx_count == 4'd9)) begin
                    rs232phytx_next_state <= 1'd0;
                end
            end
        end
        default: begin
            if (tx_sink_valid) begin
                rs232phytx_next_state <= 1'd1;
            end
        end
    endcase
end
always @(*) begin
    tx_enable <= 1'd0;
    case (rs232phytx_state)
        1'd1: begin
            tx_enable <= 1'd1;
        end
        default: begin
        end
    endcase
end
always @(*) begin
    tx_count_rs232phytx_next_value0 <= 4'd0;
    case (rs232phytx_state)
        1'd1: begin
            if (tx_tick) begin
                tx_count_rs232phytx_next_value0 <= (tx_count + 1'd1);
            end
        end
        default: begin
            tx_count_rs232phytx_next_value0 <= 1'd0;
        end
    endcase
end
always @(*) begin
    tx_count_rs232phytx_next_value_ce0 <= 1'd0;
    case (rs232phytx_state)
        1'd1: begin
            if (tx_tick) begin
                tx_count_rs232phytx_next_value_ce0 <= 1'd1;
            end
        end
        default: begin
            tx_count_rs232phytx_next_value_ce0 <= 1'd1;
        end
    endcase
end
always @(*) begin
    obj_uart_tx_rs232phytx_next_value1 <= 1'd0;
    case (rs232phytx_state)
        1'd1: begin
            if (tx_tick) begin
                obj_uart_tx_rs232phytx_next_value1 <= tx_data[0];
            end
        end
        default: begin
            obj_uart_tx_rs232phytx_next_value1 <= 1'd1;
            if (tx_sink_valid) begin
                obj_uart_tx_rs232phytx_next_value1 <= 1'd0;
            end
        end
    endcase
end
always @(*) begin
    obj_uart_tx_rs232phytx_next_value_ce1 <= 1'd0;
    case (rs232phytx_state)
        1'd1: begin
            if (tx_tick) begin
                obj_uart_tx_rs232phytx_next_value_ce1 <= 1'd1;
            end
        end
        default: begin
            obj_uart_tx_rs232phytx_next_value_ce1 <= 1'd1;
            if (tx_sink_valid) begin
                obj_uart_tx_rs232phytx_next_value_ce1 <= 1'd1;
            end
        end
    endcase
end
always @(*) begin
    tx_sink_ready <= 1'd0;
    case (rs232phytx_state)
        1'd1: begin
            if (tx_tick) begin
                if ((tx_count == 4'd9)) begin
                    tx_sink_ready <= 1'd1;
                end
            end
        end
        default: begin
        end
    endcase
end
always @(*) begin
    tx_data_rs232phytx_next_value2 <= 8'd0;
    case (rs232phytx_state)
        1'd1: begin
            if (tx_tick) begin
                tx_data_rs232phytx_next_value2 <= {1'd1, tx_data[7:1]};
            end
        end
        default: begin
            if (tx_sink_valid) begin
                tx_data_rs232phytx_next_value2 <= tx_sink_payload_data;
            end
        end
    endcase
end
always @(*) begin
    tx_data_rs232phytx_next_value_ce2 <= 1'd0;
    case (rs232phytx_state)
        1'd1: begin
            if (tx_tick) begin
                tx_data_rs232phytx_next_value_ce2 <= 1'd1;
            end
        end
        default: begin
            if (tx_sink_valid) begin
                tx_data_rs232phytx_next_value_ce2 <= 1'd1;
            end
        end
    endcase
end
always @(*) begin
    rs232phyrx_next_state <= 1'd0;
    rs232phyrx_next_state <= rs232phyrx_state;
    case (rs232phyrx_state)
        1'd1: begin
            if (rx_tick) begin
                if ((rx_count == 4'd9)) begin
                    rs232phyrx_next_state <= 1'd0;
                end
            end
        end
        default: begin
            if (((rx_rx == 1'd0) & (rx_rx_d == 1'd1))) begin
                rs232phyrx_next_state <= 1'd1;
            end
        end
    endcase
end
always @(*) begin
    rx_source_payload_data <= 8'd0;
    case (rs232phyrx_state)
        1'd1: begin
            if (rx_tick) begin
                if ((rx_count == 4'd9)) begin
                    rx_source_payload_data <= rx_data;
                end
            end
        end
        default: begin
        end
    endcase
end
always @(*) begin
    rx_enable <= 1'd0;
    case (rs232phyrx_state)
        1'd1: begin
            rx_enable <= 1'd1;
        end
        default: begin
        end
    endcase
end
always @(*) begin
    rx_count_rs232phyrx_next_value0 <= 4'd0;
    case (rs232phyrx_state)
        1'd1: begin
            if (rx_tick) begin
                rx_count_rs232phyrx_next_value0 <= (rx_count + 1'd1);
            end
        end
        default: begin
            rx_count_rs232phyrx_next_value0 <= 1'd0;
        end
    endcase
end
always @(*) begin
    rx_count_rs232phyrx_next_value_ce0 <= 1'd0;
    case (rs232phyrx_state)
        1'd1: begin
            if (rx_tick) begin
                rx_count_rs232phyrx_next_value_ce0 <= 1'd1;
            end
        end
        default: begin
            rx_count_rs232phyrx_next_value_ce0 <= 1'd1;
        end
    endcase
end
always @(*) begin
    rx_data_rs232phyrx_next_value1 <= 8'd0;
    case (rs232phyrx_state)
        1'd1: begin
            if (rx_tick) begin
                rx_data_rs232phyrx_next_value1 <= {rx_rx, rx_data[7:1]};
            end
        end
        default: begin
        end
    endcase
end
always @(*) begin
    rx_data_rs232phyrx_next_value_ce1 <= 1'd0;
    case (rs232phyrx_state)
        1'd1: begin
            if (rx_tick) begin
                rx_data_rs232phyrx_next_value_ce1 <= 1'd1;
            end
        end
        default: begin
        end
    endcase
end
always @(*) begin
    rx_source_valid <= 1'd0;
    case (rs232phyrx_state)
        1'd1: begin
            if (rx_tick) begin
                if ((rx_count == 4'd9)) begin
                    rx_source_valid <= (rx_rx == 1'd1);
                end
            end
        end
        default: begin
        end
    endcase
end
assign uart_uart_sink_valid = rx_source_valid;
assign rx_source_ready = uart_uart_sink_ready;
assign uart_uart_sink_first = rx_source_first;
assign uart_uart_sink_last = rx_source_last;
assign uart_uart_sink_payload_data = rx_source_payload_data;
assign tx_sink_valid = uart_uart_source_valid;
assign uart_uart_source_ready = tx_sink_ready;
assign tx_sink_first = uart_uart_source_first;
assign tx_sink_last = uart_uart_source_last;
assign tx_sink_payload_data = uart_uart_source_payload_data;
assign uart_tx_fifo_sink_valid = uart_rxtx_re;
assign uart_tx_fifo_sink_payload_data = uart_rxtx_r;
assign uart_uart_source_valid = uart_tx_fifo_source_valid;
assign uart_tx_fifo_source_ready = uart_uart_source_ready;
assign uart_uart_source_first = uart_tx_fifo_source_first;
assign uart_uart_source_last = uart_tx_fifo_source_last;
assign uart_uart_source_payload_data = uart_tx_fifo_source_payload_data;
assign uart_txfull_status = (~uart_tx_fifo_sink_ready);
assign uart_txempty_status = (~uart_tx_fifo_source_valid);
assign uart_tx_trigger = uart_tx_fifo_sink_ready;
assign uart_rx_fifo_sink_valid = uart_uart_sink_valid;
assign uart_uart_sink_ready = uart_rx_fifo_sink_ready;
assign uart_rx_fifo_sink_first = uart_uart_sink_first;
assign uart_rx_fifo_sink_last = uart_uart_sink_last;
assign uart_rx_fifo_sink_payload_data = uart_uart_sink_payload_data;
assign uart_rxtx_w = uart_rx_fifo_source_payload_data;
assign uart_rx_fifo_source_ready = (uart_rx_clear | (1'd0 & uart_rxtx_we));
assign uart_rxempty_status = (~uart_rx_fifo_source_valid);
assign uart_rxfull_status = (~uart_rx_fifo_sink_ready);
assign uart_rx_trigger = uart_rx_fifo_source_valid;
assign uart_tx0 = uart_tx_status;
assign uart_tx1 = uart_tx_pending;
always @(*) begin
    uart_tx_clear <= 1'd0;
    if ((uart_pending_re & uart_pending_r[0])) begin
        uart_tx_clear <= 1'd1;
    end
end
assign uart_rx0 = uart_rx_status;
assign uart_rx1 = uart_rx_pending;
always @(*) begin
    uart_rx_clear <= 1'd0;
    if ((uart_pending_re & uart_pending_r[1])) begin
        uart_rx_clear <= 1'd1;
    end
end
assign uart_irq = ((uart_pending_status[0] & uart_enable_storage[0]) | (uart_pending_status[1] & uart_enable_storage[1]));
assign uart_tx_status = uart_tx_trigger;
assign uart_rx_status = uart_rx_trigger;
assign uart_tx_fifo_syncfifo_din = {uart_tx_fifo_fifo_in_last, uart_tx_fifo_fifo_in_first, uart_tx_fifo_fifo_in_payload_data};
assign {uart_tx_fifo_fifo_out_last, uart_tx_fifo_fifo_out_first, uart_tx_fifo_fifo_out_payload_data} = uart_tx_fifo_syncfifo_dout;
assign {uart_tx_fifo_fifo_out_last, uart_tx_fifo_fifo_out_first, uart_tx_fifo_fifo_out_payload_data} = uart_tx_fifo_syncfifo_dout;
assign {uart_tx_fifo_fifo_out_last, uart_tx_fifo_fifo_out_first, uart_tx_fifo_fifo_out_payload_data} = uart_tx_fifo_syncfifo_dout;
assign uart_tx_fifo_sink_ready = uart_tx_fifo_syncfifo_writable;
assign uart_tx_fifo_syncfifo_we = uart_tx_fifo_sink_valid;
assign uart_tx_fifo_fifo_in_first = uart_tx_fifo_sink_first;
assign uart_tx_fifo_fifo_in_last = uart_tx_fifo_sink_last;
assign uart_tx_fifo_fifo_in_payload_data = uart_tx_fifo_sink_payload_data;
assign uart_tx_fifo_source_valid = uart_tx_fifo_readable;
assign uart_tx_fifo_source_first = uart_tx_fifo_fifo_out_first;
assign uart_tx_fifo_source_last = uart_tx_fifo_fifo_out_last;
assign uart_tx_fifo_source_payload_data = uart_tx_fifo_fifo_out_payload_data;
assign uart_tx_fifo_re = uart_tx_fifo_source_ready;
assign uart_tx_fifo_syncfifo_re = (uart_tx_fifo_syncfifo_readable & ((~uart_tx_fifo_readable) | uart_tx_fifo_re));
assign uart_tx_fifo_level1 = (uart_tx_fifo_level0 + uart_tx_fifo_readable);
always @(*) begin
    uart_tx_fifo_wrport_adr <= 4'd0;
    if (uart_tx_fifo_replace) begin
        uart_tx_fifo_wrport_adr <= (uart_tx_fifo_produce - 1'd1);
    end else begin
        uart_tx_fifo_wrport_adr <= uart_tx_fifo_produce;
    end
end
assign uart_tx_fifo_wrport_dat_w = uart_tx_fifo_syncfifo_din;
assign uart_tx_fifo_wrport_we = (uart_tx_fifo_syncfifo_we & (uart_tx_fifo_syncfifo_writable | uart_tx_fifo_replace));
assign uart_tx_fifo_do_read = (uart_tx_fifo_syncfifo_readable & uart_tx_fifo_syncfifo_re);
assign uart_tx_fifo_rdport_adr = uart_tx_fifo_consume;
assign uart_tx_fifo_syncfifo_dout = uart_tx_fifo_rdport_dat_r;
assign uart_tx_fifo_rdport_re = uart_tx_fifo_do_read;
assign uart_tx_fifo_syncfifo_writable = (uart_tx_fifo_level0 != 5'd16);
assign uart_tx_fifo_syncfifo_readable = (uart_tx_fifo_level0 != 1'd0);
assign uart_rx_fifo_syncfifo_din = {uart_rx_fifo_fifo_in_last, uart_rx_fifo_fifo_in_first, uart_rx_fifo_fifo_in_payload_data};
assign {uart_rx_fifo_fifo_out_last, uart_rx_fifo_fifo_out_first, uart_rx_fifo_fifo_out_payload_data} = uart_rx_fifo_syncfifo_dout;
assign {uart_rx_fifo_fifo_out_last, uart_rx_fifo_fifo_out_first, uart_rx_fifo_fifo_out_payload_data} = uart_rx_fifo_syncfifo_dout;
assign {uart_rx_fifo_fifo_out_last, uart_rx_fifo_fifo_out_first, uart_rx_fifo_fifo_out_payload_data} = uart_rx_fifo_syncfifo_dout;
assign uart_rx_fifo_sink_ready = uart_rx_fifo_syncfifo_writable;
assign uart_rx_fifo_syncfifo_we = uart_rx_fifo_sink_valid;
assign uart_rx_fifo_fifo_in_first = uart_rx_fifo_sink_first;
assign uart_rx_fifo_fifo_in_last = uart_rx_fifo_sink_last;
assign uart_rx_fifo_fifo_in_payload_data = uart_rx_fifo_sink_payload_data;
assign uart_rx_fifo_source_valid = uart_rx_fifo_readable;
assign uart_rx_fifo_source_first = uart_rx_fifo_fifo_out_first;
assign uart_rx_fifo_source_last = uart_rx_fifo_fifo_out_last;
assign uart_rx_fifo_source_payload_data = uart_rx_fifo_fifo_out_payload_data;
assign uart_rx_fifo_re = uart_rx_fifo_source_ready;
assign uart_rx_fifo_syncfifo_re = (uart_rx_fifo_syncfifo_readable & ((~uart_rx_fifo_readable) | uart_rx_fifo_re));
assign uart_rx_fifo_level1 = (uart_rx_fifo_level0 + uart_rx_fifo_readable);
always @(*) begin
    uart_rx_fifo_wrport_adr <= 4'd0;
    if (uart_rx_fifo_replace) begin
        uart_rx_fifo_wrport_adr <= (uart_rx_fifo_produce - 1'd1);
    end else begin
        uart_rx_fifo_wrport_adr <= uart_rx_fifo_produce;
    end
end
assign uart_rx_fifo_wrport_dat_w = uart_rx_fifo_syncfifo_din;
assign uart_rx_fifo_wrport_we = (uart_rx_fifo_syncfifo_we & (uart_rx_fifo_syncfifo_writable | uart_rx_fifo_replace));
assign uart_rx_fifo_do_read = (uart_rx_fifo_syncfifo_readable & uart_rx_fifo_syncfifo_re);
assign uart_rx_fifo_rdport_adr = uart_rx_fifo_consume;
assign uart_rx_fifo_syncfifo_dout = uart_rx_fifo_rdport_dat_r;
assign uart_rx_fifo_rdport_re = uart_rx_fifo_do_read;
assign uart_rx_fifo_syncfifo_writable = (uart_rx_fifo_level0 != 5'd16);
assign uart_rx_fifo_syncfifo_readable = (uart_rx_fifo_level0 != 1'd0);
assign crg_reset = (rst | crg_rst);
assign pll_locked = crg_locked;
assign crg_clkin = clk;
assign iodelay_clk = crg_clkout_buf0;
assign sys_clk = crg_clkout_buf1;
assign sys4x_clk = crg_clkout_buf2;
assign sys4x_dqs_clk = crg_clkout_buf3;
assign ddram_ba = k7ddrphy_pads_ba;
assign k7ddrphy_dqs_oe_delay_tappeddelayline = ((k7ddrphy_dqs_preamble | k7ddrphy_dqs_oe) | k7ddrphy_dqs_postamble);
assign k7ddrphy_dq_oe_delay_tappeddelayline = ((k7ddrphy_dqs_preamble | k7ddrphy_dq_oe) | k7ddrphy_dqs_postamble);
always @(*) begin
    k7ddrphy_dfi_p0_rddata <= 64'd0;
    k7ddrphy_dfi_p0_rddata[0] <= k7ddrphy_bitslip04[0];
    k7ddrphy_dfi_p0_rddata[32] <= k7ddrphy_bitslip04[1];
    k7ddrphy_dfi_p0_rddata[1] <= k7ddrphy_bitslip14[0];
    k7ddrphy_dfi_p0_rddata[33] <= k7ddrphy_bitslip14[1];
    k7ddrphy_dfi_p0_rddata[2] <= k7ddrphy_bitslip24[0];
    k7ddrphy_dfi_p0_rddata[34] <= k7ddrphy_bitslip24[1];
    k7ddrphy_dfi_p0_rddata[3] <= k7ddrphy_bitslip34[0];
    k7ddrphy_dfi_p0_rddata[35] <= k7ddrphy_bitslip34[1];
    k7ddrphy_dfi_p0_rddata[4] <= k7ddrphy_bitslip42[0];
    k7ddrphy_dfi_p0_rddata[36] <= k7ddrphy_bitslip42[1];
    k7ddrphy_dfi_p0_rddata[5] <= k7ddrphy_bitslip52[0];
    k7ddrphy_dfi_p0_rddata[37] <= k7ddrphy_bitslip52[1];
    k7ddrphy_dfi_p0_rddata[6] <= k7ddrphy_bitslip62[0];
    k7ddrphy_dfi_p0_rddata[38] <= k7ddrphy_bitslip62[1];
    k7ddrphy_dfi_p0_rddata[7] <= k7ddrphy_bitslip72[0];
    k7ddrphy_dfi_p0_rddata[39] <= k7ddrphy_bitslip72[1];
    k7ddrphy_dfi_p0_rddata[8] <= k7ddrphy_bitslip82[0];
    k7ddrphy_dfi_p0_rddata[40] <= k7ddrphy_bitslip82[1];
    k7ddrphy_dfi_p0_rddata[9] <= k7ddrphy_bitslip92[0];
    k7ddrphy_dfi_p0_rddata[41] <= k7ddrphy_bitslip92[1];
    k7ddrphy_dfi_p0_rddata[10] <= k7ddrphy_bitslip102[0];
    k7ddrphy_dfi_p0_rddata[42] <= k7ddrphy_bitslip102[1];
    k7ddrphy_dfi_p0_rddata[11] <= k7ddrphy_bitslip112[0];
    k7ddrphy_dfi_p0_rddata[43] <= k7ddrphy_bitslip112[1];
    k7ddrphy_dfi_p0_rddata[12] <= k7ddrphy_bitslip122[0];
    k7ddrphy_dfi_p0_rddata[44] <= k7ddrphy_bitslip122[1];
    k7ddrphy_dfi_p0_rddata[13] <= k7ddrphy_bitslip132[0];
    k7ddrphy_dfi_p0_rddata[45] <= k7ddrphy_bitslip132[1];
    k7ddrphy_dfi_p0_rddata[14] <= k7ddrphy_bitslip142[0];
    k7ddrphy_dfi_p0_rddata[46] <= k7ddrphy_bitslip142[1];
    k7ddrphy_dfi_p0_rddata[15] <= k7ddrphy_bitslip152[0];
    k7ddrphy_dfi_p0_rddata[47] <= k7ddrphy_bitslip152[1];
    k7ddrphy_dfi_p0_rddata[16] <= k7ddrphy_bitslip162[0];
    k7ddrphy_dfi_p0_rddata[48] <= k7ddrphy_bitslip162[1];
    k7ddrphy_dfi_p0_rddata[17] <= k7ddrphy_bitslip172[0];
    k7ddrphy_dfi_p0_rddata[49] <= k7ddrphy_bitslip172[1];
    k7ddrphy_dfi_p0_rddata[18] <= k7ddrphy_bitslip182[0];
    k7ddrphy_dfi_p0_rddata[50] <= k7ddrphy_bitslip182[1];
    k7ddrphy_dfi_p0_rddata[19] <= k7ddrphy_bitslip192[0];
    k7ddrphy_dfi_p0_rddata[51] <= k7ddrphy_bitslip192[1];
    k7ddrphy_dfi_p0_rddata[20] <= k7ddrphy_bitslip202[0];
    k7ddrphy_dfi_p0_rddata[52] <= k7ddrphy_bitslip202[1];
    k7ddrphy_dfi_p0_rddata[21] <= k7ddrphy_bitslip212[0];
    k7ddrphy_dfi_p0_rddata[53] <= k7ddrphy_bitslip212[1];
    k7ddrphy_dfi_p0_rddata[22] <= k7ddrphy_bitslip222[0];
    k7ddrphy_dfi_p0_rddata[54] <= k7ddrphy_bitslip222[1];
    k7ddrphy_dfi_p0_rddata[23] <= k7ddrphy_bitslip232[0];
    k7ddrphy_dfi_p0_rddata[55] <= k7ddrphy_bitslip232[1];
    k7ddrphy_dfi_p0_rddata[24] <= k7ddrphy_bitslip242[0];
    k7ddrphy_dfi_p0_rddata[56] <= k7ddrphy_bitslip242[1];
    k7ddrphy_dfi_p0_rddata[25] <= k7ddrphy_bitslip252[0];
    k7ddrphy_dfi_p0_rddata[57] <= k7ddrphy_bitslip252[1];
    k7ddrphy_dfi_p0_rddata[26] <= k7ddrphy_bitslip262[0];
    k7ddrphy_dfi_p0_rddata[58] <= k7ddrphy_bitslip262[1];
    k7ddrphy_dfi_p0_rddata[27] <= k7ddrphy_bitslip272[0];
    k7ddrphy_dfi_p0_rddata[59] <= k7ddrphy_bitslip272[1];
    k7ddrphy_dfi_p0_rddata[28] <= k7ddrphy_bitslip282[0];
    k7ddrphy_dfi_p0_rddata[60] <= k7ddrphy_bitslip282[1];
    k7ddrphy_dfi_p0_rddata[29] <= k7ddrphy_bitslip292[0];
    k7ddrphy_dfi_p0_rddata[61] <= k7ddrphy_bitslip292[1];
    k7ddrphy_dfi_p0_rddata[30] <= k7ddrphy_bitslip302[0];
    k7ddrphy_dfi_p0_rddata[62] <= k7ddrphy_bitslip302[1];
    k7ddrphy_dfi_p0_rddata[31] <= k7ddrphy_bitslip312[0];
    k7ddrphy_dfi_p0_rddata[63] <= k7ddrphy_bitslip312[1];
end
always @(*) begin
    k7ddrphy_dfi_p1_rddata <= 64'd0;
    k7ddrphy_dfi_p1_rddata[0] <= k7ddrphy_bitslip04[2];
    k7ddrphy_dfi_p1_rddata[32] <= k7ddrphy_bitslip04[3];
    k7ddrphy_dfi_p1_rddata[1] <= k7ddrphy_bitslip14[2];
    k7ddrphy_dfi_p1_rddata[33] <= k7ddrphy_bitslip14[3];
    k7ddrphy_dfi_p1_rddata[2] <= k7ddrphy_bitslip24[2];
    k7ddrphy_dfi_p1_rddata[34] <= k7ddrphy_bitslip24[3];
    k7ddrphy_dfi_p1_rddata[3] <= k7ddrphy_bitslip34[2];
    k7ddrphy_dfi_p1_rddata[35] <= k7ddrphy_bitslip34[3];
    k7ddrphy_dfi_p1_rddata[4] <= k7ddrphy_bitslip42[2];
    k7ddrphy_dfi_p1_rddata[36] <= k7ddrphy_bitslip42[3];
    k7ddrphy_dfi_p1_rddata[5] <= k7ddrphy_bitslip52[2];
    k7ddrphy_dfi_p1_rddata[37] <= k7ddrphy_bitslip52[3];
    k7ddrphy_dfi_p1_rddata[6] <= k7ddrphy_bitslip62[2];
    k7ddrphy_dfi_p1_rddata[38] <= k7ddrphy_bitslip62[3];
    k7ddrphy_dfi_p1_rddata[7] <= k7ddrphy_bitslip72[2];
    k7ddrphy_dfi_p1_rddata[39] <= k7ddrphy_bitslip72[3];
    k7ddrphy_dfi_p1_rddata[8] <= k7ddrphy_bitslip82[2];
    k7ddrphy_dfi_p1_rddata[40] <= k7ddrphy_bitslip82[3];
    k7ddrphy_dfi_p1_rddata[9] <= k7ddrphy_bitslip92[2];
    k7ddrphy_dfi_p1_rddata[41] <= k7ddrphy_bitslip92[3];
    k7ddrphy_dfi_p1_rddata[10] <= k7ddrphy_bitslip102[2];
    k7ddrphy_dfi_p1_rddata[42] <= k7ddrphy_bitslip102[3];
    k7ddrphy_dfi_p1_rddata[11] <= k7ddrphy_bitslip112[2];
    k7ddrphy_dfi_p1_rddata[43] <= k7ddrphy_bitslip112[3];
    k7ddrphy_dfi_p1_rddata[12] <= k7ddrphy_bitslip122[2];
    k7ddrphy_dfi_p1_rddata[44] <= k7ddrphy_bitslip122[3];
    k7ddrphy_dfi_p1_rddata[13] <= k7ddrphy_bitslip132[2];
    k7ddrphy_dfi_p1_rddata[45] <= k7ddrphy_bitslip132[3];
    k7ddrphy_dfi_p1_rddata[14] <= k7ddrphy_bitslip142[2];
    k7ddrphy_dfi_p1_rddata[46] <= k7ddrphy_bitslip142[3];
    k7ddrphy_dfi_p1_rddata[15] <= k7ddrphy_bitslip152[2];
    k7ddrphy_dfi_p1_rddata[47] <= k7ddrphy_bitslip152[3];
    k7ddrphy_dfi_p1_rddata[16] <= k7ddrphy_bitslip162[2];
    k7ddrphy_dfi_p1_rddata[48] <= k7ddrphy_bitslip162[3];
    k7ddrphy_dfi_p1_rddata[17] <= k7ddrphy_bitslip172[2];
    k7ddrphy_dfi_p1_rddata[49] <= k7ddrphy_bitslip172[3];
    k7ddrphy_dfi_p1_rddata[18] <= k7ddrphy_bitslip182[2];
    k7ddrphy_dfi_p1_rddata[50] <= k7ddrphy_bitslip182[3];
    k7ddrphy_dfi_p1_rddata[19] <= k7ddrphy_bitslip192[2];
    k7ddrphy_dfi_p1_rddata[51] <= k7ddrphy_bitslip192[3];
    k7ddrphy_dfi_p1_rddata[20] <= k7ddrphy_bitslip202[2];
    k7ddrphy_dfi_p1_rddata[52] <= k7ddrphy_bitslip202[3];
    k7ddrphy_dfi_p1_rddata[21] <= k7ddrphy_bitslip212[2];
    k7ddrphy_dfi_p1_rddata[53] <= k7ddrphy_bitslip212[3];
    k7ddrphy_dfi_p1_rddata[22] <= k7ddrphy_bitslip222[2];
    k7ddrphy_dfi_p1_rddata[54] <= k7ddrphy_bitslip222[3];
    k7ddrphy_dfi_p1_rddata[23] <= k7ddrphy_bitslip232[2];
    k7ddrphy_dfi_p1_rddata[55] <= k7ddrphy_bitslip232[3];
    k7ddrphy_dfi_p1_rddata[24] <= k7ddrphy_bitslip242[2];
    k7ddrphy_dfi_p1_rddata[56] <= k7ddrphy_bitslip242[3];
    k7ddrphy_dfi_p1_rddata[25] <= k7ddrphy_bitslip252[2];
    k7ddrphy_dfi_p1_rddata[57] <= k7ddrphy_bitslip252[3];
    k7ddrphy_dfi_p1_rddata[26] <= k7ddrphy_bitslip262[2];
    k7ddrphy_dfi_p1_rddata[58] <= k7ddrphy_bitslip262[3];
    k7ddrphy_dfi_p1_rddata[27] <= k7ddrphy_bitslip272[2];
    k7ddrphy_dfi_p1_rddata[59] <= k7ddrphy_bitslip272[3];
    k7ddrphy_dfi_p1_rddata[28] <= k7ddrphy_bitslip282[2];
    k7ddrphy_dfi_p1_rddata[60] <= k7ddrphy_bitslip282[3];
    k7ddrphy_dfi_p1_rddata[29] <= k7ddrphy_bitslip292[2];
    k7ddrphy_dfi_p1_rddata[61] <= k7ddrphy_bitslip292[3];
    k7ddrphy_dfi_p1_rddata[30] <= k7ddrphy_bitslip302[2];
    k7ddrphy_dfi_p1_rddata[62] <= k7ddrphy_bitslip302[3];
    k7ddrphy_dfi_p1_rddata[31] <= k7ddrphy_bitslip312[2];
    k7ddrphy_dfi_p1_rddata[63] <= k7ddrphy_bitslip312[3];
end
always @(*) begin
    k7ddrphy_dfi_p2_rddata <= 64'd0;
    k7ddrphy_dfi_p2_rddata[0] <= k7ddrphy_bitslip04[4];
    k7ddrphy_dfi_p2_rddata[32] <= k7ddrphy_bitslip04[5];
    k7ddrphy_dfi_p2_rddata[1] <= k7ddrphy_bitslip14[4];
    k7ddrphy_dfi_p2_rddata[33] <= k7ddrphy_bitslip14[5];
    k7ddrphy_dfi_p2_rddata[2] <= k7ddrphy_bitslip24[4];
    k7ddrphy_dfi_p2_rddata[34] <= k7ddrphy_bitslip24[5];
    k7ddrphy_dfi_p2_rddata[3] <= k7ddrphy_bitslip34[4];
    k7ddrphy_dfi_p2_rddata[35] <= k7ddrphy_bitslip34[5];
    k7ddrphy_dfi_p2_rddata[4] <= k7ddrphy_bitslip42[4];
    k7ddrphy_dfi_p2_rddata[36] <= k7ddrphy_bitslip42[5];
    k7ddrphy_dfi_p2_rddata[5] <= k7ddrphy_bitslip52[4];
    k7ddrphy_dfi_p2_rddata[37] <= k7ddrphy_bitslip52[5];
    k7ddrphy_dfi_p2_rddata[6] <= k7ddrphy_bitslip62[4];
    k7ddrphy_dfi_p2_rddata[38] <= k7ddrphy_bitslip62[5];
    k7ddrphy_dfi_p2_rddata[7] <= k7ddrphy_bitslip72[4];
    k7ddrphy_dfi_p2_rddata[39] <= k7ddrphy_bitslip72[5];
    k7ddrphy_dfi_p2_rddata[8] <= k7ddrphy_bitslip82[4];
    k7ddrphy_dfi_p2_rddata[40] <= k7ddrphy_bitslip82[5];
    k7ddrphy_dfi_p2_rddata[9] <= k7ddrphy_bitslip92[4];
    k7ddrphy_dfi_p2_rddata[41] <= k7ddrphy_bitslip92[5];
    k7ddrphy_dfi_p2_rddata[10] <= k7ddrphy_bitslip102[4];
    k7ddrphy_dfi_p2_rddata[42] <= k7ddrphy_bitslip102[5];
    k7ddrphy_dfi_p2_rddata[11] <= k7ddrphy_bitslip112[4];
    k7ddrphy_dfi_p2_rddata[43] <= k7ddrphy_bitslip112[5];
    k7ddrphy_dfi_p2_rddata[12] <= k7ddrphy_bitslip122[4];
    k7ddrphy_dfi_p2_rddata[44] <= k7ddrphy_bitslip122[5];
    k7ddrphy_dfi_p2_rddata[13] <= k7ddrphy_bitslip132[4];
    k7ddrphy_dfi_p2_rddata[45] <= k7ddrphy_bitslip132[5];
    k7ddrphy_dfi_p2_rddata[14] <= k7ddrphy_bitslip142[4];
    k7ddrphy_dfi_p2_rddata[46] <= k7ddrphy_bitslip142[5];
    k7ddrphy_dfi_p2_rddata[15] <= k7ddrphy_bitslip152[4];
    k7ddrphy_dfi_p2_rddata[47] <= k7ddrphy_bitslip152[5];
    k7ddrphy_dfi_p2_rddata[16] <= k7ddrphy_bitslip162[4];
    k7ddrphy_dfi_p2_rddata[48] <= k7ddrphy_bitslip162[5];
    k7ddrphy_dfi_p2_rddata[17] <= k7ddrphy_bitslip172[4];
    k7ddrphy_dfi_p2_rddata[49] <= k7ddrphy_bitslip172[5];
    k7ddrphy_dfi_p2_rddata[18] <= k7ddrphy_bitslip182[4];
    k7ddrphy_dfi_p2_rddata[50] <= k7ddrphy_bitslip182[5];
    k7ddrphy_dfi_p2_rddata[19] <= k7ddrphy_bitslip192[4];
    k7ddrphy_dfi_p2_rddata[51] <= k7ddrphy_bitslip192[5];
    k7ddrphy_dfi_p2_rddata[20] <= k7ddrphy_bitslip202[4];
    k7ddrphy_dfi_p2_rddata[52] <= k7ddrphy_bitslip202[5];
    k7ddrphy_dfi_p2_rddata[21] <= k7ddrphy_bitslip212[4];
    k7ddrphy_dfi_p2_rddata[53] <= k7ddrphy_bitslip212[5];
    k7ddrphy_dfi_p2_rddata[22] <= k7ddrphy_bitslip222[4];
    k7ddrphy_dfi_p2_rddata[54] <= k7ddrphy_bitslip222[5];
    k7ddrphy_dfi_p2_rddata[23] <= k7ddrphy_bitslip232[4];
    k7ddrphy_dfi_p2_rddata[55] <= k7ddrphy_bitslip232[5];
    k7ddrphy_dfi_p2_rddata[24] <= k7ddrphy_bitslip242[4];
    k7ddrphy_dfi_p2_rddata[56] <= k7ddrphy_bitslip242[5];
    k7ddrphy_dfi_p2_rddata[25] <= k7ddrphy_bitslip252[4];
    k7ddrphy_dfi_p2_rddata[57] <= k7ddrphy_bitslip252[5];
    k7ddrphy_dfi_p2_rddata[26] <= k7ddrphy_bitslip262[4];
    k7ddrphy_dfi_p2_rddata[58] <= k7ddrphy_bitslip262[5];
    k7ddrphy_dfi_p2_rddata[27] <= k7ddrphy_bitslip272[4];
    k7ddrphy_dfi_p2_rddata[59] <= k7ddrphy_bitslip272[5];
    k7ddrphy_dfi_p2_rddata[28] <= k7ddrphy_bitslip282[4];
    k7ddrphy_dfi_p2_rddata[60] <= k7ddrphy_bitslip282[5];
    k7ddrphy_dfi_p2_rddata[29] <= k7ddrphy_bitslip292[4];
    k7ddrphy_dfi_p2_rddata[61] <= k7ddrphy_bitslip292[5];
    k7ddrphy_dfi_p2_rddata[30] <= k7ddrphy_bitslip302[4];
    k7ddrphy_dfi_p2_rddata[62] <= k7ddrphy_bitslip302[5];
    k7ddrphy_dfi_p2_rddata[31] <= k7ddrphy_bitslip312[4];
    k7ddrphy_dfi_p2_rddata[63] <= k7ddrphy_bitslip312[5];
end
always @(*) begin
    k7ddrphy_dfi_p3_rddata <= 64'd0;
    k7ddrphy_dfi_p3_rddata[0] <= k7ddrphy_bitslip04[6];
    k7ddrphy_dfi_p3_rddata[32] <= k7ddrphy_bitslip04[7];
    k7ddrphy_dfi_p3_rddata[1] <= k7ddrphy_bitslip14[6];
    k7ddrphy_dfi_p3_rddata[33] <= k7ddrphy_bitslip14[7];
    k7ddrphy_dfi_p3_rddata[2] <= k7ddrphy_bitslip24[6];
    k7ddrphy_dfi_p3_rddata[34] <= k7ddrphy_bitslip24[7];
    k7ddrphy_dfi_p3_rddata[3] <= k7ddrphy_bitslip34[6];
    k7ddrphy_dfi_p3_rddata[35] <= k7ddrphy_bitslip34[7];
    k7ddrphy_dfi_p3_rddata[4] <= k7ddrphy_bitslip42[6];
    k7ddrphy_dfi_p3_rddata[36] <= k7ddrphy_bitslip42[7];
    k7ddrphy_dfi_p3_rddata[5] <= k7ddrphy_bitslip52[6];
    k7ddrphy_dfi_p3_rddata[37] <= k7ddrphy_bitslip52[7];
    k7ddrphy_dfi_p3_rddata[6] <= k7ddrphy_bitslip62[6];
    k7ddrphy_dfi_p3_rddata[38] <= k7ddrphy_bitslip62[7];
    k7ddrphy_dfi_p3_rddata[7] <= k7ddrphy_bitslip72[6];
    k7ddrphy_dfi_p3_rddata[39] <= k7ddrphy_bitslip72[7];
    k7ddrphy_dfi_p3_rddata[8] <= k7ddrphy_bitslip82[6];
    k7ddrphy_dfi_p3_rddata[40] <= k7ddrphy_bitslip82[7];
    k7ddrphy_dfi_p3_rddata[9] <= k7ddrphy_bitslip92[6];
    k7ddrphy_dfi_p3_rddata[41] <= k7ddrphy_bitslip92[7];
    k7ddrphy_dfi_p3_rddata[10] <= k7ddrphy_bitslip102[6];
    k7ddrphy_dfi_p3_rddata[42] <= k7ddrphy_bitslip102[7];
    k7ddrphy_dfi_p3_rddata[11] <= k7ddrphy_bitslip112[6];
    k7ddrphy_dfi_p3_rddata[43] <= k7ddrphy_bitslip112[7];
    k7ddrphy_dfi_p3_rddata[12] <= k7ddrphy_bitslip122[6];
    k7ddrphy_dfi_p3_rddata[44] <= k7ddrphy_bitslip122[7];
    k7ddrphy_dfi_p3_rddata[13] <= k7ddrphy_bitslip132[6];
    k7ddrphy_dfi_p3_rddata[45] <= k7ddrphy_bitslip132[7];
    k7ddrphy_dfi_p3_rddata[14] <= k7ddrphy_bitslip142[6];
    k7ddrphy_dfi_p3_rddata[46] <= k7ddrphy_bitslip142[7];
    k7ddrphy_dfi_p3_rddata[15] <= k7ddrphy_bitslip152[6];
    k7ddrphy_dfi_p3_rddata[47] <= k7ddrphy_bitslip152[7];
    k7ddrphy_dfi_p3_rddata[16] <= k7ddrphy_bitslip162[6];
    k7ddrphy_dfi_p3_rddata[48] <= k7ddrphy_bitslip162[7];
    k7ddrphy_dfi_p3_rddata[17] <= k7ddrphy_bitslip172[6];
    k7ddrphy_dfi_p3_rddata[49] <= k7ddrphy_bitslip172[7];
    k7ddrphy_dfi_p3_rddata[18] <= k7ddrphy_bitslip182[6];
    k7ddrphy_dfi_p3_rddata[50] <= k7ddrphy_bitslip182[7];
    k7ddrphy_dfi_p3_rddata[19] <= k7ddrphy_bitslip192[6];
    k7ddrphy_dfi_p3_rddata[51] <= k7ddrphy_bitslip192[7];
    k7ddrphy_dfi_p3_rddata[20] <= k7ddrphy_bitslip202[6];
    k7ddrphy_dfi_p3_rddata[52] <= k7ddrphy_bitslip202[7];
    k7ddrphy_dfi_p3_rddata[21] <= k7ddrphy_bitslip212[6];
    k7ddrphy_dfi_p3_rddata[53] <= k7ddrphy_bitslip212[7];
    k7ddrphy_dfi_p3_rddata[22] <= k7ddrphy_bitslip222[6];
    k7ddrphy_dfi_p3_rddata[54] <= k7ddrphy_bitslip222[7];
    k7ddrphy_dfi_p3_rddata[23] <= k7ddrphy_bitslip232[6];
    k7ddrphy_dfi_p3_rddata[55] <= k7ddrphy_bitslip232[7];
    k7ddrphy_dfi_p3_rddata[24] <= k7ddrphy_bitslip242[6];
    k7ddrphy_dfi_p3_rddata[56] <= k7ddrphy_bitslip242[7];
    k7ddrphy_dfi_p3_rddata[25] <= k7ddrphy_bitslip252[6];
    k7ddrphy_dfi_p3_rddata[57] <= k7ddrphy_bitslip252[7];
    k7ddrphy_dfi_p3_rddata[26] <= k7ddrphy_bitslip262[6];
    k7ddrphy_dfi_p3_rddata[58] <= k7ddrphy_bitslip262[7];
    k7ddrphy_dfi_p3_rddata[27] <= k7ddrphy_bitslip272[6];
    k7ddrphy_dfi_p3_rddata[59] <= k7ddrphy_bitslip272[7];
    k7ddrphy_dfi_p3_rddata[28] <= k7ddrphy_bitslip282[6];
    k7ddrphy_dfi_p3_rddata[60] <= k7ddrphy_bitslip282[7];
    k7ddrphy_dfi_p3_rddata[29] <= k7ddrphy_bitslip292[6];
    k7ddrphy_dfi_p3_rddata[61] <= k7ddrphy_bitslip292[7];
    k7ddrphy_dfi_p3_rddata[30] <= k7ddrphy_bitslip302[6];
    k7ddrphy_dfi_p3_rddata[62] <= k7ddrphy_bitslip302[7];
    k7ddrphy_dfi_p3_rddata[31] <= k7ddrphy_bitslip312[6];
    k7ddrphy_dfi_p3_rddata[63] <= k7ddrphy_bitslip312[7];
end
assign k7ddrphy_dfi_p0_rddata_valid = (k7ddrphy_rddata_en_tappeddelayline8 | k7ddrphy_wlevel_en_storage);
assign k7ddrphy_dfi_p1_rddata_valid = (k7ddrphy_rddata_en_tappeddelayline8 | k7ddrphy_wlevel_en_storage);
assign k7ddrphy_dfi_p2_rddata_valid = (k7ddrphy_rddata_en_tappeddelayline8 | k7ddrphy_wlevel_en_storage);
assign k7ddrphy_dfi_p3_rddata_valid = (k7ddrphy_rddata_en_tappeddelayline8 | k7ddrphy_wlevel_en_storage);
assign k7ddrphy_dq_oe = k7ddrphy_wrdata_en_tappeddelayline1;
always @(*) begin
    k7ddrphy_dqs_oe <= 1'd0;
    if (k7ddrphy_wlevel_en_storage) begin
        k7ddrphy_dqs_oe <= 1'd1;
    end else begin
        k7ddrphy_dqs_oe <= k7ddrphy_dq_oe;
    end
end
assign k7ddrphy_dqs_preamble = (k7ddrphy_wrdata_en_tappeddelayline0 & (~k7ddrphy_wrdata_en_tappeddelayline1));
assign k7ddrphy_dqs_postamble = (k7ddrphy_wrdata_en_tappeddelayline2 & (~k7ddrphy_wrdata_en_tappeddelayline1));
always @(*) begin
    k7ddrphy_dqspattern_o <= 8'd0;
    k7ddrphy_dqspattern_o <= 7'd85;
    if (k7ddrphy_dqspattern0) begin
        k7ddrphy_dqspattern_o <= 5'd21;
    end
    if (k7ddrphy_dqspattern1) begin
        k7ddrphy_dqspattern_o <= 7'd84;
    end
    if (k7ddrphy_wlevel_en_storage) begin
        k7ddrphy_dqspattern_o <= 1'd0;
        if (k7ddrphy_wlevel_strobe_re) begin
            k7ddrphy_dqspattern_o <= 1'd1;
        end
    end
end
always @(*) begin
    k7ddrphy_bitslip00 <= 8'd0;
    case (k7ddrphy_bitslip0_value0)
        1'd0: begin
            k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip10 <= 8'd0;
    case (k7ddrphy_bitslip1_value0)
        1'd0: begin
            k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip20 <= 8'd0;
    case (k7ddrphy_bitslip2_value0)
        1'd0: begin
            k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip30 <= 8'd0;
    case (k7ddrphy_bitslip3_value0)
        1'd0: begin
            k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip01 <= 8'd0;
    case (k7ddrphy_bitslip0_value1)
        1'd0: begin
            k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip11 <= 8'd0;
    case (k7ddrphy_bitslip1_value1)
        1'd0: begin
            k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip21 <= 8'd0;
    case (k7ddrphy_bitslip2_value1)
        1'd0: begin
            k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip31 <= 8'd0;
    case (k7ddrphy_bitslip3_value1)
        1'd0: begin
            k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip02 <= 8'd0;
    case (k7ddrphy_bitslip0_value2)
        1'd0: begin
            k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip04 <= 8'd0;
    case (k7ddrphy_bitslip0_value3)
        1'd0: begin
            k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip12 <= 8'd0;
    case (k7ddrphy_bitslip1_value2)
        1'd0: begin
            k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip14 <= 8'd0;
    case (k7ddrphy_bitslip1_value3)
        1'd0: begin
            k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip22 <= 8'd0;
    case (k7ddrphy_bitslip2_value2)
        1'd0: begin
            k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip24 <= 8'd0;
    case (k7ddrphy_bitslip2_value3)
        1'd0: begin
            k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip32 <= 8'd0;
    case (k7ddrphy_bitslip3_value2)
        1'd0: begin
            k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip34 <= 8'd0;
    case (k7ddrphy_bitslip3_value3)
        1'd0: begin
            k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip40 <= 8'd0;
    case (k7ddrphy_bitslip4_value0)
        1'd0: begin
            k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip42 <= 8'd0;
    case (k7ddrphy_bitslip4_value1)
        1'd0: begin
            k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip50 <= 8'd0;
    case (k7ddrphy_bitslip5_value0)
        1'd0: begin
            k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip52 <= 8'd0;
    case (k7ddrphy_bitslip5_value1)
        1'd0: begin
            k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip60 <= 8'd0;
    case (k7ddrphy_bitslip6_value0)
        1'd0: begin
            k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip62 <= 8'd0;
    case (k7ddrphy_bitslip6_value1)
        1'd0: begin
            k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip70 <= 8'd0;
    case (k7ddrphy_bitslip7_value0)
        1'd0: begin
            k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip72 <= 8'd0;
    case (k7ddrphy_bitslip7_value1)
        1'd0: begin
            k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip80 <= 8'd0;
    case (k7ddrphy_bitslip8_value0)
        1'd0: begin
            k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip82 <= 8'd0;
    case (k7ddrphy_bitslip8_value1)
        1'd0: begin
            k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip90 <= 8'd0;
    case (k7ddrphy_bitslip9_value0)
        1'd0: begin
            k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip92 <= 8'd0;
    case (k7ddrphy_bitslip9_value1)
        1'd0: begin
            k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip100 <= 8'd0;
    case (k7ddrphy_bitslip10_value0)
        1'd0: begin
            k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip102 <= 8'd0;
    case (k7ddrphy_bitslip10_value1)
        1'd0: begin
            k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip110 <= 8'd0;
    case (k7ddrphy_bitslip11_value0)
        1'd0: begin
            k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip112 <= 8'd0;
    case (k7ddrphy_bitslip11_value1)
        1'd0: begin
            k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip120 <= 8'd0;
    case (k7ddrphy_bitslip12_value0)
        1'd0: begin
            k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip122 <= 8'd0;
    case (k7ddrphy_bitslip12_value1)
        1'd0: begin
            k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip130 <= 8'd0;
    case (k7ddrphy_bitslip13_value0)
        1'd0: begin
            k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip132 <= 8'd0;
    case (k7ddrphy_bitslip13_value1)
        1'd0: begin
            k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip140 <= 8'd0;
    case (k7ddrphy_bitslip14_value0)
        1'd0: begin
            k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip142 <= 8'd0;
    case (k7ddrphy_bitslip14_value1)
        1'd0: begin
            k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip150 <= 8'd0;
    case (k7ddrphy_bitslip15_value0)
        1'd0: begin
            k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip152 <= 8'd0;
    case (k7ddrphy_bitslip15_value1)
        1'd0: begin
            k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip160 <= 8'd0;
    case (k7ddrphy_bitslip16_value0)
        1'd0: begin
            k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip162 <= 8'd0;
    case (k7ddrphy_bitslip16_value1)
        1'd0: begin
            k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip170 <= 8'd0;
    case (k7ddrphy_bitslip17_value0)
        1'd0: begin
            k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip172 <= 8'd0;
    case (k7ddrphy_bitslip17_value1)
        1'd0: begin
            k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip180 <= 8'd0;
    case (k7ddrphy_bitslip18_value0)
        1'd0: begin
            k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip182 <= 8'd0;
    case (k7ddrphy_bitslip18_value1)
        1'd0: begin
            k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip190 <= 8'd0;
    case (k7ddrphy_bitslip19_value0)
        1'd0: begin
            k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip192 <= 8'd0;
    case (k7ddrphy_bitslip19_value1)
        1'd0: begin
            k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip200 <= 8'd0;
    case (k7ddrphy_bitslip20_value0)
        1'd0: begin
            k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip202 <= 8'd0;
    case (k7ddrphy_bitslip20_value1)
        1'd0: begin
            k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip210 <= 8'd0;
    case (k7ddrphy_bitslip21_value0)
        1'd0: begin
            k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip212 <= 8'd0;
    case (k7ddrphy_bitslip21_value1)
        1'd0: begin
            k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip220 <= 8'd0;
    case (k7ddrphy_bitslip22_value0)
        1'd0: begin
            k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip222 <= 8'd0;
    case (k7ddrphy_bitslip22_value1)
        1'd0: begin
            k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip230 <= 8'd0;
    case (k7ddrphy_bitslip23_value0)
        1'd0: begin
            k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip232 <= 8'd0;
    case (k7ddrphy_bitslip23_value1)
        1'd0: begin
            k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip240 <= 8'd0;
    case (k7ddrphy_bitslip24_value0)
        1'd0: begin
            k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip242 <= 8'd0;
    case (k7ddrphy_bitslip24_value1)
        1'd0: begin
            k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip250 <= 8'd0;
    case (k7ddrphy_bitslip25_value0)
        1'd0: begin
            k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip252 <= 8'd0;
    case (k7ddrphy_bitslip25_value1)
        1'd0: begin
            k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip260 <= 8'd0;
    case (k7ddrphy_bitslip26_value0)
        1'd0: begin
            k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip262 <= 8'd0;
    case (k7ddrphy_bitslip26_value1)
        1'd0: begin
            k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip270 <= 8'd0;
    case (k7ddrphy_bitslip27_value0)
        1'd0: begin
            k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip272 <= 8'd0;
    case (k7ddrphy_bitslip27_value1)
        1'd0: begin
            k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip280 <= 8'd0;
    case (k7ddrphy_bitslip28_value0)
        1'd0: begin
            k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip282 <= 8'd0;
    case (k7ddrphy_bitslip28_value1)
        1'd0: begin
            k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip290 <= 8'd0;
    case (k7ddrphy_bitslip29_value0)
        1'd0: begin
            k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip292 <= 8'd0;
    case (k7ddrphy_bitslip29_value1)
        1'd0: begin
            k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip300 <= 8'd0;
    case (k7ddrphy_bitslip30_value0)
        1'd0: begin
            k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip302 <= 8'd0;
    case (k7ddrphy_bitslip30_value1)
        1'd0: begin
            k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip310 <= 8'd0;
    case (k7ddrphy_bitslip31_value0)
        1'd0: begin
            k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[15:8];
        end
    endcase
end
always @(*) begin
    k7ddrphy_bitslip312 <= 8'd0;
    case (k7ddrphy_bitslip31_value1)
        1'd0: begin
            k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[8:1];
        end
        1'd1: begin
            k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[9:2];
        end
        2'd2: begin
            k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[10:3];
        end
        2'd3: begin
            k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[11:4];
        end
        3'd4: begin
            k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[12:5];
        end
        3'd5: begin
            k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[13:6];
        end
        3'd6: begin
            k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[14:7];
        end
        3'd7: begin
            k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[15:8];
        end
    endcase
end
assign k7ddrphy_dfi_p0_address = litedramcore_sdram_master_p0_address;
assign k7ddrphy_dfi_p0_bank = litedramcore_sdram_master_p0_bank;
assign k7ddrphy_dfi_p0_cas_n = litedramcore_sdram_master_p0_cas_n;
assign k7ddrphy_dfi_p0_cs_n = litedramcore_sdram_master_p0_cs_n;
assign k7ddrphy_dfi_p0_ras_n = litedramcore_sdram_master_p0_ras_n;
assign k7ddrphy_dfi_p0_we_n = litedramcore_sdram_master_p0_we_n;
assign k7ddrphy_dfi_p0_cke = litedramcore_sdram_master_p0_cke;
assign k7ddrphy_dfi_p0_odt = litedramcore_sdram_master_p0_odt;
assign k7ddrphy_dfi_p0_reset_n = litedramcore_sdram_master_p0_reset_n;
assign k7ddrphy_dfi_p0_act_n = litedramcore_sdram_master_p0_act_n;
assign k7ddrphy_dfi_p0_wrdata = litedramcore_sdram_master_p0_wrdata;
assign k7ddrphy_dfi_p0_wrdata_en = litedramcore_sdram_master_p0_wrdata_en;
assign k7ddrphy_dfi_p0_wrdata_mask = litedramcore_sdram_master_p0_wrdata_mask;
assign k7ddrphy_dfi_p0_rddata_en = litedramcore_sdram_master_p0_rddata_en;
assign litedramcore_sdram_master_p0_rddata = k7ddrphy_dfi_p0_rddata;
assign litedramcore_sdram_master_p0_rddata_valid = k7ddrphy_dfi_p0_rddata_valid;
assign k7ddrphy_dfi_p1_address = litedramcore_sdram_master_p1_address;
assign k7ddrphy_dfi_p1_bank = litedramcore_sdram_master_p1_bank;
assign k7ddrphy_dfi_p1_cas_n = litedramcore_sdram_master_p1_cas_n;
assign k7ddrphy_dfi_p1_cs_n = litedramcore_sdram_master_p1_cs_n;
assign k7ddrphy_dfi_p1_ras_n = litedramcore_sdram_master_p1_ras_n;
assign k7ddrphy_dfi_p1_we_n = litedramcore_sdram_master_p1_we_n;
assign k7ddrphy_dfi_p1_cke = litedramcore_sdram_master_p1_cke;
assign k7ddrphy_dfi_p1_odt = litedramcore_sdram_master_p1_odt;
assign k7ddrphy_dfi_p1_reset_n = litedramcore_sdram_master_p1_reset_n;
assign k7ddrphy_dfi_p1_act_n = litedramcore_sdram_master_p1_act_n;
assign k7ddrphy_dfi_p1_wrdata = litedramcore_sdram_master_p1_wrdata;
assign k7ddrphy_dfi_p1_wrdata_en = litedramcore_sdram_master_p1_wrdata_en;
assign k7ddrphy_dfi_p1_wrdata_mask = litedramcore_sdram_master_p1_wrdata_mask;
assign k7ddrphy_dfi_p1_rddata_en = litedramcore_sdram_master_p1_rddata_en;
assign litedramcore_sdram_master_p1_rddata = k7ddrphy_dfi_p1_rddata;
assign litedramcore_sdram_master_p1_rddata_valid = k7ddrphy_dfi_p1_rddata_valid;
assign k7ddrphy_dfi_p2_address = litedramcore_sdram_master_p2_address;
assign k7ddrphy_dfi_p2_bank = litedramcore_sdram_master_p2_bank;
assign k7ddrphy_dfi_p2_cas_n = litedramcore_sdram_master_p2_cas_n;
assign k7ddrphy_dfi_p2_cs_n = litedramcore_sdram_master_p2_cs_n;
assign k7ddrphy_dfi_p2_ras_n = litedramcore_sdram_master_p2_ras_n;
assign k7ddrphy_dfi_p2_we_n = litedramcore_sdram_master_p2_we_n;
assign k7ddrphy_dfi_p2_cke = litedramcore_sdram_master_p2_cke;
assign k7ddrphy_dfi_p2_odt = litedramcore_sdram_master_p2_odt;
assign k7ddrphy_dfi_p2_reset_n = litedramcore_sdram_master_p2_reset_n;
assign k7ddrphy_dfi_p2_act_n = litedramcore_sdram_master_p2_act_n;
assign k7ddrphy_dfi_p2_wrdata = litedramcore_sdram_master_p2_wrdata;
assign k7ddrphy_dfi_p2_wrdata_en = litedramcore_sdram_master_p2_wrdata_en;
assign k7ddrphy_dfi_p2_wrdata_mask = litedramcore_sdram_master_p2_wrdata_mask;
assign k7ddrphy_dfi_p2_rddata_en = litedramcore_sdram_master_p2_rddata_en;
assign litedramcore_sdram_master_p2_rddata = k7ddrphy_dfi_p2_rddata;
assign litedramcore_sdram_master_p2_rddata_valid = k7ddrphy_dfi_p2_rddata_valid;
assign k7ddrphy_dfi_p3_address = litedramcore_sdram_master_p3_address;
assign k7ddrphy_dfi_p3_bank = litedramcore_sdram_master_p3_bank;
assign k7ddrphy_dfi_p3_cas_n = litedramcore_sdram_master_p3_cas_n;
assign k7ddrphy_dfi_p3_cs_n = litedramcore_sdram_master_p3_cs_n;
assign k7ddrphy_dfi_p3_ras_n = litedramcore_sdram_master_p3_ras_n;
assign k7ddrphy_dfi_p3_we_n = litedramcore_sdram_master_p3_we_n;
assign k7ddrphy_dfi_p3_cke = litedramcore_sdram_master_p3_cke;
assign k7ddrphy_dfi_p3_odt = litedramcore_sdram_master_p3_odt;
assign k7ddrphy_dfi_p3_reset_n = litedramcore_sdram_master_p3_reset_n;
assign k7ddrphy_dfi_p3_act_n = litedramcore_sdram_master_p3_act_n;
assign k7ddrphy_dfi_p3_wrdata = litedramcore_sdram_master_p3_wrdata;
assign k7ddrphy_dfi_p3_wrdata_en = litedramcore_sdram_master_p3_wrdata_en;
assign k7ddrphy_dfi_p3_wrdata_mask = litedramcore_sdram_master_p3_wrdata_mask;
assign k7ddrphy_dfi_p3_rddata_en = litedramcore_sdram_master_p3_rddata_en;
assign litedramcore_sdram_master_p3_rddata = k7ddrphy_dfi_p3_rddata;
assign litedramcore_sdram_master_p3_rddata_valid = k7ddrphy_dfi_p3_rddata_valid;
assign litedramcore_sdram_slave_p0_address = litedramcore_sdram_dfi_p0_address;
assign litedramcore_sdram_slave_p0_bank = litedramcore_sdram_dfi_p0_bank;
assign litedramcore_sdram_slave_p0_cas_n = litedramcore_sdram_dfi_p0_cas_n;
assign litedramcore_sdram_slave_p0_cs_n = litedramcore_sdram_dfi_p0_cs_n;
assign litedramcore_sdram_slave_p0_ras_n = litedramcore_sdram_dfi_p0_ras_n;
assign litedramcore_sdram_slave_p0_we_n = litedramcore_sdram_dfi_p0_we_n;
assign litedramcore_sdram_slave_p0_cke = litedramcore_sdram_dfi_p0_cke;
assign litedramcore_sdram_slave_p0_odt = litedramcore_sdram_dfi_p0_odt;
assign litedramcore_sdram_slave_p0_reset_n = litedramcore_sdram_dfi_p0_reset_n;
assign litedramcore_sdram_slave_p0_act_n = litedramcore_sdram_dfi_p0_act_n;
assign litedramcore_sdram_slave_p0_wrdata = litedramcore_sdram_dfi_p0_wrdata;
assign litedramcore_sdram_slave_p0_wrdata_en = litedramcore_sdram_dfi_p0_wrdata_en;
assign litedramcore_sdram_slave_p0_wrdata_mask = litedramcore_sdram_dfi_p0_wrdata_mask;
assign litedramcore_sdram_slave_p0_rddata_en = litedramcore_sdram_dfi_p0_rddata_en;
assign litedramcore_sdram_dfi_p0_rddata = litedramcore_sdram_slave_p0_rddata;
assign litedramcore_sdram_dfi_p0_rddata_valid = litedramcore_sdram_slave_p0_rddata_valid;
assign litedramcore_sdram_slave_p1_address = litedramcore_sdram_dfi_p1_address;
assign litedramcore_sdram_slave_p1_bank = litedramcore_sdram_dfi_p1_bank;
assign litedramcore_sdram_slave_p1_cas_n = litedramcore_sdram_dfi_p1_cas_n;
assign litedramcore_sdram_slave_p1_cs_n = litedramcore_sdram_dfi_p1_cs_n;
assign litedramcore_sdram_slave_p1_ras_n = litedramcore_sdram_dfi_p1_ras_n;
assign litedramcore_sdram_slave_p1_we_n = litedramcore_sdram_dfi_p1_we_n;
assign litedramcore_sdram_slave_p1_cke = litedramcore_sdram_dfi_p1_cke;
assign litedramcore_sdram_slave_p1_odt = litedramcore_sdram_dfi_p1_odt;
assign litedramcore_sdram_slave_p1_reset_n = litedramcore_sdram_dfi_p1_reset_n;
assign litedramcore_sdram_slave_p1_act_n = litedramcore_sdram_dfi_p1_act_n;
assign litedramcore_sdram_slave_p1_wrdata = litedramcore_sdram_dfi_p1_wrdata;
assign litedramcore_sdram_slave_p1_wrdata_en = litedramcore_sdram_dfi_p1_wrdata_en;
assign litedramcore_sdram_slave_p1_wrdata_mask = litedramcore_sdram_dfi_p1_wrdata_mask;
assign litedramcore_sdram_slave_p1_rddata_en = litedramcore_sdram_dfi_p1_rddata_en;
assign litedramcore_sdram_dfi_p1_rddata = litedramcore_sdram_slave_p1_rddata;
assign litedramcore_sdram_dfi_p1_rddata_valid = litedramcore_sdram_slave_p1_rddata_valid;
assign litedramcore_sdram_slave_p2_address = litedramcore_sdram_dfi_p2_address;
assign litedramcore_sdram_slave_p2_bank = litedramcore_sdram_dfi_p2_bank;
assign litedramcore_sdram_slave_p2_cas_n = litedramcore_sdram_dfi_p2_cas_n;
assign litedramcore_sdram_slave_p2_cs_n = litedramcore_sdram_dfi_p2_cs_n;
assign litedramcore_sdram_slave_p2_ras_n = litedramcore_sdram_dfi_p2_ras_n;
assign litedramcore_sdram_slave_p2_we_n = litedramcore_sdram_dfi_p2_we_n;
assign litedramcore_sdram_slave_p2_cke = litedramcore_sdram_dfi_p2_cke;
assign litedramcore_sdram_slave_p2_odt = litedramcore_sdram_dfi_p2_odt;
assign litedramcore_sdram_slave_p2_reset_n = litedramcore_sdram_dfi_p2_reset_n;
assign litedramcore_sdram_slave_p2_act_n = litedramcore_sdram_dfi_p2_act_n;
assign litedramcore_sdram_slave_p2_wrdata = litedramcore_sdram_dfi_p2_wrdata;
assign litedramcore_sdram_slave_p2_wrdata_en = litedramcore_sdram_dfi_p2_wrdata_en;
assign litedramcore_sdram_slave_p2_wrdata_mask = litedramcore_sdram_dfi_p2_wrdata_mask;
assign litedramcore_sdram_slave_p2_rddata_en = litedramcore_sdram_dfi_p2_rddata_en;
assign litedramcore_sdram_dfi_p2_rddata = litedramcore_sdram_slave_p2_rddata;
assign litedramcore_sdram_dfi_p2_rddata_valid = litedramcore_sdram_slave_p2_rddata_valid;
assign litedramcore_sdram_slave_p3_address = litedramcore_sdram_dfi_p3_address;
assign litedramcore_sdram_slave_p3_bank = litedramcore_sdram_dfi_p3_bank;
assign litedramcore_sdram_slave_p3_cas_n = litedramcore_sdram_dfi_p3_cas_n;
assign litedramcore_sdram_slave_p3_cs_n = litedramcore_sdram_dfi_p3_cs_n;
assign litedramcore_sdram_slave_p3_ras_n = litedramcore_sdram_dfi_p3_ras_n;
assign litedramcore_sdram_slave_p3_we_n = litedramcore_sdram_dfi_p3_we_n;
assign litedramcore_sdram_slave_p3_cke = litedramcore_sdram_dfi_p3_cke;
assign litedramcore_sdram_slave_p3_odt = litedramcore_sdram_dfi_p3_odt;
assign litedramcore_sdram_slave_p3_reset_n = litedramcore_sdram_dfi_p3_reset_n;
assign litedramcore_sdram_slave_p3_act_n = litedramcore_sdram_dfi_p3_act_n;
assign litedramcore_sdram_slave_p3_wrdata = litedramcore_sdram_dfi_p3_wrdata;
assign litedramcore_sdram_slave_p3_wrdata_en = litedramcore_sdram_dfi_p3_wrdata_en;
assign litedramcore_sdram_slave_p3_wrdata_mask = litedramcore_sdram_dfi_p3_wrdata_mask;
assign litedramcore_sdram_slave_p3_rddata_en = litedramcore_sdram_dfi_p3_rddata_en;
assign litedramcore_sdram_dfi_p3_rddata = litedramcore_sdram_slave_p3_rddata;
assign litedramcore_sdram_dfi_p3_rddata_valid = litedramcore_sdram_slave_p3_rddata_valid;
always @(*) begin
    litedramcore_sdram_slave_p2_rddata <= 64'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
        end else begin
            litedramcore_sdram_slave_p2_rddata <= litedramcore_sdram_master_p2_rddata;
        end
    end else begin
    end
end
always @(*) begin
    litedramcore_sdram_slave_p2_rddata_valid <= 1'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
        end else begin
            litedramcore_sdram_slave_p2_rddata_valid <= litedramcore_sdram_master_p2_rddata_valid;
        end
    end else begin
    end
end
always @(*) begin
    litedramcore_sdram_slave_p3_rddata <= 64'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
        end else begin
            litedramcore_sdram_slave_p3_rddata <= litedramcore_sdram_master_p3_rddata;
        end
    end else begin
    end
end
always @(*) begin
    litedramcore_sdram_slave_p3_rddata_valid <= 1'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
        end else begin
            litedramcore_sdram_slave_p3_rddata_valid <= litedramcore_sdram_master_p3_rddata_valid;
        end
    end else begin
    end
end
always @(*) begin
    litedramcore_sdram_master_p0_address <= 15'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p0_address <= litedramcore_sdram_ext_dfi_p0_address;
        end else begin
            litedramcore_sdram_master_p0_address <= litedramcore_sdram_slave_p0_address;
        end
    end else begin
        litedramcore_sdram_master_p0_address <= litedramcore_sdram_csr_dfi_p0_address;
    end
end
always @(*) begin
    litedramcore_sdram_master_p0_bank <= 3'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p0_bank <= litedramcore_sdram_ext_dfi_p0_bank;
        end else begin
            litedramcore_sdram_master_p0_bank <= litedramcore_sdram_slave_p0_bank;
        end
    end else begin
        litedramcore_sdram_master_p0_bank <= litedramcore_sdram_csr_dfi_p0_bank;
    end
end
always @(*) begin
    litedramcore_sdram_master_p0_cas_n <= 1'd1;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p0_cas_n <= litedramcore_sdram_ext_dfi_p0_cas_n;
        end else begin
            litedramcore_sdram_master_p0_cas_n <= litedramcore_sdram_slave_p0_cas_n;
        end
    end else begin
        litedramcore_sdram_master_p0_cas_n <= litedramcore_sdram_csr_dfi_p0_cas_n;
    end
end
always @(*) begin
    litedramcore_sdram_master_p0_cs_n <= 1'd1;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p0_cs_n <= litedramcore_sdram_ext_dfi_p0_cs_n;
        end else begin
            litedramcore_sdram_master_p0_cs_n <= litedramcore_sdram_slave_p0_cs_n;
            if (1'd0) begin
                litedramcore_sdram_master_p0_cs_n <= {2{litedramcore_sdram_slave_p0_cs_n}};
            end
        end
    end else begin
        litedramcore_sdram_master_p0_cs_n <= litedramcore_sdram_csr_dfi_p0_cs_n;
    end
end
always @(*) begin
    litedramcore_sdram_master_p0_ras_n <= 1'd1;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p0_ras_n <= litedramcore_sdram_ext_dfi_p0_ras_n;
        end else begin
            litedramcore_sdram_master_p0_ras_n <= litedramcore_sdram_slave_p0_ras_n;
        end
    end else begin
        litedramcore_sdram_master_p0_ras_n <= litedramcore_sdram_csr_dfi_p0_ras_n;
    end
end
always @(*) begin
    litedramcore_sdram_master_p0_we_n <= 1'd1;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p0_we_n <= litedramcore_sdram_ext_dfi_p0_we_n;
        end else begin
            litedramcore_sdram_master_p0_we_n <= litedramcore_sdram_slave_p0_we_n;
        end
    end else begin
        litedramcore_sdram_master_p0_we_n <= litedramcore_sdram_csr_dfi_p0_we_n;
    end
end
always @(*) begin
    litedramcore_sdram_master_p0_cke <= 1'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p0_cke <= litedramcore_sdram_ext_dfi_p0_cke;
        end else begin
            litedramcore_sdram_master_p0_cke <= litedramcore_sdram_slave_p0_cke;
        end
    end else begin
        litedramcore_sdram_master_p0_cke <= litedramcore_sdram_csr_dfi_p0_cke;
    end
end
always @(*) begin
    litedramcore_sdram_master_p0_odt <= 1'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p0_odt <= litedramcore_sdram_ext_dfi_p0_odt;
        end else begin
            litedramcore_sdram_master_p0_odt <= litedramcore_sdram_slave_p0_odt;
        end
    end else begin
        litedramcore_sdram_master_p0_odt <= litedramcore_sdram_csr_dfi_p0_odt;
    end
end
always @(*) begin
    litedramcore_sdram_master_p0_reset_n <= 1'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p0_reset_n <= litedramcore_sdram_ext_dfi_p0_reset_n;
        end else begin
            litedramcore_sdram_master_p0_reset_n <= litedramcore_sdram_slave_p0_reset_n;
        end
    end else begin
        litedramcore_sdram_master_p0_reset_n <= litedramcore_sdram_csr_dfi_p0_reset_n;
    end
end
always @(*) begin
    litedramcore_sdram_master_p0_act_n <= 1'd1;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p0_act_n <= litedramcore_sdram_ext_dfi_p0_act_n;
        end else begin
            litedramcore_sdram_master_p0_act_n <= litedramcore_sdram_slave_p0_act_n;
        end
    end else begin
        litedramcore_sdram_master_p0_act_n <= litedramcore_sdram_csr_dfi_p0_act_n;
    end
end
always @(*) begin
    litedramcore_sdram_master_p0_wrdata <= 64'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p0_wrdata <= litedramcore_sdram_ext_dfi_p0_wrdata;
        end else begin
            litedramcore_sdram_master_p0_wrdata <= litedramcore_sdram_slave_p0_wrdata;
        end
    end else begin
        litedramcore_sdram_master_p0_wrdata <= litedramcore_sdram_csr_dfi_p0_wrdata;
    end
end
always @(*) begin
    litedramcore_sdram_master_p0_wrdata_en <= 1'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p0_wrdata_en <= litedramcore_sdram_ext_dfi_p0_wrdata_en;
        end else begin
            litedramcore_sdram_master_p0_wrdata_en <= litedramcore_sdram_slave_p0_wrdata_en;
        end
    end else begin
        litedramcore_sdram_master_p0_wrdata_en <= litedramcore_sdram_csr_dfi_p0_wrdata_en;
    end
end
always @(*) begin
    litedramcore_sdram_master_p0_wrdata_mask <= 8'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p0_wrdata_mask <= litedramcore_sdram_ext_dfi_p0_wrdata_mask;
        end else begin
            litedramcore_sdram_master_p0_wrdata_mask <= litedramcore_sdram_slave_p0_wrdata_mask;
        end
    end else begin
        litedramcore_sdram_master_p0_wrdata_mask <= litedramcore_sdram_csr_dfi_p0_wrdata_mask;
    end
end
always @(*) begin
    litedramcore_sdram_master_p0_rddata_en <= 1'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p0_rddata_en <= litedramcore_sdram_ext_dfi_p0_rddata_en;
        end else begin
            litedramcore_sdram_master_p0_rddata_en <= litedramcore_sdram_slave_p0_rddata_en;
        end
    end else begin
        litedramcore_sdram_master_p0_rddata_en <= litedramcore_sdram_csr_dfi_p0_rddata_en;
    end
end
always @(*) begin
    litedramcore_sdram_master_p1_address <= 15'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p1_address <= litedramcore_sdram_ext_dfi_p1_address;
        end else begin
            litedramcore_sdram_master_p1_address <= litedramcore_sdram_slave_p1_address;
        end
    end else begin
        litedramcore_sdram_master_p1_address <= litedramcore_sdram_csr_dfi_p1_address;
    end
end
always @(*) begin
    litedramcore_sdram_master_p1_bank <= 3'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p1_bank <= litedramcore_sdram_ext_dfi_p1_bank;
        end else begin
            litedramcore_sdram_master_p1_bank <= litedramcore_sdram_slave_p1_bank;
        end
    end else begin
        litedramcore_sdram_master_p1_bank <= litedramcore_sdram_csr_dfi_p1_bank;
    end
end
always @(*) begin
    litedramcore_sdram_master_p1_cas_n <= 1'd1;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p1_cas_n <= litedramcore_sdram_ext_dfi_p1_cas_n;
        end else begin
            litedramcore_sdram_master_p1_cas_n <= litedramcore_sdram_slave_p1_cas_n;
        end
    end else begin
        litedramcore_sdram_master_p1_cas_n <= litedramcore_sdram_csr_dfi_p1_cas_n;
    end
end
always @(*) begin
    litedramcore_sdram_master_p1_cs_n <= 1'd1;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p1_cs_n <= litedramcore_sdram_ext_dfi_p1_cs_n;
        end else begin
            litedramcore_sdram_master_p1_cs_n <= litedramcore_sdram_slave_p1_cs_n;
            if (1'd0) begin
                litedramcore_sdram_master_p1_cs_n <= {2{litedramcore_sdram_slave_p1_cs_n}};
            end
        end
    end else begin
        litedramcore_sdram_master_p1_cs_n <= litedramcore_sdram_csr_dfi_p1_cs_n;
    end
end
always @(*) begin
    litedramcore_sdram_master_p1_ras_n <= 1'd1;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p1_ras_n <= litedramcore_sdram_ext_dfi_p1_ras_n;
        end else begin
            litedramcore_sdram_master_p1_ras_n <= litedramcore_sdram_slave_p1_ras_n;
        end
    end else begin
        litedramcore_sdram_master_p1_ras_n <= litedramcore_sdram_csr_dfi_p1_ras_n;
    end
end
always @(*) begin
    litedramcore_sdram_master_p1_we_n <= 1'd1;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p1_we_n <= litedramcore_sdram_ext_dfi_p1_we_n;
        end else begin
            litedramcore_sdram_master_p1_we_n <= litedramcore_sdram_slave_p1_we_n;
        end
    end else begin
        litedramcore_sdram_master_p1_we_n <= litedramcore_sdram_csr_dfi_p1_we_n;
    end
end
always @(*) begin
    litedramcore_sdram_master_p1_cke <= 1'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p1_cke <= litedramcore_sdram_ext_dfi_p1_cke;
        end else begin
            litedramcore_sdram_master_p1_cke <= litedramcore_sdram_slave_p1_cke;
        end
    end else begin
        litedramcore_sdram_master_p1_cke <= litedramcore_sdram_csr_dfi_p1_cke;
    end
end
always @(*) begin
    litedramcore_sdram_master_p1_odt <= 1'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p1_odt <= litedramcore_sdram_ext_dfi_p1_odt;
        end else begin
            litedramcore_sdram_master_p1_odt <= litedramcore_sdram_slave_p1_odt;
        end
    end else begin
        litedramcore_sdram_master_p1_odt <= litedramcore_sdram_csr_dfi_p1_odt;
    end
end
always @(*) begin
    litedramcore_sdram_master_p1_reset_n <= 1'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p1_reset_n <= litedramcore_sdram_ext_dfi_p1_reset_n;
        end else begin
            litedramcore_sdram_master_p1_reset_n <= litedramcore_sdram_slave_p1_reset_n;
        end
    end else begin
        litedramcore_sdram_master_p1_reset_n <= litedramcore_sdram_csr_dfi_p1_reset_n;
    end
end
always @(*) begin
    litedramcore_sdram_master_p1_act_n <= 1'd1;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p1_act_n <= litedramcore_sdram_ext_dfi_p1_act_n;
        end else begin
            litedramcore_sdram_master_p1_act_n <= litedramcore_sdram_slave_p1_act_n;
        end
    end else begin
        litedramcore_sdram_master_p1_act_n <= litedramcore_sdram_csr_dfi_p1_act_n;
    end
end
always @(*) begin
    litedramcore_sdram_master_p1_wrdata <= 64'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p1_wrdata <= litedramcore_sdram_ext_dfi_p1_wrdata;
        end else begin
            litedramcore_sdram_master_p1_wrdata <= litedramcore_sdram_slave_p1_wrdata;
        end
    end else begin
        litedramcore_sdram_master_p1_wrdata <= litedramcore_sdram_csr_dfi_p1_wrdata;
    end
end
always @(*) begin
    litedramcore_sdram_master_p1_wrdata_en <= 1'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p1_wrdata_en <= litedramcore_sdram_ext_dfi_p1_wrdata_en;
        end else begin
            litedramcore_sdram_master_p1_wrdata_en <= litedramcore_sdram_slave_p1_wrdata_en;
        end
    end else begin
        litedramcore_sdram_master_p1_wrdata_en <= litedramcore_sdram_csr_dfi_p1_wrdata_en;
    end
end
always @(*) begin
    litedramcore_sdram_master_p1_wrdata_mask <= 8'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p1_wrdata_mask <= litedramcore_sdram_ext_dfi_p1_wrdata_mask;
        end else begin
            litedramcore_sdram_master_p1_wrdata_mask <= litedramcore_sdram_slave_p1_wrdata_mask;
        end
    end else begin
        litedramcore_sdram_master_p1_wrdata_mask <= litedramcore_sdram_csr_dfi_p1_wrdata_mask;
    end
end
always @(*) begin
    litedramcore_sdram_master_p1_rddata_en <= 1'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p1_rddata_en <= litedramcore_sdram_ext_dfi_p1_rddata_en;
        end else begin
            litedramcore_sdram_master_p1_rddata_en <= litedramcore_sdram_slave_p1_rddata_en;
        end
    end else begin
        litedramcore_sdram_master_p1_rddata_en <= litedramcore_sdram_csr_dfi_p1_rddata_en;
    end
end
always @(*) begin
    litedramcore_sdram_master_p2_address <= 15'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p2_address <= litedramcore_sdram_ext_dfi_p2_address;
        end else begin
            litedramcore_sdram_master_p2_address <= litedramcore_sdram_slave_p2_address;
        end
    end else begin
        litedramcore_sdram_master_p2_address <= litedramcore_sdram_csr_dfi_p2_address;
    end
end
always @(*) begin
    litedramcore_sdram_master_p2_bank <= 3'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p2_bank <= litedramcore_sdram_ext_dfi_p2_bank;
        end else begin
            litedramcore_sdram_master_p2_bank <= litedramcore_sdram_slave_p2_bank;
        end
    end else begin
        litedramcore_sdram_master_p2_bank <= litedramcore_sdram_csr_dfi_p2_bank;
    end
end
always @(*) begin
    litedramcore_sdram_master_p2_cas_n <= 1'd1;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p2_cas_n <= litedramcore_sdram_ext_dfi_p2_cas_n;
        end else begin
            litedramcore_sdram_master_p2_cas_n <= litedramcore_sdram_slave_p2_cas_n;
        end
    end else begin
        litedramcore_sdram_master_p2_cas_n <= litedramcore_sdram_csr_dfi_p2_cas_n;
    end
end
always @(*) begin
    litedramcore_sdram_master_p2_cs_n <= 1'd1;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p2_cs_n <= litedramcore_sdram_ext_dfi_p2_cs_n;
        end else begin
            litedramcore_sdram_master_p2_cs_n <= litedramcore_sdram_slave_p2_cs_n;
            if (1'd0) begin
                litedramcore_sdram_master_p2_cs_n <= {2{litedramcore_sdram_slave_p2_cs_n}};
            end
        end
    end else begin
        litedramcore_sdram_master_p2_cs_n <= litedramcore_sdram_csr_dfi_p2_cs_n;
    end
end
always @(*) begin
    litedramcore_sdram_master_p2_ras_n <= 1'd1;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p2_ras_n <= litedramcore_sdram_ext_dfi_p2_ras_n;
        end else begin
            litedramcore_sdram_master_p2_ras_n <= litedramcore_sdram_slave_p2_ras_n;
        end
    end else begin
        litedramcore_sdram_master_p2_ras_n <= litedramcore_sdram_csr_dfi_p2_ras_n;
    end
end
always @(*) begin
    litedramcore_sdram_master_p2_we_n <= 1'd1;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p2_we_n <= litedramcore_sdram_ext_dfi_p2_we_n;
        end else begin
            litedramcore_sdram_master_p2_we_n <= litedramcore_sdram_slave_p2_we_n;
        end
    end else begin
        litedramcore_sdram_master_p2_we_n <= litedramcore_sdram_csr_dfi_p2_we_n;
    end
end
always @(*) begin
    litedramcore_sdram_master_p2_cke <= 1'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p2_cke <= litedramcore_sdram_ext_dfi_p2_cke;
        end else begin
            litedramcore_sdram_master_p2_cke <= litedramcore_sdram_slave_p2_cke;
        end
    end else begin
        litedramcore_sdram_master_p2_cke <= litedramcore_sdram_csr_dfi_p2_cke;
    end
end
always @(*) begin
    litedramcore_sdram_master_p2_odt <= 1'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p2_odt <= litedramcore_sdram_ext_dfi_p2_odt;
        end else begin
            litedramcore_sdram_master_p2_odt <= litedramcore_sdram_slave_p2_odt;
        end
    end else begin
        litedramcore_sdram_master_p2_odt <= litedramcore_sdram_csr_dfi_p2_odt;
    end
end
always @(*) begin
    litedramcore_sdram_master_p2_reset_n <= 1'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p2_reset_n <= litedramcore_sdram_ext_dfi_p2_reset_n;
        end else begin
            litedramcore_sdram_master_p2_reset_n <= litedramcore_sdram_slave_p2_reset_n;
        end
    end else begin
        litedramcore_sdram_master_p2_reset_n <= litedramcore_sdram_csr_dfi_p2_reset_n;
    end
end
always @(*) begin
    litedramcore_sdram_master_p2_act_n <= 1'd1;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p2_act_n <= litedramcore_sdram_ext_dfi_p2_act_n;
        end else begin
            litedramcore_sdram_master_p2_act_n <= litedramcore_sdram_slave_p2_act_n;
        end
    end else begin
        litedramcore_sdram_master_p2_act_n <= litedramcore_sdram_csr_dfi_p2_act_n;
    end
end
always @(*) begin
    litedramcore_sdram_master_p2_wrdata <= 64'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p2_wrdata <= litedramcore_sdram_ext_dfi_p2_wrdata;
        end else begin
            litedramcore_sdram_master_p2_wrdata <= litedramcore_sdram_slave_p2_wrdata;
        end
    end else begin
        litedramcore_sdram_master_p2_wrdata <= litedramcore_sdram_csr_dfi_p2_wrdata;
    end
end
always @(*) begin
    litedramcore_sdram_master_p2_wrdata_en <= 1'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p2_wrdata_en <= litedramcore_sdram_ext_dfi_p2_wrdata_en;
        end else begin
            litedramcore_sdram_master_p2_wrdata_en <= litedramcore_sdram_slave_p2_wrdata_en;
        end
    end else begin
        litedramcore_sdram_master_p2_wrdata_en <= litedramcore_sdram_csr_dfi_p2_wrdata_en;
    end
end
always @(*) begin
    litedramcore_sdram_master_p2_wrdata_mask <= 8'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p2_wrdata_mask <= litedramcore_sdram_ext_dfi_p2_wrdata_mask;
        end else begin
            litedramcore_sdram_master_p2_wrdata_mask <= litedramcore_sdram_slave_p2_wrdata_mask;
        end
    end else begin
        litedramcore_sdram_master_p2_wrdata_mask <= litedramcore_sdram_csr_dfi_p2_wrdata_mask;
    end
end
always @(*) begin
    litedramcore_sdram_master_p2_rddata_en <= 1'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p2_rddata_en <= litedramcore_sdram_ext_dfi_p2_rddata_en;
        end else begin
            litedramcore_sdram_master_p2_rddata_en <= litedramcore_sdram_slave_p2_rddata_en;
        end
    end else begin
        litedramcore_sdram_master_p2_rddata_en <= litedramcore_sdram_csr_dfi_p2_rddata_en;
    end
end
always @(*) begin
    litedramcore_sdram_master_p3_address <= 15'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p3_address <= litedramcore_sdram_ext_dfi_p3_address;
        end else begin
            litedramcore_sdram_master_p3_address <= litedramcore_sdram_slave_p3_address;
        end
    end else begin
        litedramcore_sdram_master_p3_address <= litedramcore_sdram_csr_dfi_p3_address;
    end
end
always @(*) begin
    litedramcore_sdram_master_p3_bank <= 3'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p3_bank <= litedramcore_sdram_ext_dfi_p3_bank;
        end else begin
            litedramcore_sdram_master_p3_bank <= litedramcore_sdram_slave_p3_bank;
        end
    end else begin
        litedramcore_sdram_master_p3_bank <= litedramcore_sdram_csr_dfi_p3_bank;
    end
end
always @(*) begin
    litedramcore_sdram_master_p3_cas_n <= 1'd1;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p3_cas_n <= litedramcore_sdram_ext_dfi_p3_cas_n;
        end else begin
            litedramcore_sdram_master_p3_cas_n <= litedramcore_sdram_slave_p3_cas_n;
        end
    end else begin
        litedramcore_sdram_master_p3_cas_n <= litedramcore_sdram_csr_dfi_p3_cas_n;
    end
end
always @(*) begin
    litedramcore_sdram_master_p3_cs_n <= 1'd1;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p3_cs_n <= litedramcore_sdram_ext_dfi_p3_cs_n;
        end else begin
            litedramcore_sdram_master_p3_cs_n <= litedramcore_sdram_slave_p3_cs_n;
            if (1'd0) begin
                litedramcore_sdram_master_p3_cs_n <= {2{litedramcore_sdram_slave_p3_cs_n}};
            end
        end
    end else begin
        litedramcore_sdram_master_p3_cs_n <= litedramcore_sdram_csr_dfi_p3_cs_n;
    end
end
always @(*) begin
    litedramcore_sdram_master_p3_ras_n <= 1'd1;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p3_ras_n <= litedramcore_sdram_ext_dfi_p3_ras_n;
        end else begin
            litedramcore_sdram_master_p3_ras_n <= litedramcore_sdram_slave_p3_ras_n;
        end
    end else begin
        litedramcore_sdram_master_p3_ras_n <= litedramcore_sdram_csr_dfi_p3_ras_n;
    end
end
always @(*) begin
    litedramcore_sdram_master_p3_we_n <= 1'd1;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p3_we_n <= litedramcore_sdram_ext_dfi_p3_we_n;
        end else begin
            litedramcore_sdram_master_p3_we_n <= litedramcore_sdram_slave_p3_we_n;
        end
    end else begin
        litedramcore_sdram_master_p3_we_n <= litedramcore_sdram_csr_dfi_p3_we_n;
    end
end
always @(*) begin
    litedramcore_sdram_master_p3_cke <= 1'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p3_cke <= litedramcore_sdram_ext_dfi_p3_cke;
        end else begin
            litedramcore_sdram_master_p3_cke <= litedramcore_sdram_slave_p3_cke;
        end
    end else begin
        litedramcore_sdram_master_p3_cke <= litedramcore_sdram_csr_dfi_p3_cke;
    end
end
always @(*) begin
    litedramcore_sdram_master_p3_odt <= 1'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p3_odt <= litedramcore_sdram_ext_dfi_p3_odt;
        end else begin
            litedramcore_sdram_master_p3_odt <= litedramcore_sdram_slave_p3_odt;
        end
    end else begin
        litedramcore_sdram_master_p3_odt <= litedramcore_sdram_csr_dfi_p3_odt;
    end
end
always @(*) begin
    litedramcore_sdram_master_p3_reset_n <= 1'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p3_reset_n <= litedramcore_sdram_ext_dfi_p3_reset_n;
        end else begin
            litedramcore_sdram_master_p3_reset_n <= litedramcore_sdram_slave_p3_reset_n;
        end
    end else begin
        litedramcore_sdram_master_p3_reset_n <= litedramcore_sdram_csr_dfi_p3_reset_n;
    end
end
always @(*) begin
    litedramcore_sdram_master_p3_act_n <= 1'd1;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p3_act_n <= litedramcore_sdram_ext_dfi_p3_act_n;
        end else begin
            litedramcore_sdram_master_p3_act_n <= litedramcore_sdram_slave_p3_act_n;
        end
    end else begin
        litedramcore_sdram_master_p3_act_n <= litedramcore_sdram_csr_dfi_p3_act_n;
    end
end
always @(*) begin
    litedramcore_sdram_master_p3_wrdata <= 64'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p3_wrdata <= litedramcore_sdram_ext_dfi_p3_wrdata;
        end else begin
            litedramcore_sdram_master_p3_wrdata <= litedramcore_sdram_slave_p3_wrdata;
        end
    end else begin
        litedramcore_sdram_master_p3_wrdata <= litedramcore_sdram_csr_dfi_p3_wrdata;
    end
end
always @(*) begin
    litedramcore_sdram_master_p3_wrdata_en <= 1'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p3_wrdata_en <= litedramcore_sdram_ext_dfi_p3_wrdata_en;
        end else begin
            litedramcore_sdram_master_p3_wrdata_en <= litedramcore_sdram_slave_p3_wrdata_en;
        end
    end else begin
        litedramcore_sdram_master_p3_wrdata_en <= litedramcore_sdram_csr_dfi_p3_wrdata_en;
    end
end
always @(*) begin
    litedramcore_sdram_master_p3_wrdata_mask <= 8'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p3_wrdata_mask <= litedramcore_sdram_ext_dfi_p3_wrdata_mask;
        end else begin
            litedramcore_sdram_master_p3_wrdata_mask <= litedramcore_sdram_slave_p3_wrdata_mask;
        end
    end else begin
        litedramcore_sdram_master_p3_wrdata_mask <= litedramcore_sdram_csr_dfi_p3_wrdata_mask;
    end
end
always @(*) begin
    litedramcore_sdram_master_p3_rddata_en <= 1'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_master_p3_rddata_en <= litedramcore_sdram_ext_dfi_p3_rddata_en;
        end else begin
            litedramcore_sdram_master_p3_rddata_en <= litedramcore_sdram_slave_p3_rddata_en;
        end
    end else begin
        litedramcore_sdram_master_p3_rddata_en <= litedramcore_sdram_csr_dfi_p3_rddata_en;
    end
end
always @(*) begin
    litedramcore_sdram_csr_dfi_p0_rddata <= 64'd0;
    if (litedramcore_sdram_sel) begin
    end else begin
        litedramcore_sdram_csr_dfi_p0_rddata <= litedramcore_sdram_master_p0_rddata;
    end
end
always @(*) begin
    litedramcore_sdram_csr_dfi_p0_rddata_valid <= 1'd0;
    if (litedramcore_sdram_sel) begin
    end else begin
        litedramcore_sdram_csr_dfi_p0_rddata_valid <= litedramcore_sdram_master_p0_rddata_valid;
    end
end
always @(*) begin
    litedramcore_sdram_csr_dfi_p1_rddata <= 64'd0;
    if (litedramcore_sdram_sel) begin
    end else begin
        litedramcore_sdram_csr_dfi_p1_rddata <= litedramcore_sdram_master_p1_rddata;
    end
end
always @(*) begin
    litedramcore_sdram_csr_dfi_p1_rddata_valid <= 1'd0;
    if (litedramcore_sdram_sel) begin
    end else begin
        litedramcore_sdram_csr_dfi_p1_rddata_valid <= litedramcore_sdram_master_p1_rddata_valid;
    end
end
always @(*) begin
    litedramcore_sdram_csr_dfi_p2_rddata <= 64'd0;
    if (litedramcore_sdram_sel) begin
    end else begin
        litedramcore_sdram_csr_dfi_p2_rddata <= litedramcore_sdram_master_p2_rddata;
    end
end
always @(*) begin
    litedramcore_sdram_csr_dfi_p2_rddata_valid <= 1'd0;
    if (litedramcore_sdram_sel) begin
    end else begin
        litedramcore_sdram_csr_dfi_p2_rddata_valid <= litedramcore_sdram_master_p2_rddata_valid;
    end
end
always @(*) begin
    litedramcore_sdram_csr_dfi_p3_rddata <= 64'd0;
    if (litedramcore_sdram_sel) begin
    end else begin
        litedramcore_sdram_csr_dfi_p3_rddata <= litedramcore_sdram_master_p3_rddata;
    end
end
always @(*) begin
    litedramcore_sdram_csr_dfi_p3_rddata_valid <= 1'd0;
    if (litedramcore_sdram_sel) begin
    end else begin
        litedramcore_sdram_csr_dfi_p3_rddata_valid <= litedramcore_sdram_master_p3_rddata_valid;
    end
end
always @(*) begin
    litedramcore_sdram_ext_dfi_p0_rddata <= 64'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_ext_dfi_p0_rddata <= litedramcore_sdram_master_p0_rddata;
        end else begin
        end
    end else begin
    end
end
always @(*) begin
    litedramcore_sdram_ext_dfi_p0_rddata_valid <= 1'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_ext_dfi_p0_rddata_valid <= litedramcore_sdram_master_p0_rddata_valid;
        end else begin
        end
    end else begin
    end
end
always @(*) begin
    litedramcore_sdram_ext_dfi_p1_rddata <= 64'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_ext_dfi_p1_rddata <= litedramcore_sdram_master_p1_rddata;
        end else begin
        end
    end else begin
    end
end
always @(*) begin
    litedramcore_sdram_ext_dfi_p1_rddata_valid <= 1'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_ext_dfi_p1_rddata_valid <= litedramcore_sdram_master_p1_rddata_valid;
        end else begin
        end
    end else begin
    end
end
always @(*) begin
    litedramcore_sdram_ext_dfi_p2_rddata <= 64'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_ext_dfi_p2_rddata <= litedramcore_sdram_master_p2_rddata;
        end else begin
        end
    end else begin
    end
end
always @(*) begin
    litedramcore_sdram_ext_dfi_p2_rddata_valid <= 1'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_ext_dfi_p2_rddata_valid <= litedramcore_sdram_master_p2_rddata_valid;
        end else begin
        end
    end else begin
    end
end
always @(*) begin
    litedramcore_sdram_slave_p0_rddata <= 64'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
        end else begin
            litedramcore_sdram_slave_p0_rddata <= litedramcore_sdram_master_p0_rddata;
        end
    end else begin
    end
end
always @(*) begin
    litedramcore_sdram_slave_p0_rddata_valid <= 1'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
        end else begin
            litedramcore_sdram_slave_p0_rddata_valid <= litedramcore_sdram_master_p0_rddata_valid;
        end
    end else begin
    end
end
always @(*) begin
    litedramcore_sdram_ext_dfi_p3_rddata <= 64'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_ext_dfi_p3_rddata <= litedramcore_sdram_master_p3_rddata;
        end else begin
        end
    end else begin
    end
end
always @(*) begin
    litedramcore_sdram_ext_dfi_p3_rddata_valid <= 1'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
            litedramcore_sdram_ext_dfi_p3_rddata_valid <= litedramcore_sdram_master_p3_rddata_valid;
        end else begin
        end
    end else begin
    end
end
always @(*) begin
    litedramcore_sdram_slave_p1_rddata <= 64'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
        end else begin
            litedramcore_sdram_slave_p1_rddata <= litedramcore_sdram_master_p1_rddata;
        end
    end else begin
    end
end
always @(*) begin
    litedramcore_sdram_slave_p1_rddata_valid <= 1'd0;
    if (litedramcore_sdram_sel) begin
        if (litedramcore_sdram_ext_dfi_sel) begin
        end else begin
            litedramcore_sdram_slave_p1_rddata_valid <= litedramcore_sdram_master_p1_rddata_valid;
        end
    end else begin
    end
end
assign litedramcore_sdram_csr_dfi_p0_cke = litedramcore_sdram_cke;
assign litedramcore_sdram_csr_dfi_p1_cke = litedramcore_sdram_cke;
assign litedramcore_sdram_csr_dfi_p2_cke = litedramcore_sdram_cke;
assign litedramcore_sdram_csr_dfi_p3_cke = litedramcore_sdram_cke;
assign litedramcore_sdram_csr_dfi_p0_odt = litedramcore_sdram_odt;
assign litedramcore_sdram_csr_dfi_p1_odt = litedramcore_sdram_odt;
assign litedramcore_sdram_csr_dfi_p2_odt = litedramcore_sdram_odt;
assign litedramcore_sdram_csr_dfi_p3_odt = litedramcore_sdram_odt;
assign litedramcore_sdram_csr_dfi_p0_reset_n = litedramcore_sdram_reset_n;
assign litedramcore_sdram_csr_dfi_p1_reset_n = litedramcore_sdram_reset_n;
assign litedramcore_sdram_csr_dfi_p2_reset_n = litedramcore_sdram_reset_n;
assign litedramcore_sdram_csr_dfi_p3_reset_n = litedramcore_sdram_reset_n;
always @(*) begin
    litedramcore_sdram_csr_dfi_p0_cas_n <= 1'd1;
    if (litedramcore_sdram_phaseinjector0_command_issue_re) begin
        litedramcore_sdram_csr_dfi_p0_cas_n <= (~litedramcore_sdram_phaseinjector0_csrfield_cas);
    end else begin
        litedramcore_sdram_csr_dfi_p0_cas_n <= 1'd1;
    end
end
always @(*) begin
    litedramcore_sdram_csr_dfi_p0_cs_n <= 1'd1;
    if (litedramcore_sdram_phaseinjector0_command_issue_re) begin
        if (litedramcore_sdram_phaseinjector0_csrfield_cs_top) begin
            litedramcore_sdram_csr_dfi_p0_cs_n <= 2'd2;
        end else begin
            if (litedramcore_sdram_phaseinjector0_csrfield_cs_bottom) begin
                litedramcore_sdram_csr_dfi_p0_cs_n <= 1'd1;
            end else begin
                litedramcore_sdram_csr_dfi_p0_cs_n <= {1{(~litedramcore_sdram_phaseinjector0_csrfield_cs)}};
            end
        end
    end else begin
        litedramcore_sdram_csr_dfi_p0_cs_n <= {1{1'd1}};
    end
end
always @(*) begin
    litedramcore_sdram_csr_dfi_p0_ras_n <= 1'd1;
    if (litedramcore_sdram_phaseinjector0_command_issue_re) begin
        litedramcore_sdram_csr_dfi_p0_ras_n <= (~litedramcore_sdram_phaseinjector0_csrfield_ras);
    end else begin
        litedramcore_sdram_csr_dfi_p0_ras_n <= 1'd1;
    end
end
always @(*) begin
    litedramcore_sdram_csr_dfi_p0_we_n <= 1'd1;
    if (litedramcore_sdram_phaseinjector0_command_issue_re) begin
        litedramcore_sdram_csr_dfi_p0_we_n <= (~litedramcore_sdram_phaseinjector0_csrfield_we);
    end else begin
        litedramcore_sdram_csr_dfi_p0_we_n <= 1'd1;
    end
end
assign litedramcore_sdram_csr_dfi_p0_address = litedramcore_sdram_phaseinjector0_address_storage;
assign litedramcore_sdram_csr_dfi_p0_bank = litedramcore_sdram_phaseinjector0_baddress_storage;
assign litedramcore_sdram_csr_dfi_p0_wrdata_en = (litedramcore_sdram_phaseinjector0_command_issue_re & litedramcore_sdram_phaseinjector0_csrfield_wren);
assign litedramcore_sdram_csr_dfi_p0_rddata_en = (litedramcore_sdram_phaseinjector0_command_issue_re & litedramcore_sdram_phaseinjector0_csrfield_rden);
assign litedramcore_sdram_csr_dfi_p0_wrdata = litedramcore_sdram_phaseinjector0_wrdata_storage;
assign litedramcore_sdram_csr_dfi_p0_wrdata_mask = 1'd0;
always @(*) begin
    litedramcore_sdram_csr_dfi_p1_cas_n <= 1'd1;
    if (litedramcore_sdram_phaseinjector1_command_issue_re) begin
        litedramcore_sdram_csr_dfi_p1_cas_n <= (~litedramcore_sdram_phaseinjector1_csrfield_cas);
    end else begin
        litedramcore_sdram_csr_dfi_p1_cas_n <= 1'd1;
    end
end
always @(*) begin
    litedramcore_sdram_csr_dfi_p1_cs_n <= 1'd1;
    if (litedramcore_sdram_phaseinjector1_command_issue_re) begin
        if (litedramcore_sdram_phaseinjector1_csrfield_cs_top) begin
            litedramcore_sdram_csr_dfi_p1_cs_n <= 2'd2;
        end else begin
            if (litedramcore_sdram_phaseinjector1_csrfield_cs_bottom) begin
                litedramcore_sdram_csr_dfi_p1_cs_n <= 1'd1;
            end else begin
                litedramcore_sdram_csr_dfi_p1_cs_n <= {1{(~litedramcore_sdram_phaseinjector1_csrfield_cs)}};
            end
        end
    end else begin
        litedramcore_sdram_csr_dfi_p1_cs_n <= {1{1'd1}};
    end
end
always @(*) begin
    litedramcore_sdram_csr_dfi_p1_ras_n <= 1'd1;
    if (litedramcore_sdram_phaseinjector1_command_issue_re) begin
        litedramcore_sdram_csr_dfi_p1_ras_n <= (~litedramcore_sdram_phaseinjector1_csrfield_ras);
    end else begin
        litedramcore_sdram_csr_dfi_p1_ras_n <= 1'd1;
    end
end
always @(*) begin
    litedramcore_sdram_csr_dfi_p1_we_n <= 1'd1;
    if (litedramcore_sdram_phaseinjector1_command_issue_re) begin
        litedramcore_sdram_csr_dfi_p1_we_n <= (~litedramcore_sdram_phaseinjector1_csrfield_we);
    end else begin
        litedramcore_sdram_csr_dfi_p1_we_n <= 1'd1;
    end
end
assign litedramcore_sdram_csr_dfi_p1_address = litedramcore_sdram_phaseinjector1_address_storage;
assign litedramcore_sdram_csr_dfi_p1_bank = litedramcore_sdram_phaseinjector1_baddress_storage;
assign litedramcore_sdram_csr_dfi_p1_wrdata_en = (litedramcore_sdram_phaseinjector1_command_issue_re & litedramcore_sdram_phaseinjector1_csrfield_wren);
assign litedramcore_sdram_csr_dfi_p1_rddata_en = (litedramcore_sdram_phaseinjector1_command_issue_re & litedramcore_sdram_phaseinjector1_csrfield_rden);
assign litedramcore_sdram_csr_dfi_p1_wrdata = litedramcore_sdram_phaseinjector1_wrdata_storage;
assign litedramcore_sdram_csr_dfi_p1_wrdata_mask = 1'd0;
always @(*) begin
    litedramcore_sdram_csr_dfi_p2_cas_n <= 1'd1;
    if (litedramcore_sdram_phaseinjector2_command_issue_re) begin
        litedramcore_sdram_csr_dfi_p2_cas_n <= (~litedramcore_sdram_phaseinjector2_csrfield_cas);
    end else begin
        litedramcore_sdram_csr_dfi_p2_cas_n <= 1'd1;
    end
end
always @(*) begin
    litedramcore_sdram_csr_dfi_p2_cs_n <= 1'd1;
    if (litedramcore_sdram_phaseinjector2_command_issue_re) begin
        if (litedramcore_sdram_phaseinjector2_csrfield_cs_top) begin
            litedramcore_sdram_csr_dfi_p2_cs_n <= 2'd2;
        end else begin
            if (litedramcore_sdram_phaseinjector2_csrfield_cs_bottom) begin
                litedramcore_sdram_csr_dfi_p2_cs_n <= 1'd1;
            end else begin
                litedramcore_sdram_csr_dfi_p2_cs_n <= {1{(~litedramcore_sdram_phaseinjector2_csrfield_cs)}};
            end
        end
    end else begin
        litedramcore_sdram_csr_dfi_p2_cs_n <= {1{1'd1}};
    end
end
always @(*) begin
    litedramcore_sdram_csr_dfi_p2_ras_n <= 1'd1;
    if (litedramcore_sdram_phaseinjector2_command_issue_re) begin
        litedramcore_sdram_csr_dfi_p2_ras_n <= (~litedramcore_sdram_phaseinjector2_csrfield_ras);
    end else begin
        litedramcore_sdram_csr_dfi_p2_ras_n <= 1'd1;
    end
end
always @(*) begin
    litedramcore_sdram_csr_dfi_p2_we_n <= 1'd1;
    if (litedramcore_sdram_phaseinjector2_command_issue_re) begin
        litedramcore_sdram_csr_dfi_p2_we_n <= (~litedramcore_sdram_phaseinjector2_csrfield_we);
    end else begin
        litedramcore_sdram_csr_dfi_p2_we_n <= 1'd1;
    end
end
assign litedramcore_sdram_csr_dfi_p2_address = litedramcore_sdram_phaseinjector2_address_storage;
assign litedramcore_sdram_csr_dfi_p2_bank = litedramcore_sdram_phaseinjector2_baddress_storage;
assign litedramcore_sdram_csr_dfi_p2_wrdata_en = (litedramcore_sdram_phaseinjector2_command_issue_re & litedramcore_sdram_phaseinjector2_csrfield_wren);
assign litedramcore_sdram_csr_dfi_p2_rddata_en = (litedramcore_sdram_phaseinjector2_command_issue_re & litedramcore_sdram_phaseinjector2_csrfield_rden);
assign litedramcore_sdram_csr_dfi_p2_wrdata = litedramcore_sdram_phaseinjector2_wrdata_storage;
assign litedramcore_sdram_csr_dfi_p2_wrdata_mask = 1'd0;
always @(*) begin
    litedramcore_sdram_csr_dfi_p3_cas_n <= 1'd1;
    if (litedramcore_sdram_phaseinjector3_command_issue_re) begin
        litedramcore_sdram_csr_dfi_p3_cas_n <= (~litedramcore_sdram_phaseinjector3_csrfield_cas);
    end else begin
        litedramcore_sdram_csr_dfi_p3_cas_n <= 1'd1;
    end
end
always @(*) begin
    litedramcore_sdram_csr_dfi_p3_cs_n <= 1'd1;
    if (litedramcore_sdram_phaseinjector3_command_issue_re) begin
        if (litedramcore_sdram_phaseinjector3_csrfield_cs_top) begin
            litedramcore_sdram_csr_dfi_p3_cs_n <= 2'd2;
        end else begin
            if (litedramcore_sdram_phaseinjector3_csrfield_cs_bottom) begin
                litedramcore_sdram_csr_dfi_p3_cs_n <= 1'd1;
            end else begin
                litedramcore_sdram_csr_dfi_p3_cs_n <= {1{(~litedramcore_sdram_phaseinjector3_csrfield_cs)}};
            end
        end
    end else begin
        litedramcore_sdram_csr_dfi_p3_cs_n <= {1{1'd1}};
    end
end
always @(*) begin
    litedramcore_sdram_csr_dfi_p3_ras_n <= 1'd1;
    if (litedramcore_sdram_phaseinjector3_command_issue_re) begin
        litedramcore_sdram_csr_dfi_p3_ras_n <= (~litedramcore_sdram_phaseinjector3_csrfield_ras);
    end else begin
        litedramcore_sdram_csr_dfi_p3_ras_n <= 1'd1;
    end
end
always @(*) begin
    litedramcore_sdram_csr_dfi_p3_we_n <= 1'd1;
    if (litedramcore_sdram_phaseinjector3_command_issue_re) begin
        litedramcore_sdram_csr_dfi_p3_we_n <= (~litedramcore_sdram_phaseinjector3_csrfield_we);
    end else begin
        litedramcore_sdram_csr_dfi_p3_we_n <= 1'd1;
    end
end
assign litedramcore_sdram_csr_dfi_p3_address = litedramcore_sdram_phaseinjector3_address_storage;
assign litedramcore_sdram_csr_dfi_p3_bank = litedramcore_sdram_phaseinjector3_baddress_storage;
assign litedramcore_sdram_csr_dfi_p3_wrdata_en = (litedramcore_sdram_phaseinjector3_command_issue_re & litedramcore_sdram_phaseinjector3_csrfield_wren);
assign litedramcore_sdram_csr_dfi_p3_rddata_en = (litedramcore_sdram_phaseinjector3_command_issue_re & litedramcore_sdram_phaseinjector3_csrfield_rden);
assign litedramcore_sdram_csr_dfi_p3_wrdata = litedramcore_sdram_phaseinjector3_wrdata_storage;
assign litedramcore_sdram_csr_dfi_p3_wrdata_mask = 1'd0;
assign litedramcore_sdram_bankmachine0_req_valid = litedramcore_sdram_interface_bank0_valid;
assign litedramcore_sdram_interface_bank0_ready = litedramcore_sdram_bankmachine0_req_ready;
assign litedramcore_sdram_bankmachine0_req_we = litedramcore_sdram_interface_bank0_we;
assign litedramcore_sdram_bankmachine0_req_addr = litedramcore_sdram_interface_bank0_addr;
assign litedramcore_sdram_interface_bank0_lock = litedramcore_sdram_bankmachine0_req_lock;
assign litedramcore_sdram_interface_bank0_wdata_ready = litedramcore_sdram_bankmachine0_req_wdata_ready;
assign litedramcore_sdram_interface_bank0_rdata_valid = litedramcore_sdram_bankmachine0_req_rdata_valid;
assign litedramcore_sdram_bankmachine1_req_valid = litedramcore_sdram_interface_bank1_valid;
assign litedramcore_sdram_interface_bank1_ready = litedramcore_sdram_bankmachine1_req_ready;
assign litedramcore_sdram_bankmachine1_req_we = litedramcore_sdram_interface_bank1_we;
assign litedramcore_sdram_bankmachine1_req_addr = litedramcore_sdram_interface_bank1_addr;
assign litedramcore_sdram_interface_bank1_lock = litedramcore_sdram_bankmachine1_req_lock;
assign litedramcore_sdram_interface_bank1_wdata_ready = litedramcore_sdram_bankmachine1_req_wdata_ready;
assign litedramcore_sdram_interface_bank1_rdata_valid = litedramcore_sdram_bankmachine1_req_rdata_valid;
assign litedramcore_sdram_bankmachine2_req_valid = litedramcore_sdram_interface_bank2_valid;
assign litedramcore_sdram_interface_bank2_ready = litedramcore_sdram_bankmachine2_req_ready;
assign litedramcore_sdram_bankmachine2_req_we = litedramcore_sdram_interface_bank2_we;
assign litedramcore_sdram_bankmachine2_req_addr = litedramcore_sdram_interface_bank2_addr;
assign litedramcore_sdram_interface_bank2_lock = litedramcore_sdram_bankmachine2_req_lock;
assign litedramcore_sdram_interface_bank2_wdata_ready = litedramcore_sdram_bankmachine2_req_wdata_ready;
assign litedramcore_sdram_interface_bank2_rdata_valid = litedramcore_sdram_bankmachine2_req_rdata_valid;
assign litedramcore_sdram_bankmachine3_req_valid = litedramcore_sdram_interface_bank3_valid;
assign litedramcore_sdram_interface_bank3_ready = litedramcore_sdram_bankmachine3_req_ready;
assign litedramcore_sdram_bankmachine3_req_we = litedramcore_sdram_interface_bank3_we;
assign litedramcore_sdram_bankmachine3_req_addr = litedramcore_sdram_interface_bank3_addr;
assign litedramcore_sdram_interface_bank3_lock = litedramcore_sdram_bankmachine3_req_lock;
assign litedramcore_sdram_interface_bank3_wdata_ready = litedramcore_sdram_bankmachine3_req_wdata_ready;
assign litedramcore_sdram_interface_bank3_rdata_valid = litedramcore_sdram_bankmachine3_req_rdata_valid;
assign litedramcore_sdram_bankmachine4_req_valid = litedramcore_sdram_interface_bank4_valid;
assign litedramcore_sdram_interface_bank4_ready = litedramcore_sdram_bankmachine4_req_ready;
assign litedramcore_sdram_bankmachine4_req_we = litedramcore_sdram_interface_bank4_we;
assign litedramcore_sdram_bankmachine4_req_addr = litedramcore_sdram_interface_bank4_addr;
assign litedramcore_sdram_interface_bank4_lock = litedramcore_sdram_bankmachine4_req_lock;
assign litedramcore_sdram_interface_bank4_wdata_ready = litedramcore_sdram_bankmachine4_req_wdata_ready;
assign litedramcore_sdram_interface_bank4_rdata_valid = litedramcore_sdram_bankmachine4_req_rdata_valid;
assign litedramcore_sdram_bankmachine5_req_valid = litedramcore_sdram_interface_bank5_valid;
assign litedramcore_sdram_interface_bank5_ready = litedramcore_sdram_bankmachine5_req_ready;
assign litedramcore_sdram_bankmachine5_req_we = litedramcore_sdram_interface_bank5_we;
assign litedramcore_sdram_bankmachine5_req_addr = litedramcore_sdram_interface_bank5_addr;
assign litedramcore_sdram_interface_bank5_lock = litedramcore_sdram_bankmachine5_req_lock;
assign litedramcore_sdram_interface_bank5_wdata_ready = litedramcore_sdram_bankmachine5_req_wdata_ready;
assign litedramcore_sdram_interface_bank5_rdata_valid = litedramcore_sdram_bankmachine5_req_rdata_valid;
assign litedramcore_sdram_bankmachine6_req_valid = litedramcore_sdram_interface_bank6_valid;
assign litedramcore_sdram_interface_bank6_ready = litedramcore_sdram_bankmachine6_req_ready;
assign litedramcore_sdram_bankmachine6_req_we = litedramcore_sdram_interface_bank6_we;
assign litedramcore_sdram_bankmachine6_req_addr = litedramcore_sdram_interface_bank6_addr;
assign litedramcore_sdram_interface_bank6_lock = litedramcore_sdram_bankmachine6_req_lock;
assign litedramcore_sdram_interface_bank6_wdata_ready = litedramcore_sdram_bankmachine6_req_wdata_ready;
assign litedramcore_sdram_interface_bank6_rdata_valid = litedramcore_sdram_bankmachine6_req_rdata_valid;
assign litedramcore_sdram_bankmachine7_req_valid = litedramcore_sdram_interface_bank7_valid;
assign litedramcore_sdram_interface_bank7_ready = litedramcore_sdram_bankmachine7_req_ready;
assign litedramcore_sdram_bankmachine7_req_we = litedramcore_sdram_interface_bank7_we;
assign litedramcore_sdram_bankmachine7_req_addr = litedramcore_sdram_interface_bank7_addr;
assign litedramcore_sdram_interface_bank7_lock = litedramcore_sdram_bankmachine7_req_lock;
assign litedramcore_sdram_interface_bank7_wdata_ready = litedramcore_sdram_bankmachine7_req_wdata_ready;
assign litedramcore_sdram_interface_bank7_rdata_valid = litedramcore_sdram_bankmachine7_req_rdata_valid;
assign litedramcore_sdram_timer_wait = (~litedramcore_sdram_timer_done0);
assign litedramcore_sdram_postponer_req_i = litedramcore_sdram_timer_done0;
assign litedramcore_sdram_wants_refresh = litedramcore_sdram_postponer_req_o;
assign litedramcore_sdram_wants_zqcs = litedramcore_sdram_zqcs_timer_done0;
assign litedramcore_sdram_zqcs_timer_wait = (~litedramcore_sdram_zqcs_executer_done);
assign litedramcore_sdram_timer_done1 = (litedramcore_sdram_timer_count1 == 1'd0);
assign litedramcore_sdram_timer_done0 = litedramcore_sdram_timer_done1;
assign litedramcore_sdram_timer_count0 = litedramcore_sdram_timer_count1;
assign litedramcore_sdram_sequencer_start1 = (litedramcore_sdram_sequencer_start0 | (litedramcore_sdram_sequencer_count != 1'd0));
assign litedramcore_sdram_sequencer_done0 = (litedramcore_sdram_sequencer_done1 & (litedramcore_sdram_sequencer_count == 1'd0));
assign litedramcore_sdram_zqcs_timer_done1 = (litedramcore_sdram_zqcs_timer_count1 == 1'd0);
assign litedramcore_sdram_zqcs_timer_done0 = litedramcore_sdram_zqcs_timer_done1;
assign litedramcore_sdram_zqcs_timer_count0 = litedramcore_sdram_zqcs_timer_count1;
always @(*) begin
    litedramcore_refresher_next_state <= 2'd0;
    litedramcore_refresher_next_state <= litedramcore_refresher_state;
    case (litedramcore_refresher_state)
        1'd1: begin
            if (litedramcore_sdram_cmd_ready) begin
                litedramcore_refresher_next_state <= 2'd2;
            end
        end
        2'd2: begin
            if (litedramcore_sdram_sequencer_done0) begin
                if (litedramcore_sdram_wants_zqcs) begin
                    litedramcore_refresher_next_state <= 2'd3;
                end else begin
                    litedramcore_refresher_next_state <= 1'd0;
                end
            end
        end
        2'd3: begin
            if (litedramcore_sdram_zqcs_executer_done) begin
                litedramcore_refresher_next_state <= 1'd0;
            end
        end
        default: begin
            if (1'd1) begin
                if (litedramcore_sdram_wants_refresh) begin
                    litedramcore_refresher_next_state <= 1'd1;
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_sequencer_start0 <= 1'd0;
    case (litedramcore_refresher_state)
        1'd1: begin
            if (litedramcore_sdram_cmd_ready) begin
                litedramcore_sdram_sequencer_start0 <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_cmd_valid <= 1'd0;
    case (litedramcore_refresher_state)
        1'd1: begin
            litedramcore_sdram_cmd_valid <= 1'd1;
        end
        2'd2: begin
            litedramcore_sdram_cmd_valid <= 1'd1;
            if (litedramcore_sdram_sequencer_done0) begin
                if (litedramcore_sdram_wants_zqcs) begin
                end else begin
                    litedramcore_sdram_cmd_valid <= 1'd0;
                end
            end
        end
        2'd3: begin
            litedramcore_sdram_cmd_valid <= 1'd1;
            if (litedramcore_sdram_zqcs_executer_done) begin
                litedramcore_sdram_cmd_valid <= 1'd0;
            end
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_zqcs_executer_start <= 1'd0;
    case (litedramcore_refresher_state)
        1'd1: begin
        end
        2'd2: begin
            if (litedramcore_sdram_sequencer_done0) begin
                if (litedramcore_sdram_wants_zqcs) begin
                    litedramcore_sdram_zqcs_executer_start <= 1'd1;
                end else begin
                end
            end
        end
        2'd3: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_cmd_last <= 1'd0;
    case (litedramcore_refresher_state)
        1'd1: begin
        end
        2'd2: begin
            if (litedramcore_sdram_sequencer_done0) begin
                if (litedramcore_sdram_wants_zqcs) begin
                end else begin
                    litedramcore_sdram_cmd_last <= 1'd1;
                end
            end
        end
        2'd3: begin
            if (litedramcore_sdram_zqcs_executer_done) begin
                litedramcore_sdram_cmd_last <= 1'd1;
            end
        end
        default: begin
        end
    endcase
end
assign litedramcore_sdram_bankmachine0_sink_valid = litedramcore_sdram_bankmachine0_req_valid;
assign litedramcore_sdram_bankmachine0_req_ready = litedramcore_sdram_bankmachine0_sink_ready;
assign litedramcore_sdram_bankmachine0_sink_payload_we = litedramcore_sdram_bankmachine0_req_we;
assign litedramcore_sdram_bankmachine0_sink_payload_addr = litedramcore_sdram_bankmachine0_req_addr;
assign litedramcore_sdram_bankmachine0_sink_sink_valid = litedramcore_sdram_bankmachine0_source_valid;
assign litedramcore_sdram_bankmachine0_source_ready = litedramcore_sdram_bankmachine0_sink_sink_ready;
assign litedramcore_sdram_bankmachine0_sink_sink_first = litedramcore_sdram_bankmachine0_source_first;
assign litedramcore_sdram_bankmachine0_sink_sink_last = litedramcore_sdram_bankmachine0_source_last;
assign litedramcore_sdram_bankmachine0_sink_sink_payload_we = litedramcore_sdram_bankmachine0_source_payload_we;
assign litedramcore_sdram_bankmachine0_sink_sink_payload_addr = litedramcore_sdram_bankmachine0_source_payload_addr;
assign litedramcore_sdram_bankmachine0_source_source_ready = (litedramcore_sdram_bankmachine0_req_wdata_ready | litedramcore_sdram_bankmachine0_req_rdata_valid);
assign litedramcore_sdram_bankmachine0_req_lock = (litedramcore_sdram_bankmachine0_source_valid | litedramcore_sdram_bankmachine0_source_source_valid);
assign litedramcore_sdram_bankmachine0_row_hit = (litedramcore_sdram_bankmachine0_row == litedramcore_sdram_bankmachine0_source_source_payload_addr[21:7]);
assign litedramcore_sdram_bankmachine0_cmd_payload_ba = 1'd0;
always @(*) begin
    litedramcore_sdram_bankmachine0_cmd_payload_a <= 15'd0;
    if (litedramcore_sdram_bankmachine0_row_col_n_addr_sel) begin
        litedramcore_sdram_bankmachine0_cmd_payload_a <= litedramcore_sdram_bankmachine0_source_source_payload_addr[21:7];
    end else begin
        litedramcore_sdram_bankmachine0_cmd_payload_a <= ((litedramcore_sdram_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_sdram_bankmachine0_source_source_payload_addr[6:0], {3{1'd0}}});
    end
end
assign litedramcore_sdram_bankmachine0_twtpcon_valid = ((litedramcore_sdram_bankmachine0_cmd_valid & litedramcore_sdram_bankmachine0_cmd_ready) & litedramcore_sdram_bankmachine0_cmd_payload_is_write);
assign litedramcore_sdram_bankmachine0_trccon_valid = ((litedramcore_sdram_bankmachine0_cmd_valid & litedramcore_sdram_bankmachine0_cmd_ready) & litedramcore_sdram_bankmachine0_row_open);
assign litedramcore_sdram_bankmachine0_trascon_valid = ((litedramcore_sdram_bankmachine0_cmd_valid & litedramcore_sdram_bankmachine0_cmd_ready) & litedramcore_sdram_bankmachine0_row_open);
always @(*) begin
    litedramcore_sdram_bankmachine0_auto_precharge <= 1'd0;
    if ((litedramcore_sdram_bankmachine0_source_valid & litedramcore_sdram_bankmachine0_source_source_valid)) begin
        if ((litedramcore_sdram_bankmachine0_source_payload_addr[21:7] != litedramcore_sdram_bankmachine0_source_source_payload_addr[21:7])) begin
            litedramcore_sdram_bankmachine0_auto_precharge <= (litedramcore_sdram_bankmachine0_row_close == 1'd0);
        end
    end
end
assign litedramcore_sdram_bankmachine0_syncfifo0_din = {litedramcore_sdram_bankmachine0_fifo_in_last, litedramcore_sdram_bankmachine0_fifo_in_first, litedramcore_sdram_bankmachine0_fifo_in_payload_addr, litedramcore_sdram_bankmachine0_fifo_in_payload_we};
assign {litedramcore_sdram_bankmachine0_fifo_out_last, litedramcore_sdram_bankmachine0_fifo_out_first, litedramcore_sdram_bankmachine0_fifo_out_payload_addr, litedramcore_sdram_bankmachine0_fifo_out_payload_we} = litedramcore_sdram_bankmachine0_syncfifo0_dout;
assign {litedramcore_sdram_bankmachine0_fifo_out_last, litedramcore_sdram_bankmachine0_fifo_out_first, litedramcore_sdram_bankmachine0_fifo_out_payload_addr, litedramcore_sdram_bankmachine0_fifo_out_payload_we} = litedramcore_sdram_bankmachine0_syncfifo0_dout;
assign {litedramcore_sdram_bankmachine0_fifo_out_last, litedramcore_sdram_bankmachine0_fifo_out_first, litedramcore_sdram_bankmachine0_fifo_out_payload_addr, litedramcore_sdram_bankmachine0_fifo_out_payload_we} = litedramcore_sdram_bankmachine0_syncfifo0_dout;
assign {litedramcore_sdram_bankmachine0_fifo_out_last, litedramcore_sdram_bankmachine0_fifo_out_first, litedramcore_sdram_bankmachine0_fifo_out_payload_addr, litedramcore_sdram_bankmachine0_fifo_out_payload_we} = litedramcore_sdram_bankmachine0_syncfifo0_dout;
assign litedramcore_sdram_bankmachine0_sink_ready = litedramcore_sdram_bankmachine0_syncfifo0_writable;
assign litedramcore_sdram_bankmachine0_syncfifo0_we = litedramcore_sdram_bankmachine0_sink_valid;
assign litedramcore_sdram_bankmachine0_fifo_in_first = litedramcore_sdram_bankmachine0_sink_first;
assign litedramcore_sdram_bankmachine0_fifo_in_last = litedramcore_sdram_bankmachine0_sink_last;
assign litedramcore_sdram_bankmachine0_fifo_in_payload_we = litedramcore_sdram_bankmachine0_sink_payload_we;
assign litedramcore_sdram_bankmachine0_fifo_in_payload_addr = litedramcore_sdram_bankmachine0_sink_payload_addr;
assign litedramcore_sdram_bankmachine0_source_valid = litedramcore_sdram_bankmachine0_syncfifo0_readable;
assign litedramcore_sdram_bankmachine0_source_first = litedramcore_sdram_bankmachine0_fifo_out_first;
assign litedramcore_sdram_bankmachine0_source_last = litedramcore_sdram_bankmachine0_fifo_out_last;
assign litedramcore_sdram_bankmachine0_source_payload_we = litedramcore_sdram_bankmachine0_fifo_out_payload_we;
assign litedramcore_sdram_bankmachine0_source_payload_addr = litedramcore_sdram_bankmachine0_fifo_out_payload_addr;
assign litedramcore_sdram_bankmachine0_syncfifo0_re = litedramcore_sdram_bankmachine0_source_ready;
always @(*) begin
    litedramcore_sdram_bankmachine0_wrport_adr <= 4'd0;
    if (litedramcore_sdram_bankmachine0_replace) begin
        litedramcore_sdram_bankmachine0_wrport_adr <= (litedramcore_sdram_bankmachine0_produce - 1'd1);
    end else begin
        litedramcore_sdram_bankmachine0_wrport_adr <= litedramcore_sdram_bankmachine0_produce;
    end
end
assign litedramcore_sdram_bankmachine0_wrport_dat_w = litedramcore_sdram_bankmachine0_syncfifo0_din;
assign litedramcore_sdram_bankmachine0_wrport_we = (litedramcore_sdram_bankmachine0_syncfifo0_we & (litedramcore_sdram_bankmachine0_syncfifo0_writable | litedramcore_sdram_bankmachine0_replace));
assign litedramcore_sdram_bankmachine0_do_read = (litedramcore_sdram_bankmachine0_syncfifo0_readable & litedramcore_sdram_bankmachine0_syncfifo0_re);
assign litedramcore_sdram_bankmachine0_rdport_adr = litedramcore_sdram_bankmachine0_consume;
assign litedramcore_sdram_bankmachine0_syncfifo0_dout = litedramcore_sdram_bankmachine0_rdport_dat_r;
assign litedramcore_sdram_bankmachine0_syncfifo0_writable = (litedramcore_sdram_bankmachine0_level != 5'd16);
assign litedramcore_sdram_bankmachine0_syncfifo0_readable = (litedramcore_sdram_bankmachine0_level != 1'd0);
assign litedramcore_sdram_bankmachine0_pipe_valid_sink_ready = ((~litedramcore_sdram_bankmachine0_pipe_valid_source_valid) | litedramcore_sdram_bankmachine0_pipe_valid_source_ready);
assign litedramcore_sdram_bankmachine0_pipe_valid_sink_valid = litedramcore_sdram_bankmachine0_sink_sink_valid;
assign litedramcore_sdram_bankmachine0_sink_sink_ready = litedramcore_sdram_bankmachine0_pipe_valid_sink_ready;
assign litedramcore_sdram_bankmachine0_pipe_valid_sink_first = litedramcore_sdram_bankmachine0_sink_sink_first;
assign litedramcore_sdram_bankmachine0_pipe_valid_sink_last = litedramcore_sdram_bankmachine0_sink_sink_last;
assign litedramcore_sdram_bankmachine0_pipe_valid_sink_payload_we = litedramcore_sdram_bankmachine0_sink_sink_payload_we;
assign litedramcore_sdram_bankmachine0_pipe_valid_sink_payload_addr = litedramcore_sdram_bankmachine0_sink_sink_payload_addr;
assign litedramcore_sdram_bankmachine0_source_source_valid = litedramcore_sdram_bankmachine0_pipe_valid_source_valid;
assign litedramcore_sdram_bankmachine0_pipe_valid_source_ready = litedramcore_sdram_bankmachine0_source_source_ready;
assign litedramcore_sdram_bankmachine0_source_source_first = litedramcore_sdram_bankmachine0_pipe_valid_source_first;
assign litedramcore_sdram_bankmachine0_source_source_last = litedramcore_sdram_bankmachine0_pipe_valid_source_last;
assign litedramcore_sdram_bankmachine0_source_source_payload_we = litedramcore_sdram_bankmachine0_pipe_valid_source_payload_we;
assign litedramcore_sdram_bankmachine0_source_source_payload_addr = litedramcore_sdram_bankmachine0_pipe_valid_source_payload_addr;
always @(*) begin
    litedramcore_bankmachine0_next_state <= 4'd0;
    litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state;
    case (litedramcore_bankmachine0_state)
        1'd1: begin
            if ((litedramcore_sdram_bankmachine0_twtpcon_ready & litedramcore_sdram_bankmachine0_trascon_ready)) begin
                if (litedramcore_sdram_bankmachine0_cmd_ready) begin
                    litedramcore_bankmachine0_next_state <= 3'd5;
                end
            end
        end
        2'd2: begin
            if ((litedramcore_sdram_bankmachine0_twtpcon_ready & litedramcore_sdram_bankmachine0_trascon_ready)) begin
                litedramcore_bankmachine0_next_state <= 3'd5;
            end
        end
        2'd3: begin
            if (litedramcore_sdram_bankmachine0_trccon_ready) begin
                if (litedramcore_sdram_bankmachine0_cmd_ready) begin
                    litedramcore_bankmachine0_next_state <= 4'd8;
                end
            end
        end
        3'd4: begin
            if ((~litedramcore_sdram_bankmachine0_refresh_req)) begin
                litedramcore_bankmachine0_next_state <= 1'd0;
            end
        end
        3'd5: begin
            litedramcore_bankmachine0_next_state <= 3'd6;
        end
        3'd6: begin
            litedramcore_bankmachine0_next_state <= 3'd7;
        end
        3'd7: begin
            litedramcore_bankmachine0_next_state <= 2'd3;
        end
        4'd8: begin
            litedramcore_bankmachine0_next_state <= 4'd9;
        end
        4'd9: begin
            litedramcore_bankmachine0_next_state <= 4'd10;
        end
        4'd10: begin
            litedramcore_bankmachine0_next_state <= 1'd0;
        end
        default: begin
            if (litedramcore_sdram_bankmachine0_refresh_req) begin
                litedramcore_bankmachine0_next_state <= 3'd4;
            end else begin
                if (litedramcore_sdram_bankmachine0_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine0_row_opened) begin
                        if (litedramcore_sdram_bankmachine0_row_hit) begin
                            if ((litedramcore_sdram_bankmachine0_cmd_ready & litedramcore_sdram_bankmachine0_auto_precharge)) begin
                                litedramcore_bankmachine0_next_state <= 2'd2;
                            end
                        end else begin
                            litedramcore_bankmachine0_next_state <= 1'd1;
                        end
                    end else begin
                        litedramcore_bankmachine0_next_state <= 2'd3;
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine0_row_col_n_addr_sel <= 1'd0;
    case (litedramcore_bankmachine0_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
            if (litedramcore_sdram_bankmachine0_trccon_ready) begin
                litedramcore_sdram_bankmachine0_row_col_n_addr_sel <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine0_cmd_payload_cas <= 1'd0;
    case (litedramcore_bankmachine0_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine0_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine0_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine0_row_opened) begin
                        if (litedramcore_sdram_bankmachine0_row_hit) begin
                            litedramcore_sdram_bankmachine0_cmd_payload_cas <= 1'd1;
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine0_cmd_payload_ras <= 1'd0;
    case (litedramcore_bankmachine0_state)
        1'd1: begin
            if ((litedramcore_sdram_bankmachine0_twtpcon_ready & litedramcore_sdram_bankmachine0_trascon_ready)) begin
                litedramcore_sdram_bankmachine0_cmd_payload_ras <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
            if (litedramcore_sdram_bankmachine0_trccon_ready) begin
                litedramcore_sdram_bankmachine0_cmd_payload_ras <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine0_cmd_payload_we <= 1'd0;
    case (litedramcore_bankmachine0_state)
        1'd1: begin
            if ((litedramcore_sdram_bankmachine0_twtpcon_ready & litedramcore_sdram_bankmachine0_trascon_ready)) begin
                litedramcore_sdram_bankmachine0_cmd_payload_we <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine0_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine0_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine0_row_opened) begin
                        if (litedramcore_sdram_bankmachine0_row_hit) begin
                            if (litedramcore_sdram_bankmachine0_source_source_payload_we) begin
                                litedramcore_sdram_bankmachine0_cmd_payload_we <= 1'd1;
                            end else begin
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd0;
    case (litedramcore_bankmachine0_state)
        1'd1: begin
            if ((litedramcore_sdram_bankmachine0_twtpcon_ready & litedramcore_sdram_bankmachine0_trascon_ready)) begin
                litedramcore_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
            if (litedramcore_sdram_bankmachine0_trccon_ready) begin
                litedramcore_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1;
            end
        end
        3'd4: begin
            litedramcore_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1;
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine0_cmd_payload_is_read <= 1'd0;
    case (litedramcore_bankmachine0_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine0_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine0_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine0_row_opened) begin
                        if (litedramcore_sdram_bankmachine0_row_hit) begin
                            if (litedramcore_sdram_bankmachine0_source_source_payload_we) begin
                            end else begin
                                litedramcore_sdram_bankmachine0_cmd_payload_is_read <= 1'd1;
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine0_cmd_payload_is_write <= 1'd0;
    case (litedramcore_bankmachine0_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine0_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine0_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine0_row_opened) begin
                        if (litedramcore_sdram_bankmachine0_row_hit) begin
                            if (litedramcore_sdram_bankmachine0_source_source_payload_we) begin
                                litedramcore_sdram_bankmachine0_cmd_payload_is_write <= 1'd1;
                            end else begin
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine0_req_wdata_ready <= 1'd0;
    case (litedramcore_bankmachine0_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine0_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine0_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine0_row_opened) begin
                        if (litedramcore_sdram_bankmachine0_row_hit) begin
                            if (litedramcore_sdram_bankmachine0_source_source_payload_we) begin
                                litedramcore_sdram_bankmachine0_req_wdata_ready <= litedramcore_sdram_bankmachine0_cmd_ready;
                            end else begin
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine0_req_rdata_valid <= 1'd0;
    case (litedramcore_bankmachine0_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine0_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine0_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine0_row_opened) begin
                        if (litedramcore_sdram_bankmachine0_row_hit) begin
                            if (litedramcore_sdram_bankmachine0_source_source_payload_we) begin
                            end else begin
                                litedramcore_sdram_bankmachine0_req_rdata_valid <= litedramcore_sdram_bankmachine0_cmd_ready;
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine0_refresh_gnt <= 1'd0;
    case (litedramcore_bankmachine0_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
            if (litedramcore_sdram_bankmachine0_twtpcon_ready) begin
                litedramcore_sdram_bankmachine0_refresh_gnt <= 1'd1;
            end
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine0_row_open <= 1'd0;
    case (litedramcore_bankmachine0_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
            if (litedramcore_sdram_bankmachine0_trccon_ready) begin
                litedramcore_sdram_bankmachine0_row_open <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine0_cmd_valid <= 1'd0;
    case (litedramcore_bankmachine0_state)
        1'd1: begin
            if ((litedramcore_sdram_bankmachine0_twtpcon_ready & litedramcore_sdram_bankmachine0_trascon_ready)) begin
                litedramcore_sdram_bankmachine0_cmd_valid <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
            if (litedramcore_sdram_bankmachine0_trccon_ready) begin
                litedramcore_sdram_bankmachine0_cmd_valid <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine0_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine0_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine0_row_opened) begin
                        if (litedramcore_sdram_bankmachine0_row_hit) begin
                            litedramcore_sdram_bankmachine0_cmd_valid <= 1'd1;
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine0_row_close <= 1'd0;
    case (litedramcore_bankmachine0_state)
        1'd1: begin
            litedramcore_sdram_bankmachine0_row_close <= 1'd1;
        end
        2'd2: begin
            litedramcore_sdram_bankmachine0_row_close <= 1'd1;
        end
        2'd3: begin
        end
        3'd4: begin
            litedramcore_sdram_bankmachine0_row_close <= 1'd1;
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
        end
    endcase
end
assign litedramcore_sdram_bankmachine1_sink_valid = litedramcore_sdram_bankmachine1_req_valid;
assign litedramcore_sdram_bankmachine1_req_ready = litedramcore_sdram_bankmachine1_sink_ready;
assign litedramcore_sdram_bankmachine1_sink_payload_we = litedramcore_sdram_bankmachine1_req_we;
assign litedramcore_sdram_bankmachine1_sink_payload_addr = litedramcore_sdram_bankmachine1_req_addr;
assign litedramcore_sdram_bankmachine1_sink_sink_valid = litedramcore_sdram_bankmachine1_source_valid;
assign litedramcore_sdram_bankmachine1_source_ready = litedramcore_sdram_bankmachine1_sink_sink_ready;
assign litedramcore_sdram_bankmachine1_sink_sink_first = litedramcore_sdram_bankmachine1_source_first;
assign litedramcore_sdram_bankmachine1_sink_sink_last = litedramcore_sdram_bankmachine1_source_last;
assign litedramcore_sdram_bankmachine1_sink_sink_payload_we = litedramcore_sdram_bankmachine1_source_payload_we;
assign litedramcore_sdram_bankmachine1_sink_sink_payload_addr = litedramcore_sdram_bankmachine1_source_payload_addr;
assign litedramcore_sdram_bankmachine1_source_source_ready = (litedramcore_sdram_bankmachine1_req_wdata_ready | litedramcore_sdram_bankmachine1_req_rdata_valid);
assign litedramcore_sdram_bankmachine1_req_lock = (litedramcore_sdram_bankmachine1_source_valid | litedramcore_sdram_bankmachine1_source_source_valid);
assign litedramcore_sdram_bankmachine1_row_hit = (litedramcore_sdram_bankmachine1_row == litedramcore_sdram_bankmachine1_source_source_payload_addr[21:7]);
assign litedramcore_sdram_bankmachine1_cmd_payload_ba = 1'd1;
always @(*) begin
    litedramcore_sdram_bankmachine1_cmd_payload_a <= 15'd0;
    if (litedramcore_sdram_bankmachine1_row_col_n_addr_sel) begin
        litedramcore_sdram_bankmachine1_cmd_payload_a <= litedramcore_sdram_bankmachine1_source_source_payload_addr[21:7];
    end else begin
        litedramcore_sdram_bankmachine1_cmd_payload_a <= ((litedramcore_sdram_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_sdram_bankmachine1_source_source_payload_addr[6:0], {3{1'd0}}});
    end
end
assign litedramcore_sdram_bankmachine1_twtpcon_valid = ((litedramcore_sdram_bankmachine1_cmd_valid & litedramcore_sdram_bankmachine1_cmd_ready) & litedramcore_sdram_bankmachine1_cmd_payload_is_write);
assign litedramcore_sdram_bankmachine1_trccon_valid = ((litedramcore_sdram_bankmachine1_cmd_valid & litedramcore_sdram_bankmachine1_cmd_ready) & litedramcore_sdram_bankmachine1_row_open);
assign litedramcore_sdram_bankmachine1_trascon_valid = ((litedramcore_sdram_bankmachine1_cmd_valid & litedramcore_sdram_bankmachine1_cmd_ready) & litedramcore_sdram_bankmachine1_row_open);
always @(*) begin
    litedramcore_sdram_bankmachine1_auto_precharge <= 1'd0;
    if ((litedramcore_sdram_bankmachine1_source_valid & litedramcore_sdram_bankmachine1_source_source_valid)) begin
        if ((litedramcore_sdram_bankmachine1_source_payload_addr[21:7] != litedramcore_sdram_bankmachine1_source_source_payload_addr[21:7])) begin
            litedramcore_sdram_bankmachine1_auto_precharge <= (litedramcore_sdram_bankmachine1_row_close == 1'd0);
        end
    end
end
assign litedramcore_sdram_bankmachine1_syncfifo1_din = {litedramcore_sdram_bankmachine1_fifo_in_last, litedramcore_sdram_bankmachine1_fifo_in_first, litedramcore_sdram_bankmachine1_fifo_in_payload_addr, litedramcore_sdram_bankmachine1_fifo_in_payload_we};
assign {litedramcore_sdram_bankmachine1_fifo_out_last, litedramcore_sdram_bankmachine1_fifo_out_first, litedramcore_sdram_bankmachine1_fifo_out_payload_addr, litedramcore_sdram_bankmachine1_fifo_out_payload_we} = litedramcore_sdram_bankmachine1_syncfifo1_dout;
assign {litedramcore_sdram_bankmachine1_fifo_out_last, litedramcore_sdram_bankmachine1_fifo_out_first, litedramcore_sdram_bankmachine1_fifo_out_payload_addr, litedramcore_sdram_bankmachine1_fifo_out_payload_we} = litedramcore_sdram_bankmachine1_syncfifo1_dout;
assign {litedramcore_sdram_bankmachine1_fifo_out_last, litedramcore_sdram_bankmachine1_fifo_out_first, litedramcore_sdram_bankmachine1_fifo_out_payload_addr, litedramcore_sdram_bankmachine1_fifo_out_payload_we} = litedramcore_sdram_bankmachine1_syncfifo1_dout;
assign {litedramcore_sdram_bankmachine1_fifo_out_last, litedramcore_sdram_bankmachine1_fifo_out_first, litedramcore_sdram_bankmachine1_fifo_out_payload_addr, litedramcore_sdram_bankmachine1_fifo_out_payload_we} = litedramcore_sdram_bankmachine1_syncfifo1_dout;
assign litedramcore_sdram_bankmachine1_sink_ready = litedramcore_sdram_bankmachine1_syncfifo1_writable;
assign litedramcore_sdram_bankmachine1_syncfifo1_we = litedramcore_sdram_bankmachine1_sink_valid;
assign litedramcore_sdram_bankmachine1_fifo_in_first = litedramcore_sdram_bankmachine1_sink_first;
assign litedramcore_sdram_bankmachine1_fifo_in_last = litedramcore_sdram_bankmachine1_sink_last;
assign litedramcore_sdram_bankmachine1_fifo_in_payload_we = litedramcore_sdram_bankmachine1_sink_payload_we;
assign litedramcore_sdram_bankmachine1_fifo_in_payload_addr = litedramcore_sdram_bankmachine1_sink_payload_addr;
assign litedramcore_sdram_bankmachine1_source_valid = litedramcore_sdram_bankmachine1_syncfifo1_readable;
assign litedramcore_sdram_bankmachine1_source_first = litedramcore_sdram_bankmachine1_fifo_out_first;
assign litedramcore_sdram_bankmachine1_source_last = litedramcore_sdram_bankmachine1_fifo_out_last;
assign litedramcore_sdram_bankmachine1_source_payload_we = litedramcore_sdram_bankmachine1_fifo_out_payload_we;
assign litedramcore_sdram_bankmachine1_source_payload_addr = litedramcore_sdram_bankmachine1_fifo_out_payload_addr;
assign litedramcore_sdram_bankmachine1_syncfifo1_re = litedramcore_sdram_bankmachine1_source_ready;
always @(*) begin
    litedramcore_sdram_bankmachine1_wrport_adr <= 4'd0;
    if (litedramcore_sdram_bankmachine1_replace) begin
        litedramcore_sdram_bankmachine1_wrport_adr <= (litedramcore_sdram_bankmachine1_produce - 1'd1);
    end else begin
        litedramcore_sdram_bankmachine1_wrport_adr <= litedramcore_sdram_bankmachine1_produce;
    end
end
assign litedramcore_sdram_bankmachine1_wrport_dat_w = litedramcore_sdram_bankmachine1_syncfifo1_din;
assign litedramcore_sdram_bankmachine1_wrport_we = (litedramcore_sdram_bankmachine1_syncfifo1_we & (litedramcore_sdram_bankmachine1_syncfifo1_writable | litedramcore_sdram_bankmachine1_replace));
assign litedramcore_sdram_bankmachine1_do_read = (litedramcore_sdram_bankmachine1_syncfifo1_readable & litedramcore_sdram_bankmachine1_syncfifo1_re);
assign litedramcore_sdram_bankmachine1_rdport_adr = litedramcore_sdram_bankmachine1_consume;
assign litedramcore_sdram_bankmachine1_syncfifo1_dout = litedramcore_sdram_bankmachine1_rdport_dat_r;
assign litedramcore_sdram_bankmachine1_syncfifo1_writable = (litedramcore_sdram_bankmachine1_level != 5'd16);
assign litedramcore_sdram_bankmachine1_syncfifo1_readable = (litedramcore_sdram_bankmachine1_level != 1'd0);
assign litedramcore_sdram_bankmachine1_pipe_valid_sink_ready = ((~litedramcore_sdram_bankmachine1_pipe_valid_source_valid) | litedramcore_sdram_bankmachine1_pipe_valid_source_ready);
assign litedramcore_sdram_bankmachine1_pipe_valid_sink_valid = litedramcore_sdram_bankmachine1_sink_sink_valid;
assign litedramcore_sdram_bankmachine1_sink_sink_ready = litedramcore_sdram_bankmachine1_pipe_valid_sink_ready;
assign litedramcore_sdram_bankmachine1_pipe_valid_sink_first = litedramcore_sdram_bankmachine1_sink_sink_first;
assign litedramcore_sdram_bankmachine1_pipe_valid_sink_last = litedramcore_sdram_bankmachine1_sink_sink_last;
assign litedramcore_sdram_bankmachine1_pipe_valid_sink_payload_we = litedramcore_sdram_bankmachine1_sink_sink_payload_we;
assign litedramcore_sdram_bankmachine1_pipe_valid_sink_payload_addr = litedramcore_sdram_bankmachine1_sink_sink_payload_addr;
assign litedramcore_sdram_bankmachine1_source_source_valid = litedramcore_sdram_bankmachine1_pipe_valid_source_valid;
assign litedramcore_sdram_bankmachine1_pipe_valid_source_ready = litedramcore_sdram_bankmachine1_source_source_ready;
assign litedramcore_sdram_bankmachine1_source_source_first = litedramcore_sdram_bankmachine1_pipe_valid_source_first;
assign litedramcore_sdram_bankmachine1_source_source_last = litedramcore_sdram_bankmachine1_pipe_valid_source_last;
assign litedramcore_sdram_bankmachine1_source_source_payload_we = litedramcore_sdram_bankmachine1_pipe_valid_source_payload_we;
assign litedramcore_sdram_bankmachine1_source_source_payload_addr = litedramcore_sdram_bankmachine1_pipe_valid_source_payload_addr;
always @(*) begin
    litedramcore_bankmachine1_next_state <= 4'd0;
    litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state;
    case (litedramcore_bankmachine1_state)
        1'd1: begin
            if ((litedramcore_sdram_bankmachine1_twtpcon_ready & litedramcore_sdram_bankmachine1_trascon_ready)) begin
                if (litedramcore_sdram_bankmachine1_cmd_ready) begin
                    litedramcore_bankmachine1_next_state <= 3'd5;
                end
            end
        end
        2'd2: begin
            if ((litedramcore_sdram_bankmachine1_twtpcon_ready & litedramcore_sdram_bankmachine1_trascon_ready)) begin
                litedramcore_bankmachine1_next_state <= 3'd5;
            end
        end
        2'd3: begin
            if (litedramcore_sdram_bankmachine1_trccon_ready) begin
                if (litedramcore_sdram_bankmachine1_cmd_ready) begin
                    litedramcore_bankmachine1_next_state <= 4'd8;
                end
            end
        end
        3'd4: begin
            if ((~litedramcore_sdram_bankmachine1_refresh_req)) begin
                litedramcore_bankmachine1_next_state <= 1'd0;
            end
        end
        3'd5: begin
            litedramcore_bankmachine1_next_state <= 3'd6;
        end
        3'd6: begin
            litedramcore_bankmachine1_next_state <= 3'd7;
        end
        3'd7: begin
            litedramcore_bankmachine1_next_state <= 2'd3;
        end
        4'd8: begin
            litedramcore_bankmachine1_next_state <= 4'd9;
        end
        4'd9: begin
            litedramcore_bankmachine1_next_state <= 4'd10;
        end
        4'd10: begin
            litedramcore_bankmachine1_next_state <= 1'd0;
        end
        default: begin
            if (litedramcore_sdram_bankmachine1_refresh_req) begin
                litedramcore_bankmachine1_next_state <= 3'd4;
            end else begin
                if (litedramcore_sdram_bankmachine1_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine1_row_opened) begin
                        if (litedramcore_sdram_bankmachine1_row_hit) begin
                            if ((litedramcore_sdram_bankmachine1_cmd_ready & litedramcore_sdram_bankmachine1_auto_precharge)) begin
                                litedramcore_bankmachine1_next_state <= 2'd2;
                            end
                        end else begin
                            litedramcore_bankmachine1_next_state <= 1'd1;
                        end
                    end else begin
                        litedramcore_bankmachine1_next_state <= 2'd3;
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine1_cmd_payload_ras <= 1'd0;
    case (litedramcore_bankmachine1_state)
        1'd1: begin
            if ((litedramcore_sdram_bankmachine1_twtpcon_ready & litedramcore_sdram_bankmachine1_trascon_ready)) begin
                litedramcore_sdram_bankmachine1_cmd_payload_ras <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
            if (litedramcore_sdram_bankmachine1_trccon_ready) begin
                litedramcore_sdram_bankmachine1_cmd_payload_ras <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine1_cmd_payload_we <= 1'd0;
    case (litedramcore_bankmachine1_state)
        1'd1: begin
            if ((litedramcore_sdram_bankmachine1_twtpcon_ready & litedramcore_sdram_bankmachine1_trascon_ready)) begin
                litedramcore_sdram_bankmachine1_cmd_payload_we <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine1_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine1_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine1_row_opened) begin
                        if (litedramcore_sdram_bankmachine1_row_hit) begin
                            if (litedramcore_sdram_bankmachine1_source_source_payload_we) begin
                                litedramcore_sdram_bankmachine1_cmd_payload_we <= 1'd1;
                            end else begin
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd0;
    case (litedramcore_bankmachine1_state)
        1'd1: begin
            if ((litedramcore_sdram_bankmachine1_twtpcon_ready & litedramcore_sdram_bankmachine1_trascon_ready)) begin
                litedramcore_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
            if (litedramcore_sdram_bankmachine1_trccon_ready) begin
                litedramcore_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1;
            end
        end
        3'd4: begin
            litedramcore_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1;
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine1_cmd_payload_is_read <= 1'd0;
    case (litedramcore_bankmachine1_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine1_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine1_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine1_row_opened) begin
                        if (litedramcore_sdram_bankmachine1_row_hit) begin
                            if (litedramcore_sdram_bankmachine1_source_source_payload_we) begin
                            end else begin
                                litedramcore_sdram_bankmachine1_cmd_payload_is_read <= 1'd1;
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine1_cmd_payload_is_write <= 1'd0;
    case (litedramcore_bankmachine1_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine1_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine1_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine1_row_opened) begin
                        if (litedramcore_sdram_bankmachine1_row_hit) begin
                            if (litedramcore_sdram_bankmachine1_source_source_payload_we) begin
                                litedramcore_sdram_bankmachine1_cmd_payload_is_write <= 1'd1;
                            end else begin
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine1_req_wdata_ready <= 1'd0;
    case (litedramcore_bankmachine1_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine1_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine1_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine1_row_opened) begin
                        if (litedramcore_sdram_bankmachine1_row_hit) begin
                            if (litedramcore_sdram_bankmachine1_source_source_payload_we) begin
                                litedramcore_sdram_bankmachine1_req_wdata_ready <= litedramcore_sdram_bankmachine1_cmd_ready;
                            end else begin
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine1_req_rdata_valid <= 1'd0;
    case (litedramcore_bankmachine1_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine1_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine1_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine1_row_opened) begin
                        if (litedramcore_sdram_bankmachine1_row_hit) begin
                            if (litedramcore_sdram_bankmachine1_source_source_payload_we) begin
                            end else begin
                                litedramcore_sdram_bankmachine1_req_rdata_valid <= litedramcore_sdram_bankmachine1_cmd_ready;
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine1_refresh_gnt <= 1'd0;
    case (litedramcore_bankmachine1_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
            if (litedramcore_sdram_bankmachine1_twtpcon_ready) begin
                litedramcore_sdram_bankmachine1_refresh_gnt <= 1'd1;
            end
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine1_cmd_valid <= 1'd0;
    case (litedramcore_bankmachine1_state)
        1'd1: begin
            if ((litedramcore_sdram_bankmachine1_twtpcon_ready & litedramcore_sdram_bankmachine1_trascon_ready)) begin
                litedramcore_sdram_bankmachine1_cmd_valid <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
            if (litedramcore_sdram_bankmachine1_trccon_ready) begin
                litedramcore_sdram_bankmachine1_cmd_valid <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine1_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine1_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine1_row_opened) begin
                        if (litedramcore_sdram_bankmachine1_row_hit) begin
                            litedramcore_sdram_bankmachine1_cmd_valid <= 1'd1;
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine1_row_close <= 1'd0;
    case (litedramcore_bankmachine1_state)
        1'd1: begin
            litedramcore_sdram_bankmachine1_row_close <= 1'd1;
        end
        2'd2: begin
            litedramcore_sdram_bankmachine1_row_close <= 1'd1;
        end
        2'd3: begin
        end
        3'd4: begin
            litedramcore_sdram_bankmachine1_row_close <= 1'd1;
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine1_row_open <= 1'd0;
    case (litedramcore_bankmachine1_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
            if (litedramcore_sdram_bankmachine1_trccon_ready) begin
                litedramcore_sdram_bankmachine1_row_open <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine1_row_col_n_addr_sel <= 1'd0;
    case (litedramcore_bankmachine1_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
            if (litedramcore_sdram_bankmachine1_trccon_ready) begin
                litedramcore_sdram_bankmachine1_row_col_n_addr_sel <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine1_cmd_payload_cas <= 1'd0;
    case (litedramcore_bankmachine1_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine1_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine1_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine1_row_opened) begin
                        if (litedramcore_sdram_bankmachine1_row_hit) begin
                            litedramcore_sdram_bankmachine1_cmd_payload_cas <= 1'd1;
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
assign litedramcore_sdram_bankmachine2_sink_valid = litedramcore_sdram_bankmachine2_req_valid;
assign litedramcore_sdram_bankmachine2_req_ready = litedramcore_sdram_bankmachine2_sink_ready;
assign litedramcore_sdram_bankmachine2_sink_payload_we = litedramcore_sdram_bankmachine2_req_we;
assign litedramcore_sdram_bankmachine2_sink_payload_addr = litedramcore_sdram_bankmachine2_req_addr;
assign litedramcore_sdram_bankmachine2_sink_sink_valid = litedramcore_sdram_bankmachine2_source_valid;
assign litedramcore_sdram_bankmachine2_source_ready = litedramcore_sdram_bankmachine2_sink_sink_ready;
assign litedramcore_sdram_bankmachine2_sink_sink_first = litedramcore_sdram_bankmachine2_source_first;
assign litedramcore_sdram_bankmachine2_sink_sink_last = litedramcore_sdram_bankmachine2_source_last;
assign litedramcore_sdram_bankmachine2_sink_sink_payload_we = litedramcore_sdram_bankmachine2_source_payload_we;
assign litedramcore_sdram_bankmachine2_sink_sink_payload_addr = litedramcore_sdram_bankmachine2_source_payload_addr;
assign litedramcore_sdram_bankmachine2_source_source_ready = (litedramcore_sdram_bankmachine2_req_wdata_ready | litedramcore_sdram_bankmachine2_req_rdata_valid);
assign litedramcore_sdram_bankmachine2_req_lock = (litedramcore_sdram_bankmachine2_source_valid | litedramcore_sdram_bankmachine2_source_source_valid);
assign litedramcore_sdram_bankmachine2_row_hit = (litedramcore_sdram_bankmachine2_row == litedramcore_sdram_bankmachine2_source_source_payload_addr[21:7]);
assign litedramcore_sdram_bankmachine2_cmd_payload_ba = 2'd2;
always @(*) begin
    litedramcore_sdram_bankmachine2_cmd_payload_a <= 15'd0;
    if (litedramcore_sdram_bankmachine2_row_col_n_addr_sel) begin
        litedramcore_sdram_bankmachine2_cmd_payload_a <= litedramcore_sdram_bankmachine2_source_source_payload_addr[21:7];
    end else begin
        litedramcore_sdram_bankmachine2_cmd_payload_a <= ((litedramcore_sdram_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_sdram_bankmachine2_source_source_payload_addr[6:0], {3{1'd0}}});
    end
end
assign litedramcore_sdram_bankmachine2_twtpcon_valid = ((litedramcore_sdram_bankmachine2_cmd_valid & litedramcore_sdram_bankmachine2_cmd_ready) & litedramcore_sdram_bankmachine2_cmd_payload_is_write);
assign litedramcore_sdram_bankmachine2_trccon_valid = ((litedramcore_sdram_bankmachine2_cmd_valid & litedramcore_sdram_bankmachine2_cmd_ready) & litedramcore_sdram_bankmachine2_row_open);
assign litedramcore_sdram_bankmachine2_trascon_valid = ((litedramcore_sdram_bankmachine2_cmd_valid & litedramcore_sdram_bankmachine2_cmd_ready) & litedramcore_sdram_bankmachine2_row_open);
always @(*) begin
    litedramcore_sdram_bankmachine2_auto_precharge <= 1'd0;
    if ((litedramcore_sdram_bankmachine2_source_valid & litedramcore_sdram_bankmachine2_source_source_valid)) begin
        if ((litedramcore_sdram_bankmachine2_source_payload_addr[21:7] != litedramcore_sdram_bankmachine2_source_source_payload_addr[21:7])) begin
            litedramcore_sdram_bankmachine2_auto_precharge <= (litedramcore_sdram_bankmachine2_row_close == 1'd0);
        end
    end
end
assign litedramcore_sdram_bankmachine2_syncfifo2_din = {litedramcore_sdram_bankmachine2_fifo_in_last, litedramcore_sdram_bankmachine2_fifo_in_first, litedramcore_sdram_bankmachine2_fifo_in_payload_addr, litedramcore_sdram_bankmachine2_fifo_in_payload_we};
assign {litedramcore_sdram_bankmachine2_fifo_out_last, litedramcore_sdram_bankmachine2_fifo_out_first, litedramcore_sdram_bankmachine2_fifo_out_payload_addr, litedramcore_sdram_bankmachine2_fifo_out_payload_we} = litedramcore_sdram_bankmachine2_syncfifo2_dout;
assign {litedramcore_sdram_bankmachine2_fifo_out_last, litedramcore_sdram_bankmachine2_fifo_out_first, litedramcore_sdram_bankmachine2_fifo_out_payload_addr, litedramcore_sdram_bankmachine2_fifo_out_payload_we} = litedramcore_sdram_bankmachine2_syncfifo2_dout;
assign {litedramcore_sdram_bankmachine2_fifo_out_last, litedramcore_sdram_bankmachine2_fifo_out_first, litedramcore_sdram_bankmachine2_fifo_out_payload_addr, litedramcore_sdram_bankmachine2_fifo_out_payload_we} = litedramcore_sdram_bankmachine2_syncfifo2_dout;
assign {litedramcore_sdram_bankmachine2_fifo_out_last, litedramcore_sdram_bankmachine2_fifo_out_first, litedramcore_sdram_bankmachine2_fifo_out_payload_addr, litedramcore_sdram_bankmachine2_fifo_out_payload_we} = litedramcore_sdram_bankmachine2_syncfifo2_dout;
assign litedramcore_sdram_bankmachine2_sink_ready = litedramcore_sdram_bankmachine2_syncfifo2_writable;
assign litedramcore_sdram_bankmachine2_syncfifo2_we = litedramcore_sdram_bankmachine2_sink_valid;
assign litedramcore_sdram_bankmachine2_fifo_in_first = litedramcore_sdram_bankmachine2_sink_first;
assign litedramcore_sdram_bankmachine2_fifo_in_last = litedramcore_sdram_bankmachine2_sink_last;
assign litedramcore_sdram_bankmachine2_fifo_in_payload_we = litedramcore_sdram_bankmachine2_sink_payload_we;
assign litedramcore_sdram_bankmachine2_fifo_in_payload_addr = litedramcore_sdram_bankmachine2_sink_payload_addr;
assign litedramcore_sdram_bankmachine2_source_valid = litedramcore_sdram_bankmachine2_syncfifo2_readable;
assign litedramcore_sdram_bankmachine2_source_first = litedramcore_sdram_bankmachine2_fifo_out_first;
assign litedramcore_sdram_bankmachine2_source_last = litedramcore_sdram_bankmachine2_fifo_out_last;
assign litedramcore_sdram_bankmachine2_source_payload_we = litedramcore_sdram_bankmachine2_fifo_out_payload_we;
assign litedramcore_sdram_bankmachine2_source_payload_addr = litedramcore_sdram_bankmachine2_fifo_out_payload_addr;
assign litedramcore_sdram_bankmachine2_syncfifo2_re = litedramcore_sdram_bankmachine2_source_ready;
always @(*) begin
    litedramcore_sdram_bankmachine2_wrport_adr <= 4'd0;
    if (litedramcore_sdram_bankmachine2_replace) begin
        litedramcore_sdram_bankmachine2_wrport_adr <= (litedramcore_sdram_bankmachine2_produce - 1'd1);
    end else begin
        litedramcore_sdram_bankmachine2_wrport_adr <= litedramcore_sdram_bankmachine2_produce;
    end
end
assign litedramcore_sdram_bankmachine2_wrport_dat_w = litedramcore_sdram_bankmachine2_syncfifo2_din;
assign litedramcore_sdram_bankmachine2_wrport_we = (litedramcore_sdram_bankmachine2_syncfifo2_we & (litedramcore_sdram_bankmachine2_syncfifo2_writable | litedramcore_sdram_bankmachine2_replace));
assign litedramcore_sdram_bankmachine2_do_read = (litedramcore_sdram_bankmachine2_syncfifo2_readable & litedramcore_sdram_bankmachine2_syncfifo2_re);
assign litedramcore_sdram_bankmachine2_rdport_adr = litedramcore_sdram_bankmachine2_consume;
assign litedramcore_sdram_bankmachine2_syncfifo2_dout = litedramcore_sdram_bankmachine2_rdport_dat_r;
assign litedramcore_sdram_bankmachine2_syncfifo2_writable = (litedramcore_sdram_bankmachine2_level != 5'd16);
assign litedramcore_sdram_bankmachine2_syncfifo2_readable = (litedramcore_sdram_bankmachine2_level != 1'd0);
assign litedramcore_sdram_bankmachine2_pipe_valid_sink_ready = ((~litedramcore_sdram_bankmachine2_pipe_valid_source_valid) | litedramcore_sdram_bankmachine2_pipe_valid_source_ready);
assign litedramcore_sdram_bankmachine2_pipe_valid_sink_valid = litedramcore_sdram_bankmachine2_sink_sink_valid;
assign litedramcore_sdram_bankmachine2_sink_sink_ready = litedramcore_sdram_bankmachine2_pipe_valid_sink_ready;
assign litedramcore_sdram_bankmachine2_pipe_valid_sink_first = litedramcore_sdram_bankmachine2_sink_sink_first;
assign litedramcore_sdram_bankmachine2_pipe_valid_sink_last = litedramcore_sdram_bankmachine2_sink_sink_last;
assign litedramcore_sdram_bankmachine2_pipe_valid_sink_payload_we = litedramcore_sdram_bankmachine2_sink_sink_payload_we;
assign litedramcore_sdram_bankmachine2_pipe_valid_sink_payload_addr = litedramcore_sdram_bankmachine2_sink_sink_payload_addr;
assign litedramcore_sdram_bankmachine2_source_source_valid = litedramcore_sdram_bankmachine2_pipe_valid_source_valid;
assign litedramcore_sdram_bankmachine2_pipe_valid_source_ready = litedramcore_sdram_bankmachine2_source_source_ready;
assign litedramcore_sdram_bankmachine2_source_source_first = litedramcore_sdram_bankmachine2_pipe_valid_source_first;
assign litedramcore_sdram_bankmachine2_source_source_last = litedramcore_sdram_bankmachine2_pipe_valid_source_last;
assign litedramcore_sdram_bankmachine2_source_source_payload_we = litedramcore_sdram_bankmachine2_pipe_valid_source_payload_we;
assign litedramcore_sdram_bankmachine2_source_source_payload_addr = litedramcore_sdram_bankmachine2_pipe_valid_source_payload_addr;
always @(*) begin
    litedramcore_bankmachine2_next_state <= 4'd0;
    litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state;
    case (litedramcore_bankmachine2_state)
        1'd1: begin
            if ((litedramcore_sdram_bankmachine2_twtpcon_ready & litedramcore_sdram_bankmachine2_trascon_ready)) begin
                if (litedramcore_sdram_bankmachine2_cmd_ready) begin
                    litedramcore_bankmachine2_next_state <= 3'd5;
                end
            end
        end
        2'd2: begin
            if ((litedramcore_sdram_bankmachine2_twtpcon_ready & litedramcore_sdram_bankmachine2_trascon_ready)) begin
                litedramcore_bankmachine2_next_state <= 3'd5;
            end
        end
        2'd3: begin
            if (litedramcore_sdram_bankmachine2_trccon_ready) begin
                if (litedramcore_sdram_bankmachine2_cmd_ready) begin
                    litedramcore_bankmachine2_next_state <= 4'd8;
                end
            end
        end
        3'd4: begin
            if ((~litedramcore_sdram_bankmachine2_refresh_req)) begin
                litedramcore_bankmachine2_next_state <= 1'd0;
            end
        end
        3'd5: begin
            litedramcore_bankmachine2_next_state <= 3'd6;
        end
        3'd6: begin
            litedramcore_bankmachine2_next_state <= 3'd7;
        end
        3'd7: begin
            litedramcore_bankmachine2_next_state <= 2'd3;
        end
        4'd8: begin
            litedramcore_bankmachine2_next_state <= 4'd9;
        end
        4'd9: begin
            litedramcore_bankmachine2_next_state <= 4'd10;
        end
        4'd10: begin
            litedramcore_bankmachine2_next_state <= 1'd0;
        end
        default: begin
            if (litedramcore_sdram_bankmachine2_refresh_req) begin
                litedramcore_bankmachine2_next_state <= 3'd4;
            end else begin
                if (litedramcore_sdram_bankmachine2_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine2_row_opened) begin
                        if (litedramcore_sdram_bankmachine2_row_hit) begin
                            if ((litedramcore_sdram_bankmachine2_cmd_ready & litedramcore_sdram_bankmachine2_auto_precharge)) begin
                                litedramcore_bankmachine2_next_state <= 2'd2;
                            end
                        end else begin
                            litedramcore_bankmachine2_next_state <= 1'd1;
                        end
                    end else begin
                        litedramcore_bankmachine2_next_state <= 2'd3;
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine2_cmd_payload_is_write <= 1'd0;
    case (litedramcore_bankmachine2_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine2_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine2_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine2_row_opened) begin
                        if (litedramcore_sdram_bankmachine2_row_hit) begin
                            if (litedramcore_sdram_bankmachine2_source_source_payload_we) begin
                                litedramcore_sdram_bankmachine2_cmd_payload_is_write <= 1'd1;
                            end else begin
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine2_req_wdata_ready <= 1'd0;
    case (litedramcore_bankmachine2_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine2_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine2_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine2_row_opened) begin
                        if (litedramcore_sdram_bankmachine2_row_hit) begin
                            if (litedramcore_sdram_bankmachine2_source_source_payload_we) begin
                                litedramcore_sdram_bankmachine2_req_wdata_ready <= litedramcore_sdram_bankmachine2_cmd_ready;
                            end else begin
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine2_req_rdata_valid <= 1'd0;
    case (litedramcore_bankmachine2_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine2_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine2_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine2_row_opened) begin
                        if (litedramcore_sdram_bankmachine2_row_hit) begin
                            if (litedramcore_sdram_bankmachine2_source_source_payload_we) begin
                            end else begin
                                litedramcore_sdram_bankmachine2_req_rdata_valid <= litedramcore_sdram_bankmachine2_cmd_ready;
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine2_refresh_gnt <= 1'd0;
    case (litedramcore_bankmachine2_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
            if (litedramcore_sdram_bankmachine2_twtpcon_ready) begin
                litedramcore_sdram_bankmachine2_refresh_gnt <= 1'd1;
            end
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine2_row_open <= 1'd0;
    case (litedramcore_bankmachine2_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
            if (litedramcore_sdram_bankmachine2_trccon_ready) begin
                litedramcore_sdram_bankmachine2_row_open <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine2_cmd_valid <= 1'd0;
    case (litedramcore_bankmachine2_state)
        1'd1: begin
            if ((litedramcore_sdram_bankmachine2_twtpcon_ready & litedramcore_sdram_bankmachine2_trascon_ready)) begin
                litedramcore_sdram_bankmachine2_cmd_valid <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
            if (litedramcore_sdram_bankmachine2_trccon_ready) begin
                litedramcore_sdram_bankmachine2_cmd_valid <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine2_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine2_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine2_row_opened) begin
                        if (litedramcore_sdram_bankmachine2_row_hit) begin
                            litedramcore_sdram_bankmachine2_cmd_valid <= 1'd1;
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine2_row_close <= 1'd0;
    case (litedramcore_bankmachine2_state)
        1'd1: begin
            litedramcore_sdram_bankmachine2_row_close <= 1'd1;
        end
        2'd2: begin
            litedramcore_sdram_bankmachine2_row_close <= 1'd1;
        end
        2'd3: begin
        end
        3'd4: begin
            litedramcore_sdram_bankmachine2_row_close <= 1'd1;
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine2_row_col_n_addr_sel <= 1'd0;
    case (litedramcore_bankmachine2_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
            if (litedramcore_sdram_bankmachine2_trccon_ready) begin
                litedramcore_sdram_bankmachine2_row_col_n_addr_sel <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine2_cmd_payload_cas <= 1'd0;
    case (litedramcore_bankmachine2_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine2_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine2_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine2_row_opened) begin
                        if (litedramcore_sdram_bankmachine2_row_hit) begin
                            litedramcore_sdram_bankmachine2_cmd_payload_cas <= 1'd1;
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine2_cmd_payload_ras <= 1'd0;
    case (litedramcore_bankmachine2_state)
        1'd1: begin
            if ((litedramcore_sdram_bankmachine2_twtpcon_ready & litedramcore_sdram_bankmachine2_trascon_ready)) begin
                litedramcore_sdram_bankmachine2_cmd_payload_ras <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
            if (litedramcore_sdram_bankmachine2_trccon_ready) begin
                litedramcore_sdram_bankmachine2_cmd_payload_ras <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine2_cmd_payload_we <= 1'd0;
    case (litedramcore_bankmachine2_state)
        1'd1: begin
            if ((litedramcore_sdram_bankmachine2_twtpcon_ready & litedramcore_sdram_bankmachine2_trascon_ready)) begin
                litedramcore_sdram_bankmachine2_cmd_payload_we <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine2_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine2_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine2_row_opened) begin
                        if (litedramcore_sdram_bankmachine2_row_hit) begin
                            if (litedramcore_sdram_bankmachine2_source_source_payload_we) begin
                                litedramcore_sdram_bankmachine2_cmd_payload_we <= 1'd1;
                            end else begin
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd0;
    case (litedramcore_bankmachine2_state)
        1'd1: begin
            if ((litedramcore_sdram_bankmachine2_twtpcon_ready & litedramcore_sdram_bankmachine2_trascon_ready)) begin
                litedramcore_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
            if (litedramcore_sdram_bankmachine2_trccon_ready) begin
                litedramcore_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1;
            end
        end
        3'd4: begin
            litedramcore_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1;
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine2_cmd_payload_is_read <= 1'd0;
    case (litedramcore_bankmachine2_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine2_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine2_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine2_row_opened) begin
                        if (litedramcore_sdram_bankmachine2_row_hit) begin
                            if (litedramcore_sdram_bankmachine2_source_source_payload_we) begin
                            end else begin
                                litedramcore_sdram_bankmachine2_cmd_payload_is_read <= 1'd1;
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
assign litedramcore_sdram_bankmachine3_sink_valid = litedramcore_sdram_bankmachine3_req_valid;
assign litedramcore_sdram_bankmachine3_req_ready = litedramcore_sdram_bankmachine3_sink_ready;
assign litedramcore_sdram_bankmachine3_sink_payload_we = litedramcore_sdram_bankmachine3_req_we;
assign litedramcore_sdram_bankmachine3_sink_payload_addr = litedramcore_sdram_bankmachine3_req_addr;
assign litedramcore_sdram_bankmachine3_sink_sink_valid = litedramcore_sdram_bankmachine3_source_valid;
assign litedramcore_sdram_bankmachine3_source_ready = litedramcore_sdram_bankmachine3_sink_sink_ready;
assign litedramcore_sdram_bankmachine3_sink_sink_first = litedramcore_sdram_bankmachine3_source_first;
assign litedramcore_sdram_bankmachine3_sink_sink_last = litedramcore_sdram_bankmachine3_source_last;
assign litedramcore_sdram_bankmachine3_sink_sink_payload_we = litedramcore_sdram_bankmachine3_source_payload_we;
assign litedramcore_sdram_bankmachine3_sink_sink_payload_addr = litedramcore_sdram_bankmachine3_source_payload_addr;
assign litedramcore_sdram_bankmachine3_source_source_ready = (litedramcore_sdram_bankmachine3_req_wdata_ready | litedramcore_sdram_bankmachine3_req_rdata_valid);
assign litedramcore_sdram_bankmachine3_req_lock = (litedramcore_sdram_bankmachine3_source_valid | litedramcore_sdram_bankmachine3_source_source_valid);
assign litedramcore_sdram_bankmachine3_row_hit = (litedramcore_sdram_bankmachine3_row == litedramcore_sdram_bankmachine3_source_source_payload_addr[21:7]);
assign litedramcore_sdram_bankmachine3_cmd_payload_ba = 2'd3;
always @(*) begin
    litedramcore_sdram_bankmachine3_cmd_payload_a <= 15'd0;
    if (litedramcore_sdram_bankmachine3_row_col_n_addr_sel) begin
        litedramcore_sdram_bankmachine3_cmd_payload_a <= litedramcore_sdram_bankmachine3_source_source_payload_addr[21:7];
    end else begin
        litedramcore_sdram_bankmachine3_cmd_payload_a <= ((litedramcore_sdram_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_sdram_bankmachine3_source_source_payload_addr[6:0], {3{1'd0}}});
    end
end
assign litedramcore_sdram_bankmachine3_twtpcon_valid = ((litedramcore_sdram_bankmachine3_cmd_valid & litedramcore_sdram_bankmachine3_cmd_ready) & litedramcore_sdram_bankmachine3_cmd_payload_is_write);
assign litedramcore_sdram_bankmachine3_trccon_valid = ((litedramcore_sdram_bankmachine3_cmd_valid & litedramcore_sdram_bankmachine3_cmd_ready) & litedramcore_sdram_bankmachine3_row_open);
assign litedramcore_sdram_bankmachine3_trascon_valid = ((litedramcore_sdram_bankmachine3_cmd_valid & litedramcore_sdram_bankmachine3_cmd_ready) & litedramcore_sdram_bankmachine3_row_open);
always @(*) begin
    litedramcore_sdram_bankmachine3_auto_precharge <= 1'd0;
    if ((litedramcore_sdram_bankmachine3_source_valid & litedramcore_sdram_bankmachine3_source_source_valid)) begin
        if ((litedramcore_sdram_bankmachine3_source_payload_addr[21:7] != litedramcore_sdram_bankmachine3_source_source_payload_addr[21:7])) begin
            litedramcore_sdram_bankmachine3_auto_precharge <= (litedramcore_sdram_bankmachine3_row_close == 1'd0);
        end
    end
end
assign litedramcore_sdram_bankmachine3_syncfifo3_din = {litedramcore_sdram_bankmachine3_fifo_in_last, litedramcore_sdram_bankmachine3_fifo_in_first, litedramcore_sdram_bankmachine3_fifo_in_payload_addr, litedramcore_sdram_bankmachine3_fifo_in_payload_we};
assign {litedramcore_sdram_bankmachine3_fifo_out_last, litedramcore_sdram_bankmachine3_fifo_out_first, litedramcore_sdram_bankmachine3_fifo_out_payload_addr, litedramcore_sdram_bankmachine3_fifo_out_payload_we} = litedramcore_sdram_bankmachine3_syncfifo3_dout;
assign {litedramcore_sdram_bankmachine3_fifo_out_last, litedramcore_sdram_bankmachine3_fifo_out_first, litedramcore_sdram_bankmachine3_fifo_out_payload_addr, litedramcore_sdram_bankmachine3_fifo_out_payload_we} = litedramcore_sdram_bankmachine3_syncfifo3_dout;
assign {litedramcore_sdram_bankmachine3_fifo_out_last, litedramcore_sdram_bankmachine3_fifo_out_first, litedramcore_sdram_bankmachine3_fifo_out_payload_addr, litedramcore_sdram_bankmachine3_fifo_out_payload_we} = litedramcore_sdram_bankmachine3_syncfifo3_dout;
assign {litedramcore_sdram_bankmachine3_fifo_out_last, litedramcore_sdram_bankmachine3_fifo_out_first, litedramcore_sdram_bankmachine3_fifo_out_payload_addr, litedramcore_sdram_bankmachine3_fifo_out_payload_we} = litedramcore_sdram_bankmachine3_syncfifo3_dout;
assign litedramcore_sdram_bankmachine3_sink_ready = litedramcore_sdram_bankmachine3_syncfifo3_writable;
assign litedramcore_sdram_bankmachine3_syncfifo3_we = litedramcore_sdram_bankmachine3_sink_valid;
assign litedramcore_sdram_bankmachine3_fifo_in_first = litedramcore_sdram_bankmachine3_sink_first;
assign litedramcore_sdram_bankmachine3_fifo_in_last = litedramcore_sdram_bankmachine3_sink_last;
assign litedramcore_sdram_bankmachine3_fifo_in_payload_we = litedramcore_sdram_bankmachine3_sink_payload_we;
assign litedramcore_sdram_bankmachine3_fifo_in_payload_addr = litedramcore_sdram_bankmachine3_sink_payload_addr;
assign litedramcore_sdram_bankmachine3_source_valid = litedramcore_sdram_bankmachine3_syncfifo3_readable;
assign litedramcore_sdram_bankmachine3_source_first = litedramcore_sdram_bankmachine3_fifo_out_first;
assign litedramcore_sdram_bankmachine3_source_last = litedramcore_sdram_bankmachine3_fifo_out_last;
assign litedramcore_sdram_bankmachine3_source_payload_we = litedramcore_sdram_bankmachine3_fifo_out_payload_we;
assign litedramcore_sdram_bankmachine3_source_payload_addr = litedramcore_sdram_bankmachine3_fifo_out_payload_addr;
assign litedramcore_sdram_bankmachine3_syncfifo3_re = litedramcore_sdram_bankmachine3_source_ready;
always @(*) begin
    litedramcore_sdram_bankmachine3_wrport_adr <= 4'd0;
    if (litedramcore_sdram_bankmachine3_replace) begin
        litedramcore_sdram_bankmachine3_wrport_adr <= (litedramcore_sdram_bankmachine3_produce - 1'd1);
    end else begin
        litedramcore_sdram_bankmachine3_wrport_adr <= litedramcore_sdram_bankmachine3_produce;
    end
end
assign litedramcore_sdram_bankmachine3_wrport_dat_w = litedramcore_sdram_bankmachine3_syncfifo3_din;
assign litedramcore_sdram_bankmachine3_wrport_we = (litedramcore_sdram_bankmachine3_syncfifo3_we & (litedramcore_sdram_bankmachine3_syncfifo3_writable | litedramcore_sdram_bankmachine3_replace));
assign litedramcore_sdram_bankmachine3_do_read = (litedramcore_sdram_bankmachine3_syncfifo3_readable & litedramcore_sdram_bankmachine3_syncfifo3_re);
assign litedramcore_sdram_bankmachine3_rdport_adr = litedramcore_sdram_bankmachine3_consume;
assign litedramcore_sdram_bankmachine3_syncfifo3_dout = litedramcore_sdram_bankmachine3_rdport_dat_r;
assign litedramcore_sdram_bankmachine3_syncfifo3_writable = (litedramcore_sdram_bankmachine3_level != 5'd16);
assign litedramcore_sdram_bankmachine3_syncfifo3_readable = (litedramcore_sdram_bankmachine3_level != 1'd0);
assign litedramcore_sdram_bankmachine3_pipe_valid_sink_ready = ((~litedramcore_sdram_bankmachine3_pipe_valid_source_valid) | litedramcore_sdram_bankmachine3_pipe_valid_source_ready);
assign litedramcore_sdram_bankmachine3_pipe_valid_sink_valid = litedramcore_sdram_bankmachine3_sink_sink_valid;
assign litedramcore_sdram_bankmachine3_sink_sink_ready = litedramcore_sdram_bankmachine3_pipe_valid_sink_ready;
assign litedramcore_sdram_bankmachine3_pipe_valid_sink_first = litedramcore_sdram_bankmachine3_sink_sink_first;
assign litedramcore_sdram_bankmachine3_pipe_valid_sink_last = litedramcore_sdram_bankmachine3_sink_sink_last;
assign litedramcore_sdram_bankmachine3_pipe_valid_sink_payload_we = litedramcore_sdram_bankmachine3_sink_sink_payload_we;
assign litedramcore_sdram_bankmachine3_pipe_valid_sink_payload_addr = litedramcore_sdram_bankmachine3_sink_sink_payload_addr;
assign litedramcore_sdram_bankmachine3_source_source_valid = litedramcore_sdram_bankmachine3_pipe_valid_source_valid;
assign litedramcore_sdram_bankmachine3_pipe_valid_source_ready = litedramcore_sdram_bankmachine3_source_source_ready;
assign litedramcore_sdram_bankmachine3_source_source_first = litedramcore_sdram_bankmachine3_pipe_valid_source_first;
assign litedramcore_sdram_bankmachine3_source_source_last = litedramcore_sdram_bankmachine3_pipe_valid_source_last;
assign litedramcore_sdram_bankmachine3_source_source_payload_we = litedramcore_sdram_bankmachine3_pipe_valid_source_payload_we;
assign litedramcore_sdram_bankmachine3_source_source_payload_addr = litedramcore_sdram_bankmachine3_pipe_valid_source_payload_addr;
always @(*) begin
    litedramcore_bankmachine3_next_state <= 4'd0;
    litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state;
    case (litedramcore_bankmachine3_state)
        1'd1: begin
            if ((litedramcore_sdram_bankmachine3_twtpcon_ready & litedramcore_sdram_bankmachine3_trascon_ready)) begin
                if (litedramcore_sdram_bankmachine3_cmd_ready) begin
                    litedramcore_bankmachine3_next_state <= 3'd5;
                end
            end
        end
        2'd2: begin
            if ((litedramcore_sdram_bankmachine3_twtpcon_ready & litedramcore_sdram_bankmachine3_trascon_ready)) begin
                litedramcore_bankmachine3_next_state <= 3'd5;
            end
        end
        2'd3: begin
            if (litedramcore_sdram_bankmachine3_trccon_ready) begin
                if (litedramcore_sdram_bankmachine3_cmd_ready) begin
                    litedramcore_bankmachine3_next_state <= 4'd8;
                end
            end
        end
        3'd4: begin
            if ((~litedramcore_sdram_bankmachine3_refresh_req)) begin
                litedramcore_bankmachine3_next_state <= 1'd0;
            end
        end
        3'd5: begin
            litedramcore_bankmachine3_next_state <= 3'd6;
        end
        3'd6: begin
            litedramcore_bankmachine3_next_state <= 3'd7;
        end
        3'd7: begin
            litedramcore_bankmachine3_next_state <= 2'd3;
        end
        4'd8: begin
            litedramcore_bankmachine3_next_state <= 4'd9;
        end
        4'd9: begin
            litedramcore_bankmachine3_next_state <= 4'd10;
        end
        4'd10: begin
            litedramcore_bankmachine3_next_state <= 1'd0;
        end
        default: begin
            if (litedramcore_sdram_bankmachine3_refresh_req) begin
                litedramcore_bankmachine3_next_state <= 3'd4;
            end else begin
                if (litedramcore_sdram_bankmachine3_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine3_row_opened) begin
                        if (litedramcore_sdram_bankmachine3_row_hit) begin
                            if ((litedramcore_sdram_bankmachine3_cmd_ready & litedramcore_sdram_bankmachine3_auto_precharge)) begin
                                litedramcore_bankmachine3_next_state <= 2'd2;
                            end
                        end else begin
                            litedramcore_bankmachine3_next_state <= 1'd1;
                        end
                    end else begin
                        litedramcore_bankmachine3_next_state <= 2'd3;
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine3_refresh_gnt <= 1'd0;
    case (litedramcore_bankmachine3_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
            if (litedramcore_sdram_bankmachine3_twtpcon_ready) begin
                litedramcore_sdram_bankmachine3_refresh_gnt <= 1'd1;
            end
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine3_row_open <= 1'd0;
    case (litedramcore_bankmachine3_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
            if (litedramcore_sdram_bankmachine3_trccon_ready) begin
                litedramcore_sdram_bankmachine3_row_open <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine3_cmd_valid <= 1'd0;
    case (litedramcore_bankmachine3_state)
        1'd1: begin
            if ((litedramcore_sdram_bankmachine3_twtpcon_ready & litedramcore_sdram_bankmachine3_trascon_ready)) begin
                litedramcore_sdram_bankmachine3_cmd_valid <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
            if (litedramcore_sdram_bankmachine3_trccon_ready) begin
                litedramcore_sdram_bankmachine3_cmd_valid <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine3_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine3_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine3_row_opened) begin
                        if (litedramcore_sdram_bankmachine3_row_hit) begin
                            litedramcore_sdram_bankmachine3_cmd_valid <= 1'd1;
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine3_row_close <= 1'd0;
    case (litedramcore_bankmachine3_state)
        1'd1: begin
            litedramcore_sdram_bankmachine3_row_close <= 1'd1;
        end
        2'd2: begin
            litedramcore_sdram_bankmachine3_row_close <= 1'd1;
        end
        2'd3: begin
        end
        3'd4: begin
            litedramcore_sdram_bankmachine3_row_close <= 1'd1;
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine3_row_col_n_addr_sel <= 1'd0;
    case (litedramcore_bankmachine3_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
            if (litedramcore_sdram_bankmachine3_trccon_ready) begin
                litedramcore_sdram_bankmachine3_row_col_n_addr_sel <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine3_cmd_payload_cas <= 1'd0;
    case (litedramcore_bankmachine3_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine3_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine3_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine3_row_opened) begin
                        if (litedramcore_sdram_bankmachine3_row_hit) begin
                            litedramcore_sdram_bankmachine3_cmd_payload_cas <= 1'd1;
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine3_cmd_payload_ras <= 1'd0;
    case (litedramcore_bankmachine3_state)
        1'd1: begin
            if ((litedramcore_sdram_bankmachine3_twtpcon_ready & litedramcore_sdram_bankmachine3_trascon_ready)) begin
                litedramcore_sdram_bankmachine3_cmd_payload_ras <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
            if (litedramcore_sdram_bankmachine3_trccon_ready) begin
                litedramcore_sdram_bankmachine3_cmd_payload_ras <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine3_cmd_payload_we <= 1'd0;
    case (litedramcore_bankmachine3_state)
        1'd1: begin
            if ((litedramcore_sdram_bankmachine3_twtpcon_ready & litedramcore_sdram_bankmachine3_trascon_ready)) begin
                litedramcore_sdram_bankmachine3_cmd_payload_we <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine3_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine3_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine3_row_opened) begin
                        if (litedramcore_sdram_bankmachine3_row_hit) begin
                            if (litedramcore_sdram_bankmachine3_source_source_payload_we) begin
                                litedramcore_sdram_bankmachine3_cmd_payload_we <= 1'd1;
                            end else begin
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd0;
    case (litedramcore_bankmachine3_state)
        1'd1: begin
            if ((litedramcore_sdram_bankmachine3_twtpcon_ready & litedramcore_sdram_bankmachine3_trascon_ready)) begin
                litedramcore_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
            if (litedramcore_sdram_bankmachine3_trccon_ready) begin
                litedramcore_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1;
            end
        end
        3'd4: begin
            litedramcore_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1;
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine3_cmd_payload_is_read <= 1'd0;
    case (litedramcore_bankmachine3_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine3_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine3_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine3_row_opened) begin
                        if (litedramcore_sdram_bankmachine3_row_hit) begin
                            if (litedramcore_sdram_bankmachine3_source_source_payload_we) begin
                            end else begin
                                litedramcore_sdram_bankmachine3_cmd_payload_is_read <= 1'd1;
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine3_cmd_payload_is_write <= 1'd0;
    case (litedramcore_bankmachine3_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine3_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine3_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine3_row_opened) begin
                        if (litedramcore_sdram_bankmachine3_row_hit) begin
                            if (litedramcore_sdram_bankmachine3_source_source_payload_we) begin
                                litedramcore_sdram_bankmachine3_cmd_payload_is_write <= 1'd1;
                            end else begin
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine3_req_wdata_ready <= 1'd0;
    case (litedramcore_bankmachine3_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine3_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine3_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine3_row_opened) begin
                        if (litedramcore_sdram_bankmachine3_row_hit) begin
                            if (litedramcore_sdram_bankmachine3_source_source_payload_we) begin
                                litedramcore_sdram_bankmachine3_req_wdata_ready <= litedramcore_sdram_bankmachine3_cmd_ready;
                            end else begin
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine3_req_rdata_valid <= 1'd0;
    case (litedramcore_bankmachine3_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine3_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine3_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine3_row_opened) begin
                        if (litedramcore_sdram_bankmachine3_row_hit) begin
                            if (litedramcore_sdram_bankmachine3_source_source_payload_we) begin
                            end else begin
                                litedramcore_sdram_bankmachine3_req_rdata_valid <= litedramcore_sdram_bankmachine3_cmd_ready;
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
assign litedramcore_sdram_bankmachine4_sink_valid = litedramcore_sdram_bankmachine4_req_valid;
assign litedramcore_sdram_bankmachine4_req_ready = litedramcore_sdram_bankmachine4_sink_ready;
assign litedramcore_sdram_bankmachine4_sink_payload_we = litedramcore_sdram_bankmachine4_req_we;
assign litedramcore_sdram_bankmachine4_sink_payload_addr = litedramcore_sdram_bankmachine4_req_addr;
assign litedramcore_sdram_bankmachine4_sink_sink_valid = litedramcore_sdram_bankmachine4_source_valid;
assign litedramcore_sdram_bankmachine4_source_ready = litedramcore_sdram_bankmachine4_sink_sink_ready;
assign litedramcore_sdram_bankmachine4_sink_sink_first = litedramcore_sdram_bankmachine4_source_first;
assign litedramcore_sdram_bankmachine4_sink_sink_last = litedramcore_sdram_bankmachine4_source_last;
assign litedramcore_sdram_bankmachine4_sink_sink_payload_we = litedramcore_sdram_bankmachine4_source_payload_we;
assign litedramcore_sdram_bankmachine4_sink_sink_payload_addr = litedramcore_sdram_bankmachine4_source_payload_addr;
assign litedramcore_sdram_bankmachine4_source_source_ready = (litedramcore_sdram_bankmachine4_req_wdata_ready | litedramcore_sdram_bankmachine4_req_rdata_valid);
assign litedramcore_sdram_bankmachine4_req_lock = (litedramcore_sdram_bankmachine4_source_valid | litedramcore_sdram_bankmachine4_source_source_valid);
assign litedramcore_sdram_bankmachine4_row_hit = (litedramcore_sdram_bankmachine4_row == litedramcore_sdram_bankmachine4_source_source_payload_addr[21:7]);
assign litedramcore_sdram_bankmachine4_cmd_payload_ba = 3'd4;
always @(*) begin
    litedramcore_sdram_bankmachine4_cmd_payload_a <= 15'd0;
    if (litedramcore_sdram_bankmachine4_row_col_n_addr_sel) begin
        litedramcore_sdram_bankmachine4_cmd_payload_a <= litedramcore_sdram_bankmachine4_source_source_payload_addr[21:7];
    end else begin
        litedramcore_sdram_bankmachine4_cmd_payload_a <= ((litedramcore_sdram_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_sdram_bankmachine4_source_source_payload_addr[6:0], {3{1'd0}}});
    end
end
assign litedramcore_sdram_bankmachine4_twtpcon_valid = ((litedramcore_sdram_bankmachine4_cmd_valid & litedramcore_sdram_bankmachine4_cmd_ready) & litedramcore_sdram_bankmachine4_cmd_payload_is_write);
assign litedramcore_sdram_bankmachine4_trccon_valid = ((litedramcore_sdram_bankmachine4_cmd_valid & litedramcore_sdram_bankmachine4_cmd_ready) & litedramcore_sdram_bankmachine4_row_open);
assign litedramcore_sdram_bankmachine4_trascon_valid = ((litedramcore_sdram_bankmachine4_cmd_valid & litedramcore_sdram_bankmachine4_cmd_ready) & litedramcore_sdram_bankmachine4_row_open);
always @(*) begin
    litedramcore_sdram_bankmachine4_auto_precharge <= 1'd0;
    if ((litedramcore_sdram_bankmachine4_source_valid & litedramcore_sdram_bankmachine4_source_source_valid)) begin
        if ((litedramcore_sdram_bankmachine4_source_payload_addr[21:7] != litedramcore_sdram_bankmachine4_source_source_payload_addr[21:7])) begin
            litedramcore_sdram_bankmachine4_auto_precharge <= (litedramcore_sdram_bankmachine4_row_close == 1'd0);
        end
    end
end
assign litedramcore_sdram_bankmachine4_syncfifo4_din = {litedramcore_sdram_bankmachine4_fifo_in_last, litedramcore_sdram_bankmachine4_fifo_in_first, litedramcore_sdram_bankmachine4_fifo_in_payload_addr, litedramcore_sdram_bankmachine4_fifo_in_payload_we};
assign {litedramcore_sdram_bankmachine4_fifo_out_last, litedramcore_sdram_bankmachine4_fifo_out_first, litedramcore_sdram_bankmachine4_fifo_out_payload_addr, litedramcore_sdram_bankmachine4_fifo_out_payload_we} = litedramcore_sdram_bankmachine4_syncfifo4_dout;
assign {litedramcore_sdram_bankmachine4_fifo_out_last, litedramcore_sdram_bankmachine4_fifo_out_first, litedramcore_sdram_bankmachine4_fifo_out_payload_addr, litedramcore_sdram_bankmachine4_fifo_out_payload_we} = litedramcore_sdram_bankmachine4_syncfifo4_dout;
assign {litedramcore_sdram_bankmachine4_fifo_out_last, litedramcore_sdram_bankmachine4_fifo_out_first, litedramcore_sdram_bankmachine4_fifo_out_payload_addr, litedramcore_sdram_bankmachine4_fifo_out_payload_we} = litedramcore_sdram_bankmachine4_syncfifo4_dout;
assign {litedramcore_sdram_bankmachine4_fifo_out_last, litedramcore_sdram_bankmachine4_fifo_out_first, litedramcore_sdram_bankmachine4_fifo_out_payload_addr, litedramcore_sdram_bankmachine4_fifo_out_payload_we} = litedramcore_sdram_bankmachine4_syncfifo4_dout;
assign litedramcore_sdram_bankmachine4_sink_ready = litedramcore_sdram_bankmachine4_syncfifo4_writable;
assign litedramcore_sdram_bankmachine4_syncfifo4_we = litedramcore_sdram_bankmachine4_sink_valid;
assign litedramcore_sdram_bankmachine4_fifo_in_first = litedramcore_sdram_bankmachine4_sink_first;
assign litedramcore_sdram_bankmachine4_fifo_in_last = litedramcore_sdram_bankmachine4_sink_last;
assign litedramcore_sdram_bankmachine4_fifo_in_payload_we = litedramcore_sdram_bankmachine4_sink_payload_we;
assign litedramcore_sdram_bankmachine4_fifo_in_payload_addr = litedramcore_sdram_bankmachine4_sink_payload_addr;
assign litedramcore_sdram_bankmachine4_source_valid = litedramcore_sdram_bankmachine4_syncfifo4_readable;
assign litedramcore_sdram_bankmachine4_source_first = litedramcore_sdram_bankmachine4_fifo_out_first;
assign litedramcore_sdram_bankmachine4_source_last = litedramcore_sdram_bankmachine4_fifo_out_last;
assign litedramcore_sdram_bankmachine4_source_payload_we = litedramcore_sdram_bankmachine4_fifo_out_payload_we;
assign litedramcore_sdram_bankmachine4_source_payload_addr = litedramcore_sdram_bankmachine4_fifo_out_payload_addr;
assign litedramcore_sdram_bankmachine4_syncfifo4_re = litedramcore_sdram_bankmachine4_source_ready;
always @(*) begin
    litedramcore_sdram_bankmachine4_wrport_adr <= 4'd0;
    if (litedramcore_sdram_bankmachine4_replace) begin
        litedramcore_sdram_bankmachine4_wrport_adr <= (litedramcore_sdram_bankmachine4_produce - 1'd1);
    end else begin
        litedramcore_sdram_bankmachine4_wrport_adr <= litedramcore_sdram_bankmachine4_produce;
    end
end
assign litedramcore_sdram_bankmachine4_wrport_dat_w = litedramcore_sdram_bankmachine4_syncfifo4_din;
assign litedramcore_sdram_bankmachine4_wrport_we = (litedramcore_sdram_bankmachine4_syncfifo4_we & (litedramcore_sdram_bankmachine4_syncfifo4_writable | litedramcore_sdram_bankmachine4_replace));
assign litedramcore_sdram_bankmachine4_do_read = (litedramcore_sdram_bankmachine4_syncfifo4_readable & litedramcore_sdram_bankmachine4_syncfifo4_re);
assign litedramcore_sdram_bankmachine4_rdport_adr = litedramcore_sdram_bankmachine4_consume;
assign litedramcore_sdram_bankmachine4_syncfifo4_dout = litedramcore_sdram_bankmachine4_rdport_dat_r;
assign litedramcore_sdram_bankmachine4_syncfifo4_writable = (litedramcore_sdram_bankmachine4_level != 5'd16);
assign litedramcore_sdram_bankmachine4_syncfifo4_readable = (litedramcore_sdram_bankmachine4_level != 1'd0);
assign litedramcore_sdram_bankmachine4_pipe_valid_sink_ready = ((~litedramcore_sdram_bankmachine4_pipe_valid_source_valid) | litedramcore_sdram_bankmachine4_pipe_valid_source_ready);
assign litedramcore_sdram_bankmachine4_pipe_valid_sink_valid = litedramcore_sdram_bankmachine4_sink_sink_valid;
assign litedramcore_sdram_bankmachine4_sink_sink_ready = litedramcore_sdram_bankmachine4_pipe_valid_sink_ready;
assign litedramcore_sdram_bankmachine4_pipe_valid_sink_first = litedramcore_sdram_bankmachine4_sink_sink_first;
assign litedramcore_sdram_bankmachine4_pipe_valid_sink_last = litedramcore_sdram_bankmachine4_sink_sink_last;
assign litedramcore_sdram_bankmachine4_pipe_valid_sink_payload_we = litedramcore_sdram_bankmachine4_sink_sink_payload_we;
assign litedramcore_sdram_bankmachine4_pipe_valid_sink_payload_addr = litedramcore_sdram_bankmachine4_sink_sink_payload_addr;
assign litedramcore_sdram_bankmachine4_source_source_valid = litedramcore_sdram_bankmachine4_pipe_valid_source_valid;
assign litedramcore_sdram_bankmachine4_pipe_valid_source_ready = litedramcore_sdram_bankmachine4_source_source_ready;
assign litedramcore_sdram_bankmachine4_source_source_first = litedramcore_sdram_bankmachine4_pipe_valid_source_first;
assign litedramcore_sdram_bankmachine4_source_source_last = litedramcore_sdram_bankmachine4_pipe_valid_source_last;
assign litedramcore_sdram_bankmachine4_source_source_payload_we = litedramcore_sdram_bankmachine4_pipe_valid_source_payload_we;
assign litedramcore_sdram_bankmachine4_source_source_payload_addr = litedramcore_sdram_bankmachine4_pipe_valid_source_payload_addr;
always @(*) begin
    litedramcore_bankmachine4_next_state <= 4'd0;
    litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state;
    case (litedramcore_bankmachine4_state)
        1'd1: begin
            if ((litedramcore_sdram_bankmachine4_twtpcon_ready & litedramcore_sdram_bankmachine4_trascon_ready)) begin
                if (litedramcore_sdram_bankmachine4_cmd_ready) begin
                    litedramcore_bankmachine4_next_state <= 3'd5;
                end
            end
        end
        2'd2: begin
            if ((litedramcore_sdram_bankmachine4_twtpcon_ready & litedramcore_sdram_bankmachine4_trascon_ready)) begin
                litedramcore_bankmachine4_next_state <= 3'd5;
            end
        end
        2'd3: begin
            if (litedramcore_sdram_bankmachine4_trccon_ready) begin
                if (litedramcore_sdram_bankmachine4_cmd_ready) begin
                    litedramcore_bankmachine4_next_state <= 4'd8;
                end
            end
        end
        3'd4: begin
            if ((~litedramcore_sdram_bankmachine4_refresh_req)) begin
                litedramcore_bankmachine4_next_state <= 1'd0;
            end
        end
        3'd5: begin
            litedramcore_bankmachine4_next_state <= 3'd6;
        end
        3'd6: begin
            litedramcore_bankmachine4_next_state <= 3'd7;
        end
        3'd7: begin
            litedramcore_bankmachine4_next_state <= 2'd3;
        end
        4'd8: begin
            litedramcore_bankmachine4_next_state <= 4'd9;
        end
        4'd9: begin
            litedramcore_bankmachine4_next_state <= 4'd10;
        end
        4'd10: begin
            litedramcore_bankmachine4_next_state <= 1'd0;
        end
        default: begin
            if (litedramcore_sdram_bankmachine4_refresh_req) begin
                litedramcore_bankmachine4_next_state <= 3'd4;
            end else begin
                if (litedramcore_sdram_bankmachine4_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine4_row_opened) begin
                        if (litedramcore_sdram_bankmachine4_row_hit) begin
                            if ((litedramcore_sdram_bankmachine4_cmd_ready & litedramcore_sdram_bankmachine4_auto_precharge)) begin
                                litedramcore_bankmachine4_next_state <= 2'd2;
                            end
                        end else begin
                            litedramcore_bankmachine4_next_state <= 1'd1;
                        end
                    end else begin
                        litedramcore_bankmachine4_next_state <= 2'd3;
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine4_row_col_n_addr_sel <= 1'd0;
    case (litedramcore_bankmachine4_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
            if (litedramcore_sdram_bankmachine4_trccon_ready) begin
                litedramcore_sdram_bankmachine4_row_col_n_addr_sel <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine4_cmd_payload_cas <= 1'd0;
    case (litedramcore_bankmachine4_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine4_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine4_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine4_row_opened) begin
                        if (litedramcore_sdram_bankmachine4_row_hit) begin
                            litedramcore_sdram_bankmachine4_cmd_payload_cas <= 1'd1;
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine4_cmd_payload_ras <= 1'd0;
    case (litedramcore_bankmachine4_state)
        1'd1: begin
            if ((litedramcore_sdram_bankmachine4_twtpcon_ready & litedramcore_sdram_bankmachine4_trascon_ready)) begin
                litedramcore_sdram_bankmachine4_cmd_payload_ras <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
            if (litedramcore_sdram_bankmachine4_trccon_ready) begin
                litedramcore_sdram_bankmachine4_cmd_payload_ras <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine4_cmd_payload_we <= 1'd0;
    case (litedramcore_bankmachine4_state)
        1'd1: begin
            if ((litedramcore_sdram_bankmachine4_twtpcon_ready & litedramcore_sdram_bankmachine4_trascon_ready)) begin
                litedramcore_sdram_bankmachine4_cmd_payload_we <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine4_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine4_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine4_row_opened) begin
                        if (litedramcore_sdram_bankmachine4_row_hit) begin
                            if (litedramcore_sdram_bankmachine4_source_source_payload_we) begin
                                litedramcore_sdram_bankmachine4_cmd_payload_we <= 1'd1;
                            end else begin
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd0;
    case (litedramcore_bankmachine4_state)
        1'd1: begin
            if ((litedramcore_sdram_bankmachine4_twtpcon_ready & litedramcore_sdram_bankmachine4_trascon_ready)) begin
                litedramcore_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
            if (litedramcore_sdram_bankmachine4_trccon_ready) begin
                litedramcore_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd1;
            end
        end
        3'd4: begin
            litedramcore_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd1;
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine4_cmd_payload_is_read <= 1'd0;
    case (litedramcore_bankmachine4_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine4_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine4_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine4_row_opened) begin
                        if (litedramcore_sdram_bankmachine4_row_hit) begin
                            if (litedramcore_sdram_bankmachine4_source_source_payload_we) begin
                            end else begin
                                litedramcore_sdram_bankmachine4_cmd_payload_is_read <= 1'd1;
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine4_cmd_payload_is_write <= 1'd0;
    case (litedramcore_bankmachine4_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine4_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine4_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine4_row_opened) begin
                        if (litedramcore_sdram_bankmachine4_row_hit) begin
                            if (litedramcore_sdram_bankmachine4_source_source_payload_we) begin
                                litedramcore_sdram_bankmachine4_cmd_payload_is_write <= 1'd1;
                            end else begin
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine4_req_wdata_ready <= 1'd0;
    case (litedramcore_bankmachine4_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine4_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine4_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine4_row_opened) begin
                        if (litedramcore_sdram_bankmachine4_row_hit) begin
                            if (litedramcore_sdram_bankmachine4_source_source_payload_we) begin
                                litedramcore_sdram_bankmachine4_req_wdata_ready <= litedramcore_sdram_bankmachine4_cmd_ready;
                            end else begin
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine4_req_rdata_valid <= 1'd0;
    case (litedramcore_bankmachine4_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine4_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine4_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine4_row_opened) begin
                        if (litedramcore_sdram_bankmachine4_row_hit) begin
                            if (litedramcore_sdram_bankmachine4_source_source_payload_we) begin
                            end else begin
                                litedramcore_sdram_bankmachine4_req_rdata_valid <= litedramcore_sdram_bankmachine4_cmd_ready;
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine4_refresh_gnt <= 1'd0;
    case (litedramcore_bankmachine4_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
            if (litedramcore_sdram_bankmachine4_twtpcon_ready) begin
                litedramcore_sdram_bankmachine4_refresh_gnt <= 1'd1;
            end
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine4_row_open <= 1'd0;
    case (litedramcore_bankmachine4_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
            if (litedramcore_sdram_bankmachine4_trccon_ready) begin
                litedramcore_sdram_bankmachine4_row_open <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine4_cmd_valid <= 1'd0;
    case (litedramcore_bankmachine4_state)
        1'd1: begin
            if ((litedramcore_sdram_bankmachine4_twtpcon_ready & litedramcore_sdram_bankmachine4_trascon_ready)) begin
                litedramcore_sdram_bankmachine4_cmd_valid <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
            if (litedramcore_sdram_bankmachine4_trccon_ready) begin
                litedramcore_sdram_bankmachine4_cmd_valid <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine4_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine4_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine4_row_opened) begin
                        if (litedramcore_sdram_bankmachine4_row_hit) begin
                            litedramcore_sdram_bankmachine4_cmd_valid <= 1'd1;
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine4_row_close <= 1'd0;
    case (litedramcore_bankmachine4_state)
        1'd1: begin
            litedramcore_sdram_bankmachine4_row_close <= 1'd1;
        end
        2'd2: begin
            litedramcore_sdram_bankmachine4_row_close <= 1'd1;
        end
        2'd3: begin
        end
        3'd4: begin
            litedramcore_sdram_bankmachine4_row_close <= 1'd1;
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
        end
    endcase
end
assign litedramcore_sdram_bankmachine5_sink_valid = litedramcore_sdram_bankmachine5_req_valid;
assign litedramcore_sdram_bankmachine5_req_ready = litedramcore_sdram_bankmachine5_sink_ready;
assign litedramcore_sdram_bankmachine5_sink_payload_we = litedramcore_sdram_bankmachine5_req_we;
assign litedramcore_sdram_bankmachine5_sink_payload_addr = litedramcore_sdram_bankmachine5_req_addr;
assign litedramcore_sdram_bankmachine5_sink_sink_valid = litedramcore_sdram_bankmachine5_source_valid;
assign litedramcore_sdram_bankmachine5_source_ready = litedramcore_sdram_bankmachine5_sink_sink_ready;
assign litedramcore_sdram_bankmachine5_sink_sink_first = litedramcore_sdram_bankmachine5_source_first;
assign litedramcore_sdram_bankmachine5_sink_sink_last = litedramcore_sdram_bankmachine5_source_last;
assign litedramcore_sdram_bankmachine5_sink_sink_payload_we = litedramcore_sdram_bankmachine5_source_payload_we;
assign litedramcore_sdram_bankmachine5_sink_sink_payload_addr = litedramcore_sdram_bankmachine5_source_payload_addr;
assign litedramcore_sdram_bankmachine5_source_source_ready = (litedramcore_sdram_bankmachine5_req_wdata_ready | litedramcore_sdram_bankmachine5_req_rdata_valid);
assign litedramcore_sdram_bankmachine5_req_lock = (litedramcore_sdram_bankmachine5_source_valid | litedramcore_sdram_bankmachine5_source_source_valid);
assign litedramcore_sdram_bankmachine5_row_hit = (litedramcore_sdram_bankmachine5_row == litedramcore_sdram_bankmachine5_source_source_payload_addr[21:7]);
assign litedramcore_sdram_bankmachine5_cmd_payload_ba = 3'd5;
always @(*) begin
    litedramcore_sdram_bankmachine5_cmd_payload_a <= 15'd0;
    if (litedramcore_sdram_bankmachine5_row_col_n_addr_sel) begin
        litedramcore_sdram_bankmachine5_cmd_payload_a <= litedramcore_sdram_bankmachine5_source_source_payload_addr[21:7];
    end else begin
        litedramcore_sdram_bankmachine5_cmd_payload_a <= ((litedramcore_sdram_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_sdram_bankmachine5_source_source_payload_addr[6:0], {3{1'd0}}});
    end
end
assign litedramcore_sdram_bankmachine5_twtpcon_valid = ((litedramcore_sdram_bankmachine5_cmd_valid & litedramcore_sdram_bankmachine5_cmd_ready) & litedramcore_sdram_bankmachine5_cmd_payload_is_write);
assign litedramcore_sdram_bankmachine5_trccon_valid = ((litedramcore_sdram_bankmachine5_cmd_valid & litedramcore_sdram_bankmachine5_cmd_ready) & litedramcore_sdram_bankmachine5_row_open);
assign litedramcore_sdram_bankmachine5_trascon_valid = ((litedramcore_sdram_bankmachine5_cmd_valid & litedramcore_sdram_bankmachine5_cmd_ready) & litedramcore_sdram_bankmachine5_row_open);
always @(*) begin
    litedramcore_sdram_bankmachine5_auto_precharge <= 1'd0;
    if ((litedramcore_sdram_bankmachine5_source_valid & litedramcore_sdram_bankmachine5_source_source_valid)) begin
        if ((litedramcore_sdram_bankmachine5_source_payload_addr[21:7] != litedramcore_sdram_bankmachine5_source_source_payload_addr[21:7])) begin
            litedramcore_sdram_bankmachine5_auto_precharge <= (litedramcore_sdram_bankmachine5_row_close == 1'd0);
        end
    end
end
assign litedramcore_sdram_bankmachine5_syncfifo5_din = {litedramcore_sdram_bankmachine5_fifo_in_last, litedramcore_sdram_bankmachine5_fifo_in_first, litedramcore_sdram_bankmachine5_fifo_in_payload_addr, litedramcore_sdram_bankmachine5_fifo_in_payload_we};
assign {litedramcore_sdram_bankmachine5_fifo_out_last, litedramcore_sdram_bankmachine5_fifo_out_first, litedramcore_sdram_bankmachine5_fifo_out_payload_addr, litedramcore_sdram_bankmachine5_fifo_out_payload_we} = litedramcore_sdram_bankmachine5_syncfifo5_dout;
assign {litedramcore_sdram_bankmachine5_fifo_out_last, litedramcore_sdram_bankmachine5_fifo_out_first, litedramcore_sdram_bankmachine5_fifo_out_payload_addr, litedramcore_sdram_bankmachine5_fifo_out_payload_we} = litedramcore_sdram_bankmachine5_syncfifo5_dout;
assign {litedramcore_sdram_bankmachine5_fifo_out_last, litedramcore_sdram_bankmachine5_fifo_out_first, litedramcore_sdram_bankmachine5_fifo_out_payload_addr, litedramcore_sdram_bankmachine5_fifo_out_payload_we} = litedramcore_sdram_bankmachine5_syncfifo5_dout;
assign {litedramcore_sdram_bankmachine5_fifo_out_last, litedramcore_sdram_bankmachine5_fifo_out_first, litedramcore_sdram_bankmachine5_fifo_out_payload_addr, litedramcore_sdram_bankmachine5_fifo_out_payload_we} = litedramcore_sdram_bankmachine5_syncfifo5_dout;
assign litedramcore_sdram_bankmachine5_sink_ready = litedramcore_sdram_bankmachine5_syncfifo5_writable;
assign litedramcore_sdram_bankmachine5_syncfifo5_we = litedramcore_sdram_bankmachine5_sink_valid;
assign litedramcore_sdram_bankmachine5_fifo_in_first = litedramcore_sdram_bankmachine5_sink_first;
assign litedramcore_sdram_bankmachine5_fifo_in_last = litedramcore_sdram_bankmachine5_sink_last;
assign litedramcore_sdram_bankmachine5_fifo_in_payload_we = litedramcore_sdram_bankmachine5_sink_payload_we;
assign litedramcore_sdram_bankmachine5_fifo_in_payload_addr = litedramcore_sdram_bankmachine5_sink_payload_addr;
assign litedramcore_sdram_bankmachine5_source_valid = litedramcore_sdram_bankmachine5_syncfifo5_readable;
assign litedramcore_sdram_bankmachine5_source_first = litedramcore_sdram_bankmachine5_fifo_out_first;
assign litedramcore_sdram_bankmachine5_source_last = litedramcore_sdram_bankmachine5_fifo_out_last;
assign litedramcore_sdram_bankmachine5_source_payload_we = litedramcore_sdram_bankmachine5_fifo_out_payload_we;
assign litedramcore_sdram_bankmachine5_source_payload_addr = litedramcore_sdram_bankmachine5_fifo_out_payload_addr;
assign litedramcore_sdram_bankmachine5_syncfifo5_re = litedramcore_sdram_bankmachine5_source_ready;
always @(*) begin
    litedramcore_sdram_bankmachine5_wrport_adr <= 4'd0;
    if (litedramcore_sdram_bankmachine5_replace) begin
        litedramcore_sdram_bankmachine5_wrport_adr <= (litedramcore_sdram_bankmachine5_produce - 1'd1);
    end else begin
        litedramcore_sdram_bankmachine5_wrport_adr <= litedramcore_sdram_bankmachine5_produce;
    end
end
assign litedramcore_sdram_bankmachine5_wrport_dat_w = litedramcore_sdram_bankmachine5_syncfifo5_din;
assign litedramcore_sdram_bankmachine5_wrport_we = (litedramcore_sdram_bankmachine5_syncfifo5_we & (litedramcore_sdram_bankmachine5_syncfifo5_writable | litedramcore_sdram_bankmachine5_replace));
assign litedramcore_sdram_bankmachine5_do_read = (litedramcore_sdram_bankmachine5_syncfifo5_readable & litedramcore_sdram_bankmachine5_syncfifo5_re);
assign litedramcore_sdram_bankmachine5_rdport_adr = litedramcore_sdram_bankmachine5_consume;
assign litedramcore_sdram_bankmachine5_syncfifo5_dout = litedramcore_sdram_bankmachine5_rdport_dat_r;
assign litedramcore_sdram_bankmachine5_syncfifo5_writable = (litedramcore_sdram_bankmachine5_level != 5'd16);
assign litedramcore_sdram_bankmachine5_syncfifo5_readable = (litedramcore_sdram_bankmachine5_level != 1'd0);
assign litedramcore_sdram_bankmachine5_pipe_valid_sink_ready = ((~litedramcore_sdram_bankmachine5_pipe_valid_source_valid) | litedramcore_sdram_bankmachine5_pipe_valid_source_ready);
assign litedramcore_sdram_bankmachine5_pipe_valid_sink_valid = litedramcore_sdram_bankmachine5_sink_sink_valid;
assign litedramcore_sdram_bankmachine5_sink_sink_ready = litedramcore_sdram_bankmachine5_pipe_valid_sink_ready;
assign litedramcore_sdram_bankmachine5_pipe_valid_sink_first = litedramcore_sdram_bankmachine5_sink_sink_first;
assign litedramcore_sdram_bankmachine5_pipe_valid_sink_last = litedramcore_sdram_bankmachine5_sink_sink_last;
assign litedramcore_sdram_bankmachine5_pipe_valid_sink_payload_we = litedramcore_sdram_bankmachine5_sink_sink_payload_we;
assign litedramcore_sdram_bankmachine5_pipe_valid_sink_payload_addr = litedramcore_sdram_bankmachine5_sink_sink_payload_addr;
assign litedramcore_sdram_bankmachine5_source_source_valid = litedramcore_sdram_bankmachine5_pipe_valid_source_valid;
assign litedramcore_sdram_bankmachine5_pipe_valid_source_ready = litedramcore_sdram_bankmachine5_source_source_ready;
assign litedramcore_sdram_bankmachine5_source_source_first = litedramcore_sdram_bankmachine5_pipe_valid_source_first;
assign litedramcore_sdram_bankmachine5_source_source_last = litedramcore_sdram_bankmachine5_pipe_valid_source_last;
assign litedramcore_sdram_bankmachine5_source_source_payload_we = litedramcore_sdram_bankmachine5_pipe_valid_source_payload_we;
assign litedramcore_sdram_bankmachine5_source_source_payload_addr = litedramcore_sdram_bankmachine5_pipe_valid_source_payload_addr;
always @(*) begin
    litedramcore_bankmachine5_next_state <= 4'd0;
    litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state;
    case (litedramcore_bankmachine5_state)
        1'd1: begin
            if ((litedramcore_sdram_bankmachine5_twtpcon_ready & litedramcore_sdram_bankmachine5_trascon_ready)) begin
                if (litedramcore_sdram_bankmachine5_cmd_ready) begin
                    litedramcore_bankmachine5_next_state <= 3'd5;
                end
            end
        end
        2'd2: begin
            if ((litedramcore_sdram_bankmachine5_twtpcon_ready & litedramcore_sdram_bankmachine5_trascon_ready)) begin
                litedramcore_bankmachine5_next_state <= 3'd5;
            end
        end
        2'd3: begin
            if (litedramcore_sdram_bankmachine5_trccon_ready) begin
                if (litedramcore_sdram_bankmachine5_cmd_ready) begin
                    litedramcore_bankmachine5_next_state <= 4'd8;
                end
            end
        end
        3'd4: begin
            if ((~litedramcore_sdram_bankmachine5_refresh_req)) begin
                litedramcore_bankmachine5_next_state <= 1'd0;
            end
        end
        3'd5: begin
            litedramcore_bankmachine5_next_state <= 3'd6;
        end
        3'd6: begin
            litedramcore_bankmachine5_next_state <= 3'd7;
        end
        3'd7: begin
            litedramcore_bankmachine5_next_state <= 2'd3;
        end
        4'd8: begin
            litedramcore_bankmachine5_next_state <= 4'd9;
        end
        4'd9: begin
            litedramcore_bankmachine5_next_state <= 4'd10;
        end
        4'd10: begin
            litedramcore_bankmachine5_next_state <= 1'd0;
        end
        default: begin
            if (litedramcore_sdram_bankmachine5_refresh_req) begin
                litedramcore_bankmachine5_next_state <= 3'd4;
            end else begin
                if (litedramcore_sdram_bankmachine5_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine5_row_opened) begin
                        if (litedramcore_sdram_bankmachine5_row_hit) begin
                            if ((litedramcore_sdram_bankmachine5_cmd_ready & litedramcore_sdram_bankmachine5_auto_precharge)) begin
                                litedramcore_bankmachine5_next_state <= 2'd2;
                            end
                        end else begin
                            litedramcore_bankmachine5_next_state <= 1'd1;
                        end
                    end else begin
                        litedramcore_bankmachine5_next_state <= 2'd3;
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine5_cmd_payload_ras <= 1'd0;
    case (litedramcore_bankmachine5_state)
        1'd1: begin
            if ((litedramcore_sdram_bankmachine5_twtpcon_ready & litedramcore_sdram_bankmachine5_trascon_ready)) begin
                litedramcore_sdram_bankmachine5_cmd_payload_ras <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
            if (litedramcore_sdram_bankmachine5_trccon_ready) begin
                litedramcore_sdram_bankmachine5_cmd_payload_ras <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine5_cmd_payload_we <= 1'd0;
    case (litedramcore_bankmachine5_state)
        1'd1: begin
            if ((litedramcore_sdram_bankmachine5_twtpcon_ready & litedramcore_sdram_bankmachine5_trascon_ready)) begin
                litedramcore_sdram_bankmachine5_cmd_payload_we <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine5_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine5_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine5_row_opened) begin
                        if (litedramcore_sdram_bankmachine5_row_hit) begin
                            if (litedramcore_sdram_bankmachine5_source_source_payload_we) begin
                                litedramcore_sdram_bankmachine5_cmd_payload_we <= 1'd1;
                            end else begin
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd0;
    case (litedramcore_bankmachine5_state)
        1'd1: begin
            if ((litedramcore_sdram_bankmachine5_twtpcon_ready & litedramcore_sdram_bankmachine5_trascon_ready)) begin
                litedramcore_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
            if (litedramcore_sdram_bankmachine5_trccon_ready) begin
                litedramcore_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd1;
            end
        end
        3'd4: begin
            litedramcore_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd1;
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine5_cmd_payload_is_read <= 1'd0;
    case (litedramcore_bankmachine5_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine5_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine5_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine5_row_opened) begin
                        if (litedramcore_sdram_bankmachine5_row_hit) begin
                            if (litedramcore_sdram_bankmachine5_source_source_payload_we) begin
                            end else begin
                                litedramcore_sdram_bankmachine5_cmd_payload_is_read <= 1'd1;
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine5_cmd_payload_is_write <= 1'd0;
    case (litedramcore_bankmachine5_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine5_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine5_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine5_row_opened) begin
                        if (litedramcore_sdram_bankmachine5_row_hit) begin
                            if (litedramcore_sdram_bankmachine5_source_source_payload_we) begin
                                litedramcore_sdram_bankmachine5_cmd_payload_is_write <= 1'd1;
                            end else begin
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine5_req_wdata_ready <= 1'd0;
    case (litedramcore_bankmachine5_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine5_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine5_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine5_row_opened) begin
                        if (litedramcore_sdram_bankmachine5_row_hit) begin
                            if (litedramcore_sdram_bankmachine5_source_source_payload_we) begin
                                litedramcore_sdram_bankmachine5_req_wdata_ready <= litedramcore_sdram_bankmachine5_cmd_ready;
                            end else begin
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine5_req_rdata_valid <= 1'd0;
    case (litedramcore_bankmachine5_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine5_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine5_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine5_row_opened) begin
                        if (litedramcore_sdram_bankmachine5_row_hit) begin
                            if (litedramcore_sdram_bankmachine5_source_source_payload_we) begin
                            end else begin
                                litedramcore_sdram_bankmachine5_req_rdata_valid <= litedramcore_sdram_bankmachine5_cmd_ready;
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine5_refresh_gnt <= 1'd0;
    case (litedramcore_bankmachine5_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
            if (litedramcore_sdram_bankmachine5_twtpcon_ready) begin
                litedramcore_sdram_bankmachine5_refresh_gnt <= 1'd1;
            end
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine5_row_open <= 1'd0;
    case (litedramcore_bankmachine5_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
            if (litedramcore_sdram_bankmachine5_trccon_ready) begin
                litedramcore_sdram_bankmachine5_row_open <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine5_cmd_valid <= 1'd0;
    case (litedramcore_bankmachine5_state)
        1'd1: begin
            if ((litedramcore_sdram_bankmachine5_twtpcon_ready & litedramcore_sdram_bankmachine5_trascon_ready)) begin
                litedramcore_sdram_bankmachine5_cmd_valid <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
            if (litedramcore_sdram_bankmachine5_trccon_ready) begin
                litedramcore_sdram_bankmachine5_cmd_valid <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine5_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine5_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine5_row_opened) begin
                        if (litedramcore_sdram_bankmachine5_row_hit) begin
                            litedramcore_sdram_bankmachine5_cmd_valid <= 1'd1;
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine5_row_close <= 1'd0;
    case (litedramcore_bankmachine5_state)
        1'd1: begin
            litedramcore_sdram_bankmachine5_row_close <= 1'd1;
        end
        2'd2: begin
            litedramcore_sdram_bankmachine5_row_close <= 1'd1;
        end
        2'd3: begin
        end
        3'd4: begin
            litedramcore_sdram_bankmachine5_row_close <= 1'd1;
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine5_row_col_n_addr_sel <= 1'd0;
    case (litedramcore_bankmachine5_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
            if (litedramcore_sdram_bankmachine5_trccon_ready) begin
                litedramcore_sdram_bankmachine5_row_col_n_addr_sel <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine5_cmd_payload_cas <= 1'd0;
    case (litedramcore_bankmachine5_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine5_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine5_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine5_row_opened) begin
                        if (litedramcore_sdram_bankmachine5_row_hit) begin
                            litedramcore_sdram_bankmachine5_cmd_payload_cas <= 1'd1;
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
assign litedramcore_sdram_bankmachine6_sink_valid = litedramcore_sdram_bankmachine6_req_valid;
assign litedramcore_sdram_bankmachine6_req_ready = litedramcore_sdram_bankmachine6_sink_ready;
assign litedramcore_sdram_bankmachine6_sink_payload_we = litedramcore_sdram_bankmachine6_req_we;
assign litedramcore_sdram_bankmachine6_sink_payload_addr = litedramcore_sdram_bankmachine6_req_addr;
assign litedramcore_sdram_bankmachine6_sink_sink_valid = litedramcore_sdram_bankmachine6_source_valid;
assign litedramcore_sdram_bankmachine6_source_ready = litedramcore_sdram_bankmachine6_sink_sink_ready;
assign litedramcore_sdram_bankmachine6_sink_sink_first = litedramcore_sdram_bankmachine6_source_first;
assign litedramcore_sdram_bankmachine6_sink_sink_last = litedramcore_sdram_bankmachine6_source_last;
assign litedramcore_sdram_bankmachine6_sink_sink_payload_we = litedramcore_sdram_bankmachine6_source_payload_we;
assign litedramcore_sdram_bankmachine6_sink_sink_payload_addr = litedramcore_sdram_bankmachine6_source_payload_addr;
assign litedramcore_sdram_bankmachine6_source_source_ready = (litedramcore_sdram_bankmachine6_req_wdata_ready | litedramcore_sdram_bankmachine6_req_rdata_valid);
assign litedramcore_sdram_bankmachine6_req_lock = (litedramcore_sdram_bankmachine6_source_valid | litedramcore_sdram_bankmachine6_source_source_valid);
assign litedramcore_sdram_bankmachine6_row_hit = (litedramcore_sdram_bankmachine6_row == litedramcore_sdram_bankmachine6_source_source_payload_addr[21:7]);
assign litedramcore_sdram_bankmachine6_cmd_payload_ba = 3'd6;
always @(*) begin
    litedramcore_sdram_bankmachine6_cmd_payload_a <= 15'd0;
    if (litedramcore_sdram_bankmachine6_row_col_n_addr_sel) begin
        litedramcore_sdram_bankmachine6_cmd_payload_a <= litedramcore_sdram_bankmachine6_source_source_payload_addr[21:7];
    end else begin
        litedramcore_sdram_bankmachine6_cmd_payload_a <= ((litedramcore_sdram_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_sdram_bankmachine6_source_source_payload_addr[6:0], {3{1'd0}}});
    end
end
assign litedramcore_sdram_bankmachine6_twtpcon_valid = ((litedramcore_sdram_bankmachine6_cmd_valid & litedramcore_sdram_bankmachine6_cmd_ready) & litedramcore_sdram_bankmachine6_cmd_payload_is_write);
assign litedramcore_sdram_bankmachine6_trccon_valid = ((litedramcore_sdram_bankmachine6_cmd_valid & litedramcore_sdram_bankmachine6_cmd_ready) & litedramcore_sdram_bankmachine6_row_open);
assign litedramcore_sdram_bankmachine6_trascon_valid = ((litedramcore_sdram_bankmachine6_cmd_valid & litedramcore_sdram_bankmachine6_cmd_ready) & litedramcore_sdram_bankmachine6_row_open);
always @(*) begin
    litedramcore_sdram_bankmachine6_auto_precharge <= 1'd0;
    if ((litedramcore_sdram_bankmachine6_source_valid & litedramcore_sdram_bankmachine6_source_source_valid)) begin
        if ((litedramcore_sdram_bankmachine6_source_payload_addr[21:7] != litedramcore_sdram_bankmachine6_source_source_payload_addr[21:7])) begin
            litedramcore_sdram_bankmachine6_auto_precharge <= (litedramcore_sdram_bankmachine6_row_close == 1'd0);
        end
    end
end
assign litedramcore_sdram_bankmachine6_syncfifo6_din = {litedramcore_sdram_bankmachine6_fifo_in_last, litedramcore_sdram_bankmachine6_fifo_in_first, litedramcore_sdram_bankmachine6_fifo_in_payload_addr, litedramcore_sdram_bankmachine6_fifo_in_payload_we};
assign {litedramcore_sdram_bankmachine6_fifo_out_last, litedramcore_sdram_bankmachine6_fifo_out_first, litedramcore_sdram_bankmachine6_fifo_out_payload_addr, litedramcore_sdram_bankmachine6_fifo_out_payload_we} = litedramcore_sdram_bankmachine6_syncfifo6_dout;
assign {litedramcore_sdram_bankmachine6_fifo_out_last, litedramcore_sdram_bankmachine6_fifo_out_first, litedramcore_sdram_bankmachine6_fifo_out_payload_addr, litedramcore_sdram_bankmachine6_fifo_out_payload_we} = litedramcore_sdram_bankmachine6_syncfifo6_dout;
assign {litedramcore_sdram_bankmachine6_fifo_out_last, litedramcore_sdram_bankmachine6_fifo_out_first, litedramcore_sdram_bankmachine6_fifo_out_payload_addr, litedramcore_sdram_bankmachine6_fifo_out_payload_we} = litedramcore_sdram_bankmachine6_syncfifo6_dout;
assign {litedramcore_sdram_bankmachine6_fifo_out_last, litedramcore_sdram_bankmachine6_fifo_out_first, litedramcore_sdram_bankmachine6_fifo_out_payload_addr, litedramcore_sdram_bankmachine6_fifo_out_payload_we} = litedramcore_sdram_bankmachine6_syncfifo6_dout;
assign litedramcore_sdram_bankmachine6_sink_ready = litedramcore_sdram_bankmachine6_syncfifo6_writable;
assign litedramcore_sdram_bankmachine6_syncfifo6_we = litedramcore_sdram_bankmachine6_sink_valid;
assign litedramcore_sdram_bankmachine6_fifo_in_first = litedramcore_sdram_bankmachine6_sink_first;
assign litedramcore_sdram_bankmachine6_fifo_in_last = litedramcore_sdram_bankmachine6_sink_last;
assign litedramcore_sdram_bankmachine6_fifo_in_payload_we = litedramcore_sdram_bankmachine6_sink_payload_we;
assign litedramcore_sdram_bankmachine6_fifo_in_payload_addr = litedramcore_sdram_bankmachine6_sink_payload_addr;
assign litedramcore_sdram_bankmachine6_source_valid = litedramcore_sdram_bankmachine6_syncfifo6_readable;
assign litedramcore_sdram_bankmachine6_source_first = litedramcore_sdram_bankmachine6_fifo_out_first;
assign litedramcore_sdram_bankmachine6_source_last = litedramcore_sdram_bankmachine6_fifo_out_last;
assign litedramcore_sdram_bankmachine6_source_payload_we = litedramcore_sdram_bankmachine6_fifo_out_payload_we;
assign litedramcore_sdram_bankmachine6_source_payload_addr = litedramcore_sdram_bankmachine6_fifo_out_payload_addr;
assign litedramcore_sdram_bankmachine6_syncfifo6_re = litedramcore_sdram_bankmachine6_source_ready;
always @(*) begin
    litedramcore_sdram_bankmachine6_wrport_adr <= 4'd0;
    if (litedramcore_sdram_bankmachine6_replace) begin
        litedramcore_sdram_bankmachine6_wrport_adr <= (litedramcore_sdram_bankmachine6_produce - 1'd1);
    end else begin
        litedramcore_sdram_bankmachine6_wrport_adr <= litedramcore_sdram_bankmachine6_produce;
    end
end
assign litedramcore_sdram_bankmachine6_wrport_dat_w = litedramcore_sdram_bankmachine6_syncfifo6_din;
assign litedramcore_sdram_bankmachine6_wrport_we = (litedramcore_sdram_bankmachine6_syncfifo6_we & (litedramcore_sdram_bankmachine6_syncfifo6_writable | litedramcore_sdram_bankmachine6_replace));
assign litedramcore_sdram_bankmachine6_do_read = (litedramcore_sdram_bankmachine6_syncfifo6_readable & litedramcore_sdram_bankmachine6_syncfifo6_re);
assign litedramcore_sdram_bankmachine6_rdport_adr = litedramcore_sdram_bankmachine6_consume;
assign litedramcore_sdram_bankmachine6_syncfifo6_dout = litedramcore_sdram_bankmachine6_rdport_dat_r;
assign litedramcore_sdram_bankmachine6_syncfifo6_writable = (litedramcore_sdram_bankmachine6_level != 5'd16);
assign litedramcore_sdram_bankmachine6_syncfifo6_readable = (litedramcore_sdram_bankmachine6_level != 1'd0);
assign litedramcore_sdram_bankmachine6_pipe_valid_sink_ready = ((~litedramcore_sdram_bankmachine6_pipe_valid_source_valid) | litedramcore_sdram_bankmachine6_pipe_valid_source_ready);
assign litedramcore_sdram_bankmachine6_pipe_valid_sink_valid = litedramcore_sdram_bankmachine6_sink_sink_valid;
assign litedramcore_sdram_bankmachine6_sink_sink_ready = litedramcore_sdram_bankmachine6_pipe_valid_sink_ready;
assign litedramcore_sdram_bankmachine6_pipe_valid_sink_first = litedramcore_sdram_bankmachine6_sink_sink_first;
assign litedramcore_sdram_bankmachine6_pipe_valid_sink_last = litedramcore_sdram_bankmachine6_sink_sink_last;
assign litedramcore_sdram_bankmachine6_pipe_valid_sink_payload_we = litedramcore_sdram_bankmachine6_sink_sink_payload_we;
assign litedramcore_sdram_bankmachine6_pipe_valid_sink_payload_addr = litedramcore_sdram_bankmachine6_sink_sink_payload_addr;
assign litedramcore_sdram_bankmachine6_source_source_valid = litedramcore_sdram_bankmachine6_pipe_valid_source_valid;
assign litedramcore_sdram_bankmachine6_pipe_valid_source_ready = litedramcore_sdram_bankmachine6_source_source_ready;
assign litedramcore_sdram_bankmachine6_source_source_first = litedramcore_sdram_bankmachine6_pipe_valid_source_first;
assign litedramcore_sdram_bankmachine6_source_source_last = litedramcore_sdram_bankmachine6_pipe_valid_source_last;
assign litedramcore_sdram_bankmachine6_source_source_payload_we = litedramcore_sdram_bankmachine6_pipe_valid_source_payload_we;
assign litedramcore_sdram_bankmachine6_source_source_payload_addr = litedramcore_sdram_bankmachine6_pipe_valid_source_payload_addr;
always @(*) begin
    litedramcore_bankmachine6_next_state <= 4'd0;
    litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state;
    case (litedramcore_bankmachine6_state)
        1'd1: begin
            if ((litedramcore_sdram_bankmachine6_twtpcon_ready & litedramcore_sdram_bankmachine6_trascon_ready)) begin
                if (litedramcore_sdram_bankmachine6_cmd_ready) begin
                    litedramcore_bankmachine6_next_state <= 3'd5;
                end
            end
        end
        2'd2: begin
            if ((litedramcore_sdram_bankmachine6_twtpcon_ready & litedramcore_sdram_bankmachine6_trascon_ready)) begin
                litedramcore_bankmachine6_next_state <= 3'd5;
            end
        end
        2'd3: begin
            if (litedramcore_sdram_bankmachine6_trccon_ready) begin
                if (litedramcore_sdram_bankmachine6_cmd_ready) begin
                    litedramcore_bankmachine6_next_state <= 4'd8;
                end
            end
        end
        3'd4: begin
            if ((~litedramcore_sdram_bankmachine6_refresh_req)) begin
                litedramcore_bankmachine6_next_state <= 1'd0;
            end
        end
        3'd5: begin
            litedramcore_bankmachine6_next_state <= 3'd6;
        end
        3'd6: begin
            litedramcore_bankmachine6_next_state <= 3'd7;
        end
        3'd7: begin
            litedramcore_bankmachine6_next_state <= 2'd3;
        end
        4'd8: begin
            litedramcore_bankmachine6_next_state <= 4'd9;
        end
        4'd9: begin
            litedramcore_bankmachine6_next_state <= 4'd10;
        end
        4'd10: begin
            litedramcore_bankmachine6_next_state <= 1'd0;
        end
        default: begin
            if (litedramcore_sdram_bankmachine6_refresh_req) begin
                litedramcore_bankmachine6_next_state <= 3'd4;
            end else begin
                if (litedramcore_sdram_bankmachine6_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine6_row_opened) begin
                        if (litedramcore_sdram_bankmachine6_row_hit) begin
                            if ((litedramcore_sdram_bankmachine6_cmd_ready & litedramcore_sdram_bankmachine6_auto_precharge)) begin
                                litedramcore_bankmachine6_next_state <= 2'd2;
                            end
                        end else begin
                            litedramcore_bankmachine6_next_state <= 1'd1;
                        end
                    end else begin
                        litedramcore_bankmachine6_next_state <= 2'd3;
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine6_cmd_payload_is_write <= 1'd0;
    case (litedramcore_bankmachine6_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine6_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine6_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine6_row_opened) begin
                        if (litedramcore_sdram_bankmachine6_row_hit) begin
                            if (litedramcore_sdram_bankmachine6_source_source_payload_we) begin
                                litedramcore_sdram_bankmachine6_cmd_payload_is_write <= 1'd1;
                            end else begin
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine6_req_wdata_ready <= 1'd0;
    case (litedramcore_bankmachine6_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine6_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine6_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine6_row_opened) begin
                        if (litedramcore_sdram_bankmachine6_row_hit) begin
                            if (litedramcore_sdram_bankmachine6_source_source_payload_we) begin
                                litedramcore_sdram_bankmachine6_req_wdata_ready <= litedramcore_sdram_bankmachine6_cmd_ready;
                            end else begin
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine6_req_rdata_valid <= 1'd0;
    case (litedramcore_bankmachine6_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine6_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine6_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine6_row_opened) begin
                        if (litedramcore_sdram_bankmachine6_row_hit) begin
                            if (litedramcore_sdram_bankmachine6_source_source_payload_we) begin
                            end else begin
                                litedramcore_sdram_bankmachine6_req_rdata_valid <= litedramcore_sdram_bankmachine6_cmd_ready;
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine6_refresh_gnt <= 1'd0;
    case (litedramcore_bankmachine6_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
            if (litedramcore_sdram_bankmachine6_twtpcon_ready) begin
                litedramcore_sdram_bankmachine6_refresh_gnt <= 1'd1;
            end
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine6_row_open <= 1'd0;
    case (litedramcore_bankmachine6_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
            if (litedramcore_sdram_bankmachine6_trccon_ready) begin
                litedramcore_sdram_bankmachine6_row_open <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine6_cmd_valid <= 1'd0;
    case (litedramcore_bankmachine6_state)
        1'd1: begin
            if ((litedramcore_sdram_bankmachine6_twtpcon_ready & litedramcore_sdram_bankmachine6_trascon_ready)) begin
                litedramcore_sdram_bankmachine6_cmd_valid <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
            if (litedramcore_sdram_bankmachine6_trccon_ready) begin
                litedramcore_sdram_bankmachine6_cmd_valid <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine6_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine6_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine6_row_opened) begin
                        if (litedramcore_sdram_bankmachine6_row_hit) begin
                            litedramcore_sdram_bankmachine6_cmd_valid <= 1'd1;
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine6_row_close <= 1'd0;
    case (litedramcore_bankmachine6_state)
        1'd1: begin
            litedramcore_sdram_bankmachine6_row_close <= 1'd1;
        end
        2'd2: begin
            litedramcore_sdram_bankmachine6_row_close <= 1'd1;
        end
        2'd3: begin
        end
        3'd4: begin
            litedramcore_sdram_bankmachine6_row_close <= 1'd1;
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine6_row_col_n_addr_sel <= 1'd0;
    case (litedramcore_bankmachine6_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
            if (litedramcore_sdram_bankmachine6_trccon_ready) begin
                litedramcore_sdram_bankmachine6_row_col_n_addr_sel <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine6_cmd_payload_cas <= 1'd0;
    case (litedramcore_bankmachine6_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine6_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine6_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine6_row_opened) begin
                        if (litedramcore_sdram_bankmachine6_row_hit) begin
                            litedramcore_sdram_bankmachine6_cmd_payload_cas <= 1'd1;
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine6_cmd_payload_ras <= 1'd0;
    case (litedramcore_bankmachine6_state)
        1'd1: begin
            if ((litedramcore_sdram_bankmachine6_twtpcon_ready & litedramcore_sdram_bankmachine6_trascon_ready)) begin
                litedramcore_sdram_bankmachine6_cmd_payload_ras <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
            if (litedramcore_sdram_bankmachine6_trccon_ready) begin
                litedramcore_sdram_bankmachine6_cmd_payload_ras <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine6_cmd_payload_we <= 1'd0;
    case (litedramcore_bankmachine6_state)
        1'd1: begin
            if ((litedramcore_sdram_bankmachine6_twtpcon_ready & litedramcore_sdram_bankmachine6_trascon_ready)) begin
                litedramcore_sdram_bankmachine6_cmd_payload_we <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine6_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine6_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine6_row_opened) begin
                        if (litedramcore_sdram_bankmachine6_row_hit) begin
                            if (litedramcore_sdram_bankmachine6_source_source_payload_we) begin
                                litedramcore_sdram_bankmachine6_cmd_payload_we <= 1'd1;
                            end else begin
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd0;
    case (litedramcore_bankmachine6_state)
        1'd1: begin
            if ((litedramcore_sdram_bankmachine6_twtpcon_ready & litedramcore_sdram_bankmachine6_trascon_ready)) begin
                litedramcore_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
            if (litedramcore_sdram_bankmachine6_trccon_ready) begin
                litedramcore_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd1;
            end
        end
        3'd4: begin
            litedramcore_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd1;
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine6_cmd_payload_is_read <= 1'd0;
    case (litedramcore_bankmachine6_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine6_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine6_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine6_row_opened) begin
                        if (litedramcore_sdram_bankmachine6_row_hit) begin
                            if (litedramcore_sdram_bankmachine6_source_source_payload_we) begin
                            end else begin
                                litedramcore_sdram_bankmachine6_cmd_payload_is_read <= 1'd1;
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
assign litedramcore_sdram_bankmachine7_sink_valid = litedramcore_sdram_bankmachine7_req_valid;
assign litedramcore_sdram_bankmachine7_req_ready = litedramcore_sdram_bankmachine7_sink_ready;
assign litedramcore_sdram_bankmachine7_sink_payload_we = litedramcore_sdram_bankmachine7_req_we;
assign litedramcore_sdram_bankmachine7_sink_payload_addr = litedramcore_sdram_bankmachine7_req_addr;
assign litedramcore_sdram_bankmachine7_sink_sink_valid = litedramcore_sdram_bankmachine7_source_valid;
assign litedramcore_sdram_bankmachine7_source_ready = litedramcore_sdram_bankmachine7_sink_sink_ready;
assign litedramcore_sdram_bankmachine7_sink_sink_first = litedramcore_sdram_bankmachine7_source_first;
assign litedramcore_sdram_bankmachine7_sink_sink_last = litedramcore_sdram_bankmachine7_source_last;
assign litedramcore_sdram_bankmachine7_sink_sink_payload_we = litedramcore_sdram_bankmachine7_source_payload_we;
assign litedramcore_sdram_bankmachine7_sink_sink_payload_addr = litedramcore_sdram_bankmachine7_source_payload_addr;
assign litedramcore_sdram_bankmachine7_source_source_ready = (litedramcore_sdram_bankmachine7_req_wdata_ready | litedramcore_sdram_bankmachine7_req_rdata_valid);
assign litedramcore_sdram_bankmachine7_req_lock = (litedramcore_sdram_bankmachine7_source_valid | litedramcore_sdram_bankmachine7_source_source_valid);
assign litedramcore_sdram_bankmachine7_row_hit = (litedramcore_sdram_bankmachine7_row == litedramcore_sdram_bankmachine7_source_source_payload_addr[21:7]);
assign litedramcore_sdram_bankmachine7_cmd_payload_ba = 3'd7;
always @(*) begin
    litedramcore_sdram_bankmachine7_cmd_payload_a <= 15'd0;
    if (litedramcore_sdram_bankmachine7_row_col_n_addr_sel) begin
        litedramcore_sdram_bankmachine7_cmd_payload_a <= litedramcore_sdram_bankmachine7_source_source_payload_addr[21:7];
    end else begin
        litedramcore_sdram_bankmachine7_cmd_payload_a <= ((litedramcore_sdram_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_sdram_bankmachine7_source_source_payload_addr[6:0], {3{1'd0}}});
    end
end
assign litedramcore_sdram_bankmachine7_twtpcon_valid = ((litedramcore_sdram_bankmachine7_cmd_valid & litedramcore_sdram_bankmachine7_cmd_ready) & litedramcore_sdram_bankmachine7_cmd_payload_is_write);
assign litedramcore_sdram_bankmachine7_trccon_valid = ((litedramcore_sdram_bankmachine7_cmd_valid & litedramcore_sdram_bankmachine7_cmd_ready) & litedramcore_sdram_bankmachine7_row_open);
assign litedramcore_sdram_bankmachine7_trascon_valid = ((litedramcore_sdram_bankmachine7_cmd_valid & litedramcore_sdram_bankmachine7_cmd_ready) & litedramcore_sdram_bankmachine7_row_open);
always @(*) begin
    litedramcore_sdram_bankmachine7_auto_precharge <= 1'd0;
    if ((litedramcore_sdram_bankmachine7_source_valid & litedramcore_sdram_bankmachine7_source_source_valid)) begin
        if ((litedramcore_sdram_bankmachine7_source_payload_addr[21:7] != litedramcore_sdram_bankmachine7_source_source_payload_addr[21:7])) begin
            litedramcore_sdram_bankmachine7_auto_precharge <= (litedramcore_sdram_bankmachine7_row_close == 1'd0);
        end
    end
end
assign litedramcore_sdram_bankmachine7_syncfifo7_din = {litedramcore_sdram_bankmachine7_fifo_in_last, litedramcore_sdram_bankmachine7_fifo_in_first, litedramcore_sdram_bankmachine7_fifo_in_payload_addr, litedramcore_sdram_bankmachine7_fifo_in_payload_we};
assign {litedramcore_sdram_bankmachine7_fifo_out_last, litedramcore_sdram_bankmachine7_fifo_out_first, litedramcore_sdram_bankmachine7_fifo_out_payload_addr, litedramcore_sdram_bankmachine7_fifo_out_payload_we} = litedramcore_sdram_bankmachine7_syncfifo7_dout;
assign {litedramcore_sdram_bankmachine7_fifo_out_last, litedramcore_sdram_bankmachine7_fifo_out_first, litedramcore_sdram_bankmachine7_fifo_out_payload_addr, litedramcore_sdram_bankmachine7_fifo_out_payload_we} = litedramcore_sdram_bankmachine7_syncfifo7_dout;
assign {litedramcore_sdram_bankmachine7_fifo_out_last, litedramcore_sdram_bankmachine7_fifo_out_first, litedramcore_sdram_bankmachine7_fifo_out_payload_addr, litedramcore_sdram_bankmachine7_fifo_out_payload_we} = litedramcore_sdram_bankmachine7_syncfifo7_dout;
assign {litedramcore_sdram_bankmachine7_fifo_out_last, litedramcore_sdram_bankmachine7_fifo_out_first, litedramcore_sdram_bankmachine7_fifo_out_payload_addr, litedramcore_sdram_bankmachine7_fifo_out_payload_we} = litedramcore_sdram_bankmachine7_syncfifo7_dout;
assign litedramcore_sdram_bankmachine7_sink_ready = litedramcore_sdram_bankmachine7_syncfifo7_writable;
assign litedramcore_sdram_bankmachine7_syncfifo7_we = litedramcore_sdram_bankmachine7_sink_valid;
assign litedramcore_sdram_bankmachine7_fifo_in_first = litedramcore_sdram_bankmachine7_sink_first;
assign litedramcore_sdram_bankmachine7_fifo_in_last = litedramcore_sdram_bankmachine7_sink_last;
assign litedramcore_sdram_bankmachine7_fifo_in_payload_we = litedramcore_sdram_bankmachine7_sink_payload_we;
assign litedramcore_sdram_bankmachine7_fifo_in_payload_addr = litedramcore_sdram_bankmachine7_sink_payload_addr;
assign litedramcore_sdram_bankmachine7_source_valid = litedramcore_sdram_bankmachine7_syncfifo7_readable;
assign litedramcore_sdram_bankmachine7_source_first = litedramcore_sdram_bankmachine7_fifo_out_first;
assign litedramcore_sdram_bankmachine7_source_last = litedramcore_sdram_bankmachine7_fifo_out_last;
assign litedramcore_sdram_bankmachine7_source_payload_we = litedramcore_sdram_bankmachine7_fifo_out_payload_we;
assign litedramcore_sdram_bankmachine7_source_payload_addr = litedramcore_sdram_bankmachine7_fifo_out_payload_addr;
assign litedramcore_sdram_bankmachine7_syncfifo7_re = litedramcore_sdram_bankmachine7_source_ready;
always @(*) begin
    litedramcore_sdram_bankmachine7_wrport_adr <= 4'd0;
    if (litedramcore_sdram_bankmachine7_replace) begin
        litedramcore_sdram_bankmachine7_wrport_adr <= (litedramcore_sdram_bankmachine7_produce - 1'd1);
    end else begin
        litedramcore_sdram_bankmachine7_wrport_adr <= litedramcore_sdram_bankmachine7_produce;
    end
end
assign litedramcore_sdram_bankmachine7_wrport_dat_w = litedramcore_sdram_bankmachine7_syncfifo7_din;
assign litedramcore_sdram_bankmachine7_wrport_we = (litedramcore_sdram_bankmachine7_syncfifo7_we & (litedramcore_sdram_bankmachine7_syncfifo7_writable | litedramcore_sdram_bankmachine7_replace));
assign litedramcore_sdram_bankmachine7_do_read = (litedramcore_sdram_bankmachine7_syncfifo7_readable & litedramcore_sdram_bankmachine7_syncfifo7_re);
assign litedramcore_sdram_bankmachine7_rdport_adr = litedramcore_sdram_bankmachine7_consume;
assign litedramcore_sdram_bankmachine7_syncfifo7_dout = litedramcore_sdram_bankmachine7_rdport_dat_r;
assign litedramcore_sdram_bankmachine7_syncfifo7_writable = (litedramcore_sdram_bankmachine7_level != 5'd16);
assign litedramcore_sdram_bankmachine7_syncfifo7_readable = (litedramcore_sdram_bankmachine7_level != 1'd0);
assign litedramcore_sdram_bankmachine7_pipe_valid_sink_ready = ((~litedramcore_sdram_bankmachine7_pipe_valid_source_valid) | litedramcore_sdram_bankmachine7_pipe_valid_source_ready);
assign litedramcore_sdram_bankmachine7_pipe_valid_sink_valid = litedramcore_sdram_bankmachine7_sink_sink_valid;
assign litedramcore_sdram_bankmachine7_sink_sink_ready = litedramcore_sdram_bankmachine7_pipe_valid_sink_ready;
assign litedramcore_sdram_bankmachine7_pipe_valid_sink_first = litedramcore_sdram_bankmachine7_sink_sink_first;
assign litedramcore_sdram_bankmachine7_pipe_valid_sink_last = litedramcore_sdram_bankmachine7_sink_sink_last;
assign litedramcore_sdram_bankmachine7_pipe_valid_sink_payload_we = litedramcore_sdram_bankmachine7_sink_sink_payload_we;
assign litedramcore_sdram_bankmachine7_pipe_valid_sink_payload_addr = litedramcore_sdram_bankmachine7_sink_sink_payload_addr;
assign litedramcore_sdram_bankmachine7_source_source_valid = litedramcore_sdram_bankmachine7_pipe_valid_source_valid;
assign litedramcore_sdram_bankmachine7_pipe_valid_source_ready = litedramcore_sdram_bankmachine7_source_source_ready;
assign litedramcore_sdram_bankmachine7_source_source_first = litedramcore_sdram_bankmachine7_pipe_valid_source_first;
assign litedramcore_sdram_bankmachine7_source_source_last = litedramcore_sdram_bankmachine7_pipe_valid_source_last;
assign litedramcore_sdram_bankmachine7_source_source_payload_we = litedramcore_sdram_bankmachine7_pipe_valid_source_payload_we;
assign litedramcore_sdram_bankmachine7_source_source_payload_addr = litedramcore_sdram_bankmachine7_pipe_valid_source_payload_addr;
always @(*) begin
    litedramcore_bankmachine7_next_state <= 4'd0;
    litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state;
    case (litedramcore_bankmachine7_state)
        1'd1: begin
            if ((litedramcore_sdram_bankmachine7_twtpcon_ready & litedramcore_sdram_bankmachine7_trascon_ready)) begin
                if (litedramcore_sdram_bankmachine7_cmd_ready) begin
                    litedramcore_bankmachine7_next_state <= 3'd5;
                end
            end
        end
        2'd2: begin
            if ((litedramcore_sdram_bankmachine7_twtpcon_ready & litedramcore_sdram_bankmachine7_trascon_ready)) begin
                litedramcore_bankmachine7_next_state <= 3'd5;
            end
        end
        2'd3: begin
            if (litedramcore_sdram_bankmachine7_trccon_ready) begin
                if (litedramcore_sdram_bankmachine7_cmd_ready) begin
                    litedramcore_bankmachine7_next_state <= 4'd8;
                end
            end
        end
        3'd4: begin
            if ((~litedramcore_sdram_bankmachine7_refresh_req)) begin
                litedramcore_bankmachine7_next_state <= 1'd0;
            end
        end
        3'd5: begin
            litedramcore_bankmachine7_next_state <= 3'd6;
        end
        3'd6: begin
            litedramcore_bankmachine7_next_state <= 3'd7;
        end
        3'd7: begin
            litedramcore_bankmachine7_next_state <= 2'd3;
        end
        4'd8: begin
            litedramcore_bankmachine7_next_state <= 4'd9;
        end
        4'd9: begin
            litedramcore_bankmachine7_next_state <= 4'd10;
        end
        4'd10: begin
            litedramcore_bankmachine7_next_state <= 1'd0;
        end
        default: begin
            if (litedramcore_sdram_bankmachine7_refresh_req) begin
                litedramcore_bankmachine7_next_state <= 3'd4;
            end else begin
                if (litedramcore_sdram_bankmachine7_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine7_row_opened) begin
                        if (litedramcore_sdram_bankmachine7_row_hit) begin
                            if ((litedramcore_sdram_bankmachine7_cmd_ready & litedramcore_sdram_bankmachine7_auto_precharge)) begin
                                litedramcore_bankmachine7_next_state <= 2'd2;
                            end
                        end else begin
                            litedramcore_bankmachine7_next_state <= 1'd1;
                        end
                    end else begin
                        litedramcore_bankmachine7_next_state <= 2'd3;
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine7_refresh_gnt <= 1'd0;
    case (litedramcore_bankmachine7_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
            if (litedramcore_sdram_bankmachine7_twtpcon_ready) begin
                litedramcore_sdram_bankmachine7_refresh_gnt <= 1'd1;
            end
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine7_row_open <= 1'd0;
    case (litedramcore_bankmachine7_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
            if (litedramcore_sdram_bankmachine7_trccon_ready) begin
                litedramcore_sdram_bankmachine7_row_open <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine7_cmd_valid <= 1'd0;
    case (litedramcore_bankmachine7_state)
        1'd1: begin
            if ((litedramcore_sdram_bankmachine7_twtpcon_ready & litedramcore_sdram_bankmachine7_trascon_ready)) begin
                litedramcore_sdram_bankmachine7_cmd_valid <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
            if (litedramcore_sdram_bankmachine7_trccon_ready) begin
                litedramcore_sdram_bankmachine7_cmd_valid <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine7_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine7_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine7_row_opened) begin
                        if (litedramcore_sdram_bankmachine7_row_hit) begin
                            litedramcore_sdram_bankmachine7_cmd_valid <= 1'd1;
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine7_row_close <= 1'd0;
    case (litedramcore_bankmachine7_state)
        1'd1: begin
            litedramcore_sdram_bankmachine7_row_close <= 1'd1;
        end
        2'd2: begin
            litedramcore_sdram_bankmachine7_row_close <= 1'd1;
        end
        2'd3: begin
        end
        3'd4: begin
            litedramcore_sdram_bankmachine7_row_close <= 1'd1;
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine7_row_col_n_addr_sel <= 1'd0;
    case (litedramcore_bankmachine7_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
            if (litedramcore_sdram_bankmachine7_trccon_ready) begin
                litedramcore_sdram_bankmachine7_row_col_n_addr_sel <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine7_cmd_payload_cas <= 1'd0;
    case (litedramcore_bankmachine7_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine7_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine7_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine7_row_opened) begin
                        if (litedramcore_sdram_bankmachine7_row_hit) begin
                            litedramcore_sdram_bankmachine7_cmd_payload_cas <= 1'd1;
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine7_cmd_payload_ras <= 1'd0;
    case (litedramcore_bankmachine7_state)
        1'd1: begin
            if ((litedramcore_sdram_bankmachine7_twtpcon_ready & litedramcore_sdram_bankmachine7_trascon_ready)) begin
                litedramcore_sdram_bankmachine7_cmd_payload_ras <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
            if (litedramcore_sdram_bankmachine7_trccon_ready) begin
                litedramcore_sdram_bankmachine7_cmd_payload_ras <= 1'd1;
            end
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine7_cmd_payload_we <= 1'd0;
    case (litedramcore_bankmachine7_state)
        1'd1: begin
            if ((litedramcore_sdram_bankmachine7_twtpcon_ready & litedramcore_sdram_bankmachine7_trascon_ready)) begin
                litedramcore_sdram_bankmachine7_cmd_payload_we <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine7_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine7_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine7_row_opened) begin
                        if (litedramcore_sdram_bankmachine7_row_hit) begin
                            if (litedramcore_sdram_bankmachine7_source_source_payload_we) begin
                                litedramcore_sdram_bankmachine7_cmd_payload_we <= 1'd1;
                            end else begin
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd0;
    case (litedramcore_bankmachine7_state)
        1'd1: begin
            if ((litedramcore_sdram_bankmachine7_twtpcon_ready & litedramcore_sdram_bankmachine7_trascon_ready)) begin
                litedramcore_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
            if (litedramcore_sdram_bankmachine7_trccon_ready) begin
                litedramcore_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd1;
            end
        end
        3'd4: begin
            litedramcore_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd1;
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine7_cmd_payload_is_read <= 1'd0;
    case (litedramcore_bankmachine7_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine7_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine7_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine7_row_opened) begin
                        if (litedramcore_sdram_bankmachine7_row_hit) begin
                            if (litedramcore_sdram_bankmachine7_source_source_payload_we) begin
                            end else begin
                                litedramcore_sdram_bankmachine7_cmd_payload_is_read <= 1'd1;
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine7_cmd_payload_is_write <= 1'd0;
    case (litedramcore_bankmachine7_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine7_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine7_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine7_row_opened) begin
                        if (litedramcore_sdram_bankmachine7_row_hit) begin
                            if (litedramcore_sdram_bankmachine7_source_source_payload_we) begin
                                litedramcore_sdram_bankmachine7_cmd_payload_is_write <= 1'd1;
                            end else begin
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine7_req_wdata_ready <= 1'd0;
    case (litedramcore_bankmachine7_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine7_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine7_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine7_row_opened) begin
                        if (litedramcore_sdram_bankmachine7_row_hit) begin
                            if (litedramcore_sdram_bankmachine7_source_source_payload_we) begin
                                litedramcore_sdram_bankmachine7_req_wdata_ready <= litedramcore_sdram_bankmachine7_cmd_ready;
                            end else begin
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_bankmachine7_req_rdata_valid <= 1'd0;
    case (litedramcore_bankmachine7_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        default: begin
            if (litedramcore_sdram_bankmachine7_refresh_req) begin
            end else begin
                if (litedramcore_sdram_bankmachine7_source_source_valid) begin
                    if (litedramcore_sdram_bankmachine7_row_opened) begin
                        if (litedramcore_sdram_bankmachine7_row_hit) begin
                            if (litedramcore_sdram_bankmachine7_source_source_payload_we) begin
                            end else begin
                                litedramcore_sdram_bankmachine7_req_rdata_valid <= litedramcore_sdram_bankmachine7_cmd_ready;
                            end
                        end else begin
                        end
                    end else begin
                    end
                end
            end
        end
    endcase
end
assign litedramcore_sdram_nphases = (k7ddrphy_rdphase_storage - 1'd1);
assign litedramcore_sdram_rdphase = (k7ddrphy_wrphase_storage - 1'd1);
assign litedramcore_sdram_trrdcon_valid = ((litedramcore_sdram_choose_cmd_cmd_valid & litedramcore_sdram_choose_cmd_cmd_ready) & ((litedramcore_sdram_choose_cmd_cmd_payload_ras & (~litedramcore_sdram_choose_cmd_cmd_payload_cas)) & (~litedramcore_sdram_choose_cmd_cmd_payload_we)));
assign litedramcore_sdram_tfawcon_valid = ((litedramcore_sdram_choose_cmd_cmd_valid & litedramcore_sdram_choose_cmd_cmd_ready) & ((litedramcore_sdram_choose_cmd_cmd_payload_ras & (~litedramcore_sdram_choose_cmd_cmd_payload_cas)) & (~litedramcore_sdram_choose_cmd_cmd_payload_we)));
assign litedramcore_sdram_ras_allowed = (litedramcore_sdram_trrdcon_ready & litedramcore_sdram_tfawcon_ready);
assign litedramcore_sdram_tccdcon_valid = ((litedramcore_sdram_choose_req_cmd_valid & litedramcore_sdram_choose_req_cmd_ready) & (litedramcore_sdram_choose_req_cmd_payload_is_write | litedramcore_sdram_choose_req_cmd_payload_is_read));
assign litedramcore_sdram_cas_allowed = litedramcore_sdram_tccdcon_ready;
assign litedramcore_sdram_twtrcon_valid = ((litedramcore_sdram_choose_req_cmd_valid & litedramcore_sdram_choose_req_cmd_ready) & litedramcore_sdram_choose_req_cmd_payload_is_write);
assign litedramcore_sdram_read_available = ((((((((litedramcore_sdram_bankmachine0_cmd_valid & litedramcore_sdram_bankmachine0_cmd_payload_is_read) | (litedramcore_sdram_bankmachine1_cmd_valid & litedramcore_sdram_bankmachine1_cmd_payload_is_read)) | (litedramcore_sdram_bankmachine2_cmd_valid & litedramcore_sdram_bankmachine2_cmd_payload_is_read)) | (litedramcore_sdram_bankmachine3_cmd_valid & litedramcore_sdram_bankmachine3_cmd_payload_is_read)) | (litedramcore_sdram_bankmachine4_cmd_valid & litedramcore_sdram_bankmachine4_cmd_payload_is_read)) | (litedramcore_sdram_bankmachine5_cmd_valid & litedramcore_sdram_bankmachine5_cmd_payload_is_read)) | (litedramcore_sdram_bankmachine6_cmd_valid & litedramcore_sdram_bankmachine6_cmd_payload_is_read)) | (litedramcore_sdram_bankmachine7_cmd_valid & litedramcore_sdram_bankmachine7_cmd_payload_is_read));
assign litedramcore_sdram_write_available = ((((((((litedramcore_sdram_bankmachine0_cmd_valid & litedramcore_sdram_bankmachine0_cmd_payload_is_write) | (litedramcore_sdram_bankmachine1_cmd_valid & litedramcore_sdram_bankmachine1_cmd_payload_is_write)) | (litedramcore_sdram_bankmachine2_cmd_valid & litedramcore_sdram_bankmachine2_cmd_payload_is_write)) | (litedramcore_sdram_bankmachine3_cmd_valid & litedramcore_sdram_bankmachine3_cmd_payload_is_write)) | (litedramcore_sdram_bankmachine4_cmd_valid & litedramcore_sdram_bankmachine4_cmd_payload_is_write)) | (litedramcore_sdram_bankmachine5_cmd_valid & litedramcore_sdram_bankmachine5_cmd_payload_is_write)) | (litedramcore_sdram_bankmachine6_cmd_valid & litedramcore_sdram_bankmachine6_cmd_payload_is_write)) | (litedramcore_sdram_bankmachine7_cmd_valid & litedramcore_sdram_bankmachine7_cmd_payload_is_write));
assign litedramcore_sdram_max_time0 = (litedramcore_sdram_time0 == 1'd0);
assign litedramcore_sdram_max_time1 = (litedramcore_sdram_time1 == 1'd0);
assign litedramcore_sdram_bankmachine0_refresh_req = litedramcore_sdram_cmd_valid;
assign litedramcore_sdram_bankmachine1_refresh_req = litedramcore_sdram_cmd_valid;
assign litedramcore_sdram_bankmachine2_refresh_req = litedramcore_sdram_cmd_valid;
assign litedramcore_sdram_bankmachine3_refresh_req = litedramcore_sdram_cmd_valid;
assign litedramcore_sdram_bankmachine4_refresh_req = litedramcore_sdram_cmd_valid;
assign litedramcore_sdram_bankmachine5_refresh_req = litedramcore_sdram_cmd_valid;
assign litedramcore_sdram_bankmachine6_refresh_req = litedramcore_sdram_cmd_valid;
assign litedramcore_sdram_bankmachine7_refresh_req = litedramcore_sdram_cmd_valid;
assign litedramcore_sdram_go_to_refresh = (((((((litedramcore_sdram_bankmachine0_refresh_gnt & litedramcore_sdram_bankmachine1_refresh_gnt) & litedramcore_sdram_bankmachine2_refresh_gnt) & litedramcore_sdram_bankmachine3_refresh_gnt) & litedramcore_sdram_bankmachine4_refresh_gnt) & litedramcore_sdram_bankmachine5_refresh_gnt) & litedramcore_sdram_bankmachine6_refresh_gnt) & litedramcore_sdram_bankmachine7_refresh_gnt);
assign litedramcore_sdram_interface_rdata = {litedramcore_sdram_dfi_p3_rddata, litedramcore_sdram_dfi_p2_rddata, litedramcore_sdram_dfi_p1_rddata, litedramcore_sdram_dfi_p0_rddata};
assign {litedramcore_sdram_dfi_p3_wrdata, litedramcore_sdram_dfi_p2_wrdata, litedramcore_sdram_dfi_p1_wrdata, litedramcore_sdram_dfi_p0_wrdata} = litedramcore_sdram_interface_wdata;
assign {litedramcore_sdram_dfi_p3_wrdata, litedramcore_sdram_dfi_p2_wrdata, litedramcore_sdram_dfi_p1_wrdata, litedramcore_sdram_dfi_p0_wrdata} = litedramcore_sdram_interface_wdata;
assign {litedramcore_sdram_dfi_p3_wrdata, litedramcore_sdram_dfi_p2_wrdata, litedramcore_sdram_dfi_p1_wrdata, litedramcore_sdram_dfi_p0_wrdata} = litedramcore_sdram_interface_wdata;
assign {litedramcore_sdram_dfi_p3_wrdata, litedramcore_sdram_dfi_p2_wrdata, litedramcore_sdram_dfi_p1_wrdata, litedramcore_sdram_dfi_p0_wrdata} = litedramcore_sdram_interface_wdata;
assign {litedramcore_sdram_dfi_p3_wrdata_mask, litedramcore_sdram_dfi_p2_wrdata_mask, litedramcore_sdram_dfi_p1_wrdata_mask, litedramcore_sdram_dfi_p0_wrdata_mask} = (~litedramcore_sdram_interface_wdata_we);
assign {litedramcore_sdram_dfi_p3_wrdata_mask, litedramcore_sdram_dfi_p2_wrdata_mask, litedramcore_sdram_dfi_p1_wrdata_mask, litedramcore_sdram_dfi_p0_wrdata_mask} = (~litedramcore_sdram_interface_wdata_we);
assign {litedramcore_sdram_dfi_p3_wrdata_mask, litedramcore_sdram_dfi_p2_wrdata_mask, litedramcore_sdram_dfi_p1_wrdata_mask, litedramcore_sdram_dfi_p0_wrdata_mask} = (~litedramcore_sdram_interface_wdata_we);
assign {litedramcore_sdram_dfi_p3_wrdata_mask, litedramcore_sdram_dfi_p2_wrdata_mask, litedramcore_sdram_dfi_p1_wrdata_mask, litedramcore_sdram_dfi_p0_wrdata_mask} = (~litedramcore_sdram_interface_wdata_we);
always @(*) begin
    litedramcore_sdram_choose_cmd_valids <= 8'd0;
    litedramcore_sdram_choose_cmd_valids[0] <= (litedramcore_sdram_bankmachine0_cmd_valid & (((litedramcore_sdram_bankmachine0_cmd_payload_is_cmd & litedramcore_sdram_choose_cmd_want_cmds) & ((~((litedramcore_sdram_bankmachine0_cmd_payload_ras & (~litedramcore_sdram_bankmachine0_cmd_payload_cas)) & (~litedramcore_sdram_bankmachine0_cmd_payload_we))) | litedramcore_sdram_choose_cmd_want_activates)) | ((litedramcore_sdram_bankmachine0_cmd_payload_is_read == litedramcore_sdram_choose_cmd_want_reads) & (litedramcore_sdram_bankmachine0_cmd_payload_is_write == litedramcore_sdram_choose_cmd_want_writes))));
    litedramcore_sdram_choose_cmd_valids[1] <= (litedramcore_sdram_bankmachine1_cmd_valid & (((litedramcore_sdram_bankmachine1_cmd_payload_is_cmd & litedramcore_sdram_choose_cmd_want_cmds) & ((~((litedramcore_sdram_bankmachine1_cmd_payload_ras & (~litedramcore_sdram_bankmachine1_cmd_payload_cas)) & (~litedramcore_sdram_bankmachine1_cmd_payload_we))) | litedramcore_sdram_choose_cmd_want_activates)) | ((litedramcore_sdram_bankmachine1_cmd_payload_is_read == litedramcore_sdram_choose_cmd_want_reads) & (litedramcore_sdram_bankmachine1_cmd_payload_is_write == litedramcore_sdram_choose_cmd_want_writes))));
    litedramcore_sdram_choose_cmd_valids[2] <= (litedramcore_sdram_bankmachine2_cmd_valid & (((litedramcore_sdram_bankmachine2_cmd_payload_is_cmd & litedramcore_sdram_choose_cmd_want_cmds) & ((~((litedramcore_sdram_bankmachine2_cmd_payload_ras & (~litedramcore_sdram_bankmachine2_cmd_payload_cas)) & (~litedramcore_sdram_bankmachine2_cmd_payload_we))) | litedramcore_sdram_choose_cmd_want_activates)) | ((litedramcore_sdram_bankmachine2_cmd_payload_is_read == litedramcore_sdram_choose_cmd_want_reads) & (litedramcore_sdram_bankmachine2_cmd_payload_is_write == litedramcore_sdram_choose_cmd_want_writes))));
    litedramcore_sdram_choose_cmd_valids[3] <= (litedramcore_sdram_bankmachine3_cmd_valid & (((litedramcore_sdram_bankmachine3_cmd_payload_is_cmd & litedramcore_sdram_choose_cmd_want_cmds) & ((~((litedramcore_sdram_bankmachine3_cmd_payload_ras & (~litedramcore_sdram_bankmachine3_cmd_payload_cas)) & (~litedramcore_sdram_bankmachine3_cmd_payload_we))) | litedramcore_sdram_choose_cmd_want_activates)) | ((litedramcore_sdram_bankmachine3_cmd_payload_is_read == litedramcore_sdram_choose_cmd_want_reads) & (litedramcore_sdram_bankmachine3_cmd_payload_is_write == litedramcore_sdram_choose_cmd_want_writes))));
    litedramcore_sdram_choose_cmd_valids[4] <= (litedramcore_sdram_bankmachine4_cmd_valid & (((litedramcore_sdram_bankmachine4_cmd_payload_is_cmd & litedramcore_sdram_choose_cmd_want_cmds) & ((~((litedramcore_sdram_bankmachine4_cmd_payload_ras & (~litedramcore_sdram_bankmachine4_cmd_payload_cas)) & (~litedramcore_sdram_bankmachine4_cmd_payload_we))) | litedramcore_sdram_choose_cmd_want_activates)) | ((litedramcore_sdram_bankmachine4_cmd_payload_is_read == litedramcore_sdram_choose_cmd_want_reads) & (litedramcore_sdram_bankmachine4_cmd_payload_is_write == litedramcore_sdram_choose_cmd_want_writes))));
    litedramcore_sdram_choose_cmd_valids[5] <= (litedramcore_sdram_bankmachine5_cmd_valid & (((litedramcore_sdram_bankmachine5_cmd_payload_is_cmd & litedramcore_sdram_choose_cmd_want_cmds) & ((~((litedramcore_sdram_bankmachine5_cmd_payload_ras & (~litedramcore_sdram_bankmachine5_cmd_payload_cas)) & (~litedramcore_sdram_bankmachine5_cmd_payload_we))) | litedramcore_sdram_choose_cmd_want_activates)) | ((litedramcore_sdram_bankmachine5_cmd_payload_is_read == litedramcore_sdram_choose_cmd_want_reads) & (litedramcore_sdram_bankmachine5_cmd_payload_is_write == litedramcore_sdram_choose_cmd_want_writes))));
    litedramcore_sdram_choose_cmd_valids[6] <= (litedramcore_sdram_bankmachine6_cmd_valid & (((litedramcore_sdram_bankmachine6_cmd_payload_is_cmd & litedramcore_sdram_choose_cmd_want_cmds) & ((~((litedramcore_sdram_bankmachine6_cmd_payload_ras & (~litedramcore_sdram_bankmachine6_cmd_payload_cas)) & (~litedramcore_sdram_bankmachine6_cmd_payload_we))) | litedramcore_sdram_choose_cmd_want_activates)) | ((litedramcore_sdram_bankmachine6_cmd_payload_is_read == litedramcore_sdram_choose_cmd_want_reads) & (litedramcore_sdram_bankmachine6_cmd_payload_is_write == litedramcore_sdram_choose_cmd_want_writes))));
    litedramcore_sdram_choose_cmd_valids[7] <= (litedramcore_sdram_bankmachine7_cmd_valid & (((litedramcore_sdram_bankmachine7_cmd_payload_is_cmd & litedramcore_sdram_choose_cmd_want_cmds) & ((~((litedramcore_sdram_bankmachine7_cmd_payload_ras & (~litedramcore_sdram_bankmachine7_cmd_payload_cas)) & (~litedramcore_sdram_bankmachine7_cmd_payload_we))) | litedramcore_sdram_choose_cmd_want_activates)) | ((litedramcore_sdram_bankmachine7_cmd_payload_is_read == litedramcore_sdram_choose_cmd_want_reads) & (litedramcore_sdram_bankmachine7_cmd_payload_is_write == litedramcore_sdram_choose_cmd_want_writes))));
end
assign litedramcore_sdram_choose_cmd_request = litedramcore_sdram_choose_cmd_valids;
assign litedramcore_sdram_choose_cmd_cmd_valid = rhs_self8;
assign litedramcore_sdram_choose_cmd_cmd_payload_a = rhs_self9;
assign litedramcore_sdram_choose_cmd_cmd_payload_ba = rhs_self10;
assign litedramcore_sdram_choose_cmd_cmd_payload_is_read = rhs_self11;
assign litedramcore_sdram_choose_cmd_cmd_payload_is_write = rhs_self12;
assign litedramcore_sdram_choose_cmd_cmd_payload_is_cmd = rhs_self13;
always @(*) begin
    litedramcore_sdram_choose_cmd_cmd_payload_cas <= 1'd0;
    if (litedramcore_sdram_choose_cmd_cmd_valid) begin
        litedramcore_sdram_choose_cmd_cmd_payload_cas <= t_self0;
    end
end
always @(*) begin
    litedramcore_sdram_choose_cmd_cmd_payload_ras <= 1'd0;
    if (litedramcore_sdram_choose_cmd_cmd_valid) begin
        litedramcore_sdram_choose_cmd_cmd_payload_ras <= t_self1;
    end
end
always @(*) begin
    litedramcore_sdram_choose_cmd_cmd_payload_we <= 1'd0;
    if (litedramcore_sdram_choose_cmd_cmd_valid) begin
        litedramcore_sdram_choose_cmd_cmd_payload_we <= t_self2;
    end
end
always @(*) begin
    litedramcore_sdram_bankmachine0_cmd_ready <= 1'd0;
    if (((litedramcore_sdram_choose_cmd_cmd_valid & litedramcore_sdram_choose_cmd_cmd_ready) & (litedramcore_sdram_choose_cmd_grant == 1'd0))) begin
        litedramcore_sdram_bankmachine0_cmd_ready <= 1'd1;
    end
    if (((litedramcore_sdram_choose_req_cmd_valid & litedramcore_sdram_choose_req_cmd_ready) & (litedramcore_sdram_choose_req_grant == 1'd0))) begin
        litedramcore_sdram_bankmachine0_cmd_ready <= 1'd1;
    end
end
always @(*) begin
    litedramcore_sdram_bankmachine1_cmd_ready <= 1'd0;
    if (((litedramcore_sdram_choose_cmd_cmd_valid & litedramcore_sdram_choose_cmd_cmd_ready) & (litedramcore_sdram_choose_cmd_grant == 1'd1))) begin
        litedramcore_sdram_bankmachine1_cmd_ready <= 1'd1;
    end
    if (((litedramcore_sdram_choose_req_cmd_valid & litedramcore_sdram_choose_req_cmd_ready) & (litedramcore_sdram_choose_req_grant == 1'd1))) begin
        litedramcore_sdram_bankmachine1_cmd_ready <= 1'd1;
    end
end
always @(*) begin
    litedramcore_sdram_bankmachine2_cmd_ready <= 1'd0;
    if (((litedramcore_sdram_choose_cmd_cmd_valid & litedramcore_sdram_choose_cmd_cmd_ready) & (litedramcore_sdram_choose_cmd_grant == 2'd2))) begin
        litedramcore_sdram_bankmachine2_cmd_ready <= 1'd1;
    end
    if (((litedramcore_sdram_choose_req_cmd_valid & litedramcore_sdram_choose_req_cmd_ready) & (litedramcore_sdram_choose_req_grant == 2'd2))) begin
        litedramcore_sdram_bankmachine2_cmd_ready <= 1'd1;
    end
end
always @(*) begin
    litedramcore_sdram_bankmachine3_cmd_ready <= 1'd0;
    if (((litedramcore_sdram_choose_cmd_cmd_valid & litedramcore_sdram_choose_cmd_cmd_ready) & (litedramcore_sdram_choose_cmd_grant == 2'd3))) begin
        litedramcore_sdram_bankmachine3_cmd_ready <= 1'd1;
    end
    if (((litedramcore_sdram_choose_req_cmd_valid & litedramcore_sdram_choose_req_cmd_ready) & (litedramcore_sdram_choose_req_grant == 2'd3))) begin
        litedramcore_sdram_bankmachine3_cmd_ready <= 1'd1;
    end
end
always @(*) begin
    litedramcore_sdram_bankmachine4_cmd_ready <= 1'd0;
    if (((litedramcore_sdram_choose_cmd_cmd_valid & litedramcore_sdram_choose_cmd_cmd_ready) & (litedramcore_sdram_choose_cmd_grant == 3'd4))) begin
        litedramcore_sdram_bankmachine4_cmd_ready <= 1'd1;
    end
    if (((litedramcore_sdram_choose_req_cmd_valid & litedramcore_sdram_choose_req_cmd_ready) & (litedramcore_sdram_choose_req_grant == 3'd4))) begin
        litedramcore_sdram_bankmachine4_cmd_ready <= 1'd1;
    end
end
always @(*) begin
    litedramcore_sdram_bankmachine5_cmd_ready <= 1'd0;
    if (((litedramcore_sdram_choose_cmd_cmd_valid & litedramcore_sdram_choose_cmd_cmd_ready) & (litedramcore_sdram_choose_cmd_grant == 3'd5))) begin
        litedramcore_sdram_bankmachine5_cmd_ready <= 1'd1;
    end
    if (((litedramcore_sdram_choose_req_cmd_valid & litedramcore_sdram_choose_req_cmd_ready) & (litedramcore_sdram_choose_req_grant == 3'd5))) begin
        litedramcore_sdram_bankmachine5_cmd_ready <= 1'd1;
    end
end
always @(*) begin
    litedramcore_sdram_bankmachine6_cmd_ready <= 1'd0;
    if (((litedramcore_sdram_choose_cmd_cmd_valid & litedramcore_sdram_choose_cmd_cmd_ready) & (litedramcore_sdram_choose_cmd_grant == 3'd6))) begin
        litedramcore_sdram_bankmachine6_cmd_ready <= 1'd1;
    end
    if (((litedramcore_sdram_choose_req_cmd_valid & litedramcore_sdram_choose_req_cmd_ready) & (litedramcore_sdram_choose_req_grant == 3'd6))) begin
        litedramcore_sdram_bankmachine6_cmd_ready <= 1'd1;
    end
end
always @(*) begin
    litedramcore_sdram_bankmachine7_cmd_ready <= 1'd0;
    if (((litedramcore_sdram_choose_cmd_cmd_valid & litedramcore_sdram_choose_cmd_cmd_ready) & (litedramcore_sdram_choose_cmd_grant == 3'd7))) begin
        litedramcore_sdram_bankmachine7_cmd_ready <= 1'd1;
    end
    if (((litedramcore_sdram_choose_req_cmd_valid & litedramcore_sdram_choose_req_cmd_ready) & (litedramcore_sdram_choose_req_grant == 3'd7))) begin
        litedramcore_sdram_bankmachine7_cmd_ready <= 1'd1;
    end
end
assign litedramcore_sdram_choose_cmd_ce = (litedramcore_sdram_choose_cmd_cmd_ready | (~litedramcore_sdram_choose_cmd_cmd_valid));
always @(*) begin
    litedramcore_sdram_choose_req_valids <= 8'd0;
    litedramcore_sdram_choose_req_valids[0] <= (litedramcore_sdram_bankmachine0_cmd_valid & (((litedramcore_sdram_bankmachine0_cmd_payload_is_cmd & litedramcore_sdram_choose_req_want_cmds) & ((~((litedramcore_sdram_bankmachine0_cmd_payload_ras & (~litedramcore_sdram_bankmachine0_cmd_payload_cas)) & (~litedramcore_sdram_bankmachine0_cmd_payload_we))) | litedramcore_sdram_choose_req_want_activates)) | ((litedramcore_sdram_bankmachine0_cmd_payload_is_read == litedramcore_sdram_choose_req_want_reads) & (litedramcore_sdram_bankmachine0_cmd_payload_is_write == litedramcore_sdram_choose_req_want_writes))));
    litedramcore_sdram_choose_req_valids[1] <= (litedramcore_sdram_bankmachine1_cmd_valid & (((litedramcore_sdram_bankmachine1_cmd_payload_is_cmd & litedramcore_sdram_choose_req_want_cmds) & ((~((litedramcore_sdram_bankmachine1_cmd_payload_ras & (~litedramcore_sdram_bankmachine1_cmd_payload_cas)) & (~litedramcore_sdram_bankmachine1_cmd_payload_we))) | litedramcore_sdram_choose_req_want_activates)) | ((litedramcore_sdram_bankmachine1_cmd_payload_is_read == litedramcore_sdram_choose_req_want_reads) & (litedramcore_sdram_bankmachine1_cmd_payload_is_write == litedramcore_sdram_choose_req_want_writes))));
    litedramcore_sdram_choose_req_valids[2] <= (litedramcore_sdram_bankmachine2_cmd_valid & (((litedramcore_sdram_bankmachine2_cmd_payload_is_cmd & litedramcore_sdram_choose_req_want_cmds) & ((~((litedramcore_sdram_bankmachine2_cmd_payload_ras & (~litedramcore_sdram_bankmachine2_cmd_payload_cas)) & (~litedramcore_sdram_bankmachine2_cmd_payload_we))) | litedramcore_sdram_choose_req_want_activates)) | ((litedramcore_sdram_bankmachine2_cmd_payload_is_read == litedramcore_sdram_choose_req_want_reads) & (litedramcore_sdram_bankmachine2_cmd_payload_is_write == litedramcore_sdram_choose_req_want_writes))));
    litedramcore_sdram_choose_req_valids[3] <= (litedramcore_sdram_bankmachine3_cmd_valid & (((litedramcore_sdram_bankmachine3_cmd_payload_is_cmd & litedramcore_sdram_choose_req_want_cmds) & ((~((litedramcore_sdram_bankmachine3_cmd_payload_ras & (~litedramcore_sdram_bankmachine3_cmd_payload_cas)) & (~litedramcore_sdram_bankmachine3_cmd_payload_we))) | litedramcore_sdram_choose_req_want_activates)) | ((litedramcore_sdram_bankmachine3_cmd_payload_is_read == litedramcore_sdram_choose_req_want_reads) & (litedramcore_sdram_bankmachine3_cmd_payload_is_write == litedramcore_sdram_choose_req_want_writes))));
    litedramcore_sdram_choose_req_valids[4] <= (litedramcore_sdram_bankmachine4_cmd_valid & (((litedramcore_sdram_bankmachine4_cmd_payload_is_cmd & litedramcore_sdram_choose_req_want_cmds) & ((~((litedramcore_sdram_bankmachine4_cmd_payload_ras & (~litedramcore_sdram_bankmachine4_cmd_payload_cas)) & (~litedramcore_sdram_bankmachine4_cmd_payload_we))) | litedramcore_sdram_choose_req_want_activates)) | ((litedramcore_sdram_bankmachine4_cmd_payload_is_read == litedramcore_sdram_choose_req_want_reads) & (litedramcore_sdram_bankmachine4_cmd_payload_is_write == litedramcore_sdram_choose_req_want_writes))));
    litedramcore_sdram_choose_req_valids[5] <= (litedramcore_sdram_bankmachine5_cmd_valid & (((litedramcore_sdram_bankmachine5_cmd_payload_is_cmd & litedramcore_sdram_choose_req_want_cmds) & ((~((litedramcore_sdram_bankmachine5_cmd_payload_ras & (~litedramcore_sdram_bankmachine5_cmd_payload_cas)) & (~litedramcore_sdram_bankmachine5_cmd_payload_we))) | litedramcore_sdram_choose_req_want_activates)) | ((litedramcore_sdram_bankmachine5_cmd_payload_is_read == litedramcore_sdram_choose_req_want_reads) & (litedramcore_sdram_bankmachine5_cmd_payload_is_write == litedramcore_sdram_choose_req_want_writes))));
    litedramcore_sdram_choose_req_valids[6] <= (litedramcore_sdram_bankmachine6_cmd_valid & (((litedramcore_sdram_bankmachine6_cmd_payload_is_cmd & litedramcore_sdram_choose_req_want_cmds) & ((~((litedramcore_sdram_bankmachine6_cmd_payload_ras & (~litedramcore_sdram_bankmachine6_cmd_payload_cas)) & (~litedramcore_sdram_bankmachine6_cmd_payload_we))) | litedramcore_sdram_choose_req_want_activates)) | ((litedramcore_sdram_bankmachine6_cmd_payload_is_read == litedramcore_sdram_choose_req_want_reads) & (litedramcore_sdram_bankmachine6_cmd_payload_is_write == litedramcore_sdram_choose_req_want_writes))));
    litedramcore_sdram_choose_req_valids[7] <= (litedramcore_sdram_bankmachine7_cmd_valid & (((litedramcore_sdram_bankmachine7_cmd_payload_is_cmd & litedramcore_sdram_choose_req_want_cmds) & ((~((litedramcore_sdram_bankmachine7_cmd_payload_ras & (~litedramcore_sdram_bankmachine7_cmd_payload_cas)) & (~litedramcore_sdram_bankmachine7_cmd_payload_we))) | litedramcore_sdram_choose_req_want_activates)) | ((litedramcore_sdram_bankmachine7_cmd_payload_is_read == litedramcore_sdram_choose_req_want_reads) & (litedramcore_sdram_bankmachine7_cmd_payload_is_write == litedramcore_sdram_choose_req_want_writes))));
end
assign litedramcore_sdram_choose_req_request = litedramcore_sdram_choose_req_valids;
assign litedramcore_sdram_choose_req_cmd_valid = rhs_self14;
assign litedramcore_sdram_choose_req_cmd_payload_a = rhs_self15;
assign litedramcore_sdram_choose_req_cmd_payload_ba = rhs_self16;
assign litedramcore_sdram_choose_req_cmd_payload_is_read = rhs_self17;
assign litedramcore_sdram_choose_req_cmd_payload_is_write = rhs_self18;
assign litedramcore_sdram_choose_req_cmd_payload_is_cmd = rhs_self19;
always @(*) begin
    litedramcore_sdram_choose_req_cmd_payload_cas <= 1'd0;
    if (litedramcore_sdram_choose_req_cmd_valid) begin
        litedramcore_sdram_choose_req_cmd_payload_cas <= t_self3;
    end
end
always @(*) begin
    litedramcore_sdram_choose_req_cmd_payload_ras <= 1'd0;
    if (litedramcore_sdram_choose_req_cmd_valid) begin
        litedramcore_sdram_choose_req_cmd_payload_ras <= t_self4;
    end
end
always @(*) begin
    litedramcore_sdram_choose_req_cmd_payload_we <= 1'd0;
    if (litedramcore_sdram_choose_req_cmd_valid) begin
        litedramcore_sdram_choose_req_cmd_payload_we <= t_self5;
    end
end
assign litedramcore_sdram_choose_req_ce = (litedramcore_sdram_choose_req_cmd_ready | (~litedramcore_sdram_choose_req_cmd_valid));
assign litedramcore_sdram_dfi_p0_reset_n = 1'd1;
assign litedramcore_sdram_dfi_p0_cke = {1{litedramcore_sdram_steerer4}};
assign litedramcore_sdram_dfi_p0_odt = {1{litedramcore_sdram_steerer5}};
assign litedramcore_sdram_dfi_p1_reset_n = 1'd1;
assign litedramcore_sdram_dfi_p1_cke = {1{litedramcore_sdram_steerer6}};
assign litedramcore_sdram_dfi_p1_odt = {1{litedramcore_sdram_steerer7}};
assign litedramcore_sdram_dfi_p2_reset_n = 1'd1;
assign litedramcore_sdram_dfi_p2_cke = {1{litedramcore_sdram_steerer8}};
assign litedramcore_sdram_dfi_p2_odt = {1{litedramcore_sdram_steerer9}};
assign litedramcore_sdram_dfi_p3_reset_n = 1'd1;
assign litedramcore_sdram_dfi_p3_cke = {1{litedramcore_sdram_steerer10}};
assign litedramcore_sdram_dfi_p3_odt = {1{litedramcore_sdram_steerer11}};
assign litedramcore_sdram_tfawcon_count = ((((((((litedramcore_sdram_tfawcon_window[0] + litedramcore_sdram_tfawcon_window[1]) + litedramcore_sdram_tfawcon_window[2]) + litedramcore_sdram_tfawcon_window[3]) + litedramcore_sdram_tfawcon_window[4]) + litedramcore_sdram_tfawcon_window[5]) + litedramcore_sdram_tfawcon_window[6]) + litedramcore_sdram_tfawcon_window[7]) + litedramcore_sdram_tfawcon_window[8]);
always @(*) begin
    litedramcore_multiplexer_next_state <= 4'd0;
    litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state;
    case (litedramcore_multiplexer_state)
        1'd1: begin
            if (litedramcore_sdram_read_available) begin
                if (((~litedramcore_sdram_write_available) | litedramcore_sdram_max_time1)) begin
                    litedramcore_multiplexer_next_state <= 2'd3;
                end
            end
            if (litedramcore_sdram_go_to_refresh) begin
                litedramcore_multiplexer_next_state <= 2'd2;
            end
        end
        2'd2: begin
            if (litedramcore_sdram_cmd_last) begin
                litedramcore_multiplexer_next_state <= 1'd0;
            end
        end
        2'd3: begin
            if (litedramcore_sdram_twtrcon_ready) begin
                litedramcore_multiplexer_next_state <= 1'd0;
            end
        end
        3'd4: begin
            litedramcore_multiplexer_next_state <= 3'd5;
        end
        3'd5: begin
            litedramcore_multiplexer_next_state <= 3'd6;
        end
        3'd6: begin
            litedramcore_multiplexer_next_state <= 3'd7;
        end
        3'd7: begin
            litedramcore_multiplexer_next_state <= 4'd8;
        end
        4'd8: begin
            litedramcore_multiplexer_next_state <= 4'd9;
        end
        4'd9: begin
            litedramcore_multiplexer_next_state <= 4'd10;
        end
        4'd10: begin
            litedramcore_multiplexer_next_state <= 4'd11;
        end
        4'd11: begin
            litedramcore_multiplexer_next_state <= 1'd1;
        end
        default: begin
            if (litedramcore_sdram_write_available) begin
                if (((~litedramcore_sdram_read_available) | litedramcore_sdram_max_time0)) begin
                    litedramcore_multiplexer_next_state <= 3'd4;
                end
            end
            if (litedramcore_sdram_go_to_refresh) begin
                litedramcore_multiplexer_next_state <= 2'd2;
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_choose_req_want_writes <= 1'd0;
    case (litedramcore_multiplexer_state)
        1'd1: begin
            litedramcore_sdram_choose_req_want_writes <= 1'd1;
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        4'd11: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_steerer3 <= 2'd0;
    case (litedramcore_multiplexer_state)
        1'd1: begin
            litedramcore_sdram_steerer3 <= 1'd0;
            if ((k7ddrphy_wrphase_storage == 2'd3)) begin
                litedramcore_sdram_steerer3 <= 2'd2;
            end
            if ((litedramcore_sdram_rdphase == 2'd3)) begin
                litedramcore_sdram_steerer3 <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        4'd11: begin
        end
        default: begin
            litedramcore_sdram_steerer3 <= 1'd0;
            if ((k7ddrphy_rdphase_storage == 2'd3)) begin
                litedramcore_sdram_steerer3 <= 2'd2;
            end
            if ((litedramcore_sdram_nphases == 2'd3)) begin
                litedramcore_sdram_steerer3 <= 1'd1;
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_en0 <= 1'd0;
    case (litedramcore_multiplexer_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        4'd11: begin
        end
        default: begin
            litedramcore_sdram_en0 <= 1'd1;
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_choose_req_cmd_ready <= 1'd0;
    case (litedramcore_multiplexer_state)
        1'd1: begin
            if (1'd0) begin
                litedramcore_sdram_choose_req_cmd_ready <= (litedramcore_sdram_cas_allowed & ((~((litedramcore_sdram_choose_req_cmd_payload_ras & (~litedramcore_sdram_choose_req_cmd_payload_cas)) & (~litedramcore_sdram_choose_req_cmd_payload_we))) | litedramcore_sdram_ras_allowed));
            end else begin
                litedramcore_sdram_choose_req_cmd_ready <= litedramcore_sdram_cas_allowed;
            end
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        4'd11: begin
        end
        default: begin
            if (1'd0) begin
                litedramcore_sdram_choose_req_cmd_ready <= (litedramcore_sdram_cas_allowed & ((~((litedramcore_sdram_choose_req_cmd_payload_ras & (~litedramcore_sdram_choose_req_cmd_payload_cas)) & (~litedramcore_sdram_choose_req_cmd_payload_we))) | litedramcore_sdram_ras_allowed));
            end else begin
                litedramcore_sdram_choose_req_cmd_ready <= litedramcore_sdram_cas_allowed;
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_en1 <= 1'd0;
    case (litedramcore_multiplexer_state)
        1'd1: begin
            litedramcore_sdram_en1 <= 1'd1;
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        4'd11: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_steerer0 <= 2'd0;
    case (litedramcore_multiplexer_state)
        1'd1: begin
            litedramcore_sdram_steerer0 <= 1'd0;
            if ((k7ddrphy_wrphase_storage == 1'd0)) begin
                litedramcore_sdram_steerer0 <= 2'd2;
            end
            if ((litedramcore_sdram_rdphase == 1'd0)) begin
                litedramcore_sdram_steerer0 <= 1'd1;
            end
        end
        2'd2: begin
            litedramcore_sdram_steerer0 <= 2'd3;
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        4'd11: begin
        end
        default: begin
            litedramcore_sdram_steerer0 <= 1'd0;
            if ((k7ddrphy_rdphase_storage == 1'd0)) begin
                litedramcore_sdram_steerer0 <= 2'd2;
            end
            if ((litedramcore_sdram_nphases == 1'd0)) begin
                litedramcore_sdram_steerer0 <= 1'd1;
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_cmd_ready <= 1'd0;
    case (litedramcore_multiplexer_state)
        1'd1: begin
        end
        2'd2: begin
            litedramcore_sdram_cmd_ready <= 1'd1;
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        4'd11: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_steerer1 <= 2'd0;
    case (litedramcore_multiplexer_state)
        1'd1: begin
            litedramcore_sdram_steerer1 <= 1'd0;
            if ((k7ddrphy_wrphase_storage == 1'd1)) begin
                litedramcore_sdram_steerer1 <= 2'd2;
            end
            if ((litedramcore_sdram_rdphase == 1'd1)) begin
                litedramcore_sdram_steerer1 <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        4'd11: begin
        end
        default: begin
            litedramcore_sdram_steerer1 <= 1'd0;
            if ((k7ddrphy_rdphase_storage == 1'd1)) begin
                litedramcore_sdram_steerer1 <= 2'd2;
            end
            if ((litedramcore_sdram_nphases == 1'd1)) begin
                litedramcore_sdram_steerer1 <= 1'd1;
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_steerer2 <= 2'd0;
    case (litedramcore_multiplexer_state)
        1'd1: begin
            litedramcore_sdram_steerer2 <= 1'd0;
            if ((k7ddrphy_wrphase_storage == 2'd2)) begin
                litedramcore_sdram_steerer2 <= 2'd2;
            end
            if ((litedramcore_sdram_rdphase == 2'd2)) begin
                litedramcore_sdram_steerer2 <= 1'd1;
            end
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        4'd11: begin
        end
        default: begin
            litedramcore_sdram_steerer2 <= 1'd0;
            if ((k7ddrphy_rdphase_storage == 2'd2)) begin
                litedramcore_sdram_steerer2 <= 2'd2;
            end
            if ((litedramcore_sdram_nphases == 2'd2)) begin
                litedramcore_sdram_steerer2 <= 1'd1;
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_choose_cmd_want_activates <= 1'd0;
    case (litedramcore_multiplexer_state)
        1'd1: begin
            if (1'd0) begin
            end else begin
                litedramcore_sdram_choose_cmd_want_activates <= litedramcore_sdram_ras_allowed;
            end
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        4'd11: begin
        end
        default: begin
            if (1'd0) begin
            end else begin
                litedramcore_sdram_choose_cmd_want_activates <= litedramcore_sdram_ras_allowed;
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_choose_cmd_cmd_ready <= 1'd0;
    case (litedramcore_multiplexer_state)
        1'd1: begin
            if (1'd0) begin
            end else begin
                litedramcore_sdram_choose_cmd_cmd_ready <= ((~((litedramcore_sdram_choose_cmd_cmd_payload_ras & (~litedramcore_sdram_choose_cmd_cmd_payload_cas)) & (~litedramcore_sdram_choose_cmd_cmd_payload_we))) | litedramcore_sdram_ras_allowed);
            end
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        4'd11: begin
        end
        default: begin
            if (1'd0) begin
            end else begin
                litedramcore_sdram_choose_cmd_cmd_ready <= ((~((litedramcore_sdram_choose_cmd_cmd_payload_ras & (~litedramcore_sdram_choose_cmd_cmd_payload_cas)) & (~litedramcore_sdram_choose_cmd_cmd_payload_we))) | litedramcore_sdram_ras_allowed);
            end
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_choose_req_want_reads <= 1'd0;
    case (litedramcore_multiplexer_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        3'd4: begin
        end
        3'd5: begin
        end
        3'd6: begin
        end
        3'd7: begin
        end
        4'd8: begin
        end
        4'd9: begin
        end
        4'd10: begin
        end
        4'd11: begin
        end
        default: begin
            litedramcore_sdram_choose_req_want_reads <= 1'd1;
        end
    endcase
end
assign litedramcore_roundrobin0_request = {(((user_port_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked1 | (litedramcore_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd1))) | (litedramcore_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd1))) | (litedramcore_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd1))) | (litedramcore_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd1))) | (litedramcore_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd1))) | (litedramcore_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd1))) | (litedramcore_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd1))))) & user_port_port_cmd_valid), (((litedramcore_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & litedramcore_port_cmd_valid)};
assign litedramcore_roundrobin0_ce = ((~litedramcore_sdram_interface_bank0_valid) & (~litedramcore_sdram_interface_bank0_lock));
assign litedramcore_sdram_interface_bank0_addr = rhs_self20;
assign litedramcore_sdram_interface_bank0_we = rhs_self21;
assign litedramcore_sdram_interface_bank0_valid = rhs_self22;
assign litedramcore_roundrobin1_request = {(((user_port_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked3 | (litedramcore_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd1))) | (litedramcore_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd1))) | (litedramcore_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd1))) | (litedramcore_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd1))) | (litedramcore_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd1))) | (litedramcore_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd1))) | (litedramcore_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd1))))) & user_port_port_cmd_valid), (((litedramcore_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked2 | (litedramcore_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & litedramcore_port_cmd_valid)};
assign litedramcore_roundrobin1_ce = ((~litedramcore_sdram_interface_bank1_valid) & (~litedramcore_sdram_interface_bank1_lock));
assign litedramcore_sdram_interface_bank1_addr = rhs_self23;
assign litedramcore_sdram_interface_bank1_we = rhs_self24;
assign litedramcore_sdram_interface_bank1_valid = rhs_self25;
assign litedramcore_roundrobin2_request = {(((user_port_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked5 | (litedramcore_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd1))) | (litedramcore_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd1))) | (litedramcore_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd1))) | (litedramcore_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd1))) | (litedramcore_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd1))) | (litedramcore_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd1))) | (litedramcore_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd1))))) & user_port_port_cmd_valid), (((litedramcore_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked4 | (litedramcore_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & litedramcore_port_cmd_valid)};
assign litedramcore_roundrobin2_ce = ((~litedramcore_sdram_interface_bank2_valid) & (~litedramcore_sdram_interface_bank2_lock));
assign litedramcore_sdram_interface_bank2_addr = rhs_self26;
assign litedramcore_sdram_interface_bank2_we = rhs_self27;
assign litedramcore_sdram_interface_bank2_valid = rhs_self28;
assign litedramcore_roundrobin3_request = {(((user_port_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked7 | (litedramcore_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd1))) | (litedramcore_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd1))) | (litedramcore_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd1))) | (litedramcore_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd1))) | (litedramcore_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd1))) | (litedramcore_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd1))) | (litedramcore_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd1))))) & user_port_port_cmd_valid), (((litedramcore_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked6 | (litedramcore_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & litedramcore_port_cmd_valid)};
assign litedramcore_roundrobin3_ce = ((~litedramcore_sdram_interface_bank3_valid) & (~litedramcore_sdram_interface_bank3_lock));
assign litedramcore_sdram_interface_bank3_addr = rhs_self29;
assign litedramcore_sdram_interface_bank3_we = rhs_self30;
assign litedramcore_sdram_interface_bank3_valid = rhs_self31;
assign litedramcore_roundrobin4_request = {(((user_port_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked9 | (litedramcore_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd1))) | (litedramcore_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd1))) | (litedramcore_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd1))) | (litedramcore_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd1))) | (litedramcore_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd1))) | (litedramcore_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd1))) | (litedramcore_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd1))))) & user_port_port_cmd_valid), (((litedramcore_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked8 | (litedramcore_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & litedramcore_port_cmd_valid)};
assign litedramcore_roundrobin4_ce = ((~litedramcore_sdram_interface_bank4_valid) & (~litedramcore_sdram_interface_bank4_lock));
assign litedramcore_sdram_interface_bank4_addr = rhs_self32;
assign litedramcore_sdram_interface_bank4_we = rhs_self33;
assign litedramcore_sdram_interface_bank4_valid = rhs_self34;
assign litedramcore_roundrobin5_request = {(((user_port_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked11 | (litedramcore_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd1))) | (litedramcore_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd1))) | (litedramcore_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd1))) | (litedramcore_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd1))) | (litedramcore_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd1))) | (litedramcore_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd1))) | (litedramcore_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd1))))) & user_port_port_cmd_valid), (((litedramcore_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked10 | (litedramcore_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & litedramcore_port_cmd_valid)};
assign litedramcore_roundrobin5_ce = ((~litedramcore_sdram_interface_bank5_valid) & (~litedramcore_sdram_interface_bank5_lock));
assign litedramcore_sdram_interface_bank5_addr = rhs_self35;
assign litedramcore_sdram_interface_bank5_we = rhs_self36;
assign litedramcore_sdram_interface_bank5_valid = rhs_self37;
assign litedramcore_roundrobin6_request = {(((user_port_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked13 | (litedramcore_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd1))) | (litedramcore_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd1))) | (litedramcore_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd1))) | (litedramcore_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd1))) | (litedramcore_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd1))) | (litedramcore_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd1))) | (litedramcore_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd1))))) & user_port_port_cmd_valid), (((litedramcore_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked12 | (litedramcore_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & litedramcore_port_cmd_valid)};
assign litedramcore_roundrobin6_ce = ((~litedramcore_sdram_interface_bank6_valid) & (~litedramcore_sdram_interface_bank6_lock));
assign litedramcore_sdram_interface_bank6_addr = rhs_self38;
assign litedramcore_sdram_interface_bank6_we = rhs_self39;
assign litedramcore_sdram_interface_bank6_valid = rhs_self40;
assign litedramcore_roundrobin7_request = {(((user_port_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked15 | (litedramcore_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd1))) | (litedramcore_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd1))) | (litedramcore_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd1))) | (litedramcore_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd1))) | (litedramcore_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd1))) | (litedramcore_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd1))) | (litedramcore_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd1))))) & user_port_port_cmd_valid), (((litedramcore_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked14 | (litedramcore_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & litedramcore_port_cmd_valid)};
assign litedramcore_roundrobin7_ce = ((~litedramcore_sdram_interface_bank7_valid) & (~litedramcore_sdram_interface_bank7_lock));
assign litedramcore_sdram_interface_bank7_addr = rhs_self41;
assign litedramcore_sdram_interface_bank7_we = rhs_self42;
assign litedramcore_sdram_interface_bank7_valid = rhs_self43;
assign litedramcore_port_cmd_ready = ((((((((1'd0 | (((litedramcore_roundrobin0_grant == 1'd0) & ((litedramcore_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_sdram_interface_bank0_ready)) | (((litedramcore_roundrobin1_grant == 1'd0) & ((litedramcore_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked2 | (litedramcore_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_sdram_interface_bank1_ready)) | (((litedramcore_roundrobin2_grant == 1'd0) & ((litedramcore_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked4 | (litedramcore_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_sdram_interface_bank2_ready)) | (((litedramcore_roundrobin3_grant == 1'd0) & ((litedramcore_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked6 | (litedramcore_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_sdram_interface_bank3_ready)) | (((litedramcore_roundrobin4_grant == 1'd0) & ((litedramcore_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked8 | (litedramcore_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_sdram_interface_bank4_ready)) | (((litedramcore_roundrobin5_grant == 1'd0) & ((litedramcore_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked10 | (litedramcore_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_sdram_interface_bank5_ready)) | (((litedramcore_roundrobin6_grant == 1'd0) & ((litedramcore_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked12 | (litedramcore_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0)))))) & litedramcore_sdram_interface_bank6_ready)) | (((litedramcore_roundrobin7_grant == 1'd0) & ((litedramcore_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked14 | (litedramcore_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0)))))) & litedramcore_sdram_interface_bank7_ready));
assign user_port_port_cmd_ready = ((((((((1'd0 | (((litedramcore_roundrobin0_grant == 1'd1) & ((user_port_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked1 | (litedramcore_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd1))) | (litedramcore_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd1))) | (litedramcore_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd1))) | (litedramcore_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd1))) | (litedramcore_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd1))) | (litedramcore_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd1))) | (litedramcore_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd1)))))) & litedramcore_sdram_interface_bank0_ready)) | (((litedramcore_roundrobin1_grant == 1'd1) & ((user_port_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked3 | (litedramcore_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd1))) | (litedramcore_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd1))) | (litedramcore_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd1))) | (litedramcore_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd1))) | (litedramcore_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd1))) | (litedramcore_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd1))) | (litedramcore_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd1)))))) & litedramcore_sdram_interface_bank1_ready)) | (((litedramcore_roundrobin2_grant == 1'd1) & ((user_port_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked5 | (litedramcore_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd1))) | (litedramcore_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd1))) | (litedramcore_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd1))) | (litedramcore_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd1))) | (litedramcore_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd1))) | (litedramcore_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd1))) | (litedramcore_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd1)))))) & litedramcore_sdram_interface_bank2_ready)) | (((litedramcore_roundrobin3_grant == 1'd1) & ((user_port_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked7 | (litedramcore_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd1))) | (litedramcore_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd1))) | (litedramcore_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd1))) | (litedramcore_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd1))) | (litedramcore_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd1))) | (litedramcore_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd1))) | (litedramcore_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd1)))))) & litedramcore_sdram_interface_bank3_ready)) | (((litedramcore_roundrobin4_grant == 1'd1) & ((user_port_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked9 | (litedramcore_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd1))) | (litedramcore_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd1))) | (litedramcore_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd1))) | (litedramcore_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd1))) | (litedramcore_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd1))) | (litedramcore_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd1))) | (litedramcore_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd1)))))) & litedramcore_sdram_interface_bank4_ready)) | (((litedramcore_roundrobin5_grant == 1'd1) & ((user_port_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked11 | (litedramcore_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd1))) | (litedramcore_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd1))) | (litedramcore_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd1))) | (litedramcore_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd1))) | (litedramcore_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd1))) | (litedramcore_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd1))) | (litedramcore_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd1)))))) & litedramcore_sdram_interface_bank5_ready)) | (((litedramcore_roundrobin6_grant == 1'd1) & ((user_port_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked13 | (litedramcore_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd1))) | (litedramcore_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd1))) | (litedramcore_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd1))) | (litedramcore_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd1))) | (litedramcore_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd1))) | (litedramcore_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd1))) | (litedramcore_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd1)))))) & litedramcore_sdram_interface_bank6_ready)) | (((litedramcore_roundrobin7_grant == 1'd1) & ((user_port_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked15 | (litedramcore_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd1))) | (litedramcore_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd1))) | (litedramcore_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd1))) | (litedramcore_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd1))) | (litedramcore_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd1))) | (litedramcore_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd1))) | (litedramcore_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd1)))))) & litedramcore_sdram_interface_bank7_ready));
assign litedramcore_port_wdata_ready = litedramcore_new_master_wdata_ready1;
assign user_port_port_wdata_ready = litedramcore_new_master_wdata_ready3;
assign litedramcore_port_rdata_valid = litedramcore_new_master_rdata_valid9;
assign user_port_port_rdata_valid = litedramcore_new_master_rdata_valid19;
always @(*) begin
    litedramcore_sdram_interface_wdata <= 256'd0;
    case ({litedramcore_new_master_wdata_ready3, litedramcore_new_master_wdata_ready1})
        1'd1: begin
            litedramcore_sdram_interface_wdata <= litedramcore_port_wdata_payload_data;
        end
        2'd2: begin
            litedramcore_sdram_interface_wdata <= user_port_port_wdata_payload_data;
        end
        default: begin
            litedramcore_sdram_interface_wdata <= 1'd0;
        end
    endcase
end
always @(*) begin
    litedramcore_sdram_interface_wdata_we <= 32'd0;
    case ({litedramcore_new_master_wdata_ready3, litedramcore_new_master_wdata_ready1})
        1'd1: begin
            litedramcore_sdram_interface_wdata_we <= litedramcore_port_wdata_payload_we;
        end
        2'd2: begin
            litedramcore_sdram_interface_wdata_we <= user_port_port_wdata_payload_we;
        end
        default: begin
            litedramcore_sdram_interface_wdata_we <= 1'd0;
        end
    endcase
end
assign litedramcore_port_rdata_payload_data = litedramcore_sdram_interface_rdata;
assign user_port_port_rdata_payload_data = litedramcore_sdram_interface_rdata;
assign user_port_litedramnativeportconverter_cmd_buffer_source_ready = (user_port_litedramnativeportconverter_wdata_finished | user_port_litedramnativeportconverter_rdata_finished);
assign user_port_litedramnativeportconverter_addr_changed = (user_port_litedramnativeportconverter_cmd_addr[27:3] != user_port_new_port_cmd_payload_addr[27:3]);
assign user_port_litedramnativeportconverter_rw_collision = ((user_port_litedramnativeportconverter_cmd_we & (user_port_new_port_cmd_valid & (~user_port_new_port_cmd_payload_we))) & (~user_port_litedramnativeportconverter_addr_changed));
assign user_port_litedramnativeportconverter_next_cmd = ((((user_port_litedramnativeportconverter_addr_changed | (user_port_litedramnativeportconverter_cmd_we != user_port_new_port_cmd_payload_we)) | (user_port_litedramnativeportconverter_sel == 8'd255)) | user_port_litedramnativeportconverter_cmd_last) | user_port_new_port_flush);
assign user_port_litedramnativeportconverter_rdata_fifo_sink_valid = user_port_port_rdata_valid;
assign user_port_port_rdata_ready = user_port_litedramnativeportconverter_rdata_fifo_sink_ready;
assign user_port_litedramnativeportconverter_rdata_fifo_sink_first = user_port_port_rdata_first;
assign user_port_litedramnativeportconverter_rdata_fifo_sink_last = user_port_port_rdata_last;
assign user_port_litedramnativeportconverter_rdata_fifo_sink_payload_data = user_port_port_rdata_payload_data;
assign user_port_litedramnativeportconverter_rdata_converter_sink_valid = user_port_litedramnativeportconverter_rdata_fifo_source_valid;
assign user_port_litedramnativeportconverter_rdata_fifo_source_ready = user_port_litedramnativeportconverter_rdata_converter_sink_ready;
assign user_port_litedramnativeportconverter_rdata_converter_sink_first = user_port_litedramnativeportconverter_rdata_fifo_source_first;
assign user_port_litedramnativeportconverter_rdata_converter_sink_last = user_port_litedramnativeportconverter_rdata_fifo_source_last;
assign user_port_litedramnativeportconverter_rdata_converter_sink_payload_data = user_port_litedramnativeportconverter_rdata_fifo_source_payload_data;
assign user_port_litedramnativeportconverter_rdata_chunk_valid = ((user_port_litedramnativeportconverter_cmd_buffer_source_payload_sel & user_port_litedramnativeportconverter_rdata_chunk) != 1'd0);
always @(*) begin
    user_port_litedramnativeportconverter_rdata_finished <= 1'd0;
    if ((user_port_litedramnativeportconverter_cmd_buffer_source_valid & (~user_port_litedramnativeportconverter_cmd_buffer_source_payload_we))) begin
        user_port_litedramnativeportconverter_rdata_finished <= ((user_port_litedramnativeportconverter_rdata_converter_source_valid & user_port_litedramnativeportconverter_rdata_converter_source_ready) & user_port_litedramnativeportconverter_rdata_chunk[7]);
    end
end
always @(*) begin
    user_port_new_port_rdata_valid <= 1'd0;
    if ((user_port_litedramnativeportconverter_cmd_buffer_source_valid & (~user_port_litedramnativeportconverter_cmd_buffer_source_payload_we))) begin
        if (user_port_litedramnativeportconverter_rdata_chunk_valid) begin
            user_port_new_port_rdata_valid <= user_port_litedramnativeportconverter_rdata_converter_source_valid;
        end else begin
        end
    end
end
always @(*) begin
    user_port_new_port_rdata_payload_data <= 32'd0;
    if ((user_port_litedramnativeportconverter_cmd_buffer_source_valid & (~user_port_litedramnativeportconverter_cmd_buffer_source_payload_we))) begin
        if (user_port_litedramnativeportconverter_rdata_chunk_valid) begin
            user_port_new_port_rdata_payload_data <= user_port_litedramnativeportconverter_rdata_converter_source_payload_data;
        end else begin
        end
    end
end
always @(*) begin
    user_port_litedramnativeportconverter_rdata_converter_source_ready <= 1'd0;
    if ((user_port_litedramnativeportconverter_cmd_buffer_source_valid & (~user_port_litedramnativeportconverter_cmd_buffer_source_payload_we))) begin
        if (user_port_litedramnativeportconverter_rdata_chunk_valid) begin
            user_port_litedramnativeportconverter_rdata_converter_source_ready <= user_port_new_port_rdata_ready;
        end else begin
            user_port_litedramnativeportconverter_rdata_converter_source_ready <= 1'd1;
        end
    end
end
assign user_port_litedramnativeportconverter_wdata_fifo_sink_valid = user_port_new_port_wdata_valid;
assign user_port_new_port_wdata_ready = user_port_litedramnativeportconverter_wdata_fifo_sink_ready;
assign user_port_litedramnativeportconverter_wdata_fifo_sink_first = user_port_new_port_wdata_first;
assign user_port_litedramnativeportconverter_wdata_fifo_sink_last = user_port_new_port_wdata_last;
assign user_port_litedramnativeportconverter_wdata_fifo_sink_payload_data = user_port_new_port_wdata_payload_data;
assign user_port_litedramnativeportconverter_wdata_fifo_sink_payload_we = user_port_new_port_wdata_payload_we;
assign user_port_port_wdata_valid = user_port_litedramnativeportconverter_wdata_buffer_source_source_valid;
assign user_port_litedramnativeportconverter_wdata_buffer_source_source_ready = user_port_port_wdata_ready;
assign user_port_port_wdata_first = user_port_litedramnativeportconverter_wdata_buffer_source_source_first;
assign user_port_port_wdata_last = user_port_litedramnativeportconverter_wdata_buffer_source_source_last;
assign user_port_port_wdata_payload_data = user_port_litedramnativeportconverter_wdata_buffer_source_source_payload_data;
assign user_port_port_wdata_payload_we = user_port_litedramnativeportconverter_wdata_buffer_source_source_payload_we;
assign user_port_litedramnativeportconverter_wdata_chunk_valid = ((user_port_litedramnativeportconverter_cmd_buffer_source_payload_sel & user_port_litedramnativeportconverter_wdata_chunk) != 1'd0);
always @(*) begin
    user_port_litedramnativeportconverter_wdata_converter_sink_payload_data <= 32'd0;
    if ((user_port_litedramnativeportconverter_cmd_buffer_source_valid & user_port_litedramnativeportconverter_cmd_buffer_source_payload_we)) begin
        if (user_port_litedramnativeportconverter_wdata_chunk_valid) begin
            user_port_litedramnativeportconverter_wdata_converter_sink_payload_data <= user_port_litedramnativeportconverter_wdata_fifo_source_payload_data;
        end else begin
        end
    end
end
always @(*) begin
    user_port_litedramnativeportconverter_wdata_converter_sink_payload_we <= 4'd0;
    if ((user_port_litedramnativeportconverter_cmd_buffer_source_valid & user_port_litedramnativeportconverter_cmd_buffer_source_payload_we)) begin
        if (user_port_litedramnativeportconverter_wdata_chunk_valid) begin
            user_port_litedramnativeportconverter_wdata_converter_sink_payload_we <= user_port_litedramnativeportconverter_wdata_fifo_source_payload_we;
        end else begin
        end
    end
end
always @(*) begin
    user_port_litedramnativeportconverter_wdata_fifo_source_ready <= 1'd0;
    if ((user_port_litedramnativeportconverter_cmd_buffer_source_valid & user_port_litedramnativeportconverter_cmd_buffer_source_payload_we)) begin
        if (user_port_litedramnativeportconverter_wdata_chunk_valid) begin
            user_port_litedramnativeportconverter_wdata_fifo_source_ready <= user_port_litedramnativeportconverter_wdata_converter_sink_ready;
        end else begin
        end
    end
end
always @(*) begin
    user_port_litedramnativeportconverter_wdata_converter_sink_valid <= 1'd0;
    if ((user_port_litedramnativeportconverter_cmd_buffer_source_valid & user_port_litedramnativeportconverter_cmd_buffer_source_payload_we)) begin
        if (user_port_litedramnativeportconverter_wdata_chunk_valid) begin
            user_port_litedramnativeportconverter_wdata_converter_sink_valid <= user_port_litedramnativeportconverter_wdata_fifo_source_valid;
        end else begin
            user_port_litedramnativeportconverter_wdata_converter_sink_valid <= 1'd1;
        end
    end
end
assign user_port_litedramnativeportconverter_wdata_buffer_sink_sink_valid = user_port_litedramnativeportconverter_wdata_converter_source_valid;
assign user_port_litedramnativeportconverter_wdata_buffer_sink_sink_payload_data = user_port_litedramnativeportconverter_wdata_converter_source_payload_data;
assign user_port_litedramnativeportconverter_wdata_buffer_sink_sink_payload_we = (user_port_litedramnativeportconverter_wdata_converter_source_payload_we & user_port_litedramnativeportconverter_wdata_sel);
assign user_port_litedramnativeportconverter_wdata_converter_source_ready = user_port_litedramnativeportconverter_wdata_buffer_sink_sink_ready;
assign user_port_litedramnativeportconverter_wdata_finished = ((user_port_litedramnativeportconverter_wdata_converter_sink_valid & user_port_litedramnativeportconverter_wdata_converter_sink_ready) & user_port_litedramnativeportconverter_wdata_chunk[7]);
assign user_port_litedramnativeportconverter_cmd_buffer_source_valid = user_port_litedramnativeportconverter_cmd_buffer_sink_valid;
assign user_port_litedramnativeportconverter_cmd_buffer_sink_ready = user_port_litedramnativeportconverter_cmd_buffer_source_ready;
assign user_port_litedramnativeportconverter_cmd_buffer_source_first = user_port_litedramnativeportconverter_cmd_buffer_sink_first;
assign user_port_litedramnativeportconverter_cmd_buffer_source_last = user_port_litedramnativeportconverter_cmd_buffer_sink_last;
assign user_port_litedramnativeportconverter_cmd_buffer_source_payload_sel = user_port_litedramnativeportconverter_cmd_buffer_sink_payload_sel;
assign user_port_litedramnativeportconverter_cmd_buffer_source_payload_we = user_port_litedramnativeportconverter_cmd_buffer_sink_payload_we;
always @(*) begin
    litedramcore_next_state <= 2'd0;
    litedramcore_next_state <= litedramcore_state;
    case (litedramcore_state)
        1'd1: begin
            if (user_port_port_cmd_ready) begin
                if (user_port_litedramnativeportconverter_cmd_we) begin
                    litedramcore_next_state <= 1'd0;
                end else begin
                    litedramcore_next_state <= 2'd2;
                end
            end
        end
        2'd2: begin
            if (user_port_litedramnativeportconverter_next_cmd) begin
                litedramcore_next_state <= 2'd3;
            end else begin
            end
        end
        2'd3: begin
            if (user_port_litedramnativeportconverter_cmd_buffer_sink_ready) begin
                if (user_port_litedramnativeportconverter_cmd_we) begin
                    litedramcore_next_state <= 1'd1;
                end else begin
                    litedramcore_next_state <= 1'd0;
                end
            end
        end
        default: begin
            if (user_port_new_port_cmd_ready) begin
                if (user_port_new_port_cmd_payload_we) begin
                    litedramcore_next_state <= 2'd2;
                end else begin
                    litedramcore_next_state <= 1'd1;
                end
            end
        end
    endcase
end
always @(*) begin
    user_port_litedramnativeportconverter_cmd_addr_litedramcore_next_value0 <= 28'd0;
    case (litedramcore_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        default: begin
            if (user_port_new_port_cmd_ready) begin
                user_port_litedramnativeportconverter_cmd_addr_litedramcore_next_value0 <= user_port_new_port_cmd_payload_addr;
            end
        end
    endcase
end
always @(*) begin
    user_port_litedramnativeportconverter_cmd_buffer_sink_payload_we <= 1'd0;
    case (litedramcore_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
            user_port_litedramnativeportconverter_cmd_buffer_sink_payload_we <= user_port_litedramnativeportconverter_cmd_we;
        end
        default: begin
        end
    endcase
end
always @(*) begin
    user_port_litedramnativeportconverter_cmd_addr_litedramcore_next_value_ce0 <= 1'd0;
    case (litedramcore_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        default: begin
            if (user_port_new_port_cmd_ready) begin
                user_port_litedramnativeportconverter_cmd_addr_litedramcore_next_value_ce0 <= 1'd1;
            end
        end
    endcase
end
always @(*) begin
    user_port_litedramnativeportconverter_cmd_we_litedramcore_next_value1 <= 1'd0;
    case (litedramcore_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        default: begin
            if (user_port_new_port_cmd_ready) begin
                user_port_litedramnativeportconverter_cmd_we_litedramcore_next_value1 <= user_port_new_port_cmd_payload_we;
            end
        end
    endcase
end
always @(*) begin
    user_port_litedramnativeportconverter_cmd_we_litedramcore_next_value_ce1 <= 1'd0;
    case (litedramcore_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
        end
        default: begin
            if (user_port_new_port_cmd_ready) begin
                user_port_litedramnativeportconverter_cmd_we_litedramcore_next_value_ce1 <= 1'd1;
            end
        end
    endcase
end
always @(*) begin
    user_port_litedramnativeportconverter_cmd_buffer_sink_valid <= 1'd0;
    case (litedramcore_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
            user_port_litedramnativeportconverter_cmd_buffer_sink_valid <= 1'd1;
        end
        default: begin
        end
    endcase
end
always @(*) begin
    user_port_litedramnativeportconverter_cmd_last_litedramcore_next_value2 <= 1'd0;
    case (litedramcore_state)
        1'd1: begin
        end
        2'd2: begin
            if (user_port_litedramnativeportconverter_next_cmd) begin
            end else begin
                user_port_litedramnativeportconverter_cmd_last_litedramcore_next_value2 <= user_port_new_port_cmd_last;
            end
        end
        2'd3: begin
        end
        default: begin
            if (user_port_new_port_cmd_ready) begin
                user_port_litedramnativeportconverter_cmd_last_litedramcore_next_value2 <= user_port_new_port_cmd_last;
            end
        end
    endcase
end
always @(*) begin
    user_port_litedramnativeportconverter_cmd_last_litedramcore_next_value_ce2 <= 1'd0;
    case (litedramcore_state)
        1'd1: begin
        end
        2'd2: begin
            if (user_port_litedramnativeportconverter_next_cmd) begin
            end else begin
                user_port_litedramnativeportconverter_cmd_last_litedramcore_next_value_ce2 <= 1'd1;
            end
        end
        2'd3: begin
        end
        default: begin
            if (user_port_new_port_cmd_ready) begin
                user_port_litedramnativeportconverter_cmd_last_litedramcore_next_value_ce2 <= 1'd1;
            end
        end
    endcase
end
always @(*) begin
    user_port_port_cmd_valid <= 1'd0;
    case (litedramcore_state)
        1'd1: begin
            user_port_port_cmd_valid <= 1'd1;
        end
        2'd2: begin
        end
        2'd3: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    user_port_litedramnativeportconverter_sel_litedramcore_next_value3 <= 8'd0;
    case (litedramcore_state)
        1'd1: begin
        end
        2'd2: begin
            if (user_port_litedramnativeportconverter_next_cmd) begin
            end else begin
                if (user_port_new_port_cmd_valid) begin
                    user_port_litedramnativeportconverter_sel_litedramcore_next_value3 <= (user_port_litedramnativeportconverter_sel | (1'd1 <<< user_port_new_port_cmd_payload_addr[2:0]));
                end
            end
        end
        2'd3: begin
        end
        default: begin
            if (user_port_new_port_cmd_ready) begin
                user_port_litedramnativeportconverter_sel_litedramcore_next_value3 <= (1'd1 <<< user_port_new_port_cmd_payload_addr[2:0]);
            end
        end
    endcase
end
always @(*) begin
    user_port_litedramnativeportconverter_sel_litedramcore_next_value_ce3 <= 1'd0;
    case (litedramcore_state)
        1'd1: begin
        end
        2'd2: begin
            if (user_port_litedramnativeportconverter_next_cmd) begin
            end else begin
                if (user_port_new_port_cmd_valid) begin
                    user_port_litedramnativeportconverter_sel_litedramcore_next_value_ce3 <= 1'd1;
                end
            end
        end
        2'd3: begin
        end
        default: begin
            if (user_port_new_port_cmd_ready) begin
                user_port_litedramnativeportconverter_sel_litedramcore_next_value_ce3 <= 1'd1;
            end
        end
    endcase
end
always @(*) begin
    user_port_new_port_cmd_ready <= 1'd0;
    case (litedramcore_state)
        1'd1: begin
        end
        2'd2: begin
            if (user_port_litedramnativeportconverter_next_cmd) begin
            end else begin
                user_port_new_port_cmd_ready <= user_port_new_port_cmd_valid;
            end
        end
        2'd3: begin
        end
        default: begin
            user_port_new_port_cmd_ready <= (user_port_new_port_cmd_valid & (~user_port_litedramnativeportconverter_read_lock));
        end
    endcase
end
always @(*) begin
    user_port_port_cmd_payload_we <= 1'd0;
    case (litedramcore_state)
        1'd1: begin
            user_port_port_cmd_payload_we <= user_port_litedramnativeportconverter_cmd_we;
        end
        2'd2: begin
        end
        2'd3: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    user_port_port_cmd_payload_addr <= 25'd0;
    case (litedramcore_state)
        1'd1: begin
            user_port_port_cmd_payload_addr <= user_port_litedramnativeportconverter_cmd_addr[27:3];
        end
        2'd2: begin
        end
        2'd3: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    user_port_litedramnativeportconverter_cmd_buffer_sink_payload_sel <= 8'd0;
    case (litedramcore_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
            user_port_litedramnativeportconverter_cmd_buffer_sink_payload_sel <= user_port_litedramnativeportconverter_sel;
        end
        default: begin
        end
    endcase
end
assign user_port_litedramnativeportconverter_rdata_fifo_syncfifo_din = {user_port_litedramnativeportconverter_rdata_fifo_fifo_in_last, user_port_litedramnativeportconverter_rdata_fifo_fifo_in_first, user_port_litedramnativeportconverter_rdata_fifo_fifo_in_payload_data};
assign {user_port_litedramnativeportconverter_rdata_fifo_fifo_out_last, user_port_litedramnativeportconverter_rdata_fifo_fifo_out_first, user_port_litedramnativeportconverter_rdata_fifo_fifo_out_payload_data} = user_port_litedramnativeportconverter_rdata_fifo_syncfifo_dout;
assign {user_port_litedramnativeportconverter_rdata_fifo_fifo_out_last, user_port_litedramnativeportconverter_rdata_fifo_fifo_out_first, user_port_litedramnativeportconverter_rdata_fifo_fifo_out_payload_data} = user_port_litedramnativeportconverter_rdata_fifo_syncfifo_dout;
assign {user_port_litedramnativeportconverter_rdata_fifo_fifo_out_last, user_port_litedramnativeportconverter_rdata_fifo_fifo_out_first, user_port_litedramnativeportconverter_rdata_fifo_fifo_out_payload_data} = user_port_litedramnativeportconverter_rdata_fifo_syncfifo_dout;
assign user_port_litedramnativeportconverter_rdata_fifo_sink_ready = user_port_litedramnativeportconverter_rdata_fifo_syncfifo_writable;
assign user_port_litedramnativeportconverter_rdata_fifo_syncfifo_we = user_port_litedramnativeportconverter_rdata_fifo_sink_valid;
assign user_port_litedramnativeportconverter_rdata_fifo_fifo_in_first = user_port_litedramnativeportconverter_rdata_fifo_sink_first;
assign user_port_litedramnativeportconverter_rdata_fifo_fifo_in_last = user_port_litedramnativeportconverter_rdata_fifo_sink_last;
assign user_port_litedramnativeportconverter_rdata_fifo_fifo_in_payload_data = user_port_litedramnativeportconverter_rdata_fifo_sink_payload_data;
assign user_port_litedramnativeportconverter_rdata_fifo_source_valid = user_port_litedramnativeportconverter_rdata_fifo_syncfifo_readable;
assign user_port_litedramnativeportconverter_rdata_fifo_source_first = user_port_litedramnativeportconverter_rdata_fifo_fifo_out_first;
assign user_port_litedramnativeportconverter_rdata_fifo_source_last = user_port_litedramnativeportconverter_rdata_fifo_fifo_out_last;
assign user_port_litedramnativeportconverter_rdata_fifo_source_payload_data = user_port_litedramnativeportconverter_rdata_fifo_fifo_out_payload_data;
assign user_port_litedramnativeportconverter_rdata_fifo_syncfifo_re = user_port_litedramnativeportconverter_rdata_fifo_source_ready;
always @(*) begin
    user_port_litedramnativeportconverter_rdata_fifo_wrport_adr <= 3'd0;
    if (user_port_litedramnativeportconverter_rdata_fifo_replace) begin
        user_port_litedramnativeportconverter_rdata_fifo_wrport_adr <= (user_port_litedramnativeportconverter_rdata_fifo_produce - 1'd1);
    end else begin
        user_port_litedramnativeportconverter_rdata_fifo_wrport_adr <= user_port_litedramnativeportconverter_rdata_fifo_produce;
    end
end
assign user_port_litedramnativeportconverter_rdata_fifo_wrport_dat_w = user_port_litedramnativeportconverter_rdata_fifo_syncfifo_din;
assign user_port_litedramnativeportconverter_rdata_fifo_wrport_we = (user_port_litedramnativeportconverter_rdata_fifo_syncfifo_we & (user_port_litedramnativeportconverter_rdata_fifo_syncfifo_writable | user_port_litedramnativeportconverter_rdata_fifo_replace));
assign user_port_litedramnativeportconverter_rdata_fifo_do_read = (user_port_litedramnativeportconverter_rdata_fifo_syncfifo_readable & user_port_litedramnativeportconverter_rdata_fifo_syncfifo_re);
assign user_port_litedramnativeportconverter_rdata_fifo_rdport_adr = user_port_litedramnativeportconverter_rdata_fifo_consume;
assign user_port_litedramnativeportconverter_rdata_fifo_syncfifo_dout = user_port_litedramnativeportconverter_rdata_fifo_rdport_dat_r;
assign user_port_litedramnativeportconverter_rdata_fifo_syncfifo_writable = (user_port_litedramnativeportconverter_rdata_fifo_level != 3'd7);
assign user_port_litedramnativeportconverter_rdata_fifo_syncfifo_readable = (user_port_litedramnativeportconverter_rdata_fifo_level != 1'd0);
assign user_port_litedramnativeportconverter_rdata_converter_converter_sink_valid = user_port_litedramnativeportconverter_rdata_converter_sink_valid;
assign user_port_litedramnativeportconverter_rdata_converter_converter_sink_first = user_port_litedramnativeportconverter_rdata_converter_sink_first;
assign user_port_litedramnativeportconverter_rdata_converter_converter_sink_last = user_port_litedramnativeportconverter_rdata_converter_sink_last;
assign user_port_litedramnativeportconverter_rdata_converter_sink_ready = user_port_litedramnativeportconverter_rdata_converter_converter_sink_ready;
always @(*) begin
    user_port_litedramnativeportconverter_rdata_converter_converter_sink_payload_data <= 256'd0;
    user_port_litedramnativeportconverter_rdata_converter_converter_sink_payload_data[31:0] <= user_port_litedramnativeportconverter_rdata_converter_sink_payload_data[31:0];
    user_port_litedramnativeportconverter_rdata_converter_converter_sink_payload_data[63:32] <= user_port_litedramnativeportconverter_rdata_converter_sink_payload_data[63:32];
    user_port_litedramnativeportconverter_rdata_converter_converter_sink_payload_data[95:64] <= user_port_litedramnativeportconverter_rdata_converter_sink_payload_data[95:64];
    user_port_litedramnativeportconverter_rdata_converter_converter_sink_payload_data[127:96] <= user_port_litedramnativeportconverter_rdata_converter_sink_payload_data[127:96];
    user_port_litedramnativeportconverter_rdata_converter_converter_sink_payload_data[159:128] <= user_port_litedramnativeportconverter_rdata_converter_sink_payload_data[159:128];
    user_port_litedramnativeportconverter_rdata_converter_converter_sink_payload_data[191:160] <= user_port_litedramnativeportconverter_rdata_converter_sink_payload_data[191:160];
    user_port_litedramnativeportconverter_rdata_converter_converter_sink_payload_data[223:192] <= user_port_litedramnativeportconverter_rdata_converter_sink_payload_data[223:192];
    user_port_litedramnativeportconverter_rdata_converter_converter_sink_payload_data[255:224] <= user_port_litedramnativeportconverter_rdata_converter_sink_payload_data[255:224];
end
assign user_port_litedramnativeportconverter_rdata_converter_source_valid = user_port_litedramnativeportconverter_rdata_converter_source_source_valid;
assign user_port_litedramnativeportconverter_rdata_converter_source_first = user_port_litedramnativeportconverter_rdata_converter_source_source_first;
assign user_port_litedramnativeportconverter_rdata_converter_source_last = user_port_litedramnativeportconverter_rdata_converter_source_source_last;
assign user_port_litedramnativeportconverter_rdata_converter_source_source_ready = user_port_litedramnativeportconverter_rdata_converter_source_ready;
assign {user_port_litedramnativeportconverter_rdata_converter_source_payload_data} = user_port_litedramnativeportconverter_rdata_converter_source_source_payload_data;
assign user_port_litedramnativeportconverter_rdata_converter_source_source_valid = user_port_litedramnativeportconverter_rdata_converter_converter_source_valid;
assign user_port_litedramnativeportconverter_rdata_converter_converter_source_ready = user_port_litedramnativeportconverter_rdata_converter_source_source_ready;
assign user_port_litedramnativeportconverter_rdata_converter_source_source_first = user_port_litedramnativeportconverter_rdata_converter_converter_source_first;
assign user_port_litedramnativeportconverter_rdata_converter_source_source_last = user_port_litedramnativeportconverter_rdata_converter_converter_source_last;
assign user_port_litedramnativeportconverter_rdata_converter_source_source_payload_data = user_port_litedramnativeportconverter_rdata_converter_converter_source_payload_data;
assign user_port_litedramnativeportconverter_rdata_converter_converter_first = (user_port_litedramnativeportconverter_rdata_converter_converter_mux == 1'd0);
assign user_port_litedramnativeportconverter_rdata_converter_converter_last = (user_port_litedramnativeportconverter_rdata_converter_converter_mux == 3'd7);
assign user_port_litedramnativeportconverter_rdata_converter_converter_source_valid = user_port_litedramnativeportconverter_rdata_converter_converter_sink_valid;
assign user_port_litedramnativeportconverter_rdata_converter_converter_source_first = (user_port_litedramnativeportconverter_rdata_converter_converter_sink_first & user_port_litedramnativeportconverter_rdata_converter_converter_first);
assign user_port_litedramnativeportconverter_rdata_converter_converter_source_last = (user_port_litedramnativeportconverter_rdata_converter_converter_sink_last & user_port_litedramnativeportconverter_rdata_converter_converter_last);
assign user_port_litedramnativeportconverter_rdata_converter_converter_sink_ready = (user_port_litedramnativeportconverter_rdata_converter_converter_last & user_port_litedramnativeportconverter_rdata_converter_converter_source_ready);
always @(*) begin
    user_port_litedramnativeportconverter_rdata_converter_converter_source_payload_data <= 32'd0;
    case (user_port_litedramnativeportconverter_rdata_converter_converter_mux)
        1'd0: begin
            user_port_litedramnativeportconverter_rdata_converter_converter_source_payload_data <= user_port_litedramnativeportconverter_rdata_converter_converter_sink_payload_data[31:0];
        end
        1'd1: begin
            user_port_litedramnativeportconverter_rdata_converter_converter_source_payload_data <= user_port_litedramnativeportconverter_rdata_converter_converter_sink_payload_data[63:32];
        end
        2'd2: begin
            user_port_litedramnativeportconverter_rdata_converter_converter_source_payload_data <= user_port_litedramnativeportconverter_rdata_converter_converter_sink_payload_data[95:64];
        end
        2'd3: begin
            user_port_litedramnativeportconverter_rdata_converter_converter_source_payload_data <= user_port_litedramnativeportconverter_rdata_converter_converter_sink_payload_data[127:96];
        end
        3'd4: begin
            user_port_litedramnativeportconverter_rdata_converter_converter_source_payload_data <= user_port_litedramnativeportconverter_rdata_converter_converter_sink_payload_data[159:128];
        end
        3'd5: begin
            user_port_litedramnativeportconverter_rdata_converter_converter_source_payload_data <= user_port_litedramnativeportconverter_rdata_converter_converter_sink_payload_data[191:160];
        end
        3'd6: begin
            user_port_litedramnativeportconverter_rdata_converter_converter_source_payload_data <= user_port_litedramnativeportconverter_rdata_converter_converter_sink_payload_data[223:192];
        end
        default: begin
            user_port_litedramnativeportconverter_rdata_converter_converter_source_payload_data <= user_port_litedramnativeportconverter_rdata_converter_converter_sink_payload_data[255:224];
        end
    endcase
end
assign user_port_litedramnativeportconverter_rdata_converter_converter_source_payload_valid_token_count = user_port_litedramnativeportconverter_rdata_converter_converter_last;
assign user_port_litedramnativeportconverter_wdata_converter_converter_sink_valid = user_port_litedramnativeportconverter_wdata_converter_sink_valid;
assign user_port_litedramnativeportconverter_wdata_converter_converter_sink_first = user_port_litedramnativeportconverter_wdata_converter_sink_first;
assign user_port_litedramnativeportconverter_wdata_converter_converter_sink_last = user_port_litedramnativeportconverter_wdata_converter_sink_last;
assign user_port_litedramnativeportconverter_wdata_converter_sink_ready = user_port_litedramnativeportconverter_wdata_converter_converter_sink_ready;
assign user_port_litedramnativeportconverter_wdata_converter_converter_sink_payload_data = {user_port_litedramnativeportconverter_wdata_converter_sink_payload_we, user_port_litedramnativeportconverter_wdata_converter_sink_payload_data};
assign user_port_litedramnativeportconverter_wdata_converter_source_valid = user_port_litedramnativeportconverter_wdata_converter_source_source_valid;
assign user_port_litedramnativeportconverter_wdata_converter_source_first = user_port_litedramnativeportconverter_wdata_converter_source_source_first;
assign user_port_litedramnativeportconverter_wdata_converter_source_last = user_port_litedramnativeportconverter_wdata_converter_source_source_last;
assign user_port_litedramnativeportconverter_wdata_converter_source_source_ready = user_port_litedramnativeportconverter_wdata_converter_source_ready;
always @(*) begin
    user_port_litedramnativeportconverter_wdata_converter_source_payload_data <= 256'd0;
    user_port_litedramnativeportconverter_wdata_converter_source_payload_data[31:0] <= user_port_litedramnativeportconverter_wdata_converter_source_source_payload_data[31:0];
    user_port_litedramnativeportconverter_wdata_converter_source_payload_data[63:32] <= user_port_litedramnativeportconverter_wdata_converter_source_source_payload_data[67:36];
    user_port_litedramnativeportconverter_wdata_converter_source_payload_data[95:64] <= user_port_litedramnativeportconverter_wdata_converter_source_source_payload_data[103:72];
    user_port_litedramnativeportconverter_wdata_converter_source_payload_data[127:96] <= user_port_litedramnativeportconverter_wdata_converter_source_source_payload_data[139:108];
    user_port_litedramnativeportconverter_wdata_converter_source_payload_data[159:128] <= user_port_litedramnativeportconverter_wdata_converter_source_source_payload_data[175:144];
    user_port_litedramnativeportconverter_wdata_converter_source_payload_data[191:160] <= user_port_litedramnativeportconverter_wdata_converter_source_source_payload_data[211:180];
    user_port_litedramnativeportconverter_wdata_converter_source_payload_data[223:192] <= user_port_litedramnativeportconverter_wdata_converter_source_source_payload_data[247:216];
    user_port_litedramnativeportconverter_wdata_converter_source_payload_data[255:224] <= user_port_litedramnativeportconverter_wdata_converter_source_source_payload_data[283:252];
end
always @(*) begin
    user_port_litedramnativeportconverter_wdata_converter_source_payload_we <= 32'd0;
    user_port_litedramnativeportconverter_wdata_converter_source_payload_we[3:0] <= user_port_litedramnativeportconverter_wdata_converter_source_source_payload_data[35:32];
    user_port_litedramnativeportconverter_wdata_converter_source_payload_we[7:4] <= user_port_litedramnativeportconverter_wdata_converter_source_source_payload_data[71:68];
    user_port_litedramnativeportconverter_wdata_converter_source_payload_we[11:8] <= user_port_litedramnativeportconverter_wdata_converter_source_source_payload_data[107:104];
    user_port_litedramnativeportconverter_wdata_converter_source_payload_we[15:12] <= user_port_litedramnativeportconverter_wdata_converter_source_source_payload_data[143:140];
    user_port_litedramnativeportconverter_wdata_converter_source_payload_we[19:16] <= user_port_litedramnativeportconverter_wdata_converter_source_source_payload_data[179:176];
    user_port_litedramnativeportconverter_wdata_converter_source_payload_we[23:20] <= user_port_litedramnativeportconverter_wdata_converter_source_source_payload_data[215:212];
    user_port_litedramnativeportconverter_wdata_converter_source_payload_we[27:24] <= user_port_litedramnativeportconverter_wdata_converter_source_source_payload_data[251:248];
    user_port_litedramnativeportconverter_wdata_converter_source_payload_we[31:28] <= user_port_litedramnativeportconverter_wdata_converter_source_source_payload_data[287:284];
end
assign user_port_litedramnativeportconverter_wdata_converter_source_source_valid = user_port_litedramnativeportconverter_wdata_converter_converter_source_valid;
assign user_port_litedramnativeportconverter_wdata_converter_converter_source_ready = user_port_litedramnativeportconverter_wdata_converter_source_source_ready;
assign user_port_litedramnativeportconverter_wdata_converter_source_source_first = user_port_litedramnativeportconverter_wdata_converter_converter_source_first;
assign user_port_litedramnativeportconverter_wdata_converter_source_source_last = user_port_litedramnativeportconverter_wdata_converter_converter_source_last;
assign user_port_litedramnativeportconverter_wdata_converter_source_source_payload_data = user_port_litedramnativeportconverter_wdata_converter_converter_source_payload_data;
assign user_port_litedramnativeportconverter_wdata_converter_converter_sink_ready = ((~user_port_litedramnativeportconverter_wdata_converter_converter_strobe_all) | user_port_litedramnativeportconverter_wdata_converter_converter_source_ready);
assign user_port_litedramnativeportconverter_wdata_converter_converter_source_valid = user_port_litedramnativeportconverter_wdata_converter_converter_strobe_all;
assign user_port_litedramnativeportconverter_wdata_converter_converter_load_part = (user_port_litedramnativeportconverter_wdata_converter_converter_sink_valid & user_port_litedramnativeportconverter_wdata_converter_converter_sink_ready);
assign user_port_litedramnativeportconverter_wdata_fifo_syncfifo_din = {user_port_litedramnativeportconverter_wdata_fifo_fifo_in_last, user_port_litedramnativeportconverter_wdata_fifo_fifo_in_first, user_port_litedramnativeportconverter_wdata_fifo_fifo_in_payload_we, user_port_litedramnativeportconverter_wdata_fifo_fifo_in_payload_data};
assign {user_port_litedramnativeportconverter_wdata_fifo_fifo_out_last, user_port_litedramnativeportconverter_wdata_fifo_fifo_out_first, user_port_litedramnativeportconverter_wdata_fifo_fifo_out_payload_we, user_port_litedramnativeportconverter_wdata_fifo_fifo_out_payload_data} = user_port_litedramnativeportconverter_wdata_fifo_syncfifo_dout;
assign {user_port_litedramnativeportconverter_wdata_fifo_fifo_out_last, user_port_litedramnativeportconverter_wdata_fifo_fifo_out_first, user_port_litedramnativeportconverter_wdata_fifo_fifo_out_payload_we, user_port_litedramnativeportconverter_wdata_fifo_fifo_out_payload_data} = user_port_litedramnativeportconverter_wdata_fifo_syncfifo_dout;
assign {user_port_litedramnativeportconverter_wdata_fifo_fifo_out_last, user_port_litedramnativeportconverter_wdata_fifo_fifo_out_first, user_port_litedramnativeportconverter_wdata_fifo_fifo_out_payload_we, user_port_litedramnativeportconverter_wdata_fifo_fifo_out_payload_data} = user_port_litedramnativeportconverter_wdata_fifo_syncfifo_dout;
assign {user_port_litedramnativeportconverter_wdata_fifo_fifo_out_last, user_port_litedramnativeportconverter_wdata_fifo_fifo_out_first, user_port_litedramnativeportconverter_wdata_fifo_fifo_out_payload_we, user_port_litedramnativeportconverter_wdata_fifo_fifo_out_payload_data} = user_port_litedramnativeportconverter_wdata_fifo_syncfifo_dout;
assign user_port_litedramnativeportconverter_wdata_fifo_sink_ready = user_port_litedramnativeportconverter_wdata_fifo_syncfifo_writable;
assign user_port_litedramnativeportconverter_wdata_fifo_syncfifo_we = user_port_litedramnativeportconverter_wdata_fifo_sink_valid;
assign user_port_litedramnativeportconverter_wdata_fifo_fifo_in_first = user_port_litedramnativeportconverter_wdata_fifo_sink_first;
assign user_port_litedramnativeportconverter_wdata_fifo_fifo_in_last = user_port_litedramnativeportconverter_wdata_fifo_sink_last;
assign user_port_litedramnativeportconverter_wdata_fifo_fifo_in_payload_data = user_port_litedramnativeportconverter_wdata_fifo_sink_payload_data;
assign user_port_litedramnativeportconverter_wdata_fifo_fifo_in_payload_we = user_port_litedramnativeportconverter_wdata_fifo_sink_payload_we;
assign user_port_litedramnativeportconverter_wdata_fifo_source_valid = user_port_litedramnativeportconverter_wdata_fifo_syncfifo_readable;
assign user_port_litedramnativeportconverter_wdata_fifo_source_first = user_port_litedramnativeportconverter_wdata_fifo_fifo_out_first;
assign user_port_litedramnativeportconverter_wdata_fifo_source_last = user_port_litedramnativeportconverter_wdata_fifo_fifo_out_last;
assign user_port_litedramnativeportconverter_wdata_fifo_source_payload_data = user_port_litedramnativeportconverter_wdata_fifo_fifo_out_payload_data;
assign user_port_litedramnativeportconverter_wdata_fifo_source_payload_we = user_port_litedramnativeportconverter_wdata_fifo_fifo_out_payload_we;
assign user_port_litedramnativeportconverter_wdata_fifo_syncfifo_re = user_port_litedramnativeportconverter_wdata_fifo_source_ready;
always @(*) begin
    user_port_litedramnativeportconverter_wdata_fifo_wrport_adr <= 3'd0;
    if (user_port_litedramnativeportconverter_wdata_fifo_replace) begin
        user_port_litedramnativeportconverter_wdata_fifo_wrport_adr <= (user_port_litedramnativeportconverter_wdata_fifo_produce - 1'd1);
    end else begin
        user_port_litedramnativeportconverter_wdata_fifo_wrport_adr <= user_port_litedramnativeportconverter_wdata_fifo_produce;
    end
end
assign user_port_litedramnativeportconverter_wdata_fifo_wrport_dat_w = user_port_litedramnativeportconverter_wdata_fifo_syncfifo_din;
assign user_port_litedramnativeportconverter_wdata_fifo_wrport_we = (user_port_litedramnativeportconverter_wdata_fifo_syncfifo_we & (user_port_litedramnativeportconverter_wdata_fifo_syncfifo_writable | user_port_litedramnativeportconverter_wdata_fifo_replace));
assign user_port_litedramnativeportconverter_wdata_fifo_do_read = (user_port_litedramnativeportconverter_wdata_fifo_syncfifo_readable & user_port_litedramnativeportconverter_wdata_fifo_syncfifo_re);
assign user_port_litedramnativeportconverter_wdata_fifo_rdport_adr = user_port_litedramnativeportconverter_wdata_fifo_consume;
assign user_port_litedramnativeportconverter_wdata_fifo_syncfifo_dout = user_port_litedramnativeportconverter_wdata_fifo_rdport_dat_r;
assign user_port_litedramnativeportconverter_wdata_fifo_syncfifo_writable = (user_port_litedramnativeportconverter_wdata_fifo_level != 3'd7);
assign user_port_litedramnativeportconverter_wdata_fifo_syncfifo_readable = (user_port_litedramnativeportconverter_wdata_fifo_level != 1'd0);
assign user_port_litedramnativeportconverter_wdata_buffer_pipe_valid_sink_ready = ((~user_port_litedramnativeportconverter_wdata_buffer_pipe_valid_source_valid) | user_port_litedramnativeportconverter_wdata_buffer_pipe_valid_source_ready);
assign user_port_litedramnativeportconverter_wdata_buffer_pipe_valid_sink_valid = user_port_litedramnativeportconverter_wdata_buffer_sink_sink_valid;
assign user_port_litedramnativeportconverter_wdata_buffer_sink_sink_ready = user_port_litedramnativeportconverter_wdata_buffer_pipe_valid_sink_ready;
assign user_port_litedramnativeportconverter_wdata_buffer_pipe_valid_sink_first = user_port_litedramnativeportconverter_wdata_buffer_sink_sink_first;
assign user_port_litedramnativeportconverter_wdata_buffer_pipe_valid_sink_last = user_port_litedramnativeportconverter_wdata_buffer_sink_sink_last;
assign user_port_litedramnativeportconverter_wdata_buffer_pipe_valid_sink_payload_data = user_port_litedramnativeportconverter_wdata_buffer_sink_sink_payload_data;
assign user_port_litedramnativeportconverter_wdata_buffer_pipe_valid_sink_payload_we = user_port_litedramnativeportconverter_wdata_buffer_sink_sink_payload_we;
assign user_port_litedramnativeportconverter_wdata_buffer_source_source_valid = user_port_litedramnativeportconverter_wdata_buffer_pipe_valid_source_valid;
assign user_port_litedramnativeportconverter_wdata_buffer_pipe_valid_source_ready = user_port_litedramnativeportconverter_wdata_buffer_source_source_ready;
assign user_port_litedramnativeportconverter_wdata_buffer_source_source_first = user_port_litedramnativeportconverter_wdata_buffer_pipe_valid_source_first;
assign user_port_litedramnativeportconverter_wdata_buffer_source_source_last = user_port_litedramnativeportconverter_wdata_buffer_pipe_valid_source_last;
assign user_port_litedramnativeportconverter_wdata_buffer_source_source_payload_data = user_port_litedramnativeportconverter_wdata_buffer_pipe_valid_source_payload_data;
assign user_port_litedramnativeportconverter_wdata_buffer_source_source_payload_we = user_port_litedramnativeportconverter_wdata_buffer_pipe_valid_source_payload_we;
assign litedramcore_data_port_adr = litedramcore_wb_sdram_adr[3];
always @(*) begin
    litedramcore_data_port_we <= 32'd0;
    if (litedramcore_write_from_slave) begin
        litedramcore_data_port_we <= {32{1'd1}};
    end else begin
        if ((((litedramcore_wb_sdram_cyc & litedramcore_wb_sdram_stb) & litedramcore_wb_sdram_we) & litedramcore_wb_sdram_ack)) begin
            litedramcore_data_port_we <= {({4{(litedramcore_wb_sdram_adr[2:0] == 3'd7)}} & litedramcore_wb_sdram_sel), ({4{(litedramcore_wb_sdram_adr[2:0] == 3'd6)}} & litedramcore_wb_sdram_sel), ({4{(litedramcore_wb_sdram_adr[2:0] == 3'd5)}} & litedramcore_wb_sdram_sel), ({4{(litedramcore_wb_sdram_adr[2:0] == 3'd4)}} & litedramcore_wb_sdram_sel), ({4{(litedramcore_wb_sdram_adr[2:0] == 2'd3)}} & litedramcore_wb_sdram_sel), ({4{(litedramcore_wb_sdram_adr[2:0] == 2'd2)}} & litedramcore_wb_sdram_sel), ({4{(litedramcore_wb_sdram_adr[2:0] == 1'd1)}} & litedramcore_wb_sdram_sel), ({4{(litedramcore_wb_sdram_adr[2:0] == 1'd0)}} & litedramcore_wb_sdram_sel)};
        end
    end
end
always @(*) begin
    litedramcore_data_port_dat_w <= 256'd0;
    if (litedramcore_write_from_slave) begin
        litedramcore_data_port_dat_w <= litedramcore_interface_dat_r;
    end else begin
        litedramcore_data_port_dat_w <= {8{litedramcore_wb_sdram_dat_w}};
    end
end
assign litedramcore_interface_dat_w = litedramcore_data_port_dat_r;
assign litedramcore_interface_sel = 32'd4294967295;
always @(*) begin
    litedramcore_wb_sdram_dat_r <= 32'd0;
    case (litedramcore_adr_offset_r)
        1'd0: begin
            litedramcore_wb_sdram_dat_r <= litedramcore_data_port_dat_r[31:0];
        end
        1'd1: begin
            litedramcore_wb_sdram_dat_r <= litedramcore_data_port_dat_r[63:32];
        end
        2'd2: begin
            litedramcore_wb_sdram_dat_r <= litedramcore_data_port_dat_r[95:64];
        end
        2'd3: begin
            litedramcore_wb_sdram_dat_r <= litedramcore_data_port_dat_r[127:96];
        end
        3'd4: begin
            litedramcore_wb_sdram_dat_r <= litedramcore_data_port_dat_r[159:128];
        end
        3'd5: begin
            litedramcore_wb_sdram_dat_r <= litedramcore_data_port_dat_r[191:160];
        end
        3'd6: begin
            litedramcore_wb_sdram_dat_r <= litedramcore_data_port_dat_r[223:192];
        end
        default: begin
            litedramcore_wb_sdram_dat_r <= litedramcore_data_port_dat_r[255:224];
        end
    endcase
end
assign {litedramcore_tag_do_dirty, litedramcore_tag_do_tag} = litedramcore_tag_port_dat_r;
assign {litedramcore_tag_do_dirty, litedramcore_tag_do_tag} = litedramcore_tag_port_dat_r;
assign litedramcore_tag_port_dat_w = {litedramcore_tag_di_dirty, litedramcore_tag_di_tag};
assign litedramcore_tag_port_adr = litedramcore_wb_sdram_adr[3];
assign litedramcore_tag_di_tag = litedramcore_wb_sdram_adr[29:4];
assign litedramcore_interface_adr = {litedramcore_tag_do_tag, litedramcore_wb_sdram_adr[3]};
always @(*) begin
    fullmemorywe_next_state <= 2'd0;
    fullmemorywe_next_state <= fullmemorywe_state;
    case (fullmemorywe_state)
        1'd1: begin
            if ((litedramcore_tag_do_tag == litedramcore_wb_sdram_adr[29:4])) begin
                fullmemorywe_next_state <= 1'd0;
            end else begin
                if (litedramcore_tag_do_dirty) begin
                    fullmemorywe_next_state <= 2'd2;
                end else begin
                    fullmemorywe_next_state <= 2'd3;
                end
            end
        end
        2'd2: begin
            if (litedramcore_interface_ack) begin
                if (1'd1) begin
                    fullmemorywe_next_state <= 2'd3;
                end
            end
        end
        2'd3: begin
            if (litedramcore_interface_ack) begin
                if (1'd1) begin
                    fullmemorywe_next_state <= 1'd1;
                end else begin
                    fullmemorywe_next_state <= 2'd3;
                end
            end
        end
        default: begin
            if ((litedramcore_wb_sdram_cyc & litedramcore_wb_sdram_stb)) begin
                fullmemorywe_next_state <= 1'd1;
            end
        end
    endcase
end
always @(*) begin
    litedramcore_write_from_slave <= 1'd0;
    case (fullmemorywe_state)
        1'd1: begin
        end
        2'd2: begin
        end
        2'd3: begin
            if (litedramcore_interface_ack) begin
                litedramcore_write_from_slave <= 1'd1;
            end
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_tag_port_we <= 1'd0;
    case (fullmemorywe_state)
        1'd1: begin
            if ((litedramcore_tag_do_tag == litedramcore_wb_sdram_adr[29:4])) begin
                if (litedramcore_wb_sdram_we) begin
                    litedramcore_tag_port_we <= 1'd1;
                end
            end else begin
                if (litedramcore_tag_do_dirty) begin
                end else begin
                    litedramcore_tag_port_we <= 1'd1;
                end
            end
        end
        2'd2: begin
            if (litedramcore_interface_ack) begin
                if (1'd1) begin
                    litedramcore_tag_port_we <= 1'd1;
                end
            end
        end
        2'd3: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_interface_cyc <= 1'd0;
    case (fullmemorywe_state)
        1'd1: begin
        end
        2'd2: begin
            litedramcore_interface_cyc <= 1'd1;
        end
        2'd3: begin
            litedramcore_interface_cyc <= 1'd1;
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_interface_stb <= 1'd0;
    case (fullmemorywe_state)
        1'd1: begin
        end
        2'd2: begin
            litedramcore_interface_stb <= 1'd1;
        end
        2'd3: begin
            litedramcore_interface_stb <= 1'd1;
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_interface_we <= 1'd0;
    case (fullmemorywe_state)
        1'd1: begin
        end
        2'd2: begin
            litedramcore_interface_we <= 1'd1;
        end
        2'd3: begin
            litedramcore_interface_we <= 1'd0;
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_wb_sdram_ack <= 1'd0;
    case (fullmemorywe_state)
        1'd1: begin
            if ((litedramcore_tag_do_tag == litedramcore_wb_sdram_adr[29:4])) begin
                litedramcore_wb_sdram_ack <= 1'd1;
            end else begin
            end
        end
        2'd2: begin
        end
        2'd3: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_tag_di_dirty <= 1'd0;
    case (fullmemorywe_state)
        1'd1: begin
            if ((litedramcore_tag_do_tag == litedramcore_wb_sdram_adr[29:4])) begin
                if (litedramcore_wb_sdram_we) begin
                    litedramcore_tag_di_dirty <= 1'd1;
                end
            end else begin
            end
        end
        2'd2: begin
        end
        2'd3: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_word_clr <= 1'd0;
    case (fullmemorywe_state)
        1'd1: begin
            litedramcore_word_clr <= 1'd1;
            if ((litedramcore_tag_do_tag == litedramcore_wb_sdram_adr[29:4])) begin
            end else begin
                if (litedramcore_tag_do_dirty) begin
                end else begin
                    litedramcore_word_clr <= 1'd1;
                end
            end
        end
        2'd2: begin
            if (litedramcore_interface_ack) begin
                if (1'd1) begin
                    litedramcore_word_clr <= 1'd1;
                end
            end
        end
        2'd3: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_word_inc <= 1'd0;
    case (fullmemorywe_state)
        1'd1: begin
        end
        2'd2: begin
            if (litedramcore_interface_ack) begin
                litedramcore_word_inc <= 1'd1;
            end
        end
        2'd3: begin
            if (litedramcore_interface_ack) begin
                litedramcore_word_inc <= 1'd1;
            end
        end
        default: begin
        end
    endcase
end
assign litedramcore_port_cmd_payload_addr = (litedramcore_interface_adr - 26'd33554432);
assign litedramcore_port_cmd_payload_we = litedramcore_interface_we;
assign litedramcore_port_cmd_last = (~litedramcore_interface_we);
assign litedramcore_port_flush = (~litedramcore_interface_cyc);
always @(*) begin
    litedramcore_port_wdata_valid <= 1'd0;
    litedramcore_port_wdata_valid <= (litedramcore_interface_stb & litedramcore_interface_we);
    if (1'd1) begin
        if ((~litedramcore_is_ongoing)) begin
            litedramcore_port_wdata_valid <= 1'd0;
        end
    end
end
assign litedramcore_port_wdata_payload_data = litedramcore_interface_dat_w;
assign litedramcore_port_wdata_payload_we = litedramcore_interface_sel;
assign litedramcore_port_rdata_ready = 1'd1;
always @(*) begin
    litedramwishbone2native0_next_state <= 2'd0;
    litedramwishbone2native0_next_state <= litedramwishbone2native0_state;
    case (litedramwishbone2native0_state)
        1'd1: begin
            if ((litedramcore_port_wdata_valid & litedramcore_port_wdata_ready)) begin
                litedramwishbone2native0_next_state <= 1'd0;
            end
        end
        2'd2: begin
            if (litedramcore_port_rdata_valid) begin
                litedramwishbone2native0_next_state <= 1'd0;
            end
        end
        default: begin
            if (((litedramcore_port_cmd_valid & litedramcore_port_cmd_ready) & litedramcore_interface_we)) begin
                litedramwishbone2native0_next_state <= 1'd1;
            end
            if (((litedramcore_port_cmd_valid & litedramcore_port_cmd_ready) & (~litedramcore_interface_we))) begin
                litedramwishbone2native0_next_state <= 2'd2;
            end
        end
    endcase
end
always @(*) begin
    litedramcore_is_ongoing <= 1'd0;
    case (litedramwishbone2native0_state)
        1'd1: begin
            litedramcore_is_ongoing <= 1'd1;
        end
        2'd2: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_interface_dat_r <= 256'd0;
    case (litedramwishbone2native0_state)
        1'd1: begin
        end
        2'd2: begin
            if (litedramcore_port_rdata_valid) begin
                litedramcore_interface_dat_r <= litedramcore_port_rdata_payload_data;
            end
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_port_cmd_valid <= 1'd0;
    case (litedramwishbone2native0_state)
        1'd1: begin
        end
        2'd2: begin
        end
        default: begin
            litedramcore_port_cmd_valid <= (litedramcore_interface_cyc & litedramcore_interface_stb);
        end
    endcase
end
always @(*) begin
    litedramcore_aborted_litedramwishbone2native0_next_value <= 1'd0;
    case (litedramwishbone2native0_state)
        1'd1: begin
            litedramcore_aborted_litedramwishbone2native0_next_value <= ((~litedramcore_interface_cyc) | litedramcore_aborted);
        end
        2'd2: begin
            litedramcore_aborted_litedramwishbone2native0_next_value <= ((~litedramcore_interface_cyc) | litedramcore_aborted);
        end
        default: begin
            litedramcore_aborted_litedramwishbone2native0_next_value <= 1'd0;
        end
    endcase
end
always @(*) begin
    litedramcore_interface_ack <= 1'd0;
    case (litedramwishbone2native0_state)
        1'd1: begin
            if ((litedramcore_port_wdata_valid & litedramcore_port_wdata_ready)) begin
                litedramcore_interface_ack <= (litedramcore_interface_cyc & (~litedramcore_aborted));
            end
        end
        2'd2: begin
            if (litedramcore_port_rdata_valid) begin
                litedramcore_interface_ack <= (litedramcore_interface_cyc & (~litedramcore_aborted));
            end
        end
        default: begin
        end
    endcase
end
always @(*) begin
    litedramcore_aborted_litedramwishbone2native0_next_value_ce <= 1'd0;
    case (litedramwishbone2native0_state)
        1'd1: begin
            litedramcore_aborted_litedramwishbone2native0_next_value_ce <= 1'd1;
        end
        2'd2: begin
            litedramcore_aborted_litedramwishbone2native0_next_value_ce <= 1'd1;
        end
        default: begin
            litedramcore_aborted_litedramwishbone2native0_next_value_ce <= 1'd1;
        end
    endcase
end
assign user_port_new_port_cmd_payload_addr = (wb_port_adr - 1'd0);
assign user_port_new_port_cmd_payload_we = wb_port_we;
assign user_port_new_port_cmd_last = (~wb_port_we);
assign user_port_new_port_flush = (~wb_port_cyc);
always @(*) begin
    user_port_new_port_wdata_valid <= 1'd0;
    user_port_new_port_wdata_valid <= (wb_port_stb & wb_port_we);
    if (1'd1) begin
        if ((~wishbone2native_is_ongoing)) begin
            user_port_new_port_wdata_valid <= 1'd0;
        end
    end
end
assign user_port_new_port_wdata_payload_data = wb_port_dat_w;
assign user_port_new_port_wdata_payload_we = wb_port_sel;
assign user_port_new_port_rdata_ready = 1'd1;
always @(*) begin
    litedramwishbone2native1_next_state <= 2'd0;
    litedramwishbone2native1_next_state <= litedramwishbone2native1_state;
    case (litedramwishbone2native1_state)
        1'd1: begin
            if ((user_port_new_port_wdata_valid & user_port_new_port_wdata_ready)) begin
                litedramwishbone2native1_next_state <= 1'd0;
            end
        end
        2'd2: begin
            if (user_port_new_port_rdata_valid) begin
                litedramwishbone2native1_next_state <= 1'd0;
            end
        end
        default: begin
            if (((user_port_new_port_cmd_valid & user_port_new_port_cmd_ready) & wb_port_we)) begin
                litedramwishbone2native1_next_state <= 1'd1;
            end
            if (((user_port_new_port_cmd_valid & user_port_new_port_cmd_ready) & (~wb_port_we))) begin
                litedramwishbone2native1_next_state <= 2'd2;
            end
        end
    endcase
end
always @(*) begin
    wb_port_ack <= 1'd0;
    case (litedramwishbone2native1_state)
        1'd1: begin
            if ((user_port_new_port_wdata_valid & user_port_new_port_wdata_ready)) begin
                wb_port_ack <= (wb_port_cyc & (~wishbone2native_aborted));
            end
        end
        2'd2: begin
            if (user_port_new_port_rdata_valid) begin
                wb_port_ack <= (wb_port_cyc & (~wishbone2native_aborted));
            end
        end
        default: begin
        end
    endcase
end
always @(*) begin
    wishbone2native_aborted_litedramwishbone2native1_next_value <= 1'd0;
    case (litedramwishbone2native1_state)
        1'd1: begin
            wishbone2native_aborted_litedramwishbone2native1_next_value <= ((~wb_port_cyc) | wishbone2native_aborted);
        end
        2'd2: begin
            wishbone2native_aborted_litedramwishbone2native1_next_value <= ((~wb_port_cyc) | wishbone2native_aborted);
        end
        default: begin
            wishbone2native_aborted_litedramwishbone2native1_next_value <= 1'd0;
        end
    endcase
end
always @(*) begin
    user_port_new_port_cmd_valid <= 1'd0;
    case (litedramwishbone2native1_state)
        1'd1: begin
        end
        2'd2: begin
        end
        default: begin
            user_port_new_port_cmd_valid <= (wb_port_cyc & wb_port_stb);
        end
    endcase
end
always @(*) begin
    wishbone2native_aborted_litedramwishbone2native1_next_value_ce <= 1'd0;
    case (litedramwishbone2native1_state)
        1'd1: begin
            wishbone2native_aborted_litedramwishbone2native1_next_value_ce <= 1'd1;
        end
        2'd2: begin
            wishbone2native_aborted_litedramwishbone2native1_next_value_ce <= 1'd1;
        end
        default: begin
            wishbone2native_aborted_litedramwishbone2native1_next_value_ce <= 1'd1;
        end
    endcase
end
always @(*) begin
    wishbone2native_is_ongoing <= 1'd0;
    case (litedramwishbone2native1_state)
        1'd1: begin
            wishbone2native_is_ongoing <= 1'd1;
        end
        2'd2: begin
        end
        default: begin
        end
    endcase
end
always @(*) begin
    wb_port_dat_r <= 32'd0;
    case (litedramwishbone2native1_state)
        1'd1: begin
        end
        2'd2: begin
            if (user_port_new_port_rdata_valid) begin
                wb_port_dat_r <= user_port_new_port_rdata_payload_data;
            end
        end
        default: begin
        end
    endcase
end
always @(*) begin
    wishbone2csr_next_state <= 2'd0;
    wishbone2csr_next_state <= wishbone2csr_state;
    case (wishbone2csr_state)
        1'd1: begin
            wishbone2csr_next_state <= 2'd2;
        end
        2'd2: begin
            wishbone2csr_next_state <= 1'd0;
        end
        default: begin
            if ((interface0_cyc & interface0_stb)) begin
                wishbone2csr_next_state <= 1'd1;
            end
        end
    endcase
end
always @(*) begin
    interface0_dat_r <= 32'd0;
    case (wishbone2csr_state)
        1'd1: begin
        end
        2'd2: begin
            interface0_dat_r <= interface1_dat_r;
        end
        default: begin
        end
    endcase
end
always @(*) begin
    interface1_dat_w_wishbone2csr_next_value0 <= 32'd0;
    case (wishbone2csr_state)
        1'd1: begin
        end
        2'd2: begin
        end
        default: begin
            interface1_dat_w_wishbone2csr_next_value0 <= interface0_dat_w;
        end
    endcase
end
always @(*) begin
    interface1_dat_w_wishbone2csr_next_value_ce0 <= 1'd0;
    case (wishbone2csr_state)
        1'd1: begin
        end
        2'd2: begin
        end
        default: begin
            interface1_dat_w_wishbone2csr_next_value_ce0 <= 1'd1;
        end
    endcase
end
always @(*) begin
    interface0_ack <= 1'd0;
    case (wishbone2csr_state)
        1'd1: begin
        end
        2'd2: begin
            interface0_ack <= 1'd1;
        end
        default: begin
        end
    endcase
end
always @(*) begin
    interface1_adr_wishbone2csr_next_value1 <= 14'd0;
    case (wishbone2csr_state)
        1'd1: begin
            interface1_adr_wishbone2csr_next_value1 <= 1'd0;
        end
        2'd2: begin
        end
        default: begin
            if ((interface0_cyc & interface0_stb)) begin
                interface1_adr_wishbone2csr_next_value1 <= interface0_adr;
            end
        end
    endcase
end
always @(*) begin
    interface1_adr_wishbone2csr_next_value_ce1 <= 1'd0;
    case (wishbone2csr_state)
        1'd1: begin
            interface1_adr_wishbone2csr_next_value_ce1 <= 1'd1;
        end
        2'd2: begin
        end
        default: begin
            if ((interface0_cyc & interface0_stb)) begin
                interface1_adr_wishbone2csr_next_value_ce1 <= 1'd1;
            end
        end
    endcase
end
always @(*) begin
    interface1_re_wishbone2csr_next_value2 <= 1'd0;
    case (wishbone2csr_state)
        1'd1: begin
            interface1_re_wishbone2csr_next_value2 <= 1'd0;
        end
        2'd2: begin
        end
        default: begin
            if ((interface0_cyc & interface0_stb)) begin
                interface1_re_wishbone2csr_next_value2 <= ((~interface0_we) & (interface0_sel != 1'd0));
            end
        end
    endcase
end
always @(*) begin
    interface1_re_wishbone2csr_next_value_ce2 <= 1'd0;
    case (wishbone2csr_state)
        1'd1: begin
            interface1_re_wishbone2csr_next_value_ce2 <= 1'd1;
        end
        2'd2: begin
        end
        default: begin
            if ((interface0_cyc & interface0_stb)) begin
                interface1_re_wishbone2csr_next_value_ce2 <= 1'd1;
            end
        end
    endcase
end
always @(*) begin
    interface1_we_wishbone2csr_next_value3 <= 1'd0;
    case (wishbone2csr_state)
        1'd1: begin
            interface1_we_wishbone2csr_next_value3 <= 1'd0;
        end
        2'd2: begin
        end
        default: begin
            if ((interface0_cyc & interface0_stb)) begin
                interface1_we_wishbone2csr_next_value3 <= (interface0_we & (interface0_sel != 1'd0));
            end
        end
    endcase
end
always @(*) begin
    interface1_we_wishbone2csr_next_value_ce3 <= 1'd0;
    case (wishbone2csr_state)
        1'd1: begin
            interface1_we_wishbone2csr_next_value_ce3 <= 1'd1;
        end
        2'd2: begin
        end
        default: begin
            if ((interface0_cyc & interface0_stb)) begin
                interface1_we_wishbone2csr_next_value_ce3 <= 1'd1;
            end
        end
    endcase
end
assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0);
assign csrbank0_reset0_r = interface0_bank_bus_dat_w[1:0];
always @(*) begin
    csrbank0_reset0_we <= 1'd0;
    if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
        csrbank0_reset0_we <= interface0_bank_bus_re;
    end
end
always @(*) begin
    csrbank0_reset0_re <= 1'd0;
    if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
        csrbank0_reset0_re <= interface0_bank_bus_we;
    end
end
assign csrbank0_scratch0_r = interface0_bank_bus_dat_w;
always @(*) begin
    csrbank0_scratch0_re <= 1'd0;
    if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
        csrbank0_scratch0_re <= interface0_bank_bus_we;
    end
end
always @(*) begin
    csrbank0_scratch0_we <= 1'd0;
    if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
        csrbank0_scratch0_we <= interface0_bank_bus_re;
    end
end
assign csrbank0_bus_errors_r = interface0_bank_bus_dat_w;
always @(*) begin
    csrbank0_bus_errors_we <= 1'd0;
    if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 2'd2))) begin
        csrbank0_bus_errors_we <= interface0_bank_bus_re;
    end
end
always @(*) begin
    csrbank0_bus_errors_re <= 1'd0;
    if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 2'd2))) begin
        csrbank0_bus_errors_re <= interface0_bank_bus_we;
    end
end
always @(*) begin
    litedramcore_soc_rst <= 1'd0;
    if (litedramcore_reset_re) begin
        litedramcore_soc_rst <= litedramcore_reset_storage[0];
    end
end
assign litedramcore_cpu_rst = litedramcore_reset_storage[1];
assign csrbank0_reset0_w = litedramcore_reset_storage;
assign csrbank0_scratch0_w = litedramcore_scratch_storage;
assign csrbank0_bus_errors_w = litedramcore_bus_errors_status;
assign litedramcore_bus_errors_we = csrbank0_bus_errors_we;
assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1);
assign csrbank1_init_done0_r = interface1_bank_bus_dat_w[0];
always @(*) begin
    csrbank1_init_done0_re <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
        csrbank1_init_done0_re <= interface1_bank_bus_we;
    end
end
always @(*) begin
    csrbank1_init_done0_we <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
        csrbank1_init_done0_we <= interface1_bank_bus_re;
    end
end
assign csrbank1_init_error0_r = interface1_bank_bus_dat_w[0];
always @(*) begin
    csrbank1_init_error0_we <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
        csrbank1_init_error0_we <= interface1_bank_bus_re;
    end
end
always @(*) begin
    csrbank1_init_error0_re <= 1'd0;
    if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
        csrbank1_init_error0_re <= interface1_bank_bus_we;
    end
end
assign csrbank1_init_done0_w = init_done_storage;
assign csrbank1_init_error0_w = init_error_storage;
assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2);
assign csrbank2_rst0_r = interface2_bank_bus_dat_w[0];
always @(*) begin
    csrbank2_rst0_we <= 1'd0;
    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
        csrbank2_rst0_we <= interface2_bank_bus_re;
    end
end
always @(*) begin
    csrbank2_rst0_re <= 1'd0;
    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
        csrbank2_rst0_re <= interface2_bank_bus_we;
    end
end
assign csrbank2_dly_sel0_r = interface2_bank_bus_dat_w[3:0];
always @(*) begin
    csrbank2_dly_sel0_we <= 1'd0;
    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
        csrbank2_dly_sel0_we <= interface2_bank_bus_re;
    end
end
always @(*) begin
    csrbank2_dly_sel0_re <= 1'd0;
    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
        csrbank2_dly_sel0_re <= interface2_bank_bus_we;
    end
end
assign csrbank2_half_sys8x_taps0_r = interface2_bank_bus_dat_w[4:0];
always @(*) begin
    csrbank2_half_sys8x_taps0_re <= 1'd0;
    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
        csrbank2_half_sys8x_taps0_re <= interface2_bank_bus_we;
    end
end
always @(*) begin
    csrbank2_half_sys8x_taps0_we <= 1'd0;
    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
        csrbank2_half_sys8x_taps0_we <= interface2_bank_bus_re;
    end
end
assign csrbank2_wlevel_en0_r = interface2_bank_bus_dat_w[0];
always @(*) begin
    csrbank2_wlevel_en0_we <= 1'd0;
    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
        csrbank2_wlevel_en0_we <= interface2_bank_bus_re;
    end
end
always @(*) begin
    csrbank2_wlevel_en0_re <= 1'd0;
    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
        csrbank2_wlevel_en0_re <= interface2_bank_bus_we;
    end
end
assign k7ddrphy_wlevel_strobe_r = interface2_bank_bus_dat_w[0];
always @(*) begin
    k7ddrphy_wlevel_strobe_we <= 1'd0;
    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
        k7ddrphy_wlevel_strobe_we <= interface2_bank_bus_re;
    end
end
always @(*) begin
    k7ddrphy_wlevel_strobe_re <= 1'd0;
    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
        k7ddrphy_wlevel_strobe_re <= interface2_bank_bus_we;
    end
end
assign k7ddrphy_cdly_rst_r = interface2_bank_bus_dat_w[0];
always @(*) begin
    k7ddrphy_cdly_rst_we <= 1'd0;
    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
        k7ddrphy_cdly_rst_we <= interface2_bank_bus_re;
    end
end
always @(*) begin
    k7ddrphy_cdly_rst_re <= 1'd0;
    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
        k7ddrphy_cdly_rst_re <= interface2_bank_bus_we;
    end
end
assign k7ddrphy_cdly_inc_r = interface2_bank_bus_dat_w[0];
always @(*) begin
    k7ddrphy_cdly_inc_we <= 1'd0;
    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
        k7ddrphy_cdly_inc_we <= interface2_bank_bus_re;
    end
end
always @(*) begin
    k7ddrphy_cdly_inc_re <= 1'd0;
    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
        k7ddrphy_cdly_inc_re <= interface2_bank_bus_we;
    end
end
assign k7ddrphy_rdly_dq_rst_r = interface2_bank_bus_dat_w[0];
always @(*) begin
    k7ddrphy_rdly_dq_rst_we <= 1'd0;
    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
        k7ddrphy_rdly_dq_rst_we <= interface2_bank_bus_re;
    end
end
always @(*) begin
    k7ddrphy_rdly_dq_rst_re <= 1'd0;
    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
        k7ddrphy_rdly_dq_rst_re <= interface2_bank_bus_we;
    end
end
assign k7ddrphy_rdly_dq_inc_r = interface2_bank_bus_dat_w[0];
always @(*) begin
    k7ddrphy_rdly_dq_inc_re <= 1'd0;
    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
        k7ddrphy_rdly_dq_inc_re <= interface2_bank_bus_we;
    end
end
always @(*) begin
    k7ddrphy_rdly_dq_inc_we <= 1'd0;
    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
        k7ddrphy_rdly_dq_inc_we <= interface2_bank_bus_re;
    end
end
assign k7ddrphy_rdly_dq_bitslip_rst_r = interface2_bank_bus_dat_w[0];
always @(*) begin
    k7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
        k7ddrphy_rdly_dq_bitslip_rst_re <= interface2_bank_bus_we;
    end
end
always @(*) begin
    k7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
        k7ddrphy_rdly_dq_bitslip_rst_we <= interface2_bank_bus_re;
    end
end
assign k7ddrphy_rdly_dq_bitslip_r = interface2_bank_bus_dat_w[0];
always @(*) begin
    k7ddrphy_rdly_dq_bitslip_re <= 1'd0;
    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
        k7ddrphy_rdly_dq_bitslip_re <= interface2_bank_bus_we;
    end
end
always @(*) begin
    k7ddrphy_rdly_dq_bitslip_we <= 1'd0;
    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
        k7ddrphy_rdly_dq_bitslip_we <= interface2_bank_bus_re;
    end
end
assign k7ddrphy_wdly_dq_rst_r = interface2_bank_bus_dat_w[0];
always @(*) begin
    k7ddrphy_wdly_dq_rst_re <= 1'd0;
    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
        k7ddrphy_wdly_dq_rst_re <= interface2_bank_bus_we;
    end
end
always @(*) begin
    k7ddrphy_wdly_dq_rst_we <= 1'd0;
    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
        k7ddrphy_wdly_dq_rst_we <= interface2_bank_bus_re;
    end
end
assign k7ddrphy_wdly_dq_inc_r = interface2_bank_bus_dat_w[0];
always @(*) begin
    k7ddrphy_wdly_dq_inc_we <= 1'd0;
    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
        k7ddrphy_wdly_dq_inc_we <= interface2_bank_bus_re;
    end
end
always @(*) begin
    k7ddrphy_wdly_dq_inc_re <= 1'd0;
    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
        k7ddrphy_wdly_dq_inc_re <= interface2_bank_bus_we;
    end
end
assign k7ddrphy_wdly_dqs_rst_r = interface2_bank_bus_dat_w[0];
always @(*) begin
    k7ddrphy_wdly_dqs_rst_we <= 1'd0;
    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
        k7ddrphy_wdly_dqs_rst_we <= interface2_bank_bus_re;
    end
end
always @(*) begin
    k7ddrphy_wdly_dqs_rst_re <= 1'd0;
    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
        k7ddrphy_wdly_dqs_rst_re <= interface2_bank_bus_we;
    end
end
assign k7ddrphy_wdly_dqs_inc_r = interface2_bank_bus_dat_w[0];
always @(*) begin
    k7ddrphy_wdly_dqs_inc_we <= 1'd0;
    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
        k7ddrphy_wdly_dqs_inc_we <= interface2_bank_bus_re;
    end
end
always @(*) begin
    k7ddrphy_wdly_dqs_inc_re <= 1'd0;
    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
        k7ddrphy_wdly_dqs_inc_re <= interface2_bank_bus_we;
    end
end
assign k7ddrphy_wdly_dq_bitslip_rst_r = interface2_bank_bus_dat_w[0];
always @(*) begin
    k7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
        k7ddrphy_wdly_dq_bitslip_rst_we <= interface2_bank_bus_re;
    end
end
always @(*) begin
    k7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
        k7ddrphy_wdly_dq_bitslip_rst_re <= interface2_bank_bus_we;
    end
end
assign k7ddrphy_wdly_dq_bitslip_r = interface2_bank_bus_dat_w[0];
always @(*) begin
    k7ddrphy_wdly_dq_bitslip_re <= 1'd0;
    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
        k7ddrphy_wdly_dq_bitslip_re <= interface2_bank_bus_we;
    end
end
always @(*) begin
    k7ddrphy_wdly_dq_bitslip_we <= 1'd0;
    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
        k7ddrphy_wdly_dq_bitslip_we <= interface2_bank_bus_re;
    end
end
assign csrbank2_rdphase0_r = interface2_bank_bus_dat_w[1:0];
always @(*) begin
    csrbank2_rdphase0_re <= 1'd0;
    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin
        csrbank2_rdphase0_re <= interface2_bank_bus_we;
    end
end
always @(*) begin
    csrbank2_rdphase0_we <= 1'd0;
    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin
        csrbank2_rdphase0_we <= interface2_bank_bus_re;
    end
end
assign csrbank2_wrphase0_r = interface2_bank_bus_dat_w[1:0];
always @(*) begin
    csrbank2_wrphase0_re <= 1'd0;
    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin
        csrbank2_wrphase0_re <= interface2_bank_bus_we;
    end
end
always @(*) begin
    csrbank2_wrphase0_we <= 1'd0;
    if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin
        csrbank2_wrphase0_we <= interface2_bank_bus_re;
    end
end
assign csrbank2_rst0_w = k7ddrphy_rst_storage;
assign csrbank2_dly_sel0_w = k7ddrphy_dly_sel_storage;
assign csrbank2_half_sys8x_taps0_w = k7ddrphy_half_sys8x_taps_storage;
assign csrbank2_wlevel_en0_w = k7ddrphy_wlevel_en_storage;
assign csrbank2_rdphase0_w = k7ddrphy_rdphase_storage;
assign csrbank2_wrphase0_w = k7ddrphy_wrphase_storage;
assign csrbank3_sel = (interface3_bank_bus_adr[13:9] == 2'd3);
assign csrbank3_dfii_control0_r = interface3_bank_bus_dat_w[3:0];
always @(*) begin
    csrbank3_dfii_control0_re <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 1'd0))) begin
        csrbank3_dfii_control0_re <= interface3_bank_bus_we;
    end
end
always @(*) begin
    csrbank3_dfii_control0_we <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 1'd0))) begin
        csrbank3_dfii_control0_we <= interface3_bank_bus_re;
    end
end
assign csrbank3_dfii_pi0_command0_r = interface3_bank_bus_dat_w[7:0];
always @(*) begin
    csrbank3_dfii_pi0_command0_we <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 1'd1))) begin
        csrbank3_dfii_pi0_command0_we <= interface3_bank_bus_re;
    end
end
always @(*) begin
    csrbank3_dfii_pi0_command0_re <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 1'd1))) begin
        csrbank3_dfii_pi0_command0_re <= interface3_bank_bus_we;
    end
end
assign litedramcore_sdram_phaseinjector0_command_issue_r = interface3_bank_bus_dat_w[0];
always @(*) begin
    litedramcore_sdram_phaseinjector0_command_issue_we <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 2'd2))) begin
        litedramcore_sdram_phaseinjector0_command_issue_we <= interface3_bank_bus_re;
    end
end
always @(*) begin
    litedramcore_sdram_phaseinjector0_command_issue_re <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 2'd2))) begin
        litedramcore_sdram_phaseinjector0_command_issue_re <= interface3_bank_bus_we;
    end
end
assign csrbank3_dfii_pi0_address0_r = interface3_bank_bus_dat_w[14:0];
always @(*) begin
    csrbank3_dfii_pi0_address0_we <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 2'd3))) begin
        csrbank3_dfii_pi0_address0_we <= interface3_bank_bus_re;
    end
end
always @(*) begin
    csrbank3_dfii_pi0_address0_re <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 2'd3))) begin
        csrbank3_dfii_pi0_address0_re <= interface3_bank_bus_we;
    end
end
assign csrbank3_dfii_pi0_baddress0_r = interface3_bank_bus_dat_w[2:0];
always @(*) begin
    csrbank3_dfii_pi0_baddress0_re <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 3'd4))) begin
        csrbank3_dfii_pi0_baddress0_re <= interface3_bank_bus_we;
    end
end
always @(*) begin
    csrbank3_dfii_pi0_baddress0_we <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 3'd4))) begin
        csrbank3_dfii_pi0_baddress0_we <= interface3_bank_bus_re;
    end
end
assign csrbank3_dfii_pi0_wrdata1_r = interface3_bank_bus_dat_w;
always @(*) begin
    csrbank3_dfii_pi0_wrdata1_we <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 3'd5))) begin
        csrbank3_dfii_pi0_wrdata1_we <= interface3_bank_bus_re;
    end
end
always @(*) begin
    csrbank3_dfii_pi0_wrdata1_re <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 3'd5))) begin
        csrbank3_dfii_pi0_wrdata1_re <= interface3_bank_bus_we;
    end
end
assign csrbank3_dfii_pi0_wrdata0_r = interface3_bank_bus_dat_w;
always @(*) begin
    csrbank3_dfii_pi0_wrdata0_re <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 3'd6))) begin
        csrbank3_dfii_pi0_wrdata0_re <= interface3_bank_bus_we;
    end
end
always @(*) begin
    csrbank3_dfii_pi0_wrdata0_we <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 3'd6))) begin
        csrbank3_dfii_pi0_wrdata0_we <= interface3_bank_bus_re;
    end
end
assign csrbank3_dfii_pi0_rddata1_r = interface3_bank_bus_dat_w;
always @(*) begin
    csrbank3_dfii_pi0_rddata1_re <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 3'd7))) begin
        csrbank3_dfii_pi0_rddata1_re <= interface3_bank_bus_we;
    end
end
always @(*) begin
    csrbank3_dfii_pi0_rddata1_we <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 3'd7))) begin
        csrbank3_dfii_pi0_rddata1_we <= interface3_bank_bus_re;
    end
end
assign csrbank3_dfii_pi0_rddata0_r = interface3_bank_bus_dat_w;
always @(*) begin
    csrbank3_dfii_pi0_rddata0_we <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 4'd8))) begin
        csrbank3_dfii_pi0_rddata0_we <= interface3_bank_bus_re;
    end
end
always @(*) begin
    csrbank3_dfii_pi0_rddata0_re <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 4'd8))) begin
        csrbank3_dfii_pi0_rddata0_re <= interface3_bank_bus_we;
    end
end
assign csrbank3_dfii_pi1_command0_r = interface3_bank_bus_dat_w[7:0];
always @(*) begin
    csrbank3_dfii_pi1_command0_we <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 4'd9))) begin
        csrbank3_dfii_pi1_command0_we <= interface3_bank_bus_re;
    end
end
always @(*) begin
    csrbank3_dfii_pi1_command0_re <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 4'd9))) begin
        csrbank3_dfii_pi1_command0_re <= interface3_bank_bus_we;
    end
end
assign litedramcore_sdram_phaseinjector1_command_issue_r = interface3_bank_bus_dat_w[0];
always @(*) begin
    litedramcore_sdram_phaseinjector1_command_issue_re <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 4'd10))) begin
        litedramcore_sdram_phaseinjector1_command_issue_re <= interface3_bank_bus_we;
    end
end
always @(*) begin
    litedramcore_sdram_phaseinjector1_command_issue_we <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 4'd10))) begin
        litedramcore_sdram_phaseinjector1_command_issue_we <= interface3_bank_bus_re;
    end
end
assign csrbank3_dfii_pi1_address0_r = interface3_bank_bus_dat_w[14:0];
always @(*) begin
    csrbank3_dfii_pi1_address0_re <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 4'd11))) begin
        csrbank3_dfii_pi1_address0_re <= interface3_bank_bus_we;
    end
end
always @(*) begin
    csrbank3_dfii_pi1_address0_we <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 4'd11))) begin
        csrbank3_dfii_pi1_address0_we <= interface3_bank_bus_re;
    end
end
assign csrbank3_dfii_pi1_baddress0_r = interface3_bank_bus_dat_w[2:0];
always @(*) begin
    csrbank3_dfii_pi1_baddress0_we <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 4'd12))) begin
        csrbank3_dfii_pi1_baddress0_we <= interface3_bank_bus_re;
    end
end
always @(*) begin
    csrbank3_dfii_pi1_baddress0_re <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 4'd12))) begin
        csrbank3_dfii_pi1_baddress0_re <= interface3_bank_bus_we;
    end
end
assign csrbank3_dfii_pi1_wrdata1_r = interface3_bank_bus_dat_w;
always @(*) begin
    csrbank3_dfii_pi1_wrdata1_re <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 4'd13))) begin
        csrbank3_dfii_pi1_wrdata1_re <= interface3_bank_bus_we;
    end
end
always @(*) begin
    csrbank3_dfii_pi1_wrdata1_we <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 4'd13))) begin
        csrbank3_dfii_pi1_wrdata1_we <= interface3_bank_bus_re;
    end
end
assign csrbank3_dfii_pi1_wrdata0_r = interface3_bank_bus_dat_w;
always @(*) begin
    csrbank3_dfii_pi1_wrdata0_re <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 4'd14))) begin
        csrbank3_dfii_pi1_wrdata0_re <= interface3_bank_bus_we;
    end
end
always @(*) begin
    csrbank3_dfii_pi1_wrdata0_we <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 4'd14))) begin
        csrbank3_dfii_pi1_wrdata0_we <= interface3_bank_bus_re;
    end
end
assign csrbank3_dfii_pi1_rddata1_r = interface3_bank_bus_dat_w;
always @(*) begin
    csrbank3_dfii_pi1_rddata1_we <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 4'd15))) begin
        csrbank3_dfii_pi1_rddata1_we <= interface3_bank_bus_re;
    end
end
always @(*) begin
    csrbank3_dfii_pi1_rddata1_re <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 4'd15))) begin
        csrbank3_dfii_pi1_rddata1_re <= interface3_bank_bus_we;
    end
end
assign csrbank3_dfii_pi1_rddata0_r = interface3_bank_bus_dat_w;
always @(*) begin
    csrbank3_dfii_pi1_rddata0_re <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 5'd16))) begin
        csrbank3_dfii_pi1_rddata0_re <= interface3_bank_bus_we;
    end
end
always @(*) begin
    csrbank3_dfii_pi1_rddata0_we <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 5'd16))) begin
        csrbank3_dfii_pi1_rddata0_we <= interface3_bank_bus_re;
    end
end
assign csrbank3_dfii_pi2_command0_r = interface3_bank_bus_dat_w[7:0];
always @(*) begin
    csrbank3_dfii_pi2_command0_re <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 5'd17))) begin
        csrbank3_dfii_pi2_command0_re <= interface3_bank_bus_we;
    end
end
always @(*) begin
    csrbank3_dfii_pi2_command0_we <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 5'd17))) begin
        csrbank3_dfii_pi2_command0_we <= interface3_bank_bus_re;
    end
end
assign litedramcore_sdram_phaseinjector2_command_issue_r = interface3_bank_bus_dat_w[0];
always @(*) begin
    litedramcore_sdram_phaseinjector2_command_issue_we <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 5'd18))) begin
        litedramcore_sdram_phaseinjector2_command_issue_we <= interface3_bank_bus_re;
    end
end
always @(*) begin
    litedramcore_sdram_phaseinjector2_command_issue_re <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 5'd18))) begin
        litedramcore_sdram_phaseinjector2_command_issue_re <= interface3_bank_bus_we;
    end
end
assign csrbank3_dfii_pi2_address0_r = interface3_bank_bus_dat_w[14:0];
always @(*) begin
    csrbank3_dfii_pi2_address0_we <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 5'd19))) begin
        csrbank3_dfii_pi2_address0_we <= interface3_bank_bus_re;
    end
end
always @(*) begin
    csrbank3_dfii_pi2_address0_re <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 5'd19))) begin
        csrbank3_dfii_pi2_address0_re <= interface3_bank_bus_we;
    end
end
assign csrbank3_dfii_pi2_baddress0_r = interface3_bank_bus_dat_w[2:0];
always @(*) begin
    csrbank3_dfii_pi2_baddress0_re <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 5'd20))) begin
        csrbank3_dfii_pi2_baddress0_re <= interface3_bank_bus_we;
    end
end
always @(*) begin
    csrbank3_dfii_pi2_baddress0_we <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 5'd20))) begin
        csrbank3_dfii_pi2_baddress0_we <= interface3_bank_bus_re;
    end
end
assign csrbank3_dfii_pi2_wrdata1_r = interface3_bank_bus_dat_w;
always @(*) begin
    csrbank3_dfii_pi2_wrdata1_re <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 5'd21))) begin
        csrbank3_dfii_pi2_wrdata1_re <= interface3_bank_bus_we;
    end
end
always @(*) begin
    csrbank3_dfii_pi2_wrdata1_we <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 5'd21))) begin
        csrbank3_dfii_pi2_wrdata1_we <= interface3_bank_bus_re;
    end
end
assign csrbank3_dfii_pi2_wrdata0_r = interface3_bank_bus_dat_w;
always @(*) begin
    csrbank3_dfii_pi2_wrdata0_we <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 5'd22))) begin
        csrbank3_dfii_pi2_wrdata0_we <= interface3_bank_bus_re;
    end
end
always @(*) begin
    csrbank3_dfii_pi2_wrdata0_re <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 5'd22))) begin
        csrbank3_dfii_pi2_wrdata0_re <= interface3_bank_bus_we;
    end
end
assign csrbank3_dfii_pi2_rddata1_r = interface3_bank_bus_dat_w;
always @(*) begin
    csrbank3_dfii_pi2_rddata1_re <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 5'd23))) begin
        csrbank3_dfii_pi2_rddata1_re <= interface3_bank_bus_we;
    end
end
always @(*) begin
    csrbank3_dfii_pi2_rddata1_we <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 5'd23))) begin
        csrbank3_dfii_pi2_rddata1_we <= interface3_bank_bus_re;
    end
end
assign csrbank3_dfii_pi2_rddata0_r = interface3_bank_bus_dat_w;
always @(*) begin
    csrbank3_dfii_pi2_rddata0_re <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 5'd24))) begin
        csrbank3_dfii_pi2_rddata0_re <= interface3_bank_bus_we;
    end
end
always @(*) begin
    csrbank3_dfii_pi2_rddata0_we <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 5'd24))) begin
        csrbank3_dfii_pi2_rddata0_we <= interface3_bank_bus_re;
    end
end
assign csrbank3_dfii_pi3_command0_r = interface3_bank_bus_dat_w[7:0];
always @(*) begin
    csrbank3_dfii_pi3_command0_we <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 5'd25))) begin
        csrbank3_dfii_pi3_command0_we <= interface3_bank_bus_re;
    end
end
always @(*) begin
    csrbank3_dfii_pi3_command0_re <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 5'd25))) begin
        csrbank3_dfii_pi3_command0_re <= interface3_bank_bus_we;
    end
end
assign litedramcore_sdram_phaseinjector3_command_issue_r = interface3_bank_bus_dat_w[0];
always @(*) begin
    litedramcore_sdram_phaseinjector3_command_issue_we <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 5'd26))) begin
        litedramcore_sdram_phaseinjector3_command_issue_we <= interface3_bank_bus_re;
    end
end
always @(*) begin
    litedramcore_sdram_phaseinjector3_command_issue_re <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 5'd26))) begin
        litedramcore_sdram_phaseinjector3_command_issue_re <= interface3_bank_bus_we;
    end
end
assign csrbank3_dfii_pi3_address0_r = interface3_bank_bus_dat_w[14:0];
always @(*) begin
    csrbank3_dfii_pi3_address0_re <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 5'd27))) begin
        csrbank3_dfii_pi3_address0_re <= interface3_bank_bus_we;
    end
end
always @(*) begin
    csrbank3_dfii_pi3_address0_we <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 5'd27))) begin
        csrbank3_dfii_pi3_address0_we <= interface3_bank_bus_re;
    end
end
assign csrbank3_dfii_pi3_baddress0_r = interface3_bank_bus_dat_w[2:0];
always @(*) begin
    csrbank3_dfii_pi3_baddress0_re <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 5'd28))) begin
        csrbank3_dfii_pi3_baddress0_re <= interface3_bank_bus_we;
    end
end
always @(*) begin
    csrbank3_dfii_pi3_baddress0_we <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 5'd28))) begin
        csrbank3_dfii_pi3_baddress0_we <= interface3_bank_bus_re;
    end
end
assign csrbank3_dfii_pi3_wrdata1_r = interface3_bank_bus_dat_w;
always @(*) begin
    csrbank3_dfii_pi3_wrdata1_we <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 5'd29))) begin
        csrbank3_dfii_pi3_wrdata1_we <= interface3_bank_bus_re;
    end
end
always @(*) begin
    csrbank3_dfii_pi3_wrdata1_re <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 5'd29))) begin
        csrbank3_dfii_pi3_wrdata1_re <= interface3_bank_bus_we;
    end
end
assign csrbank3_dfii_pi3_wrdata0_r = interface3_bank_bus_dat_w;
always @(*) begin
    csrbank3_dfii_pi3_wrdata0_re <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 5'd30))) begin
        csrbank3_dfii_pi3_wrdata0_re <= interface3_bank_bus_we;
    end
end
always @(*) begin
    csrbank3_dfii_pi3_wrdata0_we <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 5'd30))) begin
        csrbank3_dfii_pi3_wrdata0_we <= interface3_bank_bus_re;
    end
end
assign csrbank3_dfii_pi3_rddata1_r = interface3_bank_bus_dat_w;
always @(*) begin
    csrbank3_dfii_pi3_rddata1_we <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 5'd31))) begin
        csrbank3_dfii_pi3_rddata1_we <= interface3_bank_bus_re;
    end
end
always @(*) begin
    csrbank3_dfii_pi3_rddata1_re <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 5'd31))) begin
        csrbank3_dfii_pi3_rddata1_re <= interface3_bank_bus_we;
    end
end
assign csrbank3_dfii_pi3_rddata0_r = interface3_bank_bus_dat_w;
always @(*) begin
    csrbank3_dfii_pi3_rddata0_we <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 6'd32))) begin
        csrbank3_dfii_pi3_rddata0_we <= interface3_bank_bus_re;
    end
end
always @(*) begin
    csrbank3_dfii_pi3_rddata0_re <= 1'd0;
    if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 6'd32))) begin
        csrbank3_dfii_pi3_rddata0_re <= interface3_bank_bus_we;
    end
end
assign litedramcore_sdram_sel = litedramcore_sdram_storage[0];
assign litedramcore_sdram_cke = litedramcore_sdram_storage[1];
assign litedramcore_sdram_odt = litedramcore_sdram_storage[2];
assign litedramcore_sdram_reset_n = litedramcore_sdram_storage[3];
assign csrbank3_dfii_control0_w = litedramcore_sdram_storage;
assign litedramcore_sdram_phaseinjector0_csrfield_cs = litedramcore_sdram_phaseinjector0_command_storage[0];
assign litedramcore_sdram_phaseinjector0_csrfield_we = litedramcore_sdram_phaseinjector0_command_storage[1];
assign litedramcore_sdram_phaseinjector0_csrfield_cas = litedramcore_sdram_phaseinjector0_command_storage[2];
assign litedramcore_sdram_phaseinjector0_csrfield_ras = litedramcore_sdram_phaseinjector0_command_storage[3];
assign litedramcore_sdram_phaseinjector0_csrfield_wren = litedramcore_sdram_phaseinjector0_command_storage[4];
assign litedramcore_sdram_phaseinjector0_csrfield_rden = litedramcore_sdram_phaseinjector0_command_storage[5];
assign litedramcore_sdram_phaseinjector0_csrfield_cs_top = litedramcore_sdram_phaseinjector0_command_storage[6];
assign litedramcore_sdram_phaseinjector0_csrfield_cs_bottom = litedramcore_sdram_phaseinjector0_command_storage[7];
assign csrbank3_dfii_pi0_command0_w = litedramcore_sdram_phaseinjector0_command_storage;
assign csrbank3_dfii_pi0_address0_w = litedramcore_sdram_phaseinjector0_address_storage;
assign csrbank3_dfii_pi0_baddress0_w = litedramcore_sdram_phaseinjector0_baddress_storage;
assign csrbank3_dfii_pi0_wrdata1_w = litedramcore_sdram_phaseinjector0_wrdata_storage[63:32];
assign csrbank3_dfii_pi0_wrdata0_w = litedramcore_sdram_phaseinjector0_wrdata_storage[31:0];
assign csrbank3_dfii_pi0_rddata1_w = litedramcore_sdram_phaseinjector0_rddata_status[63:32];
assign csrbank3_dfii_pi0_rddata0_w = litedramcore_sdram_phaseinjector0_rddata_status[31:0];
assign litedramcore_sdram_phaseinjector0_rddata_we = csrbank3_dfii_pi0_rddata0_we;
assign litedramcore_sdram_phaseinjector1_csrfield_cs = litedramcore_sdram_phaseinjector1_command_storage[0];
assign litedramcore_sdram_phaseinjector1_csrfield_we = litedramcore_sdram_phaseinjector1_command_storage[1];
assign litedramcore_sdram_phaseinjector1_csrfield_cas = litedramcore_sdram_phaseinjector1_command_storage[2];
assign litedramcore_sdram_phaseinjector1_csrfield_ras = litedramcore_sdram_phaseinjector1_command_storage[3];
assign litedramcore_sdram_phaseinjector1_csrfield_wren = litedramcore_sdram_phaseinjector1_command_storage[4];
assign litedramcore_sdram_phaseinjector1_csrfield_rden = litedramcore_sdram_phaseinjector1_command_storage[5];
assign litedramcore_sdram_phaseinjector1_csrfield_cs_top = litedramcore_sdram_phaseinjector1_command_storage[6];
assign litedramcore_sdram_phaseinjector1_csrfield_cs_bottom = litedramcore_sdram_phaseinjector1_command_storage[7];
assign csrbank3_dfii_pi1_command0_w = litedramcore_sdram_phaseinjector1_command_storage;
assign csrbank3_dfii_pi1_address0_w = litedramcore_sdram_phaseinjector1_address_storage;
assign csrbank3_dfii_pi1_baddress0_w = litedramcore_sdram_phaseinjector1_baddress_storage;
assign csrbank3_dfii_pi1_wrdata1_w = litedramcore_sdram_phaseinjector1_wrdata_storage[63:32];
assign csrbank3_dfii_pi1_wrdata0_w = litedramcore_sdram_phaseinjector1_wrdata_storage[31:0];
assign csrbank3_dfii_pi1_rddata1_w = litedramcore_sdram_phaseinjector1_rddata_status[63:32];
assign csrbank3_dfii_pi1_rddata0_w = litedramcore_sdram_phaseinjector1_rddata_status[31:0];
assign litedramcore_sdram_phaseinjector1_rddata_we = csrbank3_dfii_pi1_rddata0_we;
assign litedramcore_sdram_phaseinjector2_csrfield_cs = litedramcore_sdram_phaseinjector2_command_storage[0];
assign litedramcore_sdram_phaseinjector2_csrfield_we = litedramcore_sdram_phaseinjector2_command_storage[1];
assign litedramcore_sdram_phaseinjector2_csrfield_cas = litedramcore_sdram_phaseinjector2_command_storage[2];
assign litedramcore_sdram_phaseinjector2_csrfield_ras = litedramcore_sdram_phaseinjector2_command_storage[3];
assign litedramcore_sdram_phaseinjector2_csrfield_wren = litedramcore_sdram_phaseinjector2_command_storage[4];
assign litedramcore_sdram_phaseinjector2_csrfield_rden = litedramcore_sdram_phaseinjector2_command_storage[5];
assign litedramcore_sdram_phaseinjector2_csrfield_cs_top = litedramcore_sdram_phaseinjector2_command_storage[6];
assign litedramcore_sdram_phaseinjector2_csrfield_cs_bottom = litedramcore_sdram_phaseinjector2_command_storage[7];
assign csrbank3_dfii_pi2_command0_w = litedramcore_sdram_phaseinjector2_command_storage;
assign csrbank3_dfii_pi2_address0_w = litedramcore_sdram_phaseinjector2_address_storage;
assign csrbank3_dfii_pi2_baddress0_w = litedramcore_sdram_phaseinjector2_baddress_storage;
assign csrbank3_dfii_pi2_wrdata1_w = litedramcore_sdram_phaseinjector2_wrdata_storage[63:32];
assign csrbank3_dfii_pi2_wrdata0_w = litedramcore_sdram_phaseinjector2_wrdata_storage[31:0];
assign csrbank3_dfii_pi2_rddata1_w = litedramcore_sdram_phaseinjector2_rddata_status[63:32];
assign csrbank3_dfii_pi2_rddata0_w = litedramcore_sdram_phaseinjector2_rddata_status[31:0];
assign litedramcore_sdram_phaseinjector2_rddata_we = csrbank3_dfii_pi2_rddata0_we;
assign litedramcore_sdram_phaseinjector3_csrfield_cs = litedramcore_sdram_phaseinjector3_command_storage[0];
assign litedramcore_sdram_phaseinjector3_csrfield_we = litedramcore_sdram_phaseinjector3_command_storage[1];
assign litedramcore_sdram_phaseinjector3_csrfield_cas = litedramcore_sdram_phaseinjector3_command_storage[2];
assign litedramcore_sdram_phaseinjector3_csrfield_ras = litedramcore_sdram_phaseinjector3_command_storage[3];
assign litedramcore_sdram_phaseinjector3_csrfield_wren = litedramcore_sdram_phaseinjector3_command_storage[4];
assign litedramcore_sdram_phaseinjector3_csrfield_rden = litedramcore_sdram_phaseinjector3_command_storage[5];
assign litedramcore_sdram_phaseinjector3_csrfield_cs_top = litedramcore_sdram_phaseinjector3_command_storage[6];
assign litedramcore_sdram_phaseinjector3_csrfield_cs_bottom = litedramcore_sdram_phaseinjector3_command_storage[7];
assign csrbank3_dfii_pi3_command0_w = litedramcore_sdram_phaseinjector3_command_storage;
assign csrbank3_dfii_pi3_address0_w = litedramcore_sdram_phaseinjector3_address_storage;
assign csrbank3_dfii_pi3_baddress0_w = litedramcore_sdram_phaseinjector3_baddress_storage;
assign csrbank3_dfii_pi3_wrdata1_w = litedramcore_sdram_phaseinjector3_wrdata_storage[63:32];
assign csrbank3_dfii_pi3_wrdata0_w = litedramcore_sdram_phaseinjector3_wrdata_storage[31:0];
assign csrbank3_dfii_pi3_rddata1_w = litedramcore_sdram_phaseinjector3_rddata_status[63:32];
assign csrbank3_dfii_pi3_rddata0_w = litedramcore_sdram_phaseinjector3_rddata_status[31:0];
assign litedramcore_sdram_phaseinjector3_rddata_we = csrbank3_dfii_pi3_rddata0_we;
assign csrbank4_sel = (interface4_bank_bus_adr[13:9] == 3'd4);
assign csrbank4_load0_r = interface4_bank_bus_dat_w;
always @(*) begin
    csrbank4_load0_we <= 1'd0;
    if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 1'd0))) begin
        csrbank4_load0_we <= interface4_bank_bus_re;
    end
end
always @(*) begin
    csrbank4_load0_re <= 1'd0;
    if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 1'd0))) begin
        csrbank4_load0_re <= interface4_bank_bus_we;
    end
end
assign csrbank4_reload0_r = interface4_bank_bus_dat_w;
always @(*) begin
    csrbank4_reload0_re <= 1'd0;
    if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 1'd1))) begin
        csrbank4_reload0_re <= interface4_bank_bus_we;
    end
end
always @(*) begin
    csrbank4_reload0_we <= 1'd0;
    if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 1'd1))) begin
        csrbank4_reload0_we <= interface4_bank_bus_re;
    end
end
assign csrbank4_en0_r = interface4_bank_bus_dat_w[0];
always @(*) begin
    csrbank4_en0_we <= 1'd0;
    if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 2'd2))) begin
        csrbank4_en0_we <= interface4_bank_bus_re;
    end
end
always @(*) begin
    csrbank4_en0_re <= 1'd0;
    if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 2'd2))) begin
        csrbank4_en0_re <= interface4_bank_bus_we;
    end
end
assign csrbank4_update_value0_r = interface4_bank_bus_dat_w[0];
always @(*) begin
    csrbank4_update_value0_re <= 1'd0;
    if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 2'd3))) begin
        csrbank4_update_value0_re <= interface4_bank_bus_we;
    end
end
always @(*) begin
    csrbank4_update_value0_we <= 1'd0;
    if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 2'd3))) begin
        csrbank4_update_value0_we <= interface4_bank_bus_re;
    end
end
assign csrbank4_value_r = interface4_bank_bus_dat_w;
always @(*) begin
    csrbank4_value_re <= 1'd0;
    if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 3'd4))) begin
        csrbank4_value_re <= interface4_bank_bus_we;
    end
end
always @(*) begin
    csrbank4_value_we <= 1'd0;
    if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 3'd4))) begin
        csrbank4_value_we <= interface4_bank_bus_re;
    end
end
assign csrbank4_ev_status_r = interface4_bank_bus_dat_w[0];
always @(*) begin
    csrbank4_ev_status_we <= 1'd0;
    if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 3'd5))) begin
        csrbank4_ev_status_we <= interface4_bank_bus_re;
    end
end
always @(*) begin
    csrbank4_ev_status_re <= 1'd0;
    if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 3'd5))) begin
        csrbank4_ev_status_re <= interface4_bank_bus_we;
    end
end
assign csrbank4_ev_pending_r = interface4_bank_bus_dat_w[0];
always @(*) begin
    csrbank4_ev_pending_we <= 1'd0;
    if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 3'd6))) begin
        csrbank4_ev_pending_we <= interface4_bank_bus_re;
    end
end
always @(*) begin
    csrbank4_ev_pending_re <= 1'd0;
    if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 3'd6))) begin
        csrbank4_ev_pending_re <= interface4_bank_bus_we;
    end
end
assign csrbank4_ev_enable0_r = interface4_bank_bus_dat_w[0];
always @(*) begin
    csrbank4_ev_enable0_re <= 1'd0;
    if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 3'd7))) begin
        csrbank4_ev_enable0_re <= interface4_bank_bus_we;
    end
end
always @(*) begin
    csrbank4_ev_enable0_we <= 1'd0;
    if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 3'd7))) begin
        csrbank4_ev_enable0_we <= interface4_bank_bus_re;
    end
end
assign csrbank4_load0_w = litedramcore_load_storage;
assign csrbank4_reload0_w = litedramcore_reload_storage;
assign csrbank4_en0_w = litedramcore_en_storage;
assign csrbank4_update_value0_w = litedramcore_update_value_storage;
assign csrbank4_value_w = litedramcore_value_status;
assign litedramcore_value_we = csrbank4_value_we;
assign litedramcore_status_status = litedramcore_zero0;
assign csrbank4_ev_status_w = litedramcore_status_status;
assign litedramcore_status_we = csrbank4_ev_status_we;
assign litedramcore_pending_status = litedramcore_zero1;
assign csrbank4_ev_pending_w = litedramcore_pending_status;
assign litedramcore_pending_we = csrbank4_ev_pending_we;
assign litedramcore_zero2 = litedramcore_enable_storage;
assign csrbank4_ev_enable0_w = litedramcore_enable_storage;
assign csrbank5_sel = (interface5_bank_bus_adr[13:9] == 3'd5);
assign uart_rxtx_r = interface5_bank_bus_dat_w[7:0];
always @(*) begin
    uart_rxtx_re <= 1'd0;
    if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 1'd0))) begin
        uart_rxtx_re <= interface5_bank_bus_we;
    end
end
always @(*) begin
    uart_rxtx_we <= 1'd0;
    if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 1'd0))) begin
        uart_rxtx_we <= interface5_bank_bus_re;
    end
end
assign csrbank5_txfull_r = interface5_bank_bus_dat_w[0];
always @(*) begin
    csrbank5_txfull_we <= 1'd0;
    if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 1'd1))) begin
        csrbank5_txfull_we <= interface5_bank_bus_re;
    end
end
always @(*) begin
    csrbank5_txfull_re <= 1'd0;
    if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 1'd1))) begin
        csrbank5_txfull_re <= interface5_bank_bus_we;
    end
end
assign csrbank5_rxempty_r = interface5_bank_bus_dat_w[0];
always @(*) begin
    csrbank5_rxempty_re <= 1'd0;
    if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 2'd2))) begin
        csrbank5_rxempty_re <= interface5_bank_bus_we;
    end
end
always @(*) begin
    csrbank5_rxempty_we <= 1'd0;
    if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 2'd2))) begin
        csrbank5_rxempty_we <= interface5_bank_bus_re;
    end
end
assign csrbank5_ev_status_r = interface5_bank_bus_dat_w[1:0];
always @(*) begin
    csrbank5_ev_status_re <= 1'd0;
    if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 2'd3))) begin
        csrbank5_ev_status_re <= interface5_bank_bus_we;
    end
end
always @(*) begin
    csrbank5_ev_status_we <= 1'd0;
    if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 2'd3))) begin
        csrbank5_ev_status_we <= interface5_bank_bus_re;
    end
end
assign csrbank5_ev_pending_r = interface5_bank_bus_dat_w[1:0];
always @(*) begin
    csrbank5_ev_pending_we <= 1'd0;
    if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 3'd4))) begin
        csrbank5_ev_pending_we <= interface5_bank_bus_re;
    end
end
always @(*) begin
    csrbank5_ev_pending_re <= 1'd0;
    if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 3'd4))) begin
        csrbank5_ev_pending_re <= interface5_bank_bus_we;
    end
end
assign csrbank5_ev_enable0_r = interface5_bank_bus_dat_w[1:0];
always @(*) begin
    csrbank5_ev_enable0_we <= 1'd0;
    if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 3'd5))) begin
        csrbank5_ev_enable0_we <= interface5_bank_bus_re;
    end
end
always @(*) begin
    csrbank5_ev_enable0_re <= 1'd0;
    if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 3'd5))) begin
        csrbank5_ev_enable0_re <= interface5_bank_bus_we;
    end
end
assign csrbank5_txempty_r = interface5_bank_bus_dat_w[0];
always @(*) begin
    csrbank5_txempty_re <= 1'd0;
    if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 3'd6))) begin
        csrbank5_txempty_re <= interface5_bank_bus_we;
    end
end
always @(*) begin
    csrbank5_txempty_we <= 1'd0;
    if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 3'd6))) begin
        csrbank5_txempty_we <= interface5_bank_bus_re;
    end
end
assign csrbank5_rxfull_r = interface5_bank_bus_dat_w[0];
always @(*) begin
    csrbank5_rxfull_we <= 1'd0;
    if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 3'd7))) begin
        csrbank5_rxfull_we <= interface5_bank_bus_re;
    end
end
always @(*) begin
    csrbank5_rxfull_re <= 1'd0;
    if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 3'd7))) begin
        csrbank5_rxfull_re <= interface5_bank_bus_we;
    end
end
assign csrbank5_txfull_w = uart_txfull_status;
assign uart_txfull_we = csrbank5_txfull_we;
assign csrbank5_rxempty_w = uart_rxempty_status;
assign uart_rxempty_we = csrbank5_rxempty_we;
always @(*) begin
    uart_status_status <= 2'd0;
    uart_status_status[0] <= uart_tx0;
    uart_status_status[1] <= uart_rx0;
end
assign csrbank5_ev_status_w = uart_status_status;
assign uart_status_we = csrbank5_ev_status_we;
always @(*) begin
    uart_pending_status <= 2'd0;
    uart_pending_status[0] <= uart_tx1;
    uart_pending_status[1] <= uart_rx1;
end
assign csrbank5_ev_pending_w = uart_pending_status;
assign uart_pending_we = csrbank5_ev_pending_we;
assign uart_tx2 = uart_enable_storage[0];
assign uart_rx2 = uart_enable_storage[1];
assign csrbank5_ev_enable0_w = uart_enable_storage;
assign csrbank5_txempty_w = uart_txempty_status;
assign uart_txempty_we = csrbank5_txempty_we;
assign csrbank5_rxfull_w = uart_rxfull_status;
assign uart_rxfull_we = csrbank5_rxfull_we;
assign adr = interface1_adr;
assign re = interface1_re;
assign we = interface1_we;
assign dat_w = interface1_dat_w;
assign interface1_dat_r = dat_r;
assign interface0_bank_bus_adr = adr;
assign interface1_bank_bus_adr = adr;
assign interface2_bank_bus_adr = adr;
assign interface3_bank_bus_adr = adr;
assign interface4_bank_bus_adr = adr;
assign interface5_bank_bus_adr = adr;
assign interface0_bank_bus_re = re;
assign interface1_bank_bus_re = re;
assign interface2_bank_bus_re = re;
assign interface3_bank_bus_re = re;
assign interface4_bank_bus_re = re;
assign interface5_bank_bus_re = re;
assign interface0_bank_bus_we = we;
assign interface1_bank_bus_we = we;
assign interface2_bank_bus_we = we;
assign interface3_bank_bus_we = we;
assign interface4_bank_bus_we = we;
assign interface5_bank_bus_we = we;
assign interface0_bank_bus_dat_w = dat_w;
assign interface1_bank_bus_dat_w = dat_w;
assign interface2_bank_bus_dat_w = dat_w;
assign interface3_bank_bus_dat_w = dat_w;
assign interface4_bank_bus_dat_w = dat_w;
assign interface5_bank_bus_dat_w = dat_w;
assign dat_r = (((((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r) | interface3_bank_bus_dat_r) | interface4_bank_bus_dat_r) | interface5_bank_bus_dat_r);
always @(*) begin
    rhs_self0 <= 30'd0;
    case (grant)
        1'd0: begin
            rhs_self0 <= litedramcore_ibus_adr;
        end
        default: begin
            rhs_self0 <= litedramcore_dbus_adr;
        end
    endcase
end
always @(*) begin
    rhs_self1 <= 32'd0;
    case (grant)
        1'd0: begin
            rhs_self1 <= litedramcore_ibus_dat_w;
        end
        default: begin
            rhs_self1 <= litedramcore_dbus_dat_w;
        end
    endcase
end
always @(*) begin
    rhs_self2 <= 4'd0;
    case (grant)
        1'd0: begin
            rhs_self2 <= litedramcore_ibus_sel;
        end
        default: begin
            rhs_self2 <= litedramcore_dbus_sel;
        end
    endcase
end
always @(*) begin
    rhs_self3 <= 1'd0;
    case (grant)
        1'd0: begin
            rhs_self3 <= litedramcore_ibus_cyc;
        end
        default: begin
            rhs_self3 <= litedramcore_dbus_cyc;
        end
    endcase
end
always @(*) begin
    rhs_self4 <= 1'd0;
    case (grant)
        1'd0: begin
            rhs_self4 <= litedramcore_ibus_stb;
        end
        default: begin
            rhs_self4 <= litedramcore_dbus_stb;
        end
    endcase
end
always @(*) begin
    rhs_self5 <= 1'd0;
    case (grant)
        1'd0: begin
            rhs_self5 <= litedramcore_ibus_we;
        end
        default: begin
            rhs_self5 <= litedramcore_dbus_we;
        end
    endcase
end
always @(*) begin
    rhs_self6 <= 3'd0;
    case (grant)
        1'd0: begin
            rhs_self6 <= litedramcore_ibus_cti;
        end
        default: begin
            rhs_self6 <= litedramcore_dbus_cti;
        end
    endcase
end
always @(*) begin
    rhs_self7 <= 2'd0;
    case (grant)
        1'd0: begin
            rhs_self7 <= litedramcore_ibus_bte;
        end
        default: begin
            rhs_self7 <= litedramcore_dbus_bte;
        end
    endcase
end
always @(*) begin
    rhs_self8 <= 1'd0;
    case (litedramcore_sdram_choose_cmd_grant)
        1'd0: begin
            rhs_self8 <= litedramcore_sdram_choose_cmd_valids[0];
        end
        1'd1: begin
            rhs_self8 <= litedramcore_sdram_choose_cmd_valids[1];
        end
        2'd2: begin
            rhs_self8 <= litedramcore_sdram_choose_cmd_valids[2];
        end
        2'd3: begin
            rhs_self8 <= litedramcore_sdram_choose_cmd_valids[3];
        end
        3'd4: begin
            rhs_self8 <= litedramcore_sdram_choose_cmd_valids[4];
        end
        3'd5: begin
            rhs_self8 <= litedramcore_sdram_choose_cmd_valids[5];
        end
        3'd6: begin
            rhs_self8 <= litedramcore_sdram_choose_cmd_valids[6];
        end
        default: begin
            rhs_self8 <= litedramcore_sdram_choose_cmd_valids[7];
        end
    endcase
end
always @(*) begin
    rhs_self9 <= 15'd0;
    case (litedramcore_sdram_choose_cmd_grant)
        1'd0: begin
            rhs_self9 <= litedramcore_sdram_bankmachine0_cmd_payload_a;
        end
        1'd1: begin
            rhs_self9 <= litedramcore_sdram_bankmachine1_cmd_payload_a;
        end
        2'd2: begin
            rhs_self9 <= litedramcore_sdram_bankmachine2_cmd_payload_a;
        end
        2'd3: begin
            rhs_self9 <= litedramcore_sdram_bankmachine3_cmd_payload_a;
        end
        3'd4: begin
            rhs_self9 <= litedramcore_sdram_bankmachine4_cmd_payload_a;
        end
        3'd5: begin
            rhs_self9 <= litedramcore_sdram_bankmachine5_cmd_payload_a;
        end
        3'd6: begin
            rhs_self9 <= litedramcore_sdram_bankmachine6_cmd_payload_a;
        end
        default: begin
            rhs_self9 <= litedramcore_sdram_bankmachine7_cmd_payload_a;
        end
    endcase
end
always @(*) begin
    rhs_self10 <= 3'd0;
    case (litedramcore_sdram_choose_cmd_grant)
        1'd0: begin
            rhs_self10 <= litedramcore_sdram_bankmachine0_cmd_payload_ba;
        end
        1'd1: begin
            rhs_self10 <= litedramcore_sdram_bankmachine1_cmd_payload_ba;
        end
        2'd2: begin
            rhs_self10 <= litedramcore_sdram_bankmachine2_cmd_payload_ba;
        end
        2'd3: begin
            rhs_self10 <= litedramcore_sdram_bankmachine3_cmd_payload_ba;
        end
        3'd4: begin
            rhs_self10 <= litedramcore_sdram_bankmachine4_cmd_payload_ba;
        end
        3'd5: begin
            rhs_self10 <= litedramcore_sdram_bankmachine5_cmd_payload_ba;
        end
        3'd6: begin
            rhs_self10 <= litedramcore_sdram_bankmachine6_cmd_payload_ba;
        end
        default: begin
            rhs_self10 <= litedramcore_sdram_bankmachine7_cmd_payload_ba;
        end
    endcase
end
always @(*) begin
    rhs_self11 <= 1'd0;
    case (litedramcore_sdram_choose_cmd_grant)
        1'd0: begin
            rhs_self11 <= litedramcore_sdram_bankmachine0_cmd_payload_is_read;
        end
        1'd1: begin
            rhs_self11 <= litedramcore_sdram_bankmachine1_cmd_payload_is_read;
        end
        2'd2: begin
            rhs_self11 <= litedramcore_sdram_bankmachine2_cmd_payload_is_read;
        end
        2'd3: begin
            rhs_self11 <= litedramcore_sdram_bankmachine3_cmd_payload_is_read;
        end
        3'd4: begin
            rhs_self11 <= litedramcore_sdram_bankmachine4_cmd_payload_is_read;
        end
        3'd5: begin
            rhs_self11 <= litedramcore_sdram_bankmachine5_cmd_payload_is_read;
        end
        3'd6: begin
            rhs_self11 <= litedramcore_sdram_bankmachine6_cmd_payload_is_read;
        end
        default: begin
            rhs_self11 <= litedramcore_sdram_bankmachine7_cmd_payload_is_read;
        end
    endcase
end
always @(*) begin
    rhs_self12 <= 1'd0;
    case (litedramcore_sdram_choose_cmd_grant)
        1'd0: begin
            rhs_self12 <= litedramcore_sdram_bankmachine0_cmd_payload_is_write;
        end
        1'd1: begin
            rhs_self12 <= litedramcore_sdram_bankmachine1_cmd_payload_is_write;
        end
        2'd2: begin
            rhs_self12 <= litedramcore_sdram_bankmachine2_cmd_payload_is_write;
        end
        2'd3: begin
            rhs_self12 <= litedramcore_sdram_bankmachine3_cmd_payload_is_write;
        end
        3'd4: begin
            rhs_self12 <= litedramcore_sdram_bankmachine4_cmd_payload_is_write;
        end
        3'd5: begin
            rhs_self12 <= litedramcore_sdram_bankmachine5_cmd_payload_is_write;
        end
        3'd6: begin
            rhs_self12 <= litedramcore_sdram_bankmachine6_cmd_payload_is_write;
        end
        default: begin
            rhs_self12 <= litedramcore_sdram_bankmachine7_cmd_payload_is_write;
        end
    endcase
end
always @(*) begin
    rhs_self13 <= 1'd0;
    case (litedramcore_sdram_choose_cmd_grant)
        1'd0: begin
            rhs_self13 <= litedramcore_sdram_bankmachine0_cmd_payload_is_cmd;
        end
        1'd1: begin
            rhs_self13 <= litedramcore_sdram_bankmachine1_cmd_payload_is_cmd;
        end
        2'd2: begin
            rhs_self13 <= litedramcore_sdram_bankmachine2_cmd_payload_is_cmd;
        end
        2'd3: begin
            rhs_self13 <= litedramcore_sdram_bankmachine3_cmd_payload_is_cmd;
        end
        3'd4: begin
            rhs_self13 <= litedramcore_sdram_bankmachine4_cmd_payload_is_cmd;
        end
        3'd5: begin
            rhs_self13 <= litedramcore_sdram_bankmachine5_cmd_payload_is_cmd;
        end
        3'd6: begin
            rhs_self13 <= litedramcore_sdram_bankmachine6_cmd_payload_is_cmd;
        end
        default: begin
            rhs_self13 <= litedramcore_sdram_bankmachine7_cmd_payload_is_cmd;
        end
    endcase
end
always @(*) begin
    t_self0 <= 1'd0;
    case (litedramcore_sdram_choose_cmd_grant)
        1'd0: begin
            t_self0 <= litedramcore_sdram_bankmachine0_cmd_payload_cas;
        end
        1'd1: begin
            t_self0 <= litedramcore_sdram_bankmachine1_cmd_payload_cas;
        end
        2'd2: begin
            t_self0 <= litedramcore_sdram_bankmachine2_cmd_payload_cas;
        end
        2'd3: begin
            t_self0 <= litedramcore_sdram_bankmachine3_cmd_payload_cas;
        end
        3'd4: begin
            t_self0 <= litedramcore_sdram_bankmachine4_cmd_payload_cas;
        end
        3'd5: begin
            t_self0 <= litedramcore_sdram_bankmachine5_cmd_payload_cas;
        end
        3'd6: begin
            t_self0 <= litedramcore_sdram_bankmachine6_cmd_payload_cas;
        end
        default: begin
            t_self0 <= litedramcore_sdram_bankmachine7_cmd_payload_cas;
        end
    endcase
end
always @(*) begin
    t_self1 <= 1'd0;
    case (litedramcore_sdram_choose_cmd_grant)
        1'd0: begin
            t_self1 <= litedramcore_sdram_bankmachine0_cmd_payload_ras;
        end
        1'd1: begin
            t_self1 <= litedramcore_sdram_bankmachine1_cmd_payload_ras;
        end
        2'd2: begin
            t_self1 <= litedramcore_sdram_bankmachine2_cmd_payload_ras;
        end
        2'd3: begin
            t_self1 <= litedramcore_sdram_bankmachine3_cmd_payload_ras;
        end
        3'd4: begin
            t_self1 <= litedramcore_sdram_bankmachine4_cmd_payload_ras;
        end
        3'd5: begin
            t_self1 <= litedramcore_sdram_bankmachine5_cmd_payload_ras;
        end
        3'd6: begin
            t_self1 <= litedramcore_sdram_bankmachine6_cmd_payload_ras;
        end
        default: begin
            t_self1 <= litedramcore_sdram_bankmachine7_cmd_payload_ras;
        end
    endcase
end
always @(*) begin
    t_self2 <= 1'd0;
    case (litedramcore_sdram_choose_cmd_grant)
        1'd0: begin
            t_self2 <= litedramcore_sdram_bankmachine0_cmd_payload_we;
        end
        1'd1: begin
            t_self2 <= litedramcore_sdram_bankmachine1_cmd_payload_we;
        end
        2'd2: begin
            t_self2 <= litedramcore_sdram_bankmachine2_cmd_payload_we;
        end
        2'd3: begin
            t_self2 <= litedramcore_sdram_bankmachine3_cmd_payload_we;
        end
        3'd4: begin
            t_self2 <= litedramcore_sdram_bankmachine4_cmd_payload_we;
        end
        3'd5: begin
            t_self2 <= litedramcore_sdram_bankmachine5_cmd_payload_we;
        end
        3'd6: begin
            t_self2 <= litedramcore_sdram_bankmachine6_cmd_payload_we;
        end
        default: begin
            t_self2 <= litedramcore_sdram_bankmachine7_cmd_payload_we;
        end
    endcase
end
always @(*) begin
    rhs_self14 <= 1'd0;
    case (litedramcore_sdram_choose_req_grant)
        1'd0: begin
            rhs_self14 <= litedramcore_sdram_choose_req_valids[0];
        end
        1'd1: begin
            rhs_self14 <= litedramcore_sdram_choose_req_valids[1];
        end
        2'd2: begin
            rhs_self14 <= litedramcore_sdram_choose_req_valids[2];
        end
        2'd3: begin
            rhs_self14 <= litedramcore_sdram_choose_req_valids[3];
        end
        3'd4: begin
            rhs_self14 <= litedramcore_sdram_choose_req_valids[4];
        end
        3'd5: begin
            rhs_self14 <= litedramcore_sdram_choose_req_valids[5];
        end
        3'd6: begin
            rhs_self14 <= litedramcore_sdram_choose_req_valids[6];
        end
        default: begin
            rhs_self14 <= litedramcore_sdram_choose_req_valids[7];
        end
    endcase
end
always @(*) begin
    rhs_self15 <= 15'd0;
    case (litedramcore_sdram_choose_req_grant)
        1'd0: begin
            rhs_self15 <= litedramcore_sdram_bankmachine0_cmd_payload_a;
        end
        1'd1: begin
            rhs_self15 <= litedramcore_sdram_bankmachine1_cmd_payload_a;
        end
        2'd2: begin
            rhs_self15 <= litedramcore_sdram_bankmachine2_cmd_payload_a;
        end
        2'd3: begin
            rhs_self15 <= litedramcore_sdram_bankmachine3_cmd_payload_a;
        end
        3'd4: begin
            rhs_self15 <= litedramcore_sdram_bankmachine4_cmd_payload_a;
        end
        3'd5: begin
            rhs_self15 <= litedramcore_sdram_bankmachine5_cmd_payload_a;
        end
        3'd6: begin
            rhs_self15 <= litedramcore_sdram_bankmachine6_cmd_payload_a;
        end
        default: begin
            rhs_self15 <= litedramcore_sdram_bankmachine7_cmd_payload_a;
        end
    endcase
end
always @(*) begin
    rhs_self16 <= 3'd0;
    case (litedramcore_sdram_choose_req_grant)
        1'd0: begin
            rhs_self16 <= litedramcore_sdram_bankmachine0_cmd_payload_ba;
        end
        1'd1: begin
            rhs_self16 <= litedramcore_sdram_bankmachine1_cmd_payload_ba;
        end
        2'd2: begin
            rhs_self16 <= litedramcore_sdram_bankmachine2_cmd_payload_ba;
        end
        2'd3: begin
            rhs_self16 <= litedramcore_sdram_bankmachine3_cmd_payload_ba;
        end
        3'd4: begin
            rhs_self16 <= litedramcore_sdram_bankmachine4_cmd_payload_ba;
        end
        3'd5: begin
            rhs_self16 <= litedramcore_sdram_bankmachine5_cmd_payload_ba;
        end
        3'd6: begin
            rhs_self16 <= litedramcore_sdram_bankmachine6_cmd_payload_ba;
        end
        default: begin
            rhs_self16 <= litedramcore_sdram_bankmachine7_cmd_payload_ba;
        end
    endcase
end
always @(*) begin
    rhs_self17 <= 1'd0;
    case (litedramcore_sdram_choose_req_grant)
        1'd0: begin
            rhs_self17 <= litedramcore_sdram_bankmachine0_cmd_payload_is_read;
        end
        1'd1: begin
            rhs_self17 <= litedramcore_sdram_bankmachine1_cmd_payload_is_read;
        end
        2'd2: begin
            rhs_self17 <= litedramcore_sdram_bankmachine2_cmd_payload_is_read;
        end
        2'd3: begin
            rhs_self17 <= litedramcore_sdram_bankmachine3_cmd_payload_is_read;
        end
        3'd4: begin
            rhs_self17 <= litedramcore_sdram_bankmachine4_cmd_payload_is_read;
        end
        3'd5: begin
            rhs_self17 <= litedramcore_sdram_bankmachine5_cmd_payload_is_read;
        end
        3'd6: begin
            rhs_self17 <= litedramcore_sdram_bankmachine6_cmd_payload_is_read;
        end
        default: begin
            rhs_self17 <= litedramcore_sdram_bankmachine7_cmd_payload_is_read;
        end
    endcase
end
always @(*) begin
    rhs_self18 <= 1'd0;
    case (litedramcore_sdram_choose_req_grant)
        1'd0: begin
            rhs_self18 <= litedramcore_sdram_bankmachine0_cmd_payload_is_write;
        end
        1'd1: begin
            rhs_self18 <= litedramcore_sdram_bankmachine1_cmd_payload_is_write;
        end
        2'd2: begin
            rhs_self18 <= litedramcore_sdram_bankmachine2_cmd_payload_is_write;
        end
        2'd3: begin
            rhs_self18 <= litedramcore_sdram_bankmachine3_cmd_payload_is_write;
        end
        3'd4: begin
            rhs_self18 <= litedramcore_sdram_bankmachine4_cmd_payload_is_write;
        end
        3'd5: begin
            rhs_self18 <= litedramcore_sdram_bankmachine5_cmd_payload_is_write;
        end
        3'd6: begin
            rhs_self18 <= litedramcore_sdram_bankmachine6_cmd_payload_is_write;
        end
        default: begin
            rhs_self18 <= litedramcore_sdram_bankmachine7_cmd_payload_is_write;
        end
    endcase
end
always @(*) begin
    rhs_self19 <= 1'd0;
    case (litedramcore_sdram_choose_req_grant)
        1'd0: begin
            rhs_self19 <= litedramcore_sdram_bankmachine0_cmd_payload_is_cmd;
        end
        1'd1: begin
            rhs_self19 <= litedramcore_sdram_bankmachine1_cmd_payload_is_cmd;
        end
        2'd2: begin
            rhs_self19 <= litedramcore_sdram_bankmachine2_cmd_payload_is_cmd;
        end
        2'd3: begin
            rhs_self19 <= litedramcore_sdram_bankmachine3_cmd_payload_is_cmd;
        end
        3'd4: begin
            rhs_self19 <= litedramcore_sdram_bankmachine4_cmd_payload_is_cmd;
        end
        3'd5: begin
            rhs_self19 <= litedramcore_sdram_bankmachine5_cmd_payload_is_cmd;
        end
        3'd6: begin
            rhs_self19 <= litedramcore_sdram_bankmachine6_cmd_payload_is_cmd;
        end
        default: begin
            rhs_self19 <= litedramcore_sdram_bankmachine7_cmd_payload_is_cmd;
        end
    endcase
end
always @(*) begin
    t_self3 <= 1'd0;
    case (litedramcore_sdram_choose_req_grant)
        1'd0: begin
            t_self3 <= litedramcore_sdram_bankmachine0_cmd_payload_cas;
        end
        1'd1: begin
            t_self3 <= litedramcore_sdram_bankmachine1_cmd_payload_cas;
        end
        2'd2: begin
            t_self3 <= litedramcore_sdram_bankmachine2_cmd_payload_cas;
        end
        2'd3: begin
            t_self3 <= litedramcore_sdram_bankmachine3_cmd_payload_cas;
        end
        3'd4: begin
            t_self3 <= litedramcore_sdram_bankmachine4_cmd_payload_cas;
        end
        3'd5: begin
            t_self3 <= litedramcore_sdram_bankmachine5_cmd_payload_cas;
        end
        3'd6: begin
            t_self3 <= litedramcore_sdram_bankmachine6_cmd_payload_cas;
        end
        default: begin
            t_self3 <= litedramcore_sdram_bankmachine7_cmd_payload_cas;
        end
    endcase
end
always @(*) begin
    t_self4 <= 1'd0;
    case (litedramcore_sdram_choose_req_grant)
        1'd0: begin
            t_self4 <= litedramcore_sdram_bankmachine0_cmd_payload_ras;
        end
        1'd1: begin
            t_self4 <= litedramcore_sdram_bankmachine1_cmd_payload_ras;
        end
        2'd2: begin
            t_self4 <= litedramcore_sdram_bankmachine2_cmd_payload_ras;
        end
        2'd3: begin
            t_self4 <= litedramcore_sdram_bankmachine3_cmd_payload_ras;
        end
        3'd4: begin
            t_self4 <= litedramcore_sdram_bankmachine4_cmd_payload_ras;
        end
        3'd5: begin
            t_self4 <= litedramcore_sdram_bankmachine5_cmd_payload_ras;
        end
        3'd6: begin
            t_self4 <= litedramcore_sdram_bankmachine6_cmd_payload_ras;
        end
        default: begin
            t_self4 <= litedramcore_sdram_bankmachine7_cmd_payload_ras;
        end
    endcase
end
always @(*) begin
    t_self5 <= 1'd0;
    case (litedramcore_sdram_choose_req_grant)
        1'd0: begin
            t_self5 <= litedramcore_sdram_bankmachine0_cmd_payload_we;
        end
        1'd1: begin
            t_self5 <= litedramcore_sdram_bankmachine1_cmd_payload_we;
        end
        2'd2: begin
            t_self5 <= litedramcore_sdram_bankmachine2_cmd_payload_we;
        end
        2'd3: begin
            t_self5 <= litedramcore_sdram_bankmachine3_cmd_payload_we;
        end
        3'd4: begin
            t_self5 <= litedramcore_sdram_bankmachine4_cmd_payload_we;
        end
        3'd5: begin
            t_self5 <= litedramcore_sdram_bankmachine5_cmd_payload_we;
        end
        3'd6: begin
            t_self5 <= litedramcore_sdram_bankmachine6_cmd_payload_we;
        end
        default: begin
            t_self5 <= litedramcore_sdram_bankmachine7_cmd_payload_we;
        end
    endcase
end
always @(*) begin
    rhs_self20 <= 22'd0;
    case (litedramcore_roundrobin0_grant)
        1'd0: begin
            rhs_self20 <= {litedramcore_port_cmd_payload_addr[24:10], litedramcore_port_cmd_payload_addr[6:0]};
        end
        default: begin
            rhs_self20 <= {user_port_port_cmd_payload_addr[24:10], user_port_port_cmd_payload_addr[6:0]};
        end
    endcase
end
always @(*) begin
    rhs_self21 <= 1'd0;
    case (litedramcore_roundrobin0_grant)
        1'd0: begin
            rhs_self21 <= litedramcore_port_cmd_payload_we;
        end
        default: begin
            rhs_self21 <= user_port_port_cmd_payload_we;
        end
    endcase
end
always @(*) begin
    rhs_self22 <= 1'd0;
    case (litedramcore_roundrobin0_grant)
        1'd0: begin
            rhs_self22 <= (((litedramcore_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & litedramcore_port_cmd_valid);
        end
        default: begin
            rhs_self22 <= (((user_port_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked1 | (litedramcore_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd1))) | (litedramcore_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd1))) | (litedramcore_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd1))) | (litedramcore_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd1))) | (litedramcore_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd1))) | (litedramcore_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd1))) | (litedramcore_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd1))))) & user_port_port_cmd_valid);
        end
    endcase
end
always @(*) begin
    rhs_self23 <= 22'd0;
    case (litedramcore_roundrobin1_grant)
        1'd0: begin
            rhs_self23 <= {litedramcore_port_cmd_payload_addr[24:10], litedramcore_port_cmd_payload_addr[6:0]};
        end
        default: begin
            rhs_self23 <= {user_port_port_cmd_payload_addr[24:10], user_port_port_cmd_payload_addr[6:0]};
        end
    endcase
end
always @(*) begin
    rhs_self24 <= 1'd0;
    case (litedramcore_roundrobin1_grant)
        1'd0: begin
            rhs_self24 <= litedramcore_port_cmd_payload_we;
        end
        default: begin
            rhs_self24 <= user_port_port_cmd_payload_we;
        end
    endcase
end
always @(*) begin
    rhs_self25 <= 1'd0;
    case (litedramcore_roundrobin1_grant)
        1'd0: begin
            rhs_self25 <= (((litedramcore_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked2 | (litedramcore_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & litedramcore_port_cmd_valid);
        end
        default: begin
            rhs_self25 <= (((user_port_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked3 | (litedramcore_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd1))) | (litedramcore_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd1))) | (litedramcore_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd1))) | (litedramcore_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd1))) | (litedramcore_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd1))) | (litedramcore_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd1))) | (litedramcore_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd1))))) & user_port_port_cmd_valid);
        end
    endcase
end
always @(*) begin
    rhs_self26 <= 22'd0;
    case (litedramcore_roundrobin2_grant)
        1'd0: begin
            rhs_self26 <= {litedramcore_port_cmd_payload_addr[24:10], litedramcore_port_cmd_payload_addr[6:0]};
        end
        default: begin
            rhs_self26 <= {user_port_port_cmd_payload_addr[24:10], user_port_port_cmd_payload_addr[6:0]};
        end
    endcase
end
always @(*) begin
    rhs_self27 <= 1'd0;
    case (litedramcore_roundrobin2_grant)
        1'd0: begin
            rhs_self27 <= litedramcore_port_cmd_payload_we;
        end
        default: begin
            rhs_self27 <= user_port_port_cmd_payload_we;
        end
    endcase
end
always @(*) begin
    rhs_self28 <= 1'd0;
    case (litedramcore_roundrobin2_grant)
        1'd0: begin
            rhs_self28 <= (((litedramcore_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked4 | (litedramcore_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & litedramcore_port_cmd_valid);
        end
        default: begin
            rhs_self28 <= (((user_port_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked5 | (litedramcore_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd1))) | (litedramcore_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd1))) | (litedramcore_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd1))) | (litedramcore_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd1))) | (litedramcore_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd1))) | (litedramcore_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd1))) | (litedramcore_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd1))))) & user_port_port_cmd_valid);
        end
    endcase
end
always @(*) begin
    rhs_self29 <= 22'd0;
    case (litedramcore_roundrobin3_grant)
        1'd0: begin
            rhs_self29 <= {litedramcore_port_cmd_payload_addr[24:10], litedramcore_port_cmd_payload_addr[6:0]};
        end
        default: begin
            rhs_self29 <= {user_port_port_cmd_payload_addr[24:10], user_port_port_cmd_payload_addr[6:0]};
        end
    endcase
end
always @(*) begin
    rhs_self30 <= 1'd0;
    case (litedramcore_roundrobin3_grant)
        1'd0: begin
            rhs_self30 <= litedramcore_port_cmd_payload_we;
        end
        default: begin
            rhs_self30 <= user_port_port_cmd_payload_we;
        end
    endcase
end
always @(*) begin
    rhs_self31 <= 1'd0;
    case (litedramcore_roundrobin3_grant)
        1'd0: begin
            rhs_self31 <= (((litedramcore_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked6 | (litedramcore_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & litedramcore_port_cmd_valid);
        end
        default: begin
            rhs_self31 <= (((user_port_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked7 | (litedramcore_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd1))) | (litedramcore_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd1))) | (litedramcore_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd1))) | (litedramcore_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd1))) | (litedramcore_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd1))) | (litedramcore_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd1))) | (litedramcore_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd1))))) & user_port_port_cmd_valid);
        end
    endcase
end
always @(*) begin
    rhs_self32 <= 22'd0;
    case (litedramcore_roundrobin4_grant)
        1'd0: begin
            rhs_self32 <= {litedramcore_port_cmd_payload_addr[24:10], litedramcore_port_cmd_payload_addr[6:0]};
        end
        default: begin
            rhs_self32 <= {user_port_port_cmd_payload_addr[24:10], user_port_port_cmd_payload_addr[6:0]};
        end
    endcase
end
always @(*) begin
    rhs_self33 <= 1'd0;
    case (litedramcore_roundrobin4_grant)
        1'd0: begin
            rhs_self33 <= litedramcore_port_cmd_payload_we;
        end
        default: begin
            rhs_self33 <= user_port_port_cmd_payload_we;
        end
    endcase
end
always @(*) begin
    rhs_self34 <= 1'd0;
    case (litedramcore_roundrobin4_grant)
        1'd0: begin
            rhs_self34 <= (((litedramcore_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked8 | (litedramcore_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & litedramcore_port_cmd_valid);
        end
        default: begin
            rhs_self34 <= (((user_port_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked9 | (litedramcore_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd1))) | (litedramcore_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd1))) | (litedramcore_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd1))) | (litedramcore_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd1))) | (litedramcore_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd1))) | (litedramcore_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd1))) | (litedramcore_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd1))))) & user_port_port_cmd_valid);
        end
    endcase
end
always @(*) begin
    rhs_self35 <= 22'd0;
    case (litedramcore_roundrobin5_grant)
        1'd0: begin
            rhs_self35 <= {litedramcore_port_cmd_payload_addr[24:10], litedramcore_port_cmd_payload_addr[6:0]};
        end
        default: begin
            rhs_self35 <= {user_port_port_cmd_payload_addr[24:10], user_port_port_cmd_payload_addr[6:0]};
        end
    endcase
end
always @(*) begin
    rhs_self36 <= 1'd0;
    case (litedramcore_roundrobin5_grant)
        1'd0: begin
            rhs_self36 <= litedramcore_port_cmd_payload_we;
        end
        default: begin
            rhs_self36 <= user_port_port_cmd_payload_we;
        end
    endcase
end
always @(*) begin
    rhs_self37 <= 1'd0;
    case (litedramcore_roundrobin5_grant)
        1'd0: begin
            rhs_self37 <= (((litedramcore_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked10 | (litedramcore_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & litedramcore_port_cmd_valid);
        end
        default: begin
            rhs_self37 <= (((user_port_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked11 | (litedramcore_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd1))) | (litedramcore_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd1))) | (litedramcore_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd1))) | (litedramcore_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd1))) | (litedramcore_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd1))) | (litedramcore_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd1))) | (litedramcore_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd1))))) & user_port_port_cmd_valid);
        end
    endcase
end
always @(*) begin
    rhs_self38 <= 22'd0;
    case (litedramcore_roundrobin6_grant)
        1'd0: begin
            rhs_self38 <= {litedramcore_port_cmd_payload_addr[24:10], litedramcore_port_cmd_payload_addr[6:0]};
        end
        default: begin
            rhs_self38 <= {user_port_port_cmd_payload_addr[24:10], user_port_port_cmd_payload_addr[6:0]};
        end
    endcase
end
always @(*) begin
    rhs_self39 <= 1'd0;
    case (litedramcore_roundrobin6_grant)
        1'd0: begin
            rhs_self39 <= litedramcore_port_cmd_payload_we;
        end
        default: begin
            rhs_self39 <= user_port_port_cmd_payload_we;
        end
    endcase
end
always @(*) begin
    rhs_self40 <= 1'd0;
    case (litedramcore_roundrobin6_grant)
        1'd0: begin
            rhs_self40 <= (((litedramcore_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked12 | (litedramcore_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & litedramcore_port_cmd_valid);
        end
        default: begin
            rhs_self40 <= (((user_port_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked13 | (litedramcore_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd1))) | (litedramcore_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd1))) | (litedramcore_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd1))) | (litedramcore_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd1))) | (litedramcore_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd1))) | (litedramcore_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd1))) | (litedramcore_sdram_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd1))))) & user_port_port_cmd_valid);
        end
    endcase
end
always @(*) begin
    rhs_self41 <= 22'd0;
    case (litedramcore_roundrobin7_grant)
        1'd0: begin
            rhs_self41 <= {litedramcore_port_cmd_payload_addr[24:10], litedramcore_port_cmd_payload_addr[6:0]};
        end
        default: begin
            rhs_self41 <= {user_port_port_cmd_payload_addr[24:10], user_port_port_cmd_payload_addr[6:0]};
        end
    endcase
end
always @(*) begin
    rhs_self42 <= 1'd0;
    case (litedramcore_roundrobin7_grant)
        1'd0: begin
            rhs_self42 <= litedramcore_port_cmd_payload_we;
        end
        default: begin
            rhs_self42 <= user_port_port_cmd_payload_we;
        end
    endcase
end
always @(*) begin
    rhs_self43 <= 1'd0;
    case (litedramcore_roundrobin7_grant)
        1'd0: begin
            rhs_self43 <= (((litedramcore_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked14 | (litedramcore_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & litedramcore_port_cmd_valid);
        end
        default: begin
            rhs_self43 <= (((user_port_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked15 | (litedramcore_sdram_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd1))) | (litedramcore_sdram_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd1))) | (litedramcore_sdram_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd1))) | (litedramcore_sdram_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd1))) | (litedramcore_sdram_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd1))) | (litedramcore_sdram_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd1))) | (litedramcore_sdram_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd1))))) & user_port_port_cmd_valid);
        end
    endcase
end
always @(*) begin
    self0 <= 3'd0;
    case (litedramcore_sdram_steerer0)
        1'd0: begin
            self0 <= litedramcore_sdram_nop_ba;
        end
        1'd1: begin
            self0 <= litedramcore_sdram_choose_cmd_cmd_payload_ba;
        end
        2'd2: begin
            self0 <= litedramcore_sdram_choose_req_cmd_payload_ba;
        end
        default: begin
            self0 <= litedramcore_sdram_cmd_payload_ba;
        end
    endcase
end
always @(*) begin
    self1 <= 15'd0;
    case (litedramcore_sdram_steerer0)
        1'd0: begin
            self1 <= litedramcore_sdram_nop_a;
        end
        1'd1: begin
            self1 <= litedramcore_sdram_choose_cmd_cmd_payload_a;
        end
        2'd2: begin
            self1 <= litedramcore_sdram_choose_req_cmd_payload_a;
        end
        default: begin
            self1 <= litedramcore_sdram_cmd_payload_a;
        end
    endcase
end
always @(*) begin
    self2 <= 1'd0;
    case (litedramcore_sdram_steerer0)
        1'd0: begin
            self2 <= 1'd0;
        end
        1'd1: begin
            self2 <= ((litedramcore_sdram_choose_cmd_cmd_valid & litedramcore_sdram_choose_cmd_cmd_ready) & litedramcore_sdram_choose_cmd_cmd_payload_cas);
        end
        2'd2: begin
            self2 <= ((litedramcore_sdram_choose_req_cmd_valid & litedramcore_sdram_choose_req_cmd_ready) & litedramcore_sdram_choose_req_cmd_payload_cas);
        end
        default: begin
            self2 <= ((litedramcore_sdram_cmd_valid & litedramcore_sdram_cmd_ready) & litedramcore_sdram_cmd_payload_cas);
        end
    endcase
end
always @(*) begin
    self3 <= 1'd0;
    case (litedramcore_sdram_steerer0)
        1'd0: begin
            self3 <= 1'd0;
        end
        1'd1: begin
            self3 <= ((litedramcore_sdram_choose_cmd_cmd_valid & litedramcore_sdram_choose_cmd_cmd_ready) & litedramcore_sdram_choose_cmd_cmd_payload_ras);
        end
        2'd2: begin
            self3 <= ((litedramcore_sdram_choose_req_cmd_valid & litedramcore_sdram_choose_req_cmd_ready) & litedramcore_sdram_choose_req_cmd_payload_ras);
        end
        default: begin
            self3 <= ((litedramcore_sdram_cmd_valid & litedramcore_sdram_cmd_ready) & litedramcore_sdram_cmd_payload_ras);
        end
    endcase
end
always @(*) begin
    self4 <= 1'd0;
    case (litedramcore_sdram_steerer0)
        1'd0: begin
            self4 <= 1'd0;
        end
        1'd1: begin
            self4 <= ((litedramcore_sdram_choose_cmd_cmd_valid & litedramcore_sdram_choose_cmd_cmd_ready) & litedramcore_sdram_choose_cmd_cmd_payload_we);
        end
        2'd2: begin
            self4 <= ((litedramcore_sdram_choose_req_cmd_valid & litedramcore_sdram_choose_req_cmd_ready) & litedramcore_sdram_choose_req_cmd_payload_we);
        end
        default: begin
            self4 <= ((litedramcore_sdram_cmd_valid & litedramcore_sdram_cmd_ready) & litedramcore_sdram_cmd_payload_we);
        end
    endcase
end
always @(*) begin
    self5 <= 1'd0;
    case (litedramcore_sdram_steerer0)
        1'd0: begin
            self5 <= 1'd0;
        end
        1'd1: begin
            self5 <= ((litedramcore_sdram_choose_cmd_cmd_valid & litedramcore_sdram_choose_cmd_cmd_ready) & litedramcore_sdram_choose_cmd_cmd_payload_is_read);
        end
        2'd2: begin
            self5 <= ((litedramcore_sdram_choose_req_cmd_valid & litedramcore_sdram_choose_req_cmd_ready) & litedramcore_sdram_choose_req_cmd_payload_is_read);
        end
        default: begin
            self5 <= ((litedramcore_sdram_cmd_valid & litedramcore_sdram_cmd_ready) & litedramcore_sdram_cmd_payload_is_read);
        end
    endcase
end
always @(*) begin
    self6 <= 1'd0;
    case (litedramcore_sdram_steerer0)
        1'd0: begin
            self6 <= 1'd0;
        end
        1'd1: begin
            self6 <= ((litedramcore_sdram_choose_cmd_cmd_valid & litedramcore_sdram_choose_cmd_cmd_ready) & litedramcore_sdram_choose_cmd_cmd_payload_is_write);
        end
        2'd2: begin
            self6 <= ((litedramcore_sdram_choose_req_cmd_valid & litedramcore_sdram_choose_req_cmd_ready) & litedramcore_sdram_choose_req_cmd_payload_is_write);
        end
        default: begin
            self6 <= ((litedramcore_sdram_cmd_valid & litedramcore_sdram_cmd_ready) & litedramcore_sdram_cmd_payload_is_write);
        end
    endcase
end
always @(*) begin
    self7 <= 3'd0;
    case (litedramcore_sdram_steerer1)
        1'd0: begin
            self7 <= litedramcore_sdram_nop_ba;
        end
        1'd1: begin
            self7 <= litedramcore_sdram_choose_cmd_cmd_payload_ba;
        end
        2'd2: begin
            self7 <= litedramcore_sdram_choose_req_cmd_payload_ba;
        end
        default: begin
            self7 <= litedramcore_sdram_cmd_payload_ba;
        end
    endcase
end
always @(*) begin
    self8 <= 15'd0;
    case (litedramcore_sdram_steerer1)
        1'd0: begin
            self8 <= litedramcore_sdram_nop_a;
        end
        1'd1: begin
            self8 <= litedramcore_sdram_choose_cmd_cmd_payload_a;
        end
        2'd2: begin
            self8 <= litedramcore_sdram_choose_req_cmd_payload_a;
        end
        default: begin
            self8 <= litedramcore_sdram_cmd_payload_a;
        end
    endcase
end
always @(*) begin
    self9 <= 1'd0;
    case (litedramcore_sdram_steerer1)
        1'd0: begin
            self9 <= 1'd0;
        end
        1'd1: begin
            self9 <= ((litedramcore_sdram_choose_cmd_cmd_valid & litedramcore_sdram_choose_cmd_cmd_ready) & litedramcore_sdram_choose_cmd_cmd_payload_cas);
        end
        2'd2: begin
            self9 <= ((litedramcore_sdram_choose_req_cmd_valid & litedramcore_sdram_choose_req_cmd_ready) & litedramcore_sdram_choose_req_cmd_payload_cas);
        end
        default: begin
            self9 <= ((litedramcore_sdram_cmd_valid & litedramcore_sdram_cmd_ready) & litedramcore_sdram_cmd_payload_cas);
        end
    endcase
end
always @(*) begin
    self10 <= 1'd0;
    case (litedramcore_sdram_steerer1)
        1'd0: begin
            self10 <= 1'd0;
        end
        1'd1: begin
            self10 <= ((litedramcore_sdram_choose_cmd_cmd_valid & litedramcore_sdram_choose_cmd_cmd_ready) & litedramcore_sdram_choose_cmd_cmd_payload_ras);
        end
        2'd2: begin
            self10 <= ((litedramcore_sdram_choose_req_cmd_valid & litedramcore_sdram_choose_req_cmd_ready) & litedramcore_sdram_choose_req_cmd_payload_ras);
        end
        default: begin
            self10 <= ((litedramcore_sdram_cmd_valid & litedramcore_sdram_cmd_ready) & litedramcore_sdram_cmd_payload_ras);
        end
    endcase
end
always @(*) begin
    self11 <= 1'd0;
    case (litedramcore_sdram_steerer1)
        1'd0: begin
            self11 <= 1'd0;
        end
        1'd1: begin
            self11 <= ((litedramcore_sdram_choose_cmd_cmd_valid & litedramcore_sdram_choose_cmd_cmd_ready) & litedramcore_sdram_choose_cmd_cmd_payload_we);
        end
        2'd2: begin
            self11 <= ((litedramcore_sdram_choose_req_cmd_valid & litedramcore_sdram_choose_req_cmd_ready) & litedramcore_sdram_choose_req_cmd_payload_we);
        end
        default: begin
            self11 <= ((litedramcore_sdram_cmd_valid & litedramcore_sdram_cmd_ready) & litedramcore_sdram_cmd_payload_we);
        end
    endcase
end
always @(*) begin
    self12 <= 1'd0;
    case (litedramcore_sdram_steerer1)
        1'd0: begin
            self12 <= 1'd0;
        end
        1'd1: begin
            self12 <= ((litedramcore_sdram_choose_cmd_cmd_valid & litedramcore_sdram_choose_cmd_cmd_ready) & litedramcore_sdram_choose_cmd_cmd_payload_is_read);
        end
        2'd2: begin
            self12 <= ((litedramcore_sdram_choose_req_cmd_valid & litedramcore_sdram_choose_req_cmd_ready) & litedramcore_sdram_choose_req_cmd_payload_is_read);
        end
        default: begin
            self12 <= ((litedramcore_sdram_cmd_valid & litedramcore_sdram_cmd_ready) & litedramcore_sdram_cmd_payload_is_read);
        end
    endcase
end
always @(*) begin
    self13 <= 1'd0;
    case (litedramcore_sdram_steerer1)
        1'd0: begin
            self13 <= 1'd0;
        end
        1'd1: begin
            self13 <= ((litedramcore_sdram_choose_cmd_cmd_valid & litedramcore_sdram_choose_cmd_cmd_ready) & litedramcore_sdram_choose_cmd_cmd_payload_is_write);
        end
        2'd2: begin
            self13 <= ((litedramcore_sdram_choose_req_cmd_valid & litedramcore_sdram_choose_req_cmd_ready) & litedramcore_sdram_choose_req_cmd_payload_is_write);
        end
        default: begin
            self13 <= ((litedramcore_sdram_cmd_valid & litedramcore_sdram_cmd_ready) & litedramcore_sdram_cmd_payload_is_write);
        end
    endcase
end
always @(*) begin
    self14 <= 3'd0;
    case (litedramcore_sdram_steerer2)
        1'd0: begin
            self14 <= litedramcore_sdram_nop_ba;
        end
        1'd1: begin
            self14 <= litedramcore_sdram_choose_cmd_cmd_payload_ba;
        end
        2'd2: begin
            self14 <= litedramcore_sdram_choose_req_cmd_payload_ba;
        end
        default: begin
            self14 <= litedramcore_sdram_cmd_payload_ba;
        end
    endcase
end
always @(*) begin
    self15 <= 15'd0;
    case (litedramcore_sdram_steerer2)
        1'd0: begin
            self15 <= litedramcore_sdram_nop_a;
        end
        1'd1: begin
            self15 <= litedramcore_sdram_choose_cmd_cmd_payload_a;
        end
        2'd2: begin
            self15 <= litedramcore_sdram_choose_req_cmd_payload_a;
        end
        default: begin
            self15 <= litedramcore_sdram_cmd_payload_a;
        end
    endcase
end
always @(*) begin
    self16 <= 1'd0;
    case (litedramcore_sdram_steerer2)
        1'd0: begin
            self16 <= 1'd0;
        end
        1'd1: begin
            self16 <= ((litedramcore_sdram_choose_cmd_cmd_valid & litedramcore_sdram_choose_cmd_cmd_ready) & litedramcore_sdram_choose_cmd_cmd_payload_cas);
        end
        2'd2: begin
            self16 <= ((litedramcore_sdram_choose_req_cmd_valid & litedramcore_sdram_choose_req_cmd_ready) & litedramcore_sdram_choose_req_cmd_payload_cas);
        end
        default: begin
            self16 <= ((litedramcore_sdram_cmd_valid & litedramcore_sdram_cmd_ready) & litedramcore_sdram_cmd_payload_cas);
        end
    endcase
end
always @(*) begin
    self17 <= 1'd0;
    case (litedramcore_sdram_steerer2)
        1'd0: begin
            self17 <= 1'd0;
        end
        1'd1: begin
            self17 <= ((litedramcore_sdram_choose_cmd_cmd_valid & litedramcore_sdram_choose_cmd_cmd_ready) & litedramcore_sdram_choose_cmd_cmd_payload_ras);
        end
        2'd2: begin
            self17 <= ((litedramcore_sdram_choose_req_cmd_valid & litedramcore_sdram_choose_req_cmd_ready) & litedramcore_sdram_choose_req_cmd_payload_ras);
        end
        default: begin
            self17 <= ((litedramcore_sdram_cmd_valid & litedramcore_sdram_cmd_ready) & litedramcore_sdram_cmd_payload_ras);
        end
    endcase
end
always @(*) begin
    self18 <= 1'd0;
    case (litedramcore_sdram_steerer2)
        1'd0: begin
            self18 <= 1'd0;
        end
        1'd1: begin
            self18 <= ((litedramcore_sdram_choose_cmd_cmd_valid & litedramcore_sdram_choose_cmd_cmd_ready) & litedramcore_sdram_choose_cmd_cmd_payload_we);
        end
        2'd2: begin
            self18 <= ((litedramcore_sdram_choose_req_cmd_valid & litedramcore_sdram_choose_req_cmd_ready) & litedramcore_sdram_choose_req_cmd_payload_we);
        end
        default: begin
            self18 <= ((litedramcore_sdram_cmd_valid & litedramcore_sdram_cmd_ready) & litedramcore_sdram_cmd_payload_we);
        end
    endcase
end
always @(*) begin
    self19 <= 1'd0;
    case (litedramcore_sdram_steerer2)
        1'd0: begin
            self19 <= 1'd0;
        end
        1'd1: begin
            self19 <= ((litedramcore_sdram_choose_cmd_cmd_valid & litedramcore_sdram_choose_cmd_cmd_ready) & litedramcore_sdram_choose_cmd_cmd_payload_is_read);
        end
        2'd2: begin
            self19 <= ((litedramcore_sdram_choose_req_cmd_valid & litedramcore_sdram_choose_req_cmd_ready) & litedramcore_sdram_choose_req_cmd_payload_is_read);
        end
        default: begin
            self19 <= ((litedramcore_sdram_cmd_valid & litedramcore_sdram_cmd_ready) & litedramcore_sdram_cmd_payload_is_read);
        end
    endcase
end
always @(*) begin
    self20 <= 1'd0;
    case (litedramcore_sdram_steerer2)
        1'd0: begin
            self20 <= 1'd0;
        end
        1'd1: begin
            self20 <= ((litedramcore_sdram_choose_cmd_cmd_valid & litedramcore_sdram_choose_cmd_cmd_ready) & litedramcore_sdram_choose_cmd_cmd_payload_is_write);
        end
        2'd2: begin
            self20 <= ((litedramcore_sdram_choose_req_cmd_valid & litedramcore_sdram_choose_req_cmd_ready) & litedramcore_sdram_choose_req_cmd_payload_is_write);
        end
        default: begin
            self20 <= ((litedramcore_sdram_cmd_valid & litedramcore_sdram_cmd_ready) & litedramcore_sdram_cmd_payload_is_write);
        end
    endcase
end
always @(*) begin
    self21 <= 3'd0;
    case (litedramcore_sdram_steerer3)
        1'd0: begin
            self21 <= litedramcore_sdram_nop_ba;
        end
        1'd1: begin
            self21 <= litedramcore_sdram_choose_cmd_cmd_payload_ba;
        end
        2'd2: begin
            self21 <= litedramcore_sdram_choose_req_cmd_payload_ba;
        end
        default: begin
            self21 <= litedramcore_sdram_cmd_payload_ba;
        end
    endcase
end
always @(*) begin
    self22 <= 15'd0;
    case (litedramcore_sdram_steerer3)
        1'd0: begin
            self22 <= litedramcore_sdram_nop_a;
        end
        1'd1: begin
            self22 <= litedramcore_sdram_choose_cmd_cmd_payload_a;
        end
        2'd2: begin
            self22 <= litedramcore_sdram_choose_req_cmd_payload_a;
        end
        default: begin
            self22 <= litedramcore_sdram_cmd_payload_a;
        end
    endcase
end
always @(*) begin
    self23 <= 1'd0;
    case (litedramcore_sdram_steerer3)
        1'd0: begin
            self23 <= 1'd0;
        end
        1'd1: begin
            self23 <= ((litedramcore_sdram_choose_cmd_cmd_valid & litedramcore_sdram_choose_cmd_cmd_ready) & litedramcore_sdram_choose_cmd_cmd_payload_cas);
        end
        2'd2: begin
            self23 <= ((litedramcore_sdram_choose_req_cmd_valid & litedramcore_sdram_choose_req_cmd_ready) & litedramcore_sdram_choose_req_cmd_payload_cas);
        end
        default: begin
            self23 <= ((litedramcore_sdram_cmd_valid & litedramcore_sdram_cmd_ready) & litedramcore_sdram_cmd_payload_cas);
        end
    endcase
end
always @(*) begin
    self24 <= 1'd0;
    case (litedramcore_sdram_steerer3)
        1'd0: begin
            self24 <= 1'd0;
        end
        1'd1: begin
            self24 <= ((litedramcore_sdram_choose_cmd_cmd_valid & litedramcore_sdram_choose_cmd_cmd_ready) & litedramcore_sdram_choose_cmd_cmd_payload_ras);
        end
        2'd2: begin
            self24 <= ((litedramcore_sdram_choose_req_cmd_valid & litedramcore_sdram_choose_req_cmd_ready) & litedramcore_sdram_choose_req_cmd_payload_ras);
        end
        default: begin
            self24 <= ((litedramcore_sdram_cmd_valid & litedramcore_sdram_cmd_ready) & litedramcore_sdram_cmd_payload_ras);
        end
    endcase
end
always @(*) begin
    self25 <= 1'd0;
    case (litedramcore_sdram_steerer3)
        1'd0: begin
            self25 <= 1'd0;
        end
        1'd1: begin
            self25 <= ((litedramcore_sdram_choose_cmd_cmd_valid & litedramcore_sdram_choose_cmd_cmd_ready) & litedramcore_sdram_choose_cmd_cmd_payload_we);
        end
        2'd2: begin
            self25 <= ((litedramcore_sdram_choose_req_cmd_valid & litedramcore_sdram_choose_req_cmd_ready) & litedramcore_sdram_choose_req_cmd_payload_we);
        end
        default: begin
            self25 <= ((litedramcore_sdram_cmd_valid & litedramcore_sdram_cmd_ready) & litedramcore_sdram_cmd_payload_we);
        end
    endcase
end
always @(*) begin
    self26 <= 1'd0;
    case (litedramcore_sdram_steerer3)
        1'd0: begin
            self26 <= 1'd0;
        end
        1'd1: begin
            self26 <= ((litedramcore_sdram_choose_cmd_cmd_valid & litedramcore_sdram_choose_cmd_cmd_ready) & litedramcore_sdram_choose_cmd_cmd_payload_is_read);
        end
        2'd2: begin
            self26 <= ((litedramcore_sdram_choose_req_cmd_valid & litedramcore_sdram_choose_req_cmd_ready) & litedramcore_sdram_choose_req_cmd_payload_is_read);
        end
        default: begin
            self26 <= ((litedramcore_sdram_cmd_valid & litedramcore_sdram_cmd_ready) & litedramcore_sdram_cmd_payload_is_read);
        end
    endcase
end
always @(*) begin
    self27 <= 1'd0;
    case (litedramcore_sdram_steerer3)
        1'd0: begin
            self27 <= 1'd0;
        end
        1'd1: begin
            self27 <= ((litedramcore_sdram_choose_cmd_cmd_valid & litedramcore_sdram_choose_cmd_cmd_ready) & litedramcore_sdram_choose_cmd_cmd_payload_is_write);
        end
        2'd2: begin
            self27 <= ((litedramcore_sdram_choose_req_cmd_valid & litedramcore_sdram_choose_req_cmd_ready) & litedramcore_sdram_choose_req_cmd_payload_is_write);
        end
        default: begin
            self27 <= ((litedramcore_sdram_cmd_valid & litedramcore_sdram_cmd_ready) & litedramcore_sdram_cmd_payload_is_write);
        end
    endcase
end
assign rx_rx = xilinxmultiregimpl1;
assign xilinxasyncresetsynchronizerimpl0 = (~crg_locked);
assign xilinxasyncresetsynchronizerimpl1 = (~crg_locked);
assign xilinxasyncresetsynchronizerimpl2 = (~crg_locked);
assign xilinxasyncresetsynchronizerimpl3 = (~crg_locked);


//------------------------------------------------------------------------------
// Synchronous Logic
//------------------------------------------------------------------------------

always @(posedge iodelay_clk) begin
    if ((crg_reset_counter != 1'd0)) begin
        crg_reset_counter <= (crg_reset_counter - 1'd1);
    end else begin
        crg_ic_reset <= 1'd0;
    end
    if (iodelay_rst) begin
        crg_reset_counter <= 4'd15;
        crg_ic_reset <= 1'd1;
    end
end

always @(posedge sys_clk) begin
    user_enable <= (init_done_storage & (~init_error_storage));
    case (grant)
        1'd0: begin
            if ((~request[0])) begin
                if (request[1]) begin
                    grant <= 1'd1;
                end
            end
        end
        1'd1: begin
            if ((~request[1])) begin
                if (request[0]) begin
                    grant <= 1'd0;
                end
            end
        end
    endcase
    slave_sel_r <= slave_sel;
    if (wait_1) begin
        if ((~done)) begin
            count <= (count - 1'd1);
        end
    end else begin
        count <= 20'd1000000;
    end
    if ((litedramcore_bus_errors != 32'd4294967295)) begin
        if (litedramcore_bus_error) begin
            litedramcore_bus_errors <= (litedramcore_bus_errors + 1'd1);
        end
    end
    litedramcore_litedramcore_ram_bus_ack <= 1'd0;
    if (((litedramcore_litedramcore_ram_bus_cyc & litedramcore_litedramcore_ram_bus_stb) & ((~litedramcore_litedramcore_ram_bus_ack) | litedramcore_litedramcore_adr_burst))) begin
        litedramcore_litedramcore_ram_bus_ack <= 1'd1;
    end
    litedramcore_ram_bus_ram_bus_ack <= 1'd0;
    if (((litedramcore_ram_bus_ram_bus_cyc & litedramcore_ram_bus_ram_bus_stb) & ((~litedramcore_ram_bus_ram_bus_ack) | litedramcore_ram_adr_burst))) begin
        litedramcore_ram_bus_ram_bus_ack <= 1'd1;
    end
    if (litedramcore_en_storage) begin
        if ((litedramcore_value == 1'd0)) begin
            litedramcore_value <= litedramcore_reload_storage;
        end else begin
            litedramcore_value <= (litedramcore_value - 1'd1);
        end
    end else begin
        litedramcore_value <= litedramcore_load_storage;
    end
    if (litedramcore_update_value_re) begin
        litedramcore_value_status <= litedramcore_value;
    end
    if (litedramcore_zero_clear) begin
        litedramcore_zero_pending <= 1'd0;
    end
    litedramcore_zero_trigger_d <= litedramcore_zero_trigger;
    if ((litedramcore_zero_trigger & (~litedramcore_zero_trigger_d))) begin
        litedramcore_zero_pending <= 1'd1;
    end
    {tx_tick, tx_phase} <= 22'd2473901;
    if (tx_enable) begin
        {tx_tick, tx_phase} <= (tx_phase + 22'd2473901);
    end
    rs232phytx_state <= rs232phytx_next_state;
    if (tx_count_rs232phytx_next_value_ce0) begin
        tx_count <= tx_count_rs232phytx_next_value0;
    end
    if (obj_uart_tx_rs232phytx_next_value_ce1) begin
        uart_tx <= obj_uart_tx_rs232phytx_next_value1;
    end
    if (tx_data_rs232phytx_next_value_ce2) begin
        tx_data <= tx_data_rs232phytx_next_value2;
    end
    rx_rx_d <= rx_rx;
    {rx_tick, rx_phase} <= 32'd2147483648;
    if (rx_enable) begin
        {rx_tick, rx_phase} <= (rx_phase + 22'd2473901);
    end
    rs232phyrx_state <= rs232phyrx_next_state;
    if (rx_count_rs232phyrx_next_value_ce0) begin
        rx_count <= rx_count_rs232phyrx_next_value0;
    end
    if (rx_data_rs232phyrx_next_value_ce1) begin
        rx_data <= rx_data_rs232phyrx_next_value1;
    end
    if (uart_tx_clear) begin
        uart_tx_pending <= 1'd0;
    end
    uart_tx_trigger_d <= uart_tx_trigger;
    if ((uart_tx_trigger & (~uart_tx_trigger_d))) begin
        uart_tx_pending <= 1'd1;
    end
    if (uart_rx_clear) begin
        uart_rx_pending <= 1'd0;
    end
    uart_rx_trigger_d <= uart_rx_trigger;
    if ((uart_rx_trigger & (~uart_rx_trigger_d))) begin
        uart_rx_pending <= 1'd1;
    end
    if (uart_tx_fifo_syncfifo_re) begin
        uart_tx_fifo_readable <= 1'd1;
    end else begin
        if (uart_tx_fifo_re) begin
            uart_tx_fifo_readable <= 1'd0;
        end
    end
    if (((uart_tx_fifo_syncfifo_we & uart_tx_fifo_syncfifo_writable) & (~uart_tx_fifo_replace))) begin
        uart_tx_fifo_produce <= (uart_tx_fifo_produce + 1'd1);
    end
    if (uart_tx_fifo_do_read) begin
        uart_tx_fifo_consume <= (uart_tx_fifo_consume + 1'd1);
    end
    if (((uart_tx_fifo_syncfifo_we & uart_tx_fifo_syncfifo_writable) & (~uart_tx_fifo_replace))) begin
        if ((~uart_tx_fifo_do_read)) begin
            uart_tx_fifo_level0 <= (uart_tx_fifo_level0 + 1'd1);
        end
    end else begin
        if (uart_tx_fifo_do_read) begin
            uart_tx_fifo_level0 <= (uart_tx_fifo_level0 - 1'd1);
        end
    end
    if (uart_rx_fifo_syncfifo_re) begin
        uart_rx_fifo_readable <= 1'd1;
    end else begin
        if (uart_rx_fifo_re) begin
            uart_rx_fifo_readable <= 1'd0;
        end
    end
    if (((uart_rx_fifo_syncfifo_we & uart_rx_fifo_syncfifo_writable) & (~uart_rx_fifo_replace))) begin
        uart_rx_fifo_produce <= (uart_rx_fifo_produce + 1'd1);
    end
    if (uart_rx_fifo_do_read) begin
        uart_rx_fifo_consume <= (uart_rx_fifo_consume + 1'd1);
    end
    if (((uart_rx_fifo_syncfifo_we & uart_rx_fifo_syncfifo_writable) & (~uart_rx_fifo_replace))) begin
        if ((~uart_rx_fifo_do_read)) begin
            uart_rx_fifo_level0 <= (uart_rx_fifo_level0 + 1'd1);
        end
    end else begin
        if (uart_rx_fifo_do_read) begin
            uart_rx_fifo_level0 <= (uart_rx_fifo_level0 - 1'd1);
        end
    end
    k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= k7ddrphy_dqs_oe_delay_tappeddelayline;
    k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0;
    if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip0_value0 <= (k7ddrphy_bitslip0_value0 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip0_value0 <= 3'd7;
    end
    k7ddrphy_bitslip0_r0 <= {k7ddrphy_dqspattern_o, k7ddrphy_bitslip0_r0[15:8]};
    if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip1_value0 <= (k7ddrphy_bitslip1_value0 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip1_value0 <= 3'd7;
    end
    k7ddrphy_bitslip1_r0 <= {k7ddrphy_dqspattern_o, k7ddrphy_bitslip1_r0[15:8]};
    if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip2_value0 <= (k7ddrphy_bitslip2_value0 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip2_value0 <= 3'd7;
    end
    k7ddrphy_bitslip2_r0 <= {k7ddrphy_dqspattern_o, k7ddrphy_bitslip2_r0[15:8]};
    if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip3_value0 <= (k7ddrphy_bitslip3_value0 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip3_value0 <= 3'd7;
    end
    k7ddrphy_bitslip3_r0 <= {k7ddrphy_dqspattern_o, k7ddrphy_bitslip3_r0[15:8]};
    if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip0_value1 <= (k7ddrphy_bitslip0_value1 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip0_value1 <= 3'd7;
    end
    k7ddrphy_bitslip0_r1 <= {{k7ddrphy_dfi_p3_wrdata_mask[4], k7ddrphy_dfi_p3_wrdata_mask[0], k7ddrphy_dfi_p2_wrdata_mask[4], k7ddrphy_dfi_p2_wrdata_mask[0], k7ddrphy_dfi_p1_wrdata_mask[4], k7ddrphy_dfi_p1_wrdata_mask[0], k7ddrphy_dfi_p0_wrdata_mask[4], k7ddrphy_dfi_p0_wrdata_mask[0]}, k7ddrphy_bitslip0_r1[15:8]};
    if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip1_value1 <= (k7ddrphy_bitslip1_value1 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip1_value1 <= 3'd7;
    end
    k7ddrphy_bitslip1_r1 <= {{k7ddrphy_dfi_p3_wrdata_mask[5], k7ddrphy_dfi_p3_wrdata_mask[1], k7ddrphy_dfi_p2_wrdata_mask[5], k7ddrphy_dfi_p2_wrdata_mask[1], k7ddrphy_dfi_p1_wrdata_mask[5], k7ddrphy_dfi_p1_wrdata_mask[1], k7ddrphy_dfi_p0_wrdata_mask[5], k7ddrphy_dfi_p0_wrdata_mask[1]}, k7ddrphy_bitslip1_r1[15:8]};
    if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip2_value1 <= (k7ddrphy_bitslip2_value1 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip2_value1 <= 3'd7;
    end
    k7ddrphy_bitslip2_r1 <= {{k7ddrphy_dfi_p3_wrdata_mask[6], k7ddrphy_dfi_p3_wrdata_mask[2], k7ddrphy_dfi_p2_wrdata_mask[6], k7ddrphy_dfi_p2_wrdata_mask[2], k7ddrphy_dfi_p1_wrdata_mask[6], k7ddrphy_dfi_p1_wrdata_mask[2], k7ddrphy_dfi_p0_wrdata_mask[6], k7ddrphy_dfi_p0_wrdata_mask[2]}, k7ddrphy_bitslip2_r1[15:8]};
    if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip3_value1 <= (k7ddrphy_bitslip3_value1 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip3_value1 <= 3'd7;
    end
    k7ddrphy_bitslip3_r1 <= {{k7ddrphy_dfi_p3_wrdata_mask[7], k7ddrphy_dfi_p3_wrdata_mask[3], k7ddrphy_dfi_p2_wrdata_mask[7], k7ddrphy_dfi_p2_wrdata_mask[3], k7ddrphy_dfi_p1_wrdata_mask[7], k7ddrphy_dfi_p1_wrdata_mask[3], k7ddrphy_dfi_p0_wrdata_mask[7], k7ddrphy_dfi_p0_wrdata_mask[3]}, k7ddrphy_bitslip3_r1[15:8]};
    k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= k7ddrphy_dq_oe_delay_tappeddelayline;
    k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0;
    if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip0_value2 <= (k7ddrphy_bitslip0_value2 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip0_value2 <= 3'd7;
    end
    k7ddrphy_bitslip0_r2 <= {{k7ddrphy_dfi_p3_wrdata[32], k7ddrphy_dfi_p3_wrdata[0], k7ddrphy_dfi_p2_wrdata[32], k7ddrphy_dfi_p2_wrdata[0], k7ddrphy_dfi_p1_wrdata[32], k7ddrphy_dfi_p1_wrdata[0], k7ddrphy_dfi_p0_wrdata[32], k7ddrphy_dfi_p0_wrdata[0]}, k7ddrphy_bitslip0_r2[15:8]};
    if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip0_value3 <= (k7ddrphy_bitslip0_value3 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip0_value3 <= 3'd7;
    end
    k7ddrphy_bitslip0_r3 <= {k7ddrphy_bitslip03, k7ddrphy_bitslip0_r3[15:8]};
    if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip1_value2 <= (k7ddrphy_bitslip1_value2 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip1_value2 <= 3'd7;
    end
    k7ddrphy_bitslip1_r2 <= {{k7ddrphy_dfi_p3_wrdata[33], k7ddrphy_dfi_p3_wrdata[1], k7ddrphy_dfi_p2_wrdata[33], k7ddrphy_dfi_p2_wrdata[1], k7ddrphy_dfi_p1_wrdata[33], k7ddrphy_dfi_p1_wrdata[1], k7ddrphy_dfi_p0_wrdata[33], k7ddrphy_dfi_p0_wrdata[1]}, k7ddrphy_bitslip1_r2[15:8]};
    if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip1_value3 <= (k7ddrphy_bitslip1_value3 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip1_value3 <= 3'd7;
    end
    k7ddrphy_bitslip1_r3 <= {k7ddrphy_bitslip13, k7ddrphy_bitslip1_r3[15:8]};
    if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip2_value2 <= (k7ddrphy_bitslip2_value2 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip2_value2 <= 3'd7;
    end
    k7ddrphy_bitslip2_r2 <= {{k7ddrphy_dfi_p3_wrdata[34], k7ddrphy_dfi_p3_wrdata[2], k7ddrphy_dfi_p2_wrdata[34], k7ddrphy_dfi_p2_wrdata[2], k7ddrphy_dfi_p1_wrdata[34], k7ddrphy_dfi_p1_wrdata[2], k7ddrphy_dfi_p0_wrdata[34], k7ddrphy_dfi_p0_wrdata[2]}, k7ddrphy_bitslip2_r2[15:8]};
    if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip2_value3 <= (k7ddrphy_bitslip2_value3 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip2_value3 <= 3'd7;
    end
    k7ddrphy_bitslip2_r3 <= {k7ddrphy_bitslip23, k7ddrphy_bitslip2_r3[15:8]};
    if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip3_value2 <= (k7ddrphy_bitslip3_value2 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip3_value2 <= 3'd7;
    end
    k7ddrphy_bitslip3_r2 <= {{k7ddrphy_dfi_p3_wrdata[35], k7ddrphy_dfi_p3_wrdata[3], k7ddrphy_dfi_p2_wrdata[35], k7ddrphy_dfi_p2_wrdata[3], k7ddrphy_dfi_p1_wrdata[35], k7ddrphy_dfi_p1_wrdata[3], k7ddrphy_dfi_p0_wrdata[35], k7ddrphy_dfi_p0_wrdata[3]}, k7ddrphy_bitslip3_r2[15:8]};
    if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip3_value3 <= (k7ddrphy_bitslip3_value3 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip3_value3 <= 3'd7;
    end
    k7ddrphy_bitslip3_r3 <= {k7ddrphy_bitslip33, k7ddrphy_bitslip3_r3[15:8]};
    if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip4_value0 <= (k7ddrphy_bitslip4_value0 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip4_value0 <= 3'd7;
    end
    k7ddrphy_bitslip4_r0 <= {{k7ddrphy_dfi_p3_wrdata[36], k7ddrphy_dfi_p3_wrdata[4], k7ddrphy_dfi_p2_wrdata[36], k7ddrphy_dfi_p2_wrdata[4], k7ddrphy_dfi_p1_wrdata[36], k7ddrphy_dfi_p1_wrdata[4], k7ddrphy_dfi_p0_wrdata[36], k7ddrphy_dfi_p0_wrdata[4]}, k7ddrphy_bitslip4_r0[15:8]};
    if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip4_value1 <= (k7ddrphy_bitslip4_value1 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip4_value1 <= 3'd7;
    end
    k7ddrphy_bitslip4_r1 <= {k7ddrphy_bitslip41, k7ddrphy_bitslip4_r1[15:8]};
    if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip5_value0 <= (k7ddrphy_bitslip5_value0 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip5_value0 <= 3'd7;
    end
    k7ddrphy_bitslip5_r0 <= {{k7ddrphy_dfi_p3_wrdata[37], k7ddrphy_dfi_p3_wrdata[5], k7ddrphy_dfi_p2_wrdata[37], k7ddrphy_dfi_p2_wrdata[5], k7ddrphy_dfi_p1_wrdata[37], k7ddrphy_dfi_p1_wrdata[5], k7ddrphy_dfi_p0_wrdata[37], k7ddrphy_dfi_p0_wrdata[5]}, k7ddrphy_bitslip5_r0[15:8]};
    if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip5_value1 <= (k7ddrphy_bitslip5_value1 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip5_value1 <= 3'd7;
    end
    k7ddrphy_bitslip5_r1 <= {k7ddrphy_bitslip51, k7ddrphy_bitslip5_r1[15:8]};
    if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip6_value0 <= (k7ddrphy_bitslip6_value0 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip6_value0 <= 3'd7;
    end
    k7ddrphy_bitslip6_r0 <= {{k7ddrphy_dfi_p3_wrdata[38], k7ddrphy_dfi_p3_wrdata[6], k7ddrphy_dfi_p2_wrdata[38], k7ddrphy_dfi_p2_wrdata[6], k7ddrphy_dfi_p1_wrdata[38], k7ddrphy_dfi_p1_wrdata[6], k7ddrphy_dfi_p0_wrdata[38], k7ddrphy_dfi_p0_wrdata[6]}, k7ddrphy_bitslip6_r0[15:8]};
    if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip6_value1 <= (k7ddrphy_bitslip6_value1 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip6_value1 <= 3'd7;
    end
    k7ddrphy_bitslip6_r1 <= {k7ddrphy_bitslip61, k7ddrphy_bitslip6_r1[15:8]};
    if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip7_value0 <= (k7ddrphy_bitslip7_value0 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip7_value0 <= 3'd7;
    end
    k7ddrphy_bitslip7_r0 <= {{k7ddrphy_dfi_p3_wrdata[39], k7ddrphy_dfi_p3_wrdata[7], k7ddrphy_dfi_p2_wrdata[39], k7ddrphy_dfi_p2_wrdata[7], k7ddrphy_dfi_p1_wrdata[39], k7ddrphy_dfi_p1_wrdata[7], k7ddrphy_dfi_p0_wrdata[39], k7ddrphy_dfi_p0_wrdata[7]}, k7ddrphy_bitslip7_r0[15:8]};
    if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip7_value1 <= (k7ddrphy_bitslip7_value1 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip7_value1 <= 3'd7;
    end
    k7ddrphy_bitslip7_r1 <= {k7ddrphy_bitslip71, k7ddrphy_bitslip7_r1[15:8]};
    if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip8_value0 <= (k7ddrphy_bitslip8_value0 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip8_value0 <= 3'd7;
    end
    k7ddrphy_bitslip8_r0 <= {{k7ddrphy_dfi_p3_wrdata[40], k7ddrphy_dfi_p3_wrdata[8], k7ddrphy_dfi_p2_wrdata[40], k7ddrphy_dfi_p2_wrdata[8], k7ddrphy_dfi_p1_wrdata[40], k7ddrphy_dfi_p1_wrdata[8], k7ddrphy_dfi_p0_wrdata[40], k7ddrphy_dfi_p0_wrdata[8]}, k7ddrphy_bitslip8_r0[15:8]};
    if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip8_value1 <= (k7ddrphy_bitslip8_value1 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip8_value1 <= 3'd7;
    end
    k7ddrphy_bitslip8_r1 <= {k7ddrphy_bitslip81, k7ddrphy_bitslip8_r1[15:8]};
    if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip9_value0 <= (k7ddrphy_bitslip9_value0 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip9_value0 <= 3'd7;
    end
    k7ddrphy_bitslip9_r0 <= {{k7ddrphy_dfi_p3_wrdata[41], k7ddrphy_dfi_p3_wrdata[9], k7ddrphy_dfi_p2_wrdata[41], k7ddrphy_dfi_p2_wrdata[9], k7ddrphy_dfi_p1_wrdata[41], k7ddrphy_dfi_p1_wrdata[9], k7ddrphy_dfi_p0_wrdata[41], k7ddrphy_dfi_p0_wrdata[9]}, k7ddrphy_bitslip9_r0[15:8]};
    if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip9_value1 <= (k7ddrphy_bitslip9_value1 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip9_value1 <= 3'd7;
    end
    k7ddrphy_bitslip9_r1 <= {k7ddrphy_bitslip91, k7ddrphy_bitslip9_r1[15:8]};
    if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip10_value0 <= (k7ddrphy_bitslip10_value0 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip10_value0 <= 3'd7;
    end
    k7ddrphy_bitslip10_r0 <= {{k7ddrphy_dfi_p3_wrdata[42], k7ddrphy_dfi_p3_wrdata[10], k7ddrphy_dfi_p2_wrdata[42], k7ddrphy_dfi_p2_wrdata[10], k7ddrphy_dfi_p1_wrdata[42], k7ddrphy_dfi_p1_wrdata[10], k7ddrphy_dfi_p0_wrdata[42], k7ddrphy_dfi_p0_wrdata[10]}, k7ddrphy_bitslip10_r0[15:8]};
    if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip10_value1 <= (k7ddrphy_bitslip10_value1 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip10_value1 <= 3'd7;
    end
    k7ddrphy_bitslip10_r1 <= {k7ddrphy_bitslip101, k7ddrphy_bitslip10_r1[15:8]};
    if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip11_value0 <= (k7ddrphy_bitslip11_value0 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip11_value0 <= 3'd7;
    end
    k7ddrphy_bitslip11_r0 <= {{k7ddrphy_dfi_p3_wrdata[43], k7ddrphy_dfi_p3_wrdata[11], k7ddrphy_dfi_p2_wrdata[43], k7ddrphy_dfi_p2_wrdata[11], k7ddrphy_dfi_p1_wrdata[43], k7ddrphy_dfi_p1_wrdata[11], k7ddrphy_dfi_p0_wrdata[43], k7ddrphy_dfi_p0_wrdata[11]}, k7ddrphy_bitslip11_r0[15:8]};
    if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip11_value1 <= (k7ddrphy_bitslip11_value1 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip11_value1 <= 3'd7;
    end
    k7ddrphy_bitslip11_r1 <= {k7ddrphy_bitslip111, k7ddrphy_bitslip11_r1[15:8]};
    if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip12_value0 <= (k7ddrphy_bitslip12_value0 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip12_value0 <= 3'd7;
    end
    k7ddrphy_bitslip12_r0 <= {{k7ddrphy_dfi_p3_wrdata[44], k7ddrphy_dfi_p3_wrdata[12], k7ddrphy_dfi_p2_wrdata[44], k7ddrphy_dfi_p2_wrdata[12], k7ddrphy_dfi_p1_wrdata[44], k7ddrphy_dfi_p1_wrdata[12], k7ddrphy_dfi_p0_wrdata[44], k7ddrphy_dfi_p0_wrdata[12]}, k7ddrphy_bitslip12_r0[15:8]};
    if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip12_value1 <= (k7ddrphy_bitslip12_value1 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip12_value1 <= 3'd7;
    end
    k7ddrphy_bitslip12_r1 <= {k7ddrphy_bitslip121, k7ddrphy_bitslip12_r1[15:8]};
    if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip13_value0 <= (k7ddrphy_bitslip13_value0 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip13_value0 <= 3'd7;
    end
    k7ddrphy_bitslip13_r0 <= {{k7ddrphy_dfi_p3_wrdata[45], k7ddrphy_dfi_p3_wrdata[13], k7ddrphy_dfi_p2_wrdata[45], k7ddrphy_dfi_p2_wrdata[13], k7ddrphy_dfi_p1_wrdata[45], k7ddrphy_dfi_p1_wrdata[13], k7ddrphy_dfi_p0_wrdata[45], k7ddrphy_dfi_p0_wrdata[13]}, k7ddrphy_bitslip13_r0[15:8]};
    if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip13_value1 <= (k7ddrphy_bitslip13_value1 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip13_value1 <= 3'd7;
    end
    k7ddrphy_bitslip13_r1 <= {k7ddrphy_bitslip131, k7ddrphy_bitslip13_r1[15:8]};
    if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip14_value0 <= (k7ddrphy_bitslip14_value0 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip14_value0 <= 3'd7;
    end
    k7ddrphy_bitslip14_r0 <= {{k7ddrphy_dfi_p3_wrdata[46], k7ddrphy_dfi_p3_wrdata[14], k7ddrphy_dfi_p2_wrdata[46], k7ddrphy_dfi_p2_wrdata[14], k7ddrphy_dfi_p1_wrdata[46], k7ddrphy_dfi_p1_wrdata[14], k7ddrphy_dfi_p0_wrdata[46], k7ddrphy_dfi_p0_wrdata[14]}, k7ddrphy_bitslip14_r0[15:8]};
    if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip14_value1 <= (k7ddrphy_bitslip14_value1 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip14_value1 <= 3'd7;
    end
    k7ddrphy_bitslip14_r1 <= {k7ddrphy_bitslip141, k7ddrphy_bitslip14_r1[15:8]};
    if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip15_value0 <= (k7ddrphy_bitslip15_value0 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip15_value0 <= 3'd7;
    end
    k7ddrphy_bitslip15_r0 <= {{k7ddrphy_dfi_p3_wrdata[47], k7ddrphy_dfi_p3_wrdata[15], k7ddrphy_dfi_p2_wrdata[47], k7ddrphy_dfi_p2_wrdata[15], k7ddrphy_dfi_p1_wrdata[47], k7ddrphy_dfi_p1_wrdata[15], k7ddrphy_dfi_p0_wrdata[47], k7ddrphy_dfi_p0_wrdata[15]}, k7ddrphy_bitslip15_r0[15:8]};
    if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip15_value1 <= (k7ddrphy_bitslip15_value1 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip15_value1 <= 3'd7;
    end
    k7ddrphy_bitslip15_r1 <= {k7ddrphy_bitslip151, k7ddrphy_bitslip15_r1[15:8]};
    if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip16_value0 <= (k7ddrphy_bitslip16_value0 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip16_value0 <= 3'd7;
    end
    k7ddrphy_bitslip16_r0 <= {{k7ddrphy_dfi_p3_wrdata[48], k7ddrphy_dfi_p3_wrdata[16], k7ddrphy_dfi_p2_wrdata[48], k7ddrphy_dfi_p2_wrdata[16], k7ddrphy_dfi_p1_wrdata[48], k7ddrphy_dfi_p1_wrdata[16], k7ddrphy_dfi_p0_wrdata[48], k7ddrphy_dfi_p0_wrdata[16]}, k7ddrphy_bitslip16_r0[15:8]};
    if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip16_value1 <= (k7ddrphy_bitslip16_value1 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip16_value1 <= 3'd7;
    end
    k7ddrphy_bitslip16_r1 <= {k7ddrphy_bitslip161, k7ddrphy_bitslip16_r1[15:8]};
    if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip17_value0 <= (k7ddrphy_bitslip17_value0 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip17_value0 <= 3'd7;
    end
    k7ddrphy_bitslip17_r0 <= {{k7ddrphy_dfi_p3_wrdata[49], k7ddrphy_dfi_p3_wrdata[17], k7ddrphy_dfi_p2_wrdata[49], k7ddrphy_dfi_p2_wrdata[17], k7ddrphy_dfi_p1_wrdata[49], k7ddrphy_dfi_p1_wrdata[17], k7ddrphy_dfi_p0_wrdata[49], k7ddrphy_dfi_p0_wrdata[17]}, k7ddrphy_bitslip17_r0[15:8]};
    if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip17_value1 <= (k7ddrphy_bitslip17_value1 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip17_value1 <= 3'd7;
    end
    k7ddrphy_bitslip17_r1 <= {k7ddrphy_bitslip171, k7ddrphy_bitslip17_r1[15:8]};
    if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip18_value0 <= (k7ddrphy_bitslip18_value0 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip18_value0 <= 3'd7;
    end
    k7ddrphy_bitslip18_r0 <= {{k7ddrphy_dfi_p3_wrdata[50], k7ddrphy_dfi_p3_wrdata[18], k7ddrphy_dfi_p2_wrdata[50], k7ddrphy_dfi_p2_wrdata[18], k7ddrphy_dfi_p1_wrdata[50], k7ddrphy_dfi_p1_wrdata[18], k7ddrphy_dfi_p0_wrdata[50], k7ddrphy_dfi_p0_wrdata[18]}, k7ddrphy_bitslip18_r0[15:8]};
    if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip18_value1 <= (k7ddrphy_bitslip18_value1 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip18_value1 <= 3'd7;
    end
    k7ddrphy_bitslip18_r1 <= {k7ddrphy_bitslip181, k7ddrphy_bitslip18_r1[15:8]};
    if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip19_value0 <= (k7ddrphy_bitslip19_value0 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip19_value0 <= 3'd7;
    end
    k7ddrphy_bitslip19_r0 <= {{k7ddrphy_dfi_p3_wrdata[51], k7ddrphy_dfi_p3_wrdata[19], k7ddrphy_dfi_p2_wrdata[51], k7ddrphy_dfi_p2_wrdata[19], k7ddrphy_dfi_p1_wrdata[51], k7ddrphy_dfi_p1_wrdata[19], k7ddrphy_dfi_p0_wrdata[51], k7ddrphy_dfi_p0_wrdata[19]}, k7ddrphy_bitslip19_r0[15:8]};
    if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip19_value1 <= (k7ddrphy_bitslip19_value1 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip19_value1 <= 3'd7;
    end
    k7ddrphy_bitslip19_r1 <= {k7ddrphy_bitslip191, k7ddrphy_bitslip19_r1[15:8]};
    if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip20_value0 <= (k7ddrphy_bitslip20_value0 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip20_value0 <= 3'd7;
    end
    k7ddrphy_bitslip20_r0 <= {{k7ddrphy_dfi_p3_wrdata[52], k7ddrphy_dfi_p3_wrdata[20], k7ddrphy_dfi_p2_wrdata[52], k7ddrphy_dfi_p2_wrdata[20], k7ddrphy_dfi_p1_wrdata[52], k7ddrphy_dfi_p1_wrdata[20], k7ddrphy_dfi_p0_wrdata[52], k7ddrphy_dfi_p0_wrdata[20]}, k7ddrphy_bitslip20_r0[15:8]};
    if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip20_value1 <= (k7ddrphy_bitslip20_value1 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip20_value1 <= 3'd7;
    end
    k7ddrphy_bitslip20_r1 <= {k7ddrphy_bitslip201, k7ddrphy_bitslip20_r1[15:8]};
    if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip21_value0 <= (k7ddrphy_bitslip21_value0 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip21_value0 <= 3'd7;
    end
    k7ddrphy_bitslip21_r0 <= {{k7ddrphy_dfi_p3_wrdata[53], k7ddrphy_dfi_p3_wrdata[21], k7ddrphy_dfi_p2_wrdata[53], k7ddrphy_dfi_p2_wrdata[21], k7ddrphy_dfi_p1_wrdata[53], k7ddrphy_dfi_p1_wrdata[21], k7ddrphy_dfi_p0_wrdata[53], k7ddrphy_dfi_p0_wrdata[21]}, k7ddrphy_bitslip21_r0[15:8]};
    if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip21_value1 <= (k7ddrphy_bitslip21_value1 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip21_value1 <= 3'd7;
    end
    k7ddrphy_bitslip21_r1 <= {k7ddrphy_bitslip211, k7ddrphy_bitslip21_r1[15:8]};
    if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip22_value0 <= (k7ddrphy_bitslip22_value0 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip22_value0 <= 3'd7;
    end
    k7ddrphy_bitslip22_r0 <= {{k7ddrphy_dfi_p3_wrdata[54], k7ddrphy_dfi_p3_wrdata[22], k7ddrphy_dfi_p2_wrdata[54], k7ddrphy_dfi_p2_wrdata[22], k7ddrphy_dfi_p1_wrdata[54], k7ddrphy_dfi_p1_wrdata[22], k7ddrphy_dfi_p0_wrdata[54], k7ddrphy_dfi_p0_wrdata[22]}, k7ddrphy_bitslip22_r0[15:8]};
    if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip22_value1 <= (k7ddrphy_bitslip22_value1 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip22_value1 <= 3'd7;
    end
    k7ddrphy_bitslip22_r1 <= {k7ddrphy_bitslip221, k7ddrphy_bitslip22_r1[15:8]};
    if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip23_value0 <= (k7ddrphy_bitslip23_value0 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip23_value0 <= 3'd7;
    end
    k7ddrphy_bitslip23_r0 <= {{k7ddrphy_dfi_p3_wrdata[55], k7ddrphy_dfi_p3_wrdata[23], k7ddrphy_dfi_p2_wrdata[55], k7ddrphy_dfi_p2_wrdata[23], k7ddrphy_dfi_p1_wrdata[55], k7ddrphy_dfi_p1_wrdata[23], k7ddrphy_dfi_p0_wrdata[55], k7ddrphy_dfi_p0_wrdata[23]}, k7ddrphy_bitslip23_r0[15:8]};
    if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip23_value1 <= (k7ddrphy_bitslip23_value1 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip23_value1 <= 3'd7;
    end
    k7ddrphy_bitslip23_r1 <= {k7ddrphy_bitslip231, k7ddrphy_bitslip23_r1[15:8]};
    if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip24_value0 <= (k7ddrphy_bitslip24_value0 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip24_value0 <= 3'd7;
    end
    k7ddrphy_bitslip24_r0 <= {{k7ddrphy_dfi_p3_wrdata[56], k7ddrphy_dfi_p3_wrdata[24], k7ddrphy_dfi_p2_wrdata[56], k7ddrphy_dfi_p2_wrdata[24], k7ddrphy_dfi_p1_wrdata[56], k7ddrphy_dfi_p1_wrdata[24], k7ddrphy_dfi_p0_wrdata[56], k7ddrphy_dfi_p0_wrdata[24]}, k7ddrphy_bitslip24_r0[15:8]};
    if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip24_value1 <= (k7ddrphy_bitslip24_value1 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip24_value1 <= 3'd7;
    end
    k7ddrphy_bitslip24_r1 <= {k7ddrphy_bitslip241, k7ddrphy_bitslip24_r1[15:8]};
    if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip25_value0 <= (k7ddrphy_bitslip25_value0 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip25_value0 <= 3'd7;
    end
    k7ddrphy_bitslip25_r0 <= {{k7ddrphy_dfi_p3_wrdata[57], k7ddrphy_dfi_p3_wrdata[25], k7ddrphy_dfi_p2_wrdata[57], k7ddrphy_dfi_p2_wrdata[25], k7ddrphy_dfi_p1_wrdata[57], k7ddrphy_dfi_p1_wrdata[25], k7ddrphy_dfi_p0_wrdata[57], k7ddrphy_dfi_p0_wrdata[25]}, k7ddrphy_bitslip25_r0[15:8]};
    if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip25_value1 <= (k7ddrphy_bitslip25_value1 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip25_value1 <= 3'd7;
    end
    k7ddrphy_bitslip25_r1 <= {k7ddrphy_bitslip251, k7ddrphy_bitslip25_r1[15:8]};
    if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip26_value0 <= (k7ddrphy_bitslip26_value0 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip26_value0 <= 3'd7;
    end
    k7ddrphy_bitslip26_r0 <= {{k7ddrphy_dfi_p3_wrdata[58], k7ddrphy_dfi_p3_wrdata[26], k7ddrphy_dfi_p2_wrdata[58], k7ddrphy_dfi_p2_wrdata[26], k7ddrphy_dfi_p1_wrdata[58], k7ddrphy_dfi_p1_wrdata[26], k7ddrphy_dfi_p0_wrdata[58], k7ddrphy_dfi_p0_wrdata[26]}, k7ddrphy_bitslip26_r0[15:8]};
    if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip26_value1 <= (k7ddrphy_bitslip26_value1 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip26_value1 <= 3'd7;
    end
    k7ddrphy_bitslip26_r1 <= {k7ddrphy_bitslip261, k7ddrphy_bitslip26_r1[15:8]};
    if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip27_value0 <= (k7ddrphy_bitslip27_value0 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip27_value0 <= 3'd7;
    end
    k7ddrphy_bitslip27_r0 <= {{k7ddrphy_dfi_p3_wrdata[59], k7ddrphy_dfi_p3_wrdata[27], k7ddrphy_dfi_p2_wrdata[59], k7ddrphy_dfi_p2_wrdata[27], k7ddrphy_dfi_p1_wrdata[59], k7ddrphy_dfi_p1_wrdata[27], k7ddrphy_dfi_p0_wrdata[59], k7ddrphy_dfi_p0_wrdata[27]}, k7ddrphy_bitslip27_r0[15:8]};
    if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip27_value1 <= (k7ddrphy_bitslip27_value1 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip27_value1 <= 3'd7;
    end
    k7ddrphy_bitslip27_r1 <= {k7ddrphy_bitslip271, k7ddrphy_bitslip27_r1[15:8]};
    if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip28_value0 <= (k7ddrphy_bitslip28_value0 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip28_value0 <= 3'd7;
    end
    k7ddrphy_bitslip28_r0 <= {{k7ddrphy_dfi_p3_wrdata[60], k7ddrphy_dfi_p3_wrdata[28], k7ddrphy_dfi_p2_wrdata[60], k7ddrphy_dfi_p2_wrdata[28], k7ddrphy_dfi_p1_wrdata[60], k7ddrphy_dfi_p1_wrdata[28], k7ddrphy_dfi_p0_wrdata[60], k7ddrphy_dfi_p0_wrdata[28]}, k7ddrphy_bitslip28_r0[15:8]};
    if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip28_value1 <= (k7ddrphy_bitslip28_value1 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip28_value1 <= 3'd7;
    end
    k7ddrphy_bitslip28_r1 <= {k7ddrphy_bitslip281, k7ddrphy_bitslip28_r1[15:8]};
    if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip29_value0 <= (k7ddrphy_bitslip29_value0 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip29_value0 <= 3'd7;
    end
    k7ddrphy_bitslip29_r0 <= {{k7ddrphy_dfi_p3_wrdata[61], k7ddrphy_dfi_p3_wrdata[29], k7ddrphy_dfi_p2_wrdata[61], k7ddrphy_dfi_p2_wrdata[29], k7ddrphy_dfi_p1_wrdata[61], k7ddrphy_dfi_p1_wrdata[29], k7ddrphy_dfi_p0_wrdata[61], k7ddrphy_dfi_p0_wrdata[29]}, k7ddrphy_bitslip29_r0[15:8]};
    if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip29_value1 <= (k7ddrphy_bitslip29_value1 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip29_value1 <= 3'd7;
    end
    k7ddrphy_bitslip29_r1 <= {k7ddrphy_bitslip291, k7ddrphy_bitslip29_r1[15:8]};
    if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip30_value0 <= (k7ddrphy_bitslip30_value0 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip30_value0 <= 3'd7;
    end
    k7ddrphy_bitslip30_r0 <= {{k7ddrphy_dfi_p3_wrdata[62], k7ddrphy_dfi_p3_wrdata[30], k7ddrphy_dfi_p2_wrdata[62], k7ddrphy_dfi_p2_wrdata[30], k7ddrphy_dfi_p1_wrdata[62], k7ddrphy_dfi_p1_wrdata[30], k7ddrphy_dfi_p0_wrdata[62], k7ddrphy_dfi_p0_wrdata[30]}, k7ddrphy_bitslip30_r0[15:8]};
    if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip30_value1 <= (k7ddrphy_bitslip30_value1 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip30_value1 <= 3'd7;
    end
    k7ddrphy_bitslip30_r1 <= {k7ddrphy_bitslip301, k7ddrphy_bitslip30_r1[15:8]};
    if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip31_value0 <= (k7ddrphy_bitslip31_value0 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip31_value0 <= 3'd7;
    end
    k7ddrphy_bitslip31_r0 <= {{k7ddrphy_dfi_p3_wrdata[63], k7ddrphy_dfi_p3_wrdata[31], k7ddrphy_dfi_p2_wrdata[63], k7ddrphy_dfi_p2_wrdata[31], k7ddrphy_dfi_p1_wrdata[63], k7ddrphy_dfi_p1_wrdata[31], k7ddrphy_dfi_p0_wrdata[63], k7ddrphy_dfi_p0_wrdata[31]}, k7ddrphy_bitslip31_r0[15:8]};
    if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin
        k7ddrphy_bitslip31_value1 <= (k7ddrphy_bitslip31_value1 + 1'd1);
    end
    if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
        k7ddrphy_bitslip31_value1 <= 3'd7;
    end
    k7ddrphy_bitslip31_r1 <= {k7ddrphy_bitslip311, k7ddrphy_bitslip31_r1[15:8]};
    k7ddrphy_rddata_en_tappeddelayline0 <= (((k7ddrphy_dfi_p0_rddata_en | k7ddrphy_dfi_p1_rddata_en) | k7ddrphy_dfi_p2_rddata_en) | k7ddrphy_dfi_p3_rddata_en);
    k7ddrphy_rddata_en_tappeddelayline1 <= k7ddrphy_rddata_en_tappeddelayline0;
    k7ddrphy_rddata_en_tappeddelayline2 <= k7ddrphy_rddata_en_tappeddelayline1;
    k7ddrphy_rddata_en_tappeddelayline3 <= k7ddrphy_rddata_en_tappeddelayline2;
    k7ddrphy_rddata_en_tappeddelayline4 <= k7ddrphy_rddata_en_tappeddelayline3;
    k7ddrphy_rddata_en_tappeddelayline5 <= k7ddrphy_rddata_en_tappeddelayline4;
    k7ddrphy_rddata_en_tappeddelayline6 <= k7ddrphy_rddata_en_tappeddelayline5;
    k7ddrphy_rddata_en_tappeddelayline7 <= k7ddrphy_rddata_en_tappeddelayline6;
    k7ddrphy_rddata_en_tappeddelayline8 <= k7ddrphy_rddata_en_tappeddelayline7;
    k7ddrphy_wrdata_en_tappeddelayline0 <= (((k7ddrphy_dfi_p0_wrdata_en | k7ddrphy_dfi_p1_wrdata_en) | k7ddrphy_dfi_p2_wrdata_en) | k7ddrphy_dfi_p3_wrdata_en);
    k7ddrphy_wrdata_en_tappeddelayline1 <= k7ddrphy_wrdata_en_tappeddelayline0;
    k7ddrphy_wrdata_en_tappeddelayline2 <= k7ddrphy_wrdata_en_tappeddelayline1;
    if (litedramcore_sdram_csr_dfi_p0_rddata_valid) begin
        litedramcore_sdram_phaseinjector0_rddata_status <= litedramcore_sdram_csr_dfi_p0_rddata;
    end
    if (litedramcore_sdram_csr_dfi_p1_rddata_valid) begin
        litedramcore_sdram_phaseinjector1_rddata_status <= litedramcore_sdram_csr_dfi_p1_rddata;
    end
    if (litedramcore_sdram_csr_dfi_p2_rddata_valid) begin
        litedramcore_sdram_phaseinjector2_rddata_status <= litedramcore_sdram_csr_dfi_p2_rddata;
    end
    if (litedramcore_sdram_csr_dfi_p3_rddata_valid) begin
        litedramcore_sdram_phaseinjector3_rddata_status <= litedramcore_sdram_csr_dfi_p3_rddata;
    end
    if ((litedramcore_sdram_timer_wait & (~litedramcore_sdram_timer_done0))) begin
        litedramcore_sdram_timer_count1 <= (litedramcore_sdram_timer_count1 - 1'd1);
    end else begin
        litedramcore_sdram_timer_count1 <= 11'd1562;
    end
    litedramcore_sdram_postponer_req_o <= 1'd0;
    if (litedramcore_sdram_postponer_req_i) begin
        litedramcore_sdram_postponer_count <= (litedramcore_sdram_postponer_count - 1'd1);
        if ((litedramcore_sdram_postponer_count == 1'd0)) begin
            litedramcore_sdram_postponer_count <= 1'd0;
            litedramcore_sdram_postponer_req_o <= 1'd1;
        end
    end
    if (litedramcore_sdram_sequencer_start0) begin
        litedramcore_sdram_sequencer_count <= 1'd0;
    end else begin
        if (litedramcore_sdram_sequencer_done1) begin
            if ((litedramcore_sdram_sequencer_count != 1'd0)) begin
                litedramcore_sdram_sequencer_count <= (litedramcore_sdram_sequencer_count - 1'd1);
            end
        end
    end
    litedramcore_sdram_cmd_payload_a <= 1'd0;
    litedramcore_sdram_cmd_payload_ba <= 1'd0;
    litedramcore_sdram_cmd_payload_cas <= 1'd0;
    litedramcore_sdram_cmd_payload_ras <= 1'd0;
    litedramcore_sdram_cmd_payload_we <= 1'd0;
    litedramcore_sdram_sequencer_done1 <= 1'd0;
    if ((litedramcore_sdram_sequencer_start1 & (litedramcore_sdram_sequencer_trigger == 1'd0))) begin
        litedramcore_sdram_cmd_payload_a <= 11'd1024;
        litedramcore_sdram_cmd_payload_ba <= 1'd0;
        litedramcore_sdram_cmd_payload_cas <= 1'd0;
        litedramcore_sdram_cmd_payload_ras <= 1'd1;
        litedramcore_sdram_cmd_payload_we <= 1'd1;
    end
    if ((litedramcore_sdram_sequencer_trigger == 3'd4)) begin
        litedramcore_sdram_cmd_payload_a <= 11'd1024;
        litedramcore_sdram_cmd_payload_ba <= 1'd0;
        litedramcore_sdram_cmd_payload_cas <= 1'd1;
        litedramcore_sdram_cmd_payload_ras <= 1'd1;
        litedramcore_sdram_cmd_payload_we <= 1'd0;
    end
    if ((litedramcore_sdram_sequencer_trigger == 6'd56)) begin
        litedramcore_sdram_cmd_payload_a <= 1'd0;
        litedramcore_sdram_cmd_payload_ba <= 1'd0;
        litedramcore_sdram_cmd_payload_cas <= 1'd0;
        litedramcore_sdram_cmd_payload_ras <= 1'd0;
        litedramcore_sdram_cmd_payload_we <= 1'd0;
        litedramcore_sdram_sequencer_done1 <= 1'd1;
    end
    if ((litedramcore_sdram_sequencer_trigger == 6'd56)) begin
        litedramcore_sdram_sequencer_trigger <= 1'd0;
    end else begin
        if ((litedramcore_sdram_sequencer_trigger != 1'd0)) begin
            litedramcore_sdram_sequencer_trigger <= (litedramcore_sdram_sequencer_trigger + 1'd1);
        end else begin
            if (litedramcore_sdram_sequencer_start1) begin
                litedramcore_sdram_sequencer_trigger <= 1'd1;
            end
        end
    end
    if ((litedramcore_sdram_zqcs_timer_wait & (~litedramcore_sdram_zqcs_timer_done0))) begin
        litedramcore_sdram_zqcs_timer_count1 <= (litedramcore_sdram_zqcs_timer_count1 - 1'd1);
    end else begin
        litedramcore_sdram_zqcs_timer_count1 <= 28'd199999999;
    end
    litedramcore_sdram_zqcs_executer_done <= 1'd0;
    if ((litedramcore_sdram_zqcs_executer_start & (litedramcore_sdram_zqcs_executer_trigger == 1'd0))) begin
        litedramcore_sdram_cmd_payload_a <= 11'd1024;
        litedramcore_sdram_cmd_payload_ba <= 1'd0;
        litedramcore_sdram_cmd_payload_cas <= 1'd0;
        litedramcore_sdram_cmd_payload_ras <= 1'd1;
        litedramcore_sdram_cmd_payload_we <= 1'd1;
    end
    if ((litedramcore_sdram_zqcs_executer_trigger == 3'd4)) begin
        litedramcore_sdram_cmd_payload_a <= 1'd0;
        litedramcore_sdram_cmd_payload_ba <= 1'd0;
        litedramcore_sdram_cmd_payload_cas <= 1'd0;
        litedramcore_sdram_cmd_payload_ras <= 1'd0;
        litedramcore_sdram_cmd_payload_we <= 1'd1;
    end
    if ((litedramcore_sdram_zqcs_executer_trigger == 5'd21)) begin
        litedramcore_sdram_cmd_payload_a <= 1'd0;
        litedramcore_sdram_cmd_payload_ba <= 1'd0;
        litedramcore_sdram_cmd_payload_cas <= 1'd0;
        litedramcore_sdram_cmd_payload_ras <= 1'd0;
        litedramcore_sdram_cmd_payload_we <= 1'd0;
        litedramcore_sdram_zqcs_executer_done <= 1'd1;
    end
    if ((litedramcore_sdram_zqcs_executer_trigger == 5'd21)) begin
        litedramcore_sdram_zqcs_executer_trigger <= 1'd0;
    end else begin
        if ((litedramcore_sdram_zqcs_executer_trigger != 1'd0)) begin
            litedramcore_sdram_zqcs_executer_trigger <= (litedramcore_sdram_zqcs_executer_trigger + 1'd1);
        end else begin
            if (litedramcore_sdram_zqcs_executer_start) begin
                litedramcore_sdram_zqcs_executer_trigger <= 1'd1;
            end
        end
    end
    litedramcore_refresher_state <= litedramcore_refresher_next_state;
    if (litedramcore_sdram_bankmachine0_row_close) begin
        litedramcore_sdram_bankmachine0_row_opened <= 1'd0;
    end else begin
        if (litedramcore_sdram_bankmachine0_row_open) begin
            litedramcore_sdram_bankmachine0_row_opened <= 1'd1;
            litedramcore_sdram_bankmachine0_row <= litedramcore_sdram_bankmachine0_source_source_payload_addr[21:7];
        end
    end
    if (((litedramcore_sdram_bankmachine0_syncfifo0_we & litedramcore_sdram_bankmachine0_syncfifo0_writable) & (~litedramcore_sdram_bankmachine0_replace))) begin
        litedramcore_sdram_bankmachine0_produce <= (litedramcore_sdram_bankmachine0_produce + 1'd1);
    end
    if (litedramcore_sdram_bankmachine0_do_read) begin
        litedramcore_sdram_bankmachine0_consume <= (litedramcore_sdram_bankmachine0_consume + 1'd1);
    end
    if (((litedramcore_sdram_bankmachine0_syncfifo0_we & litedramcore_sdram_bankmachine0_syncfifo0_writable) & (~litedramcore_sdram_bankmachine0_replace))) begin
        if ((~litedramcore_sdram_bankmachine0_do_read)) begin
            litedramcore_sdram_bankmachine0_level <= (litedramcore_sdram_bankmachine0_level + 1'd1);
        end
    end else begin
        if (litedramcore_sdram_bankmachine0_do_read) begin
            litedramcore_sdram_bankmachine0_level <= (litedramcore_sdram_bankmachine0_level - 1'd1);
        end
    end
    if (((~litedramcore_sdram_bankmachine0_pipe_valid_source_valid) | litedramcore_sdram_bankmachine0_pipe_valid_source_ready)) begin
        litedramcore_sdram_bankmachine0_pipe_valid_source_valid <= litedramcore_sdram_bankmachine0_pipe_valid_sink_valid;
        litedramcore_sdram_bankmachine0_pipe_valid_source_first <= litedramcore_sdram_bankmachine0_pipe_valid_sink_first;
        litedramcore_sdram_bankmachine0_pipe_valid_source_last <= litedramcore_sdram_bankmachine0_pipe_valid_sink_last;
        litedramcore_sdram_bankmachine0_pipe_valid_source_payload_we <= litedramcore_sdram_bankmachine0_pipe_valid_sink_payload_we;
        litedramcore_sdram_bankmachine0_pipe_valid_source_payload_addr <= litedramcore_sdram_bankmachine0_pipe_valid_sink_payload_addr;
    end
    if (litedramcore_sdram_bankmachine0_twtpcon_valid) begin
        litedramcore_sdram_bankmachine0_twtpcon_count <= 3'd6;
        if (1'd0) begin
            litedramcore_sdram_bankmachine0_twtpcon_ready <= 1'd1;
        end else begin
            litedramcore_sdram_bankmachine0_twtpcon_ready <= 1'd0;
        end
    end else begin
        if ((~litedramcore_sdram_bankmachine0_twtpcon_ready)) begin
            litedramcore_sdram_bankmachine0_twtpcon_count <= (litedramcore_sdram_bankmachine0_twtpcon_count - 1'd1);
            if ((litedramcore_sdram_bankmachine0_twtpcon_count == 1'd1)) begin
                litedramcore_sdram_bankmachine0_twtpcon_ready <= 1'd1;
            end
        end
    end
    if (litedramcore_sdram_bankmachine0_trccon_valid) begin
        litedramcore_sdram_bankmachine0_trccon_count <= 4'd10;
        if (1'd0) begin
            litedramcore_sdram_bankmachine0_trccon_ready <= 1'd1;
        end else begin
            litedramcore_sdram_bankmachine0_trccon_ready <= 1'd0;
        end
    end else begin
        if ((~litedramcore_sdram_bankmachine0_trccon_ready)) begin
            litedramcore_sdram_bankmachine0_trccon_count <= (litedramcore_sdram_bankmachine0_trccon_count - 1'd1);
            if ((litedramcore_sdram_bankmachine0_trccon_count == 1'd1)) begin
                litedramcore_sdram_bankmachine0_trccon_ready <= 1'd1;
            end
        end
    end
    if (litedramcore_sdram_bankmachine0_trascon_valid) begin
        litedramcore_sdram_bankmachine0_trascon_count <= 3'd7;
        if (1'd0) begin
            litedramcore_sdram_bankmachine0_trascon_ready <= 1'd1;
        end else begin
            litedramcore_sdram_bankmachine0_trascon_ready <= 1'd0;
        end
    end else begin
        if ((~litedramcore_sdram_bankmachine0_trascon_ready)) begin
            litedramcore_sdram_bankmachine0_trascon_count <= (litedramcore_sdram_bankmachine0_trascon_count - 1'd1);
            if ((litedramcore_sdram_bankmachine0_trascon_count == 1'd1)) begin
                litedramcore_sdram_bankmachine0_trascon_ready <= 1'd1;
            end
        end
    end
    litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state;
    if (litedramcore_sdram_bankmachine1_row_close) begin
        litedramcore_sdram_bankmachine1_row_opened <= 1'd0;
    end else begin
        if (litedramcore_sdram_bankmachine1_row_open) begin
            litedramcore_sdram_bankmachine1_row_opened <= 1'd1;
            litedramcore_sdram_bankmachine1_row <= litedramcore_sdram_bankmachine1_source_source_payload_addr[21:7];
        end
    end
    if (((litedramcore_sdram_bankmachine1_syncfifo1_we & litedramcore_sdram_bankmachine1_syncfifo1_writable) & (~litedramcore_sdram_bankmachine1_replace))) begin
        litedramcore_sdram_bankmachine1_produce <= (litedramcore_sdram_bankmachine1_produce + 1'd1);
    end
    if (litedramcore_sdram_bankmachine1_do_read) begin
        litedramcore_sdram_bankmachine1_consume <= (litedramcore_sdram_bankmachine1_consume + 1'd1);
    end
    if (((litedramcore_sdram_bankmachine1_syncfifo1_we & litedramcore_sdram_bankmachine1_syncfifo1_writable) & (~litedramcore_sdram_bankmachine1_replace))) begin
        if ((~litedramcore_sdram_bankmachine1_do_read)) begin
            litedramcore_sdram_bankmachine1_level <= (litedramcore_sdram_bankmachine1_level + 1'd1);
        end
    end else begin
        if (litedramcore_sdram_bankmachine1_do_read) begin
            litedramcore_sdram_bankmachine1_level <= (litedramcore_sdram_bankmachine1_level - 1'd1);
        end
    end
    if (((~litedramcore_sdram_bankmachine1_pipe_valid_source_valid) | litedramcore_sdram_bankmachine1_pipe_valid_source_ready)) begin
        litedramcore_sdram_bankmachine1_pipe_valid_source_valid <= litedramcore_sdram_bankmachine1_pipe_valid_sink_valid;
        litedramcore_sdram_bankmachine1_pipe_valid_source_first <= litedramcore_sdram_bankmachine1_pipe_valid_sink_first;
        litedramcore_sdram_bankmachine1_pipe_valid_source_last <= litedramcore_sdram_bankmachine1_pipe_valid_sink_last;
        litedramcore_sdram_bankmachine1_pipe_valid_source_payload_we <= litedramcore_sdram_bankmachine1_pipe_valid_sink_payload_we;
        litedramcore_sdram_bankmachine1_pipe_valid_source_payload_addr <= litedramcore_sdram_bankmachine1_pipe_valid_sink_payload_addr;
    end
    if (litedramcore_sdram_bankmachine1_twtpcon_valid) begin
        litedramcore_sdram_bankmachine1_twtpcon_count <= 3'd6;
        if (1'd0) begin
            litedramcore_sdram_bankmachine1_twtpcon_ready <= 1'd1;
        end else begin
            litedramcore_sdram_bankmachine1_twtpcon_ready <= 1'd0;
        end
    end else begin
        if ((~litedramcore_sdram_bankmachine1_twtpcon_ready)) begin
            litedramcore_sdram_bankmachine1_twtpcon_count <= (litedramcore_sdram_bankmachine1_twtpcon_count - 1'd1);
            if ((litedramcore_sdram_bankmachine1_twtpcon_count == 1'd1)) begin
                litedramcore_sdram_bankmachine1_twtpcon_ready <= 1'd1;
            end
        end
    end
    if (litedramcore_sdram_bankmachine1_trccon_valid) begin
        litedramcore_sdram_bankmachine1_trccon_count <= 4'd10;
        if (1'd0) begin
            litedramcore_sdram_bankmachine1_trccon_ready <= 1'd1;
        end else begin
            litedramcore_sdram_bankmachine1_trccon_ready <= 1'd0;
        end
    end else begin
        if ((~litedramcore_sdram_bankmachine1_trccon_ready)) begin
            litedramcore_sdram_bankmachine1_trccon_count <= (litedramcore_sdram_bankmachine1_trccon_count - 1'd1);
            if ((litedramcore_sdram_bankmachine1_trccon_count == 1'd1)) begin
                litedramcore_sdram_bankmachine1_trccon_ready <= 1'd1;
            end
        end
    end
    if (litedramcore_sdram_bankmachine1_trascon_valid) begin
        litedramcore_sdram_bankmachine1_trascon_count <= 3'd7;
        if (1'd0) begin
            litedramcore_sdram_bankmachine1_trascon_ready <= 1'd1;
        end else begin
            litedramcore_sdram_bankmachine1_trascon_ready <= 1'd0;
        end
    end else begin
        if ((~litedramcore_sdram_bankmachine1_trascon_ready)) begin
            litedramcore_sdram_bankmachine1_trascon_count <= (litedramcore_sdram_bankmachine1_trascon_count - 1'd1);
            if ((litedramcore_sdram_bankmachine1_trascon_count == 1'd1)) begin
                litedramcore_sdram_bankmachine1_trascon_ready <= 1'd1;
            end
        end
    end
    litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state;
    if (litedramcore_sdram_bankmachine2_row_close) begin
        litedramcore_sdram_bankmachine2_row_opened <= 1'd0;
    end else begin
        if (litedramcore_sdram_bankmachine2_row_open) begin
            litedramcore_sdram_bankmachine2_row_opened <= 1'd1;
            litedramcore_sdram_bankmachine2_row <= litedramcore_sdram_bankmachine2_source_source_payload_addr[21:7];
        end
    end
    if (((litedramcore_sdram_bankmachine2_syncfifo2_we & litedramcore_sdram_bankmachine2_syncfifo2_writable) & (~litedramcore_sdram_bankmachine2_replace))) begin
        litedramcore_sdram_bankmachine2_produce <= (litedramcore_sdram_bankmachine2_produce + 1'd1);
    end
    if (litedramcore_sdram_bankmachine2_do_read) begin
        litedramcore_sdram_bankmachine2_consume <= (litedramcore_sdram_bankmachine2_consume + 1'd1);
    end
    if (((litedramcore_sdram_bankmachine2_syncfifo2_we & litedramcore_sdram_bankmachine2_syncfifo2_writable) & (~litedramcore_sdram_bankmachine2_replace))) begin
        if ((~litedramcore_sdram_bankmachine2_do_read)) begin
            litedramcore_sdram_bankmachine2_level <= (litedramcore_sdram_bankmachine2_level + 1'd1);
        end
    end else begin
        if (litedramcore_sdram_bankmachine2_do_read) begin
            litedramcore_sdram_bankmachine2_level <= (litedramcore_sdram_bankmachine2_level - 1'd1);
        end
    end
    if (((~litedramcore_sdram_bankmachine2_pipe_valid_source_valid) | litedramcore_sdram_bankmachine2_pipe_valid_source_ready)) begin
        litedramcore_sdram_bankmachine2_pipe_valid_source_valid <= litedramcore_sdram_bankmachine2_pipe_valid_sink_valid;
        litedramcore_sdram_bankmachine2_pipe_valid_source_first <= litedramcore_sdram_bankmachine2_pipe_valid_sink_first;
        litedramcore_sdram_bankmachine2_pipe_valid_source_last <= litedramcore_sdram_bankmachine2_pipe_valid_sink_last;
        litedramcore_sdram_bankmachine2_pipe_valid_source_payload_we <= litedramcore_sdram_bankmachine2_pipe_valid_sink_payload_we;
        litedramcore_sdram_bankmachine2_pipe_valid_source_payload_addr <= litedramcore_sdram_bankmachine2_pipe_valid_sink_payload_addr;
    end
    if (litedramcore_sdram_bankmachine2_twtpcon_valid) begin
        litedramcore_sdram_bankmachine2_twtpcon_count <= 3'd6;
        if (1'd0) begin
            litedramcore_sdram_bankmachine2_twtpcon_ready <= 1'd1;
        end else begin
            litedramcore_sdram_bankmachine2_twtpcon_ready <= 1'd0;
        end
    end else begin
        if ((~litedramcore_sdram_bankmachine2_twtpcon_ready)) begin
            litedramcore_sdram_bankmachine2_twtpcon_count <= (litedramcore_sdram_bankmachine2_twtpcon_count - 1'd1);
            if ((litedramcore_sdram_bankmachine2_twtpcon_count == 1'd1)) begin
                litedramcore_sdram_bankmachine2_twtpcon_ready <= 1'd1;
            end
        end
    end
    if (litedramcore_sdram_bankmachine2_trccon_valid) begin
        litedramcore_sdram_bankmachine2_trccon_count <= 4'd10;
        if (1'd0) begin
            litedramcore_sdram_bankmachine2_trccon_ready <= 1'd1;
        end else begin
            litedramcore_sdram_bankmachine2_trccon_ready <= 1'd0;
        end
    end else begin
        if ((~litedramcore_sdram_bankmachine2_trccon_ready)) begin
            litedramcore_sdram_bankmachine2_trccon_count <= (litedramcore_sdram_bankmachine2_trccon_count - 1'd1);
            if ((litedramcore_sdram_bankmachine2_trccon_count == 1'd1)) begin
                litedramcore_sdram_bankmachine2_trccon_ready <= 1'd1;
            end
        end
    end
    if (litedramcore_sdram_bankmachine2_trascon_valid) begin
        litedramcore_sdram_bankmachine2_trascon_count <= 3'd7;
        if (1'd0) begin
            litedramcore_sdram_bankmachine2_trascon_ready <= 1'd1;
        end else begin
            litedramcore_sdram_bankmachine2_trascon_ready <= 1'd0;
        end
    end else begin
        if ((~litedramcore_sdram_bankmachine2_trascon_ready)) begin
            litedramcore_sdram_bankmachine2_trascon_count <= (litedramcore_sdram_bankmachine2_trascon_count - 1'd1);
            if ((litedramcore_sdram_bankmachine2_trascon_count == 1'd1)) begin
                litedramcore_sdram_bankmachine2_trascon_ready <= 1'd1;
            end
        end
    end
    litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state;
    if (litedramcore_sdram_bankmachine3_row_close) begin
        litedramcore_sdram_bankmachine3_row_opened <= 1'd0;
    end else begin
        if (litedramcore_sdram_bankmachine3_row_open) begin
            litedramcore_sdram_bankmachine3_row_opened <= 1'd1;
            litedramcore_sdram_bankmachine3_row <= litedramcore_sdram_bankmachine3_source_source_payload_addr[21:7];
        end
    end
    if (((litedramcore_sdram_bankmachine3_syncfifo3_we & litedramcore_sdram_bankmachine3_syncfifo3_writable) & (~litedramcore_sdram_bankmachine3_replace))) begin
        litedramcore_sdram_bankmachine3_produce <= (litedramcore_sdram_bankmachine3_produce + 1'd1);
    end
    if (litedramcore_sdram_bankmachine3_do_read) begin
        litedramcore_sdram_bankmachine3_consume <= (litedramcore_sdram_bankmachine3_consume + 1'd1);
    end
    if (((litedramcore_sdram_bankmachine3_syncfifo3_we & litedramcore_sdram_bankmachine3_syncfifo3_writable) & (~litedramcore_sdram_bankmachine3_replace))) begin
        if ((~litedramcore_sdram_bankmachine3_do_read)) begin
            litedramcore_sdram_bankmachine3_level <= (litedramcore_sdram_bankmachine3_level + 1'd1);
        end
    end else begin
        if (litedramcore_sdram_bankmachine3_do_read) begin
            litedramcore_sdram_bankmachine3_level <= (litedramcore_sdram_bankmachine3_level - 1'd1);
        end
    end
    if (((~litedramcore_sdram_bankmachine3_pipe_valid_source_valid) | litedramcore_sdram_bankmachine3_pipe_valid_source_ready)) begin
        litedramcore_sdram_bankmachine3_pipe_valid_source_valid <= litedramcore_sdram_bankmachine3_pipe_valid_sink_valid;
        litedramcore_sdram_bankmachine3_pipe_valid_source_first <= litedramcore_sdram_bankmachine3_pipe_valid_sink_first;
        litedramcore_sdram_bankmachine3_pipe_valid_source_last <= litedramcore_sdram_bankmachine3_pipe_valid_sink_last;
        litedramcore_sdram_bankmachine3_pipe_valid_source_payload_we <= litedramcore_sdram_bankmachine3_pipe_valid_sink_payload_we;
        litedramcore_sdram_bankmachine3_pipe_valid_source_payload_addr <= litedramcore_sdram_bankmachine3_pipe_valid_sink_payload_addr;
    end
    if (litedramcore_sdram_bankmachine3_twtpcon_valid) begin
        litedramcore_sdram_bankmachine3_twtpcon_count <= 3'd6;
        if (1'd0) begin
            litedramcore_sdram_bankmachine3_twtpcon_ready <= 1'd1;
        end else begin
            litedramcore_sdram_bankmachine3_twtpcon_ready <= 1'd0;
        end
    end else begin
        if ((~litedramcore_sdram_bankmachine3_twtpcon_ready)) begin
            litedramcore_sdram_bankmachine3_twtpcon_count <= (litedramcore_sdram_bankmachine3_twtpcon_count - 1'd1);
            if ((litedramcore_sdram_bankmachine3_twtpcon_count == 1'd1)) begin
                litedramcore_sdram_bankmachine3_twtpcon_ready <= 1'd1;
            end
        end
    end
    if (litedramcore_sdram_bankmachine3_trccon_valid) begin
        litedramcore_sdram_bankmachine3_trccon_count <= 4'd10;
        if (1'd0) begin
            litedramcore_sdram_bankmachine3_trccon_ready <= 1'd1;
        end else begin
            litedramcore_sdram_bankmachine3_trccon_ready <= 1'd0;
        end
    end else begin
        if ((~litedramcore_sdram_bankmachine3_trccon_ready)) begin
            litedramcore_sdram_bankmachine3_trccon_count <= (litedramcore_sdram_bankmachine3_trccon_count - 1'd1);
            if ((litedramcore_sdram_bankmachine3_trccon_count == 1'd1)) begin
                litedramcore_sdram_bankmachine3_trccon_ready <= 1'd1;
            end
        end
    end
    if (litedramcore_sdram_bankmachine3_trascon_valid) begin
        litedramcore_sdram_bankmachine3_trascon_count <= 3'd7;
        if (1'd0) begin
            litedramcore_sdram_bankmachine3_trascon_ready <= 1'd1;
        end else begin
            litedramcore_sdram_bankmachine3_trascon_ready <= 1'd0;
        end
    end else begin
        if ((~litedramcore_sdram_bankmachine3_trascon_ready)) begin
            litedramcore_sdram_bankmachine3_trascon_count <= (litedramcore_sdram_bankmachine3_trascon_count - 1'd1);
            if ((litedramcore_sdram_bankmachine3_trascon_count == 1'd1)) begin
                litedramcore_sdram_bankmachine3_trascon_ready <= 1'd1;
            end
        end
    end
    litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state;
    if (litedramcore_sdram_bankmachine4_row_close) begin
        litedramcore_sdram_bankmachine4_row_opened <= 1'd0;
    end else begin
        if (litedramcore_sdram_bankmachine4_row_open) begin
            litedramcore_sdram_bankmachine4_row_opened <= 1'd1;
            litedramcore_sdram_bankmachine4_row <= litedramcore_sdram_bankmachine4_source_source_payload_addr[21:7];
        end
    end
    if (((litedramcore_sdram_bankmachine4_syncfifo4_we & litedramcore_sdram_bankmachine4_syncfifo4_writable) & (~litedramcore_sdram_bankmachine4_replace))) begin
        litedramcore_sdram_bankmachine4_produce <= (litedramcore_sdram_bankmachine4_produce + 1'd1);
    end
    if (litedramcore_sdram_bankmachine4_do_read) begin
        litedramcore_sdram_bankmachine4_consume <= (litedramcore_sdram_bankmachine4_consume + 1'd1);
    end
    if (((litedramcore_sdram_bankmachine4_syncfifo4_we & litedramcore_sdram_bankmachine4_syncfifo4_writable) & (~litedramcore_sdram_bankmachine4_replace))) begin
        if ((~litedramcore_sdram_bankmachine4_do_read)) begin
            litedramcore_sdram_bankmachine4_level <= (litedramcore_sdram_bankmachine4_level + 1'd1);
        end
    end else begin
        if (litedramcore_sdram_bankmachine4_do_read) begin
            litedramcore_sdram_bankmachine4_level <= (litedramcore_sdram_bankmachine4_level - 1'd1);
        end
    end
    if (((~litedramcore_sdram_bankmachine4_pipe_valid_source_valid) | litedramcore_sdram_bankmachine4_pipe_valid_source_ready)) begin
        litedramcore_sdram_bankmachine4_pipe_valid_source_valid <= litedramcore_sdram_bankmachine4_pipe_valid_sink_valid;
        litedramcore_sdram_bankmachine4_pipe_valid_source_first <= litedramcore_sdram_bankmachine4_pipe_valid_sink_first;
        litedramcore_sdram_bankmachine4_pipe_valid_source_last <= litedramcore_sdram_bankmachine4_pipe_valid_sink_last;
        litedramcore_sdram_bankmachine4_pipe_valid_source_payload_we <= litedramcore_sdram_bankmachine4_pipe_valid_sink_payload_we;
        litedramcore_sdram_bankmachine4_pipe_valid_source_payload_addr <= litedramcore_sdram_bankmachine4_pipe_valid_sink_payload_addr;
    end
    if (litedramcore_sdram_bankmachine4_twtpcon_valid) begin
        litedramcore_sdram_bankmachine4_twtpcon_count <= 3'd6;
        if (1'd0) begin
            litedramcore_sdram_bankmachine4_twtpcon_ready <= 1'd1;
        end else begin
            litedramcore_sdram_bankmachine4_twtpcon_ready <= 1'd0;
        end
    end else begin
        if ((~litedramcore_sdram_bankmachine4_twtpcon_ready)) begin
            litedramcore_sdram_bankmachine4_twtpcon_count <= (litedramcore_sdram_bankmachine4_twtpcon_count - 1'd1);
            if ((litedramcore_sdram_bankmachine4_twtpcon_count == 1'd1)) begin
                litedramcore_sdram_bankmachine4_twtpcon_ready <= 1'd1;
            end
        end
    end
    if (litedramcore_sdram_bankmachine4_trccon_valid) begin
        litedramcore_sdram_bankmachine4_trccon_count <= 4'd10;
        if (1'd0) begin
            litedramcore_sdram_bankmachine4_trccon_ready <= 1'd1;
        end else begin
            litedramcore_sdram_bankmachine4_trccon_ready <= 1'd0;
        end
    end else begin
        if ((~litedramcore_sdram_bankmachine4_trccon_ready)) begin
            litedramcore_sdram_bankmachine4_trccon_count <= (litedramcore_sdram_bankmachine4_trccon_count - 1'd1);
            if ((litedramcore_sdram_bankmachine4_trccon_count == 1'd1)) begin
                litedramcore_sdram_bankmachine4_trccon_ready <= 1'd1;
            end
        end
    end
    if (litedramcore_sdram_bankmachine4_trascon_valid) begin
        litedramcore_sdram_bankmachine4_trascon_count <= 3'd7;
        if (1'd0) begin
            litedramcore_sdram_bankmachine4_trascon_ready <= 1'd1;
        end else begin
            litedramcore_sdram_bankmachine4_trascon_ready <= 1'd0;
        end
    end else begin
        if ((~litedramcore_sdram_bankmachine4_trascon_ready)) begin
            litedramcore_sdram_bankmachine4_trascon_count <= (litedramcore_sdram_bankmachine4_trascon_count - 1'd1);
            if ((litedramcore_sdram_bankmachine4_trascon_count == 1'd1)) begin
                litedramcore_sdram_bankmachine4_trascon_ready <= 1'd1;
            end
        end
    end
    litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state;
    if (litedramcore_sdram_bankmachine5_row_close) begin
        litedramcore_sdram_bankmachine5_row_opened <= 1'd0;
    end else begin
        if (litedramcore_sdram_bankmachine5_row_open) begin
            litedramcore_sdram_bankmachine5_row_opened <= 1'd1;
            litedramcore_sdram_bankmachine5_row <= litedramcore_sdram_bankmachine5_source_source_payload_addr[21:7];
        end
    end
    if (((litedramcore_sdram_bankmachine5_syncfifo5_we & litedramcore_sdram_bankmachine5_syncfifo5_writable) & (~litedramcore_sdram_bankmachine5_replace))) begin
        litedramcore_sdram_bankmachine5_produce <= (litedramcore_sdram_bankmachine5_produce + 1'd1);
    end
    if (litedramcore_sdram_bankmachine5_do_read) begin
        litedramcore_sdram_bankmachine5_consume <= (litedramcore_sdram_bankmachine5_consume + 1'd1);
    end
    if (((litedramcore_sdram_bankmachine5_syncfifo5_we & litedramcore_sdram_bankmachine5_syncfifo5_writable) & (~litedramcore_sdram_bankmachine5_replace))) begin
        if ((~litedramcore_sdram_bankmachine5_do_read)) begin
            litedramcore_sdram_bankmachine5_level <= (litedramcore_sdram_bankmachine5_level + 1'd1);
        end
    end else begin
        if (litedramcore_sdram_bankmachine5_do_read) begin
            litedramcore_sdram_bankmachine5_level <= (litedramcore_sdram_bankmachine5_level - 1'd1);
        end
    end
    if (((~litedramcore_sdram_bankmachine5_pipe_valid_source_valid) | litedramcore_sdram_bankmachine5_pipe_valid_source_ready)) begin
        litedramcore_sdram_bankmachine5_pipe_valid_source_valid <= litedramcore_sdram_bankmachine5_pipe_valid_sink_valid;
        litedramcore_sdram_bankmachine5_pipe_valid_source_first <= litedramcore_sdram_bankmachine5_pipe_valid_sink_first;
        litedramcore_sdram_bankmachine5_pipe_valid_source_last <= litedramcore_sdram_bankmachine5_pipe_valid_sink_last;
        litedramcore_sdram_bankmachine5_pipe_valid_source_payload_we <= litedramcore_sdram_bankmachine5_pipe_valid_sink_payload_we;
        litedramcore_sdram_bankmachine5_pipe_valid_source_payload_addr <= litedramcore_sdram_bankmachine5_pipe_valid_sink_payload_addr;
    end
    if (litedramcore_sdram_bankmachine5_twtpcon_valid) begin
        litedramcore_sdram_bankmachine5_twtpcon_count <= 3'd6;
        if (1'd0) begin
            litedramcore_sdram_bankmachine5_twtpcon_ready <= 1'd1;
        end else begin
            litedramcore_sdram_bankmachine5_twtpcon_ready <= 1'd0;
        end
    end else begin
        if ((~litedramcore_sdram_bankmachine5_twtpcon_ready)) begin
            litedramcore_sdram_bankmachine5_twtpcon_count <= (litedramcore_sdram_bankmachine5_twtpcon_count - 1'd1);
            if ((litedramcore_sdram_bankmachine5_twtpcon_count == 1'd1)) begin
                litedramcore_sdram_bankmachine5_twtpcon_ready <= 1'd1;
            end
        end
    end
    if (litedramcore_sdram_bankmachine5_trccon_valid) begin
        litedramcore_sdram_bankmachine5_trccon_count <= 4'd10;
        if (1'd0) begin
            litedramcore_sdram_bankmachine5_trccon_ready <= 1'd1;
        end else begin
            litedramcore_sdram_bankmachine5_trccon_ready <= 1'd0;
        end
    end else begin
        if ((~litedramcore_sdram_bankmachine5_trccon_ready)) begin
            litedramcore_sdram_bankmachine5_trccon_count <= (litedramcore_sdram_bankmachine5_trccon_count - 1'd1);
            if ((litedramcore_sdram_bankmachine5_trccon_count == 1'd1)) begin
                litedramcore_sdram_bankmachine5_trccon_ready <= 1'd1;
            end
        end
    end
    if (litedramcore_sdram_bankmachine5_trascon_valid) begin
        litedramcore_sdram_bankmachine5_trascon_count <= 3'd7;
        if (1'd0) begin
            litedramcore_sdram_bankmachine5_trascon_ready <= 1'd1;
        end else begin
            litedramcore_sdram_bankmachine5_trascon_ready <= 1'd0;
        end
    end else begin
        if ((~litedramcore_sdram_bankmachine5_trascon_ready)) begin
            litedramcore_sdram_bankmachine5_trascon_count <= (litedramcore_sdram_bankmachine5_trascon_count - 1'd1);
            if ((litedramcore_sdram_bankmachine5_trascon_count == 1'd1)) begin
                litedramcore_sdram_bankmachine5_trascon_ready <= 1'd1;
            end
        end
    end
    litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state;
    if (litedramcore_sdram_bankmachine6_row_close) begin
        litedramcore_sdram_bankmachine6_row_opened <= 1'd0;
    end else begin
        if (litedramcore_sdram_bankmachine6_row_open) begin
            litedramcore_sdram_bankmachine6_row_opened <= 1'd1;
            litedramcore_sdram_bankmachine6_row <= litedramcore_sdram_bankmachine6_source_source_payload_addr[21:7];
        end
    end
    if (((litedramcore_sdram_bankmachine6_syncfifo6_we & litedramcore_sdram_bankmachine6_syncfifo6_writable) & (~litedramcore_sdram_bankmachine6_replace))) begin
        litedramcore_sdram_bankmachine6_produce <= (litedramcore_sdram_bankmachine6_produce + 1'd1);
    end
    if (litedramcore_sdram_bankmachine6_do_read) begin
        litedramcore_sdram_bankmachine6_consume <= (litedramcore_sdram_bankmachine6_consume + 1'd1);
    end
    if (((litedramcore_sdram_bankmachine6_syncfifo6_we & litedramcore_sdram_bankmachine6_syncfifo6_writable) & (~litedramcore_sdram_bankmachine6_replace))) begin
        if ((~litedramcore_sdram_bankmachine6_do_read)) begin
            litedramcore_sdram_bankmachine6_level <= (litedramcore_sdram_bankmachine6_level + 1'd1);
        end
    end else begin
        if (litedramcore_sdram_bankmachine6_do_read) begin
            litedramcore_sdram_bankmachine6_level <= (litedramcore_sdram_bankmachine6_level - 1'd1);
        end
    end
    if (((~litedramcore_sdram_bankmachine6_pipe_valid_source_valid) | litedramcore_sdram_bankmachine6_pipe_valid_source_ready)) begin
        litedramcore_sdram_bankmachine6_pipe_valid_source_valid <= litedramcore_sdram_bankmachine6_pipe_valid_sink_valid;
        litedramcore_sdram_bankmachine6_pipe_valid_source_first <= litedramcore_sdram_bankmachine6_pipe_valid_sink_first;
        litedramcore_sdram_bankmachine6_pipe_valid_source_last <= litedramcore_sdram_bankmachine6_pipe_valid_sink_last;
        litedramcore_sdram_bankmachine6_pipe_valid_source_payload_we <= litedramcore_sdram_bankmachine6_pipe_valid_sink_payload_we;
        litedramcore_sdram_bankmachine6_pipe_valid_source_payload_addr <= litedramcore_sdram_bankmachine6_pipe_valid_sink_payload_addr;
    end
    if (litedramcore_sdram_bankmachine6_twtpcon_valid) begin
        litedramcore_sdram_bankmachine6_twtpcon_count <= 3'd6;
        if (1'd0) begin
            litedramcore_sdram_bankmachine6_twtpcon_ready <= 1'd1;
        end else begin
            litedramcore_sdram_bankmachine6_twtpcon_ready <= 1'd0;
        end
    end else begin
        if ((~litedramcore_sdram_bankmachine6_twtpcon_ready)) begin
            litedramcore_sdram_bankmachine6_twtpcon_count <= (litedramcore_sdram_bankmachine6_twtpcon_count - 1'd1);
            if ((litedramcore_sdram_bankmachine6_twtpcon_count == 1'd1)) begin
                litedramcore_sdram_bankmachine6_twtpcon_ready <= 1'd1;
            end
        end
    end
    if (litedramcore_sdram_bankmachine6_trccon_valid) begin
        litedramcore_sdram_bankmachine6_trccon_count <= 4'd10;
        if (1'd0) begin
            litedramcore_sdram_bankmachine6_trccon_ready <= 1'd1;
        end else begin
            litedramcore_sdram_bankmachine6_trccon_ready <= 1'd0;
        end
    end else begin
        if ((~litedramcore_sdram_bankmachine6_trccon_ready)) begin
            litedramcore_sdram_bankmachine6_trccon_count <= (litedramcore_sdram_bankmachine6_trccon_count - 1'd1);
            if ((litedramcore_sdram_bankmachine6_trccon_count == 1'd1)) begin
                litedramcore_sdram_bankmachine6_trccon_ready <= 1'd1;
            end
        end
    end
    if (litedramcore_sdram_bankmachine6_trascon_valid) begin
        litedramcore_sdram_bankmachine6_trascon_count <= 3'd7;
        if (1'd0) begin
            litedramcore_sdram_bankmachine6_trascon_ready <= 1'd1;
        end else begin
            litedramcore_sdram_bankmachine6_trascon_ready <= 1'd0;
        end
    end else begin
        if ((~litedramcore_sdram_bankmachine6_trascon_ready)) begin
            litedramcore_sdram_bankmachine6_trascon_count <= (litedramcore_sdram_bankmachine6_trascon_count - 1'd1);
            if ((litedramcore_sdram_bankmachine6_trascon_count == 1'd1)) begin
                litedramcore_sdram_bankmachine6_trascon_ready <= 1'd1;
            end
        end
    end
    litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state;
    if (litedramcore_sdram_bankmachine7_row_close) begin
        litedramcore_sdram_bankmachine7_row_opened <= 1'd0;
    end else begin
        if (litedramcore_sdram_bankmachine7_row_open) begin
            litedramcore_sdram_bankmachine7_row_opened <= 1'd1;
            litedramcore_sdram_bankmachine7_row <= litedramcore_sdram_bankmachine7_source_source_payload_addr[21:7];
        end
    end
    if (((litedramcore_sdram_bankmachine7_syncfifo7_we & litedramcore_sdram_bankmachine7_syncfifo7_writable) & (~litedramcore_sdram_bankmachine7_replace))) begin
        litedramcore_sdram_bankmachine7_produce <= (litedramcore_sdram_bankmachine7_produce + 1'd1);
    end
    if (litedramcore_sdram_bankmachine7_do_read) begin
        litedramcore_sdram_bankmachine7_consume <= (litedramcore_sdram_bankmachine7_consume + 1'd1);
    end
    if (((litedramcore_sdram_bankmachine7_syncfifo7_we & litedramcore_sdram_bankmachine7_syncfifo7_writable) & (~litedramcore_sdram_bankmachine7_replace))) begin
        if ((~litedramcore_sdram_bankmachine7_do_read)) begin
            litedramcore_sdram_bankmachine7_level <= (litedramcore_sdram_bankmachine7_level + 1'd1);
        end
    end else begin
        if (litedramcore_sdram_bankmachine7_do_read) begin
            litedramcore_sdram_bankmachine7_level <= (litedramcore_sdram_bankmachine7_level - 1'd1);
        end
    end
    if (((~litedramcore_sdram_bankmachine7_pipe_valid_source_valid) | litedramcore_sdram_bankmachine7_pipe_valid_source_ready)) begin
        litedramcore_sdram_bankmachine7_pipe_valid_source_valid <= litedramcore_sdram_bankmachine7_pipe_valid_sink_valid;
        litedramcore_sdram_bankmachine7_pipe_valid_source_first <= litedramcore_sdram_bankmachine7_pipe_valid_sink_first;
        litedramcore_sdram_bankmachine7_pipe_valid_source_last <= litedramcore_sdram_bankmachine7_pipe_valid_sink_last;
        litedramcore_sdram_bankmachine7_pipe_valid_source_payload_we <= litedramcore_sdram_bankmachine7_pipe_valid_sink_payload_we;
        litedramcore_sdram_bankmachine7_pipe_valid_source_payload_addr <= litedramcore_sdram_bankmachine7_pipe_valid_sink_payload_addr;
    end
    if (litedramcore_sdram_bankmachine7_twtpcon_valid) begin
        litedramcore_sdram_bankmachine7_twtpcon_count <= 3'd6;
        if (1'd0) begin
            litedramcore_sdram_bankmachine7_twtpcon_ready <= 1'd1;
        end else begin
            litedramcore_sdram_bankmachine7_twtpcon_ready <= 1'd0;
        end
    end else begin
        if ((~litedramcore_sdram_bankmachine7_twtpcon_ready)) begin
            litedramcore_sdram_bankmachine7_twtpcon_count <= (litedramcore_sdram_bankmachine7_twtpcon_count - 1'd1);
            if ((litedramcore_sdram_bankmachine7_twtpcon_count == 1'd1)) begin
                litedramcore_sdram_bankmachine7_twtpcon_ready <= 1'd1;
            end
        end
    end
    if (litedramcore_sdram_bankmachine7_trccon_valid) begin
        litedramcore_sdram_bankmachine7_trccon_count <= 4'd10;
        if (1'd0) begin
            litedramcore_sdram_bankmachine7_trccon_ready <= 1'd1;
        end else begin
            litedramcore_sdram_bankmachine7_trccon_ready <= 1'd0;
        end
    end else begin
        if ((~litedramcore_sdram_bankmachine7_trccon_ready)) begin
            litedramcore_sdram_bankmachine7_trccon_count <= (litedramcore_sdram_bankmachine7_trccon_count - 1'd1);
            if ((litedramcore_sdram_bankmachine7_trccon_count == 1'd1)) begin
                litedramcore_sdram_bankmachine7_trccon_ready <= 1'd1;
            end
        end
    end
    if (litedramcore_sdram_bankmachine7_trascon_valid) begin
        litedramcore_sdram_bankmachine7_trascon_count <= 3'd7;
        if (1'd0) begin
            litedramcore_sdram_bankmachine7_trascon_ready <= 1'd1;
        end else begin
            litedramcore_sdram_bankmachine7_trascon_ready <= 1'd0;
        end
    end else begin
        if ((~litedramcore_sdram_bankmachine7_trascon_ready)) begin
            litedramcore_sdram_bankmachine7_trascon_count <= (litedramcore_sdram_bankmachine7_trascon_count - 1'd1);
            if ((litedramcore_sdram_bankmachine7_trascon_count == 1'd1)) begin
                litedramcore_sdram_bankmachine7_trascon_ready <= 1'd1;
            end
        end
    end
    litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state;
    if ((~litedramcore_sdram_en0)) begin
        litedramcore_sdram_time0 <= 5'd31;
    end else begin
        if ((~litedramcore_sdram_max_time0)) begin
            litedramcore_sdram_time0 <= (litedramcore_sdram_time0 - 1'd1);
        end
    end
    if ((~litedramcore_sdram_en1)) begin
        litedramcore_sdram_time1 <= 4'd15;
    end else begin
        if ((~litedramcore_sdram_max_time1)) begin
            litedramcore_sdram_time1 <= (litedramcore_sdram_time1 - 1'd1);
        end
    end
    if (litedramcore_sdram_choose_cmd_ce) begin
        case (litedramcore_sdram_choose_cmd_grant)
            1'd0: begin
                if (litedramcore_sdram_choose_cmd_request[1]) begin
                    litedramcore_sdram_choose_cmd_grant <= 1'd1;
                end else begin
                    if (litedramcore_sdram_choose_cmd_request[2]) begin
                        litedramcore_sdram_choose_cmd_grant <= 2'd2;
                    end else begin
                        if (litedramcore_sdram_choose_cmd_request[3]) begin
                            litedramcore_sdram_choose_cmd_grant <= 2'd3;
                        end else begin
                            if (litedramcore_sdram_choose_cmd_request[4]) begin
                                litedramcore_sdram_choose_cmd_grant <= 3'd4;
                            end else begin
                                if (litedramcore_sdram_choose_cmd_request[5]) begin
                                    litedramcore_sdram_choose_cmd_grant <= 3'd5;
                                end else begin
                                    if (litedramcore_sdram_choose_cmd_request[6]) begin
                                        litedramcore_sdram_choose_cmd_grant <= 3'd6;
                                    end else begin
                                        if (litedramcore_sdram_choose_cmd_request[7]) begin
                                            litedramcore_sdram_choose_cmd_grant <= 3'd7;
                                        end
                                    end
                                end
                            end
                        end
                    end
                end
            end
            1'd1: begin
                if (litedramcore_sdram_choose_cmd_request[2]) begin
                    litedramcore_sdram_choose_cmd_grant <= 2'd2;
                end else begin
                    if (litedramcore_sdram_choose_cmd_request[3]) begin
                        litedramcore_sdram_choose_cmd_grant <= 2'd3;
                    end else begin
                        if (litedramcore_sdram_choose_cmd_request[4]) begin
                            litedramcore_sdram_choose_cmd_grant <= 3'd4;
                        end else begin
                            if (litedramcore_sdram_choose_cmd_request[5]) begin
                                litedramcore_sdram_choose_cmd_grant <= 3'd5;
                            end else begin
                                if (litedramcore_sdram_choose_cmd_request[6]) begin
                                    litedramcore_sdram_choose_cmd_grant <= 3'd6;
                                end else begin
                                    if (litedramcore_sdram_choose_cmd_request[7]) begin
                                        litedramcore_sdram_choose_cmd_grant <= 3'd7;
                                    end else begin
                                        if (litedramcore_sdram_choose_cmd_request[0]) begin
                                            litedramcore_sdram_choose_cmd_grant <= 1'd0;
                                        end
                                    end
                                end
                            end
                        end
                    end
                end
            end
            2'd2: begin
                if (litedramcore_sdram_choose_cmd_request[3]) begin
                    litedramcore_sdram_choose_cmd_grant <= 2'd3;
                end else begin
                    if (litedramcore_sdram_choose_cmd_request[4]) begin
                        litedramcore_sdram_choose_cmd_grant <= 3'd4;
                    end else begin
                        if (litedramcore_sdram_choose_cmd_request[5]) begin
                            litedramcore_sdram_choose_cmd_grant <= 3'd5;
                        end else begin
                            if (litedramcore_sdram_choose_cmd_request[6]) begin
                                litedramcore_sdram_choose_cmd_grant <= 3'd6;
                            end else begin
                                if (litedramcore_sdram_choose_cmd_request[7]) begin
                                    litedramcore_sdram_choose_cmd_grant <= 3'd7;
                                end else begin
                                    if (litedramcore_sdram_choose_cmd_request[0]) begin
                                        litedramcore_sdram_choose_cmd_grant <= 1'd0;
                                    end else begin
                                        if (litedramcore_sdram_choose_cmd_request[1]) begin
                                            litedramcore_sdram_choose_cmd_grant <= 1'd1;
                                        end
                                    end
                                end
                            end
                        end
                    end
                end
            end
            2'd3: begin
                if (litedramcore_sdram_choose_cmd_request[4]) begin
                    litedramcore_sdram_choose_cmd_grant <= 3'd4;
                end else begin
                    if (litedramcore_sdram_choose_cmd_request[5]) begin
                        litedramcore_sdram_choose_cmd_grant <= 3'd5;
                    end else begin
                        if (litedramcore_sdram_choose_cmd_request[6]) begin
                            litedramcore_sdram_choose_cmd_grant <= 3'd6;
                        end else begin
                            if (litedramcore_sdram_choose_cmd_request[7]) begin
                                litedramcore_sdram_choose_cmd_grant <= 3'd7;
                            end else begin
                                if (litedramcore_sdram_choose_cmd_request[0]) begin
                                    litedramcore_sdram_choose_cmd_grant <= 1'd0;
                                end else begin
                                    if (litedramcore_sdram_choose_cmd_request[1]) begin
                                        litedramcore_sdram_choose_cmd_grant <= 1'd1;
                                    end else begin
                                        if (litedramcore_sdram_choose_cmd_request[2]) begin
                                            litedramcore_sdram_choose_cmd_grant <= 2'd2;
                                        end
                                    end
                                end
                            end
                        end
                    end
                end
            end
            3'd4: begin
                if (litedramcore_sdram_choose_cmd_request[5]) begin
                    litedramcore_sdram_choose_cmd_grant <= 3'd5;
                end else begin
                    if (litedramcore_sdram_choose_cmd_request[6]) begin
                        litedramcore_sdram_choose_cmd_grant <= 3'd6;
                    end else begin
                        if (litedramcore_sdram_choose_cmd_request[7]) begin
                            litedramcore_sdram_choose_cmd_grant <= 3'd7;
                        end else begin
                            if (litedramcore_sdram_choose_cmd_request[0]) begin
                                litedramcore_sdram_choose_cmd_grant <= 1'd0;
                            end else begin
                                if (litedramcore_sdram_choose_cmd_request[1]) begin
                                    litedramcore_sdram_choose_cmd_grant <= 1'd1;
                                end else begin
                                    if (litedramcore_sdram_choose_cmd_request[2]) begin
                                        litedramcore_sdram_choose_cmd_grant <= 2'd2;
                                    end else begin
                                        if (litedramcore_sdram_choose_cmd_request[3]) begin
                                            litedramcore_sdram_choose_cmd_grant <= 2'd3;
                                        end
                                    end
                                end
                            end
                        end
                    end
                end
            end
            3'd5: begin
                if (litedramcore_sdram_choose_cmd_request[6]) begin
                    litedramcore_sdram_choose_cmd_grant <= 3'd6;
                end else begin
                    if (litedramcore_sdram_choose_cmd_request[7]) begin
                        litedramcore_sdram_choose_cmd_grant <= 3'd7;
                    end else begin
                        if (litedramcore_sdram_choose_cmd_request[0]) begin
                            litedramcore_sdram_choose_cmd_grant <= 1'd0;
                        end else begin
                            if (litedramcore_sdram_choose_cmd_request[1]) begin
                                litedramcore_sdram_choose_cmd_grant <= 1'd1;
                            end else begin
                                if (litedramcore_sdram_choose_cmd_request[2]) begin
                                    litedramcore_sdram_choose_cmd_grant <= 2'd2;
                                end else begin
                                    if (litedramcore_sdram_choose_cmd_request[3]) begin
                                        litedramcore_sdram_choose_cmd_grant <= 2'd3;
                                    end else begin
                                        if (litedramcore_sdram_choose_cmd_request[4]) begin
                                            litedramcore_sdram_choose_cmd_grant <= 3'd4;
                                        end
                                    end
                                end
                            end
                        end
                    end
                end
            end
            3'd6: begin
                if (litedramcore_sdram_choose_cmd_request[7]) begin
                    litedramcore_sdram_choose_cmd_grant <= 3'd7;
                end else begin
                    if (litedramcore_sdram_choose_cmd_request[0]) begin
                        litedramcore_sdram_choose_cmd_grant <= 1'd0;
                    end else begin
                        if (litedramcore_sdram_choose_cmd_request[1]) begin
                            litedramcore_sdram_choose_cmd_grant <= 1'd1;
                        end else begin
                            if (litedramcore_sdram_choose_cmd_request[2]) begin
                                litedramcore_sdram_choose_cmd_grant <= 2'd2;
                            end else begin
                                if (litedramcore_sdram_choose_cmd_request[3]) begin
                                    litedramcore_sdram_choose_cmd_grant <= 2'd3;
                                end else begin
                                    if (litedramcore_sdram_choose_cmd_request[4]) begin
                                        litedramcore_sdram_choose_cmd_grant <= 3'd4;
                                    end else begin
                                        if (litedramcore_sdram_choose_cmd_request[5]) begin
                                            litedramcore_sdram_choose_cmd_grant <= 3'd5;
                                        end
                                    end
                                end
                            end
                        end
                    end
                end
            end
            3'd7: begin
                if (litedramcore_sdram_choose_cmd_request[0]) begin
                    litedramcore_sdram_choose_cmd_grant <= 1'd0;
                end else begin
                    if (litedramcore_sdram_choose_cmd_request[1]) begin
                        litedramcore_sdram_choose_cmd_grant <= 1'd1;
                    end else begin
                        if (litedramcore_sdram_choose_cmd_request[2]) begin
                            litedramcore_sdram_choose_cmd_grant <= 2'd2;
                        end else begin
                            if (litedramcore_sdram_choose_cmd_request[3]) begin
                                litedramcore_sdram_choose_cmd_grant <= 2'd3;
                            end else begin
                                if (litedramcore_sdram_choose_cmd_request[4]) begin
                                    litedramcore_sdram_choose_cmd_grant <= 3'd4;
                                end else begin
                                    if (litedramcore_sdram_choose_cmd_request[5]) begin
                                        litedramcore_sdram_choose_cmd_grant <= 3'd5;
                                    end else begin
                                        if (litedramcore_sdram_choose_cmd_request[6]) begin
                                            litedramcore_sdram_choose_cmd_grant <= 3'd6;
                                        end
                                    end
                                end
                            end
                        end
                    end
                end
            end
        endcase
    end
    if (litedramcore_sdram_choose_req_ce) begin
        case (litedramcore_sdram_choose_req_grant)
            1'd0: begin
                if (litedramcore_sdram_choose_req_request[1]) begin
                    litedramcore_sdram_choose_req_grant <= 1'd1;
                end else begin
                    if (litedramcore_sdram_choose_req_request[2]) begin
                        litedramcore_sdram_choose_req_grant <= 2'd2;
                    end else begin
                        if (litedramcore_sdram_choose_req_request[3]) begin
                            litedramcore_sdram_choose_req_grant <= 2'd3;
                        end else begin
                            if (litedramcore_sdram_choose_req_request[4]) begin
                                litedramcore_sdram_choose_req_grant <= 3'd4;
                            end else begin
                                if (litedramcore_sdram_choose_req_request[5]) begin
                                    litedramcore_sdram_choose_req_grant <= 3'd5;
                                end else begin
                                    if (litedramcore_sdram_choose_req_request[6]) begin
                                        litedramcore_sdram_choose_req_grant <= 3'd6;
                                    end else begin
                                        if (litedramcore_sdram_choose_req_request[7]) begin
                                            litedramcore_sdram_choose_req_grant <= 3'd7;
                                        end
                                    end
                                end
                            end
                        end
                    end
                end
            end
            1'd1: begin
                if (litedramcore_sdram_choose_req_request[2]) begin
                    litedramcore_sdram_choose_req_grant <= 2'd2;
                end else begin
                    if (litedramcore_sdram_choose_req_request[3]) begin
                        litedramcore_sdram_choose_req_grant <= 2'd3;
                    end else begin
                        if (litedramcore_sdram_choose_req_request[4]) begin
                            litedramcore_sdram_choose_req_grant <= 3'd4;
                        end else begin
                            if (litedramcore_sdram_choose_req_request[5]) begin
                                litedramcore_sdram_choose_req_grant <= 3'd5;
                            end else begin
                                if (litedramcore_sdram_choose_req_request[6]) begin
                                    litedramcore_sdram_choose_req_grant <= 3'd6;
                                end else begin
                                    if (litedramcore_sdram_choose_req_request[7]) begin
                                        litedramcore_sdram_choose_req_grant <= 3'd7;
                                    end else begin
                                        if (litedramcore_sdram_choose_req_request[0]) begin
                                            litedramcore_sdram_choose_req_grant <= 1'd0;
                                        end
                                    end
                                end
                            end
                        end
                    end
                end
            end
            2'd2: begin
                if (litedramcore_sdram_choose_req_request[3]) begin
                    litedramcore_sdram_choose_req_grant <= 2'd3;
                end else begin
                    if (litedramcore_sdram_choose_req_request[4]) begin
                        litedramcore_sdram_choose_req_grant <= 3'd4;
                    end else begin
                        if (litedramcore_sdram_choose_req_request[5]) begin
                            litedramcore_sdram_choose_req_grant <= 3'd5;
                        end else begin
                            if (litedramcore_sdram_choose_req_request[6]) begin
                                litedramcore_sdram_choose_req_grant <= 3'd6;
                            end else begin
                                if (litedramcore_sdram_choose_req_request[7]) begin
                                    litedramcore_sdram_choose_req_grant <= 3'd7;
                                end else begin
                                    if (litedramcore_sdram_choose_req_request[0]) begin
                                        litedramcore_sdram_choose_req_grant <= 1'd0;
                                    end else begin
                                        if (litedramcore_sdram_choose_req_request[1]) begin
                                            litedramcore_sdram_choose_req_grant <= 1'd1;
                                        end
                                    end
                                end
                            end
                        end
                    end
                end
            end
            2'd3: begin
                if (litedramcore_sdram_choose_req_request[4]) begin
                    litedramcore_sdram_choose_req_grant <= 3'd4;
                end else begin
                    if (litedramcore_sdram_choose_req_request[5]) begin
                        litedramcore_sdram_choose_req_grant <= 3'd5;
                    end else begin
                        if (litedramcore_sdram_choose_req_request[6]) begin
                            litedramcore_sdram_choose_req_grant <= 3'd6;
                        end else begin
                            if (litedramcore_sdram_choose_req_request[7]) begin
                                litedramcore_sdram_choose_req_grant <= 3'd7;
                            end else begin
                                if (litedramcore_sdram_choose_req_request[0]) begin
                                    litedramcore_sdram_choose_req_grant <= 1'd0;
                                end else begin
                                    if (litedramcore_sdram_choose_req_request[1]) begin
                                        litedramcore_sdram_choose_req_grant <= 1'd1;
                                    end else begin
                                        if (litedramcore_sdram_choose_req_request[2]) begin
                                            litedramcore_sdram_choose_req_grant <= 2'd2;
                                        end
                                    end
                                end
                            end
                        end
                    end
                end
            end
            3'd4: begin
                if (litedramcore_sdram_choose_req_request[5]) begin
                    litedramcore_sdram_choose_req_grant <= 3'd5;
                end else begin
                    if (litedramcore_sdram_choose_req_request[6]) begin
                        litedramcore_sdram_choose_req_grant <= 3'd6;
                    end else begin
                        if (litedramcore_sdram_choose_req_request[7]) begin
                            litedramcore_sdram_choose_req_grant <= 3'd7;
                        end else begin
                            if (litedramcore_sdram_choose_req_request[0]) begin
                                litedramcore_sdram_choose_req_grant <= 1'd0;
                            end else begin
                                if (litedramcore_sdram_choose_req_request[1]) begin
                                    litedramcore_sdram_choose_req_grant <= 1'd1;
                                end else begin
                                    if (litedramcore_sdram_choose_req_request[2]) begin
                                        litedramcore_sdram_choose_req_grant <= 2'd2;
                                    end else begin
                                        if (litedramcore_sdram_choose_req_request[3]) begin
                                            litedramcore_sdram_choose_req_grant <= 2'd3;
                                        end
                                    end
                                end
                            end
                        end
                    end
                end
            end
            3'd5: begin
                if (litedramcore_sdram_choose_req_request[6]) begin
                    litedramcore_sdram_choose_req_grant <= 3'd6;
                end else begin
                    if (litedramcore_sdram_choose_req_request[7]) begin
                        litedramcore_sdram_choose_req_grant <= 3'd7;
                    end else begin
                        if (litedramcore_sdram_choose_req_request[0]) begin
                            litedramcore_sdram_choose_req_grant <= 1'd0;
                        end else begin
                            if (litedramcore_sdram_choose_req_request[1]) begin
                                litedramcore_sdram_choose_req_grant <= 1'd1;
                            end else begin
                                if (litedramcore_sdram_choose_req_request[2]) begin
                                    litedramcore_sdram_choose_req_grant <= 2'd2;
                                end else begin
                                    if (litedramcore_sdram_choose_req_request[3]) begin
                                        litedramcore_sdram_choose_req_grant <= 2'd3;
                                    end else begin
                                        if (litedramcore_sdram_choose_req_request[4]) begin
                                            litedramcore_sdram_choose_req_grant <= 3'd4;
                                        end
                                    end
                                end
                            end
                        end
                    end
                end
            end
            3'd6: begin
                if (litedramcore_sdram_choose_req_request[7]) begin
                    litedramcore_sdram_choose_req_grant <= 3'd7;
                end else begin
                    if (litedramcore_sdram_choose_req_request[0]) begin
                        litedramcore_sdram_choose_req_grant <= 1'd0;
                    end else begin
                        if (litedramcore_sdram_choose_req_request[1]) begin
                            litedramcore_sdram_choose_req_grant <= 1'd1;
                        end else begin
                            if (litedramcore_sdram_choose_req_request[2]) begin
                                litedramcore_sdram_choose_req_grant <= 2'd2;
                            end else begin
                                if (litedramcore_sdram_choose_req_request[3]) begin
                                    litedramcore_sdram_choose_req_grant <= 2'd3;
                                end else begin
                                    if (litedramcore_sdram_choose_req_request[4]) begin
                                        litedramcore_sdram_choose_req_grant <= 3'd4;
                                    end else begin
                                        if (litedramcore_sdram_choose_req_request[5]) begin
                                            litedramcore_sdram_choose_req_grant <= 3'd5;
                                        end
                                    end
                                end
                            end
                        end
                    end
                end
            end
            3'd7: begin
                if (litedramcore_sdram_choose_req_request[0]) begin
                    litedramcore_sdram_choose_req_grant <= 1'd0;
                end else begin
                    if (litedramcore_sdram_choose_req_request[1]) begin
                        litedramcore_sdram_choose_req_grant <= 1'd1;
                    end else begin
                        if (litedramcore_sdram_choose_req_request[2]) begin
                            litedramcore_sdram_choose_req_grant <= 2'd2;
                        end else begin
                            if (litedramcore_sdram_choose_req_request[3]) begin
                                litedramcore_sdram_choose_req_grant <= 2'd3;
                            end else begin
                                if (litedramcore_sdram_choose_req_request[4]) begin
                                    litedramcore_sdram_choose_req_grant <= 3'd4;
                                end else begin
                                    if (litedramcore_sdram_choose_req_request[5]) begin
                                        litedramcore_sdram_choose_req_grant <= 3'd5;
                                    end else begin
                                        if (litedramcore_sdram_choose_req_request[6]) begin
                                            litedramcore_sdram_choose_req_grant <= 3'd6;
                                        end
                                    end
                                end
                            end
                        end
                    end
                end
            end
        endcase
    end
    litedramcore_sdram_dfi_p0_cs_n <= 1'd0;
    litedramcore_sdram_dfi_p0_bank <= self0;
    litedramcore_sdram_dfi_p0_address <= self1;
    litedramcore_sdram_dfi_p0_cas_n <= (~self2);
    litedramcore_sdram_dfi_p0_ras_n <= (~self3);
    litedramcore_sdram_dfi_p0_we_n <= (~self4);
    litedramcore_sdram_dfi_p0_rddata_en <= self5;
    litedramcore_sdram_dfi_p0_wrdata_en <= self6;
    litedramcore_sdram_dfi_p1_cs_n <= 1'd0;
    litedramcore_sdram_dfi_p1_bank <= self7;
    litedramcore_sdram_dfi_p1_address <= self8;
    litedramcore_sdram_dfi_p1_cas_n <= (~self9);
    litedramcore_sdram_dfi_p1_ras_n <= (~self10);
    litedramcore_sdram_dfi_p1_we_n <= (~self11);
    litedramcore_sdram_dfi_p1_rddata_en <= self12;
    litedramcore_sdram_dfi_p1_wrdata_en <= self13;
    litedramcore_sdram_dfi_p2_cs_n <= 1'd0;
    litedramcore_sdram_dfi_p2_bank <= self14;
    litedramcore_sdram_dfi_p2_address <= self15;
    litedramcore_sdram_dfi_p2_cas_n <= (~self16);
    litedramcore_sdram_dfi_p2_ras_n <= (~self17);
    litedramcore_sdram_dfi_p2_we_n <= (~self18);
    litedramcore_sdram_dfi_p2_rddata_en <= self19;
    litedramcore_sdram_dfi_p2_wrdata_en <= self20;
    litedramcore_sdram_dfi_p3_cs_n <= 1'd0;
    litedramcore_sdram_dfi_p3_bank <= self21;
    litedramcore_sdram_dfi_p3_address <= self22;
    litedramcore_sdram_dfi_p3_cas_n <= (~self23);
    litedramcore_sdram_dfi_p3_ras_n <= (~self24);
    litedramcore_sdram_dfi_p3_we_n <= (~self25);
    litedramcore_sdram_dfi_p3_rddata_en <= self26;
    litedramcore_sdram_dfi_p3_wrdata_en <= self27;
    if (litedramcore_sdram_trrdcon_valid) begin
        litedramcore_sdram_trrdcon_count <= 2'd2;
        if (1'd0) begin
            litedramcore_sdram_trrdcon_ready <= 1'd1;
        end else begin
            litedramcore_sdram_trrdcon_ready <= 1'd0;
        end
    end else begin
        if ((~litedramcore_sdram_trrdcon_ready)) begin
            litedramcore_sdram_trrdcon_count <= (litedramcore_sdram_trrdcon_count - 1'd1);
            if ((litedramcore_sdram_trrdcon_count == 1'd1)) begin
                litedramcore_sdram_trrdcon_ready <= 1'd1;
            end
        end
    end
    litedramcore_sdram_tfawcon_window <= {litedramcore_sdram_tfawcon_window, litedramcore_sdram_tfawcon_valid};
    if ((litedramcore_sdram_tfawcon_count < 3'd4)) begin
        if ((litedramcore_sdram_tfawcon_count == 2'd3)) begin
            litedramcore_sdram_tfawcon_ready <= (~litedramcore_sdram_tfawcon_valid);
        end else begin
            litedramcore_sdram_tfawcon_ready <= 1'd1;
        end
    end
    if (litedramcore_sdram_tccdcon_valid) begin
        litedramcore_sdram_tccdcon_count <= 1'd0;
        if (1'd1) begin
            litedramcore_sdram_tccdcon_ready <= 1'd1;
        end else begin
            litedramcore_sdram_tccdcon_ready <= 1'd0;
        end
    end else begin
        if ((~litedramcore_sdram_tccdcon_ready)) begin
            litedramcore_sdram_tccdcon_count <= (litedramcore_sdram_tccdcon_count - 1'd1);
            if ((litedramcore_sdram_tccdcon_count == 1'd1)) begin
                litedramcore_sdram_tccdcon_ready <= 1'd1;
            end
        end
    end
    if (litedramcore_sdram_twtrcon_valid) begin
        litedramcore_sdram_twtrcon_count <= 3'd5;
        if (1'd0) begin
            litedramcore_sdram_twtrcon_ready <= 1'd1;
        end else begin
            litedramcore_sdram_twtrcon_ready <= 1'd0;
        end
    end else begin
        if ((~litedramcore_sdram_twtrcon_ready)) begin
            litedramcore_sdram_twtrcon_count <= (litedramcore_sdram_twtrcon_count - 1'd1);
            if ((litedramcore_sdram_twtrcon_count == 1'd1)) begin
                litedramcore_sdram_twtrcon_ready <= 1'd1;
            end
        end
    end
    litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state;
    litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_sdram_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_sdram_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_sdram_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_sdram_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_sdram_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_sdram_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_sdram_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_sdram_interface_bank7_wdata_ready));
    litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0;
    litedramcore_new_master_wdata_ready2 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd1) & litedramcore_sdram_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd1) & litedramcore_sdram_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd1) & litedramcore_sdram_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd1) & litedramcore_sdram_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd1) & litedramcore_sdram_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd1) & litedramcore_sdram_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd1) & litedramcore_sdram_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd1) & litedramcore_sdram_interface_bank7_wdata_ready));
    litedramcore_new_master_wdata_ready3 <= litedramcore_new_master_wdata_ready2;
    litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_sdram_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_sdram_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_sdram_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_sdram_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_sdram_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_sdram_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_sdram_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_sdram_interface_bank7_rdata_valid));
    litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0;
    litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1;
    litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2;
    litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3;
    litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4;
    litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5;
    litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6;
    litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7;
    litedramcore_new_master_rdata_valid9 <= litedramcore_new_master_rdata_valid8;
    litedramcore_new_master_rdata_valid10 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd1) & litedramcore_sdram_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd1) & litedramcore_sdram_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd1) & litedramcore_sdram_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd1) & litedramcore_sdram_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd1) & litedramcore_sdram_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd1) & litedramcore_sdram_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd1) & litedramcore_sdram_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd1) & litedramcore_sdram_interface_bank7_rdata_valid));
    litedramcore_new_master_rdata_valid11 <= litedramcore_new_master_rdata_valid10;
    litedramcore_new_master_rdata_valid12 <= litedramcore_new_master_rdata_valid11;
    litedramcore_new_master_rdata_valid13 <= litedramcore_new_master_rdata_valid12;
    litedramcore_new_master_rdata_valid14 <= litedramcore_new_master_rdata_valid13;
    litedramcore_new_master_rdata_valid15 <= litedramcore_new_master_rdata_valid14;
    litedramcore_new_master_rdata_valid16 <= litedramcore_new_master_rdata_valid15;
    litedramcore_new_master_rdata_valid17 <= litedramcore_new_master_rdata_valid16;
    litedramcore_new_master_rdata_valid18 <= litedramcore_new_master_rdata_valid17;
    litedramcore_new_master_rdata_valid19 <= litedramcore_new_master_rdata_valid18;
    if (user_port_litedramnativeportconverter_wdata_finished) begin
        user_port_litedramnativeportconverter_read_lock <= 1'd0;
        user_port_litedramnativeportconverter_read_unlocked <= 1'd1;
    end else begin
        if (((user_port_litedramnativeportconverter_rw_collision & (~user_port_port_cmd_valid)) & (~user_port_litedramnativeportconverter_read_unlocked))) begin
            user_port_litedramnativeportconverter_read_lock <= 1'd1;
        end
    end
    if ((user_port_new_port_cmd_valid & user_port_new_port_cmd_ready)) begin
        user_port_litedramnativeportconverter_read_unlocked <= 1'd0;
    end
    if ((user_port_litedramnativeportconverter_rdata_converter_source_valid & user_port_litedramnativeportconverter_rdata_converter_source_ready)) begin
        user_port_litedramnativeportconverter_rdata_chunk <= {user_port_litedramnativeportconverter_rdata_chunk[6:0], user_port_litedramnativeportconverter_rdata_chunk[7]};
    end
    if ((user_port_litedramnativeportconverter_wdata_converter_sink_valid & user_port_litedramnativeportconverter_wdata_converter_sink_ready)) begin
        user_port_litedramnativeportconverter_wdata_chunk <= {user_port_litedramnativeportconverter_wdata_chunk[6:0], user_port_litedramnativeportconverter_wdata_chunk[7]};
    end
    if (((user_port_litedramnativeportconverter_cmd_buffer_source_valid & user_port_litedramnativeportconverter_cmd_buffer_source_payload_we) & user_port_litedramnativeportconverter_wdata_chunk[7])) begin
        user_port_litedramnativeportconverter_wdata_sel <= {{4{user_port_litedramnativeportconverter_cmd_buffer_source_payload_sel[7]}}, {4{user_port_litedramnativeportconverter_cmd_buffer_source_payload_sel[6]}}, {4{user_port_litedramnativeportconverter_cmd_buffer_source_payload_sel[5]}}, {4{user_port_litedramnativeportconverter_cmd_buffer_source_payload_sel[4]}}, {4{user_port_litedramnativeportconverter_cmd_buffer_source_payload_sel[3]}}, {4{user_port_litedramnativeportconverter_cmd_buffer_source_payload_sel[2]}}, {4{user_port_litedramnativeportconverter_cmd_buffer_source_payload_sel[1]}}, {4{user_port_litedramnativeportconverter_cmd_buffer_source_payload_sel[0]}}};
    end
    litedramcore_state <= litedramcore_next_state;
    if (user_port_litedramnativeportconverter_cmd_addr_litedramcore_next_value_ce0) begin
        user_port_litedramnativeportconverter_cmd_addr <= user_port_litedramnativeportconverter_cmd_addr_litedramcore_next_value0;
    end
    if (user_port_litedramnativeportconverter_cmd_we_litedramcore_next_value_ce1) begin
        user_port_litedramnativeportconverter_cmd_we <= user_port_litedramnativeportconverter_cmd_we_litedramcore_next_value1;
    end
    if (user_port_litedramnativeportconverter_cmd_last_litedramcore_next_value_ce2) begin
        user_port_litedramnativeportconverter_cmd_last <= user_port_litedramnativeportconverter_cmd_last_litedramcore_next_value2;
    end
    if (user_port_litedramnativeportconverter_sel_litedramcore_next_value_ce3) begin
        user_port_litedramnativeportconverter_sel <= user_port_litedramnativeportconverter_sel_litedramcore_next_value3;
    end
    if (((user_port_litedramnativeportconverter_rdata_fifo_syncfifo_we & user_port_litedramnativeportconverter_rdata_fifo_syncfifo_writable) & (~user_port_litedramnativeportconverter_rdata_fifo_replace))) begin
        if ((user_port_litedramnativeportconverter_rdata_fifo_produce == 3'd6)) begin
            user_port_litedramnativeportconverter_rdata_fifo_produce <= 1'd0;
        end else begin
            user_port_litedramnativeportconverter_rdata_fifo_produce <= (user_port_litedramnativeportconverter_rdata_fifo_produce + 1'd1);
        end
    end
    if (user_port_litedramnativeportconverter_rdata_fifo_do_read) begin
        if ((user_port_litedramnativeportconverter_rdata_fifo_consume == 3'd6)) begin
            user_port_litedramnativeportconverter_rdata_fifo_consume <= 1'd0;
        end else begin
            user_port_litedramnativeportconverter_rdata_fifo_consume <= (user_port_litedramnativeportconverter_rdata_fifo_consume + 1'd1);
        end
    end
    if (((user_port_litedramnativeportconverter_rdata_fifo_syncfifo_we & user_port_litedramnativeportconverter_rdata_fifo_syncfifo_writable) & (~user_port_litedramnativeportconverter_rdata_fifo_replace))) begin
        if ((~user_port_litedramnativeportconverter_rdata_fifo_do_read)) begin
            user_port_litedramnativeportconverter_rdata_fifo_level <= (user_port_litedramnativeportconverter_rdata_fifo_level + 1'd1);
        end
    end else begin
        if (user_port_litedramnativeportconverter_rdata_fifo_do_read) begin
            user_port_litedramnativeportconverter_rdata_fifo_level <= (user_port_litedramnativeportconverter_rdata_fifo_level - 1'd1);
        end
    end
    if ((user_port_litedramnativeportconverter_rdata_converter_converter_source_valid & user_port_litedramnativeportconverter_rdata_converter_converter_source_ready)) begin
        if (user_port_litedramnativeportconverter_rdata_converter_converter_last) begin
            user_port_litedramnativeportconverter_rdata_converter_converter_mux <= 1'd0;
        end else begin
            user_port_litedramnativeportconverter_rdata_converter_converter_mux <= (user_port_litedramnativeportconverter_rdata_converter_converter_mux + 1'd1);
        end
    end
    if (user_port_litedramnativeportconverter_wdata_converter_converter_source_ready) begin
        user_port_litedramnativeportconverter_wdata_converter_converter_strobe_all <= 1'd0;
    end
    if (user_port_litedramnativeportconverter_wdata_converter_converter_load_part) begin
        if (((user_port_litedramnativeportconverter_wdata_converter_converter_demux == 3'd7) | user_port_litedramnativeportconverter_wdata_converter_converter_sink_last)) begin
            user_port_litedramnativeportconverter_wdata_converter_converter_demux <= 1'd0;
            user_port_litedramnativeportconverter_wdata_converter_converter_strobe_all <= 1'd1;
        end else begin
            user_port_litedramnativeportconverter_wdata_converter_converter_demux <= (user_port_litedramnativeportconverter_wdata_converter_converter_demux + 1'd1);
        end
    end
    if ((user_port_litedramnativeportconverter_wdata_converter_converter_source_valid & user_port_litedramnativeportconverter_wdata_converter_converter_source_ready)) begin
        if ((user_port_litedramnativeportconverter_wdata_converter_converter_sink_valid & user_port_litedramnativeportconverter_wdata_converter_converter_sink_ready)) begin
            user_port_litedramnativeportconverter_wdata_converter_converter_source_first <= user_port_litedramnativeportconverter_wdata_converter_converter_sink_first;
            user_port_litedramnativeportconverter_wdata_converter_converter_source_last <= user_port_litedramnativeportconverter_wdata_converter_converter_sink_last;
        end else begin
            user_port_litedramnativeportconverter_wdata_converter_converter_source_first <= 1'd0;
            user_port_litedramnativeportconverter_wdata_converter_converter_source_last <= 1'd0;
        end
    end else begin
        if ((user_port_litedramnativeportconverter_wdata_converter_converter_sink_valid & user_port_litedramnativeportconverter_wdata_converter_converter_sink_ready)) begin
            user_port_litedramnativeportconverter_wdata_converter_converter_source_first <= (user_port_litedramnativeportconverter_wdata_converter_converter_sink_first | user_port_litedramnativeportconverter_wdata_converter_converter_source_first);
            user_port_litedramnativeportconverter_wdata_converter_converter_source_last <= (user_port_litedramnativeportconverter_wdata_converter_converter_sink_last | user_port_litedramnativeportconverter_wdata_converter_converter_source_last);
        end
    end
    if (user_port_litedramnativeportconverter_wdata_converter_converter_load_part) begin
        case (user_port_litedramnativeportconverter_wdata_converter_converter_demux)
            1'd0: begin
                user_port_litedramnativeportconverter_wdata_converter_converter_source_payload_data[35:0] <= user_port_litedramnativeportconverter_wdata_converter_converter_sink_payload_data;
            end
            1'd1: begin
                user_port_litedramnativeportconverter_wdata_converter_converter_source_payload_data[71:36] <= user_port_litedramnativeportconverter_wdata_converter_converter_sink_payload_data;
            end
            2'd2: begin
                user_port_litedramnativeportconverter_wdata_converter_converter_source_payload_data[107:72] <= user_port_litedramnativeportconverter_wdata_converter_converter_sink_payload_data;
            end
            2'd3: begin
                user_port_litedramnativeportconverter_wdata_converter_converter_source_payload_data[143:108] <= user_port_litedramnativeportconverter_wdata_converter_converter_sink_payload_data;
            end
            3'd4: begin
                user_port_litedramnativeportconverter_wdata_converter_converter_source_payload_data[179:144] <= user_port_litedramnativeportconverter_wdata_converter_converter_sink_payload_data;
            end
            3'd5: begin
                user_port_litedramnativeportconverter_wdata_converter_converter_source_payload_data[215:180] <= user_port_litedramnativeportconverter_wdata_converter_converter_sink_payload_data;
            end
            3'd6: begin
                user_port_litedramnativeportconverter_wdata_converter_converter_source_payload_data[251:216] <= user_port_litedramnativeportconverter_wdata_converter_converter_sink_payload_data;
            end
            3'd7: begin
                user_port_litedramnativeportconverter_wdata_converter_converter_source_payload_data[287:252] <= user_port_litedramnativeportconverter_wdata_converter_converter_sink_payload_data;
            end
        endcase
    end
    if (user_port_litedramnativeportconverter_wdata_converter_converter_load_part) begin
        user_port_litedramnativeportconverter_wdata_converter_converter_source_payload_valid_token_count <= (user_port_litedramnativeportconverter_wdata_converter_converter_demux + 1'd1);
    end
    if (((user_port_litedramnativeportconverter_wdata_fifo_syncfifo_we & user_port_litedramnativeportconverter_wdata_fifo_syncfifo_writable) & (~user_port_litedramnativeportconverter_wdata_fifo_replace))) begin
        if ((user_port_litedramnativeportconverter_wdata_fifo_produce == 3'd6)) begin
            user_port_litedramnativeportconverter_wdata_fifo_produce <= 1'd0;
        end else begin
            user_port_litedramnativeportconverter_wdata_fifo_produce <= (user_port_litedramnativeportconverter_wdata_fifo_produce + 1'd1);
        end
    end
    if (user_port_litedramnativeportconverter_wdata_fifo_do_read) begin
        if ((user_port_litedramnativeportconverter_wdata_fifo_consume == 3'd6)) begin
            user_port_litedramnativeportconverter_wdata_fifo_consume <= 1'd0;
        end else begin
            user_port_litedramnativeportconverter_wdata_fifo_consume <= (user_port_litedramnativeportconverter_wdata_fifo_consume + 1'd1);
        end
    end
    if (((user_port_litedramnativeportconverter_wdata_fifo_syncfifo_we & user_port_litedramnativeportconverter_wdata_fifo_syncfifo_writable) & (~user_port_litedramnativeportconverter_wdata_fifo_replace))) begin
        if ((~user_port_litedramnativeportconverter_wdata_fifo_do_read)) begin
            user_port_litedramnativeportconverter_wdata_fifo_level <= (user_port_litedramnativeportconverter_wdata_fifo_level + 1'd1);
        end
    end else begin
        if (user_port_litedramnativeportconverter_wdata_fifo_do_read) begin
            user_port_litedramnativeportconverter_wdata_fifo_level <= (user_port_litedramnativeportconverter_wdata_fifo_level - 1'd1);
        end
    end
    if (((~user_port_litedramnativeportconverter_wdata_buffer_pipe_valid_source_valid) | user_port_litedramnativeportconverter_wdata_buffer_pipe_valid_source_ready)) begin
        user_port_litedramnativeportconverter_wdata_buffer_pipe_valid_source_valid <= user_port_litedramnativeportconverter_wdata_buffer_pipe_valid_sink_valid;
        user_port_litedramnativeportconverter_wdata_buffer_pipe_valid_source_first <= user_port_litedramnativeportconverter_wdata_buffer_pipe_valid_sink_first;
        user_port_litedramnativeportconverter_wdata_buffer_pipe_valid_source_last <= user_port_litedramnativeportconverter_wdata_buffer_pipe_valid_sink_last;
        user_port_litedramnativeportconverter_wdata_buffer_pipe_valid_source_payload_data <= user_port_litedramnativeportconverter_wdata_buffer_pipe_valid_sink_payload_data;
        user_port_litedramnativeportconverter_wdata_buffer_pipe_valid_source_payload_we <= user_port_litedramnativeportconverter_wdata_buffer_pipe_valid_sink_payload_we;
    end
    if (litedramcore_roundrobin0_ce) begin
        case (litedramcore_roundrobin0_grant)
            1'd0: begin
                if (litedramcore_roundrobin0_request[1]) begin
                    litedramcore_roundrobin0_grant <= 1'd1;
                end
            end
            1'd1: begin
                if (litedramcore_roundrobin0_request[0]) begin
                    litedramcore_roundrobin0_grant <= 1'd0;
                end
            end
        endcase
    end
    if (litedramcore_roundrobin1_ce) begin
        case (litedramcore_roundrobin1_grant)
            1'd0: begin
                if (litedramcore_roundrobin1_request[1]) begin
                    litedramcore_roundrobin1_grant <= 1'd1;
                end
            end
            1'd1: begin
                if (litedramcore_roundrobin1_request[0]) begin
                    litedramcore_roundrobin1_grant <= 1'd0;
                end
            end
        endcase
    end
    if (litedramcore_roundrobin2_ce) begin
        case (litedramcore_roundrobin2_grant)
            1'd0: begin
                if (litedramcore_roundrobin2_request[1]) begin
                    litedramcore_roundrobin2_grant <= 1'd1;
                end
            end
            1'd1: begin
                if (litedramcore_roundrobin2_request[0]) begin
                    litedramcore_roundrobin2_grant <= 1'd0;
                end
            end
        endcase
    end
    if (litedramcore_roundrobin3_ce) begin
        case (litedramcore_roundrobin3_grant)
            1'd0: begin
                if (litedramcore_roundrobin3_request[1]) begin
                    litedramcore_roundrobin3_grant <= 1'd1;
                end
            end
            1'd1: begin
                if (litedramcore_roundrobin3_request[0]) begin
                    litedramcore_roundrobin3_grant <= 1'd0;
                end
            end
        endcase
    end
    if (litedramcore_roundrobin4_ce) begin
        case (litedramcore_roundrobin4_grant)
            1'd0: begin
                if (litedramcore_roundrobin4_request[1]) begin
                    litedramcore_roundrobin4_grant <= 1'd1;
                end
            end
            1'd1: begin
                if (litedramcore_roundrobin4_request[0]) begin
                    litedramcore_roundrobin4_grant <= 1'd0;
                end
            end
        endcase
    end
    if (litedramcore_roundrobin5_ce) begin
        case (litedramcore_roundrobin5_grant)
            1'd0: begin
                if (litedramcore_roundrobin5_request[1]) begin
                    litedramcore_roundrobin5_grant <= 1'd1;
                end
            end
            1'd1: begin
                if (litedramcore_roundrobin5_request[0]) begin
                    litedramcore_roundrobin5_grant <= 1'd0;
                end
            end
        endcase
    end
    if (litedramcore_roundrobin6_ce) begin
        case (litedramcore_roundrobin6_grant)
            1'd0: begin
                if (litedramcore_roundrobin6_request[1]) begin
                    litedramcore_roundrobin6_grant <= 1'd1;
                end
            end
            1'd1: begin
                if (litedramcore_roundrobin6_request[0]) begin
                    litedramcore_roundrobin6_grant <= 1'd0;
                end
            end
        endcase
    end
    if (litedramcore_roundrobin7_ce) begin
        case (litedramcore_roundrobin7_grant)
            1'd0: begin
                if (litedramcore_roundrobin7_request[1]) begin
                    litedramcore_roundrobin7_grant <= 1'd1;
                end
            end
            1'd1: begin
                if (litedramcore_roundrobin7_request[0]) begin
                    litedramcore_roundrobin7_grant <= 1'd0;
                end
            end
        endcase
    end
    litedramcore_adr_offset_r <= litedramcore_wb_sdram_adr[2:0];
    fullmemorywe_state <= fullmemorywe_next_state;
    litedramwishbone2native0_state <= litedramwishbone2native0_next_state;
    if (litedramcore_aborted_litedramwishbone2native0_next_value_ce) begin
        litedramcore_aborted <= litedramcore_aborted_litedramwishbone2native0_next_value;
    end
    litedramwishbone2native1_state <= litedramwishbone2native1_next_state;
    if (wishbone2native_aborted_litedramwishbone2native1_next_value_ce) begin
        wishbone2native_aborted <= wishbone2native_aborted_litedramwishbone2native1_next_value;
    end
    wishbone2csr_state <= wishbone2csr_next_state;
    if (interface1_dat_w_wishbone2csr_next_value_ce0) begin
        interface1_dat_w <= interface1_dat_w_wishbone2csr_next_value0;
    end
    if (interface1_adr_wishbone2csr_next_value_ce1) begin
        interface1_adr <= interface1_adr_wishbone2csr_next_value1;
    end
    if (interface1_re_wishbone2csr_next_value_ce2) begin
        interface1_re <= interface1_re_wishbone2csr_next_value2;
    end
    if (interface1_we_wishbone2csr_next_value_ce3) begin
        interface1_we <= interface1_we_wishbone2csr_next_value3;
    end
    interface0_bank_bus_dat_r <= 1'd0;
    if (csrbank0_sel) begin
        case (interface0_bank_bus_adr[8:0])
            1'd0: begin
                interface0_bank_bus_dat_r <= csrbank0_reset0_w;
            end
            1'd1: begin
                interface0_bank_bus_dat_r <= csrbank0_scratch0_w;
            end
            2'd2: begin
                interface0_bank_bus_dat_r <= csrbank0_bus_errors_w;
            end
        endcase
    end
    if (csrbank0_reset0_re) begin
        litedramcore_reset_storage <= csrbank0_reset0_r;
    end
    litedramcore_reset_re <= csrbank0_reset0_re;
    if (csrbank0_scratch0_re) begin
        litedramcore_scratch_storage <= csrbank0_scratch0_r;
    end
    litedramcore_scratch_re <= csrbank0_scratch0_re;
    litedramcore_bus_errors_re <= csrbank0_bus_errors_re;
    interface1_bank_bus_dat_r <= 1'd0;
    if (csrbank1_sel) begin
        case (interface1_bank_bus_adr[8:0])
            1'd0: begin
                interface1_bank_bus_dat_r <= csrbank1_init_done0_w;
            end
            1'd1: begin
                interface1_bank_bus_dat_r <= csrbank1_init_error0_w;
            end
        endcase
    end
    if (csrbank1_init_done0_re) begin
        init_done_storage <= csrbank1_init_done0_r;
    end
    init_done_re <= csrbank1_init_done0_re;
    if (csrbank1_init_error0_re) begin
        init_error_storage <= csrbank1_init_error0_r;
    end
    init_error_re <= csrbank1_init_error0_re;
    interface2_bank_bus_dat_r <= 1'd0;
    if (csrbank2_sel) begin
        case (interface2_bank_bus_adr[8:0])
            1'd0: begin
                interface2_bank_bus_dat_r <= csrbank2_rst0_w;
            end
            1'd1: begin
                interface2_bank_bus_dat_r <= csrbank2_dly_sel0_w;
            end
            2'd2: begin
                interface2_bank_bus_dat_r <= csrbank2_half_sys8x_taps0_w;
            end
            2'd3: begin
                interface2_bank_bus_dat_r <= csrbank2_wlevel_en0_w;
            end
            3'd4: begin
                interface2_bank_bus_dat_r <= k7ddrphy_wlevel_strobe_w;
            end
            3'd5: begin
                interface2_bank_bus_dat_r <= k7ddrphy_cdly_rst_w;
            end
            3'd6: begin
                interface2_bank_bus_dat_r <= k7ddrphy_cdly_inc_w;
            end
            3'd7: begin
                interface2_bank_bus_dat_r <= k7ddrphy_rdly_dq_rst_w;
            end
            4'd8: begin
                interface2_bank_bus_dat_r <= k7ddrphy_rdly_dq_inc_w;
            end
            4'd9: begin
                interface2_bank_bus_dat_r <= k7ddrphy_rdly_dq_bitslip_rst_w;
            end
            4'd10: begin
                interface2_bank_bus_dat_r <= k7ddrphy_rdly_dq_bitslip_w;
            end
            4'd11: begin
                interface2_bank_bus_dat_r <= k7ddrphy_wdly_dq_rst_w;
            end
            4'd12: begin
                interface2_bank_bus_dat_r <= k7ddrphy_wdly_dq_inc_w;
            end
            4'd13: begin
                interface2_bank_bus_dat_r <= k7ddrphy_wdly_dqs_rst_w;
            end
            4'd14: begin
                interface2_bank_bus_dat_r <= k7ddrphy_wdly_dqs_inc_w;
            end
            4'd15: begin
                interface2_bank_bus_dat_r <= k7ddrphy_wdly_dq_bitslip_rst_w;
            end
            5'd16: begin
                interface2_bank_bus_dat_r <= k7ddrphy_wdly_dq_bitslip_w;
            end
            5'd17: begin
                interface2_bank_bus_dat_r <= csrbank2_rdphase0_w;
            end
            5'd18: begin
                interface2_bank_bus_dat_r <= csrbank2_wrphase0_w;
            end
        endcase
    end
    if (csrbank2_rst0_re) begin
        k7ddrphy_rst_storage <= csrbank2_rst0_r;
    end
    k7ddrphy_rst_re <= csrbank2_rst0_re;
    if (csrbank2_dly_sel0_re) begin
        k7ddrphy_dly_sel_storage <= csrbank2_dly_sel0_r;
    end
    k7ddrphy_dly_sel_re <= csrbank2_dly_sel0_re;
    if (csrbank2_half_sys8x_taps0_re) begin
        k7ddrphy_half_sys8x_taps_storage <= csrbank2_half_sys8x_taps0_r;
    end
    k7ddrphy_half_sys8x_taps_re <= csrbank2_half_sys8x_taps0_re;
    if (csrbank2_wlevel_en0_re) begin
        k7ddrphy_wlevel_en_storage <= csrbank2_wlevel_en0_r;
    end
    k7ddrphy_wlevel_en_re <= csrbank2_wlevel_en0_re;
    if (csrbank2_rdphase0_re) begin
        k7ddrphy_rdphase_storage <= csrbank2_rdphase0_r;
    end
    k7ddrphy_rdphase_re <= csrbank2_rdphase0_re;
    if (csrbank2_wrphase0_re) begin
        k7ddrphy_wrphase_storage <= csrbank2_wrphase0_r;
    end
    k7ddrphy_wrphase_re <= csrbank2_wrphase0_re;
    interface3_bank_bus_dat_r <= 1'd0;
    if (csrbank3_sel) begin
        case (interface3_bank_bus_adr[8:0])
            1'd0: begin
                interface3_bank_bus_dat_r <= csrbank3_dfii_control0_w;
            end
            1'd1: begin
                interface3_bank_bus_dat_r <= csrbank3_dfii_pi0_command0_w;
            end
            2'd2: begin
                interface3_bank_bus_dat_r <= litedramcore_sdram_phaseinjector0_command_issue_w;
            end
            2'd3: begin
                interface3_bank_bus_dat_r <= csrbank3_dfii_pi0_address0_w;
            end
            3'd4: begin
                interface3_bank_bus_dat_r <= csrbank3_dfii_pi0_baddress0_w;
            end
            3'd5: begin
                interface3_bank_bus_dat_r <= csrbank3_dfii_pi0_wrdata1_w;
            end
            3'd6: begin
                interface3_bank_bus_dat_r <= csrbank3_dfii_pi0_wrdata0_w;
            end
            3'd7: begin
                interface3_bank_bus_dat_r <= csrbank3_dfii_pi0_rddata1_w;
            end
            4'd8: begin
                interface3_bank_bus_dat_r <= csrbank3_dfii_pi0_rddata0_w;
            end
            4'd9: begin
                interface3_bank_bus_dat_r <= csrbank3_dfii_pi1_command0_w;
            end
            4'd10: begin
                interface3_bank_bus_dat_r <= litedramcore_sdram_phaseinjector1_command_issue_w;
            end
            4'd11: begin
                interface3_bank_bus_dat_r <= csrbank3_dfii_pi1_address0_w;
            end
            4'd12: begin
                interface3_bank_bus_dat_r <= csrbank3_dfii_pi1_baddress0_w;
            end
            4'd13: begin
                interface3_bank_bus_dat_r <= csrbank3_dfii_pi1_wrdata1_w;
            end
            4'd14: begin
                interface3_bank_bus_dat_r <= csrbank3_dfii_pi1_wrdata0_w;
            end
            4'd15: begin
                interface3_bank_bus_dat_r <= csrbank3_dfii_pi1_rddata1_w;
            end
            5'd16: begin
                interface3_bank_bus_dat_r <= csrbank3_dfii_pi1_rddata0_w;
            end
            5'd17: begin
                interface3_bank_bus_dat_r <= csrbank3_dfii_pi2_command0_w;
            end
            5'd18: begin
                interface3_bank_bus_dat_r <= litedramcore_sdram_phaseinjector2_command_issue_w;
            end
            5'd19: begin
                interface3_bank_bus_dat_r <= csrbank3_dfii_pi2_address0_w;
            end
            5'd20: begin
                interface3_bank_bus_dat_r <= csrbank3_dfii_pi2_baddress0_w;
            end
            5'd21: begin
                interface3_bank_bus_dat_r <= csrbank3_dfii_pi2_wrdata1_w;
            end
            5'd22: begin
                interface3_bank_bus_dat_r <= csrbank3_dfii_pi2_wrdata0_w;
            end
            5'd23: begin
                interface3_bank_bus_dat_r <= csrbank3_dfii_pi2_rddata1_w;
            end
            5'd24: begin
                interface3_bank_bus_dat_r <= csrbank3_dfii_pi2_rddata0_w;
            end
            5'd25: begin
                interface3_bank_bus_dat_r <= csrbank3_dfii_pi3_command0_w;
            end
            5'd26: begin
                interface3_bank_bus_dat_r <= litedramcore_sdram_phaseinjector3_command_issue_w;
            end
            5'd27: begin
                interface3_bank_bus_dat_r <= csrbank3_dfii_pi3_address0_w;
            end
            5'd28: begin
                interface3_bank_bus_dat_r <= csrbank3_dfii_pi3_baddress0_w;
            end
            5'd29: begin
                interface3_bank_bus_dat_r <= csrbank3_dfii_pi3_wrdata1_w;
            end
            5'd30: begin
                interface3_bank_bus_dat_r <= csrbank3_dfii_pi3_wrdata0_w;
            end
            5'd31: begin
                interface3_bank_bus_dat_r <= csrbank3_dfii_pi3_rddata1_w;
            end
            6'd32: begin
                interface3_bank_bus_dat_r <= csrbank3_dfii_pi3_rddata0_w;
            end
        endcase
    end
    if (csrbank3_dfii_control0_re) begin
        litedramcore_sdram_storage <= csrbank3_dfii_control0_r;
    end
    litedramcore_sdram_re <= csrbank3_dfii_control0_re;
    if (csrbank3_dfii_pi0_command0_re) begin
        litedramcore_sdram_phaseinjector0_command_storage <= csrbank3_dfii_pi0_command0_r;
    end
    litedramcore_sdram_phaseinjector0_command_re <= csrbank3_dfii_pi0_command0_re;
    if (csrbank3_dfii_pi0_address0_re) begin
        litedramcore_sdram_phaseinjector0_address_storage <= csrbank3_dfii_pi0_address0_r;
    end
    litedramcore_sdram_phaseinjector0_address_re <= csrbank3_dfii_pi0_address0_re;
    if (csrbank3_dfii_pi0_baddress0_re) begin
        litedramcore_sdram_phaseinjector0_baddress_storage <= csrbank3_dfii_pi0_baddress0_r;
    end
    litedramcore_sdram_phaseinjector0_baddress_re <= csrbank3_dfii_pi0_baddress0_re;
    if (csrbank3_dfii_pi0_wrdata1_re) begin
        litedramcore_sdram_phaseinjector0_wrdata_storage[63:32] <= csrbank3_dfii_pi0_wrdata1_r;
    end
    if (csrbank3_dfii_pi0_wrdata0_re) begin
        litedramcore_sdram_phaseinjector0_wrdata_storage[31:0] <= csrbank3_dfii_pi0_wrdata0_r;
    end
    litedramcore_sdram_phaseinjector0_wrdata_re <= csrbank3_dfii_pi0_wrdata0_re;
    litedramcore_sdram_phaseinjector0_rddata_re <= csrbank3_dfii_pi0_rddata0_re;
    if (csrbank3_dfii_pi1_command0_re) begin
        litedramcore_sdram_phaseinjector1_command_storage <= csrbank3_dfii_pi1_command0_r;
    end
    litedramcore_sdram_phaseinjector1_command_re <= csrbank3_dfii_pi1_command0_re;
    if (csrbank3_dfii_pi1_address0_re) begin
        litedramcore_sdram_phaseinjector1_address_storage <= csrbank3_dfii_pi1_address0_r;
    end
    litedramcore_sdram_phaseinjector1_address_re <= csrbank3_dfii_pi1_address0_re;
    if (csrbank3_dfii_pi1_baddress0_re) begin
        litedramcore_sdram_phaseinjector1_baddress_storage <= csrbank3_dfii_pi1_baddress0_r;
    end
    litedramcore_sdram_phaseinjector1_baddress_re <= csrbank3_dfii_pi1_baddress0_re;
    if (csrbank3_dfii_pi1_wrdata1_re) begin
        litedramcore_sdram_phaseinjector1_wrdata_storage[63:32] <= csrbank3_dfii_pi1_wrdata1_r;
    end
    if (csrbank3_dfii_pi1_wrdata0_re) begin
        litedramcore_sdram_phaseinjector1_wrdata_storage[31:0] <= csrbank3_dfii_pi1_wrdata0_r;
    end
    litedramcore_sdram_phaseinjector1_wrdata_re <= csrbank3_dfii_pi1_wrdata0_re;
    litedramcore_sdram_phaseinjector1_rddata_re <= csrbank3_dfii_pi1_rddata0_re;
    if (csrbank3_dfii_pi2_command0_re) begin
        litedramcore_sdram_phaseinjector2_command_storage <= csrbank3_dfii_pi2_command0_r;
    end
    litedramcore_sdram_phaseinjector2_command_re <= csrbank3_dfii_pi2_command0_re;
    if (csrbank3_dfii_pi2_address0_re) begin
        litedramcore_sdram_phaseinjector2_address_storage <= csrbank3_dfii_pi2_address0_r;
    end
    litedramcore_sdram_phaseinjector2_address_re <= csrbank3_dfii_pi2_address0_re;
    if (csrbank3_dfii_pi2_baddress0_re) begin
        litedramcore_sdram_phaseinjector2_baddress_storage <= csrbank3_dfii_pi2_baddress0_r;
    end
    litedramcore_sdram_phaseinjector2_baddress_re <= csrbank3_dfii_pi2_baddress0_re;
    if (csrbank3_dfii_pi2_wrdata1_re) begin
        litedramcore_sdram_phaseinjector2_wrdata_storage[63:32] <= csrbank3_dfii_pi2_wrdata1_r;
    end
    if (csrbank3_dfii_pi2_wrdata0_re) begin
        litedramcore_sdram_phaseinjector2_wrdata_storage[31:0] <= csrbank3_dfii_pi2_wrdata0_r;
    end
    litedramcore_sdram_phaseinjector2_wrdata_re <= csrbank3_dfii_pi2_wrdata0_re;
    litedramcore_sdram_phaseinjector2_rddata_re <= csrbank3_dfii_pi2_rddata0_re;
    if (csrbank3_dfii_pi3_command0_re) begin
        litedramcore_sdram_phaseinjector3_command_storage <= csrbank3_dfii_pi3_command0_r;
    end
    litedramcore_sdram_phaseinjector3_command_re <= csrbank3_dfii_pi3_command0_re;
    if (csrbank3_dfii_pi3_address0_re) begin
        litedramcore_sdram_phaseinjector3_address_storage <= csrbank3_dfii_pi3_address0_r;
    end
    litedramcore_sdram_phaseinjector3_address_re <= csrbank3_dfii_pi3_address0_re;
    if (csrbank3_dfii_pi3_baddress0_re) begin
        litedramcore_sdram_phaseinjector3_baddress_storage <= csrbank3_dfii_pi3_baddress0_r;
    end
    litedramcore_sdram_phaseinjector3_baddress_re <= csrbank3_dfii_pi3_baddress0_re;
    if (csrbank3_dfii_pi3_wrdata1_re) begin
        litedramcore_sdram_phaseinjector3_wrdata_storage[63:32] <= csrbank3_dfii_pi3_wrdata1_r;
    end
    if (csrbank3_dfii_pi3_wrdata0_re) begin
        litedramcore_sdram_phaseinjector3_wrdata_storage[31:0] <= csrbank3_dfii_pi3_wrdata0_r;
    end
    litedramcore_sdram_phaseinjector3_wrdata_re <= csrbank3_dfii_pi3_wrdata0_re;
    litedramcore_sdram_phaseinjector3_rddata_re <= csrbank3_dfii_pi3_rddata0_re;
    interface4_bank_bus_dat_r <= 1'd0;
    if (csrbank4_sel) begin
        case (interface4_bank_bus_adr[8:0])
            1'd0: begin
                interface4_bank_bus_dat_r <= csrbank4_load0_w;
            end
            1'd1: begin
                interface4_bank_bus_dat_r <= csrbank4_reload0_w;
            end
            2'd2: begin
                interface4_bank_bus_dat_r <= csrbank4_en0_w;
            end
            2'd3: begin
                interface4_bank_bus_dat_r <= csrbank4_update_value0_w;
            end
            3'd4: begin
                interface4_bank_bus_dat_r <= csrbank4_value_w;
            end
            3'd5: begin
                interface4_bank_bus_dat_r <= csrbank4_ev_status_w;
            end
            3'd6: begin
                interface4_bank_bus_dat_r <= csrbank4_ev_pending_w;
            end
            3'd7: begin
                interface4_bank_bus_dat_r <= csrbank4_ev_enable0_w;
            end
        endcase
    end
    if (csrbank4_load0_re) begin
        litedramcore_load_storage <= csrbank4_load0_r;
    end
    litedramcore_load_re <= csrbank4_load0_re;
    if (csrbank4_reload0_re) begin
        litedramcore_reload_storage <= csrbank4_reload0_r;
    end
    litedramcore_reload_re <= csrbank4_reload0_re;
    if (csrbank4_en0_re) begin
        litedramcore_en_storage <= csrbank4_en0_r;
    end
    litedramcore_en_re <= csrbank4_en0_re;
    if (csrbank4_update_value0_re) begin
        litedramcore_update_value_storage <= csrbank4_update_value0_r;
    end
    litedramcore_update_value_re <= csrbank4_update_value0_re;
    litedramcore_value_re <= csrbank4_value_re;
    litedramcore_status_re <= csrbank4_ev_status_re;
    if (csrbank4_ev_pending_re) begin
        litedramcore_pending_r <= csrbank4_ev_pending_r;
    end
    litedramcore_pending_re <= csrbank4_ev_pending_re;
    if (csrbank4_ev_enable0_re) begin
        litedramcore_enable_storage <= csrbank4_ev_enable0_r;
    end
    litedramcore_enable_re <= csrbank4_ev_enable0_re;
    interface5_bank_bus_dat_r <= 1'd0;
    if (csrbank5_sel) begin
        case (interface5_bank_bus_adr[8:0])
            1'd0: begin
                interface5_bank_bus_dat_r <= uart_rxtx_w;
            end
            1'd1: begin
                interface5_bank_bus_dat_r <= csrbank5_txfull_w;
            end
            2'd2: begin
                interface5_bank_bus_dat_r <= csrbank5_rxempty_w;
            end
            2'd3: begin
                interface5_bank_bus_dat_r <= csrbank5_ev_status_w;
            end
            3'd4: begin
                interface5_bank_bus_dat_r <= csrbank5_ev_pending_w;
            end
            3'd5: begin
                interface5_bank_bus_dat_r <= csrbank5_ev_enable0_w;
            end
            3'd6: begin
                interface5_bank_bus_dat_r <= csrbank5_txempty_w;
            end
            3'd7: begin
                interface5_bank_bus_dat_r <= csrbank5_rxfull_w;
            end
        endcase
    end
    uart_txfull_re <= csrbank5_txfull_re;
    uart_rxempty_re <= csrbank5_rxempty_re;
    uart_status_re <= csrbank5_ev_status_re;
    if (csrbank5_ev_pending_re) begin
        uart_pending_r <= csrbank5_ev_pending_r;
    end
    uart_pending_re <= csrbank5_ev_pending_re;
    if (csrbank5_ev_enable0_re) begin
        uart_enable_storage <= csrbank5_ev_enable0_r;
    end
    uart_enable_re <= csrbank5_ev_enable0_re;
    uart_txempty_re <= csrbank5_txempty_re;
    uart_rxfull_re <= csrbank5_rxfull_re;
    if (sys_rst) begin
        litedramcore_reset_storage <= 2'd0;
        litedramcore_reset_re <= 1'd0;
        litedramcore_scratch_storage <= 32'd305419896;
        litedramcore_scratch_re <= 1'd0;
        litedramcore_bus_errors_re <= 1'd0;
        litedramcore_bus_errors <= 32'd0;
        litedramcore_litedramcore_ram_bus_ack <= 1'd0;
        litedramcore_ram_bus_ram_bus_ack <= 1'd0;
        litedramcore_load_storage <= 32'd0;
        litedramcore_load_re <= 1'd0;
        litedramcore_reload_storage <= 32'd0;
        litedramcore_reload_re <= 1'd0;
        litedramcore_en_storage <= 1'd0;
        litedramcore_en_re <= 1'd0;
        litedramcore_update_value_storage <= 1'd0;
        litedramcore_update_value_re <= 1'd0;
        litedramcore_value_status <= 32'd0;
        litedramcore_value_re <= 1'd0;
        litedramcore_zero_pending <= 1'd0;
        litedramcore_zero_trigger_d <= 1'd0;
        litedramcore_status_re <= 1'd0;
        litedramcore_pending_re <= 1'd0;
        litedramcore_pending_r <= 1'd0;
        litedramcore_enable_storage <= 1'd0;
        litedramcore_enable_re <= 1'd0;
        litedramcore_value <= 32'd0;
        uart_tx <= 1'd1;
        tx_tick <= 1'd0;
        rx_tick <= 1'd0;
        rx_rx_d <= 1'd0;
        uart_txfull_re <= 1'd0;
        uart_rxempty_re <= 1'd0;
        uart_tx_pending <= 1'd0;
        uart_tx_trigger_d <= 1'd0;
        uart_rx_pending <= 1'd0;
        uart_rx_trigger_d <= 1'd0;
        uart_status_re <= 1'd0;
        uart_pending_re <= 1'd0;
        uart_pending_r <= 2'd0;
        uart_enable_storage <= 2'd0;
        uart_enable_re <= 1'd0;
        uart_txempty_re <= 1'd0;
        uart_rxfull_re <= 1'd0;
        uart_tx_fifo_readable <= 1'd0;
        uart_tx_fifo_level0 <= 5'd0;
        uart_tx_fifo_produce <= 4'd0;
        uart_tx_fifo_consume <= 4'd0;
        uart_rx_fifo_readable <= 1'd0;
        uart_rx_fifo_level0 <= 5'd0;
        uart_rx_fifo_produce <= 4'd0;
        uart_rx_fifo_consume <= 4'd0;
        k7ddrphy_rst_storage <= 1'd0;
        k7ddrphy_rst_re <= 1'd0;
        k7ddrphy_dly_sel_storage <= 4'd0;
        k7ddrphy_dly_sel_re <= 1'd0;
        k7ddrphy_half_sys8x_taps_storage <= 5'd4;
        k7ddrphy_half_sys8x_taps_re <= 1'd0;
        k7ddrphy_wlevel_en_storage <= 1'd0;
        k7ddrphy_wlevel_en_re <= 1'd0;
        k7ddrphy_rdphase_storage <= 2'd0;
        k7ddrphy_rdphase_re <= 1'd0;
        k7ddrphy_wrphase_storage <= -2'd1;
        k7ddrphy_wrphase_re <= 1'd0;
        k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
        k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
        k7ddrphy_bitslip0_value0 <= 3'd7;
        k7ddrphy_bitslip1_value0 <= 3'd7;
        k7ddrphy_bitslip2_value0 <= 3'd7;
        k7ddrphy_bitslip3_value0 <= 3'd7;
        k7ddrphy_bitslip0_value1 <= 3'd7;
        k7ddrphy_bitslip1_value1 <= 3'd7;
        k7ddrphy_bitslip2_value1 <= 3'd7;
        k7ddrphy_bitslip3_value1 <= 3'd7;
        k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
        k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
        k7ddrphy_bitslip0_value2 <= 3'd7;
        k7ddrphy_bitslip0_value3 <= 3'd7;
        k7ddrphy_bitslip1_value2 <= 3'd7;
        k7ddrphy_bitslip1_value3 <= 3'd7;
        k7ddrphy_bitslip2_value2 <= 3'd7;
        k7ddrphy_bitslip2_value3 <= 3'd7;
        k7ddrphy_bitslip3_value2 <= 3'd7;
        k7ddrphy_bitslip3_value3 <= 3'd7;
        k7ddrphy_bitslip4_value0 <= 3'd7;
        k7ddrphy_bitslip4_value1 <= 3'd7;
        k7ddrphy_bitslip5_value0 <= 3'd7;
        k7ddrphy_bitslip5_value1 <= 3'd7;
        k7ddrphy_bitslip6_value0 <= 3'd7;
        k7ddrphy_bitslip6_value1 <= 3'd7;
        k7ddrphy_bitslip7_value0 <= 3'd7;
        k7ddrphy_bitslip7_value1 <= 3'd7;
        k7ddrphy_bitslip8_value0 <= 3'd7;
        k7ddrphy_bitslip8_value1 <= 3'd7;
        k7ddrphy_bitslip9_value0 <= 3'd7;
        k7ddrphy_bitslip9_value1 <= 3'd7;
        k7ddrphy_bitslip10_value0 <= 3'd7;
        k7ddrphy_bitslip10_value1 <= 3'd7;
        k7ddrphy_bitslip11_value0 <= 3'd7;
        k7ddrphy_bitslip11_value1 <= 3'd7;
        k7ddrphy_bitslip12_value0 <= 3'd7;
        k7ddrphy_bitslip12_value1 <= 3'd7;
        k7ddrphy_bitslip13_value0 <= 3'd7;
        k7ddrphy_bitslip13_value1 <= 3'd7;
        k7ddrphy_bitslip14_value0 <= 3'd7;
        k7ddrphy_bitslip14_value1 <= 3'd7;
        k7ddrphy_bitslip15_value0 <= 3'd7;
        k7ddrphy_bitslip15_value1 <= 3'd7;
        k7ddrphy_bitslip16_value0 <= 3'd7;
        k7ddrphy_bitslip16_value1 <= 3'd7;
        k7ddrphy_bitslip17_value0 <= 3'd7;
        k7ddrphy_bitslip17_value1 <= 3'd7;
        k7ddrphy_bitslip18_value0 <= 3'd7;
        k7ddrphy_bitslip18_value1 <= 3'd7;
        k7ddrphy_bitslip19_value0 <= 3'd7;
        k7ddrphy_bitslip19_value1 <= 3'd7;
        k7ddrphy_bitslip20_value0 <= 3'd7;
        k7ddrphy_bitslip20_value1 <= 3'd7;
        k7ddrphy_bitslip21_value0 <= 3'd7;
        k7ddrphy_bitslip21_value1 <= 3'd7;
        k7ddrphy_bitslip22_value0 <= 3'd7;
        k7ddrphy_bitslip22_value1 <= 3'd7;
        k7ddrphy_bitslip23_value0 <= 3'd7;
        k7ddrphy_bitslip23_value1 <= 3'd7;
        k7ddrphy_bitslip24_value0 <= 3'd7;
        k7ddrphy_bitslip24_value1 <= 3'd7;
        k7ddrphy_bitslip25_value0 <= 3'd7;
        k7ddrphy_bitslip25_value1 <= 3'd7;
        k7ddrphy_bitslip26_value0 <= 3'd7;
        k7ddrphy_bitslip26_value1 <= 3'd7;
        k7ddrphy_bitslip27_value0 <= 3'd7;
        k7ddrphy_bitslip27_value1 <= 3'd7;
        k7ddrphy_bitslip28_value0 <= 3'd7;
        k7ddrphy_bitslip28_value1 <= 3'd7;
        k7ddrphy_bitslip29_value0 <= 3'd7;
        k7ddrphy_bitslip29_value1 <= 3'd7;
        k7ddrphy_bitslip30_value0 <= 3'd7;
        k7ddrphy_bitslip30_value1 <= 3'd7;
        k7ddrphy_bitslip31_value0 <= 3'd7;
        k7ddrphy_bitslip31_value1 <= 3'd7;
        k7ddrphy_rddata_en_tappeddelayline0 <= 1'd0;
        k7ddrphy_rddata_en_tappeddelayline1 <= 1'd0;
        k7ddrphy_rddata_en_tappeddelayline2 <= 1'd0;
        k7ddrphy_rddata_en_tappeddelayline3 <= 1'd0;
        k7ddrphy_rddata_en_tappeddelayline4 <= 1'd0;
        k7ddrphy_rddata_en_tappeddelayline5 <= 1'd0;
        k7ddrphy_rddata_en_tappeddelayline6 <= 1'd0;
        k7ddrphy_rddata_en_tappeddelayline7 <= 1'd0;
        k7ddrphy_rddata_en_tappeddelayline8 <= 1'd0;
        k7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0;
        k7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0;
        k7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0;
        litedramcore_sdram_storage <= 4'd1;
        litedramcore_sdram_re <= 1'd0;
        litedramcore_sdram_phaseinjector0_command_storage <= 8'd0;
        litedramcore_sdram_phaseinjector0_command_re <= 1'd0;
        litedramcore_sdram_phaseinjector0_address_re <= 1'd0;
        litedramcore_sdram_phaseinjector0_baddress_re <= 1'd0;
        litedramcore_sdram_phaseinjector0_wrdata_re <= 1'd0;
        litedramcore_sdram_phaseinjector0_rddata_status <= 64'd0;
        litedramcore_sdram_phaseinjector0_rddata_re <= 1'd0;
        litedramcore_sdram_phaseinjector1_command_storage <= 8'd0;
        litedramcore_sdram_phaseinjector1_command_re <= 1'd0;
        litedramcore_sdram_phaseinjector1_address_re <= 1'd0;
        litedramcore_sdram_phaseinjector1_baddress_re <= 1'd0;
        litedramcore_sdram_phaseinjector1_wrdata_re <= 1'd0;
        litedramcore_sdram_phaseinjector1_rddata_status <= 64'd0;
        litedramcore_sdram_phaseinjector1_rddata_re <= 1'd0;
        litedramcore_sdram_phaseinjector2_command_storage <= 8'd0;
        litedramcore_sdram_phaseinjector2_command_re <= 1'd0;
        litedramcore_sdram_phaseinjector2_address_re <= 1'd0;
        litedramcore_sdram_phaseinjector2_baddress_re <= 1'd0;
        litedramcore_sdram_phaseinjector2_wrdata_re <= 1'd0;
        litedramcore_sdram_phaseinjector2_rddata_status <= 64'd0;
        litedramcore_sdram_phaseinjector2_rddata_re <= 1'd0;
        litedramcore_sdram_phaseinjector3_command_storage <= 8'd0;
        litedramcore_sdram_phaseinjector3_command_re <= 1'd0;
        litedramcore_sdram_phaseinjector3_address_re <= 1'd0;
        litedramcore_sdram_phaseinjector3_baddress_re <= 1'd0;
        litedramcore_sdram_phaseinjector3_wrdata_re <= 1'd0;
        litedramcore_sdram_phaseinjector3_rddata_status <= 64'd0;
        litedramcore_sdram_phaseinjector3_rddata_re <= 1'd0;
        litedramcore_sdram_dfi_p0_address <= 15'd0;
        litedramcore_sdram_dfi_p0_bank <= 3'd0;
        litedramcore_sdram_dfi_p0_cas_n <= 1'd1;
        litedramcore_sdram_dfi_p0_cs_n <= 1'd1;
        litedramcore_sdram_dfi_p0_ras_n <= 1'd1;
        litedramcore_sdram_dfi_p0_we_n <= 1'd1;
        litedramcore_sdram_dfi_p0_wrdata_en <= 1'd0;
        litedramcore_sdram_dfi_p0_rddata_en <= 1'd0;
        litedramcore_sdram_dfi_p1_address <= 15'd0;
        litedramcore_sdram_dfi_p1_bank <= 3'd0;
        litedramcore_sdram_dfi_p1_cas_n <= 1'd1;
        litedramcore_sdram_dfi_p1_cs_n <= 1'd1;
        litedramcore_sdram_dfi_p1_ras_n <= 1'd1;
        litedramcore_sdram_dfi_p1_we_n <= 1'd1;
        litedramcore_sdram_dfi_p1_wrdata_en <= 1'd0;
        litedramcore_sdram_dfi_p1_rddata_en <= 1'd0;
        litedramcore_sdram_dfi_p2_address <= 15'd0;
        litedramcore_sdram_dfi_p2_bank <= 3'd0;
        litedramcore_sdram_dfi_p2_cas_n <= 1'd1;
        litedramcore_sdram_dfi_p2_cs_n <= 1'd1;
        litedramcore_sdram_dfi_p2_ras_n <= 1'd1;
        litedramcore_sdram_dfi_p2_we_n <= 1'd1;
        litedramcore_sdram_dfi_p2_wrdata_en <= 1'd0;
        litedramcore_sdram_dfi_p2_rddata_en <= 1'd0;
        litedramcore_sdram_dfi_p3_address <= 15'd0;
        litedramcore_sdram_dfi_p3_bank <= 3'd0;
        litedramcore_sdram_dfi_p3_cas_n <= 1'd1;
        litedramcore_sdram_dfi_p3_cs_n <= 1'd1;
        litedramcore_sdram_dfi_p3_ras_n <= 1'd1;
        litedramcore_sdram_dfi_p3_we_n <= 1'd1;
        litedramcore_sdram_dfi_p3_wrdata_en <= 1'd0;
        litedramcore_sdram_dfi_p3_rddata_en <= 1'd0;
        litedramcore_sdram_cmd_payload_a <= 15'd0;
        litedramcore_sdram_cmd_payload_ba <= 3'd0;
        litedramcore_sdram_cmd_payload_cas <= 1'd0;
        litedramcore_sdram_cmd_payload_ras <= 1'd0;
        litedramcore_sdram_cmd_payload_we <= 1'd0;
        litedramcore_sdram_timer_count1 <= 11'd1562;
        litedramcore_sdram_postponer_req_o <= 1'd0;
        litedramcore_sdram_postponer_count <= 1'd0;
        litedramcore_sdram_sequencer_done1 <= 1'd0;
        litedramcore_sdram_sequencer_trigger <= 6'd0;
        litedramcore_sdram_sequencer_count <= 1'd0;
        litedramcore_sdram_zqcs_timer_count1 <= 28'd199999999;
        litedramcore_sdram_zqcs_executer_done <= 1'd0;
        litedramcore_sdram_zqcs_executer_trigger <= 5'd0;
        litedramcore_sdram_bankmachine0_level <= 5'd0;
        litedramcore_sdram_bankmachine0_produce <= 4'd0;
        litedramcore_sdram_bankmachine0_consume <= 4'd0;
        litedramcore_sdram_bankmachine0_pipe_valid_source_valid <= 1'd0;
        litedramcore_sdram_bankmachine0_pipe_valid_source_payload_we <= 1'd0;
        litedramcore_sdram_bankmachine0_pipe_valid_source_payload_addr <= 22'd0;
        litedramcore_sdram_bankmachine0_row <= 15'd0;
        litedramcore_sdram_bankmachine0_row_opened <= 1'd0;
        litedramcore_sdram_bankmachine0_twtpcon_ready <= 1'd0;
        litedramcore_sdram_bankmachine0_twtpcon_count <= 3'd0;
        litedramcore_sdram_bankmachine0_trccon_ready <= 1'd0;
        litedramcore_sdram_bankmachine0_trccon_count <= 4'd0;
        litedramcore_sdram_bankmachine0_trascon_ready <= 1'd0;
        litedramcore_sdram_bankmachine0_trascon_count <= 3'd0;
        litedramcore_sdram_bankmachine1_level <= 5'd0;
        litedramcore_sdram_bankmachine1_produce <= 4'd0;
        litedramcore_sdram_bankmachine1_consume <= 4'd0;
        litedramcore_sdram_bankmachine1_pipe_valid_source_valid <= 1'd0;
        litedramcore_sdram_bankmachine1_pipe_valid_source_payload_we <= 1'd0;
        litedramcore_sdram_bankmachine1_pipe_valid_source_payload_addr <= 22'd0;
        litedramcore_sdram_bankmachine1_row <= 15'd0;
        litedramcore_sdram_bankmachine1_row_opened <= 1'd0;
        litedramcore_sdram_bankmachine1_twtpcon_ready <= 1'd0;
        litedramcore_sdram_bankmachine1_twtpcon_count <= 3'd0;
        litedramcore_sdram_bankmachine1_trccon_ready <= 1'd0;
        litedramcore_sdram_bankmachine1_trccon_count <= 4'd0;
        litedramcore_sdram_bankmachine1_trascon_ready <= 1'd0;
        litedramcore_sdram_bankmachine1_trascon_count <= 3'd0;
        litedramcore_sdram_bankmachine2_level <= 5'd0;
        litedramcore_sdram_bankmachine2_produce <= 4'd0;
        litedramcore_sdram_bankmachine2_consume <= 4'd0;
        litedramcore_sdram_bankmachine2_pipe_valid_source_valid <= 1'd0;
        litedramcore_sdram_bankmachine2_pipe_valid_source_payload_we <= 1'd0;
        litedramcore_sdram_bankmachine2_pipe_valid_source_payload_addr <= 22'd0;
        litedramcore_sdram_bankmachine2_row <= 15'd0;
        litedramcore_sdram_bankmachine2_row_opened <= 1'd0;
        litedramcore_sdram_bankmachine2_twtpcon_ready <= 1'd0;
        litedramcore_sdram_bankmachine2_twtpcon_count <= 3'd0;
        litedramcore_sdram_bankmachine2_trccon_ready <= 1'd0;
        litedramcore_sdram_bankmachine2_trccon_count <= 4'd0;
        litedramcore_sdram_bankmachine2_trascon_ready <= 1'd0;
        litedramcore_sdram_bankmachine2_trascon_count <= 3'd0;
        litedramcore_sdram_bankmachine3_level <= 5'd0;
        litedramcore_sdram_bankmachine3_produce <= 4'd0;
        litedramcore_sdram_bankmachine3_consume <= 4'd0;
        litedramcore_sdram_bankmachine3_pipe_valid_source_valid <= 1'd0;
        litedramcore_sdram_bankmachine3_pipe_valid_source_payload_we <= 1'd0;
        litedramcore_sdram_bankmachine3_pipe_valid_source_payload_addr <= 22'd0;
        litedramcore_sdram_bankmachine3_row <= 15'd0;
        litedramcore_sdram_bankmachine3_row_opened <= 1'd0;
        litedramcore_sdram_bankmachine3_twtpcon_ready <= 1'd0;
        litedramcore_sdram_bankmachine3_twtpcon_count <= 3'd0;
        litedramcore_sdram_bankmachine3_trccon_ready <= 1'd0;
        litedramcore_sdram_bankmachine3_trccon_count <= 4'd0;
        litedramcore_sdram_bankmachine3_trascon_ready <= 1'd0;
        litedramcore_sdram_bankmachine3_trascon_count <= 3'd0;
        litedramcore_sdram_bankmachine4_level <= 5'd0;
        litedramcore_sdram_bankmachine4_produce <= 4'd0;
        litedramcore_sdram_bankmachine4_consume <= 4'd0;
        litedramcore_sdram_bankmachine4_pipe_valid_source_valid <= 1'd0;
        litedramcore_sdram_bankmachine4_pipe_valid_source_payload_we <= 1'd0;
        litedramcore_sdram_bankmachine4_pipe_valid_source_payload_addr <= 22'd0;
        litedramcore_sdram_bankmachine4_row <= 15'd0;
        litedramcore_sdram_bankmachine4_row_opened <= 1'd0;
        litedramcore_sdram_bankmachine4_twtpcon_ready <= 1'd0;
        litedramcore_sdram_bankmachine4_twtpcon_count <= 3'd0;
        litedramcore_sdram_bankmachine4_trccon_ready <= 1'd0;
        litedramcore_sdram_bankmachine4_trccon_count <= 4'd0;
        litedramcore_sdram_bankmachine4_trascon_ready <= 1'd0;
        litedramcore_sdram_bankmachine4_trascon_count <= 3'd0;
        litedramcore_sdram_bankmachine5_level <= 5'd0;
        litedramcore_sdram_bankmachine5_produce <= 4'd0;
        litedramcore_sdram_bankmachine5_consume <= 4'd0;
        litedramcore_sdram_bankmachine5_pipe_valid_source_valid <= 1'd0;
        litedramcore_sdram_bankmachine5_pipe_valid_source_payload_we <= 1'd0;
        litedramcore_sdram_bankmachine5_pipe_valid_source_payload_addr <= 22'd0;
        litedramcore_sdram_bankmachine5_row <= 15'd0;
        litedramcore_sdram_bankmachine5_row_opened <= 1'd0;
        litedramcore_sdram_bankmachine5_twtpcon_ready <= 1'd0;
        litedramcore_sdram_bankmachine5_twtpcon_count <= 3'd0;
        litedramcore_sdram_bankmachine5_trccon_ready <= 1'd0;
        litedramcore_sdram_bankmachine5_trccon_count <= 4'd0;
        litedramcore_sdram_bankmachine5_trascon_ready <= 1'd0;
        litedramcore_sdram_bankmachine5_trascon_count <= 3'd0;
        litedramcore_sdram_bankmachine6_level <= 5'd0;
        litedramcore_sdram_bankmachine6_produce <= 4'd0;
        litedramcore_sdram_bankmachine6_consume <= 4'd0;
        litedramcore_sdram_bankmachine6_pipe_valid_source_valid <= 1'd0;
        litedramcore_sdram_bankmachine6_pipe_valid_source_payload_we <= 1'd0;
        litedramcore_sdram_bankmachine6_pipe_valid_source_payload_addr <= 22'd0;
        litedramcore_sdram_bankmachine6_row <= 15'd0;
        litedramcore_sdram_bankmachine6_row_opened <= 1'd0;
        litedramcore_sdram_bankmachine6_twtpcon_ready <= 1'd0;
        litedramcore_sdram_bankmachine6_twtpcon_count <= 3'd0;
        litedramcore_sdram_bankmachine6_trccon_ready <= 1'd0;
        litedramcore_sdram_bankmachine6_trccon_count <= 4'd0;
        litedramcore_sdram_bankmachine6_trascon_ready <= 1'd0;
        litedramcore_sdram_bankmachine6_trascon_count <= 3'd0;
        litedramcore_sdram_bankmachine7_level <= 5'd0;
        litedramcore_sdram_bankmachine7_produce <= 4'd0;
        litedramcore_sdram_bankmachine7_consume <= 4'd0;
        litedramcore_sdram_bankmachine7_pipe_valid_source_valid <= 1'd0;
        litedramcore_sdram_bankmachine7_pipe_valid_source_payload_we <= 1'd0;
        litedramcore_sdram_bankmachine7_pipe_valid_source_payload_addr <= 22'd0;
        litedramcore_sdram_bankmachine7_row <= 15'd0;
        litedramcore_sdram_bankmachine7_row_opened <= 1'd0;
        litedramcore_sdram_bankmachine7_twtpcon_ready <= 1'd0;
        litedramcore_sdram_bankmachine7_twtpcon_count <= 3'd0;
        litedramcore_sdram_bankmachine7_trccon_ready <= 1'd0;
        litedramcore_sdram_bankmachine7_trccon_count <= 4'd0;
        litedramcore_sdram_bankmachine7_trascon_ready <= 1'd0;
        litedramcore_sdram_bankmachine7_trascon_count <= 3'd0;
        litedramcore_sdram_choose_cmd_grant <= 3'd0;
        litedramcore_sdram_choose_req_grant <= 3'd0;
        litedramcore_sdram_trrdcon_ready <= 1'd0;
        litedramcore_sdram_trrdcon_count <= 2'd0;
        litedramcore_sdram_tfawcon_ready <= 1'd1;
        litedramcore_sdram_tfawcon_window <= 9'd0;
        litedramcore_sdram_tccdcon_ready <= 1'd0;
        litedramcore_sdram_tccdcon_count <= 1'd0;
        litedramcore_sdram_twtrcon_ready <= 1'd0;
        litedramcore_sdram_twtrcon_count <= 3'd0;
        litedramcore_sdram_time0 <= 5'd0;
        litedramcore_sdram_time1 <= 4'd0;
        litedramcore_aborted <= 1'd0;
        init_done_storage <= 1'd0;
        init_done_re <= 1'd0;
        init_error_storage <= 1'd0;
        init_error_re <= 1'd0;
        user_enable <= 1'd0;
        user_port_litedramnativeportconverter_sel <= 8'd0;
        user_port_litedramnativeportconverter_cmd_addr <= 28'd0;
        user_port_litedramnativeportconverter_cmd_we <= 1'd0;
        user_port_litedramnativeportconverter_cmd_last <= 1'd0;
        user_port_litedramnativeportconverter_read_lock <= 1'd0;
        user_port_litedramnativeportconverter_read_unlocked <= 1'd0;
        user_port_litedramnativeportconverter_rdata_fifo_level <= 3'd0;
        user_port_litedramnativeportconverter_rdata_fifo_produce <= 3'd0;
        user_port_litedramnativeportconverter_rdata_fifo_consume <= 3'd0;
        user_port_litedramnativeportconverter_rdata_converter_converter_mux <= 3'd0;
        user_port_litedramnativeportconverter_rdata_chunk <= 8'd1;
        user_port_litedramnativeportconverter_wdata_fifo_level <= 3'd0;
        user_port_litedramnativeportconverter_wdata_fifo_produce <= 3'd0;
        user_port_litedramnativeportconverter_wdata_fifo_consume <= 3'd0;
        user_port_litedramnativeportconverter_wdata_buffer_pipe_valid_source_valid <= 1'd0;
        user_port_litedramnativeportconverter_wdata_buffer_pipe_valid_source_payload_data <= 256'd0;
        user_port_litedramnativeportconverter_wdata_buffer_pipe_valid_source_payload_we <= 32'd0;
        user_port_litedramnativeportconverter_wdata_converter_converter_source_payload_data <= 288'd0;
        user_port_litedramnativeportconverter_wdata_converter_converter_source_payload_valid_token_count <= 4'd0;
        user_port_litedramnativeportconverter_wdata_converter_converter_demux <= 3'd0;
        user_port_litedramnativeportconverter_wdata_converter_converter_strobe_all <= 1'd0;
        user_port_litedramnativeportconverter_wdata_chunk <= 8'd1;
        user_port_litedramnativeportconverter_wdata_sel <= 32'd0;
        wishbone2native_aborted <= 1'd0;
        interface1_re <= 1'd0;
        interface1_we <= 1'd0;
        grant <= 1'd0;
        slave_sel_r <= 4'd0;
        count <= 20'd1000000;
        rs232phytx_state <= 1'd0;
        rs232phyrx_state <= 1'd0;
        litedramcore_refresher_state <= 2'd0;
        litedramcore_bankmachine0_state <= 4'd0;
        litedramcore_bankmachine1_state <= 4'd0;
        litedramcore_bankmachine2_state <= 4'd0;
        litedramcore_bankmachine3_state <= 4'd0;
        litedramcore_bankmachine4_state <= 4'd0;
        litedramcore_bankmachine5_state <= 4'd0;
        litedramcore_bankmachine6_state <= 4'd0;
        litedramcore_bankmachine7_state <= 4'd0;
        litedramcore_multiplexer_state <= 4'd0;
        litedramcore_state <= 2'd0;
        litedramcore_roundrobin0_grant <= 1'd0;
        litedramcore_roundrobin1_grant <= 1'd0;
        litedramcore_roundrobin2_grant <= 1'd0;
        litedramcore_roundrobin3_grant <= 1'd0;
        litedramcore_roundrobin4_grant <= 1'd0;
        litedramcore_roundrobin5_grant <= 1'd0;
        litedramcore_roundrobin6_grant <= 1'd0;
        litedramcore_roundrobin7_grant <= 1'd0;
        litedramcore_new_master_wdata_ready0 <= 1'd0;
        litedramcore_new_master_wdata_ready1 <= 1'd0;
        litedramcore_new_master_wdata_ready2 <= 1'd0;
        litedramcore_new_master_wdata_ready3 <= 1'd0;
        litedramcore_new_master_rdata_valid0 <= 1'd0;
        litedramcore_new_master_rdata_valid1 <= 1'd0;
        litedramcore_new_master_rdata_valid2 <= 1'd0;
        litedramcore_new_master_rdata_valid3 <= 1'd0;
        litedramcore_new_master_rdata_valid4 <= 1'd0;
        litedramcore_new_master_rdata_valid5 <= 1'd0;
        litedramcore_new_master_rdata_valid6 <= 1'd0;
        litedramcore_new_master_rdata_valid7 <= 1'd0;
        litedramcore_new_master_rdata_valid8 <= 1'd0;
        litedramcore_new_master_rdata_valid9 <= 1'd0;
        litedramcore_new_master_rdata_valid10 <= 1'd0;
        litedramcore_new_master_rdata_valid11 <= 1'd0;
        litedramcore_new_master_rdata_valid12 <= 1'd0;
        litedramcore_new_master_rdata_valid13 <= 1'd0;
        litedramcore_new_master_rdata_valid14 <= 1'd0;
        litedramcore_new_master_rdata_valid15 <= 1'd0;
        litedramcore_new_master_rdata_valid16 <= 1'd0;
        litedramcore_new_master_rdata_valid17 <= 1'd0;
        litedramcore_new_master_rdata_valid18 <= 1'd0;
        litedramcore_new_master_rdata_valid19 <= 1'd0;
        fullmemorywe_state <= 2'd0;
        litedramwishbone2native0_state <= 2'd0;
        litedramwishbone2native1_state <= 2'd0;
        wishbone2csr_state <= 2'd0;
    end
    xilinxmultiregimpl0 <= uart_rx;
    xilinxmultiregimpl1 <= xilinxmultiregimpl0;
end


//------------------------------------------------------------------------------
// Specialized Logic
//------------------------------------------------------------------------------

//------------------------------------------------------------------------------
// Memory rom: 8481-words x 32-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: ---- | 
reg [31:0] rom[0:8480];
initial begin
	$readmemh("litedram_core_rom.init", rom);
end
reg [31:0] rom_dat0;
always @(posedge sys_clk) begin
	rom_dat0 <= rom[litedramcore_litedramcore_adr];
end
assign litedramcore_litedramcore_dat_r = rom_dat0;


//------------------------------------------------------------------------------
// Memory sram: 2048-words x 32-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
reg [31:0] sram[0:2047];
initial begin
	$readmemh("litedram_core_sram.init", sram);
end
reg [10:0] sram_adr0;
always @(posedge sys_clk) begin
	if (litedramcore_ram_we[0])
		sram[litedramcore_ram_adr][7:0] <= litedramcore_ram_dat_w[7:0];
	if (litedramcore_ram_we[1])
		sram[litedramcore_ram_adr][15:8] <= litedramcore_ram_dat_w[15:8];
	if (litedramcore_ram_we[2])
		sram[litedramcore_ram_adr][23:16] <= litedramcore_ram_dat_w[23:16];
	if (litedramcore_ram_we[3])
		sram[litedramcore_ram_adr][31:24] <= litedramcore_ram_dat_w[31:24];
	sram_adr0 <= litedramcore_ram_adr;
end
assign litedramcore_ram_dat_r = sram[sram_adr0];


//------------------------------------------------------------------------------
// Memory storage: 16-words x 10-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 10 
// Port 1 | Read: Sync  | Write: ---- | 
reg [9:0] storage[0:15];
reg [9:0] storage_dat0;
reg [9:0] storage_dat1;
always @(posedge sys_clk) begin
	if (uart_tx_fifo_wrport_we)
		storage[uart_tx_fifo_wrport_adr] <= uart_tx_fifo_wrport_dat_w;
	storage_dat0 <= storage[uart_tx_fifo_wrport_adr];
end
always @(posedge sys_clk) begin
	if (uart_tx_fifo_rdport_re)
		storage_dat1 <= storage[uart_tx_fifo_rdport_adr];
end
assign uart_tx_fifo_wrport_dat_r = storage_dat0;
assign uart_tx_fifo_rdport_dat_r = storage_dat1;


//------------------------------------------------------------------------------
// Memory storage_1: 16-words x 10-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 10 
// Port 1 | Read: Sync  | Write: ---- | 
reg [9:0] storage_1[0:15];
reg [9:0] storage_1_dat0;
reg [9:0] storage_1_dat1;
always @(posedge sys_clk) begin
	if (uart_rx_fifo_wrport_we)
		storage_1[uart_rx_fifo_wrport_adr] <= uart_rx_fifo_wrport_dat_w;
	storage_1_dat0 <= storage_1[uart_rx_fifo_wrport_adr];
end
always @(posedge sys_clk) begin
	if (uart_rx_fifo_rdport_re)
		storage_1_dat1 <= storage_1[uart_rx_fifo_rdport_adr];
end
assign uart_rx_fifo_wrport_dat_r = storage_1_dat0;
assign uart_rx_fifo_rdport_dat_r = storage_1_dat1;


//------------------------------------------------------------------------------
// Instance BUFG of BUFG Module.
//------------------------------------------------------------------------------
BUFG BUFG(
	// Inputs.
	.I (crg_clkout0),

	// Outputs.
	.O (crg_clkout_buf0)
);

//------------------------------------------------------------------------------
// Instance BUFG_1 of BUFG Module.
//------------------------------------------------------------------------------
BUFG BUFG_1(
	// Inputs.
	.I (crg_clkout1),

	// Outputs.
	.O (crg_clkout_buf1)
);

//------------------------------------------------------------------------------
// Instance BUFG_2 of BUFG Module.
//------------------------------------------------------------------------------
BUFG BUFG_2(
	// Inputs.
	.I (crg_clkout2),

	// Outputs.
	.O (crg_clkout_buf2)
);

//------------------------------------------------------------------------------
// Instance BUFG_3 of BUFG Module.
//------------------------------------------------------------------------------
BUFG BUFG_3(
	// Inputs.
	.I (crg_clkout3),

	// Outputs.
	.O (crg_clkout_buf3)
);

//------------------------------------------------------------------------------
// Instance IDELAYCTRL of IDELAYCTRL Module.
//------------------------------------------------------------------------------
IDELAYCTRL IDELAYCTRL(
	// Inputs.
	.REFCLK (iodelay_clk),
	.RST    (crg_ic_reset)
);

//------------------------------------------------------------------------------
// Instance OSERDESE2 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (1'd0),
	.D2     (1'd1),
	.D3     (1'd0),
	.D4     (1'd1),
	.D5     (1'd0),
	.D6     (1'd1),
	.D7     (1'd0),
	.D8     (1'd1),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.OQ     (k7ddrphy_sd_clk_se_nodelay)
);

//------------------------------------------------------------------------------
// Instance ODELAYE2 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2 (
	// Inputs.
	.C        (sys_clk),
	.CE       (k7ddrphy_cdly_inc_re),
	.INC      (1'd1),
	.LD       (((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_sd_clk_se_delayed),
	.ODATAIN  (k7ddrphy_sd_clk_se_nodelay)
);

//------------------------------------------------------------------------------
// Instance OBUFDS of OBUFDS Module.
//------------------------------------------------------------------------------
OBUFDS OBUFDS(
	// Inputs.
	.I  (k7ddrphy_sd_clk_se_delayed),

	// Outputs.
	.O  (ddram_clk_p),
	.OB (ddram_clk_n)
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_1 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_1 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_dfi_p0_reset_n),
	.D2     (k7ddrphy_dfi_p0_reset_n),
	.D3     (k7ddrphy_dfi_p1_reset_n),
	.D4     (k7ddrphy_dfi_p1_reset_n),
	.D5     (k7ddrphy_dfi_p2_reset_n),
	.D6     (k7ddrphy_dfi_p2_reset_n),
	.D7     (k7ddrphy_dfi_p3_reset_n),
	.D8     (k7ddrphy_dfi_p3_reset_n),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.OQ     (k7ddrphy_oq0)
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_1 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_1 (
	// Inputs.
	.C        (sys_clk),
	.CE       (k7ddrphy_cdly_inc_re),
	.INC      (1'd1),
	.LD       (((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (ddram_reset_n),
	.ODATAIN  (k7ddrphy_oq0)
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_2 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_2 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_dfi_p0_cs_n),
	.D2     (k7ddrphy_dfi_p0_cs_n),
	.D3     (k7ddrphy_dfi_p1_cs_n),
	.D4     (k7ddrphy_dfi_p1_cs_n),
	.D5     (k7ddrphy_dfi_p2_cs_n),
	.D6     (k7ddrphy_dfi_p2_cs_n),
	.D7     (k7ddrphy_dfi_p3_cs_n),
	.D8     (k7ddrphy_dfi_p3_cs_n),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.OQ     (k7ddrphy_oq1)
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_2 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_2 (
	// Inputs.
	.C        (sys_clk),
	.CE       (k7ddrphy_cdly_inc_re),
	.INC      (1'd1),
	.LD       (((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (ddram_cs_n),
	.ODATAIN  (k7ddrphy_oq1)
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_3 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_3 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_dfi_p0_address[0]),
	.D2     (k7ddrphy_dfi_p0_address[0]),
	.D3     (k7ddrphy_dfi_p1_address[0]),
	.D4     (k7ddrphy_dfi_p1_address[0]),
	.D5     (k7ddrphy_dfi_p2_address[0]),
	.D6     (k7ddrphy_dfi_p2_address[0]),
	.D7     (k7ddrphy_dfi_p3_address[0]),
	.D8     (k7ddrphy_dfi_p3_address[0]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.OQ     (k7ddrphy_oq2)
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_3 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_3 (
	// Inputs.
	.C        (sys_clk),
	.CE       (k7ddrphy_cdly_inc_re),
	.INC      (1'd1),
	.LD       (((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (ddram_a[0]),
	.ODATAIN  (k7ddrphy_oq2)
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_4 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_4 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_dfi_p0_address[1]),
	.D2     (k7ddrphy_dfi_p0_address[1]),
	.D3     (k7ddrphy_dfi_p1_address[1]),
	.D4     (k7ddrphy_dfi_p1_address[1]),
	.D5     (k7ddrphy_dfi_p2_address[1]),
	.D6     (k7ddrphy_dfi_p2_address[1]),
	.D7     (k7ddrphy_dfi_p3_address[1]),
	.D8     (k7ddrphy_dfi_p3_address[1]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.OQ     (k7ddrphy_oq3)
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_4 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_4 (
	// Inputs.
	.C        (sys_clk),
	.CE       (k7ddrphy_cdly_inc_re),
	.INC      (1'd1),
	.LD       (((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (ddram_a[1]),
	.ODATAIN  (k7ddrphy_oq3)
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_5 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_5 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_dfi_p0_address[2]),
	.D2     (k7ddrphy_dfi_p0_address[2]),
	.D3     (k7ddrphy_dfi_p1_address[2]),
	.D4     (k7ddrphy_dfi_p1_address[2]),
	.D5     (k7ddrphy_dfi_p2_address[2]),
	.D6     (k7ddrphy_dfi_p2_address[2]),
	.D7     (k7ddrphy_dfi_p3_address[2]),
	.D8     (k7ddrphy_dfi_p3_address[2]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.OQ     (k7ddrphy_oq4)
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_5 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_5 (
	// Inputs.
	.C        (sys_clk),
	.CE       (k7ddrphy_cdly_inc_re),
	.INC      (1'd1),
	.LD       (((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (ddram_a[2]),
	.ODATAIN  (k7ddrphy_oq4)
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_6 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_6 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_dfi_p0_address[3]),
	.D2     (k7ddrphy_dfi_p0_address[3]),
	.D3     (k7ddrphy_dfi_p1_address[3]),
	.D4     (k7ddrphy_dfi_p1_address[3]),
	.D5     (k7ddrphy_dfi_p2_address[3]),
	.D6     (k7ddrphy_dfi_p2_address[3]),
	.D7     (k7ddrphy_dfi_p3_address[3]),
	.D8     (k7ddrphy_dfi_p3_address[3]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.OQ     (k7ddrphy_oq5)
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_6 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_6 (
	// Inputs.
	.C        (sys_clk),
	.CE       (k7ddrphy_cdly_inc_re),
	.INC      (1'd1),
	.LD       (((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (ddram_a[3]),
	.ODATAIN  (k7ddrphy_oq5)
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_7 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_7 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_dfi_p0_address[4]),
	.D2     (k7ddrphy_dfi_p0_address[4]),
	.D3     (k7ddrphy_dfi_p1_address[4]),
	.D4     (k7ddrphy_dfi_p1_address[4]),
	.D5     (k7ddrphy_dfi_p2_address[4]),
	.D6     (k7ddrphy_dfi_p2_address[4]),
	.D7     (k7ddrphy_dfi_p3_address[4]),
	.D8     (k7ddrphy_dfi_p3_address[4]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.OQ     (k7ddrphy_oq6)
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_7 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_7 (
	// Inputs.
	.C        (sys_clk),
	.CE       (k7ddrphy_cdly_inc_re),
	.INC      (1'd1),
	.LD       (((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (ddram_a[4]),
	.ODATAIN  (k7ddrphy_oq6)
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_8 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_8 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_dfi_p0_address[5]),
	.D2     (k7ddrphy_dfi_p0_address[5]),
	.D3     (k7ddrphy_dfi_p1_address[5]),
	.D4     (k7ddrphy_dfi_p1_address[5]),
	.D5     (k7ddrphy_dfi_p2_address[5]),
	.D6     (k7ddrphy_dfi_p2_address[5]),
	.D7     (k7ddrphy_dfi_p3_address[5]),
	.D8     (k7ddrphy_dfi_p3_address[5]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.OQ     (k7ddrphy_oq7)
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_8 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_8 (
	// Inputs.
	.C        (sys_clk),
	.CE       (k7ddrphy_cdly_inc_re),
	.INC      (1'd1),
	.LD       (((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (ddram_a[5]),
	.ODATAIN  (k7ddrphy_oq7)
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_9 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_9 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_dfi_p0_address[6]),
	.D2     (k7ddrphy_dfi_p0_address[6]),
	.D3     (k7ddrphy_dfi_p1_address[6]),
	.D4     (k7ddrphy_dfi_p1_address[6]),
	.D5     (k7ddrphy_dfi_p2_address[6]),
	.D6     (k7ddrphy_dfi_p2_address[6]),
	.D7     (k7ddrphy_dfi_p3_address[6]),
	.D8     (k7ddrphy_dfi_p3_address[6]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.OQ     (k7ddrphy_oq8)
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_9 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_9 (
	// Inputs.
	.C        (sys_clk),
	.CE       (k7ddrphy_cdly_inc_re),
	.INC      (1'd1),
	.LD       (((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (ddram_a[6]),
	.ODATAIN  (k7ddrphy_oq8)
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_10 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_10 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_dfi_p0_address[7]),
	.D2     (k7ddrphy_dfi_p0_address[7]),
	.D3     (k7ddrphy_dfi_p1_address[7]),
	.D4     (k7ddrphy_dfi_p1_address[7]),
	.D5     (k7ddrphy_dfi_p2_address[7]),
	.D6     (k7ddrphy_dfi_p2_address[7]),
	.D7     (k7ddrphy_dfi_p3_address[7]),
	.D8     (k7ddrphy_dfi_p3_address[7]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.OQ     (k7ddrphy_oq9)
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_10 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_10 (
	// Inputs.
	.C        (sys_clk),
	.CE       (k7ddrphy_cdly_inc_re),
	.INC      (1'd1),
	.LD       (((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (ddram_a[7]),
	.ODATAIN  (k7ddrphy_oq9)
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_11 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_11 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_dfi_p0_address[8]),
	.D2     (k7ddrphy_dfi_p0_address[8]),
	.D3     (k7ddrphy_dfi_p1_address[8]),
	.D4     (k7ddrphy_dfi_p1_address[8]),
	.D5     (k7ddrphy_dfi_p2_address[8]),
	.D6     (k7ddrphy_dfi_p2_address[8]),
	.D7     (k7ddrphy_dfi_p3_address[8]),
	.D8     (k7ddrphy_dfi_p3_address[8]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.OQ     (k7ddrphy_oq10)
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_11 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_11 (
	// Inputs.
	.C        (sys_clk),
	.CE       (k7ddrphy_cdly_inc_re),
	.INC      (1'd1),
	.LD       (((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (ddram_a[8]),
	.ODATAIN  (k7ddrphy_oq10)
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_12 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_12 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_dfi_p0_address[9]),
	.D2     (k7ddrphy_dfi_p0_address[9]),
	.D3     (k7ddrphy_dfi_p1_address[9]),
	.D4     (k7ddrphy_dfi_p1_address[9]),
	.D5     (k7ddrphy_dfi_p2_address[9]),
	.D6     (k7ddrphy_dfi_p2_address[9]),
	.D7     (k7ddrphy_dfi_p3_address[9]),
	.D8     (k7ddrphy_dfi_p3_address[9]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.OQ     (k7ddrphy_oq11)
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_12 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_12 (
	// Inputs.
	.C        (sys_clk),
	.CE       (k7ddrphy_cdly_inc_re),
	.INC      (1'd1),
	.LD       (((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (ddram_a[9]),
	.ODATAIN  (k7ddrphy_oq11)
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_13 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_13 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_dfi_p0_address[10]),
	.D2     (k7ddrphy_dfi_p0_address[10]),
	.D3     (k7ddrphy_dfi_p1_address[10]),
	.D4     (k7ddrphy_dfi_p1_address[10]),
	.D5     (k7ddrphy_dfi_p2_address[10]),
	.D6     (k7ddrphy_dfi_p2_address[10]),
	.D7     (k7ddrphy_dfi_p3_address[10]),
	.D8     (k7ddrphy_dfi_p3_address[10]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.OQ     (k7ddrphy_oq12)
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_13 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_13 (
	// Inputs.
	.C        (sys_clk),
	.CE       (k7ddrphy_cdly_inc_re),
	.INC      (1'd1),
	.LD       (((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (ddram_a[10]),
	.ODATAIN  (k7ddrphy_oq12)
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_14 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_14 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_dfi_p0_address[11]),
	.D2     (k7ddrphy_dfi_p0_address[11]),
	.D3     (k7ddrphy_dfi_p1_address[11]),
	.D4     (k7ddrphy_dfi_p1_address[11]),
	.D5     (k7ddrphy_dfi_p2_address[11]),
	.D6     (k7ddrphy_dfi_p2_address[11]),
	.D7     (k7ddrphy_dfi_p3_address[11]),
	.D8     (k7ddrphy_dfi_p3_address[11]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.OQ     (k7ddrphy_oq13)
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_14 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_14 (
	// Inputs.
	.C        (sys_clk),
	.CE       (k7ddrphy_cdly_inc_re),
	.INC      (1'd1),
	.LD       (((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (ddram_a[11]),
	.ODATAIN  (k7ddrphy_oq13)
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_15 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_15 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_dfi_p0_address[12]),
	.D2     (k7ddrphy_dfi_p0_address[12]),
	.D3     (k7ddrphy_dfi_p1_address[12]),
	.D4     (k7ddrphy_dfi_p1_address[12]),
	.D5     (k7ddrphy_dfi_p2_address[12]),
	.D6     (k7ddrphy_dfi_p2_address[12]),
	.D7     (k7ddrphy_dfi_p3_address[12]),
	.D8     (k7ddrphy_dfi_p3_address[12]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.OQ     (k7ddrphy_oq14)
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_15 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_15 (
	// Inputs.
	.C        (sys_clk),
	.CE       (k7ddrphy_cdly_inc_re),
	.INC      (1'd1),
	.LD       (((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (ddram_a[12]),
	.ODATAIN  (k7ddrphy_oq14)
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_16 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_16 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_dfi_p0_address[13]),
	.D2     (k7ddrphy_dfi_p0_address[13]),
	.D3     (k7ddrphy_dfi_p1_address[13]),
	.D4     (k7ddrphy_dfi_p1_address[13]),
	.D5     (k7ddrphy_dfi_p2_address[13]),
	.D6     (k7ddrphy_dfi_p2_address[13]),
	.D7     (k7ddrphy_dfi_p3_address[13]),
	.D8     (k7ddrphy_dfi_p3_address[13]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.OQ     (k7ddrphy_oq15)
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_16 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_16 (
	// Inputs.
	.C        (sys_clk),
	.CE       (k7ddrphy_cdly_inc_re),
	.INC      (1'd1),
	.LD       (((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (ddram_a[13]),
	.ODATAIN  (k7ddrphy_oq15)
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_17 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_17 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_dfi_p0_address[14]),
	.D2     (k7ddrphy_dfi_p0_address[14]),
	.D3     (k7ddrphy_dfi_p1_address[14]),
	.D4     (k7ddrphy_dfi_p1_address[14]),
	.D5     (k7ddrphy_dfi_p2_address[14]),
	.D6     (k7ddrphy_dfi_p2_address[14]),
	.D7     (k7ddrphy_dfi_p3_address[14]),
	.D8     (k7ddrphy_dfi_p3_address[14]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.OQ     (k7ddrphy_oq16)
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_17 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_17 (
	// Inputs.
	.C        (sys_clk),
	.CE       (k7ddrphy_cdly_inc_re),
	.INC      (1'd1),
	.LD       (((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (ddram_a[14]),
	.ODATAIN  (k7ddrphy_oq16)
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_18 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_18 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_dfi_p0_bank[0]),
	.D2     (k7ddrphy_dfi_p0_bank[0]),
	.D3     (k7ddrphy_dfi_p1_bank[0]),
	.D4     (k7ddrphy_dfi_p1_bank[0]),
	.D5     (k7ddrphy_dfi_p2_bank[0]),
	.D6     (k7ddrphy_dfi_p2_bank[0]),
	.D7     (k7ddrphy_dfi_p3_bank[0]),
	.D8     (k7ddrphy_dfi_p3_bank[0]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.OQ     (k7ddrphy_oq17)
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_18 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_18 (
	// Inputs.
	.C        (sys_clk),
	.CE       (k7ddrphy_cdly_inc_re),
	.INC      (1'd1),
	.LD       (((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_pads_ba[0]),
	.ODATAIN  (k7ddrphy_oq17)
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_19 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_19 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_dfi_p0_bank[1]),
	.D2     (k7ddrphy_dfi_p0_bank[1]),
	.D3     (k7ddrphy_dfi_p1_bank[1]),
	.D4     (k7ddrphy_dfi_p1_bank[1]),
	.D5     (k7ddrphy_dfi_p2_bank[1]),
	.D6     (k7ddrphy_dfi_p2_bank[1]),
	.D7     (k7ddrphy_dfi_p3_bank[1]),
	.D8     (k7ddrphy_dfi_p3_bank[1]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.OQ     (k7ddrphy_oq18)
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_19 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_19 (
	// Inputs.
	.C        (sys_clk),
	.CE       (k7ddrphy_cdly_inc_re),
	.INC      (1'd1),
	.LD       (((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_pads_ba[1]),
	.ODATAIN  (k7ddrphy_oq18)
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_20 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_20 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_dfi_p0_bank[2]),
	.D2     (k7ddrphy_dfi_p0_bank[2]),
	.D3     (k7ddrphy_dfi_p1_bank[2]),
	.D4     (k7ddrphy_dfi_p1_bank[2]),
	.D5     (k7ddrphy_dfi_p2_bank[2]),
	.D6     (k7ddrphy_dfi_p2_bank[2]),
	.D7     (k7ddrphy_dfi_p3_bank[2]),
	.D8     (k7ddrphy_dfi_p3_bank[2]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.OQ     (k7ddrphy_oq19)
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_20 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_20 (
	// Inputs.
	.C        (sys_clk),
	.CE       (k7ddrphy_cdly_inc_re),
	.INC      (1'd1),
	.LD       (((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_pads_ba[2]),
	.ODATAIN  (k7ddrphy_oq19)
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_21 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_21 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_dfi_p0_ras_n),
	.D2     (k7ddrphy_dfi_p0_ras_n),
	.D3     (k7ddrphy_dfi_p1_ras_n),
	.D4     (k7ddrphy_dfi_p1_ras_n),
	.D5     (k7ddrphy_dfi_p2_ras_n),
	.D6     (k7ddrphy_dfi_p2_ras_n),
	.D7     (k7ddrphy_dfi_p3_ras_n),
	.D8     (k7ddrphy_dfi_p3_ras_n),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.OQ     (k7ddrphy_oq20)
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_21 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_21 (
	// Inputs.
	.C        (sys_clk),
	.CE       (k7ddrphy_cdly_inc_re),
	.INC      (1'd1),
	.LD       (((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (ddram_ras_n),
	.ODATAIN  (k7ddrphy_oq20)
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_22 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_22 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_dfi_p0_cas_n),
	.D2     (k7ddrphy_dfi_p0_cas_n),
	.D3     (k7ddrphy_dfi_p1_cas_n),
	.D4     (k7ddrphy_dfi_p1_cas_n),
	.D5     (k7ddrphy_dfi_p2_cas_n),
	.D6     (k7ddrphy_dfi_p2_cas_n),
	.D7     (k7ddrphy_dfi_p3_cas_n),
	.D8     (k7ddrphy_dfi_p3_cas_n),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.OQ     (k7ddrphy_oq21)
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_22 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_22 (
	// Inputs.
	.C        (sys_clk),
	.CE       (k7ddrphy_cdly_inc_re),
	.INC      (1'd1),
	.LD       (((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (ddram_cas_n),
	.ODATAIN  (k7ddrphy_oq21)
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_23 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_23 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_dfi_p0_we_n),
	.D2     (k7ddrphy_dfi_p0_we_n),
	.D3     (k7ddrphy_dfi_p1_we_n),
	.D4     (k7ddrphy_dfi_p1_we_n),
	.D5     (k7ddrphy_dfi_p2_we_n),
	.D6     (k7ddrphy_dfi_p2_we_n),
	.D7     (k7ddrphy_dfi_p3_we_n),
	.D8     (k7ddrphy_dfi_p3_we_n),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.OQ     (k7ddrphy_oq22)
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_23 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_23 (
	// Inputs.
	.C        (sys_clk),
	.CE       (k7ddrphy_cdly_inc_re),
	.INC      (1'd1),
	.LD       (((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (ddram_we_n),
	.ODATAIN  (k7ddrphy_oq22)
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_24 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_24 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_dfi_p0_cke),
	.D2     (k7ddrphy_dfi_p0_cke),
	.D3     (k7ddrphy_dfi_p1_cke),
	.D4     (k7ddrphy_dfi_p1_cke),
	.D5     (k7ddrphy_dfi_p2_cke),
	.D6     (k7ddrphy_dfi_p2_cke),
	.D7     (k7ddrphy_dfi_p3_cke),
	.D8     (k7ddrphy_dfi_p3_cke),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.OQ     (k7ddrphy_oq23)
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_24 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_24 (
	// Inputs.
	.C        (sys_clk),
	.CE       (k7ddrphy_cdly_inc_re),
	.INC      (1'd1),
	.LD       (((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (ddram_cke),
	.ODATAIN  (k7ddrphy_oq23)
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_25 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_25 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_dfi_p0_odt),
	.D2     (k7ddrphy_dfi_p0_odt),
	.D3     (k7ddrphy_dfi_p1_odt),
	.D4     (k7ddrphy_dfi_p1_odt),
	.D5     (k7ddrphy_dfi_p2_odt),
	.D6     (k7ddrphy_dfi_p2_odt),
	.D7     (k7ddrphy_dfi_p3_odt),
	.D8     (k7ddrphy_dfi_p3_odt),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.OQ     (k7ddrphy_oq24)
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_25 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_25 (
	// Inputs.
	.C        (sys_clk),
	.CE       (k7ddrphy_cdly_inc_re),
	.INC      (1'd1),
	.LD       (((k7ddrphy_cdly_rst_re | k7ddrphy_rst_storage) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (ddram_odt),
	.ODATAIN  (k7ddrphy_oq24)
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_26 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_26 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_bitslip00[0]),
	.D2     (k7ddrphy_bitslip00[1]),
	.D3     (k7ddrphy_bitslip00[2]),
	.D4     (k7ddrphy_bitslip00[3]),
	.D5     (k7ddrphy_bitslip00[4]),
	.D6     (k7ddrphy_bitslip00[5]),
	.D7     (k7ddrphy_bitslip00[6]),
	.D8     (k7ddrphy_bitslip00[7]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),
	.T1     ((~k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
	.TCE    (1'd1),

	// Outputs.
	.OFB    (k7ddrphy_dqs_o_no_delay0),
	.OQ     (k7ddrphy0),
	.TQ     (k7ddrphy_dqs_t0)
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_26 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (3'd4),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_26 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dqs_inc_re)),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dqs_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dqs_o_delayed0),
	.ODATAIN  (k7ddrphy_dqs_o_no_delay0)
);

//------------------------------------------------------------------------------
// Instance IOBUFDS of IOBUFDS Module.
//------------------------------------------------------------------------------
IOBUFDS IOBUFDS(
	// Inputs.
	.I   (k7ddrphy_dqs_o_delayed0),
	.T   (k7ddrphy_dqs_t0),

	// InOuts.
	.IO  (ddram_dqs_p[0]),
	.IOB (ddram_dqs_n[0])
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_27 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_27 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_bitslip10[0]),
	.D2     (k7ddrphy_bitslip10[1]),
	.D3     (k7ddrphy_bitslip10[2]),
	.D4     (k7ddrphy_bitslip10[3]),
	.D5     (k7ddrphy_bitslip10[4]),
	.D6     (k7ddrphy_bitslip10[5]),
	.D7     (k7ddrphy_bitslip10[6]),
	.D8     (k7ddrphy_bitslip10[7]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),
	.T1     ((~k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
	.TCE    (1'd1),

	// Outputs.
	.OFB    (k7ddrphy_dqs_o_no_delay1),
	.OQ     (k7ddrphy1),
	.TQ     (k7ddrphy_dqs_t1)
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_27 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (3'd4),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_27 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dqs_inc_re)),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dqs_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dqs_o_delayed1),
	.ODATAIN  (k7ddrphy_dqs_o_no_delay1)
);

//------------------------------------------------------------------------------
// Instance IOBUFDS_1 of IOBUFDS Module.
//------------------------------------------------------------------------------
IOBUFDS IOBUFDS_1(
	// Inputs.
	.I   (k7ddrphy_dqs_o_delayed1),
	.T   (k7ddrphy_dqs_t1),

	// InOuts.
	.IO  (ddram_dqs_p[1]),
	.IOB (ddram_dqs_n[1])
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_28 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_28 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_bitslip20[0]),
	.D2     (k7ddrphy_bitslip20[1]),
	.D3     (k7ddrphy_bitslip20[2]),
	.D4     (k7ddrphy_bitslip20[3]),
	.D5     (k7ddrphy_bitslip20[4]),
	.D6     (k7ddrphy_bitslip20[5]),
	.D7     (k7ddrphy_bitslip20[6]),
	.D8     (k7ddrphy_bitslip20[7]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),
	.T1     ((~k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
	.TCE    (1'd1),

	// Outputs.
	.OFB    (k7ddrphy_dqs_o_no_delay2),
	.OQ     (k7ddrphy2),
	.TQ     (k7ddrphy_dqs_t2)
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_28 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (3'd4),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_28 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dqs_inc_re)),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dqs_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dqs_o_delayed2),
	.ODATAIN  (k7ddrphy_dqs_o_no_delay2)
);

//------------------------------------------------------------------------------
// Instance IOBUFDS_2 of IOBUFDS Module.
//------------------------------------------------------------------------------
IOBUFDS IOBUFDS_2(
	// Inputs.
	.I   (k7ddrphy_dqs_o_delayed2),
	.T   (k7ddrphy_dqs_t2),

	// InOuts.
	.IO  (ddram_dqs_p[2]),
	.IOB (ddram_dqs_n[2])
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_29 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_29 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_bitslip30[0]),
	.D2     (k7ddrphy_bitslip30[1]),
	.D3     (k7ddrphy_bitslip30[2]),
	.D4     (k7ddrphy_bitslip30[3]),
	.D5     (k7ddrphy_bitslip30[4]),
	.D6     (k7ddrphy_bitslip30[5]),
	.D7     (k7ddrphy_bitslip30[6]),
	.D8     (k7ddrphy_bitslip30[7]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),
	.T1     ((~k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
	.TCE    (1'd1),

	// Outputs.
	.OFB    (k7ddrphy_dqs_o_no_delay3),
	.OQ     (k7ddrphy3),
	.TQ     (k7ddrphy_dqs_t3)
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_29 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (3'd4),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_29 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dqs_inc_re)),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dqs_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dqs_o_delayed3),
	.ODATAIN  (k7ddrphy_dqs_o_no_delay3)
);

//------------------------------------------------------------------------------
// Instance IOBUFDS_3 of IOBUFDS Module.
//------------------------------------------------------------------------------
IOBUFDS IOBUFDS_3(
	// Inputs.
	.I   (k7ddrphy_dqs_o_delayed3),
	.T   (k7ddrphy_dqs_t3),

	// InOuts.
	.IO  (ddram_dqs_p[3]),
	.IOB (ddram_dqs_n[3])
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_30 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_30 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_bitslip01[0]),
	.D2     (k7ddrphy_bitslip01[1]),
	.D3     (k7ddrphy_bitslip01[2]),
	.D4     (k7ddrphy_bitslip01[3]),
	.D5     (k7ddrphy_bitslip01[4]),
	.D6     (k7ddrphy_bitslip01[5]),
	.D7     (k7ddrphy_bitslip01[6]),
	.D8     (k7ddrphy_bitslip01[7]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.OQ     (k7ddrphy_dm_o_nodelay0)
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_30 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_30 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_inc_re)),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (ddram_dm[0]),
	.ODATAIN  (k7ddrphy_dm_o_nodelay0)
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_31 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_31 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_bitslip11[0]),
	.D2     (k7ddrphy_bitslip11[1]),
	.D3     (k7ddrphy_bitslip11[2]),
	.D4     (k7ddrphy_bitslip11[3]),
	.D5     (k7ddrphy_bitslip11[4]),
	.D6     (k7ddrphy_bitslip11[5]),
	.D7     (k7ddrphy_bitslip11[6]),
	.D8     (k7ddrphy_bitslip11[7]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.OQ     (k7ddrphy_dm_o_nodelay1)
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_31 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_31 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_inc_re)),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (ddram_dm[1]),
	.ODATAIN  (k7ddrphy_dm_o_nodelay1)
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_32 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_32 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_bitslip21[0]),
	.D2     (k7ddrphy_bitslip21[1]),
	.D3     (k7ddrphy_bitslip21[2]),
	.D4     (k7ddrphy_bitslip21[3]),
	.D5     (k7ddrphy_bitslip21[4]),
	.D6     (k7ddrphy_bitslip21[5]),
	.D7     (k7ddrphy_bitslip21[6]),
	.D8     (k7ddrphy_bitslip21[7]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.OQ     (k7ddrphy_dm_o_nodelay2)
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_32 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_32 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_inc_re)),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (ddram_dm[2]),
	.ODATAIN  (k7ddrphy_dm_o_nodelay2)
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_33 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_33 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_bitslip31[0]),
	.D2     (k7ddrphy_bitslip31[1]),
	.D3     (k7ddrphy_bitslip31[2]),
	.D4     (k7ddrphy_bitslip31[3]),
	.D5     (k7ddrphy_bitslip31[4]),
	.D6     (k7ddrphy_bitslip31[5]),
	.D7     (k7ddrphy_bitslip31[6]),
	.D8     (k7ddrphy_bitslip31[7]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.OQ     (k7ddrphy_dm_o_nodelay3)
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_33 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_33 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_inc_re)),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (ddram_dm[3]),
	.ODATAIN  (k7ddrphy_dm_o_nodelay3)
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_34 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_34 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_bitslip02[0]),
	.D2     (k7ddrphy_bitslip02[1]),
	.D3     (k7ddrphy_bitslip02[2]),
	.D4     (k7ddrphy_bitslip02[3]),
	.D5     (k7ddrphy_bitslip02[4]),
	.D6     (k7ddrphy_bitslip02[5]),
	.D7     (k7ddrphy_bitslip02[6]),
	.D8     (k7ddrphy_bitslip02[7]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),
	.T1     ((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
	.TCE    (1'd1),

	// Outputs.
	.OQ     (k7ddrphy_dq_o_nodelay0),
	.TQ     (k7ddrphy_dq_t0)
);

//------------------------------------------------------------------------------
// Instance ISERDESE2 of ISERDESE2 Module.
//------------------------------------------------------------------------------
ISERDESE2 #(
	// Parameters.
	.DATA_RATE      ("DDR"),
	.DATA_WIDTH     (4'd8),
	.INTERFACE_TYPE ("NETWORKING"),
	.IOBDELAY       ("IFD"),
	.NUM_CE         (1'd1),
	.SERDES_MODE    ("MASTER")
) ISERDESE2 (
	// Inputs.
	.BITSLIP (1'd0),
	.CE1     (1'd1),
	.CLK     (sys4x_clk),
	.CLKB    ((~sys4x_clk)),
	.CLKDIV  (sys_clk),
	.DDLY    (k7ddrphy_dq_i_delayed0),
	.RST     ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.Q1      (k7ddrphy_bitslip03[7]),
	.Q2      (k7ddrphy_bitslip03[6]),
	.Q3      (k7ddrphy_bitslip03[5]),
	.Q4      (k7ddrphy_bitslip03[4]),
	.Q5      (k7ddrphy_bitslip03[3]),
	.Q6      (k7ddrphy_bitslip03[2]),
	.Q7      (k7ddrphy_bitslip03[1]),
	.Q8      (k7ddrphy_bitslip03[0])
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_34 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_34 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_inc_re)),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_o_delayed0),
	.ODATAIN  (k7ddrphy_dq_o_nodelay0)
);

//------------------------------------------------------------------------------
// Instance IDELAYE2 of IDELAYE2 Module.
//------------------------------------------------------------------------------
IDELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("IDATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.IDELAY_TYPE           ("VARIABLE"),
	.IDELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) IDELAYE2 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_inc_re)),
	.IDATAIN  (k7ddrphy_dq_i_nodelay0),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_i_delayed0)
);

//------------------------------------------------------------------------------
// Instance IOBUF of IOBUF Module.
//------------------------------------------------------------------------------
IOBUF IOBUF(
	// Inputs.
	.I  (k7ddrphy_dq_o_delayed0),
	.T  (k7ddrphy_dq_t0),

	// Outputs.
	.O  (k7ddrphy_dq_i_nodelay0),

	// InOuts.
	.IO (ddram_dq[0])
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_35 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_35 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_bitslip12[0]),
	.D2     (k7ddrphy_bitslip12[1]),
	.D3     (k7ddrphy_bitslip12[2]),
	.D4     (k7ddrphy_bitslip12[3]),
	.D5     (k7ddrphy_bitslip12[4]),
	.D6     (k7ddrphy_bitslip12[5]),
	.D7     (k7ddrphy_bitslip12[6]),
	.D8     (k7ddrphy_bitslip12[7]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),
	.T1     ((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
	.TCE    (1'd1),

	// Outputs.
	.OQ     (k7ddrphy_dq_o_nodelay1),
	.TQ     (k7ddrphy_dq_t1)
);

//------------------------------------------------------------------------------
// Instance ISERDESE2_1 of ISERDESE2 Module.
//------------------------------------------------------------------------------
ISERDESE2 #(
	// Parameters.
	.DATA_RATE      ("DDR"),
	.DATA_WIDTH     (4'd8),
	.INTERFACE_TYPE ("NETWORKING"),
	.IOBDELAY       ("IFD"),
	.NUM_CE         (1'd1),
	.SERDES_MODE    ("MASTER")
) ISERDESE2_1 (
	// Inputs.
	.BITSLIP (1'd0),
	.CE1     (1'd1),
	.CLK     (sys4x_clk),
	.CLKB    ((~sys4x_clk)),
	.CLKDIV  (sys_clk),
	.DDLY    (k7ddrphy_dq_i_delayed1),
	.RST     ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.Q1      (k7ddrphy_bitslip13[7]),
	.Q2      (k7ddrphy_bitslip13[6]),
	.Q3      (k7ddrphy_bitslip13[5]),
	.Q4      (k7ddrphy_bitslip13[4]),
	.Q5      (k7ddrphy_bitslip13[3]),
	.Q6      (k7ddrphy_bitslip13[2]),
	.Q7      (k7ddrphy_bitslip13[1]),
	.Q8      (k7ddrphy_bitslip13[0])
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_35 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_35 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_inc_re)),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_o_delayed1),
	.ODATAIN  (k7ddrphy_dq_o_nodelay1)
);

//------------------------------------------------------------------------------
// Instance IDELAYE2_1 of IDELAYE2 Module.
//------------------------------------------------------------------------------
IDELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("IDATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.IDELAY_TYPE           ("VARIABLE"),
	.IDELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) IDELAYE2_1 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_inc_re)),
	.IDATAIN  (k7ddrphy_dq_i_nodelay1),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_i_delayed1)
);

//------------------------------------------------------------------------------
// Instance IOBUF_1 of IOBUF Module.
//------------------------------------------------------------------------------
IOBUF IOBUF_1(
	// Inputs.
	.I  (k7ddrphy_dq_o_delayed1),
	.T  (k7ddrphy_dq_t1),

	// Outputs.
	.O  (k7ddrphy_dq_i_nodelay1),

	// InOuts.
	.IO (ddram_dq[1])
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_36 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_36 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_bitslip22[0]),
	.D2     (k7ddrphy_bitslip22[1]),
	.D3     (k7ddrphy_bitslip22[2]),
	.D4     (k7ddrphy_bitslip22[3]),
	.D5     (k7ddrphy_bitslip22[4]),
	.D6     (k7ddrphy_bitslip22[5]),
	.D7     (k7ddrphy_bitslip22[6]),
	.D8     (k7ddrphy_bitslip22[7]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),
	.T1     ((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
	.TCE    (1'd1),

	// Outputs.
	.OQ     (k7ddrphy_dq_o_nodelay2),
	.TQ     (k7ddrphy_dq_t2)
);

//------------------------------------------------------------------------------
// Instance ISERDESE2_2 of ISERDESE2 Module.
//------------------------------------------------------------------------------
ISERDESE2 #(
	// Parameters.
	.DATA_RATE      ("DDR"),
	.DATA_WIDTH     (4'd8),
	.INTERFACE_TYPE ("NETWORKING"),
	.IOBDELAY       ("IFD"),
	.NUM_CE         (1'd1),
	.SERDES_MODE    ("MASTER")
) ISERDESE2_2 (
	// Inputs.
	.BITSLIP (1'd0),
	.CE1     (1'd1),
	.CLK     (sys4x_clk),
	.CLKB    ((~sys4x_clk)),
	.CLKDIV  (sys_clk),
	.DDLY    (k7ddrphy_dq_i_delayed2),
	.RST     ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.Q1      (k7ddrphy_bitslip23[7]),
	.Q2      (k7ddrphy_bitslip23[6]),
	.Q3      (k7ddrphy_bitslip23[5]),
	.Q4      (k7ddrphy_bitslip23[4]),
	.Q5      (k7ddrphy_bitslip23[3]),
	.Q6      (k7ddrphy_bitslip23[2]),
	.Q7      (k7ddrphy_bitslip23[1]),
	.Q8      (k7ddrphy_bitslip23[0])
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_36 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_36 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_inc_re)),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_o_delayed2),
	.ODATAIN  (k7ddrphy_dq_o_nodelay2)
);

//------------------------------------------------------------------------------
// Instance IDELAYE2_2 of IDELAYE2 Module.
//------------------------------------------------------------------------------
IDELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("IDATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.IDELAY_TYPE           ("VARIABLE"),
	.IDELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) IDELAYE2_2 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_inc_re)),
	.IDATAIN  (k7ddrphy_dq_i_nodelay2),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_i_delayed2)
);

//------------------------------------------------------------------------------
// Instance IOBUF_2 of IOBUF Module.
//------------------------------------------------------------------------------
IOBUF IOBUF_2(
	// Inputs.
	.I  (k7ddrphy_dq_o_delayed2),
	.T  (k7ddrphy_dq_t2),

	// Outputs.
	.O  (k7ddrphy_dq_i_nodelay2),

	// InOuts.
	.IO (ddram_dq[2])
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_37 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_37 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_bitslip32[0]),
	.D2     (k7ddrphy_bitslip32[1]),
	.D3     (k7ddrphy_bitslip32[2]),
	.D4     (k7ddrphy_bitslip32[3]),
	.D5     (k7ddrphy_bitslip32[4]),
	.D6     (k7ddrphy_bitslip32[5]),
	.D7     (k7ddrphy_bitslip32[6]),
	.D8     (k7ddrphy_bitslip32[7]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),
	.T1     ((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
	.TCE    (1'd1),

	// Outputs.
	.OQ     (k7ddrphy_dq_o_nodelay3),
	.TQ     (k7ddrphy_dq_t3)
);

//------------------------------------------------------------------------------
// Instance ISERDESE2_3 of ISERDESE2 Module.
//------------------------------------------------------------------------------
ISERDESE2 #(
	// Parameters.
	.DATA_RATE      ("DDR"),
	.DATA_WIDTH     (4'd8),
	.INTERFACE_TYPE ("NETWORKING"),
	.IOBDELAY       ("IFD"),
	.NUM_CE         (1'd1),
	.SERDES_MODE    ("MASTER")
) ISERDESE2_3 (
	// Inputs.
	.BITSLIP (1'd0),
	.CE1     (1'd1),
	.CLK     (sys4x_clk),
	.CLKB    ((~sys4x_clk)),
	.CLKDIV  (sys_clk),
	.DDLY    (k7ddrphy_dq_i_delayed3),
	.RST     ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.Q1      (k7ddrphy_bitslip33[7]),
	.Q2      (k7ddrphy_bitslip33[6]),
	.Q3      (k7ddrphy_bitslip33[5]),
	.Q4      (k7ddrphy_bitslip33[4]),
	.Q5      (k7ddrphy_bitslip33[3]),
	.Q6      (k7ddrphy_bitslip33[2]),
	.Q7      (k7ddrphy_bitslip33[1]),
	.Q8      (k7ddrphy_bitslip33[0])
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_37 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_37 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_inc_re)),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_o_delayed3),
	.ODATAIN  (k7ddrphy_dq_o_nodelay3)
);

//------------------------------------------------------------------------------
// Instance IDELAYE2_3 of IDELAYE2 Module.
//------------------------------------------------------------------------------
IDELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("IDATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.IDELAY_TYPE           ("VARIABLE"),
	.IDELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) IDELAYE2_3 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_inc_re)),
	.IDATAIN  (k7ddrphy_dq_i_nodelay3),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_i_delayed3)
);

//------------------------------------------------------------------------------
// Instance IOBUF_3 of IOBUF Module.
//------------------------------------------------------------------------------
IOBUF IOBUF_3(
	// Inputs.
	.I  (k7ddrphy_dq_o_delayed3),
	.T  (k7ddrphy_dq_t3),

	// Outputs.
	.O  (k7ddrphy_dq_i_nodelay3),

	// InOuts.
	.IO (ddram_dq[3])
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_38 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_38 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_bitslip40[0]),
	.D2     (k7ddrphy_bitslip40[1]),
	.D3     (k7ddrphy_bitslip40[2]),
	.D4     (k7ddrphy_bitslip40[3]),
	.D5     (k7ddrphy_bitslip40[4]),
	.D6     (k7ddrphy_bitslip40[5]),
	.D7     (k7ddrphy_bitslip40[6]),
	.D8     (k7ddrphy_bitslip40[7]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),
	.T1     ((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
	.TCE    (1'd1),

	// Outputs.
	.OQ     (k7ddrphy_dq_o_nodelay4),
	.TQ     (k7ddrphy_dq_t4)
);

//------------------------------------------------------------------------------
// Instance ISERDESE2_4 of ISERDESE2 Module.
//------------------------------------------------------------------------------
ISERDESE2 #(
	// Parameters.
	.DATA_RATE      ("DDR"),
	.DATA_WIDTH     (4'd8),
	.INTERFACE_TYPE ("NETWORKING"),
	.IOBDELAY       ("IFD"),
	.NUM_CE         (1'd1),
	.SERDES_MODE    ("MASTER")
) ISERDESE2_4 (
	// Inputs.
	.BITSLIP (1'd0),
	.CE1     (1'd1),
	.CLK     (sys4x_clk),
	.CLKB    ((~sys4x_clk)),
	.CLKDIV  (sys_clk),
	.DDLY    (k7ddrphy_dq_i_delayed4),
	.RST     ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.Q1      (k7ddrphy_bitslip41[7]),
	.Q2      (k7ddrphy_bitslip41[6]),
	.Q3      (k7ddrphy_bitslip41[5]),
	.Q4      (k7ddrphy_bitslip41[4]),
	.Q5      (k7ddrphy_bitslip41[3]),
	.Q6      (k7ddrphy_bitslip41[2]),
	.Q7      (k7ddrphy_bitslip41[1]),
	.Q8      (k7ddrphy_bitslip41[0])
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_38 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_38 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_inc_re)),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_o_delayed4),
	.ODATAIN  (k7ddrphy_dq_o_nodelay4)
);

//------------------------------------------------------------------------------
// Instance IDELAYE2_4 of IDELAYE2 Module.
//------------------------------------------------------------------------------
IDELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("IDATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.IDELAY_TYPE           ("VARIABLE"),
	.IDELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) IDELAYE2_4 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_inc_re)),
	.IDATAIN  (k7ddrphy_dq_i_nodelay4),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_i_delayed4)
);

//------------------------------------------------------------------------------
// Instance IOBUF_4 of IOBUF Module.
//------------------------------------------------------------------------------
IOBUF IOBUF_4(
	// Inputs.
	.I  (k7ddrphy_dq_o_delayed4),
	.T  (k7ddrphy_dq_t4),

	// Outputs.
	.O  (k7ddrphy_dq_i_nodelay4),

	// InOuts.
	.IO (ddram_dq[4])
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_39 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_39 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_bitslip50[0]),
	.D2     (k7ddrphy_bitslip50[1]),
	.D3     (k7ddrphy_bitslip50[2]),
	.D4     (k7ddrphy_bitslip50[3]),
	.D5     (k7ddrphy_bitslip50[4]),
	.D6     (k7ddrphy_bitslip50[5]),
	.D7     (k7ddrphy_bitslip50[6]),
	.D8     (k7ddrphy_bitslip50[7]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),
	.T1     ((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
	.TCE    (1'd1),

	// Outputs.
	.OQ     (k7ddrphy_dq_o_nodelay5),
	.TQ     (k7ddrphy_dq_t5)
);

//------------------------------------------------------------------------------
// Instance ISERDESE2_5 of ISERDESE2 Module.
//------------------------------------------------------------------------------
ISERDESE2 #(
	// Parameters.
	.DATA_RATE      ("DDR"),
	.DATA_WIDTH     (4'd8),
	.INTERFACE_TYPE ("NETWORKING"),
	.IOBDELAY       ("IFD"),
	.NUM_CE         (1'd1),
	.SERDES_MODE    ("MASTER")
) ISERDESE2_5 (
	// Inputs.
	.BITSLIP (1'd0),
	.CE1     (1'd1),
	.CLK     (sys4x_clk),
	.CLKB    ((~sys4x_clk)),
	.CLKDIV  (sys_clk),
	.DDLY    (k7ddrphy_dq_i_delayed5),
	.RST     ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.Q1      (k7ddrphy_bitslip51[7]),
	.Q2      (k7ddrphy_bitslip51[6]),
	.Q3      (k7ddrphy_bitslip51[5]),
	.Q4      (k7ddrphy_bitslip51[4]),
	.Q5      (k7ddrphy_bitslip51[3]),
	.Q6      (k7ddrphy_bitslip51[2]),
	.Q7      (k7ddrphy_bitslip51[1]),
	.Q8      (k7ddrphy_bitslip51[0])
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_39 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_39 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_inc_re)),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_o_delayed5),
	.ODATAIN  (k7ddrphy_dq_o_nodelay5)
);

//------------------------------------------------------------------------------
// Instance IDELAYE2_5 of IDELAYE2 Module.
//------------------------------------------------------------------------------
IDELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("IDATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.IDELAY_TYPE           ("VARIABLE"),
	.IDELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) IDELAYE2_5 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_inc_re)),
	.IDATAIN  (k7ddrphy_dq_i_nodelay5),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_i_delayed5)
);

//------------------------------------------------------------------------------
// Instance IOBUF_5 of IOBUF Module.
//------------------------------------------------------------------------------
IOBUF IOBUF_5(
	// Inputs.
	.I  (k7ddrphy_dq_o_delayed5),
	.T  (k7ddrphy_dq_t5),

	// Outputs.
	.O  (k7ddrphy_dq_i_nodelay5),

	// InOuts.
	.IO (ddram_dq[5])
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_40 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_40 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_bitslip60[0]),
	.D2     (k7ddrphy_bitslip60[1]),
	.D3     (k7ddrphy_bitslip60[2]),
	.D4     (k7ddrphy_bitslip60[3]),
	.D5     (k7ddrphy_bitslip60[4]),
	.D6     (k7ddrphy_bitslip60[5]),
	.D7     (k7ddrphy_bitslip60[6]),
	.D8     (k7ddrphy_bitslip60[7]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),
	.T1     ((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
	.TCE    (1'd1),

	// Outputs.
	.OQ     (k7ddrphy_dq_o_nodelay6),
	.TQ     (k7ddrphy_dq_t6)
);

//------------------------------------------------------------------------------
// Instance ISERDESE2_6 of ISERDESE2 Module.
//------------------------------------------------------------------------------
ISERDESE2 #(
	// Parameters.
	.DATA_RATE      ("DDR"),
	.DATA_WIDTH     (4'd8),
	.INTERFACE_TYPE ("NETWORKING"),
	.IOBDELAY       ("IFD"),
	.NUM_CE         (1'd1),
	.SERDES_MODE    ("MASTER")
) ISERDESE2_6 (
	// Inputs.
	.BITSLIP (1'd0),
	.CE1     (1'd1),
	.CLK     (sys4x_clk),
	.CLKB    ((~sys4x_clk)),
	.CLKDIV  (sys_clk),
	.DDLY    (k7ddrphy_dq_i_delayed6),
	.RST     ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.Q1      (k7ddrphy_bitslip61[7]),
	.Q2      (k7ddrphy_bitslip61[6]),
	.Q3      (k7ddrphy_bitslip61[5]),
	.Q4      (k7ddrphy_bitslip61[4]),
	.Q5      (k7ddrphy_bitslip61[3]),
	.Q6      (k7ddrphy_bitslip61[2]),
	.Q7      (k7ddrphy_bitslip61[1]),
	.Q8      (k7ddrphy_bitslip61[0])
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_40 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_40 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_inc_re)),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_o_delayed6),
	.ODATAIN  (k7ddrphy_dq_o_nodelay6)
);

//------------------------------------------------------------------------------
// Instance IDELAYE2_6 of IDELAYE2 Module.
//------------------------------------------------------------------------------
IDELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("IDATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.IDELAY_TYPE           ("VARIABLE"),
	.IDELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) IDELAYE2_6 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_inc_re)),
	.IDATAIN  (k7ddrphy_dq_i_nodelay6),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_i_delayed6)
);

//------------------------------------------------------------------------------
// Instance IOBUF_6 of IOBUF Module.
//------------------------------------------------------------------------------
IOBUF IOBUF_6(
	// Inputs.
	.I  (k7ddrphy_dq_o_delayed6),
	.T  (k7ddrphy_dq_t6),

	// Outputs.
	.O  (k7ddrphy_dq_i_nodelay6),

	// InOuts.
	.IO (ddram_dq[6])
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_41 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_41 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_bitslip70[0]),
	.D2     (k7ddrphy_bitslip70[1]),
	.D3     (k7ddrphy_bitslip70[2]),
	.D4     (k7ddrphy_bitslip70[3]),
	.D5     (k7ddrphy_bitslip70[4]),
	.D6     (k7ddrphy_bitslip70[5]),
	.D7     (k7ddrphy_bitslip70[6]),
	.D8     (k7ddrphy_bitslip70[7]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),
	.T1     ((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
	.TCE    (1'd1),

	// Outputs.
	.OQ     (k7ddrphy_dq_o_nodelay7),
	.TQ     (k7ddrphy_dq_t7)
);

//------------------------------------------------------------------------------
// Instance ISERDESE2_7 of ISERDESE2 Module.
//------------------------------------------------------------------------------
ISERDESE2 #(
	// Parameters.
	.DATA_RATE      ("DDR"),
	.DATA_WIDTH     (4'd8),
	.INTERFACE_TYPE ("NETWORKING"),
	.IOBDELAY       ("IFD"),
	.NUM_CE         (1'd1),
	.SERDES_MODE    ("MASTER")
) ISERDESE2_7 (
	// Inputs.
	.BITSLIP (1'd0),
	.CE1     (1'd1),
	.CLK     (sys4x_clk),
	.CLKB    ((~sys4x_clk)),
	.CLKDIV  (sys_clk),
	.DDLY    (k7ddrphy_dq_i_delayed7),
	.RST     ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.Q1      (k7ddrphy_bitslip71[7]),
	.Q2      (k7ddrphy_bitslip71[6]),
	.Q3      (k7ddrphy_bitslip71[5]),
	.Q4      (k7ddrphy_bitslip71[4]),
	.Q5      (k7ddrphy_bitslip71[3]),
	.Q6      (k7ddrphy_bitslip71[2]),
	.Q7      (k7ddrphy_bitslip71[1]),
	.Q8      (k7ddrphy_bitslip71[0])
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_41 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_41 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_inc_re)),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_o_delayed7),
	.ODATAIN  (k7ddrphy_dq_o_nodelay7)
);

//------------------------------------------------------------------------------
// Instance IDELAYE2_7 of IDELAYE2 Module.
//------------------------------------------------------------------------------
IDELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("IDATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.IDELAY_TYPE           ("VARIABLE"),
	.IDELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) IDELAYE2_7 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_inc_re)),
	.IDATAIN  (k7ddrphy_dq_i_nodelay7),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_i_delayed7)
);

//------------------------------------------------------------------------------
// Instance IOBUF_7 of IOBUF Module.
//------------------------------------------------------------------------------
IOBUF IOBUF_7(
	// Inputs.
	.I  (k7ddrphy_dq_o_delayed7),
	.T  (k7ddrphy_dq_t7),

	// Outputs.
	.O  (k7ddrphy_dq_i_nodelay7),

	// InOuts.
	.IO (ddram_dq[7])
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_42 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_42 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_bitslip80[0]),
	.D2     (k7ddrphy_bitslip80[1]),
	.D3     (k7ddrphy_bitslip80[2]),
	.D4     (k7ddrphy_bitslip80[3]),
	.D5     (k7ddrphy_bitslip80[4]),
	.D6     (k7ddrphy_bitslip80[5]),
	.D7     (k7ddrphy_bitslip80[6]),
	.D8     (k7ddrphy_bitslip80[7]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),
	.T1     ((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
	.TCE    (1'd1),

	// Outputs.
	.OQ     (k7ddrphy_dq_o_nodelay8),
	.TQ     (k7ddrphy_dq_t8)
);

//------------------------------------------------------------------------------
// Instance ISERDESE2_8 of ISERDESE2 Module.
//------------------------------------------------------------------------------
ISERDESE2 #(
	// Parameters.
	.DATA_RATE      ("DDR"),
	.DATA_WIDTH     (4'd8),
	.INTERFACE_TYPE ("NETWORKING"),
	.IOBDELAY       ("IFD"),
	.NUM_CE         (1'd1),
	.SERDES_MODE    ("MASTER")
) ISERDESE2_8 (
	// Inputs.
	.BITSLIP (1'd0),
	.CE1     (1'd1),
	.CLK     (sys4x_clk),
	.CLKB    ((~sys4x_clk)),
	.CLKDIV  (sys_clk),
	.DDLY    (k7ddrphy_dq_i_delayed8),
	.RST     ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.Q1      (k7ddrphy_bitslip81[7]),
	.Q2      (k7ddrphy_bitslip81[6]),
	.Q3      (k7ddrphy_bitslip81[5]),
	.Q4      (k7ddrphy_bitslip81[4]),
	.Q5      (k7ddrphy_bitslip81[3]),
	.Q6      (k7ddrphy_bitslip81[2]),
	.Q7      (k7ddrphy_bitslip81[1]),
	.Q8      (k7ddrphy_bitslip81[0])
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_42 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_42 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_inc_re)),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_o_delayed8),
	.ODATAIN  (k7ddrphy_dq_o_nodelay8)
);

//------------------------------------------------------------------------------
// Instance IDELAYE2_8 of IDELAYE2 Module.
//------------------------------------------------------------------------------
IDELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("IDATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.IDELAY_TYPE           ("VARIABLE"),
	.IDELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) IDELAYE2_8 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_inc_re)),
	.IDATAIN  (k7ddrphy_dq_i_nodelay8),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_i_delayed8)
);

//------------------------------------------------------------------------------
// Instance IOBUF_8 of IOBUF Module.
//------------------------------------------------------------------------------
IOBUF IOBUF_8(
	// Inputs.
	.I  (k7ddrphy_dq_o_delayed8),
	.T  (k7ddrphy_dq_t8),

	// Outputs.
	.O  (k7ddrphy_dq_i_nodelay8),

	// InOuts.
	.IO (ddram_dq[8])
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_43 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_43 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_bitslip90[0]),
	.D2     (k7ddrphy_bitslip90[1]),
	.D3     (k7ddrphy_bitslip90[2]),
	.D4     (k7ddrphy_bitslip90[3]),
	.D5     (k7ddrphy_bitslip90[4]),
	.D6     (k7ddrphy_bitslip90[5]),
	.D7     (k7ddrphy_bitslip90[6]),
	.D8     (k7ddrphy_bitslip90[7]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),
	.T1     ((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
	.TCE    (1'd1),

	// Outputs.
	.OQ     (k7ddrphy_dq_o_nodelay9),
	.TQ     (k7ddrphy_dq_t9)
);

//------------------------------------------------------------------------------
// Instance ISERDESE2_9 of ISERDESE2 Module.
//------------------------------------------------------------------------------
ISERDESE2 #(
	// Parameters.
	.DATA_RATE      ("DDR"),
	.DATA_WIDTH     (4'd8),
	.INTERFACE_TYPE ("NETWORKING"),
	.IOBDELAY       ("IFD"),
	.NUM_CE         (1'd1),
	.SERDES_MODE    ("MASTER")
) ISERDESE2_9 (
	// Inputs.
	.BITSLIP (1'd0),
	.CE1     (1'd1),
	.CLK     (sys4x_clk),
	.CLKB    ((~sys4x_clk)),
	.CLKDIV  (sys_clk),
	.DDLY    (k7ddrphy_dq_i_delayed9),
	.RST     ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.Q1      (k7ddrphy_bitslip91[7]),
	.Q2      (k7ddrphy_bitslip91[6]),
	.Q3      (k7ddrphy_bitslip91[5]),
	.Q4      (k7ddrphy_bitslip91[4]),
	.Q5      (k7ddrphy_bitslip91[3]),
	.Q6      (k7ddrphy_bitslip91[2]),
	.Q7      (k7ddrphy_bitslip91[1]),
	.Q8      (k7ddrphy_bitslip91[0])
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_43 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_43 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_inc_re)),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_o_delayed9),
	.ODATAIN  (k7ddrphy_dq_o_nodelay9)
);

//------------------------------------------------------------------------------
// Instance IDELAYE2_9 of IDELAYE2 Module.
//------------------------------------------------------------------------------
IDELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("IDATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.IDELAY_TYPE           ("VARIABLE"),
	.IDELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) IDELAYE2_9 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_inc_re)),
	.IDATAIN  (k7ddrphy_dq_i_nodelay9),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_i_delayed9)
);

//------------------------------------------------------------------------------
// Instance IOBUF_9 of IOBUF Module.
//------------------------------------------------------------------------------
IOBUF IOBUF_9(
	// Inputs.
	.I  (k7ddrphy_dq_o_delayed9),
	.T  (k7ddrphy_dq_t9),

	// Outputs.
	.O  (k7ddrphy_dq_i_nodelay9),

	// InOuts.
	.IO (ddram_dq[9])
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_44 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_44 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_bitslip100[0]),
	.D2     (k7ddrphy_bitslip100[1]),
	.D3     (k7ddrphy_bitslip100[2]),
	.D4     (k7ddrphy_bitslip100[3]),
	.D5     (k7ddrphy_bitslip100[4]),
	.D6     (k7ddrphy_bitslip100[5]),
	.D7     (k7ddrphy_bitslip100[6]),
	.D8     (k7ddrphy_bitslip100[7]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),
	.T1     ((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
	.TCE    (1'd1),

	// Outputs.
	.OQ     (k7ddrphy_dq_o_nodelay10),
	.TQ     (k7ddrphy_dq_t10)
);

//------------------------------------------------------------------------------
// Instance ISERDESE2_10 of ISERDESE2 Module.
//------------------------------------------------------------------------------
ISERDESE2 #(
	// Parameters.
	.DATA_RATE      ("DDR"),
	.DATA_WIDTH     (4'd8),
	.INTERFACE_TYPE ("NETWORKING"),
	.IOBDELAY       ("IFD"),
	.NUM_CE         (1'd1),
	.SERDES_MODE    ("MASTER")
) ISERDESE2_10 (
	// Inputs.
	.BITSLIP (1'd0),
	.CE1     (1'd1),
	.CLK     (sys4x_clk),
	.CLKB    ((~sys4x_clk)),
	.CLKDIV  (sys_clk),
	.DDLY    (k7ddrphy_dq_i_delayed10),
	.RST     ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.Q1      (k7ddrphy_bitslip101[7]),
	.Q2      (k7ddrphy_bitslip101[6]),
	.Q3      (k7ddrphy_bitslip101[5]),
	.Q4      (k7ddrphy_bitslip101[4]),
	.Q5      (k7ddrphy_bitslip101[3]),
	.Q6      (k7ddrphy_bitslip101[2]),
	.Q7      (k7ddrphy_bitslip101[1]),
	.Q8      (k7ddrphy_bitslip101[0])
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_44 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_44 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_inc_re)),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_o_delayed10),
	.ODATAIN  (k7ddrphy_dq_o_nodelay10)
);

//------------------------------------------------------------------------------
// Instance IDELAYE2_10 of IDELAYE2 Module.
//------------------------------------------------------------------------------
IDELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("IDATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.IDELAY_TYPE           ("VARIABLE"),
	.IDELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) IDELAYE2_10 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_inc_re)),
	.IDATAIN  (k7ddrphy_dq_i_nodelay10),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_i_delayed10)
);

//------------------------------------------------------------------------------
// Instance IOBUF_10 of IOBUF Module.
//------------------------------------------------------------------------------
IOBUF IOBUF_10(
	// Inputs.
	.I  (k7ddrphy_dq_o_delayed10),
	.T  (k7ddrphy_dq_t10),

	// Outputs.
	.O  (k7ddrphy_dq_i_nodelay10),

	// InOuts.
	.IO (ddram_dq[10])
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_45 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_45 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_bitslip110[0]),
	.D2     (k7ddrphy_bitslip110[1]),
	.D3     (k7ddrphy_bitslip110[2]),
	.D4     (k7ddrphy_bitslip110[3]),
	.D5     (k7ddrphy_bitslip110[4]),
	.D6     (k7ddrphy_bitslip110[5]),
	.D7     (k7ddrphy_bitslip110[6]),
	.D8     (k7ddrphy_bitslip110[7]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),
	.T1     ((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
	.TCE    (1'd1),

	// Outputs.
	.OQ     (k7ddrphy_dq_o_nodelay11),
	.TQ     (k7ddrphy_dq_t11)
);

//------------------------------------------------------------------------------
// Instance ISERDESE2_11 of ISERDESE2 Module.
//------------------------------------------------------------------------------
ISERDESE2 #(
	// Parameters.
	.DATA_RATE      ("DDR"),
	.DATA_WIDTH     (4'd8),
	.INTERFACE_TYPE ("NETWORKING"),
	.IOBDELAY       ("IFD"),
	.NUM_CE         (1'd1),
	.SERDES_MODE    ("MASTER")
) ISERDESE2_11 (
	// Inputs.
	.BITSLIP (1'd0),
	.CE1     (1'd1),
	.CLK     (sys4x_clk),
	.CLKB    ((~sys4x_clk)),
	.CLKDIV  (sys_clk),
	.DDLY    (k7ddrphy_dq_i_delayed11),
	.RST     ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.Q1      (k7ddrphy_bitslip111[7]),
	.Q2      (k7ddrphy_bitslip111[6]),
	.Q3      (k7ddrphy_bitslip111[5]),
	.Q4      (k7ddrphy_bitslip111[4]),
	.Q5      (k7ddrphy_bitslip111[3]),
	.Q6      (k7ddrphy_bitslip111[2]),
	.Q7      (k7ddrphy_bitslip111[1]),
	.Q8      (k7ddrphy_bitslip111[0])
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_45 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_45 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_inc_re)),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_o_delayed11),
	.ODATAIN  (k7ddrphy_dq_o_nodelay11)
);

//------------------------------------------------------------------------------
// Instance IDELAYE2_11 of IDELAYE2 Module.
//------------------------------------------------------------------------------
IDELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("IDATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.IDELAY_TYPE           ("VARIABLE"),
	.IDELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) IDELAYE2_11 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_inc_re)),
	.IDATAIN  (k7ddrphy_dq_i_nodelay11),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_i_delayed11)
);

//------------------------------------------------------------------------------
// Instance IOBUF_11 of IOBUF Module.
//------------------------------------------------------------------------------
IOBUF IOBUF_11(
	// Inputs.
	.I  (k7ddrphy_dq_o_delayed11),
	.T  (k7ddrphy_dq_t11),

	// Outputs.
	.O  (k7ddrphy_dq_i_nodelay11),

	// InOuts.
	.IO (ddram_dq[11])
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_46 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_46 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_bitslip120[0]),
	.D2     (k7ddrphy_bitslip120[1]),
	.D3     (k7ddrphy_bitslip120[2]),
	.D4     (k7ddrphy_bitslip120[3]),
	.D5     (k7ddrphy_bitslip120[4]),
	.D6     (k7ddrphy_bitslip120[5]),
	.D7     (k7ddrphy_bitslip120[6]),
	.D8     (k7ddrphy_bitslip120[7]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),
	.T1     ((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
	.TCE    (1'd1),

	// Outputs.
	.OQ     (k7ddrphy_dq_o_nodelay12),
	.TQ     (k7ddrphy_dq_t12)
);

//------------------------------------------------------------------------------
// Instance ISERDESE2_12 of ISERDESE2 Module.
//------------------------------------------------------------------------------
ISERDESE2 #(
	// Parameters.
	.DATA_RATE      ("DDR"),
	.DATA_WIDTH     (4'd8),
	.INTERFACE_TYPE ("NETWORKING"),
	.IOBDELAY       ("IFD"),
	.NUM_CE         (1'd1),
	.SERDES_MODE    ("MASTER")
) ISERDESE2_12 (
	// Inputs.
	.BITSLIP (1'd0),
	.CE1     (1'd1),
	.CLK     (sys4x_clk),
	.CLKB    ((~sys4x_clk)),
	.CLKDIV  (sys_clk),
	.DDLY    (k7ddrphy_dq_i_delayed12),
	.RST     ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.Q1      (k7ddrphy_bitslip121[7]),
	.Q2      (k7ddrphy_bitslip121[6]),
	.Q3      (k7ddrphy_bitslip121[5]),
	.Q4      (k7ddrphy_bitslip121[4]),
	.Q5      (k7ddrphy_bitslip121[3]),
	.Q6      (k7ddrphy_bitslip121[2]),
	.Q7      (k7ddrphy_bitslip121[1]),
	.Q8      (k7ddrphy_bitslip121[0])
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_46 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_46 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_inc_re)),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_o_delayed12),
	.ODATAIN  (k7ddrphy_dq_o_nodelay12)
);

//------------------------------------------------------------------------------
// Instance IDELAYE2_12 of IDELAYE2 Module.
//------------------------------------------------------------------------------
IDELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("IDATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.IDELAY_TYPE           ("VARIABLE"),
	.IDELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) IDELAYE2_12 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_inc_re)),
	.IDATAIN  (k7ddrphy_dq_i_nodelay12),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_i_delayed12)
);

//------------------------------------------------------------------------------
// Instance IOBUF_12 of IOBUF Module.
//------------------------------------------------------------------------------
IOBUF IOBUF_12(
	// Inputs.
	.I  (k7ddrphy_dq_o_delayed12),
	.T  (k7ddrphy_dq_t12),

	// Outputs.
	.O  (k7ddrphy_dq_i_nodelay12),

	// InOuts.
	.IO (ddram_dq[12])
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_47 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_47 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_bitslip130[0]),
	.D2     (k7ddrphy_bitslip130[1]),
	.D3     (k7ddrphy_bitslip130[2]),
	.D4     (k7ddrphy_bitslip130[3]),
	.D5     (k7ddrphy_bitslip130[4]),
	.D6     (k7ddrphy_bitslip130[5]),
	.D7     (k7ddrphy_bitslip130[6]),
	.D8     (k7ddrphy_bitslip130[7]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),
	.T1     ((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
	.TCE    (1'd1),

	// Outputs.
	.OQ     (k7ddrphy_dq_o_nodelay13),
	.TQ     (k7ddrphy_dq_t13)
);

//------------------------------------------------------------------------------
// Instance ISERDESE2_13 of ISERDESE2 Module.
//------------------------------------------------------------------------------
ISERDESE2 #(
	// Parameters.
	.DATA_RATE      ("DDR"),
	.DATA_WIDTH     (4'd8),
	.INTERFACE_TYPE ("NETWORKING"),
	.IOBDELAY       ("IFD"),
	.NUM_CE         (1'd1),
	.SERDES_MODE    ("MASTER")
) ISERDESE2_13 (
	// Inputs.
	.BITSLIP (1'd0),
	.CE1     (1'd1),
	.CLK     (sys4x_clk),
	.CLKB    ((~sys4x_clk)),
	.CLKDIV  (sys_clk),
	.DDLY    (k7ddrphy_dq_i_delayed13),
	.RST     ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.Q1      (k7ddrphy_bitslip131[7]),
	.Q2      (k7ddrphy_bitslip131[6]),
	.Q3      (k7ddrphy_bitslip131[5]),
	.Q4      (k7ddrphy_bitslip131[4]),
	.Q5      (k7ddrphy_bitslip131[3]),
	.Q6      (k7ddrphy_bitslip131[2]),
	.Q7      (k7ddrphy_bitslip131[1]),
	.Q8      (k7ddrphy_bitslip131[0])
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_47 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_47 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_inc_re)),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_o_delayed13),
	.ODATAIN  (k7ddrphy_dq_o_nodelay13)
);

//------------------------------------------------------------------------------
// Instance IDELAYE2_13 of IDELAYE2 Module.
//------------------------------------------------------------------------------
IDELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("IDATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.IDELAY_TYPE           ("VARIABLE"),
	.IDELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) IDELAYE2_13 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_inc_re)),
	.IDATAIN  (k7ddrphy_dq_i_nodelay13),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_i_delayed13)
);

//------------------------------------------------------------------------------
// Instance IOBUF_13 of IOBUF Module.
//------------------------------------------------------------------------------
IOBUF IOBUF_13(
	// Inputs.
	.I  (k7ddrphy_dq_o_delayed13),
	.T  (k7ddrphy_dq_t13),

	// Outputs.
	.O  (k7ddrphy_dq_i_nodelay13),

	// InOuts.
	.IO (ddram_dq[13])
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_48 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_48 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_bitslip140[0]),
	.D2     (k7ddrphy_bitslip140[1]),
	.D3     (k7ddrphy_bitslip140[2]),
	.D4     (k7ddrphy_bitslip140[3]),
	.D5     (k7ddrphy_bitslip140[4]),
	.D6     (k7ddrphy_bitslip140[5]),
	.D7     (k7ddrphy_bitslip140[6]),
	.D8     (k7ddrphy_bitslip140[7]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),
	.T1     ((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
	.TCE    (1'd1),

	// Outputs.
	.OQ     (k7ddrphy_dq_o_nodelay14),
	.TQ     (k7ddrphy_dq_t14)
);

//------------------------------------------------------------------------------
// Instance ISERDESE2_14 of ISERDESE2 Module.
//------------------------------------------------------------------------------
ISERDESE2 #(
	// Parameters.
	.DATA_RATE      ("DDR"),
	.DATA_WIDTH     (4'd8),
	.INTERFACE_TYPE ("NETWORKING"),
	.IOBDELAY       ("IFD"),
	.NUM_CE         (1'd1),
	.SERDES_MODE    ("MASTER")
) ISERDESE2_14 (
	// Inputs.
	.BITSLIP (1'd0),
	.CE1     (1'd1),
	.CLK     (sys4x_clk),
	.CLKB    ((~sys4x_clk)),
	.CLKDIV  (sys_clk),
	.DDLY    (k7ddrphy_dq_i_delayed14),
	.RST     ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.Q1      (k7ddrphy_bitslip141[7]),
	.Q2      (k7ddrphy_bitslip141[6]),
	.Q3      (k7ddrphy_bitslip141[5]),
	.Q4      (k7ddrphy_bitslip141[4]),
	.Q5      (k7ddrphy_bitslip141[3]),
	.Q6      (k7ddrphy_bitslip141[2]),
	.Q7      (k7ddrphy_bitslip141[1]),
	.Q8      (k7ddrphy_bitslip141[0])
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_48 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_48 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_inc_re)),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_o_delayed14),
	.ODATAIN  (k7ddrphy_dq_o_nodelay14)
);

//------------------------------------------------------------------------------
// Instance IDELAYE2_14 of IDELAYE2 Module.
//------------------------------------------------------------------------------
IDELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("IDATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.IDELAY_TYPE           ("VARIABLE"),
	.IDELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) IDELAYE2_14 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_inc_re)),
	.IDATAIN  (k7ddrphy_dq_i_nodelay14),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_i_delayed14)
);

//------------------------------------------------------------------------------
// Instance IOBUF_14 of IOBUF Module.
//------------------------------------------------------------------------------
IOBUF IOBUF_14(
	// Inputs.
	.I  (k7ddrphy_dq_o_delayed14),
	.T  (k7ddrphy_dq_t14),

	// Outputs.
	.O  (k7ddrphy_dq_i_nodelay14),

	// InOuts.
	.IO (ddram_dq[14])
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_49 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_49 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_bitslip150[0]),
	.D2     (k7ddrphy_bitslip150[1]),
	.D3     (k7ddrphy_bitslip150[2]),
	.D4     (k7ddrphy_bitslip150[3]),
	.D5     (k7ddrphy_bitslip150[4]),
	.D6     (k7ddrphy_bitslip150[5]),
	.D7     (k7ddrphy_bitslip150[6]),
	.D8     (k7ddrphy_bitslip150[7]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),
	.T1     ((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
	.TCE    (1'd1),

	// Outputs.
	.OQ     (k7ddrphy_dq_o_nodelay15),
	.TQ     (k7ddrphy_dq_t15)
);

//------------------------------------------------------------------------------
// Instance ISERDESE2_15 of ISERDESE2 Module.
//------------------------------------------------------------------------------
ISERDESE2 #(
	// Parameters.
	.DATA_RATE      ("DDR"),
	.DATA_WIDTH     (4'd8),
	.INTERFACE_TYPE ("NETWORKING"),
	.IOBDELAY       ("IFD"),
	.NUM_CE         (1'd1),
	.SERDES_MODE    ("MASTER")
) ISERDESE2_15 (
	// Inputs.
	.BITSLIP (1'd0),
	.CE1     (1'd1),
	.CLK     (sys4x_clk),
	.CLKB    ((~sys4x_clk)),
	.CLKDIV  (sys_clk),
	.DDLY    (k7ddrphy_dq_i_delayed15),
	.RST     ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.Q1      (k7ddrphy_bitslip151[7]),
	.Q2      (k7ddrphy_bitslip151[6]),
	.Q3      (k7ddrphy_bitslip151[5]),
	.Q4      (k7ddrphy_bitslip151[4]),
	.Q5      (k7ddrphy_bitslip151[3]),
	.Q6      (k7ddrphy_bitslip151[2]),
	.Q7      (k7ddrphy_bitslip151[1]),
	.Q8      (k7ddrphy_bitslip151[0])
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_49 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_49 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_inc_re)),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_o_delayed15),
	.ODATAIN  (k7ddrphy_dq_o_nodelay15)
);

//------------------------------------------------------------------------------
// Instance IDELAYE2_15 of IDELAYE2 Module.
//------------------------------------------------------------------------------
IDELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("IDATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.IDELAY_TYPE           ("VARIABLE"),
	.IDELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) IDELAYE2_15 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_inc_re)),
	.IDATAIN  (k7ddrphy_dq_i_nodelay15),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_i_delayed15)
);

//------------------------------------------------------------------------------
// Instance IOBUF_15 of IOBUF Module.
//------------------------------------------------------------------------------
IOBUF IOBUF_15(
	// Inputs.
	.I  (k7ddrphy_dq_o_delayed15),
	.T  (k7ddrphy_dq_t15),

	// Outputs.
	.O  (k7ddrphy_dq_i_nodelay15),

	// InOuts.
	.IO (ddram_dq[15])
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_50 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_50 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_bitslip160[0]),
	.D2     (k7ddrphy_bitslip160[1]),
	.D3     (k7ddrphy_bitslip160[2]),
	.D4     (k7ddrphy_bitslip160[3]),
	.D5     (k7ddrphy_bitslip160[4]),
	.D6     (k7ddrphy_bitslip160[5]),
	.D7     (k7ddrphy_bitslip160[6]),
	.D8     (k7ddrphy_bitslip160[7]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),
	.T1     ((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
	.TCE    (1'd1),

	// Outputs.
	.OQ     (k7ddrphy_dq_o_nodelay16),
	.TQ     (k7ddrphy_dq_t16)
);

//------------------------------------------------------------------------------
// Instance ISERDESE2_16 of ISERDESE2 Module.
//------------------------------------------------------------------------------
ISERDESE2 #(
	// Parameters.
	.DATA_RATE      ("DDR"),
	.DATA_WIDTH     (4'd8),
	.INTERFACE_TYPE ("NETWORKING"),
	.IOBDELAY       ("IFD"),
	.NUM_CE         (1'd1),
	.SERDES_MODE    ("MASTER")
) ISERDESE2_16 (
	// Inputs.
	.BITSLIP (1'd0),
	.CE1     (1'd1),
	.CLK     (sys4x_clk),
	.CLKB    ((~sys4x_clk)),
	.CLKDIV  (sys_clk),
	.DDLY    (k7ddrphy_dq_i_delayed16),
	.RST     ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.Q1      (k7ddrphy_bitslip161[7]),
	.Q2      (k7ddrphy_bitslip161[6]),
	.Q3      (k7ddrphy_bitslip161[5]),
	.Q4      (k7ddrphy_bitslip161[4]),
	.Q5      (k7ddrphy_bitslip161[3]),
	.Q6      (k7ddrphy_bitslip161[2]),
	.Q7      (k7ddrphy_bitslip161[1]),
	.Q8      (k7ddrphy_bitslip161[0])
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_50 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_50 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_inc_re)),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_o_delayed16),
	.ODATAIN  (k7ddrphy_dq_o_nodelay16)
);

//------------------------------------------------------------------------------
// Instance IDELAYE2_16 of IDELAYE2 Module.
//------------------------------------------------------------------------------
IDELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("IDATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.IDELAY_TYPE           ("VARIABLE"),
	.IDELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) IDELAYE2_16 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_inc_re)),
	.IDATAIN  (k7ddrphy_dq_i_nodelay16),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_i_delayed16)
);

//------------------------------------------------------------------------------
// Instance IOBUF_16 of IOBUF Module.
//------------------------------------------------------------------------------
IOBUF IOBUF_16(
	// Inputs.
	.I  (k7ddrphy_dq_o_delayed16),
	.T  (k7ddrphy_dq_t16),

	// Outputs.
	.O  (k7ddrphy_dq_i_nodelay16),

	// InOuts.
	.IO (ddram_dq[16])
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_51 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_51 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_bitslip170[0]),
	.D2     (k7ddrphy_bitslip170[1]),
	.D3     (k7ddrphy_bitslip170[2]),
	.D4     (k7ddrphy_bitslip170[3]),
	.D5     (k7ddrphy_bitslip170[4]),
	.D6     (k7ddrphy_bitslip170[5]),
	.D7     (k7ddrphy_bitslip170[6]),
	.D8     (k7ddrphy_bitslip170[7]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),
	.T1     ((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
	.TCE    (1'd1),

	// Outputs.
	.OQ     (k7ddrphy_dq_o_nodelay17),
	.TQ     (k7ddrphy_dq_t17)
);

//------------------------------------------------------------------------------
// Instance ISERDESE2_17 of ISERDESE2 Module.
//------------------------------------------------------------------------------
ISERDESE2 #(
	// Parameters.
	.DATA_RATE      ("DDR"),
	.DATA_WIDTH     (4'd8),
	.INTERFACE_TYPE ("NETWORKING"),
	.IOBDELAY       ("IFD"),
	.NUM_CE         (1'd1),
	.SERDES_MODE    ("MASTER")
) ISERDESE2_17 (
	// Inputs.
	.BITSLIP (1'd0),
	.CE1     (1'd1),
	.CLK     (sys4x_clk),
	.CLKB    ((~sys4x_clk)),
	.CLKDIV  (sys_clk),
	.DDLY    (k7ddrphy_dq_i_delayed17),
	.RST     ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.Q1      (k7ddrphy_bitslip171[7]),
	.Q2      (k7ddrphy_bitslip171[6]),
	.Q3      (k7ddrphy_bitslip171[5]),
	.Q4      (k7ddrphy_bitslip171[4]),
	.Q5      (k7ddrphy_bitslip171[3]),
	.Q6      (k7ddrphy_bitslip171[2]),
	.Q7      (k7ddrphy_bitslip171[1]),
	.Q8      (k7ddrphy_bitslip171[0])
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_51 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_51 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_inc_re)),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_o_delayed17),
	.ODATAIN  (k7ddrphy_dq_o_nodelay17)
);

//------------------------------------------------------------------------------
// Instance IDELAYE2_17 of IDELAYE2 Module.
//------------------------------------------------------------------------------
IDELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("IDATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.IDELAY_TYPE           ("VARIABLE"),
	.IDELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) IDELAYE2_17 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_inc_re)),
	.IDATAIN  (k7ddrphy_dq_i_nodelay17),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_i_delayed17)
);

//------------------------------------------------------------------------------
// Instance IOBUF_17 of IOBUF Module.
//------------------------------------------------------------------------------
IOBUF IOBUF_17(
	// Inputs.
	.I  (k7ddrphy_dq_o_delayed17),
	.T  (k7ddrphy_dq_t17),

	// Outputs.
	.O  (k7ddrphy_dq_i_nodelay17),

	// InOuts.
	.IO (ddram_dq[17])
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_52 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_52 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_bitslip180[0]),
	.D2     (k7ddrphy_bitslip180[1]),
	.D3     (k7ddrphy_bitslip180[2]),
	.D4     (k7ddrphy_bitslip180[3]),
	.D5     (k7ddrphy_bitslip180[4]),
	.D6     (k7ddrphy_bitslip180[5]),
	.D7     (k7ddrphy_bitslip180[6]),
	.D8     (k7ddrphy_bitslip180[7]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),
	.T1     ((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
	.TCE    (1'd1),

	// Outputs.
	.OQ     (k7ddrphy_dq_o_nodelay18),
	.TQ     (k7ddrphy_dq_t18)
);

//------------------------------------------------------------------------------
// Instance ISERDESE2_18 of ISERDESE2 Module.
//------------------------------------------------------------------------------
ISERDESE2 #(
	// Parameters.
	.DATA_RATE      ("DDR"),
	.DATA_WIDTH     (4'd8),
	.INTERFACE_TYPE ("NETWORKING"),
	.IOBDELAY       ("IFD"),
	.NUM_CE         (1'd1),
	.SERDES_MODE    ("MASTER")
) ISERDESE2_18 (
	// Inputs.
	.BITSLIP (1'd0),
	.CE1     (1'd1),
	.CLK     (sys4x_clk),
	.CLKB    ((~sys4x_clk)),
	.CLKDIV  (sys_clk),
	.DDLY    (k7ddrphy_dq_i_delayed18),
	.RST     ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.Q1      (k7ddrphy_bitslip181[7]),
	.Q2      (k7ddrphy_bitslip181[6]),
	.Q3      (k7ddrphy_bitslip181[5]),
	.Q4      (k7ddrphy_bitslip181[4]),
	.Q5      (k7ddrphy_bitslip181[3]),
	.Q6      (k7ddrphy_bitslip181[2]),
	.Q7      (k7ddrphy_bitslip181[1]),
	.Q8      (k7ddrphy_bitslip181[0])
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_52 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_52 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_inc_re)),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_o_delayed18),
	.ODATAIN  (k7ddrphy_dq_o_nodelay18)
);

//------------------------------------------------------------------------------
// Instance IDELAYE2_18 of IDELAYE2 Module.
//------------------------------------------------------------------------------
IDELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("IDATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.IDELAY_TYPE           ("VARIABLE"),
	.IDELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) IDELAYE2_18 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_inc_re)),
	.IDATAIN  (k7ddrphy_dq_i_nodelay18),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_i_delayed18)
);

//------------------------------------------------------------------------------
// Instance IOBUF_18 of IOBUF Module.
//------------------------------------------------------------------------------
IOBUF IOBUF_18(
	// Inputs.
	.I  (k7ddrphy_dq_o_delayed18),
	.T  (k7ddrphy_dq_t18),

	// Outputs.
	.O  (k7ddrphy_dq_i_nodelay18),

	// InOuts.
	.IO (ddram_dq[18])
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_53 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_53 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_bitslip190[0]),
	.D2     (k7ddrphy_bitslip190[1]),
	.D3     (k7ddrphy_bitslip190[2]),
	.D4     (k7ddrphy_bitslip190[3]),
	.D5     (k7ddrphy_bitslip190[4]),
	.D6     (k7ddrphy_bitslip190[5]),
	.D7     (k7ddrphy_bitslip190[6]),
	.D8     (k7ddrphy_bitslip190[7]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),
	.T1     ((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
	.TCE    (1'd1),

	// Outputs.
	.OQ     (k7ddrphy_dq_o_nodelay19),
	.TQ     (k7ddrphy_dq_t19)
);

//------------------------------------------------------------------------------
// Instance ISERDESE2_19 of ISERDESE2 Module.
//------------------------------------------------------------------------------
ISERDESE2 #(
	// Parameters.
	.DATA_RATE      ("DDR"),
	.DATA_WIDTH     (4'd8),
	.INTERFACE_TYPE ("NETWORKING"),
	.IOBDELAY       ("IFD"),
	.NUM_CE         (1'd1),
	.SERDES_MODE    ("MASTER")
) ISERDESE2_19 (
	// Inputs.
	.BITSLIP (1'd0),
	.CE1     (1'd1),
	.CLK     (sys4x_clk),
	.CLKB    ((~sys4x_clk)),
	.CLKDIV  (sys_clk),
	.DDLY    (k7ddrphy_dq_i_delayed19),
	.RST     ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.Q1      (k7ddrphy_bitslip191[7]),
	.Q2      (k7ddrphy_bitslip191[6]),
	.Q3      (k7ddrphy_bitslip191[5]),
	.Q4      (k7ddrphy_bitslip191[4]),
	.Q5      (k7ddrphy_bitslip191[3]),
	.Q6      (k7ddrphy_bitslip191[2]),
	.Q7      (k7ddrphy_bitslip191[1]),
	.Q8      (k7ddrphy_bitslip191[0])
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_53 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_53 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_inc_re)),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_o_delayed19),
	.ODATAIN  (k7ddrphy_dq_o_nodelay19)
);

//------------------------------------------------------------------------------
// Instance IDELAYE2_19 of IDELAYE2 Module.
//------------------------------------------------------------------------------
IDELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("IDATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.IDELAY_TYPE           ("VARIABLE"),
	.IDELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) IDELAYE2_19 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_inc_re)),
	.IDATAIN  (k7ddrphy_dq_i_nodelay19),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_i_delayed19)
);

//------------------------------------------------------------------------------
// Instance IOBUF_19 of IOBUF Module.
//------------------------------------------------------------------------------
IOBUF IOBUF_19(
	// Inputs.
	.I  (k7ddrphy_dq_o_delayed19),
	.T  (k7ddrphy_dq_t19),

	// Outputs.
	.O  (k7ddrphy_dq_i_nodelay19),

	// InOuts.
	.IO (ddram_dq[19])
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_54 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_54 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_bitslip200[0]),
	.D2     (k7ddrphy_bitslip200[1]),
	.D3     (k7ddrphy_bitslip200[2]),
	.D4     (k7ddrphy_bitslip200[3]),
	.D5     (k7ddrphy_bitslip200[4]),
	.D6     (k7ddrphy_bitslip200[5]),
	.D7     (k7ddrphy_bitslip200[6]),
	.D8     (k7ddrphy_bitslip200[7]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),
	.T1     ((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
	.TCE    (1'd1),

	// Outputs.
	.OQ     (k7ddrphy_dq_o_nodelay20),
	.TQ     (k7ddrphy_dq_t20)
);

//------------------------------------------------------------------------------
// Instance ISERDESE2_20 of ISERDESE2 Module.
//------------------------------------------------------------------------------
ISERDESE2 #(
	// Parameters.
	.DATA_RATE      ("DDR"),
	.DATA_WIDTH     (4'd8),
	.INTERFACE_TYPE ("NETWORKING"),
	.IOBDELAY       ("IFD"),
	.NUM_CE         (1'd1),
	.SERDES_MODE    ("MASTER")
) ISERDESE2_20 (
	// Inputs.
	.BITSLIP (1'd0),
	.CE1     (1'd1),
	.CLK     (sys4x_clk),
	.CLKB    ((~sys4x_clk)),
	.CLKDIV  (sys_clk),
	.DDLY    (k7ddrphy_dq_i_delayed20),
	.RST     ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.Q1      (k7ddrphy_bitslip201[7]),
	.Q2      (k7ddrphy_bitslip201[6]),
	.Q3      (k7ddrphy_bitslip201[5]),
	.Q4      (k7ddrphy_bitslip201[4]),
	.Q5      (k7ddrphy_bitslip201[3]),
	.Q6      (k7ddrphy_bitslip201[2]),
	.Q7      (k7ddrphy_bitslip201[1]),
	.Q8      (k7ddrphy_bitslip201[0])
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_54 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_54 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_inc_re)),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_o_delayed20),
	.ODATAIN  (k7ddrphy_dq_o_nodelay20)
);

//------------------------------------------------------------------------------
// Instance IDELAYE2_20 of IDELAYE2 Module.
//------------------------------------------------------------------------------
IDELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("IDATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.IDELAY_TYPE           ("VARIABLE"),
	.IDELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) IDELAYE2_20 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_inc_re)),
	.IDATAIN  (k7ddrphy_dq_i_nodelay20),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_i_delayed20)
);

//------------------------------------------------------------------------------
// Instance IOBUF_20 of IOBUF Module.
//------------------------------------------------------------------------------
IOBUF IOBUF_20(
	// Inputs.
	.I  (k7ddrphy_dq_o_delayed20),
	.T  (k7ddrphy_dq_t20),

	// Outputs.
	.O  (k7ddrphy_dq_i_nodelay20),

	// InOuts.
	.IO (ddram_dq[20])
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_55 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_55 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_bitslip210[0]),
	.D2     (k7ddrphy_bitslip210[1]),
	.D3     (k7ddrphy_bitslip210[2]),
	.D4     (k7ddrphy_bitslip210[3]),
	.D5     (k7ddrphy_bitslip210[4]),
	.D6     (k7ddrphy_bitslip210[5]),
	.D7     (k7ddrphy_bitslip210[6]),
	.D8     (k7ddrphy_bitslip210[7]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),
	.T1     ((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
	.TCE    (1'd1),

	// Outputs.
	.OQ     (k7ddrphy_dq_o_nodelay21),
	.TQ     (k7ddrphy_dq_t21)
);

//------------------------------------------------------------------------------
// Instance ISERDESE2_21 of ISERDESE2 Module.
//------------------------------------------------------------------------------
ISERDESE2 #(
	// Parameters.
	.DATA_RATE      ("DDR"),
	.DATA_WIDTH     (4'd8),
	.INTERFACE_TYPE ("NETWORKING"),
	.IOBDELAY       ("IFD"),
	.NUM_CE         (1'd1),
	.SERDES_MODE    ("MASTER")
) ISERDESE2_21 (
	// Inputs.
	.BITSLIP (1'd0),
	.CE1     (1'd1),
	.CLK     (sys4x_clk),
	.CLKB    ((~sys4x_clk)),
	.CLKDIV  (sys_clk),
	.DDLY    (k7ddrphy_dq_i_delayed21),
	.RST     ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.Q1      (k7ddrphy_bitslip211[7]),
	.Q2      (k7ddrphy_bitslip211[6]),
	.Q3      (k7ddrphy_bitslip211[5]),
	.Q4      (k7ddrphy_bitslip211[4]),
	.Q5      (k7ddrphy_bitslip211[3]),
	.Q6      (k7ddrphy_bitslip211[2]),
	.Q7      (k7ddrphy_bitslip211[1]),
	.Q8      (k7ddrphy_bitslip211[0])
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_55 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_55 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_inc_re)),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_o_delayed21),
	.ODATAIN  (k7ddrphy_dq_o_nodelay21)
);

//------------------------------------------------------------------------------
// Instance IDELAYE2_21 of IDELAYE2 Module.
//------------------------------------------------------------------------------
IDELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("IDATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.IDELAY_TYPE           ("VARIABLE"),
	.IDELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) IDELAYE2_21 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_inc_re)),
	.IDATAIN  (k7ddrphy_dq_i_nodelay21),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_i_delayed21)
);

//------------------------------------------------------------------------------
// Instance IOBUF_21 of IOBUF Module.
//------------------------------------------------------------------------------
IOBUF IOBUF_21(
	// Inputs.
	.I  (k7ddrphy_dq_o_delayed21),
	.T  (k7ddrphy_dq_t21),

	// Outputs.
	.O  (k7ddrphy_dq_i_nodelay21),

	// InOuts.
	.IO (ddram_dq[21])
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_56 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_56 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_bitslip220[0]),
	.D2     (k7ddrphy_bitslip220[1]),
	.D3     (k7ddrphy_bitslip220[2]),
	.D4     (k7ddrphy_bitslip220[3]),
	.D5     (k7ddrphy_bitslip220[4]),
	.D6     (k7ddrphy_bitslip220[5]),
	.D7     (k7ddrphy_bitslip220[6]),
	.D8     (k7ddrphy_bitslip220[7]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),
	.T1     ((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
	.TCE    (1'd1),

	// Outputs.
	.OQ     (k7ddrphy_dq_o_nodelay22),
	.TQ     (k7ddrphy_dq_t22)
);

//------------------------------------------------------------------------------
// Instance ISERDESE2_22 of ISERDESE2 Module.
//------------------------------------------------------------------------------
ISERDESE2 #(
	// Parameters.
	.DATA_RATE      ("DDR"),
	.DATA_WIDTH     (4'd8),
	.INTERFACE_TYPE ("NETWORKING"),
	.IOBDELAY       ("IFD"),
	.NUM_CE         (1'd1),
	.SERDES_MODE    ("MASTER")
) ISERDESE2_22 (
	// Inputs.
	.BITSLIP (1'd0),
	.CE1     (1'd1),
	.CLK     (sys4x_clk),
	.CLKB    ((~sys4x_clk)),
	.CLKDIV  (sys_clk),
	.DDLY    (k7ddrphy_dq_i_delayed22),
	.RST     ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.Q1      (k7ddrphy_bitslip221[7]),
	.Q2      (k7ddrphy_bitslip221[6]),
	.Q3      (k7ddrphy_bitslip221[5]),
	.Q4      (k7ddrphy_bitslip221[4]),
	.Q5      (k7ddrphy_bitslip221[3]),
	.Q6      (k7ddrphy_bitslip221[2]),
	.Q7      (k7ddrphy_bitslip221[1]),
	.Q8      (k7ddrphy_bitslip221[0])
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_56 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_56 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_inc_re)),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_o_delayed22),
	.ODATAIN  (k7ddrphy_dq_o_nodelay22)
);

//------------------------------------------------------------------------------
// Instance IDELAYE2_22 of IDELAYE2 Module.
//------------------------------------------------------------------------------
IDELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("IDATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.IDELAY_TYPE           ("VARIABLE"),
	.IDELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) IDELAYE2_22 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_inc_re)),
	.IDATAIN  (k7ddrphy_dq_i_nodelay22),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_i_delayed22)
);

//------------------------------------------------------------------------------
// Instance IOBUF_22 of IOBUF Module.
//------------------------------------------------------------------------------
IOBUF IOBUF_22(
	// Inputs.
	.I  (k7ddrphy_dq_o_delayed22),
	.T  (k7ddrphy_dq_t22),

	// Outputs.
	.O  (k7ddrphy_dq_i_nodelay22),

	// InOuts.
	.IO (ddram_dq[22])
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_57 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_57 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_bitslip230[0]),
	.D2     (k7ddrphy_bitslip230[1]),
	.D3     (k7ddrphy_bitslip230[2]),
	.D4     (k7ddrphy_bitslip230[3]),
	.D5     (k7ddrphy_bitslip230[4]),
	.D6     (k7ddrphy_bitslip230[5]),
	.D7     (k7ddrphy_bitslip230[6]),
	.D8     (k7ddrphy_bitslip230[7]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),
	.T1     ((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
	.TCE    (1'd1),

	// Outputs.
	.OQ     (k7ddrphy_dq_o_nodelay23),
	.TQ     (k7ddrphy_dq_t23)
);

//------------------------------------------------------------------------------
// Instance ISERDESE2_23 of ISERDESE2 Module.
//------------------------------------------------------------------------------
ISERDESE2 #(
	// Parameters.
	.DATA_RATE      ("DDR"),
	.DATA_WIDTH     (4'd8),
	.INTERFACE_TYPE ("NETWORKING"),
	.IOBDELAY       ("IFD"),
	.NUM_CE         (1'd1),
	.SERDES_MODE    ("MASTER")
) ISERDESE2_23 (
	// Inputs.
	.BITSLIP (1'd0),
	.CE1     (1'd1),
	.CLK     (sys4x_clk),
	.CLKB    ((~sys4x_clk)),
	.CLKDIV  (sys_clk),
	.DDLY    (k7ddrphy_dq_i_delayed23),
	.RST     ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.Q1      (k7ddrphy_bitslip231[7]),
	.Q2      (k7ddrphy_bitslip231[6]),
	.Q3      (k7ddrphy_bitslip231[5]),
	.Q4      (k7ddrphy_bitslip231[4]),
	.Q5      (k7ddrphy_bitslip231[3]),
	.Q6      (k7ddrphy_bitslip231[2]),
	.Q7      (k7ddrphy_bitslip231[1]),
	.Q8      (k7ddrphy_bitslip231[0])
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_57 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_57 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_inc_re)),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_o_delayed23),
	.ODATAIN  (k7ddrphy_dq_o_nodelay23)
);

//------------------------------------------------------------------------------
// Instance IDELAYE2_23 of IDELAYE2 Module.
//------------------------------------------------------------------------------
IDELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("IDATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.IDELAY_TYPE           ("VARIABLE"),
	.IDELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) IDELAYE2_23 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_inc_re)),
	.IDATAIN  (k7ddrphy_dq_i_nodelay23),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_i_delayed23)
);

//------------------------------------------------------------------------------
// Instance IOBUF_23 of IOBUF Module.
//------------------------------------------------------------------------------
IOBUF IOBUF_23(
	// Inputs.
	.I  (k7ddrphy_dq_o_delayed23),
	.T  (k7ddrphy_dq_t23),

	// Outputs.
	.O  (k7ddrphy_dq_i_nodelay23),

	// InOuts.
	.IO (ddram_dq[23])
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_58 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_58 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_bitslip240[0]),
	.D2     (k7ddrphy_bitslip240[1]),
	.D3     (k7ddrphy_bitslip240[2]),
	.D4     (k7ddrphy_bitslip240[3]),
	.D5     (k7ddrphy_bitslip240[4]),
	.D6     (k7ddrphy_bitslip240[5]),
	.D7     (k7ddrphy_bitslip240[6]),
	.D8     (k7ddrphy_bitslip240[7]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),
	.T1     ((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
	.TCE    (1'd1),

	// Outputs.
	.OQ     (k7ddrphy_dq_o_nodelay24),
	.TQ     (k7ddrphy_dq_t24)
);

//------------------------------------------------------------------------------
// Instance ISERDESE2_24 of ISERDESE2 Module.
//------------------------------------------------------------------------------
ISERDESE2 #(
	// Parameters.
	.DATA_RATE      ("DDR"),
	.DATA_WIDTH     (4'd8),
	.INTERFACE_TYPE ("NETWORKING"),
	.IOBDELAY       ("IFD"),
	.NUM_CE         (1'd1),
	.SERDES_MODE    ("MASTER")
) ISERDESE2_24 (
	// Inputs.
	.BITSLIP (1'd0),
	.CE1     (1'd1),
	.CLK     (sys4x_clk),
	.CLKB    ((~sys4x_clk)),
	.CLKDIV  (sys_clk),
	.DDLY    (k7ddrphy_dq_i_delayed24),
	.RST     ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.Q1      (k7ddrphy_bitslip241[7]),
	.Q2      (k7ddrphy_bitslip241[6]),
	.Q3      (k7ddrphy_bitslip241[5]),
	.Q4      (k7ddrphy_bitslip241[4]),
	.Q5      (k7ddrphy_bitslip241[3]),
	.Q6      (k7ddrphy_bitslip241[2]),
	.Q7      (k7ddrphy_bitslip241[1]),
	.Q8      (k7ddrphy_bitslip241[0])
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_58 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_58 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_inc_re)),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_o_delayed24),
	.ODATAIN  (k7ddrphy_dq_o_nodelay24)
);

//------------------------------------------------------------------------------
// Instance IDELAYE2_24 of IDELAYE2 Module.
//------------------------------------------------------------------------------
IDELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("IDATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.IDELAY_TYPE           ("VARIABLE"),
	.IDELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) IDELAYE2_24 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_inc_re)),
	.IDATAIN  (k7ddrphy_dq_i_nodelay24),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_i_delayed24)
);

//------------------------------------------------------------------------------
// Instance IOBUF_24 of IOBUF Module.
//------------------------------------------------------------------------------
IOBUF IOBUF_24(
	// Inputs.
	.I  (k7ddrphy_dq_o_delayed24),
	.T  (k7ddrphy_dq_t24),

	// Outputs.
	.O  (k7ddrphy_dq_i_nodelay24),

	// InOuts.
	.IO (ddram_dq[24])
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_59 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_59 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_bitslip250[0]),
	.D2     (k7ddrphy_bitslip250[1]),
	.D3     (k7ddrphy_bitslip250[2]),
	.D4     (k7ddrphy_bitslip250[3]),
	.D5     (k7ddrphy_bitslip250[4]),
	.D6     (k7ddrphy_bitslip250[5]),
	.D7     (k7ddrphy_bitslip250[6]),
	.D8     (k7ddrphy_bitslip250[7]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),
	.T1     ((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
	.TCE    (1'd1),

	// Outputs.
	.OQ     (k7ddrphy_dq_o_nodelay25),
	.TQ     (k7ddrphy_dq_t25)
);

//------------------------------------------------------------------------------
// Instance ISERDESE2_25 of ISERDESE2 Module.
//------------------------------------------------------------------------------
ISERDESE2 #(
	// Parameters.
	.DATA_RATE      ("DDR"),
	.DATA_WIDTH     (4'd8),
	.INTERFACE_TYPE ("NETWORKING"),
	.IOBDELAY       ("IFD"),
	.NUM_CE         (1'd1),
	.SERDES_MODE    ("MASTER")
) ISERDESE2_25 (
	// Inputs.
	.BITSLIP (1'd0),
	.CE1     (1'd1),
	.CLK     (sys4x_clk),
	.CLKB    ((~sys4x_clk)),
	.CLKDIV  (sys_clk),
	.DDLY    (k7ddrphy_dq_i_delayed25),
	.RST     ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.Q1      (k7ddrphy_bitslip251[7]),
	.Q2      (k7ddrphy_bitslip251[6]),
	.Q3      (k7ddrphy_bitslip251[5]),
	.Q4      (k7ddrphy_bitslip251[4]),
	.Q5      (k7ddrphy_bitslip251[3]),
	.Q6      (k7ddrphy_bitslip251[2]),
	.Q7      (k7ddrphy_bitslip251[1]),
	.Q8      (k7ddrphy_bitslip251[0])
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_59 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_59 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_inc_re)),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_o_delayed25),
	.ODATAIN  (k7ddrphy_dq_o_nodelay25)
);

//------------------------------------------------------------------------------
// Instance IDELAYE2_25 of IDELAYE2 Module.
//------------------------------------------------------------------------------
IDELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("IDATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.IDELAY_TYPE           ("VARIABLE"),
	.IDELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) IDELAYE2_25 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_inc_re)),
	.IDATAIN  (k7ddrphy_dq_i_nodelay25),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_i_delayed25)
);

//------------------------------------------------------------------------------
// Instance IOBUF_25 of IOBUF Module.
//------------------------------------------------------------------------------
IOBUF IOBUF_25(
	// Inputs.
	.I  (k7ddrphy_dq_o_delayed25),
	.T  (k7ddrphy_dq_t25),

	// Outputs.
	.O  (k7ddrphy_dq_i_nodelay25),

	// InOuts.
	.IO (ddram_dq[25])
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_60 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_60 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_bitslip260[0]),
	.D2     (k7ddrphy_bitslip260[1]),
	.D3     (k7ddrphy_bitslip260[2]),
	.D4     (k7ddrphy_bitslip260[3]),
	.D5     (k7ddrphy_bitslip260[4]),
	.D6     (k7ddrphy_bitslip260[5]),
	.D7     (k7ddrphy_bitslip260[6]),
	.D8     (k7ddrphy_bitslip260[7]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),
	.T1     ((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
	.TCE    (1'd1),

	// Outputs.
	.OQ     (k7ddrphy_dq_o_nodelay26),
	.TQ     (k7ddrphy_dq_t26)
);

//------------------------------------------------------------------------------
// Instance ISERDESE2_26 of ISERDESE2 Module.
//------------------------------------------------------------------------------
ISERDESE2 #(
	// Parameters.
	.DATA_RATE      ("DDR"),
	.DATA_WIDTH     (4'd8),
	.INTERFACE_TYPE ("NETWORKING"),
	.IOBDELAY       ("IFD"),
	.NUM_CE         (1'd1),
	.SERDES_MODE    ("MASTER")
) ISERDESE2_26 (
	// Inputs.
	.BITSLIP (1'd0),
	.CE1     (1'd1),
	.CLK     (sys4x_clk),
	.CLKB    ((~sys4x_clk)),
	.CLKDIV  (sys_clk),
	.DDLY    (k7ddrphy_dq_i_delayed26),
	.RST     ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.Q1      (k7ddrphy_bitslip261[7]),
	.Q2      (k7ddrphy_bitslip261[6]),
	.Q3      (k7ddrphy_bitslip261[5]),
	.Q4      (k7ddrphy_bitslip261[4]),
	.Q5      (k7ddrphy_bitslip261[3]),
	.Q6      (k7ddrphy_bitslip261[2]),
	.Q7      (k7ddrphy_bitslip261[1]),
	.Q8      (k7ddrphy_bitslip261[0])
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_60 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_60 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_inc_re)),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_o_delayed26),
	.ODATAIN  (k7ddrphy_dq_o_nodelay26)
);

//------------------------------------------------------------------------------
// Instance IDELAYE2_26 of IDELAYE2 Module.
//------------------------------------------------------------------------------
IDELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("IDATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.IDELAY_TYPE           ("VARIABLE"),
	.IDELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) IDELAYE2_26 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_inc_re)),
	.IDATAIN  (k7ddrphy_dq_i_nodelay26),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_i_delayed26)
);

//------------------------------------------------------------------------------
// Instance IOBUF_26 of IOBUF Module.
//------------------------------------------------------------------------------
IOBUF IOBUF_26(
	// Inputs.
	.I  (k7ddrphy_dq_o_delayed26),
	.T  (k7ddrphy_dq_t26),

	// Outputs.
	.O  (k7ddrphy_dq_i_nodelay26),

	// InOuts.
	.IO (ddram_dq[26])
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_61 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_61 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_bitslip270[0]),
	.D2     (k7ddrphy_bitslip270[1]),
	.D3     (k7ddrphy_bitslip270[2]),
	.D4     (k7ddrphy_bitslip270[3]),
	.D5     (k7ddrphy_bitslip270[4]),
	.D6     (k7ddrphy_bitslip270[5]),
	.D7     (k7ddrphy_bitslip270[6]),
	.D8     (k7ddrphy_bitslip270[7]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),
	.T1     ((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
	.TCE    (1'd1),

	// Outputs.
	.OQ     (k7ddrphy_dq_o_nodelay27),
	.TQ     (k7ddrphy_dq_t27)
);

//------------------------------------------------------------------------------
// Instance ISERDESE2_27 of ISERDESE2 Module.
//------------------------------------------------------------------------------
ISERDESE2 #(
	// Parameters.
	.DATA_RATE      ("DDR"),
	.DATA_WIDTH     (4'd8),
	.INTERFACE_TYPE ("NETWORKING"),
	.IOBDELAY       ("IFD"),
	.NUM_CE         (1'd1),
	.SERDES_MODE    ("MASTER")
) ISERDESE2_27 (
	// Inputs.
	.BITSLIP (1'd0),
	.CE1     (1'd1),
	.CLK     (sys4x_clk),
	.CLKB    ((~sys4x_clk)),
	.CLKDIV  (sys_clk),
	.DDLY    (k7ddrphy_dq_i_delayed27),
	.RST     ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.Q1      (k7ddrphy_bitslip271[7]),
	.Q2      (k7ddrphy_bitslip271[6]),
	.Q3      (k7ddrphy_bitslip271[5]),
	.Q4      (k7ddrphy_bitslip271[4]),
	.Q5      (k7ddrphy_bitslip271[3]),
	.Q6      (k7ddrphy_bitslip271[2]),
	.Q7      (k7ddrphy_bitslip271[1]),
	.Q8      (k7ddrphy_bitslip271[0])
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_61 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_61 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_inc_re)),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_o_delayed27),
	.ODATAIN  (k7ddrphy_dq_o_nodelay27)
);

//------------------------------------------------------------------------------
// Instance IDELAYE2_27 of IDELAYE2 Module.
//------------------------------------------------------------------------------
IDELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("IDATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.IDELAY_TYPE           ("VARIABLE"),
	.IDELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) IDELAYE2_27 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_inc_re)),
	.IDATAIN  (k7ddrphy_dq_i_nodelay27),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_i_delayed27)
);

//------------------------------------------------------------------------------
// Instance IOBUF_27 of IOBUF Module.
//------------------------------------------------------------------------------
IOBUF IOBUF_27(
	// Inputs.
	.I  (k7ddrphy_dq_o_delayed27),
	.T  (k7ddrphy_dq_t27),

	// Outputs.
	.O  (k7ddrphy_dq_i_nodelay27),

	// InOuts.
	.IO (ddram_dq[27])
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_62 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_62 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_bitslip280[0]),
	.D2     (k7ddrphy_bitslip280[1]),
	.D3     (k7ddrphy_bitslip280[2]),
	.D4     (k7ddrphy_bitslip280[3]),
	.D5     (k7ddrphy_bitslip280[4]),
	.D6     (k7ddrphy_bitslip280[5]),
	.D7     (k7ddrphy_bitslip280[6]),
	.D8     (k7ddrphy_bitslip280[7]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),
	.T1     ((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
	.TCE    (1'd1),

	// Outputs.
	.OQ     (k7ddrphy_dq_o_nodelay28),
	.TQ     (k7ddrphy_dq_t28)
);

//------------------------------------------------------------------------------
// Instance ISERDESE2_28 of ISERDESE2 Module.
//------------------------------------------------------------------------------
ISERDESE2 #(
	// Parameters.
	.DATA_RATE      ("DDR"),
	.DATA_WIDTH     (4'd8),
	.INTERFACE_TYPE ("NETWORKING"),
	.IOBDELAY       ("IFD"),
	.NUM_CE         (1'd1),
	.SERDES_MODE    ("MASTER")
) ISERDESE2_28 (
	// Inputs.
	.BITSLIP (1'd0),
	.CE1     (1'd1),
	.CLK     (sys4x_clk),
	.CLKB    ((~sys4x_clk)),
	.CLKDIV  (sys_clk),
	.DDLY    (k7ddrphy_dq_i_delayed28),
	.RST     ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.Q1      (k7ddrphy_bitslip281[7]),
	.Q2      (k7ddrphy_bitslip281[6]),
	.Q3      (k7ddrphy_bitslip281[5]),
	.Q4      (k7ddrphy_bitslip281[4]),
	.Q5      (k7ddrphy_bitslip281[3]),
	.Q6      (k7ddrphy_bitslip281[2]),
	.Q7      (k7ddrphy_bitslip281[1]),
	.Q8      (k7ddrphy_bitslip281[0])
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_62 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_62 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_inc_re)),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_o_delayed28),
	.ODATAIN  (k7ddrphy_dq_o_nodelay28)
);

//------------------------------------------------------------------------------
// Instance IDELAYE2_28 of IDELAYE2 Module.
//------------------------------------------------------------------------------
IDELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("IDATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.IDELAY_TYPE           ("VARIABLE"),
	.IDELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) IDELAYE2_28 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_inc_re)),
	.IDATAIN  (k7ddrphy_dq_i_nodelay28),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_i_delayed28)
);

//------------------------------------------------------------------------------
// Instance IOBUF_28 of IOBUF Module.
//------------------------------------------------------------------------------
IOBUF IOBUF_28(
	// Inputs.
	.I  (k7ddrphy_dq_o_delayed28),
	.T  (k7ddrphy_dq_t28),

	// Outputs.
	.O  (k7ddrphy_dq_i_nodelay28),

	// InOuts.
	.IO (ddram_dq[28])
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_63 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_63 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_bitslip290[0]),
	.D2     (k7ddrphy_bitslip290[1]),
	.D3     (k7ddrphy_bitslip290[2]),
	.D4     (k7ddrphy_bitslip290[3]),
	.D5     (k7ddrphy_bitslip290[4]),
	.D6     (k7ddrphy_bitslip290[5]),
	.D7     (k7ddrphy_bitslip290[6]),
	.D8     (k7ddrphy_bitslip290[7]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),
	.T1     ((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
	.TCE    (1'd1),

	// Outputs.
	.OQ     (k7ddrphy_dq_o_nodelay29),
	.TQ     (k7ddrphy_dq_t29)
);

//------------------------------------------------------------------------------
// Instance ISERDESE2_29 of ISERDESE2 Module.
//------------------------------------------------------------------------------
ISERDESE2 #(
	// Parameters.
	.DATA_RATE      ("DDR"),
	.DATA_WIDTH     (4'd8),
	.INTERFACE_TYPE ("NETWORKING"),
	.IOBDELAY       ("IFD"),
	.NUM_CE         (1'd1),
	.SERDES_MODE    ("MASTER")
) ISERDESE2_29 (
	// Inputs.
	.BITSLIP (1'd0),
	.CE1     (1'd1),
	.CLK     (sys4x_clk),
	.CLKB    ((~sys4x_clk)),
	.CLKDIV  (sys_clk),
	.DDLY    (k7ddrphy_dq_i_delayed29),
	.RST     ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.Q1      (k7ddrphy_bitslip291[7]),
	.Q2      (k7ddrphy_bitslip291[6]),
	.Q3      (k7ddrphy_bitslip291[5]),
	.Q4      (k7ddrphy_bitslip291[4]),
	.Q5      (k7ddrphy_bitslip291[3]),
	.Q6      (k7ddrphy_bitslip291[2]),
	.Q7      (k7ddrphy_bitslip291[1]),
	.Q8      (k7ddrphy_bitslip291[0])
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_63 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_63 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_inc_re)),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_o_delayed29),
	.ODATAIN  (k7ddrphy_dq_o_nodelay29)
);

//------------------------------------------------------------------------------
// Instance IDELAYE2_29 of IDELAYE2 Module.
//------------------------------------------------------------------------------
IDELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("IDATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.IDELAY_TYPE           ("VARIABLE"),
	.IDELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) IDELAYE2_29 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_inc_re)),
	.IDATAIN  (k7ddrphy_dq_i_nodelay29),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_i_delayed29)
);

//------------------------------------------------------------------------------
// Instance IOBUF_29 of IOBUF Module.
//------------------------------------------------------------------------------
IOBUF IOBUF_29(
	// Inputs.
	.I  (k7ddrphy_dq_o_delayed29),
	.T  (k7ddrphy_dq_t29),

	// Outputs.
	.O  (k7ddrphy_dq_i_nodelay29),

	// InOuts.
	.IO (ddram_dq[29])
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_64 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_64 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_bitslip300[0]),
	.D2     (k7ddrphy_bitslip300[1]),
	.D3     (k7ddrphy_bitslip300[2]),
	.D4     (k7ddrphy_bitslip300[3]),
	.D5     (k7ddrphy_bitslip300[4]),
	.D6     (k7ddrphy_bitslip300[5]),
	.D7     (k7ddrphy_bitslip300[6]),
	.D8     (k7ddrphy_bitslip300[7]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),
	.T1     ((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
	.TCE    (1'd1),

	// Outputs.
	.OQ     (k7ddrphy_dq_o_nodelay30),
	.TQ     (k7ddrphy_dq_t30)
);

//------------------------------------------------------------------------------
// Instance ISERDESE2_30 of ISERDESE2 Module.
//------------------------------------------------------------------------------
ISERDESE2 #(
	// Parameters.
	.DATA_RATE      ("DDR"),
	.DATA_WIDTH     (4'd8),
	.INTERFACE_TYPE ("NETWORKING"),
	.IOBDELAY       ("IFD"),
	.NUM_CE         (1'd1),
	.SERDES_MODE    ("MASTER")
) ISERDESE2_30 (
	// Inputs.
	.BITSLIP (1'd0),
	.CE1     (1'd1),
	.CLK     (sys4x_clk),
	.CLKB    ((~sys4x_clk)),
	.CLKDIV  (sys_clk),
	.DDLY    (k7ddrphy_dq_i_delayed30),
	.RST     ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.Q1      (k7ddrphy_bitslip301[7]),
	.Q2      (k7ddrphy_bitslip301[6]),
	.Q3      (k7ddrphy_bitslip301[5]),
	.Q4      (k7ddrphy_bitslip301[4]),
	.Q5      (k7ddrphy_bitslip301[3]),
	.Q6      (k7ddrphy_bitslip301[2]),
	.Q7      (k7ddrphy_bitslip301[1]),
	.Q8      (k7ddrphy_bitslip301[0])
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_64 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_64 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_inc_re)),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_o_delayed30),
	.ODATAIN  (k7ddrphy_dq_o_nodelay30)
);

//------------------------------------------------------------------------------
// Instance IDELAYE2_30 of IDELAYE2 Module.
//------------------------------------------------------------------------------
IDELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("IDATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.IDELAY_TYPE           ("VARIABLE"),
	.IDELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) IDELAYE2_30 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_inc_re)),
	.IDATAIN  (k7ddrphy_dq_i_nodelay30),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_i_delayed30)
);

//------------------------------------------------------------------------------
// Instance IOBUF_30 of IOBUF Module.
//------------------------------------------------------------------------------
IOBUF IOBUF_30(
	// Inputs.
	.I  (k7ddrphy_dq_o_delayed30),
	.T  (k7ddrphy_dq_t30),

	// Outputs.
	.O  (k7ddrphy_dq_i_nodelay30),

	// InOuts.
	.IO (ddram_dq[30])
);

//------------------------------------------------------------------------------
// Instance OSERDESE2_65 of OSERDESE2 Module.
//------------------------------------------------------------------------------
OSERDESE2 #(
	// Parameters.
	.DATA_RATE_OQ   ("DDR"),
	.DATA_RATE_TQ   ("BUF"),
	.DATA_WIDTH     (4'd8),
	.SERDES_MODE    ("MASTER"),
	.TRISTATE_WIDTH (1'd1)
) OSERDESE2_65 (
	// Inputs.
	.CLK    (sys4x_clk),
	.CLKDIV (sys_clk),
	.D1     (k7ddrphy_bitslip310[0]),
	.D2     (k7ddrphy_bitslip310[1]),
	.D3     (k7ddrphy_bitslip310[2]),
	.D4     (k7ddrphy_bitslip310[3]),
	.D5     (k7ddrphy_bitslip310[4]),
	.D6     (k7ddrphy_bitslip310[5]),
	.D7     (k7ddrphy_bitslip310[6]),
	.D8     (k7ddrphy_bitslip310[7]),
	.OCE    (1'd1),
	.RST    ((sys_rst | k7ddrphy_rst_storage)),
	.T1     ((~k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
	.TCE    (1'd1),

	// Outputs.
	.OQ     (k7ddrphy_dq_o_nodelay31),
	.TQ     (k7ddrphy_dq_t31)
);

//------------------------------------------------------------------------------
// Instance ISERDESE2_31 of ISERDESE2 Module.
//------------------------------------------------------------------------------
ISERDESE2 #(
	// Parameters.
	.DATA_RATE      ("DDR"),
	.DATA_WIDTH     (4'd8),
	.INTERFACE_TYPE ("NETWORKING"),
	.IOBDELAY       ("IFD"),
	.NUM_CE         (1'd1),
	.SERDES_MODE    ("MASTER")
) ISERDESE2_31 (
	// Inputs.
	.BITSLIP (1'd0),
	.CE1     (1'd1),
	.CLK     (sys4x_clk),
	.CLKB    ((~sys4x_clk)),
	.CLKDIV  (sys_clk),
	.DDLY    (k7ddrphy_dq_i_delayed31),
	.RST     ((sys_rst | k7ddrphy_rst_storage)),

	// Outputs.
	.Q1      (k7ddrphy_bitslip311[7]),
	.Q2      (k7ddrphy_bitslip311[6]),
	.Q3      (k7ddrphy_bitslip311[5]),
	.Q4      (k7ddrphy_bitslip311[4]),
	.Q5      (k7ddrphy_bitslip311[3]),
	.Q6      (k7ddrphy_bitslip311[2]),
	.Q7      (k7ddrphy_bitslip311[1]),
	.Q8      (k7ddrphy_bitslip311[0])
);

//------------------------------------------------------------------------------
// Instance ODELAYE2_65 of ODELAYE2 Module.
//------------------------------------------------------------------------------
ODELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("ODATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.ODELAY_TYPE           ("VARIABLE"),
	.ODELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) ODELAYE2_65 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_inc_re)),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_o_delayed31),
	.ODATAIN  (k7ddrphy_dq_o_nodelay31)
);

//------------------------------------------------------------------------------
// Instance IDELAYE2_31 of IDELAYE2 Module.
//------------------------------------------------------------------------------
IDELAYE2 #(
	// Parameters.
	.CINVCTRL_SEL          ("FALSE"),
	.DELAY_SRC             ("IDATAIN"),
	.HIGH_PERFORMANCE_MODE ("TRUE"),
	.IDELAY_TYPE           ("VARIABLE"),
	.IDELAY_VALUE          (1'd0),
	.PIPE_SEL              ("FALSE"),
	.REFCLK_FREQUENCY      (200.0),
	.SIGNAL_PATTERN        ("DATA")
) IDELAYE2_31 (
	// Inputs.
	.C        (sys_clk),
	.CE       ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_inc_re)),
	.IDATAIN  (k7ddrphy_dq_i_nodelay31),
	.INC      (1'd1),
	.LD       (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_rst_re) | k7ddrphy_rst_storage)),
	.LDPIPEEN (1'd0),

	// Outputs.
	.DATAOUT  (k7ddrphy_dq_i_delayed31)
);

//------------------------------------------------------------------------------
// Instance IOBUF_31 of IOBUF Module.
//------------------------------------------------------------------------------
IOBUF IOBUF_31(
	// Inputs.
	.I  (k7ddrphy_dq_o_delayed31),
	.T  (k7ddrphy_dq_t31),

	// Outputs.
	.O  (k7ddrphy_dq_i_nodelay31),

	// InOuts.
	.IO (ddram_dq[31])
);

//------------------------------------------------------------------------------
// Memory storage_2: 16-words x 25-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 25 
// Port 1 | Read: Async | Write: ---- | 
reg [24:0] storage_2[0:15];
reg [24:0] storage_2_dat0;
always @(posedge sys_clk) begin
	if (litedramcore_sdram_bankmachine0_wrport_we)
		storage_2[litedramcore_sdram_bankmachine0_wrport_adr] <= litedramcore_sdram_bankmachine0_wrport_dat_w;
	storage_2_dat0 <= storage_2[litedramcore_sdram_bankmachine0_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign litedramcore_sdram_bankmachine0_wrport_dat_r = storage_2_dat0;
assign litedramcore_sdram_bankmachine0_rdport_dat_r = storage_2[litedramcore_sdram_bankmachine0_rdport_adr];


//------------------------------------------------------------------------------
// Memory storage_3: 16-words x 25-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 25 
// Port 1 | Read: Async | Write: ---- | 
reg [24:0] storage_3[0:15];
reg [24:0] storage_3_dat0;
always @(posedge sys_clk) begin
	if (litedramcore_sdram_bankmachine1_wrport_we)
		storage_3[litedramcore_sdram_bankmachine1_wrport_adr] <= litedramcore_sdram_bankmachine1_wrport_dat_w;
	storage_3_dat0 <= storage_3[litedramcore_sdram_bankmachine1_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign litedramcore_sdram_bankmachine1_wrport_dat_r = storage_3_dat0;
assign litedramcore_sdram_bankmachine1_rdport_dat_r = storage_3[litedramcore_sdram_bankmachine1_rdport_adr];


//------------------------------------------------------------------------------
// Memory storage_4: 16-words x 25-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 25 
// Port 1 | Read: Async | Write: ---- | 
reg [24:0] storage_4[0:15];
reg [24:0] storage_4_dat0;
always @(posedge sys_clk) begin
	if (litedramcore_sdram_bankmachine2_wrport_we)
		storage_4[litedramcore_sdram_bankmachine2_wrport_adr] <= litedramcore_sdram_bankmachine2_wrport_dat_w;
	storage_4_dat0 <= storage_4[litedramcore_sdram_bankmachine2_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign litedramcore_sdram_bankmachine2_wrport_dat_r = storage_4_dat0;
assign litedramcore_sdram_bankmachine2_rdport_dat_r = storage_4[litedramcore_sdram_bankmachine2_rdport_adr];


//------------------------------------------------------------------------------
// Memory storage_5: 16-words x 25-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 25 
// Port 1 | Read: Async | Write: ---- | 
reg [24:0] storage_5[0:15];
reg [24:0] storage_5_dat0;
always @(posedge sys_clk) begin
	if (litedramcore_sdram_bankmachine3_wrport_we)
		storage_5[litedramcore_sdram_bankmachine3_wrport_adr] <= litedramcore_sdram_bankmachine3_wrport_dat_w;
	storage_5_dat0 <= storage_5[litedramcore_sdram_bankmachine3_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign litedramcore_sdram_bankmachine3_wrport_dat_r = storage_5_dat0;
assign litedramcore_sdram_bankmachine3_rdport_dat_r = storage_5[litedramcore_sdram_bankmachine3_rdport_adr];


//------------------------------------------------------------------------------
// Memory storage_6: 16-words x 25-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 25 
// Port 1 | Read: Async | Write: ---- | 
reg [24:0] storage_6[0:15];
reg [24:0] storage_6_dat0;
always @(posedge sys_clk) begin
	if (litedramcore_sdram_bankmachine4_wrport_we)
		storage_6[litedramcore_sdram_bankmachine4_wrport_adr] <= litedramcore_sdram_bankmachine4_wrport_dat_w;
	storage_6_dat0 <= storage_6[litedramcore_sdram_bankmachine4_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign litedramcore_sdram_bankmachine4_wrport_dat_r = storage_6_dat0;
assign litedramcore_sdram_bankmachine4_rdport_dat_r = storage_6[litedramcore_sdram_bankmachine4_rdport_adr];


//------------------------------------------------------------------------------
// Memory storage_7: 16-words x 25-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 25 
// Port 1 | Read: Async | Write: ---- | 
reg [24:0] storage_7[0:15];
reg [24:0] storage_7_dat0;
always @(posedge sys_clk) begin
	if (litedramcore_sdram_bankmachine5_wrport_we)
		storage_7[litedramcore_sdram_bankmachine5_wrport_adr] <= litedramcore_sdram_bankmachine5_wrport_dat_w;
	storage_7_dat0 <= storage_7[litedramcore_sdram_bankmachine5_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign litedramcore_sdram_bankmachine5_wrport_dat_r = storage_7_dat0;
assign litedramcore_sdram_bankmachine5_rdport_dat_r = storage_7[litedramcore_sdram_bankmachine5_rdport_adr];


//------------------------------------------------------------------------------
// Memory storage_8: 16-words x 25-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 25 
// Port 1 | Read: Async | Write: ---- | 
reg [24:0] storage_8[0:15];
reg [24:0] storage_8_dat0;
always @(posedge sys_clk) begin
	if (litedramcore_sdram_bankmachine6_wrport_we)
		storage_8[litedramcore_sdram_bankmachine6_wrport_adr] <= litedramcore_sdram_bankmachine6_wrport_dat_w;
	storage_8_dat0 <= storage_8[litedramcore_sdram_bankmachine6_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign litedramcore_sdram_bankmachine6_wrport_dat_r = storage_8_dat0;
assign litedramcore_sdram_bankmachine6_rdport_dat_r = storage_8[litedramcore_sdram_bankmachine6_rdport_adr];


//------------------------------------------------------------------------------
// Memory storage_9: 16-words x 25-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 25 
// Port 1 | Read: Async | Write: ---- | 
reg [24:0] storage_9[0:15];
reg [24:0] storage_9_dat0;
always @(posedge sys_clk) begin
	if (litedramcore_sdram_bankmachine7_wrport_we)
		storage_9[litedramcore_sdram_bankmachine7_wrport_adr] <= litedramcore_sdram_bankmachine7_wrport_dat_w;
	storage_9_dat0 <= storage_9[litedramcore_sdram_bankmachine7_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign litedramcore_sdram_bankmachine7_wrport_dat_r = storage_9_dat0;
assign litedramcore_sdram_bankmachine7_rdport_dat_r = storage_9[litedramcore_sdram_bankmachine7_rdport_adr];


//------------------------------------------------------------------------------
// Memory tag_mem: 2-words x 30-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 30 
reg [29:0] tag_mem[0:1];
reg [0:0] tag_mem_adr0;
always @(posedge sys_clk) begin
	if (litedramcore_tag_port_we)
		tag_mem[litedramcore_tag_port_adr] <= litedramcore_tag_port_dat_w;
	tag_mem_adr0 <= litedramcore_tag_port_adr;
end
assign litedramcore_tag_port_dat_r = tag_mem[tag_mem_adr0];


//------------------------------------------------------------------------------
// Memory storage_10: 7-words x 258-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 258 
// Port 1 | Read: Async | Write: ---- | 
reg [257:0] storage_10[0:6];
reg [257:0] storage_10_dat0;
always @(posedge sys_clk) begin
	if (user_port_litedramnativeportconverter_rdata_fifo_wrport_we)
		storage_10[user_port_litedramnativeportconverter_rdata_fifo_wrport_adr] <= user_port_litedramnativeportconverter_rdata_fifo_wrport_dat_w;
	storage_10_dat0 <= storage_10[user_port_litedramnativeportconverter_rdata_fifo_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign user_port_litedramnativeportconverter_rdata_fifo_wrport_dat_r = storage_10_dat0;
assign user_port_litedramnativeportconverter_rdata_fifo_rdport_dat_r = storage_10[user_port_litedramnativeportconverter_rdata_fifo_rdport_adr];


//------------------------------------------------------------------------------
// Memory storage_11: 7-words x 38-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 38 
// Port 1 | Read: Async | Write: ---- | 
reg [37:0] storage_11[0:6];
reg [37:0] storage_11_dat0;
always @(posedge sys_clk) begin
	if (user_port_litedramnativeportconverter_wdata_fifo_wrport_we)
		storage_11[user_port_litedramnativeportconverter_wdata_fifo_wrport_adr] <= user_port_litedramnativeportconverter_wdata_fifo_wrport_dat_w;
	storage_11_dat0 <= storage_11[user_port_litedramnativeportconverter_wdata_fifo_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign user_port_litedramnativeportconverter_wdata_fifo_wrport_dat_r = storage_11_dat0;
assign user_port_litedramnativeportconverter_wdata_fifo_rdport_dat_r = storage_11[user_port_litedramnativeportconverter_wdata_fifo_rdport_adr];


//------------------------------------------------------------------------------
// Instance VexRiscv of VexRiscv Module.
//------------------------------------------------------------------------------
VexRiscv VexRiscv(
	// Inputs.
	.clk                    (sys_clk),
	.dBusWishbone_ACK       (litedramcore_dbus_ack),
	.dBusWishbone_DAT_MISO  (litedramcore_dbus_dat_r),
	.dBusWishbone_ERR       (litedramcore_dbus_err),
	.externalInterruptArray (litedramcore_interrupt),
	.externalResetVector    (litedramcore_vexriscv),
	.iBusWishbone_ACK       (litedramcore_ibus_ack),
	.iBusWishbone_DAT_MISO  (litedramcore_ibus_dat_r),
	.iBusWishbone_ERR       (litedramcore_ibus_err),
	.reset                  ((sys_rst | litedramcore_reset)),
	.softwareInterrupt      (1'd0),
	.timerInterrupt         (1'd0),

	// Outputs.
	.dBusWishbone_ADR       (litedramcore_dbus_adr),
	.dBusWishbone_BTE       (litedramcore_dbus_bte),
	.dBusWishbone_CTI       (litedramcore_dbus_cti),
	.dBusWishbone_CYC       (litedramcore_dbus_cyc),
	.dBusWishbone_DAT_MOSI  (litedramcore_dbus_dat_w),
	.dBusWishbone_SEL       (litedramcore_dbus_sel),
	.dBusWishbone_STB       (litedramcore_dbus_stb),
	.dBusWishbone_WE        (litedramcore_dbus_we),
	.iBusWishbone_ADR       (litedramcore_ibus_adr),
	.iBusWishbone_BTE       (litedramcore_ibus_bte),
	.iBusWishbone_CTI       (litedramcore_ibus_cti),
	.iBusWishbone_CYC       (litedramcore_ibus_cyc),
	.iBusWishbone_DAT_MOSI  (litedramcore_ibus_dat_w),
	.iBusWishbone_SEL       (litedramcore_ibus_sel),
	.iBusWishbone_STB       (litedramcore_ibus_stb),
	.iBusWishbone_WE        (litedramcore_ibus_we)
);

//------------------------------------------------------------------------------
// Instance FDCE of FDCE Module.
//------------------------------------------------------------------------------
FDCE FDCE(
	// Inputs.
	.C   (crg_clkin),
	.CE  (1'd1),
	.CLR (1'd0),
	.D   (crg_reset),

	// Outputs.
	.Q   (reset0)
);

//------------------------------------------------------------------------------
// Instance FDCE_1 of FDCE Module.
//------------------------------------------------------------------------------
FDCE FDCE_1(
	// Inputs.
	.C   (crg_clkin),
	.CE  (1'd1),
	.CLR (1'd0),
	.D   (reset0),

	// Outputs.
	.Q   (reset1)
);

//------------------------------------------------------------------------------
// Instance FDCE_2 of FDCE Module.
//------------------------------------------------------------------------------
FDCE FDCE_2(
	// Inputs.
	.C   (crg_clkin),
	.CE  (1'd1),
	.CLR (1'd0),
	.D   (reset1),

	// Outputs.
	.Q   (reset2)
);

//------------------------------------------------------------------------------
// Instance FDCE_3 of FDCE Module.
//------------------------------------------------------------------------------
FDCE FDCE_3(
	// Inputs.
	.C   (crg_clkin),
	.CE  (1'd1),
	.CLR (1'd0),
	.D   (reset2),

	// Outputs.
	.Q   (reset3)
);

//------------------------------------------------------------------------------
// Instance FDCE_4 of FDCE Module.
//------------------------------------------------------------------------------
FDCE FDCE_4(
	// Inputs.
	.C   (crg_clkin),
	.CE  (1'd1),
	.CLR (1'd0),
	.D   (reset3),

	// Outputs.
	.Q   (reset4)
);

//------------------------------------------------------------------------------
// Instance FDCE_5 of FDCE Module.
//------------------------------------------------------------------------------
FDCE FDCE_5(
	// Inputs.
	.C   (crg_clkin),
	.CE  (1'd1),
	.CLR (1'd0),
	.D   (reset4),

	// Outputs.
	.Q   (reset5)
);

//------------------------------------------------------------------------------
// Instance FDCE_6 of FDCE Module.
//------------------------------------------------------------------------------
FDCE FDCE_6(
	// Inputs.
	.C   (crg_clkin),
	.CE  (1'd1),
	.CLR (1'd0),
	.D   (reset5),

	// Outputs.
	.Q   (reset6)
);

//------------------------------------------------------------------------------
// Instance FDCE_7 of FDCE Module.
//------------------------------------------------------------------------------
FDCE FDCE_7(
	// Inputs.
	.C   (crg_clkin),
	.CE  (1'd1),
	.CLR (1'd0),
	.D   (reset6),

	// Outputs.
	.Q   (reset7)
);

//------------------------------------------------------------------------------
// Instance PLLE2_ADV of PLLE2_ADV Module.
//------------------------------------------------------------------------------
PLLE2_ADV #(
	// Parameters.
	.CLKFBOUT_MULT  (5'd16),
	.CLKIN1_PERIOD  (10.0),
	.CLKOUT0_DIVIDE (4'd8),
	.CLKOUT0_PHASE  (1'd0),
	.CLKOUT1_DIVIDE (4'd8),
	.CLKOUT1_PHASE  (1'd0),
	.CLKOUT2_DIVIDE (2'd2),
	.CLKOUT2_PHASE  (1'd0),
	.CLKOUT3_DIVIDE (2'd2),
	.CLKOUT3_PHASE  (7'd90),
	.DIVCLK_DIVIDE  (1'd1),
	.REF_JITTER1    (0.01),
	.STARTUP_WAIT   ("FALSE")
) PLLE2_ADV (
	// Inputs.
	.CLKFBIN  (pll_fb),
	.CLKIN1   (crg_clkin),
	.PWRDWN   (crg_power_down),
	.RST      (reset7),

	// Outputs.
	.CLKFBOUT (pll_fb),
	.CLKOUT0  (crg_clkout0),
	.CLKOUT1  (crg_clkout1),
	.CLKOUT2  (crg_clkout2),
	.CLKOUT3  (crg_clkout3),
	.LOCKED   (crg_locked)
);

//------------------------------------------------------------------------------
// Memory data_mem_grain0: 2-words x 8-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
reg [7:0] data_mem_grain0[0:1];
reg [0:0] data_mem_grain0_adr0;
always @(posedge sys_clk) begin
	if (litedramcore_data_port_we[0])
		data_mem_grain0[litedramcore_data_port_adr] <= litedramcore_data_port_dat_w[7:0];
	data_mem_grain0_adr0 <= litedramcore_data_port_adr;
end
assign litedramcore_data_port_dat_r[7:0] = data_mem_grain0[data_mem_grain0_adr0];


//------------------------------------------------------------------------------
// Memory data_mem_grain1: 2-words x 8-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
reg [7:0] data_mem_grain1[0:1];
reg [0:0] data_mem_grain1_adr0;
always @(posedge sys_clk) begin
	if (litedramcore_data_port_we[1])
		data_mem_grain1[litedramcore_data_port_adr] <= litedramcore_data_port_dat_w[15:8];
	data_mem_grain1_adr0 <= litedramcore_data_port_adr;
end
assign litedramcore_data_port_dat_r[15:8] = data_mem_grain1[data_mem_grain1_adr0];


//------------------------------------------------------------------------------
// Memory data_mem_grain2: 2-words x 8-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
reg [7:0] data_mem_grain2[0:1];
reg [0:0] data_mem_grain2_adr0;
always @(posedge sys_clk) begin
	if (litedramcore_data_port_we[2])
		data_mem_grain2[litedramcore_data_port_adr] <= litedramcore_data_port_dat_w[23:16];
	data_mem_grain2_adr0 <= litedramcore_data_port_adr;
end
assign litedramcore_data_port_dat_r[23:16] = data_mem_grain2[data_mem_grain2_adr0];


//------------------------------------------------------------------------------
// Memory data_mem_grain3: 2-words x 8-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
reg [7:0] data_mem_grain3[0:1];
reg [0:0] data_mem_grain3_adr0;
always @(posedge sys_clk) begin
	if (litedramcore_data_port_we[3])
		data_mem_grain3[litedramcore_data_port_adr] <= litedramcore_data_port_dat_w[31:24];
	data_mem_grain3_adr0 <= litedramcore_data_port_adr;
end
assign litedramcore_data_port_dat_r[31:24] = data_mem_grain3[data_mem_grain3_adr0];


//------------------------------------------------------------------------------
// Memory data_mem_grain4: 2-words x 8-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
reg [7:0] data_mem_grain4[0:1];
reg [0:0] data_mem_grain4_adr0;
always @(posedge sys_clk) begin
	if (litedramcore_data_port_we[4])
		data_mem_grain4[litedramcore_data_port_adr] <= litedramcore_data_port_dat_w[39:32];
	data_mem_grain4_adr0 <= litedramcore_data_port_adr;
end
assign litedramcore_data_port_dat_r[39:32] = data_mem_grain4[data_mem_grain4_adr0];


//------------------------------------------------------------------------------
// Memory data_mem_grain5: 2-words x 8-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
reg [7:0] data_mem_grain5[0:1];
reg [0:0] data_mem_grain5_adr0;
always @(posedge sys_clk) begin
	if (litedramcore_data_port_we[5])
		data_mem_grain5[litedramcore_data_port_adr] <= litedramcore_data_port_dat_w[47:40];
	data_mem_grain5_adr0 <= litedramcore_data_port_adr;
end
assign litedramcore_data_port_dat_r[47:40] = data_mem_grain5[data_mem_grain5_adr0];


//------------------------------------------------------------------------------
// Memory data_mem_grain6: 2-words x 8-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
reg [7:0] data_mem_grain6[0:1];
reg [0:0] data_mem_grain6_adr0;
always @(posedge sys_clk) begin
	if (litedramcore_data_port_we[6])
		data_mem_grain6[litedramcore_data_port_adr] <= litedramcore_data_port_dat_w[55:48];
	data_mem_grain6_adr0 <= litedramcore_data_port_adr;
end
assign litedramcore_data_port_dat_r[55:48] = data_mem_grain6[data_mem_grain6_adr0];


//------------------------------------------------------------------------------
// Memory data_mem_grain7: 2-words x 8-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
reg [7:0] data_mem_grain7[0:1];
reg [0:0] data_mem_grain7_adr0;
always @(posedge sys_clk) begin
	if (litedramcore_data_port_we[7])
		data_mem_grain7[litedramcore_data_port_adr] <= litedramcore_data_port_dat_w[63:56];
	data_mem_grain7_adr0 <= litedramcore_data_port_adr;
end
assign litedramcore_data_port_dat_r[63:56] = data_mem_grain7[data_mem_grain7_adr0];


//------------------------------------------------------------------------------
// Memory data_mem_grain8: 2-words x 8-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
reg [7:0] data_mem_grain8[0:1];
reg [0:0] data_mem_grain8_adr0;
always @(posedge sys_clk) begin
	if (litedramcore_data_port_we[8])
		data_mem_grain8[litedramcore_data_port_adr] <= litedramcore_data_port_dat_w[71:64];
	data_mem_grain8_adr0 <= litedramcore_data_port_adr;
end
assign litedramcore_data_port_dat_r[71:64] = data_mem_grain8[data_mem_grain8_adr0];


//------------------------------------------------------------------------------
// Memory data_mem_grain9: 2-words x 8-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
reg [7:0] data_mem_grain9[0:1];
reg [0:0] data_mem_grain9_adr0;
always @(posedge sys_clk) begin
	if (litedramcore_data_port_we[9])
		data_mem_grain9[litedramcore_data_port_adr] <= litedramcore_data_port_dat_w[79:72];
	data_mem_grain9_adr0 <= litedramcore_data_port_adr;
end
assign litedramcore_data_port_dat_r[79:72] = data_mem_grain9[data_mem_grain9_adr0];


//------------------------------------------------------------------------------
// Memory data_mem_grain10: 2-words x 8-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
reg [7:0] data_mem_grain10[0:1];
reg [0:0] data_mem_grain10_adr0;
always @(posedge sys_clk) begin
	if (litedramcore_data_port_we[10])
		data_mem_grain10[litedramcore_data_port_adr] <= litedramcore_data_port_dat_w[87:80];
	data_mem_grain10_adr0 <= litedramcore_data_port_adr;
end
assign litedramcore_data_port_dat_r[87:80] = data_mem_grain10[data_mem_grain10_adr0];


//------------------------------------------------------------------------------
// Memory data_mem_grain11: 2-words x 8-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
reg [7:0] data_mem_grain11[0:1];
reg [0:0] data_mem_grain11_adr0;
always @(posedge sys_clk) begin
	if (litedramcore_data_port_we[11])
		data_mem_grain11[litedramcore_data_port_adr] <= litedramcore_data_port_dat_w[95:88];
	data_mem_grain11_adr0 <= litedramcore_data_port_adr;
end
assign litedramcore_data_port_dat_r[95:88] = data_mem_grain11[data_mem_grain11_adr0];


//------------------------------------------------------------------------------
// Memory data_mem_grain12: 2-words x 8-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
reg [7:0] data_mem_grain12[0:1];
reg [0:0] data_mem_grain12_adr0;
always @(posedge sys_clk) begin
	if (litedramcore_data_port_we[12])
		data_mem_grain12[litedramcore_data_port_adr] <= litedramcore_data_port_dat_w[103:96];
	data_mem_grain12_adr0 <= litedramcore_data_port_adr;
end
assign litedramcore_data_port_dat_r[103:96] = data_mem_grain12[data_mem_grain12_adr0];


//------------------------------------------------------------------------------
// Memory data_mem_grain13: 2-words x 8-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
reg [7:0] data_mem_grain13[0:1];
reg [0:0] data_mem_grain13_adr0;
always @(posedge sys_clk) begin
	if (litedramcore_data_port_we[13])
		data_mem_grain13[litedramcore_data_port_adr] <= litedramcore_data_port_dat_w[111:104];
	data_mem_grain13_adr0 <= litedramcore_data_port_adr;
end
assign litedramcore_data_port_dat_r[111:104] = data_mem_grain13[data_mem_grain13_adr0];


//------------------------------------------------------------------------------
// Memory data_mem_grain14: 2-words x 8-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
reg [7:0] data_mem_grain14[0:1];
reg [0:0] data_mem_grain14_adr0;
always @(posedge sys_clk) begin
	if (litedramcore_data_port_we[14])
		data_mem_grain14[litedramcore_data_port_adr] <= litedramcore_data_port_dat_w[119:112];
	data_mem_grain14_adr0 <= litedramcore_data_port_adr;
end
assign litedramcore_data_port_dat_r[119:112] = data_mem_grain14[data_mem_grain14_adr0];


//------------------------------------------------------------------------------
// Memory data_mem_grain15: 2-words x 8-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
reg [7:0] data_mem_grain15[0:1];
reg [0:0] data_mem_grain15_adr0;
always @(posedge sys_clk) begin
	if (litedramcore_data_port_we[15])
		data_mem_grain15[litedramcore_data_port_adr] <= litedramcore_data_port_dat_w[127:120];
	data_mem_grain15_adr0 <= litedramcore_data_port_adr;
end
assign litedramcore_data_port_dat_r[127:120] = data_mem_grain15[data_mem_grain15_adr0];


//------------------------------------------------------------------------------
// Memory data_mem_grain16: 2-words x 8-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
reg [7:0] data_mem_grain16[0:1];
reg [0:0] data_mem_grain16_adr0;
always @(posedge sys_clk) begin
	if (litedramcore_data_port_we[16])
		data_mem_grain16[litedramcore_data_port_adr] <= litedramcore_data_port_dat_w[135:128];
	data_mem_grain16_adr0 <= litedramcore_data_port_adr;
end
assign litedramcore_data_port_dat_r[135:128] = data_mem_grain16[data_mem_grain16_adr0];


//------------------------------------------------------------------------------
// Memory data_mem_grain17: 2-words x 8-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
reg [7:0] data_mem_grain17[0:1];
reg [0:0] data_mem_grain17_adr0;
always @(posedge sys_clk) begin
	if (litedramcore_data_port_we[17])
		data_mem_grain17[litedramcore_data_port_adr] <= litedramcore_data_port_dat_w[143:136];
	data_mem_grain17_adr0 <= litedramcore_data_port_adr;
end
assign litedramcore_data_port_dat_r[143:136] = data_mem_grain17[data_mem_grain17_adr0];


//------------------------------------------------------------------------------
// Memory data_mem_grain18: 2-words x 8-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
reg [7:0] data_mem_grain18[0:1];
reg [0:0] data_mem_grain18_adr0;
always @(posedge sys_clk) begin
	if (litedramcore_data_port_we[18])
		data_mem_grain18[litedramcore_data_port_adr] <= litedramcore_data_port_dat_w[151:144];
	data_mem_grain18_adr0 <= litedramcore_data_port_adr;
end
assign litedramcore_data_port_dat_r[151:144] = data_mem_grain18[data_mem_grain18_adr0];


//------------------------------------------------------------------------------
// Memory data_mem_grain19: 2-words x 8-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
reg [7:0] data_mem_grain19[0:1];
reg [0:0] data_mem_grain19_adr0;
always @(posedge sys_clk) begin
	if (litedramcore_data_port_we[19])
		data_mem_grain19[litedramcore_data_port_adr] <= litedramcore_data_port_dat_w[159:152];
	data_mem_grain19_adr0 <= litedramcore_data_port_adr;
end
assign litedramcore_data_port_dat_r[159:152] = data_mem_grain19[data_mem_grain19_adr0];


//------------------------------------------------------------------------------
// Memory data_mem_grain20: 2-words x 8-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
reg [7:0] data_mem_grain20[0:1];
reg [0:0] data_mem_grain20_adr0;
always @(posedge sys_clk) begin
	if (litedramcore_data_port_we[20])
		data_mem_grain20[litedramcore_data_port_adr] <= litedramcore_data_port_dat_w[167:160];
	data_mem_grain20_adr0 <= litedramcore_data_port_adr;
end
assign litedramcore_data_port_dat_r[167:160] = data_mem_grain20[data_mem_grain20_adr0];


//------------------------------------------------------------------------------
// Memory data_mem_grain21: 2-words x 8-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
reg [7:0] data_mem_grain21[0:1];
reg [0:0] data_mem_grain21_adr0;
always @(posedge sys_clk) begin
	if (litedramcore_data_port_we[21])
		data_mem_grain21[litedramcore_data_port_adr] <= litedramcore_data_port_dat_w[175:168];
	data_mem_grain21_adr0 <= litedramcore_data_port_adr;
end
assign litedramcore_data_port_dat_r[175:168] = data_mem_grain21[data_mem_grain21_adr0];


//------------------------------------------------------------------------------
// Memory data_mem_grain22: 2-words x 8-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
reg [7:0] data_mem_grain22[0:1];
reg [0:0] data_mem_grain22_adr0;
always @(posedge sys_clk) begin
	if (litedramcore_data_port_we[22])
		data_mem_grain22[litedramcore_data_port_adr] <= litedramcore_data_port_dat_w[183:176];
	data_mem_grain22_adr0 <= litedramcore_data_port_adr;
end
assign litedramcore_data_port_dat_r[183:176] = data_mem_grain22[data_mem_grain22_adr0];


//------------------------------------------------------------------------------
// Memory data_mem_grain23: 2-words x 8-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
reg [7:0] data_mem_grain23[0:1];
reg [0:0] data_mem_grain23_adr0;
always @(posedge sys_clk) begin
	if (litedramcore_data_port_we[23])
		data_mem_grain23[litedramcore_data_port_adr] <= litedramcore_data_port_dat_w[191:184];
	data_mem_grain23_adr0 <= litedramcore_data_port_adr;
end
assign litedramcore_data_port_dat_r[191:184] = data_mem_grain23[data_mem_grain23_adr0];


//------------------------------------------------------------------------------
// Memory data_mem_grain24: 2-words x 8-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
reg [7:0] data_mem_grain24[0:1];
reg [0:0] data_mem_grain24_adr0;
always @(posedge sys_clk) begin
	if (litedramcore_data_port_we[24])
		data_mem_grain24[litedramcore_data_port_adr] <= litedramcore_data_port_dat_w[199:192];
	data_mem_grain24_adr0 <= litedramcore_data_port_adr;
end
assign litedramcore_data_port_dat_r[199:192] = data_mem_grain24[data_mem_grain24_adr0];


//------------------------------------------------------------------------------
// Memory data_mem_grain25: 2-words x 8-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
reg [7:0] data_mem_grain25[0:1];
reg [0:0] data_mem_grain25_adr0;
always @(posedge sys_clk) begin
	if (litedramcore_data_port_we[25])
		data_mem_grain25[litedramcore_data_port_adr] <= litedramcore_data_port_dat_w[207:200];
	data_mem_grain25_adr0 <= litedramcore_data_port_adr;
end
assign litedramcore_data_port_dat_r[207:200] = data_mem_grain25[data_mem_grain25_adr0];


//------------------------------------------------------------------------------
// Memory data_mem_grain26: 2-words x 8-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
reg [7:0] data_mem_grain26[0:1];
reg [0:0] data_mem_grain26_adr0;
always @(posedge sys_clk) begin
	if (litedramcore_data_port_we[26])
		data_mem_grain26[litedramcore_data_port_adr] <= litedramcore_data_port_dat_w[215:208];
	data_mem_grain26_adr0 <= litedramcore_data_port_adr;
end
assign litedramcore_data_port_dat_r[215:208] = data_mem_grain26[data_mem_grain26_adr0];


//------------------------------------------------------------------------------
// Memory data_mem_grain27: 2-words x 8-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
reg [7:0] data_mem_grain27[0:1];
reg [0:0] data_mem_grain27_adr0;
always @(posedge sys_clk) begin
	if (litedramcore_data_port_we[27])
		data_mem_grain27[litedramcore_data_port_adr] <= litedramcore_data_port_dat_w[223:216];
	data_mem_grain27_adr0 <= litedramcore_data_port_adr;
end
assign litedramcore_data_port_dat_r[223:216] = data_mem_grain27[data_mem_grain27_adr0];


//------------------------------------------------------------------------------
// Memory data_mem_grain28: 2-words x 8-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
reg [7:0] data_mem_grain28[0:1];
reg [0:0] data_mem_grain28_adr0;
always @(posedge sys_clk) begin
	if (litedramcore_data_port_we[28])
		data_mem_grain28[litedramcore_data_port_adr] <= litedramcore_data_port_dat_w[231:224];
	data_mem_grain28_adr0 <= litedramcore_data_port_adr;
end
assign litedramcore_data_port_dat_r[231:224] = data_mem_grain28[data_mem_grain28_adr0];


//------------------------------------------------------------------------------
// Memory data_mem_grain29: 2-words x 8-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
reg [7:0] data_mem_grain29[0:1];
reg [0:0] data_mem_grain29_adr0;
always @(posedge sys_clk) begin
	if (litedramcore_data_port_we[29])
		data_mem_grain29[litedramcore_data_port_adr] <= litedramcore_data_port_dat_w[239:232];
	data_mem_grain29_adr0 <= litedramcore_data_port_adr;
end
assign litedramcore_data_port_dat_r[239:232] = data_mem_grain29[data_mem_grain29_adr0];


//------------------------------------------------------------------------------
// Memory data_mem_grain30: 2-words x 8-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
reg [7:0] data_mem_grain30[0:1];
reg [0:0] data_mem_grain30_adr0;
always @(posedge sys_clk) begin
	if (litedramcore_data_port_we[30])
		data_mem_grain30[litedramcore_data_port_adr] <= litedramcore_data_port_dat_w[247:240];
	data_mem_grain30_adr0 <= litedramcore_data_port_adr;
end
assign litedramcore_data_port_dat_r[247:240] = data_mem_grain30[data_mem_grain30_adr0];


//------------------------------------------------------------------------------
// Memory data_mem_grain31: 2-words x 8-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
reg [7:0] data_mem_grain31[0:1];
reg [0:0] data_mem_grain31_adr0;
always @(posedge sys_clk) begin
	if (litedramcore_data_port_we[31])
		data_mem_grain31[litedramcore_data_port_adr] <= litedramcore_data_port_dat_w[255:248];
	data_mem_grain31_adr0 <= litedramcore_data_port_adr;
end
assign litedramcore_data_port_dat_r[255:248] = data_mem_grain31[data_mem_grain31_adr0];


(* ars_ff1 = "true", async_reg = "true" *)
//------------------------------------------------------------------------------
// Instance FDPE of FDPE Module.
//------------------------------------------------------------------------------
FDPE #(
	// Parameters.
	.INIT (1'd1)
) FDPE (
	// Inputs.
	.C   (iodelay_clk),
	.CE  (1'd1),
	.D   (1'd0),
	.PRE (xilinxasyncresetsynchronizerimpl0),

	// Outputs.
	.Q   (xilinxasyncresetsynchronizerimpl0_rst_meta)
);

(* ars_ff2 = "true", async_reg = "true" *)
//------------------------------------------------------------------------------
// Instance FDPE_1 of FDPE Module.
//------------------------------------------------------------------------------
FDPE #(
	// Parameters.
	.INIT (1'd1)
) FDPE_1 (
	// Inputs.
	.C   (iodelay_clk),
	.CE  (1'd1),
	.D   (xilinxasyncresetsynchronizerimpl0_rst_meta),
	.PRE (xilinxasyncresetsynchronizerimpl0),

	// Outputs.
	.Q   (iodelay_rst)
);

(* ars_ff1 = "true", async_reg = "true" *)
//------------------------------------------------------------------------------
// Instance FDPE_2 of FDPE Module.
//------------------------------------------------------------------------------
FDPE #(
	// Parameters.
	.INIT (1'd1)
) FDPE_2 (
	// Inputs.
	.C   (sys_clk),
	.CE  (1'd1),
	.D   (1'd0),
	.PRE (xilinxasyncresetsynchronizerimpl1),

	// Outputs.
	.Q   (xilinxasyncresetsynchronizerimpl1_rst_meta)
);

(* ars_ff2 = "true", async_reg = "true" *)
//------------------------------------------------------------------------------
// Instance FDPE_3 of FDPE Module.
//------------------------------------------------------------------------------
FDPE #(
	// Parameters.
	.INIT (1'd1)
) FDPE_3 (
	// Inputs.
	.C   (sys_clk),
	.CE  (1'd1),
	.D   (xilinxasyncresetsynchronizerimpl1_rst_meta),
	.PRE (xilinxasyncresetsynchronizerimpl1),

	// Outputs.
	.Q   (sys_rst)
);

(* ars_ff1 = "true", async_reg = "true" *)
//------------------------------------------------------------------------------
// Instance FDPE_4 of FDPE Module.
//------------------------------------------------------------------------------
FDPE #(
	// Parameters.
	.INIT (1'd1)
) FDPE_4 (
	// Inputs.
	.C   (sys4x_clk),
	.CE  (1'd1),
	.D   (1'd0),
	.PRE (xilinxasyncresetsynchronizerimpl2),

	// Outputs.
	.Q   (xilinxasyncresetsynchronizerimpl2_rst_meta)
);

(* ars_ff2 = "true", async_reg = "true" *)
//------------------------------------------------------------------------------
// Instance FDPE_5 of FDPE Module.
//------------------------------------------------------------------------------
FDPE #(
	// Parameters.
	.INIT (1'd1)
) FDPE_5 (
	// Inputs.
	.C   (sys4x_clk),
	.CE  (1'd1),
	.D   (xilinxasyncresetsynchronizerimpl2_rst_meta),
	.PRE (xilinxasyncresetsynchronizerimpl2),

	// Outputs.
	.Q   (xilinxasyncresetsynchronizerimpl2_expr)
);

(* ars_ff1 = "true", async_reg = "true" *)
//------------------------------------------------------------------------------
// Instance FDPE_6 of FDPE Module.
//------------------------------------------------------------------------------
FDPE #(
	// Parameters.
	.INIT (1'd1)
) FDPE_6 (
	// Inputs.
	.C   (sys4x_dqs_clk),
	.CE  (1'd1),
	.D   (1'd0),
	.PRE (xilinxasyncresetsynchronizerimpl3),

	// Outputs.
	.Q   (xilinxasyncresetsynchronizerimpl3_rst_meta)
);

(* ars_ff2 = "true", async_reg = "true" *)
//------------------------------------------------------------------------------
// Instance FDPE_7 of FDPE Module.
//------------------------------------------------------------------------------
FDPE #(
	// Parameters.
	.INIT (1'd1)
) FDPE_7 (
	// Inputs.
	.C   (sys4x_dqs_clk),
	.CE  (1'd1),
	.D   (xilinxasyncresetsynchronizerimpl3_rst_meta),
	.PRE (xilinxasyncresetsynchronizerimpl3),

	// Outputs.
	.Q   (xilinxasyncresetsynchronizerimpl3_expr)
);

endmodule

// -----------------------------------------------------------------------------
//  Auto-Generated by LiteX on 2025-06-25 17:27:30.
//------------------------------------------------------------------------------
