# 
# Synthesis run script generated by Vivado
# 

namespace eval rt {
    variable rc
}
set rt::rc [catch {
  uplevel #0 {
    set ::env(BUILTIN_SYNTH) true
    source $::env(HRT_TCL_PATH)/rtSynthPrep.tcl
    rt::HARTNDb_resetJobStats
    rt::HARTNDb_resetSystemStats
    rt::HARTNDb_startSystemStats
    rt::HARTNDb_startJobStats
    set rt::cmdEcho 0
    rt::set_parameter writeXmsg true
    rt::set_parameter enableParallelHelperSpawn true
    set ::env(RT_TMP) "./.Xil/Vivado-1862491-685a421e500f/realtime/tmp"
    if { [ info exists ::env(RT_TMP) ] } {
      file delete -force $::env(RT_TMP)
      file mkdir $::env(RT_TMP)
    }

    rt::delete_design

    rt::set_parameter datapathDensePacking false
    set rt::partid xc7a100tcsg324-1
    source $::env(HRT_TCL_PATH)/rtSynthParallelPrep.tcl
     file delete -force synth_hints.os

    set rt::multiChipSynthesisFlow false
    source $::env(SYNTH_COMMON)/common.tcl
    set rt::defaultWorkLibName xil_defaultlib
    rt::set_parameter defaultVhdlWorkLib xil_defaultlib

    rt::set_parameter loadVhdl2008Libs false
    rt::set_parameter loadVhdl2019Libs false
    rt::set_parameter deferParseUntilElab true
    rt::set_parameter sortHdlCommandLine true
    set rt::useElabCache false
    if {$rt::useElabCache == false} {
      rt::read_verilog -sv -include /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core {
      /eda/processor_ci/rtl/Grande-Risco-5.sv
      /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/grande_risco5_types.sv
      /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv
      /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu_control.sv
      /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv
      /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/cache_request_multiplexer.sv
      /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv
      /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv
      /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv
      /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/forwarding_unit.sv
      /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/Grande_Risco5.sv
      /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv
      /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv
      /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv
      /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/immediate_generator.sv
      /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/invalid_ir_check.sv
      /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/ir_decomp.sv
      /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv
      /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv
      /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mux.sv
      /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv
      /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/core.sv
      /eda/processor-ci-controller/modules/uart.sv
      /eda/processor_ci/internal/ahblite_to_wishbone.sv
      /eda/processor_ci/internal/axi4_to_wishbone.sv
      /eda/processor_ci/internal/axi4lite_to_wishbone.sv
      /eda/processor-ci-controller/rtl/fifo.sv
      /eda/processor-ci-controller/rtl/reset.sv
      /eda/processor-ci-controller/rtl/clk_divider.sv
      /eda/processor-ci-controller/rtl/memory.sv
      /eda/processor-ci-controller/rtl/interpreter.sv
      /eda/processor-ci-controller/rtl/controller.sv
      /eda/processor-ci-controller/rtl/timer.sv
      /eda/processor_ci/internal/fpga_top.sv
    }
      rt::read_verilog -include /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core {
      /eda/processor-ci-controller/modules/UART/rtl/uart_rx.v
      /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v
    }
      rt::filesetChecksum
    }
    rt::set_parameter usePostFindUniquification false
    set rt::top fpga_top
    rt::set_parameter enableIncremental true
    rt::set_parameter markDebugPreservationLevel "enable"
    set rt::reportTiming false
    rt::set_parameter elaborateOnly true
    rt::set_parameter elaborateRtl true
    rt::set_parameter eliminateRedundantBitOperator false
    rt::set_parameter dataflowBusHighlighting false
    rt::set_parameter generateDataflowBusNetlist false
    rt::set_parameter dataFlowViewInElab false
    rt::set_parameter busViewFixBrokenConnections false
    rt::set_parameter elaborateRtlOnlyFlow false
    rt::set_parameter writeBlackboxInterface true
    rt::set_parameter merge_flipflops true
    rt::set_parameter srlDepthThreshold 3
    rt::set_parameter rstSrlDepthThreshold 4
# MODE: 
    rt::set_parameter webTalkPath {}
    rt::set_parameter synthDebugLog false
    rt::set_parameter printModuleName false
    rt::set_parameter enableSplitFlowPath "./.Xil/Vivado-1862491-685a421e500f/"
    set ok_to_delete_rt_tmp true 
    if { [rt::get_parameter parallelDebug] } { 
       set ok_to_delete_rt_tmp false 
    } 
    if {$rt::useElabCache == false} {
        set oldMIITMVal [rt::get_parameter maxInputIncreaseToMerge]; rt::set_parameter maxInputIncreaseToMerge 1000
        set oldCDPCRL [rt::get_parameter createDfgPartConstrRecurLimit]; rt::set_parameter createDfgPartConstrRecurLimit 1
        $rt::db readXRFFile
      rt::run_rtlelab -module $rt::top
        rt::set_parameter maxInputIncreaseToMerge $oldMIITMVal
        rt::set_parameter createDfgPartConstrRecurLimit $oldCDPCRL
    }

    set rt::flowresult [ source $::env(SYNTH_COMMON)/flow.tcl ]
    rt::HARTNDb_stopJobStats
    if { $rt::flowresult == 1 } { return -code error }


    if { [ info exists ::env(RT_TMP) ] } {
      if { [info exists ok_to_delete_rt_tmp] && $ok_to_delete_rt_tmp } { 
        file delete -force $::env(RT_TMP)
      }
    }

    source $::env(HRT_TCL_PATH)/rtSynthCleanup.tcl
  } ; #end uplevel
} rt::result]

if { $rt::rc } {
  $rt::db resetHdlParse
  set hsKey [rt::get_parameter helper_shm_key] 
  if { $hsKey != "" && [info exists ::env(BUILTIN_SYNTH)] && [rt::get_parameter enableParallelHelperSpawn] } { 
     $rt::db killSynthHelper $hsKey
  } 
  source $::env(HRT_TCL_PATH)/rtSynthCleanup.tcl
  return -code "error" $rt::result
}
