
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.11.0
// timestamp : Mon May  8 04:40:30 2023 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.w.h.cgf \
 \
//                  -- xlen 32  \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.w.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.w.h_b24 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.w.h_b24)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x211e; valaddr_reg:x3;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)

inst_1:// rs1==f30, rd==x30,fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and  fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f30; dest:x30; op1val:0x211e; valaddr_reg:x3;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x30, f30, dyn, 32, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)

inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and  fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f29; dest:x29; op1val:0x211e; valaddr_reg:x3;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x29, f29, dyn, 64, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)

inst_3:// rs1==f28, rd==x28,fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and  fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f28; dest:x28; op1val:0x211e; valaddr_reg:x3;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x28, f28, dyn, 96, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)

inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and  fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f27; dest:x27; op1val:0x211e; valaddr_reg:x3;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x27, f27, dyn, 128, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)

inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f26; dest:x26; op1val:0x2e66; valaddr_reg:x3;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x26, f26, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)

inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and  fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f25; dest:x25; op1val:0x2e66; valaddr_reg:x3;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x25, f25, dyn, 32, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)

inst_7:// rs1==f24, rd==x24,fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and  fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f24; dest:x24; op1val:0x2e66; valaddr_reg:x3;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x24, f24, dyn, 64, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)

inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and  fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f23; dest:x23; op1val:0x2e66; valaddr_reg:x3;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x23, f23, dyn, 96, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)

inst_9:// rs1==f22, rd==x22,fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and  fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f22; dest:x22; op1val:0x2e66; valaddr_reg:x3;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x22, f22, dyn, 128, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)

inst_10:// rs1==f21, rd==x21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f21; dest:x21; op1val:0xf0; valaddr_reg:x3;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x21, f21, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)

inst_11:// rs1==f20, rd==x20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and  fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f20; dest:x20; op1val:0xf0; valaddr_reg:x3;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x20, f20, dyn, 32, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)

inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and  fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f19; dest:x19; op1val:0xf0; valaddr_reg:x3;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x19, f19, dyn, 64, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)

inst_13:// rs1==f18, rd==x18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and  fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f18; dest:x18; op1val:0xf0; valaddr_reg:x3;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x18, f18, dyn, 96, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)

inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and  fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f17; dest:x17; op1val:0xf0; valaddr_reg:x3;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x17, f17, dyn, 128, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)

inst_15:// rs1==f16, rd==x16,fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f16; dest:x16; op1val:0xbb1e; valaddr_reg:x3;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x16, f16, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)

inst_16:// rs1==f15, rd==x15,fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and  fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f15; dest:x15; op1val:0xbb1e; valaddr_reg:x3;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x15, f15, dyn, 32, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)

inst_17:// rs1==f14, rd==x14,fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and  fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f14; dest:x14; op1val:0xbb1e; valaddr_reg:x3;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x14, f14, dyn, 64, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)

inst_18:// rs1==f13, rd==x13,fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and  fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f13; dest:x13; op1val:0xbb1e; valaddr_reg:x3;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x13, f13, dyn, 96, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)

inst_19:// rs1==f12, rd==x12,fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and  fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f12; dest:x12; op1val:0xbb1e; valaddr_reg:x3;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x12, f12, dyn, 128, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)

inst_20:// rs1==f11, rd==x11,fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f11; dest:x11; op1val:0x2f0a; valaddr_reg:x3;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x11, f11, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)

inst_21:// rs1==f10, rd==x10,fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and  fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f10; dest:x10; op1val:0x2f0a; valaddr_reg:x3;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x10, f10, dyn, 32, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)

inst_22:// rs1==f9, rd==x9,fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and  fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f9; dest:x9; op1val:0x2f0a; valaddr_reg:x3;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x9, f9, dyn, 64, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)

inst_23:// rs1==f8, rd==x8,fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and  fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f8; dest:x8; op1val:0x2f0a; valaddr_reg:x3;
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x8, f8, dyn, 96, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
RVTEST_VALBASEUPD(x8,test_dataset_1)

inst_24:// rs1==f7, rd==x7,fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and  fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f7; dest:x7; op1val:0x2f0a; valaddr_reg:x8;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x7, f7, dyn, 128, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)

inst_25:// rs1==f6, rd==x6,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f6; dest:x6; op1val:0xaf0a; valaddr_reg:x8;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x6, f6, dyn, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)

inst_26:// rs1==f5, rd==x5,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and  fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f5; dest:x5; op1val:0xaf0a; valaddr_reg:x8;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x5, f5, dyn, 32, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
RVTEST_SIGBASE(x5,signature_x5_0)

inst_27:// rs1==f4, rd==x4,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and  fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f4; dest:x4; op1val:0xaf0a; valaddr_reg:x8;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x4, f4, dyn, 64, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)

inst_28:// rs1==f3, rd==x3,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and  fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f3; dest:x3; op1val:0xaf0a; valaddr_reg:x8;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x3, f3, dyn, 96, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)

inst_29:// rs1==f2, rd==x2,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and  fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f2; dest:x2; op1val:0xaf0a; valaddr_reg:x8;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x2, f2, dyn, 128, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)

inst_30:// rs1==f1, rd==x1,fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f1; dest:x1; op1val:0xae66; valaddr_reg:x8;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x1, f1, dyn, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)

inst_31:// rs1==f0, rd==x0,fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and  fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f0; dest:x0; op1val:0xae66; valaddr_reg:x8;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x0, f0, dyn, 32, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)

inst_32:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and  fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xae66; valaddr_reg:x8;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 8*FLEN/8, x9, x5, x6,FLREG)

inst_33:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and  fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xae66; valaddr_reg:x8;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 9*FLEN/8, x9, x5, x6,FLREG)

inst_34:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and  fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xae66; valaddr_reg:x8;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 10*FLEN/8, x9, x5, x6,FLREG)

inst_35:// fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xa11e; valaddr_reg:x8;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 11*FLEN/8, x9, x5, x6,FLREG)

inst_36:// fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and  fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xa11e; valaddr_reg:x8;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 12*FLEN/8, x9, x5, x6,FLREG)

inst_37:// fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and  fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xa11e; valaddr_reg:x8;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 13*FLEN/8, x9, x5, x6,FLREG)

inst_38:// fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and  fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xa11e; valaddr_reg:x8;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 14*FLEN/8, x9, x5, x6,FLREG)

inst_39:// fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and  fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xa11e; valaddr_reg:x8;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 15*FLEN/8, x9, x5, x6,FLREG)

inst_40:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc00; valaddr_reg:x8;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 16*FLEN/8, x9, x5, x6,FLREG)

inst_41:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and  fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc00; valaddr_reg:x8;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 17*FLEN/8, x9, x5, x6,FLREG)

inst_42:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and  fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc00; valaddr_reg:x8;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 18*FLEN/8, x9, x5, x6,FLREG)

inst_43:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc00; valaddr_reg:x8;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 19*FLEN/8, x9, x5, x6,FLREG)

inst_44:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and  fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc00; valaddr_reg:x8;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 20*FLEN/8, x9, x5, x6,FLREG)

inst_45:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc66; valaddr_reg:x8;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 21*FLEN/8, x9, x5, x6,FLREG)

inst_46:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and  fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc66; valaddr_reg:x8;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 22*FLEN/8, x9, x5, x6,FLREG)

inst_47:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and  fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc66; valaddr_reg:x8;
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 23*FLEN/8, x9, x5, x6,FLREG)

inst_48:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and  fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc66; valaddr_reg:x8;
val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 24*FLEN/8, x9, x5, x6,FLREG)

inst_49:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and  fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc66; valaddr_reg:x8;
val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 25*FLEN/8, x9, x5, x6,FLREG)

inst_50:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c70; valaddr_reg:x8;
val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 26*FLEN/8, x9, x5, x6,FLREG)

inst_51:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and  fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c70; valaddr_reg:x8;
val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 27*FLEN/8, x9, x5, x6,FLREG)

inst_52:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and  fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c70; valaddr_reg:x8;
val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 28*FLEN/8, x9, x5, x6,FLREG)

inst_53:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and  fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c70; valaddr_reg:x8;
val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 29*FLEN/8, x9, x5, x6,FLREG)

inst_54:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and  fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c70; valaddr_reg:x8;
val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 30*FLEN/8, x9, x5, x6,FLREG)

inst_55:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c00; valaddr_reg:x8;
val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 31*FLEN/8, x9, x5, x6,FLREG)

inst_56:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and  fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c00; valaddr_reg:x8;
val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 32*FLEN/8, x9, x5, x6,FLREG)

inst_57:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and  fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c00; valaddr_reg:x8;
val_offset:33*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 33*FLEN/8, x9, x5, x6,FLREG)

inst_58:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c00; valaddr_reg:x8;
val_offset:34*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 34*FLEN/8, x9, x5, x6,FLREG)

inst_59:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and  fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c00; valaddr_reg:x8;
val_offset:35*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 35*FLEN/8, x9, x5, x6,FLREG)

inst_60:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbb33; valaddr_reg:x8;
val_offset:36*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 36*FLEN/8, x9, x5, x6,FLREG)

inst_61:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and  fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbb33; valaddr_reg:x8;
val_offset:37*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 37*FLEN/8, x9, x5, x6,FLREG)

inst_62:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and  fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbb33; valaddr_reg:x8;
val_offset:38*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 38*FLEN/8, x9, x5, x6,FLREG)

inst_63:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and  fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbb33; valaddr_reg:x8;
val_offset:39*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 39*FLEN/8, x9, x5, x6,FLREG)

inst_64:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and  fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbb33; valaddr_reg:x8;
val_offset:40*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 40*FLEN/8, x9, x5, x6,FLREG)

inst_65:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3b1e; valaddr_reg:x8;
val_offset:41*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 41*FLEN/8, x9, x5, x6,FLREG)

inst_66:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and  fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3b1e; valaddr_reg:x8;
val_offset:42*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 42*FLEN/8, x9, x5, x6,FLREG)

inst_67:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and  fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3b1e; valaddr_reg:x8;
val_offset:43*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 43*FLEN/8, x9, x5, x6,FLREG)

inst_68:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and  fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3b1e; valaddr_reg:x8;
val_offset:44*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 44*FLEN/8, x9, x5, x6,FLREG)

inst_69:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and  fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3b1e; valaddr_reg:x8;
val_offset:45*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 45*FLEN/8, x9, x5, x6,FLREG)

inst_70:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc70; valaddr_reg:x8;
val_offset:46*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 46*FLEN/8, x9, x5, x6,FLREG)

inst_71:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and  fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc70; valaddr_reg:x8;
val_offset:47*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 47*FLEN/8, x9, x5, x6,FLREG)

inst_72:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and  fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc70; valaddr_reg:x8;
val_offset:48*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 48*FLEN/8, x9, x5, x6,FLREG)

inst_73:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and  fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc70; valaddr_reg:x8;
val_offset:49*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 49*FLEN/8, x9, x5, x6,FLREG)

inst_74:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and  fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc70; valaddr_reg:x8;
val_offset:50*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 50*FLEN/8, x9, x5, x6,FLREG)

inst_75:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbbeb; valaddr_reg:x8;
val_offset:51*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 51*FLEN/8, x9, x5, x6,FLREG)

inst_76:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and  fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbbeb; valaddr_reg:x8;
val_offset:52*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 52*FLEN/8, x9, x5, x6,FLREG)

inst_77:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and  fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbbeb; valaddr_reg:x8;
val_offset:53*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 53*FLEN/8, x9, x5, x6,FLREG)

inst_78:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and  fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbbeb; valaddr_reg:x8;
val_offset:54*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 54*FLEN/8, x9, x5, x6,FLREG)

inst_79:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and  fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbbeb; valaddr_reg:x8;
val_offset:55*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 55*FLEN/8, x9, x5, x6,FLREG)

inst_80:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc0a; valaddr_reg:x8;
val_offset:56*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 56*FLEN/8, x9, x5, x6,FLREG)

inst_81:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and  fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc0a; valaddr_reg:x8;
val_offset:57*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 57*FLEN/8, x9, x5, x6,FLREG)

inst_82:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and  fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc0a; valaddr_reg:x8;
val_offset:58*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 58*FLEN/8, x9, x5, x6,FLREG)

inst_83:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and  fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc0a; valaddr_reg:x8;
val_offset:59*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 59*FLEN/8, x9, x5, x6,FLREG)

inst_84:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and  fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc0a; valaddr_reg:x8;
val_offset:60*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 60*FLEN/8, x9, x5, x6,FLREG)

inst_85:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c66; valaddr_reg:x8;
val_offset:61*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 61*FLEN/8, x9, x5, x6,FLREG)

inst_86:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and  fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c66; valaddr_reg:x8;
val_offset:62*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 62*FLEN/8, x9, x5, x6,FLREG)

inst_87:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and  fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c66; valaddr_reg:x8;
val_offset:63*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 63*FLEN/8, x9, x5, x6,FLREG)

inst_88:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and  fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c66; valaddr_reg:x8;
val_offset:64*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 64*FLEN/8, x9, x5, x6,FLREG)

inst_89:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and  fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c66; valaddr_reg:x8;
val_offset:65*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 65*FLEN/8, x9, x5, x6,FLREG)

inst_90:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c0a; valaddr_reg:x8;
val_offset:66*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 66*FLEN/8, x9, x5, x6,FLREG)

inst_91:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and  fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c0a; valaddr_reg:x8;
val_offset:67*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 67*FLEN/8, x9, x5, x6,FLREG)

inst_92:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and  fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c0a; valaddr_reg:x8;
val_offset:68*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 68*FLEN/8, x9, x5, x6,FLREG)

inst_93:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and  fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c0a; valaddr_reg:x8;
val_offset:69*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 69*FLEN/8, x9, x5, x6,FLREG)

inst_94:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and  fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c0a; valaddr_reg:x8;
val_offset:70*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 70*FLEN/8, x9, x5, x6,FLREG)

inst_95:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3beb; valaddr_reg:x8;
val_offset:71*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 71*FLEN/8, x9, x5, x6,FLREG)

inst_96:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and  fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3beb; valaddr_reg:x8;
val_offset:72*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 72*FLEN/8, x9, x5, x6,FLREG)

inst_97:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and  fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3beb; valaddr_reg:x8;
val_offset:73*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 73*FLEN/8, x9, x5, x6,FLREG)

inst_98:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and  fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3beb; valaddr_reg:x8;
val_offset:74*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 74*FLEN/8, x9, x5, x6,FLREG)

inst_99:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and  fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3beb; valaddr_reg:x8;
val_offset:75*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 75*FLEN/8, x9, x5, x6,FLREG)

inst_100:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3b33; valaddr_reg:x8;
val_offset:76*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 76*FLEN/8, x9, x5, x6,FLREG)

inst_101:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and  fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3b33; valaddr_reg:x8;
val_offset:77*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 77*FLEN/8, x9, x5, x6,FLREG)

inst_102:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and  fcsr == 0x40 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3b33; valaddr_reg:x8;
val_offset:78*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 78*FLEN/8, x9, x5, x6,FLREG)

inst_103:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and  fcsr == 0x60 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3b33; valaddr_reg:x8;
val_offset:79*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 79*FLEN/8, x9, x5, x6,FLREG)

inst_104:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and  fcsr == 0x80 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3b33; valaddr_reg:x8;
val_offset:80*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 80*FLEN/8, x9, x5, x6,FLREG)

inst_105:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and  fcsr == 0x20 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xae66; valaddr_reg:x8;
val_offset:81*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 81*FLEN/8, x9, x5, x6,FLREG)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(8478,16,FLEN)
NAN_BOXED(8478,16,FLEN)
NAN_BOXED(8478,16,FLEN)
NAN_BOXED(8478,16,FLEN)
NAN_BOXED(8478,16,FLEN)
NAN_BOXED(11878,16,FLEN)
NAN_BOXED(11878,16,FLEN)
NAN_BOXED(11878,16,FLEN)
NAN_BOXED(11878,16,FLEN)
NAN_BOXED(11878,16,FLEN)
NAN_BOXED(240,16,FLEN)
NAN_BOXED(240,16,FLEN)
NAN_BOXED(240,16,FLEN)
NAN_BOXED(240,16,FLEN)
NAN_BOXED(240,16,FLEN)
NAN_BOXED(47902,16,FLEN)
NAN_BOXED(47902,16,FLEN)
NAN_BOXED(47902,16,FLEN)
NAN_BOXED(47902,16,FLEN)
NAN_BOXED(47902,16,FLEN)
NAN_BOXED(12042,16,FLEN)
NAN_BOXED(12042,16,FLEN)
NAN_BOXED(12042,16,FLEN)
NAN_BOXED(12042,16,FLEN)
test_dataset_1:
NAN_BOXED(12042,16,FLEN)
NAN_BOXED(44810,16,FLEN)
NAN_BOXED(44810,16,FLEN)
NAN_BOXED(44810,16,FLEN)
NAN_BOXED(44810,16,FLEN)
NAN_BOXED(44810,16,FLEN)
NAN_BOXED(44646,16,FLEN)
NAN_BOXED(44646,16,FLEN)
NAN_BOXED(44646,16,FLEN)
NAN_BOXED(44646,16,FLEN)
NAN_BOXED(44646,16,FLEN)
NAN_BOXED(41246,16,FLEN)
NAN_BOXED(41246,16,FLEN)
NAN_BOXED(41246,16,FLEN)
NAN_BOXED(41246,16,FLEN)
NAN_BOXED(41246,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(48230,16,FLEN)
NAN_BOXED(48230,16,FLEN)
NAN_BOXED(48230,16,FLEN)
NAN_BOXED(48230,16,FLEN)
NAN_BOXED(48230,16,FLEN)
NAN_BOXED(15472,16,FLEN)
NAN_BOXED(15472,16,FLEN)
NAN_BOXED(15472,16,FLEN)
NAN_BOXED(15472,16,FLEN)
NAN_BOXED(15472,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(47923,16,FLEN)
NAN_BOXED(47923,16,FLEN)
NAN_BOXED(47923,16,FLEN)
NAN_BOXED(47923,16,FLEN)
NAN_BOXED(47923,16,FLEN)
NAN_BOXED(15134,16,FLEN)
NAN_BOXED(15134,16,FLEN)
NAN_BOXED(15134,16,FLEN)
NAN_BOXED(15134,16,FLEN)
NAN_BOXED(15134,16,FLEN)
NAN_BOXED(48240,16,FLEN)
NAN_BOXED(48240,16,FLEN)
NAN_BOXED(48240,16,FLEN)
NAN_BOXED(48240,16,FLEN)
NAN_BOXED(48240,16,FLEN)
NAN_BOXED(48107,16,FLEN)
NAN_BOXED(48107,16,FLEN)
NAN_BOXED(48107,16,FLEN)
NAN_BOXED(48107,16,FLEN)
NAN_BOXED(48107,16,FLEN)
NAN_BOXED(48138,16,FLEN)
NAN_BOXED(48138,16,FLEN)
NAN_BOXED(48138,16,FLEN)
NAN_BOXED(48138,16,FLEN)
NAN_BOXED(48138,16,FLEN)
NAN_BOXED(15462,16,FLEN)
NAN_BOXED(15462,16,FLEN)
NAN_BOXED(15462,16,FLEN)
NAN_BOXED(15462,16,FLEN)
NAN_BOXED(15462,16,FLEN)
NAN_BOXED(15370,16,FLEN)
NAN_BOXED(15370,16,FLEN)
NAN_BOXED(15370,16,FLEN)
NAN_BOXED(15370,16,FLEN)
NAN_BOXED(15370,16,FLEN)
NAN_BOXED(15339,16,FLEN)
NAN_BOXED(15339,16,FLEN)
NAN_BOXED(15339,16,FLEN)
NAN_BOXED(15339,16,FLEN)
NAN_BOXED(15339,16,FLEN)
NAN_BOXED(15155,16,FLEN)
NAN_BOXED(15155,16,FLEN)
NAN_BOXED(15155,16,FLEN)
NAN_BOXED(15155,16,FLEN)
NAN_BOXED(15155,16,FLEN)
NAN_BOXED(44646,16,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;



signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 54*((SIGALIGN)/4),4,0xdeadbeef


signature_x5_0:
    .fill 158*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;

mtrap_sigptr:
    .fill 64*XLEN/32,4,0xdeadbeef

tsig_end_canary:
CANARY;
#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif


sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
