
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.11.0
// timestamp : Mon May  8 06:10:56 2023 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64H/rv64h_fcvt.lu.h.cgf \
 \
//                  -- xlen 64  \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.lu.h instruction of the RISC-V RV64F_Zicsr_Zfh extension for the fcvt.lu.h_b27 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV64IF_Zicsr_Zfh")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.lu.h_b27)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.lu.h ; op1:f31; dest:x31; op1val:0x7c01; valaddr_reg:x3;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.lu.h, x31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)

inst_1:// rs1==f30, rd==x30,fs1 == 1 and fe1 == 0x1f and fm1 == 0x001 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.lu.h ; op1:f30; dest:x30; op1val:0xfc01; valaddr_reg:x3;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.lu.h, x30, f30, dyn, 0, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)

inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x1f and fm1 == 0x155 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.lu.h ; op1:f29; dest:x29; op1val:0x7d55; valaddr_reg:x3;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.lu.h, x29, f29, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)

inst_3:// rs1==f28, rd==x28,fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.lu.h ; op1:f28; dest:x28; op1val:0xfd55; valaddr_reg:x3;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.lu.h, x28, f28, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)

inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.lu.h ; op1:f27; dest:x27; op1val:0x7e01; valaddr_reg:x3;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.lu.h, x27, f27, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)

inst_5:// rs1==f26, rd==x26,fs1 == 1 and fe1 == 0x1f and fm1 == 0x201 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.lu.h ; op1:f26; dest:x26; op1val:0xfe01; valaddr_reg:x3;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.lu.h, x26, f26, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)

inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x1f and fm1 == 0x255 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.lu.h ; op1:f25; dest:x25; op1val:0x7e55; valaddr_reg:x3;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.lu.h, x25, f25, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)

inst_7:// rs1==f24, rd==x24,fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.lu.h ; op1:f24; dest:x24; op1val:0xfe55; valaddr_reg:x3;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.lu.h, x24, f24, dyn, 0, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)

inst_8:// rs1==f23, rd==x23,
/* opcode: fcvt.lu.h ; op1:f23; dest:x23; op1val:0x0; valaddr_reg:x3;
val_offset:8*FLEN/8; rmval:rne; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.lu.h, x23, f23, rne, 0, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)

inst_9:// rs1==f22, rd==x22,
/* opcode: fcvt.lu.h ; op1:f22; dest:x22; op1val:0x0; valaddr_reg:x3;
val_offset:9*FLEN/8; rmval:rne; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.lu.h, x22, f22, rne, 0, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)

inst_10:// rs1==f21, rd==x21,
/* opcode: fcvt.lu.h ; op1:f21; dest:x21; op1val:0x0; valaddr_reg:x3;
val_offset:10*FLEN/8; rmval:rne; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.lu.h, x21, f21, rne, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)

inst_11:// rs1==f20, rd==x20,
/* opcode: fcvt.lu.h ; op1:f20; dest:x20; op1val:0x0; valaddr_reg:x3;
val_offset:11*FLEN/8; rmval:rne; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.lu.h, x20, f20, rne, 0, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)

inst_12:// rs1==f19, rd==x19,
/* opcode: fcvt.lu.h ; op1:f19; dest:x19; op1val:0x0; valaddr_reg:x3;
val_offset:12*FLEN/8; rmval:rne; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.lu.h, x19, f19, rne, 0, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)

inst_13:// rs1==f18, rd==x18,
/* opcode: fcvt.lu.h ; op1:f18; dest:x18; op1val:0x0; valaddr_reg:x3;
val_offset:13*FLEN/8; rmval:rne; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.lu.h, x18, f18, rne, 0, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)

inst_14:// rs1==f17, rd==x17,
/* opcode: fcvt.lu.h ; op1:f17; dest:x17; op1val:0x0; valaddr_reg:x3;
val_offset:14*FLEN/8; rmval:rne; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.lu.h, x17, f17, rne, 0, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)

inst_15:// rs1==f16, rd==x16,
/* opcode: fcvt.lu.h ; op1:f16; dest:x16; op1val:0x0; valaddr_reg:x3;
val_offset:15*FLEN/8; rmval:rne; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.lu.h, x16, f16, rne, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)

inst_16:// rs1==f15, rd==x15,
/* opcode: fcvt.lu.h ; op1:f15; dest:x15; op1val:0x0; valaddr_reg:x3;
val_offset:16*FLEN/8; rmval:rne; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.lu.h, x15, f15, rne, 0, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)

inst_17:// rs1==f14, rd==x14,
/* opcode: fcvt.lu.h ; op1:f14; dest:x14; op1val:0x0; valaddr_reg:x3;
val_offset:17*FLEN/8; rmval:rne; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.lu.h, x14, f14, rne, 0, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)

inst_18:// rs1==f13, rd==x13,
/* opcode: fcvt.lu.h ; op1:f13; dest:x13; op1val:0x0; valaddr_reg:x3;
val_offset:18*FLEN/8; rmval:rne; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.lu.h, x13, f13, rne, 0, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)

inst_19:// rs1==f12, rd==x12,
/* opcode: fcvt.lu.h ; op1:f12; dest:x12; op1val:0x0; valaddr_reg:x3;
val_offset:19*FLEN/8; rmval:rne; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.lu.h, x12, f12, rne, 0, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)

inst_20:// rs1==f11, rd==x11,
/* opcode: fcvt.lu.h ; op1:f11; dest:x11; op1val:0x0; valaddr_reg:x3;
val_offset:20*FLEN/8; rmval:rne; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.lu.h, x11, f11, rne, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)

inst_21:// rs1==f10, rd==x10,
/* opcode: fcvt.lu.h ; op1:f10; dest:x10; op1val:0x0; valaddr_reg:x3;
val_offset:21*FLEN/8; rmval:rne; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.lu.h, x10, f10, rne, 0, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)

inst_22:// rs1==f9, rd==x9,
/* opcode: fcvt.lu.h ; op1:f9; dest:x9; op1val:0x0; valaddr_reg:x3;
val_offset:22*FLEN/8; rmval:rne; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.lu.h, x9, f9, rne, 0, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)

inst_23:// rs1==f8, rd==x8,
/* opcode: fcvt.lu.h ; op1:f8; dest:x8; op1val:0x0; valaddr_reg:x3;
val_offset:23*FLEN/8; rmval:rne; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.lu.h, x8, f8, rne, 0, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
RVTEST_VALBASEUPD(x8,test_dataset_1)

inst_24:// rs1==f7, rd==x7,
/* opcode: fcvt.lu.h ; op1:f7; dest:x7; op1val:0x0; valaddr_reg:x8;
val_offset:0*FLEN/8; rmval:rne; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.lu.h, x7, f7, rne, 0, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)

inst_25:// rs1==f6, rd==x6,
/* opcode: fcvt.lu.h ; op1:f6; dest:x6; op1val:0x0; valaddr_reg:x8;
val_offset:1*FLEN/8; rmval:rne; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.lu.h, x6, f6, rne, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)

inst_26:// rs1==f5, rd==x5,
/* opcode: fcvt.lu.h ; op1:f5; dest:x5; op1val:0x0; valaddr_reg:x8;
val_offset:2*FLEN/8; rmval:rne; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.lu.h, x5, f5, rne, 0, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
RVTEST_SIGBASE(x5,signature_x5_0)

inst_27:// rs1==f4, rd==x4,
/* opcode: fcvt.lu.h ; op1:f4; dest:x4; op1val:0x0; valaddr_reg:x8;
val_offset:3*FLEN/8; rmval:rne; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.lu.h, x4, f4, rne, 0, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)

inst_28:// rs1==f3, rd==x3,
/* opcode: fcvt.lu.h ; op1:f3; dest:x3; op1val:0x0; valaddr_reg:x8;
val_offset:4*FLEN/8; rmval:rne; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.lu.h, x3, f3, rne, 0, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)

inst_29:// rs1==f2, rd==x2,
/* opcode: fcvt.lu.h ; op1:f2; dest:x2; op1val:0x0; valaddr_reg:x8;
val_offset:5*FLEN/8; rmval:rne; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.lu.h, x2, f2, rne, 0, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)

inst_30:// rs1==f1, rd==x1,
/* opcode: fcvt.lu.h ; op1:f1; dest:x1; op1val:0x0; valaddr_reg:x8;
val_offset:6*FLEN/8; rmval:rne; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.lu.h, x1, f1, rne, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)

inst_31:// rs1==f0, rd==x0,
/* opcode: fcvt.lu.h ; op1:f0; dest:x0; op1val:0x0; valaddr_reg:x8;
val_offset:7*FLEN/8; rmval:rne; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.lu.h, x0, f0, rne, 0, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(64513,16,FLEN)
NAN_BOXED(32085,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(65025,16,FLEN)
NAN_BOXED(32341,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
test_dataset_1:
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;



signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 54*((SIGALIGN)/4),4,0xdeadbeef


signature_x5_0:
    .fill 10*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;

mtrap_sigptr:
    .fill 64*XLEN/32,4,0xdeadbeef

tsig_end_canary:
CANARY;
#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif


sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
