
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.12.2
// timestamp : Fri Sep 13 19:12:48 2024 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.d.h.cgf \
 \
//                  -- xlen 32  \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.d.h instruction of the RISC-V RV32FD_Zicsr_Zfh,RV64FD_Zicsr_Zfh extension for the fcvt.d.h_b24 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IFD_Zicsr_Zfh,RV64IFD_Zicsr_Zfh")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.d.h_b24)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_0:
// rs1 == rd, rs1==f31, rd==f31,fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.d.h ; op1:f31; dest:f31; op1val:0xbc0a; valaddr_reg:x3;
val_offset:0*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.h, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) 

inst_1:
// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.d.h ; op1:f29; dest:f30; op1val:0x3c00; valaddr_reg:x3;
val_offset:1*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.h, f30, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) 

inst_2:
// rs1==f30, rd==f29,fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.d.h ; op1:f30; dest:f29; op1val:0xa11e; valaddr_reg:x3;
val_offset:2*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.h, f29, f30, 0, 0, x3, 2*FLEN/8, x4, x1, x2) 

inst_3:
// rs1==f27, rd==f28,fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.d.h ; op1:f27; dest:f28; op1val:0xbb33; valaddr_reg:x3;
val_offset:3*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.h, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) 

inst_4:
// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.d.h ; op1:f28; dest:f27; op1val:0xf0; valaddr_reg:x3;
val_offset:4*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.h, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) 

inst_5:
// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.d.h ; op1:f25; dest:f26; op1val:0x2f0a; valaddr_reg:x3;
val_offset:5*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.h, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) 

inst_6:
// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.d.h ; op1:f26; dest:f25; op1val:0x3c70; valaddr_reg:x3;
val_offset:6*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.h, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) 

inst_7:
// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.d.h ; op1:f23; dest:f24; op1val:0xbc66; valaddr_reg:x3;
val_offset:7*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.h, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) 

inst_8:
// rs1==f24, rd==f23,fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.d.h ; op1:f24; dest:f23; op1val:0xae66; valaddr_reg:x3;
val_offset:8*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.h, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) 

inst_9:
// rs1==f21, rd==f22,fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.d.h ; op1:f21; dest:f22; op1val:0x3b1e; valaddr_reg:x3;
val_offset:9*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.h, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) 

inst_10:
// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.d.h ; op1:f22; dest:f21; op1val:0x3beb; valaddr_reg:x3;
val_offset:10*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.h, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) 

inst_11:
// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.d.h ; op1:f19; dest:f20; op1val:0x3b33; valaddr_reg:x3;
val_offset:11*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.h, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) 

inst_12:
// rs1==f20, rd==f19,fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.d.h ; op1:f20; dest:f19; op1val:0xbc00; valaddr_reg:x3;
val_offset:12*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.h, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) 

inst_13:
// rs1==f17, rd==f18,fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.d.h ; op1:f17; dest:f18; op1val:0xbc70; valaddr_reg:x3;
val_offset:13*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.h, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) 

inst_14:
// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.d.h ; op1:f18; dest:f17; op1val:0x211e; valaddr_reg:x3;
val_offset:14*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.h, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) 

inst_15:
// rs1==f15, rd==f16,fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.d.h ; op1:f15; dest:f16; op1val:0x2e66; valaddr_reg:x3;
val_offset:15*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.h, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) 

inst_16:
// rs1==f16, rd==f15,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.d.h ; op1:f16; dest:f15; op1val:0xaf0a; valaddr_reg:x3;
val_offset:16*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.h, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) 

inst_17:
// rs1==f13, rd==f14,fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.d.h ; op1:f13; dest:f14; op1val:0x3c66; valaddr_reg:x3;
val_offset:17*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.h, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) 

inst_18:
// rs1==f14, rd==f13,fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.d.h ; op1:f14; dest:f13; op1val:0xbbeb; valaddr_reg:x3;
val_offset:18*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.h, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) 

inst_19:
// rs1==f11, rd==f12,fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.d.h ; op1:f11; dest:f12; op1val:0x3c0a; valaddr_reg:x3;
val_offset:19*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.h, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) 

inst_20:
// rs1==f12, rd==f11,fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff  
/* opcode: fcvt.d.h ; op1:f12; dest:f11; op1val:0xbb1e; valaddr_reg:x3;
val_offset:20*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.h, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) 

inst_21:
// rs1==f9, rd==f10,
/* opcode: fcvt.d.h ; op1:f9; dest:f10; op1val:0x0; valaddr_reg:x3;
val_offset:21*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.h, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) 

inst_22:
// rs1==f10, rd==f9,
/* opcode: fcvt.d.h ; op1:f10; dest:f9; op1val:0x0; valaddr_reg:x3;
val_offset:22*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.h, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) 

inst_23:
// rs1==f7, rd==f8,
/* opcode: fcvt.d.h ; op1:f7; dest:f8; op1val:0x0; valaddr_reg:x3;
val_offset:23*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.h, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) 

inst_24:
// rs1==f8, rd==f7,
/* opcode: fcvt.d.h ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3;
val_offset:24*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.h, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) 

inst_25:
// rs1==f5, rd==f6,
/* opcode: fcvt.d.h ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3;
val_offset:25*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.h, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) 

inst_26:
// rs1==f6, rd==f5,
/* opcode: fcvt.d.h ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3;
val_offset:26*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.h, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) 

inst_27:
// rs1==f3, rd==f4,
/* opcode: fcvt.d.h ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3;
val_offset:27*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.h, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) 

inst_28:
// rs1==f4, rd==f3,
/* opcode: fcvt.d.h ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3;
val_offset:28*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.h, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) 

inst_29:
// rs1==f1, rd==f2,
/* opcode: fcvt.d.h ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3;
val_offset:29*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.h, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) 

inst_30:
// rs1==f2, rd==f1,
/* opcode: fcvt.d.h ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3;
val_offset:30*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.h, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) 

inst_31:
// rs1==f0,
/* opcode: fcvt.d.h ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3;
val_offset:31*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.h, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) 

inst_32:
// rd==f0,
/* opcode: fcvt.d.h ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3;
val_offset:32*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.h, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) 
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(48138,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(41246,16,FLEN)
NAN_BOXED(47923,16,FLEN)
NAN_BOXED(240,16,FLEN)
NAN_BOXED(12042,16,FLEN)
NAN_BOXED(15472,16,FLEN)
NAN_BOXED(48230,16,FLEN)
NAN_BOXED(44646,16,FLEN)
NAN_BOXED(15134,16,FLEN)
NAN_BOXED(15339,16,FLEN)
NAN_BOXED(15155,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(48240,16,FLEN)
NAN_BOXED(8478,16,FLEN)
NAN_BOXED(11878,16,FLEN)
NAN_BOXED(44810,16,FLEN)
NAN_BOXED(15462,16,FLEN)
NAN_BOXED(48107,16,FLEN)
NAN_BOXED(15370,16,FLEN)
NAN_BOXED(47902,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;



signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 66*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;

mtrap_sigptr:
    .fill 64*XLEN/32,4,0xdeadbeef

tsig_end_canary:
CANARY;
#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif


sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
