
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.11.0
// timestamp : Tue Jan 30 08:43:40 2024 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fmadd.cgf \
 \
//                  -- xlen 32  \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fmadd.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fmadd_b2 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fmadd_b2)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_0:
// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==f30, rs2==f29, rs3==f29, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x050 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x266 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x021 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f29; dest:f31; op1val:0x50; op2val:0xb666;
op3val:0xb666; valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f29, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)

inst_1:
// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==f29, rs2==f31, rs3==f30, rd==f29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x05f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x369 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x02e and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f29; op2:f31; op3:f30; dest:f29; op1val:0x5f; op2val:0xb769;
op3val:0x2e; valaddr_reg:x3; val_offset:3*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f29, f29, f31, f30, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2)

inst_2:
// rs1 == rs2 == rs3 != rd, rs1==f28, rs2==f28, rs3==f28, rd==f30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x059 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x017 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x05f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f28; op2:f28; op3:f28; dest:f30; op1val:0x59; op2val:0x59;
op3val:0x59; valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f30, f28, f28, f28, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2)

inst_3:
// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==f27, rs2==f27, rs3==f31, rd==f28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x054 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b6 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x044 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f27; op2:f27; op3:f31; dest:f28; op1val:0x54; op2val:0x54;
op3val:0x44; valaddr_reg:x3; val_offset:9*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f28, f27, f27, f31, dyn, 0, 0, x3, 9*FLEN/8, x4, x1, x2)

inst_4:
// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==f26, rs2==f30, rs3==f26, rd==f27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x004 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x180 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x03c and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f26; op2:f30; op3:f26; dest:f27; op1val:0x4; op2val:0xc980;
op3val:0x4; valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f27, f26, f30, f26, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2)

inst_5:
// rd == rs2 == rs3 != rs1, rs1==f31, rs2==f25, rs3==f25, rd==f25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x020 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x280 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x054 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f31; op2:f25; op3:f25; dest:f25; op1val:0x20; op2val:0xbe80;
op3val:0xbe80; valaddr_reg:x3; val_offset:15*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f25, f31, f25, f25, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2)

inst_6:
// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==f25, rs2==f24, rs3==f27, rd==f26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x224 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x015 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f25; op2:f24; op3:f27; dest:f26; op1val:0x7; op2val:0x4624;
op3val:0x15; valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f26, f25, f24, f27, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2)

inst_7:
// rs1 == rs2 == rs3 == rd, rs1==f23, rs2==f23, rs3==f23, rd==f23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x11 and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x030 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f23; op2:f23; op3:f23; dest:f23; op1val:0xf; op2val:0xf;
op3val:0xf; valaddr_reg:x3; val_offset:21*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f23, f23, f23, f23, dyn, 0, 0, x3, 21*FLEN/8, x4, x1, x2)

inst_8:
// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==f22, rs2==f26, rs3==f24, rd==f24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x03d and fs2 == 0 and fe2 == 0x10 and fm2 == 0x358 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x020 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f22; op2:f26; op3:f24; dest:f24; op1val:0x3d; op2val:0x4358;
op3val:0x20; valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f24, f22, f26, f24, dyn, 0, 0, x3, 24*FLEN/8, x4, x1, x2)

inst_9:
// rs1 == rs2 == rd != rs3, rs1==f21, rs2==f21, rs3==f22, rd==f21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x031 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x082 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x046 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f21; op2:f21; op3:f22; dest:f21; op1val:0x31; op2val:0x31;
op3val:0x46; valaddr_reg:x3; val_offset:27*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f21, f21, f21, f22, dyn, 0, 0, x3, 27*FLEN/8, x4, x1, x2)

inst_10:
// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==f24, rs2==f22, rs3==f21, rd==f22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 1 and fe2 == 0x11 and fm2 == 0x15b and fs3 == 0 and fe3 == 0x00 and fm3 == 0x04a and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f24; op2:f22; op3:f21; dest:f22; op1val:0xe; op2val:0xc55b;
op3val:0x4a; valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f22, f24, f22, f21, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)

inst_11:
// rs1 == rd == rs3 != rs2, rs1==f20, rs2==f19, rs3==f20, rd==f20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x020 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f20; op2:f19; op3:f20; dest:f20; op1val:0x20; op2val:0xb000;
op3val:0x20; valaddr_reg:x3; val_offset:33*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f20, f20, f19, f20, dyn, 0, 0, x3, 33*FLEN/8, x4, x1, x2)

inst_12:
// rs1==f18, rs2==f20, rs3==f17, rd==f19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x05e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x172 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x01c and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f18; op2:f20; op3:f17; dest:f19; op1val:0x5e; op2val:0xb572;
op3val:0x1c; valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f19, f18, f20, f17, dyn, 0, 0, x3, 36*FLEN/8, x4, x1, x2)

inst_13:
// rs1==f19, rs2==f17, rs3==f16, rd==f18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x035 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2a4 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x024 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f19; op2:f17; op3:f16; dest:f18; op1val:0x35; op2val:0xbaa4;
op3val:0x24; valaddr_reg:x3; val_offset:39*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f18, f19, f17, f16, dyn, 0, 0, x3, 39*FLEN/8, x4, x1, x2)

inst_14:
// rs1==f16, rs2==f18, rs3==f19, rd==f17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x018 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0ca and fs3 == 0 and fe3 == 0x00 and fm3 == 0x063 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f16; op2:f18; op3:f19; dest:f17; op1val:0x18; op2val:0xc4ca;
op3val:0x63; valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f17, f16, f18, f19, dyn, 0, 0, x3, 42*FLEN/8, x4, x1, x2)

inst_15:
// rs1==f17, rs2==f15, rs3==f18, rd==f16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x032 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03d and fs3 == 0 and fe3 == 0x00 and fm3 == 0x015 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f17; op2:f15; op3:f18; dest:f16; op1val:0x32; op2val:0xbc3d;
op3val:0x15; valaddr_reg:x3; val_offset:45*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f16, f17, f15, f18, dyn, 0, 0, x3, 45*FLEN/8, x4, x1, x2)

inst_16:
// rs1==f14, rs2==f16, rs3==f13, rd==f15,fs1 == 0 and fe1 == 0x00 and fm1 == 0x062 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x20a and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00a and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f14; op2:f16; op3:f13; dest:f15; op1val:0x62; op2val:0xba0a;
op3val:0xa; valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f15, f14, f16, f13, dyn, 0, 0, x3, 48*FLEN/8, x4, x1, x2)

inst_17:
// rs1==f15, rs2==f13, rs3==f12, rd==f14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x012 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x1c7 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x050 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f15; op2:f13; op3:f12; dest:f14; op1val:0x12; op2val:0xc9c7;
op3val:0x50; valaddr_reg:x3; val_offset:51*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f14, f15, f13, f12, dyn, 0, 0, x3, 51*FLEN/8, x4, x1, x2)

inst_18:
// rs1==f12, rs2==f14, rs3==f15, rd==f13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x050 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3d3 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x039 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f12; op2:f14; op3:f15; dest:f13; op1val:0x50; op2val:0xc3d3;
op3val:0x39; valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f13, f12, f14, f15, dyn, 0, 0, x3, 54*FLEN/8, x4, x1, x2)

inst_19:
// rs1==f13, rs2==f11, rs3==f14, rd==f12,fs1 == 0 and fe1 == 0x00 and fm1 == 0x011 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x3c7 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x011 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f13; op2:f11; op3:f14; dest:f12; op1val:0x11; op2val:0xcfc7;
op3val:0x11; valaddr_reg:x3; val_offset:57*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f12, f13, f11, f14, dyn, 0, 0, x3, 57*FLEN/8, x4, x1, x2)

inst_20:
// rs1==f10, rs2==f12, rs3==f9, rd==f11,fs1 == 0 and fe1 == 0x0f and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0f0 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f10; op2:f12; op3:f9; dest:f11; op1val:0x3c01; op2val:0xf0;
op3val:0x3c01; valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f11, f10, f12, f9, dyn, 0, 0, x3, 60*FLEN/8, x4, x1, x2)

inst_21:
// rs1==f11, rs2==f9, rs3==f8, rd==f10,fs1 == 0 and fe1 == 0x0f and fm1 == 0x01b and fs2 == 1 and fe2 == 0x09 and fm2 == 0x255 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x01c and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f11; op2:f9; op3:f8; dest:f10; op1val:0x3c1b; op2val:0xa655;
op3val:0x3c1c; valaddr_reg:x3; val_offset:63*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f10, f11, f9, f8, dyn, 0, 0, x3, 63*FLEN/8, x4, x1, x2)

inst_22:
// rs1==f8, rs2==f10, rs3==f11, rd==f9,fs1 == 0 and fe1 == 0x0f and fm1 == 0x016 and fs2 == 1 and fe2 == 0x09 and fm2 == 0x067 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x016 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f8; op2:f10; op3:f11; dest:f9; op1val:0x3c16; op2val:0xa467;
op3val:0x3c16; valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f9, f8, f10, f11, dyn, 0, 0, x3, 66*FLEN/8, x4, x1, x2)

inst_23:
// rs1==f9, rs2==f7, rs3==f10, rd==f8,fs1 == 0 and fe1 == 0x0f and fm1 == 0x026 and fs2 == 1 and fe2 == 0x09 and fm2 == 0x3f4 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x029 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f9; op2:f7; op3:f10; dest:f8; op1val:0x3c26; op2val:0xa7f4;
op3val:0x3c29; valaddr_reg:x3; val_offset:69*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f8, f9, f7, f10, dyn, 0, 0, x3, 69*FLEN/8, x4, x1, x2)

inst_24:
// rs1==f6, rs2==f8, rs3==f5, rd==f7,fs1 == 0 and fe1 == 0x0f and fm1 == 0x01a and fs2 == 1 and fe2 == 0x0a and fm2 == 0x295 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x046 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f6; op2:f8; op3:f5; dest:f7; op1val:0x3c1a; op2val:0xaa95;
op3val:0x3c46; valaddr_reg:x3; val_offset:72*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f7, f6, f8, f5, dyn, 0, 0, x3, 72*FLEN/8, x4, x1, x2)

inst_25:
// rs1==f7, rs2==f5, rs3==f4, rd==f6,fs1 == 0 and fe1 == 0x0f and fm1 == 0x057 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x051 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f7; op2:f5; op3:f4; dest:f6; op1val:0x3c57; op2val:0xa9a5;
op3val:0x3c51; valaddr_reg:x3; val_offset:75*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f6, f7, f5, f4, dyn, 0, 0, x3, 75*FLEN/8, x4, x1, x2)

inst_26:
// rs1==f4, rs2==f6, rs3==f7, rd==f5,fs1 == 0 and fe1 == 0x0f and fm1 == 0x01b and fs2 == 0 and fe2 == 0x0a and fm2 == 0x0df and fs3 == 0 and fe3 == 0x0f and fm3 == 0x018 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f4; op2:f6; op3:f7; dest:f5; op1val:0x3c1b; op2val:0x28df;
op3val:0x3c18; valaddr_reg:x3; val_offset:78*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f5, f4, f6, f7, dyn, 0, 0, x3, 78*FLEN/8, x4, x1, x2)

inst_27:
// rs1==f5, rs2==f3, rs3==f6, rd==f4,fs1 == 0 and fe1 == 0x0f and fm1 == 0x059 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x0f and fm3 == 0x01a and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f5; op2:f3; op3:f6; dest:f4; op1val:0x3c59; op2val:0x2ddd;
op3val:0x3c1a; valaddr_reg:x3; val_offset:81*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f4, f5, f3, f6, dyn, 0, 0, x3, 81*FLEN/8, x4, x1, x2)

inst_28:
// rs1==f2, rs2==f4, rs3==f1, rd==f3,fs1 == 0 and fe1 == 0x0f and fm1 == 0x032 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x277 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x027 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f2; op2:f4; op3:f1; dest:f3; op1val:0x3c32; op2val:0x3277;
op3val:0x3c27; valaddr_reg:x3; val_offset:84*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f3, f2, f4, f1, dyn, 0, 0, x3, 84*FLEN/8, x4, x1, x2)

inst_29:
// rs1==f3, rs2==f1, rs3==f0, rd==f2,fs1 == 0 and fe1 == 0x0f and fm1 == 0x003 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x33e and fs3 == 0 and fe3 == 0x0f and fm3 == 0x02f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f3; op2:f1; op3:f0; dest:f2; op1val:0x3c03; op2val:0x373e;
op3val:0x3c2f; valaddr_reg:x3; val_offset:87*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f2, f3, f1, f0, dyn, 0, 0, x3, 87*FLEN/8, x4, x1, x2)

inst_30:
// rs1==f0, rs2==f2, rs3==f3, rd==f1,fs1 == 0 and fe1 == 0x0f and fm1 == 0x036 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3af and fs3 == 0 and fe3 == 0x0f and fm3 == 0x016 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f0; op2:f2; op3:f3; dest:f1; op1val:0x3c36; op2val:0xbfaf;
op3val:0x3c16; valaddr_reg:x3; val_offset:90*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f1, f0, f2, f3, dyn, 0, 0, x3, 90*FLEN/8, x4, x1, x2)

inst_31:
// rs1==f1,fs1 == 0 and fe1 == 0x0f and fm1 == 0x013 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x0f and fm3 == 0x022 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f1; op2:f30; op3:f29; dest:f31; op1val:0x3c13; op2val:0xbffe;
op3val:0x3c22; valaddr_reg:x3; val_offset:93*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f1, f30, f29, dyn, 0, 0, x3, 93*FLEN/8, x4, x1, x2)

inst_32:
// rs2==f0,fs1 == 0 and fe1 == 0x0f and fm1 == 0x009 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x00e and fs3 == 0 and fe3 == 0x0f and fm3 == 0x02b and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f0; op3:f29; dest:f31; op1val:0x3c09; op2val:0xc00e;
op3val:0x3c2b; valaddr_reg:x3; val_offset:96*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f0, f29, dyn, 0, 0, x3, 96*FLEN/8, x4, x1, x2)

inst_33:
// rs3==f2,fs1 == 0 and fe1 == 0x0f and fm1 == 0x027 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x003 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x04e and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f2; dest:f31; op1val:0x3c27; op2val:0xc003;
op3val:0x3c4e; valaddr_reg:x3; val_offset:99*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f2, dyn, 0, 0, x3, 99*FLEN/8, x4, x1, x2)

inst_34:
// rd==f0,fs1 == 0 and fe1 == 0x0f and fm1 == 0x04c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x382 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f31; op2:f30; op3:f29; dest:f0; op1val:0x3c4c; op2val:0xbf82;
op3val:0x3c01; valaddr_reg:x3; val_offset:102*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f0, f31, f30, f29, dyn, 0, 0, x3, 102*FLEN/8, x4, x1, x2)

inst_35:
// fs1 == 0 and fe1 == 0x0f and fm1 == 0x04d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3df and fs3 == 0 and fe3 == 0x0f and fm3 == 0x057 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3c4d; op2val:0xbfdf;
op3val:0x3c57; valaddr_reg:x3; val_offset:105*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 105*FLEN/8, x4, x1, x2)

inst_36:
// fs1 == 0 and fe1 == 0x0f and fm1 == 0x05b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3bc and fs3 == 0 and fe3 == 0x0f and fm3 == 0x02c and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3c5b; op2val:0xbfbc;
op3val:0x3c2c; valaddr_reg:x3; val_offset:108*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 108*FLEN/8, x4, x1, x2)

inst_37:
// fs1 == 0 and fe1 == 0x0f and fm1 == 0x009 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x04a and fs3 == 0 and fe3 == 0x0f and fm3 == 0x028 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3c09; op2val:0xc04a;
op3val:0x3c28; valaddr_reg:x3; val_offset:111*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 111*FLEN/8, x4, x1, x2)

inst_38:
// fs1 == 0 and fe1 == 0x0f and fm1 == 0x02e and fs2 == 1 and fe2 == 0x10 and fm2 == 0x061 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x028 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3c2e; op2val:0xc061;
op3val:0x3c28; valaddr_reg:x3; val_offset:114*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 114*FLEN/8, x4, x1, x2)

inst_39:
// fs1 == 0 and fe1 == 0x0f and fm1 == 0x03e and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0e1 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x05a and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3c3e; op2val:0xc0e1;
op3val:0x3c5a; valaddr_reg:x3; val_offset:117*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 117*FLEN/8, x4, x1, x2)

inst_40:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x029 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x07c and fs3 == 0 and fe3 == 0x00 and fm3 == 0x018 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x29; op2val:0xb87c;
op3val:0x18; valaddr_reg:x3; val_offset:120*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 120*FLEN/8, x4, x1, x2)

inst_41:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x37b and fs3 == 0 and fe3 == 0x00 and fm3 == 0x03d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3e; op2val:0xbb7b;
op3val:0x3d; valaddr_reg:x3; val_offset:123*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 123*FLEN/8, x4, x1, x2)

inst_42:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05b and fs2 == 1 and fe2 == 0x0c and fm2 == 0x254 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x017 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5b; op2val:0xb254;
op3val:0x17; valaddr_reg:x3; val_offset:126*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 126*FLEN/8, x4, x1, x2)

inst_43:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x008 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x021 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x8; op2val:0xc200;
op3val:0x21; valaddr_reg:x3; val_offset:129*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 129*FLEN/8, x4, x1, x2)

inst_44:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x295 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x060 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3; op2val:0xce95;
op3val:0x60; valaddr_reg:x3; val_offset:132*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 132*FLEN/8, x4, x1, x2)

inst_45:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x29b and fs3 == 0 and fe3 == 0x00 and fm3 == 0x034 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2e; op2val:0xb69b;
op3val:0x34; valaddr_reg:x3; val_offset:135*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 135*FLEN/8, x4, x1, x2)

inst_46:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x047 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3; op2val:0xc000;
op3val:0x47; valaddr_reg:x3; val_offset:138*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 138*FLEN/8, x4, x1, x2)

inst_47:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x036 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x212 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x02f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x36; op2val:0x3e12;
op3val:0x2f; valaddr_reg:x3; val_offset:141*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 141*FLEN/8, x4, x1, x2)

inst_48:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x031 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x36d and fs3 == 0 and fe3 == 0x00 and fm3 == 0x04b and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x31; op2val:0x436d;
op3val:0x4b; valaddr_reg:x3; val_offset:144*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 144*FLEN/8, x4, x1, x2)

inst_49:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fs2 == 0 and fe2 == 0x16 and fm2 == 0x31c and fs3 == 0 and fe3 == 0x00 and fm3 == 0x03a and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2; op2val:0x5b1c;
op3val:0x3a; valaddr_reg:x3; val_offset:147*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 147*FLEN/8, x4, x1, x2)

inst_50:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x006 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x3aa and fs3 == 0 and fe3 == 0x00 and fm3 == 0x05b and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6; op2val:0xcbaa;
op3val:0x5b; valaddr_reg:x3; val_offset:150*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 150*FLEN/8, x4, x1, x2)

inst_51:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x018 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x00 and fm3 == 0x050 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x18; op2val:0xc2ea;
op3val:0x50; valaddr_reg:x3; val_offset:153*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 153*FLEN/8, x4, x1, x2)

inst_52:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x276 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x010 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1a; op2val:0xba76;
op3val:0x10; valaddr_reg:x3; val_offset:156*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 156*FLEN/8, x4, x1, x2)

inst_53:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x061 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2c3 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x020 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x61; op2val:0xb6c3;
op3val:0x20; valaddr_reg:x3; val_offset:159*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 159*FLEN/8, x4, x1, x2)

inst_54:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x022 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x02d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3c; op2val:0xbc22;
op3val:0x2d; valaddr_reg:x3; val_offset:162*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 162*FLEN/8, x4, x1, x2)

inst_55:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x042 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c9 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x02e and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x42; op2val:0xbcc9;
op3val:0x2e; valaddr_reg:x3; val_offset:165*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 165*FLEN/8, x4, x1, x2)

inst_56:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x044 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1c3 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x021 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x44; op2val:0xbdc3;
op3val:0x21; valaddr_reg:x3; val_offset:168*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 168*FLEN/8, x4, x1, x2)

inst_57:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0c4 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00e and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3c; op2val:0xc0c4;
op3val:0xe; valaddr_reg:x3; val_offset:171*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 171*FLEN/8, x4, x1, x2)

inst_58:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04c and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0a5 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x060 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4c; op2val:0xc4a5;
op3val:0x60; valaddr_reg:x3; val_offset:174*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 174*FLEN/8, x4, x1, x2)

inst_59:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x030 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x1bd and fs3 == 0 and fe3 == 0x00 and fm3 == 0x026 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x30; op2val:0xc9bd;
op3val:0x26; valaddr_reg:x3; val_offset:177*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 177*FLEN/8, x4, x1, x2)

inst_60:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x005 and fs2 == 0 and fe2 == 0x16 and fm2 == 0x209 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x038 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5; op2val:0x5a09;
op3val:0x38; valaddr_reg:x3; val_offset:180*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 180*FLEN/8, x4, x1, x2)

inst_61:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00c and fs2 == 0 and fe2 == 0x15 and fm2 == 0x12d and fs3 == 0 and fe3 == 0x00 and fm3 == 0x01b and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xc; op2val:0x552d;
op3val:0x1b; valaddr_reg:x3; val_offset:183*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 183*FLEN/8, x4, x1, x2)

inst_62:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02c and fs2 == 0 and fe2 == 0x13 and fm2 == 0x16a and fs3 == 0 and fe3 == 0x00 and fm3 == 0x042 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x2c; op2val:0x4d6a;
op3val:0x42; valaddr_reg:x3; val_offset:186*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 186*FLEN/8, x4, x1, x2)

inst_63:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04f and fs2 == 0 and fe2 == 0x12 and fm2 == 0x220 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x02f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4f; op2val:0x4a20;
op3val:0x2f; valaddr_reg:x3; val_offset:189*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 189*FLEN/8, x4, x1, x2)

inst_64:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x013 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x02c and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x13; op2val:0x5255;
op3val:0x2c; valaddr_reg:x3; val_offset:192*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 192*FLEN/8, x4, x1, x2)

inst_65:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x024 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x241 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x05a and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x24; op2val:0x4e41;
op3val:0x5a; valaddr_reg:x3; val_offset:195*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 195*FLEN/8, x4, x1, x2)

inst_66:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x046 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x2c3 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00c and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x46; op2val:0x4ac3;
op3val:0xc; valaddr_reg:x3; val_offset:198*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 198*FLEN/8, x4, x1, x2)

inst_67:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x028 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x10b and fs3 == 0 and fe3 == 0x00 and fm3 == 0x058 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x28; op2val:0x4d0b;
op3val:0x58; valaddr_reg:x3; val_offset:201*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 201*FLEN/8, x4, x1, x2)

inst_68:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x029 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x06e and fs3 == 0 and fe3 == 0x00 and fm3 == 0x028 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x29; op2val:0x4c6e;
op3val:0x28; valaddr_reg:x3; val_offset:204*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 204*FLEN/8, x4, x1, x2)

inst_69:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x017 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x16f and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00b and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x17; op2val:0x4d6f;
op3val:0xb; valaddr_reg:x3; val_offset:207*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 207*FLEN/8, x4, x1, x2)

inst_70:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x051 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x26e and fs3 == 0 and fe3 == 0x00 and fm3 == 0x014 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x51; op2val:0xca6e;
op3val:0x14; valaddr_reg:x3; val_offset:210*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 210*FLEN/8, x4, x1, x2)

inst_71:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05d and fs2 == 1 and fe2 == 0x12 and fm2 == 0x1f7 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x059 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5d; op2val:0xc9f7;
op3val:0x59; valaddr_reg:x3; val_offset:213*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 213*FLEN/8, x4, x1, x2)

inst_72:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x028 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x2c1 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x03e and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x28; op2val:0xcec1;
op3val:0x3e; valaddr_reg:x3; val_offset:216*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 216*FLEN/8, x4, x1, x2)

inst_73:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x015 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x298 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x05d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x15; op2val:0xd298;
op3val:0x5d; valaddr_reg:x3; val_offset:219*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 219*FLEN/8, x4, x1, x2)

inst_74:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x16 and fm2 == 0x08b and fs3 == 0 and fe3 == 0x00 and fm3 == 0x00b and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7; op2val:0xd88b;
op3val:0xb; valaddr_reg:x3; val_offset:222*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 222*FLEN/8, x4, x1, x2)

inst_75:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04d and fs2 == 1 and fe2 == 0x12 and fm2 == 0x2e2 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x045 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4d; op2val:0xcae2;
op3val:0x45; valaddr_reg:x3; val_offset:225*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 225*FLEN/8, x4, x1, x2)

inst_76:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x034 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x0a2 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x005 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x34; op2val:0xcca2;
op3val:0x5; valaddr_reg:x3; val_offset:228*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 228*FLEN/8, x4, x1, x2)

inst_77:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01f and fs2 == 1 and fe2 == 0x13 and fm2 == 0x3fb and fs3 == 0 and fe3 == 0x00 and fm3 == 0x05f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x1f; op2val:0xcffb;
op3val:0x5f; valaddr_reg:x3; val_offset:231*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 231*FLEN/8, x4, x1, x2)

inst_78:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04d and fs2 == 1 and fe2 == 0x12 and fm2 == 0x145 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x02d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4d; op2val:0xc945;
op3val:0x2d; valaddr_reg:x3; val_offset:234*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 234*FLEN/8, x4, x1, x2)

inst_79:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x021 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x051 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x03b and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x21; op2val:0xcc51;
op3val:0x3b; valaddr_reg:x3; val_offset:237*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 237*FLEN/8, x4, x1, x2)

inst_80:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x054 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x21f and fs3 == 0 and fe3 == 0x01 and fm3 == 0x036 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x454; op2val:0xaa1f;
op3val:0x436; valaddr_reg:x3; val_offset:240*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 240*FLEN/8, x4, x1, x2)

inst_81:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x013 and fs2 == 1 and fe2 == 0x07 and fm2 == 0x1e4 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x008 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x413; op2val:0x9de4;
op3val:0x408; valaddr_reg:x3; val_offset:243*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 243*FLEN/8, x4, x1, x2)

inst_82:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x052 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x368 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x005 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x452; op2val:0x9368;
op3val:0x405; valaddr_reg:x3; val_offset:246*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 246*FLEN/8, x4, x1, x2)

inst_83:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x040 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x01e and fs3 == 0 and fe3 == 0x01 and fm3 == 0x02b and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x440; op2val:0xa81e;
op3val:0x42b; valaddr_reg:x3; val_offset:249*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 249*FLEN/8, x4, x1, x2)

inst_84:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x01b and fs2 == 1 and fe2 == 0x04 and fm2 == 0x3cb and fs3 == 0 and fe3 == 0x01 and fm3 == 0x011 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x41b; op2val:0x93cb;
op3val:0x411; valaddr_reg:x3; val_offset:252*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 252*FLEN/8, x4, x1, x2)

inst_85:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x05e and fs2 == 1 and fe2 == 0x0a and fm2 == 0x0b1 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x049 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x45e; op2val:0xa8b1;
op3val:0x449; valaddr_reg:x3; val_offset:255*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 255*FLEN/8, x4, x1, x2)

inst_86:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x011 and fs2 == 1 and fe2 == 0x09 and fm2 == 0x02e and fs3 == 0 and fe3 == 0x01 and fm3 == 0x051 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x411; op2val:0xa42e;
op3val:0x451; valaddr_reg:x3; val_offset:258*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 258*FLEN/8, x4, x1, x2)

inst_87:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x035 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2c6 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x00e and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x435; op2val:0x2ec6;
op3val:0x40e; valaddr_reg:x3; val_offset:261*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 261*FLEN/8, x4, x1, x2)

inst_88:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x016 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x21e and fs3 == 0 and fe3 == 0x01 and fm3 == 0x038 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x416; op2val:0x321e;
op3val:0x438; valaddr_reg:x3; val_offset:264*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 264*FLEN/8, x4, x1, x2)

inst_89:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x030 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x357 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x014 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x430; op2val:0x3757;
op3val:0x414; valaddr_reg:x3; val_offset:267*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 267*FLEN/8, x4, x1, x2)

inst_90:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x008 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x013 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x036 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x408; op2val:0xc013;
op3val:0x436; valaddr_reg:x3; val_offset:270*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 270*FLEN/8, x4, x1, x2)

inst_91:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x026 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3ca and fs3 == 0 and fe3 == 0x01 and fm3 == 0x013 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x426; op2val:0xbfca;
op3val:0x413; valaddr_reg:x3; val_offset:273*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 273*FLEN/8, x4, x1, x2)

inst_92:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x03b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3df and fs3 == 0 and fe3 == 0x01 and fm3 == 0x050 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x43b; op2val:0xbfdf;
op3val:0x450; valaddr_reg:x3; val_offset:276*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 276*FLEN/8, x4, x1, x2)

inst_93:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x016 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x00f and fs3 == 0 and fe3 == 0x01 and fm3 == 0x043 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x416; op2val:0xc00f;
op3val:0x443; valaddr_reg:x3; val_offset:279*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 279*FLEN/8, x4, x1, x2)

inst_94:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x03b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3db and fs3 == 0 and fe3 == 0x01 and fm3 == 0x03f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x43b; op2val:0xbfdb;
op3val:0x43f; valaddr_reg:x3; val_offset:282*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 282*FLEN/8, x4, x1, x2)

inst_95:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x059 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3d0 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x05e and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x459; op2val:0xbfd0;
op3val:0x45e; valaddr_reg:x3; val_offset:285*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 285*FLEN/8, x4, x1, x2)

inst_96:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x029 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x015 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x03e and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x429; op2val:0xc015;
op3val:0x43e; valaddr_reg:x3; val_offset:288*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 288*FLEN/8, x4, x1, x2)

inst_97:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x024 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x02d and fs3 == 0 and fe3 == 0x01 and fm3 == 0x026 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x424; op2val:0xc02d;
op3val:0x426; valaddr_reg:x3; val_offset:291*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 291*FLEN/8, x4, x1, x2)

inst_98:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x03d and fs2 == 1 and fe2 == 0x10 and fm2 == 0x057 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x034 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x43d; op2val:0xc057;
op3val:0x434; valaddr_reg:x3; val_offset:294*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 294*FLEN/8, x4, x1, x2)

inst_99:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x013 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0f0 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x00f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x413; op2val:0xc0f0;
op3val:0x40f; valaddr_reg:x3; val_offset:297*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 297*FLEN/8, x4, x1, x2)

inst_100:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x031 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x31a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x045 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7831; op2val:0x3b1a;
op3val:0x7845; valaddr_reg:x3; val_offset:300*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 300*FLEN/8, x4, x1, x2)

inst_101:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x017 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x32e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x051 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7817; op2val:0x3b2e;
op3val:0x7851; valaddr_reg:x3; val_offset:303*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 303*FLEN/8, x4, x1, x2)

inst_102:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x040 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x32b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x02c and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7840; op2val:0x3b2b;
op3val:0x782c; valaddr_reg:x3; val_offset:306*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 306*FLEN/8, x4, x1, x2)

inst_103:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x018 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3a8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00c and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7818; op2val:0x3ba8;
op3val:0x780c; valaddr_reg:x3; val_offset:309*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 309*FLEN/8, x4, x1, x2)

inst_104:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x327 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x023 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x783f; op2val:0x3b27;
op3val:0x7823; valaddr_reg:x3; val_offset:312*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 312*FLEN/8, x4, x1, x2)

inst_105:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x042 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2c0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x047 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7842; op2val:0x3ac0;
op3val:0x7847; valaddr_reg:x3; val_offset:315*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 315*FLEN/8, x4, x1, x2)

inst_106:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x041 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x02f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7841; op2val:0x3ab3;
op3val:0x782f; valaddr_reg:x3; val_offset:318*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 318*FLEN/8, x4, x1, x2)

inst_107:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x009 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x293 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x02e and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7809; op2val:0x3a93;
op3val:0x782e; valaddr_reg:x3; val_offset:321*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 321*FLEN/8, x4, x1, x2)

inst_108:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x059 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0f7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x04c and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7859; op2val:0x38f7;
op3val:0x784c; valaddr_reg:x3; val_offset:324*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 324*FLEN/8, x4, x1, x2)

inst_109:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x34c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x005 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7855; op2val:0x374c;
op3val:0x7805; valaddr_reg:x3; val_offset:327*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 327*FLEN/8, x4, x1, x2)

inst_110:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x062 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x18b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x028 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7862; op2val:0xc18b;
op3val:0x7828; valaddr_reg:x3; val_offset:330*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 330*FLEN/8, x4, x1, x2)

inst_111:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x048 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x782f; op2val:0xc1dd;
op3val:0x7848; valaddr_reg:x3; val_offset:333*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 333*FLEN/8, x4, x1, x2)

inst_112:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1a7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x056 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x785b; op2val:0xc1a7;
op3val:0x7856; valaddr_reg:x3; val_offset:336*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 336*FLEN/8, x4, x1, x2)

inst_113:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x024 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7824; op2val:0xc1e5;
op3val:0x783f; valaddr_reg:x3; val_offset:339*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 339*FLEN/8, x4, x1, x2)

inst_114:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x022 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1f6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x063 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7822; op2val:0xc1f6;
op3val:0x7863; valaddr_reg:x3; val_offset:342*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 342*FLEN/8, x4, x1, x2)

inst_115:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x059 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1a0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x05c and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7859; op2val:0xc1a0;
op3val:0x785c; valaddr_reg:x3; val_offset:345*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 345*FLEN/8, x4, x1, x2)

inst_116:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x026 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1be and fs3 == 0 and fe3 == 0x1e and fm3 == 0x02c and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7826; op2val:0xc1be;
op3val:0x782c; valaddr_reg:x3; val_offset:348*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 348*FLEN/8, x4, x1, x2)

inst_117:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x054 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x15a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x017 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7854; op2val:0xc15a;
op3val:0x7817; valaddr_reg:x3; val_offset:351*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 351*FLEN/8, x4, x1, x2)

inst_118:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x120 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x784b; op2val:0xc120;
op3val:0x7802; valaddr_reg:x3; val_offset:354*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 354*FLEN/8, x4, x1, x2)

inst_119:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03d and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0d9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x047 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x783d; op2val:0xc0d9;
op3val:0x7847; valaddr_reg:x3; val_offset:357*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 357*FLEN/8, x4, x1, x2)

inst_120:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x050 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x266 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x021 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x50; op2val:0xb666;
op3val:0x21; valaddr_reg:x3; val_offset:360*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 360*FLEN/8, x4, x1, x2)

inst_121:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x059 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x017 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x05f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x59; op2val:0xbc17;
op3val:0x5f; valaddr_reg:x3; val_offset:363*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 363*FLEN/8, x4, x1, x2)

inst_122:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x054 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b6 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x044 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x54; op2val:0xb9b6;
op3val:0x44; valaddr_reg:x3; val_offset:366*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 366*FLEN/8, x4, x1, x2)

inst_123:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x004 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x180 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x03c and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x4; op2val:0xc980;
op3val:0x3c; valaddr_reg:x3; val_offset:369*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 369*FLEN/8, x4, x1, x2)

inst_124:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x020 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x280 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x054 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x20; op2val:0xbe80;
op3val:0x54; valaddr_reg:x3; val_offset:372*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 372*FLEN/8, x4, x1, x2)

inst_125:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x11 and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x030 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0xf; op2val:0x4555;
op3val:0x30; valaddr_reg:x3; val_offset:375*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 375*FLEN/8, x4, x1, x2)

inst_126:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x031 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x082 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x046 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x31; op2val:0x4882;
op3val:0x46; valaddr_reg:x3; val_offset:378*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 378*FLEN/8, x4, x1, x2)

inst_127:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x020 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x20; op2val:0xb000;
op3val:0x2; valaddr_reg:x3; val_offset:381*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 381*FLEN/8, x4, x1, x2)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(80,16,FLEN)
NAN_BOXED(46694,16,FLEN)
NAN_BOXED(46694,16,FLEN)
NAN_BOXED(95,16,FLEN)
NAN_BOXED(46953,16,FLEN)
NAN_BOXED(46,16,FLEN)
NAN_BOXED(89,16,FLEN)
NAN_BOXED(89,16,FLEN)
NAN_BOXED(89,16,FLEN)
NAN_BOXED(84,16,FLEN)
NAN_BOXED(84,16,FLEN)
NAN_BOXED(68,16,FLEN)
NAN_BOXED(4,16,FLEN)
NAN_BOXED(51584,16,FLEN)
NAN_BOXED(4,16,FLEN)
NAN_BOXED(32,16,FLEN)
NAN_BOXED(48768,16,FLEN)
NAN_BOXED(48768,16,FLEN)
NAN_BOXED(7,16,FLEN)
NAN_BOXED(17956,16,FLEN)
NAN_BOXED(21,16,FLEN)
NAN_BOXED(15,16,FLEN)
NAN_BOXED(15,16,FLEN)
NAN_BOXED(15,16,FLEN)
NAN_BOXED(61,16,FLEN)
NAN_BOXED(17240,16,FLEN)
NAN_BOXED(32,16,FLEN)
NAN_BOXED(49,16,FLEN)
NAN_BOXED(49,16,FLEN)
NAN_BOXED(70,16,FLEN)
NAN_BOXED(14,16,FLEN)
NAN_BOXED(50523,16,FLEN)
NAN_BOXED(74,16,FLEN)
NAN_BOXED(32,16,FLEN)
NAN_BOXED(45056,16,FLEN)
NAN_BOXED(32,16,FLEN)
NAN_BOXED(94,16,FLEN)
NAN_BOXED(46450,16,FLEN)
NAN_BOXED(28,16,FLEN)
NAN_BOXED(53,16,FLEN)
NAN_BOXED(47780,16,FLEN)
NAN_BOXED(36,16,FLEN)
NAN_BOXED(24,16,FLEN)
NAN_BOXED(50378,16,FLEN)
NAN_BOXED(99,16,FLEN)
NAN_BOXED(50,16,FLEN)
NAN_BOXED(48189,16,FLEN)
NAN_BOXED(21,16,FLEN)
NAN_BOXED(98,16,FLEN)
NAN_BOXED(47626,16,FLEN)
NAN_BOXED(10,16,FLEN)
NAN_BOXED(18,16,FLEN)
NAN_BOXED(51655,16,FLEN)
NAN_BOXED(80,16,FLEN)
NAN_BOXED(80,16,FLEN)
NAN_BOXED(50131,16,FLEN)
NAN_BOXED(57,16,FLEN)
NAN_BOXED(17,16,FLEN)
NAN_BOXED(53191,16,FLEN)
NAN_BOXED(17,16,FLEN)
NAN_BOXED(15361,16,FLEN)
NAN_BOXED(240,16,FLEN)
NAN_BOXED(15361,16,FLEN)
NAN_BOXED(15387,16,FLEN)
NAN_BOXED(42581,16,FLEN)
NAN_BOXED(15388,16,FLEN)
NAN_BOXED(15382,16,FLEN)
NAN_BOXED(42087,16,FLEN)
NAN_BOXED(15382,16,FLEN)
NAN_BOXED(15398,16,FLEN)
NAN_BOXED(42996,16,FLEN)
NAN_BOXED(15401,16,FLEN)
NAN_BOXED(15386,16,FLEN)
NAN_BOXED(43669,16,FLEN)
NAN_BOXED(15430,16,FLEN)
NAN_BOXED(15447,16,FLEN)
NAN_BOXED(43429,16,FLEN)
NAN_BOXED(15441,16,FLEN)
NAN_BOXED(15387,16,FLEN)
NAN_BOXED(10463,16,FLEN)
NAN_BOXED(15384,16,FLEN)
NAN_BOXED(15449,16,FLEN)
NAN_BOXED(11741,16,FLEN)
NAN_BOXED(15386,16,FLEN)
NAN_BOXED(15410,16,FLEN)
NAN_BOXED(12919,16,FLEN)
NAN_BOXED(15399,16,FLEN)
NAN_BOXED(15363,16,FLEN)
NAN_BOXED(14142,16,FLEN)
NAN_BOXED(15407,16,FLEN)
NAN_BOXED(15414,16,FLEN)
NAN_BOXED(49071,16,FLEN)
NAN_BOXED(15382,16,FLEN)
NAN_BOXED(15379,16,FLEN)
NAN_BOXED(49150,16,FLEN)
NAN_BOXED(15394,16,FLEN)
NAN_BOXED(15369,16,FLEN)
NAN_BOXED(49166,16,FLEN)
NAN_BOXED(15403,16,FLEN)
NAN_BOXED(15399,16,FLEN)
NAN_BOXED(49155,16,FLEN)
NAN_BOXED(15438,16,FLEN)
NAN_BOXED(15436,16,FLEN)
NAN_BOXED(49026,16,FLEN)
NAN_BOXED(15361,16,FLEN)
NAN_BOXED(15437,16,FLEN)
NAN_BOXED(49119,16,FLEN)
NAN_BOXED(15447,16,FLEN)
NAN_BOXED(15451,16,FLEN)
NAN_BOXED(49084,16,FLEN)
NAN_BOXED(15404,16,FLEN)
NAN_BOXED(15369,16,FLEN)
NAN_BOXED(49226,16,FLEN)
NAN_BOXED(15400,16,FLEN)
NAN_BOXED(15406,16,FLEN)
NAN_BOXED(49249,16,FLEN)
NAN_BOXED(15400,16,FLEN)
NAN_BOXED(15422,16,FLEN)
NAN_BOXED(49377,16,FLEN)
NAN_BOXED(15450,16,FLEN)
NAN_BOXED(41,16,FLEN)
NAN_BOXED(47228,16,FLEN)
NAN_BOXED(24,16,FLEN)
NAN_BOXED(62,16,FLEN)
NAN_BOXED(47995,16,FLEN)
NAN_BOXED(61,16,FLEN)
NAN_BOXED(91,16,FLEN)
NAN_BOXED(45652,16,FLEN)
NAN_BOXED(23,16,FLEN)
NAN_BOXED(8,16,FLEN)
NAN_BOXED(49664,16,FLEN)
NAN_BOXED(33,16,FLEN)
NAN_BOXED(3,16,FLEN)
NAN_BOXED(52885,16,FLEN)
NAN_BOXED(96,16,FLEN)
NAN_BOXED(46,16,FLEN)
NAN_BOXED(46747,16,FLEN)
NAN_BOXED(52,16,FLEN)
NAN_BOXED(3,16,FLEN)
NAN_BOXED(49152,16,FLEN)
NAN_BOXED(71,16,FLEN)
NAN_BOXED(54,16,FLEN)
NAN_BOXED(15890,16,FLEN)
NAN_BOXED(47,16,FLEN)
NAN_BOXED(49,16,FLEN)
NAN_BOXED(17261,16,FLEN)
NAN_BOXED(75,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(23324,16,FLEN)
NAN_BOXED(58,16,FLEN)
NAN_BOXED(6,16,FLEN)
NAN_BOXED(52138,16,FLEN)
NAN_BOXED(91,16,FLEN)
NAN_BOXED(24,16,FLEN)
NAN_BOXED(49898,16,FLEN)
NAN_BOXED(80,16,FLEN)
NAN_BOXED(26,16,FLEN)
NAN_BOXED(47734,16,FLEN)
NAN_BOXED(16,16,FLEN)
NAN_BOXED(97,16,FLEN)
NAN_BOXED(46787,16,FLEN)
NAN_BOXED(32,16,FLEN)
NAN_BOXED(60,16,FLEN)
NAN_BOXED(48162,16,FLEN)
NAN_BOXED(45,16,FLEN)
NAN_BOXED(66,16,FLEN)
NAN_BOXED(48329,16,FLEN)
NAN_BOXED(46,16,FLEN)
NAN_BOXED(68,16,FLEN)
NAN_BOXED(48579,16,FLEN)
NAN_BOXED(33,16,FLEN)
NAN_BOXED(60,16,FLEN)
NAN_BOXED(49348,16,FLEN)
NAN_BOXED(14,16,FLEN)
NAN_BOXED(76,16,FLEN)
NAN_BOXED(50341,16,FLEN)
NAN_BOXED(96,16,FLEN)
NAN_BOXED(48,16,FLEN)
NAN_BOXED(51645,16,FLEN)
NAN_BOXED(38,16,FLEN)
NAN_BOXED(5,16,FLEN)
NAN_BOXED(23049,16,FLEN)
NAN_BOXED(56,16,FLEN)
NAN_BOXED(12,16,FLEN)
NAN_BOXED(21805,16,FLEN)
NAN_BOXED(27,16,FLEN)
NAN_BOXED(44,16,FLEN)
NAN_BOXED(19818,16,FLEN)
NAN_BOXED(66,16,FLEN)
NAN_BOXED(79,16,FLEN)
NAN_BOXED(18976,16,FLEN)
NAN_BOXED(47,16,FLEN)
NAN_BOXED(19,16,FLEN)
NAN_BOXED(21077,16,FLEN)
NAN_BOXED(44,16,FLEN)
NAN_BOXED(36,16,FLEN)
NAN_BOXED(20033,16,FLEN)
NAN_BOXED(90,16,FLEN)
NAN_BOXED(70,16,FLEN)
NAN_BOXED(19139,16,FLEN)
NAN_BOXED(12,16,FLEN)
NAN_BOXED(40,16,FLEN)
NAN_BOXED(19723,16,FLEN)
NAN_BOXED(88,16,FLEN)
NAN_BOXED(41,16,FLEN)
NAN_BOXED(19566,16,FLEN)
NAN_BOXED(40,16,FLEN)
NAN_BOXED(23,16,FLEN)
NAN_BOXED(19823,16,FLEN)
NAN_BOXED(11,16,FLEN)
NAN_BOXED(81,16,FLEN)
NAN_BOXED(51822,16,FLEN)
NAN_BOXED(20,16,FLEN)
NAN_BOXED(93,16,FLEN)
NAN_BOXED(51703,16,FLEN)
NAN_BOXED(89,16,FLEN)
NAN_BOXED(40,16,FLEN)
NAN_BOXED(52929,16,FLEN)
NAN_BOXED(62,16,FLEN)
NAN_BOXED(21,16,FLEN)
NAN_BOXED(53912,16,FLEN)
NAN_BOXED(93,16,FLEN)
NAN_BOXED(7,16,FLEN)
NAN_BOXED(55435,16,FLEN)
NAN_BOXED(11,16,FLEN)
NAN_BOXED(77,16,FLEN)
NAN_BOXED(51938,16,FLEN)
NAN_BOXED(69,16,FLEN)
NAN_BOXED(52,16,FLEN)
NAN_BOXED(52386,16,FLEN)
NAN_BOXED(5,16,FLEN)
NAN_BOXED(31,16,FLEN)
NAN_BOXED(53243,16,FLEN)
NAN_BOXED(95,16,FLEN)
NAN_BOXED(77,16,FLEN)
NAN_BOXED(51525,16,FLEN)
NAN_BOXED(45,16,FLEN)
NAN_BOXED(33,16,FLEN)
NAN_BOXED(52305,16,FLEN)
NAN_BOXED(59,16,FLEN)
NAN_BOXED(1108,16,FLEN)
NAN_BOXED(43551,16,FLEN)
NAN_BOXED(1078,16,FLEN)
NAN_BOXED(1043,16,FLEN)
NAN_BOXED(40420,16,FLEN)
NAN_BOXED(1032,16,FLEN)
NAN_BOXED(1106,16,FLEN)
NAN_BOXED(37736,16,FLEN)
NAN_BOXED(1029,16,FLEN)
NAN_BOXED(1088,16,FLEN)
NAN_BOXED(43038,16,FLEN)
NAN_BOXED(1067,16,FLEN)
NAN_BOXED(1051,16,FLEN)
NAN_BOXED(37835,16,FLEN)
NAN_BOXED(1041,16,FLEN)
NAN_BOXED(1118,16,FLEN)
NAN_BOXED(43185,16,FLEN)
NAN_BOXED(1097,16,FLEN)
NAN_BOXED(1041,16,FLEN)
NAN_BOXED(42030,16,FLEN)
NAN_BOXED(1105,16,FLEN)
NAN_BOXED(1077,16,FLEN)
NAN_BOXED(11974,16,FLEN)
NAN_BOXED(1038,16,FLEN)
NAN_BOXED(1046,16,FLEN)
NAN_BOXED(12830,16,FLEN)
NAN_BOXED(1080,16,FLEN)
NAN_BOXED(1072,16,FLEN)
NAN_BOXED(14167,16,FLEN)
NAN_BOXED(1044,16,FLEN)
NAN_BOXED(1032,16,FLEN)
NAN_BOXED(49171,16,FLEN)
NAN_BOXED(1078,16,FLEN)
NAN_BOXED(1062,16,FLEN)
NAN_BOXED(49098,16,FLEN)
NAN_BOXED(1043,16,FLEN)
NAN_BOXED(1083,16,FLEN)
NAN_BOXED(49119,16,FLEN)
NAN_BOXED(1104,16,FLEN)
NAN_BOXED(1046,16,FLEN)
NAN_BOXED(49167,16,FLEN)
NAN_BOXED(1091,16,FLEN)
NAN_BOXED(1083,16,FLEN)
NAN_BOXED(49115,16,FLEN)
NAN_BOXED(1087,16,FLEN)
NAN_BOXED(1113,16,FLEN)
NAN_BOXED(49104,16,FLEN)
NAN_BOXED(1118,16,FLEN)
NAN_BOXED(1065,16,FLEN)
NAN_BOXED(49173,16,FLEN)
NAN_BOXED(1086,16,FLEN)
NAN_BOXED(1060,16,FLEN)
NAN_BOXED(49197,16,FLEN)
NAN_BOXED(1062,16,FLEN)
NAN_BOXED(1085,16,FLEN)
NAN_BOXED(49239,16,FLEN)
NAN_BOXED(1076,16,FLEN)
NAN_BOXED(1043,16,FLEN)
NAN_BOXED(49392,16,FLEN)
NAN_BOXED(1039,16,FLEN)
NAN_BOXED(30769,16,FLEN)
NAN_BOXED(15130,16,FLEN)
NAN_BOXED(30789,16,FLEN)
NAN_BOXED(30743,16,FLEN)
NAN_BOXED(15150,16,FLEN)
NAN_BOXED(30801,16,FLEN)
NAN_BOXED(30784,16,FLEN)
NAN_BOXED(15147,16,FLEN)
NAN_BOXED(30764,16,FLEN)
NAN_BOXED(30744,16,FLEN)
NAN_BOXED(15272,16,FLEN)
NAN_BOXED(30732,16,FLEN)
NAN_BOXED(30783,16,FLEN)
NAN_BOXED(15143,16,FLEN)
NAN_BOXED(30755,16,FLEN)
NAN_BOXED(30786,16,FLEN)
NAN_BOXED(15040,16,FLEN)
NAN_BOXED(30791,16,FLEN)
NAN_BOXED(30785,16,FLEN)
NAN_BOXED(15027,16,FLEN)
NAN_BOXED(30767,16,FLEN)
NAN_BOXED(30729,16,FLEN)
NAN_BOXED(14995,16,FLEN)
NAN_BOXED(30766,16,FLEN)
NAN_BOXED(30809,16,FLEN)
NAN_BOXED(14583,16,FLEN)
NAN_BOXED(30796,16,FLEN)
NAN_BOXED(30805,16,FLEN)
NAN_BOXED(14156,16,FLEN)
NAN_BOXED(30725,16,FLEN)
NAN_BOXED(30818,16,FLEN)
NAN_BOXED(49547,16,FLEN)
NAN_BOXED(30760,16,FLEN)
NAN_BOXED(30767,16,FLEN)
NAN_BOXED(49629,16,FLEN)
NAN_BOXED(30792,16,FLEN)
NAN_BOXED(30811,16,FLEN)
NAN_BOXED(49575,16,FLEN)
NAN_BOXED(30806,16,FLEN)
NAN_BOXED(30756,16,FLEN)
NAN_BOXED(49637,16,FLEN)
NAN_BOXED(30783,16,FLEN)
NAN_BOXED(30754,16,FLEN)
NAN_BOXED(49654,16,FLEN)
NAN_BOXED(30819,16,FLEN)
NAN_BOXED(30809,16,FLEN)
NAN_BOXED(49568,16,FLEN)
NAN_BOXED(30812,16,FLEN)
NAN_BOXED(30758,16,FLEN)
NAN_BOXED(49598,16,FLEN)
NAN_BOXED(30764,16,FLEN)
NAN_BOXED(30804,16,FLEN)
NAN_BOXED(49498,16,FLEN)
NAN_BOXED(30743,16,FLEN)
NAN_BOXED(30795,16,FLEN)
NAN_BOXED(49440,16,FLEN)
NAN_BOXED(30722,16,FLEN)
NAN_BOXED(30781,16,FLEN)
NAN_BOXED(49369,16,FLEN)
NAN_BOXED(30791,16,FLEN)
NAN_BOXED(80,16,FLEN)
NAN_BOXED(46694,16,FLEN)
NAN_BOXED(33,16,FLEN)
NAN_BOXED(89,16,FLEN)
NAN_BOXED(48151,16,FLEN)
NAN_BOXED(95,16,FLEN)
NAN_BOXED(84,16,FLEN)
NAN_BOXED(47542,16,FLEN)
NAN_BOXED(68,16,FLEN)
NAN_BOXED(4,16,FLEN)
NAN_BOXED(51584,16,FLEN)
NAN_BOXED(60,16,FLEN)
NAN_BOXED(32,16,FLEN)
NAN_BOXED(48768,16,FLEN)
NAN_BOXED(84,16,FLEN)
NAN_BOXED(15,16,FLEN)
NAN_BOXED(17749,16,FLEN)
NAN_BOXED(48,16,FLEN)
NAN_BOXED(49,16,FLEN)
NAN_BOXED(18562,16,FLEN)
NAN_BOXED(70,16,FLEN)
NAN_BOXED(32,16,FLEN)
NAN_BOXED(45056,16,FLEN)
NAN_BOXED(2,16,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;



signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;

mtrap_sigptr:
    .fill 64*XLEN/32,4,0xdeadbeef

tsig_end_canary:
CANARY;
#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif


sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
