
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.11.0
// timestamp : Wed Jun 21 10:32:06 2023 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/riscv/update/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/riscv/update/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fsqrt.s.cgf \
 \
//                  -- xlen 64  \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fsqrt.s instruction of the RISC-V RV64_Zfinx,RV64_Zdinx extension for the fsqrt_b2 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV64I_Zfinx,RV64I_Zdinx")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*);def TEST_CASE_1=True;",fsqrt_b2)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_0:
// rs1 == rd, rs1==x31, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000  
/* opcode: fsqrt.s ; op1:x31; dest:x31; op1val:0x7f0; valaddr_reg:x3;
val_offset:0*FLEN/8; rmval:dyn; correctval:0; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fsqrt.s, x31, x31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)

inst_1:
// rs1 != rd, rs1==x29, rd==x30,fs1 == 0 and fe1 == 0x7f and fm1 == 0x000002 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000  
/* opcode: fsqrt.s ; op1:x29; dest:x30; op1val:0x3f800002; valaddr_reg:x3;
val_offset:1*FLEN/8; rmval:dyn; correctval:0; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fsqrt.s, x30, x29, dyn, 0, 0, x3, 1*FLEN/8, x4, x1, x2)

inst_2:
// rs1==x30, rd==x29,fs1 == 0 and fe1 == 0x7f and fm1 == 0x000004 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000  
/* opcode: fsqrt.s ; op1:x30; dest:x29; op1val:0x3f800004; valaddr_reg:x3;
val_offset:2*FLEN/8; rmval:dyn; correctval:0; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fsqrt.s, x29, x30, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2)

inst_3:
// rs1==x27, rd==x28,fs1 == 0 and fe1 == 0x7f and fm1 == 0x000008 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000  
/* opcode: fsqrt.s ; op1:x27; dest:x28; op1val:0x3f800008; valaddr_reg:x3;
val_offset:3*FLEN/8; rmval:dyn; correctval:0; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fsqrt.s, x28, x27, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2)

inst_4:
// rs1==x28, rd==x27,fs1 == 0 and fe1 == 0x7f and fm1 == 0x000010 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000  
/* opcode: fsqrt.s ; op1:x28; dest:x27; op1val:0x3f800010; valaddr_reg:x3;
val_offset:4*FLEN/8; rmval:dyn; correctval:0; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fsqrt.s, x27, x28, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2)

inst_5:
// rs1==x25, rd==x26,fs1 == 0 and fe1 == 0x7f and fm1 == 0x000020 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000  
/* opcode: fsqrt.s ; op1:x25; dest:x26; op1val:0x3f800020; valaddr_reg:x3;
val_offset:5*FLEN/8; rmval:dyn; correctval:0; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fsqrt.s, x26, x25, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2)

inst_6:
// rs1==x26, rd==x25,fs1 == 0 and fe1 == 0x7f and fm1 == 0x000040 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000  
/* opcode: fsqrt.s ; op1:x26; dest:x25; op1val:0x3f800040; valaddr_reg:x3;
val_offset:6*FLEN/8; rmval:dyn; correctval:0; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fsqrt.s, x25, x26, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2)

inst_7:
// rs1==x23, rd==x24,fs1 == 0 and fe1 == 0x7f and fm1 == 0x000080 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000  
/* opcode: fsqrt.s ; op1:x23; dest:x24; op1val:0x3f800080; valaddr_reg:x3;
val_offset:7*FLEN/8; rmval:dyn; correctval:0; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fsqrt.s, x24, x23, dyn, 0, 0, x3, 7*FLEN/8, x4, x1, x2)

inst_8:
// rs1==x24, rd==x23,fs1 == 0 and fe1 == 0x7f and fm1 == 0x000100 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000  
/* opcode: fsqrt.s ; op1:x24; dest:x23; op1val:0x3f800100; valaddr_reg:x3;
val_offset:8*FLEN/8; rmval:dyn; correctval:0; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fsqrt.s, x23, x24, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2)

inst_9:
// rs1==x21, rd==x22,fs1 == 0 and fe1 == 0x7f and fm1 == 0x000200 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000  
/* opcode: fsqrt.s ; op1:x21; dest:x22; op1val:0x3f800200; valaddr_reg:x3;
val_offset:9*FLEN/8; rmval:dyn; correctval:0; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fsqrt.s, x22, x21, dyn, 0, 0, x3, 9*FLEN/8, x4, x1, x2)

inst_10:
// rs1==x22, rd==x21,fs1 == 0 and fe1 == 0x7f and fm1 == 0x000400 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000  
/* opcode: fsqrt.s ; op1:x22; dest:x21; op1val:0x3f800400; valaddr_reg:x3;
val_offset:10*FLEN/8; rmval:dyn; correctval:0; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fsqrt.s, x21, x22, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2)

inst_11:
// rs1==x19, rd==x20,fs1 == 0 and fe1 == 0x7f and fm1 == 0x000800 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000  
/* opcode: fsqrt.s ; op1:x19; dest:x20; op1val:0x3f800800; valaddr_reg:x3;
val_offset:11*FLEN/8; rmval:dyn; correctval:0; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fsqrt.s, x20, x19, dyn, 0, 0, x3, 11*FLEN/8, x4, x1, x2)

inst_12:
// rs1==x20, rd==x19,fs1 == 0 and fe1 == 0x7f and fm1 == 0x001000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000  
/* opcode: fsqrt.s ; op1:x20; dest:x19; op1val:0x3f801000; valaddr_reg:x3;
val_offset:12*FLEN/8; rmval:dyn; correctval:0; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fsqrt.s, x19, x20, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2)

inst_13:
// rs1==x17, rd==x18,fs1 == 0 and fe1 == 0x7f and fm1 == 0x002002 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000  
/* opcode: fsqrt.s ; op1:x17; dest:x18; op1val:0x3f802002; valaddr_reg:x3;
val_offset:13*FLEN/8; rmval:dyn; correctval:0; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fsqrt.s, x18, x17, dyn, 0, 0, x3, 13*FLEN/8, x4, x1, x2)

inst_14:
// rs1==x18, rd==x17,fs1 == 0 and fe1 == 0x7f and fm1 == 0x004008 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000  
/* opcode: fsqrt.s ; op1:x18; dest:x17; op1val:0x3f804008; valaddr_reg:x3;
val_offset:14*FLEN/8; rmval:dyn; correctval:0; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fsqrt.s, x17, x18, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2)

inst_15:
// rs1==x15, rd==x16,fs1 == 0 and fe1 == 0x7f and fm1 == 0x008020 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000  
/* opcode: fsqrt.s ; op1:x15; dest:x16; op1val:0x3f808020; valaddr_reg:x3;
val_offset:15*FLEN/8; rmval:dyn; correctval:0; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fsqrt.s, x16, x15, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2)

inst_16:
// rs1==x16, rd==x15,fs1 == 0 and fe1 == 0x7f and fm1 == 0x010080 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000  
/* opcode: fsqrt.s ; op1:x16; dest:x15; op1val:0x3f810080; valaddr_reg:x3;
val_offset:16*FLEN/8; rmval:dyn; correctval:0; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fsqrt.s, x15, x16, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2)

inst_17:
// rs1==x13, rd==x14,fs1 == 0 and fe1 == 0x7f and fm1 == 0x020200 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000  
/* opcode: fsqrt.s ; op1:x13; dest:x14; op1val:0x3f820200; valaddr_reg:x3;
val_offset:17*FLEN/8; rmval:dyn; correctval:0; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fsqrt.s, x14, x13, dyn, 0, 0, x3, 17*FLEN/8, x4, x1, x2)

inst_18:
// rs1==x14, rd==x13,fs1 == 0 and fe1 == 0x7f and fm1 == 0x040800 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000  
/* opcode: fsqrt.s ; op1:x14; dest:x13; op1val:0x3f840800; valaddr_reg:x3;
val_offset:18*FLEN/8; rmval:dyn; correctval:0; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fsqrt.s, x13, x14, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2)

inst_19:
// rs1==x11, rd==x12,fs1 == 0 and fe1 == 0x7f and fm1 == 0x082000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000  
/* opcode: fsqrt.s ; op1:x11; dest:x12; op1val:0x3f882000; valaddr_reg:x3;
val_offset:19*FLEN/8; rmval:dyn; correctval:0; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fsqrt.s, x12, x11, dyn, 0, 0, x3, 19*FLEN/8, x4, x1, x2)

inst_20:
// rs1==x12, rd==x11,fs1 == 0 and fe1 == 0x7f and fm1 == 0x108000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000  
/* opcode: fsqrt.s ; op1:x12; dest:x11; op1val:0x3f908000; valaddr_reg:x3;
val_offset:20*FLEN/8; rmval:dyn; correctval:0; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fsqrt.s, x11, x12, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2)

inst_21:
// rs1==x9, rd==x10,fs1 == 0 and fe1 == 0x7f and fm1 == 0x220000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000  
/* opcode: fsqrt.s ; op1:x9; dest:x10; op1val:0x3fa20000; valaddr_reg:x3;
val_offset:21*FLEN/8; rmval:dyn; correctval:0; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fsqrt.s, x10, x9, dyn, 0, 0, x3, 21*FLEN/8, x4, x1, x2)

inst_22:
// rs1==x10, rd==x9,fs1 == 0 and fe1 == 0x7f and fm1 == 0x480000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000  
/* opcode: fsqrt.s ; op1:x10; dest:x9; op1val:0x3fc80000; valaddr_reg:x3;
val_offset:22*FLEN/8; rmval:dyn; correctval:0; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fsqrt.s, x9, x10, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2)

inst_23:
// rs1==x7, rd==x8,fs1 == 0 and fe1 == 0x80 and fm1 == 0x100000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000  
/* opcode: fsqrt.s ; op1:x7; dest:x8; op1val:0x40100000; valaddr_reg:x3;
val_offset:23*FLEN/8; rmval:dyn; correctval:0; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fsqrt.s, x8, x7, dyn, 0, 0, x3, 23*FLEN/8, x4, x1, x2)
RVTEST_VALBASEUPD(x9,test_dataset_1)

inst_24:
// rs1==x8, rd==x7,fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000  
/* opcode: fsqrt.s ; op1:x8; dest:x7; op1val:0x7f800000; valaddr_reg:x9;
val_offset:0*FLEN/8; rmval:dyn; correctval:0; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fsqrt.s, x7, x8, dyn, 0, 0, x9, 0*FLEN/8, x10, x1, x2)

inst_25:
// rs1==x5, rd==x6,
/* opcode: fsqrt.s ; op1:x5; dest:x6; op1val:0x0; valaddr_reg:x9;
val_offset:1*FLEN/8; rmval:dyn; correctval:0; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fsqrt.s, x6, x5, dyn, 0, 0, x9, 1*FLEN/8, x10, x1, x2)
RVTEST_SIGBASE(x7,signature_x7_0)

inst_26:
// rs1==x6, rd==x5,
/* opcode: fsqrt.s ; op1:x6; dest:x5; op1val:0x0; valaddr_reg:x9;
val_offset:2*FLEN/8; rmval:dyn; correctval:0; testreg:x8;
fcsr_val: 0 */
TEST_FPSR_OP(fsqrt.s, x5, x6, dyn, 0, 0, x9, 2*FLEN/8, x10, x7, x8)

inst_27:
// rs1==x3, rd==x4,
/* opcode: fsqrt.s ; op1:x3; dest:x4; op1val:0x0; valaddr_reg:x9;
val_offset:3*FLEN/8; rmval:dyn; correctval:0; testreg:x8;
fcsr_val: 0 */
TEST_FPSR_OP(fsqrt.s, x4, x3, dyn, 0, 0, x9, 3*FLEN/8, x10, x7, x8)

inst_28:
// rs1==x4, rd==x3,
/* opcode: fsqrt.s ; op1:x4; dest:x3; op1val:0x0; valaddr_reg:x9;
val_offset:4*FLEN/8; rmval:dyn; correctval:0; testreg:x8;
fcsr_val: 0 */
TEST_FPSR_OP(fsqrt.s, x3, x4, dyn, 0, 0, x9, 4*FLEN/8, x10, x7, x8)

inst_29:
// rs1==x1, rd==x2,
/* opcode: fsqrt.s ; op1:x1; dest:x2; op1val:0x0; valaddr_reg:x9;
val_offset:5*FLEN/8; rmval:dyn; correctval:0; testreg:x8;
fcsr_val: 0 */
TEST_FPSR_OP(fsqrt.s, x2, x1, dyn, 0, 0, x9, 5*FLEN/8, x10, x7, x8)

inst_30:
// rs1==x2, rd==x1,
/* opcode: fsqrt.s ; op1:x2; dest:x1; op1val:0x0; valaddr_reg:x9;
val_offset:6*FLEN/8; rmval:dyn; correctval:0; testreg:x8;
fcsr_val: 0 */
TEST_FPSR_OP(fsqrt.s, x1, x2, dyn, 0, 0, x9, 6*FLEN/8, x10, x7, x8)

inst_31:
// rs1==x0,
/* opcode: fsqrt.s ; op1:x0; dest:x31; op1val:0x0; valaddr_reg:x9;
val_offset:7*FLEN/8; rmval:dyn; correctval:0; testreg:x8;
fcsr_val: 0 */
TEST_FPSR_OP(fsqrt.s, x31, x0, dyn, 0, 0, x9, 7*FLEN/8, x10, x7, x8)

inst_32:
// rd==x0,
/* opcode: fsqrt.s ; op1:x31; dest:x0; op1val:0x0; valaddr_reg:x9;
val_offset:8*FLEN/8; rmval:dyn; correctval:0; testreg:x8;
fcsr_val: 0 */
TEST_FPSR_OP(fsqrt.s, x0, x31, dyn, 0, 0, x9, 8*FLEN/8, x10, x7, x8)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(2032,64,FLEN)
NAN_BOXED(1065353218,64,FLEN)
NAN_BOXED(1065353220,64,FLEN)
NAN_BOXED(1065353224,64,FLEN)
NAN_BOXED(1065353232,64,FLEN)
NAN_BOXED(1065353248,64,FLEN)
NAN_BOXED(1065353280,64,FLEN)
NAN_BOXED(1065353344,64,FLEN)
NAN_BOXED(1065353472,64,FLEN)
NAN_BOXED(1065353728,64,FLEN)
NAN_BOXED(1065354240,64,FLEN)
NAN_BOXED(1065355264,64,FLEN)
NAN_BOXED(1065357312,64,FLEN)
NAN_BOXED(1065361410,64,FLEN)
NAN_BOXED(1065369608,64,FLEN)
NAN_BOXED(1065386016,64,FLEN)
NAN_BOXED(1065418880,64,FLEN)
NAN_BOXED(1065484800,64,FLEN)
NAN_BOXED(1065617408,64,FLEN)
NAN_BOXED(1065885696,64,FLEN)
NAN_BOXED(1066434560,64,FLEN)
NAN_BOXED(1067581440,64,FLEN)
NAN_BOXED(1070071808,64,FLEN)
NAN_BOXED(1074790400,64,FLEN)
test_dataset_1:
NAN_BOXED(2139095040,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;



signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 26*((SIGALIGN)/4),4,0xdeadbeef


signature_x7_0:
    .fill 7*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;

mtrap_sigptr:
    .fill 64*XLEN/32,4,0xdeadbeef

tsig_end_canary:
CANARY;
#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif


sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
