
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.11.0
// timestamp : Tue Jan 30 08:43:50 2024 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fnmadd.cgf \
 \
//                  -- xlen 32  \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fnmadd.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV32FD_Zicsr,RV64F_Zicsr_Zfh,RV64FD_Zicsr extension for the fnmadd_b17 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV32IFD_Zicsr,RV64IF_Zicsr_Zfh,RV64IFD_Zicsr")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fnmadd_b17)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_0:
// rs1 == rs2 == rs3 == rd, rs1==f31, rs2==f31, rs3==f31, rd==f31,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x394 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f31; op2:f31; op3:f31; dest:f31; op1val:0x7ba5; op2val:0x7ba5;
op3val:0x7ba5; valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f31, f31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)

inst_1:
// rd == rs2 == rs3 != rs1, rs1==f29, rs2==f30, rs3==f30, rd==f30,fs1 == 0 and fe1 == 0x1b and fm1 == 0x16d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f29; op2:f30; op3:f30; dest:f30; op1val:0x6d6d; op2val:0x7aae;
op3val:0x7aae; valaddr_reg:x3; val_offset:3*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f30, f29, f30, f30, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2)

inst_2:
// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==f28, rs2==f28, rs3==f27, rd==f29,fs1 == 0 and fe1 == 0x1e and fm1 == 0x15a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0ed and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f28; op2:f28; op3:f27; dest:f29; op1val:0x795a; op2val:0x795a;
op3val:0xfbff; valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f29, f28, f28, f27, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2)

inst_3:
// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==f27, rs2==f29, rs3==f28, rd==f27,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0da and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0a5 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f27; op2:f29; op3:f28; dest:f27; op1val:0x78da; op2val:0x78a5;
op3val:0xfbff; valaddr_reg:x3; val_offset:9*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f27, f27, f29, f28, dyn, 0, 0, x3, 9*FLEN/8, x4, x1, x2)

inst_4:
// rs1 == rd == rs3 != rs2, rs1==f26, rs2==f27, rs3==f26, rd==f26,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x24b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f26; op2:f27; op3:f26; dest:f26; op1val:0x76e3; op2val:0x764b;
op3val:0x76e3; valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f26, f26, f27, f26, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2)

inst_5:
// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==f30, rs2==f26, rs3==f25, rd==f25,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x397 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f26; op3:f25; dest:f25; op1val:0x7bf4; op2val:0x7b97;
op3val:0xfbff; valaddr_reg:x3; val_offset:15*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f25, f30, f26, f25, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2)

inst_6:
// rs1 == rs2 == rs3 != rd, rs1==f24, rs2==f24, rs3==f24, rd==f28,fs1 == 0 and fe1 == 0x1d and fm1 == 0x31d and fs2 == 0 and fe2 == 0x1d and fm2 == 0x04a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f24; op2:f24; op3:f24; dest:f28; op1val:0x771d; op2val:0x771d;
op3val:0x771d; valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f28, f24, f24, f24, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2)

inst_7:
// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==f25, rs2==f23, rs3==f23, rd==f24,fs1 == 0 and fe1 == 0x19 and fm1 == 0x305 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x36f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f25; op2:f23; op3:f23; dest:f24; op1val:0x6705; op2val:0x776f;
op3val:0x776f; valaddr_reg:x3; val_offset:21*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f24, f25, f23, f23, dyn, 0, 0, x3, 21*FLEN/8, x4, x1, x2)

inst_8:
// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==f22, rs2==f25, rs3==f22, rd==f23,fs1 == 0 and fe1 == 0x1d and fm1 == 0x213 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x321 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f22; op2:f25; op3:f22; dest:f23; op1val:0x7613; op2val:0x7b21;
op3val:0x7613; valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f23, f22, f25, f22, dyn, 0, 0, x3, 24*FLEN/8, x4, x1, x2)

inst_9:
// rs1 == rs2 == rd != rs3, rs1==f21, rs2==f21, rs3==f29, rd==f21,fs1 == 0 and fe1 == 0x1e and fm1 == 0x07b and fs2 == 0 and fe2 == 0x1c and fm2 == 0x38d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f21; op2:f21; op3:f29; dest:f21; op1val:0x787b; op2val:0x787b;
op3val:0xfbff; valaddr_reg:x3; val_offset:27*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f21, f21, f21, f29, dyn, 0, 0, x3, 27*FLEN/8, x4, x1, x2)

inst_10:
// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==f23, rs2==f20, rs3==f21, rd==f22,fs1 == 0 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x05f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f23; op2:f20; op3:f21; dest:f22; op1val:0x7533; op2val:0x705f;
op3val:0xfbff; valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f22, f23, f20, f21, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)

inst_11:
// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==f20, rs2==f19, rs3==f18, rd==f19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x164 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f20; op2:f19; op3:f18; dest:f19; op1val:0x7bfc; op2val:0x7964;
op3val:0xfbff; valaddr_reg:x3; val_offset:33*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f19, f20, f19, f18, dyn, 0, 0, x3, 33*FLEN/8, x4, x1, x2)

inst_12:
// rs1==f18, rs2==f22, rs3==f19, rd==f20,fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x25e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f18; op2:f22; op3:f19; dest:f20; op1val:0x7b25; op2val:0x7a5e;
op3val:0xfbff; valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f20, f18, f22, f19, dyn, 0, 0, x3, 36*FLEN/8, x4, x1, x2)

inst_13:
// rs1==f19, rs2==f17, rs3==f20, rd==f18,fs1 == 0 and fe1 == 0x1e and fm1 == 0x33f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x219 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f19; op2:f17; op3:f20; dest:f18; op1val:0x7b3f; op2val:0x7a19;
op3val:0xfbff; valaddr_reg:x3; val_offset:39*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f18, f19, f17, f20, dyn, 0, 0, x3, 39*FLEN/8, x4, x1, x2)

inst_14:
// rs1==f16, rs2==f18, rs3==f15, rd==f17,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3d8 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f16; op2:f18; op3:f15; dest:f17; op1val:0x75a8; op2val:0x7bd8;
op3val:0xfbff; valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f17, f16, f18, f15, dyn, 0, 0, x3, 42*FLEN/8, x4, x1, x2)

inst_15:
// rs1==f17, rs2==f15, rs3==f14, rd==f16,fs1 == 0 and fe1 == 0x1c and fm1 == 0x127 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x207 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f17; op2:f15; op3:f14; dest:f16; op1val:0x7127; op2val:0x7a07;
op3val:0xfbff; valaddr_reg:x3; val_offset:45*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f16, f17, f15, f14, dyn, 0, 0, x3, 45*FLEN/8, x4, x1, x2)

inst_16:
// rs1==f14, rs2==f16, rs3==f17, rd==f15,fs1 == 0 and fe1 == 0x1d and fm1 == 0x360 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x03d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f14; op2:f16; op3:f17; dest:f15; op1val:0x7760; op2val:0x783d;
op3val:0xfbff; valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f15, f14, f16, f17, dyn, 0, 0, x3, 48*FLEN/8, x4, x1, x2)

inst_17:
// rs1==f15, rs2==f13, rs3==f16, rd==f14,fs1 == 0 and fe1 == 0x1e and fm1 == 0x365 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f15; op2:f13; op3:f16; dest:f14; op1val:0x7b65; op2val:0x7801;
op3val:0xfbff; valaddr_reg:x3; val_offset:51*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f14, f15, f13, f16, dyn, 0, 0, x3, 51*FLEN/8, x4, x1, x2)

inst_18:
// rs1==f12, rs2==f14, rs3==f11, rd==f13,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x30f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f12; op2:f14; op3:f11; dest:f13; op1val:0x75a8; op2val:0x7b0f;
op3val:0xfbff; valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f13, f12, f14, f11, dyn, 0, 0, x3, 54*FLEN/8, x4, x1, x2)

inst_19:
// rs1==f13, rs2==f11, rs3==f10, rd==f12,fs1 == 0 and fe1 == 0x1d and fm1 == 0x35f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x08a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f13; op2:f11; op3:f10; dest:f12; op1val:0x775f; op2val:0x788a;
op3val:0xfbff; valaddr_reg:x3; val_offset:57*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f12, f13, f11, f10, dyn, 0, 0, x3, 57*FLEN/8, x4, x1, x2)

inst_20:
// rs1==f10, rs2==f12, rs3==f13, rd==f11,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c9 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3c8 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f10; op2:f12; op3:f13; dest:f11; op1val:0x79c9; op2val:0x77c8;
op3val:0xfbff; valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f11, f10, f12, f13, dyn, 0, 0, x3, 60*FLEN/8, x4, x1, x2)

inst_21:
// rs1==f11, rs2==f9, rs3==f12, rd==f10,fs1 == 0 and fe1 == 0x1d and fm1 == 0x131 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x198 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f11; op2:f9; op3:f12; dest:f10; op1val:0x7531; op2val:0x7998;
op3val:0xfbff; valaddr_reg:x3; val_offset:63*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f10, f11, f9, f12, dyn, 0, 0, x3, 63*FLEN/8, x4, x1, x2)

inst_22:
// rs1==f8, rs2==f10, rs3==f7, rd==f9,fs1 == 0 and fe1 == 0x1e and fm1 == 0x342 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x049 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f8; op2:f10; op3:f7; dest:f9; op1val:0x7b42; op2val:0x7449;
op3val:0xfbff; valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f9, f8, f10, f7, dyn, 0, 0, x3, 66*FLEN/8, x4, x1, x2)

inst_23:
// rs1==f9, rs2==f7, rs3==f6, rd==f8,fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a7 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f9; op2:f7; op3:f6; dest:f8; op1val:0x74f3; op2val:0x7ba7;
op3val:0xfbff; valaddr_reg:x3; val_offset:69*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f8, f9, f7, f6, dyn, 0, 0, x3, 69*FLEN/8, x4, x1, x2)

inst_24:
// rs1==f6, rs2==f8, rs3==f9, rd==f7,fs1 == 0 and fe1 == 0x1e and fm1 == 0x008 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x023 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f6; op2:f8; op3:f9; dest:f7; op1val:0x7808; op2val:0x7823;
op3val:0xfbff; valaddr_reg:x3; val_offset:72*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f7, f6, f8, f9, dyn, 0, 0, x3, 72*FLEN/8, x4, x1, x2)

inst_25:
// rs1==f7, rs2==f5, rs3==f8, rd==f6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b3 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0fc and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f7; op2:f5; op3:f8; dest:f6; op1val:0x78b3; op2val:0x74fc;
op3val:0xfbff; valaddr_reg:x3; val_offset:75*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f6, f7, f5, f8, dyn, 0, 0, x3, 75*FLEN/8, x4, x1, x2)

inst_26:
// rs1==f4, rs2==f6, rs3==f3, rd==f5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x017 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x378 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f4; op2:f6; op3:f3; dest:f5; op1val:0x7817; op2val:0x7b78;
op3val:0xfbff; valaddr_reg:x3; val_offset:78*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f5, f4, f6, f3, dyn, 0, 0, x3, 78*FLEN/8, x4, x1, x2)

inst_27:
// rs1==f5, rs2==f3, rs3==f2, rd==f4,fs1 == 0 and fe1 == 0x1b and fm1 == 0x0d2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x28f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f5; op2:f3; op3:f2; dest:f4; op1val:0x6cd2; op2val:0x7a8f;
op3val:0xfbff; valaddr_reg:x3; val_offset:81*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f4, f5, f3, f2, dyn, 0, 0, x3, 81*FLEN/8, x4, x1, x2)

inst_28:
// rs1==f2, rs2==f4, rs3==f5, rd==f3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x341 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x21f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f2; op2:f4; op3:f5; dest:f3; op1val:0x7b41; op2val:0x721f;
op3val:0xfbff; valaddr_reg:x3; val_offset:84*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f3, f2, f4, f5, dyn, 0, 0, x3, 84*FLEN/8, x4, x1, x2)

inst_29:
// rs1==f3, rs2==f1, rs3==f4, rd==f2,fs1 == 0 and fe1 == 0x1a and fm1 == 0x384 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x138 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f3; op2:f1; op3:f4; dest:f2; op1val:0x6b84; op2val:0x7938;
op3val:0xfbff; valaddr_reg:x3; val_offset:87*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f2, f3, f1, f4, dyn, 0, 0, x3, 87*FLEN/8, x4, x1, x2)

inst_30:
// rs1==f1,fs1 == 0 and fe1 == 0x1c and fm1 == 0x33f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x300 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f1; op2:f30; op3:f29; dest:f31; op1val:0x733f; op2val:0x7b00;
op3val:0xfbff; valaddr_reg:x3; val_offset:90*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f1, f30, f29, dyn, 0, 0, x3, 90*FLEN/8, x4, x1, x2)

inst_31:
// rs1==f0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x02d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2d4 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f0; op2:f30; op3:f29; dest:f31; op1val:0x782d; op2val:0x7ad4;
op3val:0xfbff; valaddr_reg:x3; val_offset:93*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f0, f30, f29, dyn, 0, 0, x3, 93*FLEN/8, x4, x1, x2)

inst_32:
// rs2==f2,fs1 == 0 and fe1 == 0x1c and fm1 == 0x2bb and fs2 == 0 and fe2 == 0x1e and fm2 == 0x30a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f2; op3:f29; dest:f31; op1val:0x72bb; op2val:0x7b0a;
op3val:0xfbff; valaddr_reg:x3; val_offset:96*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f2, f29, dyn, 0, 0, x3, 96*FLEN/8, x4, x1, x2)

inst_33:
// rs2==f0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bb and fs2 == 0 and fe2 == 0x1a and fm2 == 0x013 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f0; op3:f29; dest:f31; op1val:0x79bb; op2val:0x6813;
op3val:0xfbff; valaddr_reg:x3; val_offset:99*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f0, f29, dyn, 0, 0, x3, 99*FLEN/8, x4, x1, x2)

inst_34:
// rs3==f1,fs1 == 0 and fe1 == 0x1c and fm1 == 0x17f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x161 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f1; dest:f31; op1val:0x717f; op2val:0x7961;
op3val:0xfbff; valaddr_reg:x3; val_offset:102*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f1, dyn, 0, 0, x3, 102*FLEN/8, x4, x1, x2)

inst_35:
// rs3==f0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x27c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f0; dest:f31; op1val:0x7ba1; op2val:0x667c;
op3val:0xfbff; valaddr_reg:x3; val_offset:105*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f0, dyn, 0, 0, x3, 105*FLEN/8, x4, x1, x2)

inst_36:
// rd==f1,fs1 == 0 and fe1 == 0x19 and fm1 == 0x169 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x016 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f31; op2:f30; op3:f29; dest:f1; op1val:0x6569; op2val:0x7416;
op3val:0xfbff; valaddr_reg:x3; val_offset:108*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f1, f31, f30, f29, dyn, 0, 0, x3, 108*FLEN/8, x4, x1, x2)

inst_37:
// rd==f0,fs1 == 0 and fe1 == 0x1c and fm1 == 0x106 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1e0 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f31; op2:f30; op3:f29; dest:f0; op1val:0x7106; op2val:0x71e0;
op3val:0xfbff; valaddr_reg:x3; val_offset:111*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f0, f31, f30, f29, dyn, 0, 0, x3, 111*FLEN/8, x4, x1, x2)

inst_38:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22a and fs2 == 0 and fe2 == 0x1a and fm2 == 0x185 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x762a; op2val:0x6985;
op3val:0xfbff; valaddr_reg:x3; val_offset:114*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 114*FLEN/8, x4, x1, x2)

inst_39:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0d7 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x0a3 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x70d7; op2val:0x68a3;
op3val:0xfbff; valaddr_reg:x3; val_offset:117*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 117*FLEN/8, x4, x1, x2)

inst_40:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0eb and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1ef and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78eb; op2val:0x79ef;
op3val:0xfbff; valaddr_reg:x3; val_offset:120*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 120*FLEN/8, x4, x1, x2)

inst_41:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x164 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x3e2 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7564; op2val:0x67e2;
op3val:0xfbff; valaddr_reg:x3; val_offset:123*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 123*FLEN/8, x4, x1, x2)

inst_42:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1ea and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a1f; op2val:0x79ea;
op3val:0xfbff; valaddr_reg:x3; val_offset:126*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 126*FLEN/8, x4, x1, x2)

inst_43:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e5 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a0a; op2val:0x7ae5;
op3val:0xfbff; valaddr_reg:x3; val_offset:129*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 129*FLEN/8, x4, x1, x2)

inst_44:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x38f and fs2 == 0 and fe2 == 0x1c and fm2 == 0x336 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x778f; op2val:0x7336;
op3val:0xfbff; valaddr_reg:x3; val_offset:132*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 132*FLEN/8, x4, x1, x2)

inst_45:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10e and fs2 == 0 and fe2 == 0x1b and fm2 == 0x287 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x750e; op2val:0x6e87;
op3val:0xfbff; valaddr_reg:x3; val_offset:135*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 135*FLEN/8, x4, x1, x2)

inst_46:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2fe and fs2 == 0 and fe2 == 0x1c and fm2 == 0x014 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7afe; op2val:0x7014;
op3val:0xfbff; valaddr_reg:x3; val_offset:138*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 138*FLEN/8, x4, x1, x2)

inst_47:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x248 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x01d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7648; op2val:0x781d;
op3val:0xfbff; valaddr_reg:x3; val_offset:141*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 141*FLEN/8, x4, x1, x2)

inst_48:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ac and fs2 == 0 and fe2 == 0x1d and fm2 == 0x024 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bac; op2val:0x7424;
op3val:0xfbff; valaddr_reg:x3; val_offset:144*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 144*FLEN/8, x4, x1, x2)

inst_49:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2b6 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x09d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x76b6; op2val:0x649d;
op3val:0xfbff; valaddr_reg:x3; val_offset:147*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 147*FLEN/8, x4, x1, x2)

inst_50:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x07e and fs2 == 0 and fe2 == 0x1a and fm2 == 0x343 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x707e; op2val:0x6b43;
op3val:0xfbff; valaddr_reg:x3; val_offset:150*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 150*FLEN/8, x4, x1, x2)

inst_51:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x127 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x221 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7127; op2val:0x6e21;
op3val:0xfbff; valaddr_reg:x3; val_offset:153*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 153*FLEN/8, x4, x1, x2)

inst_52:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x010 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3dd and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7810; op2val:0x7bdd;
op3val:0xfbff; valaddr_reg:x3; val_offset:156*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 156*FLEN/8, x4, x1, x2)

inst_53:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f3 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x36f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bf3; op2val:0x736f;
op3val:0xfbff; valaddr_reg:x3; val_offset:159*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 159*FLEN/8, x4, x1, x2)

inst_54:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x002 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0ba and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7402; op2val:0x78ba;
op3val:0xfbff; valaddr_reg:x3; val_offset:162*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 162*FLEN/8, x4, x1, x2)

inst_55:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x266 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1ac and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a66; op2val:0x79ac;
op3val:0xfbff; valaddr_reg:x3; val_offset:165*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 165*FLEN/8, x4, x1, x2)

inst_56:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2c3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x035 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x76c3; op2val:0x7835;
op3val:0xfbff; valaddr_reg:x3; val_offset:168*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 168*FLEN/8, x4, x1, x2)

inst_57:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x08a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x289 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x688a; op2val:0x7689;
op3val:0xfbff; valaddr_reg:x3; val_offset:171*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 171*FLEN/8, x4, x1, x2)

inst_58:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c9 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3b4 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79c9; op2val:0x73b4;
op3val:0xfbff; valaddr_reg:x3; val_offset:174*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 174*FLEN/8, x4, x1, x2)

inst_59:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1d0 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x367 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71d0; op2val:0x7367;
op3val:0xfbff; valaddr_reg:x3; val_offset:177*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 177*FLEN/8, x4, x1, x2)

inst_60:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x029 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x36d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7829; op2val:0x776d;
op3val:0xfbff; valaddr_reg:x3; val_offset:180*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 180*FLEN/8, x4, x1, x2)

inst_61:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x121 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2cb and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7921; op2val:0x72cb;
op3val:0xfbff; valaddr_reg:x3; val_offset:183*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 183*FLEN/8, x4, x1, x2)

inst_62:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1d4 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bb3; op2val:0x79d4;
op3val:0xfbff; valaddr_reg:x3; val_offset:186*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 186*FLEN/8, x4, x1, x2)

inst_63:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x017 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0a5 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7817; op2val:0x78a5;
op3val:0xfbff; valaddr_reg:x3; val_offset:189*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 189*FLEN/8, x4, x1, x2)

inst_64:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2af and fs2 == 0 and fe2 == 0x1e and fm2 == 0x032 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x76af; op2val:0x7832;
op3val:0xfbff; valaddr_reg:x3; val_offset:192*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 192*FLEN/8, x4, x1, x2)

inst_65:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x26b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6dff; op2val:0x7a6b;
op3val:0xfbff; valaddr_reg:x3; val_offset:195*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 195*FLEN/8, x4, x1, x2)

inst_66:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x026 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x35e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7826; op2val:0x7b5e;
op3val:0xfbff; valaddr_reg:x3; val_offset:198*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 198*FLEN/8, x4, x1, x2)

inst_67:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3dd and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x74a1; op2val:0x7bdd;
op3val:0xfbff; valaddr_reg:x3; val_offset:201*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 201*FLEN/8, x4, x1, x2)

inst_68:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x0e0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x17a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x64e0; op2val:0x797a;
op3val:0xfbff; valaddr_reg:x3; val_offset:204*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 204*FLEN/8, x4, x1, x2)

inst_69:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0e4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b8 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x74e4; op2val:0x7ab8;
op3val:0xfbff; valaddr_reg:x3; val_offset:207*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 207*FLEN/8, x4, x1, x2)

inst_70:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x005 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x338 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6405; op2val:0x7738;
op3val:0xfbff; valaddr_reg:x3; val_offset:210*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 210*FLEN/8, x4, x1, x2)

inst_71:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c5 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2a9 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x77c5; op2val:0x72a9;
op3val:0xfbff; valaddr_reg:x3; val_offset:213*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 213*FLEN/8, x4, x1, x2)

inst_72:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0b8 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x08c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6cb8; op2val:0x748c;
op3val:0xfbff; valaddr_reg:x3; val_offset:216*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 216*FLEN/8, x4, x1, x2)

inst_73:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37a and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0e5 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b7a; op2val:0x6ce5;
op3val:0xfbff; valaddr_reg:x3; val_offset:219*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 219*FLEN/8, x4, x1, x2)

inst_74:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x227 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x091 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7227; op2val:0x7891;
op3val:0xfbff; valaddr_reg:x3; val_offset:222*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 222*FLEN/8, x4, x1, x2)

inst_75:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x368 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x206 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7768; op2val:0x7a06;
op3val:0xfbff; valaddr_reg:x3; val_offset:225*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 225*FLEN/8, x4, x1, x2)

inst_76:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3c9 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3ca and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6fc9; op2val:0x6fca;
op3val:0xfbff; valaddr_reg:x3; val_offset:228*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 228*FLEN/8, x4, x1, x2)

inst_77:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2cc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x120 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7acc; op2val:0x7920;
op3val:0xfbff; valaddr_reg:x3; val_offset:231*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 231*FLEN/8, x4, x1, x2)

inst_78:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x189 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x24f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7989; op2val:0x664f;
op3val:0xfbff; valaddr_reg:x3; val_offset:234*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 234*FLEN/8, x4, x1, x2)

inst_79:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x236 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1c9 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a36; op2val:0x79c9;
op3val:0xfbff; valaddr_reg:x3; val_offset:237*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 237*FLEN/8, x4, x1, x2)

inst_80:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b7 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x34f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75b7; op2val:0x774f;
op3val:0xfbff; valaddr_reg:x3; val_offset:240*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 240*FLEN/8, x4, x1, x2)

inst_81:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x04d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x035 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x744d; op2val:0x7835;
op3val:0xfbff; valaddr_reg:x3; val_offset:243*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 243*FLEN/8, x4, x1, x2)

inst_82:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x26e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ba2; op2val:0x7a6e;
op3val:0xfbff; valaddr_reg:x3; val_offset:246*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 246*FLEN/8, x4, x1, x2)

inst_83:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2af and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0be and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7aaf; op2val:0x74be;
op3val:0xfbff; valaddr_reg:x3; val_offset:249*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 249*FLEN/8, x4, x1, x2)

inst_84:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d1 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x026 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x77d1; op2val:0x7426;
op3val:0xfbff; valaddr_reg:x3; val_offset:252*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 252*FLEN/8, x4, x1, x2)

inst_85:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x16e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x358 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x796e; op2val:0x7b58;
op3val:0xfbff; valaddr_reg:x3; val_offset:255*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 255*FLEN/8, x4, x1, x2)

inst_86:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28a and fs2 == 0 and fe2 == 0x1b and fm2 == 0x223 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a8a; op2val:0x6e23;
op3val:0xfbff; valaddr_reg:x3; val_offset:258*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 258*FLEN/8, x4, x1, x2)

inst_87:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fa and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0af and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bfa; op2val:0x70af;
op3val:0xfbff; valaddr_reg:x3; val_offset:261*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 261*FLEN/8, x4, x1, x2)

inst_88:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x046 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x182 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6c46; op2val:0x6d82;
op3val:0xfbff; valaddr_reg:x3; val_offset:264*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 264*FLEN/8, x4, x1, x2)

inst_89:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x12e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7be7; op2val:0x792e;
op3val:0xfbff; valaddr_reg:x3; val_offset:267*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 267*FLEN/8, x4, x1, x2)

inst_90:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0bd and fs2 == 0 and fe2 == 0x1c and fm2 == 0x369 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x74bd; op2val:0x7369;
op3val:0xfbff; valaddr_reg:x3; val_offset:270*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 270*FLEN/8, x4, x1, x2)

inst_91:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x172 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x304 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7972; op2val:0x7704;
op3val:0xfbff; valaddr_reg:x3; val_offset:273*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 273*FLEN/8, x4, x1, x2)

inst_92:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x32b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x053 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6f2b; op2val:0x7853;
op3val:0xfbff; valaddr_reg:x3; val_offset:276*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 276*FLEN/8, x4, x1, x2)

inst_93:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20b and fs2 == 0 and fe2 == 0x1b and fm2 == 0x226 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a0b; op2val:0x6e26;
op3val:0xfbff; valaddr_reg:x3; val_offset:279*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 279*FLEN/8, x4, x1, x2)

inst_94:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b8 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x01d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79b8; op2val:0x741d;
op3val:0xfbff; valaddr_reg:x3; val_offset:282*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 282*FLEN/8, x4, x1, x2)

inst_95:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x35f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x19f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x775f; op2val:0x799f;
op3val:0xfbff; valaddr_reg:x3; val_offset:285*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 285*FLEN/8, x4, x1, x2)

inst_96:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x242 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bf5; op2val:0x7a42;
op3val:0xfbff; valaddr_reg:x3; val_offset:288*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 288*FLEN/8, x4, x1, x2)

inst_97:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0a1 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x30e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x70a1; op2val:0x770e;
op3val:0xfbff; valaddr_reg:x3; val_offset:291*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 291*FLEN/8, x4, x1, x2)

inst_98:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x30d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78c2; op2val:0x7b0d;
op3val:0xfbff; valaddr_reg:x3; val_offset:294*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 294*FLEN/8, x4, x1, x2)

inst_99:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x014 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3b7 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7814; op2val:0x77b7;
op3val:0xfbff; valaddr_reg:x3; val_offset:297*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 297*FLEN/8, x4, x1, x2)

inst_100:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ae and fs2 == 0 and fe2 == 0x1e and fm2 == 0x37d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79ae; op2val:0x7b7d;
op3val:0xfbff; valaddr_reg:x3; val_offset:300*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 300*FLEN/8, x4, x1, x2)

inst_101:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x38e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3b1 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x778e; op2val:0x7bb1;
op3val:0xfbff; valaddr_reg:x3; val_offset:303*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 303*FLEN/8, x4, x1, x2)

inst_102:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x143 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79f6; op2val:0x7943;
op3val:0xfbff; valaddr_reg:x3; val_offset:306*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 306*FLEN/8, x4, x1, x2)

inst_103:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d0 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x332 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ad0; op2val:0x7332;
op3val:0xfbff; valaddr_reg:x3; val_offset:309*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 309*FLEN/8, x4, x1, x2)

inst_104:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x270 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7670; op2val:0x7955;
op3val:0xfbff; valaddr_reg:x3; val_offset:312*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 312*FLEN/8, x4, x1, x2)

inst_105:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x1f0 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7913; op2val:0x61f0;
op3val:0xfbff; valaddr_reg:x3; val_offset:315*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 315*FLEN/8, x4, x1, x2)

inst_106:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x30f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79b0; op2val:0x7b0f;
op3val:0xfbff; valaddr_reg:x3; val_offset:318*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 318*FLEN/8, x4, x1, x2)

inst_107:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x286 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x062 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a86; op2val:0x6462;
op3val:0xfbff; valaddr_reg:x3; val_offset:321*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 321*FLEN/8, x4, x1, x2)

inst_108:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d9 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79d5; op2val:0x78d9;
op3val:0xfbff; valaddr_reg:x3; val_offset:324*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 324*FLEN/8, x4, x1, x2)

inst_109:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x312 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x26d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b12; op2val:0x6e6d;
op3val:0xfbff; valaddr_reg:x3; val_offset:327*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 327*FLEN/8, x4, x1, x2)

inst_110:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x222 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x261 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a22; op2val:0x7261;
op3val:0xfbff; valaddr_reg:x3; val_offset:330*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 330*FLEN/8, x4, x1, x2)

inst_111:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b0 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x21f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78b0; op2val:0x721f;
op3val:0xfbff; valaddr_reg:x3; val_offset:333*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 333*FLEN/8, x4, x1, x2)

inst_112:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x068 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0e5 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7068; op2val:0x78e5;
op3val:0xfbff; valaddr_reg:x3; val_offset:336*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 336*FLEN/8, x4, x1, x2)

inst_113:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x00e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x086 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x740e; op2val:0x7886;
op3val:0xfbff; valaddr_reg:x3; val_offset:339*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 339*FLEN/8, x4, x1, x2)

inst_114:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x28e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3bb and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x728e; op2val:0x7bbb;
op3val:0xfbff; valaddr_reg:x3; val_offset:342*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 342*FLEN/8, x4, x1, x2)

inst_115:
// fs1 == 0 and fe1 == 0x16 and fm1 == 0x237 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3c3 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5a37; op2val:0x77c3;
op3val:0xfbff; valaddr_reg:x3; val_offset:345*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 345*FLEN/8, x4, x1, x2)

inst_116:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x143 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x208 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7943; op2val:0x7a08;
op3val:0xfbff; valaddr_reg:x3; val_offset:348*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 348*FLEN/8, x4, x1, x2)

inst_117:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x165 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x15b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7965; op2val:0x755b;
op3val:0xfbff; valaddr_reg:x3; val_offset:351*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 351*FLEN/8, x4, x1, x2)

inst_118:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x005 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x30b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7805; op2val:0x670b;
op3val:0xfbff; valaddr_reg:x3; val_offset:354*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 354*FLEN/8, x4, x1, x2)

inst_119:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x207 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x18e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a07; op2val:0x718e;
op3val:0xfbff; valaddr_reg:x3; val_offset:357*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 357*FLEN/8, x4, x1, x2)

inst_120:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x245 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x277 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a45; op2val:0x7677;
op3val:0xfbff; valaddr_reg:x3; val_offset:360*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 360*FLEN/8, x4, x1, x2)

inst_121:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x24b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e8 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a4b; op2val:0x7ae8;
op3val:0xfbff; valaddr_reg:x3; val_offset:363*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 363*FLEN/8, x4, x1, x2)

inst_122:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x133 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x21a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7133; op2val:0x761a;
op3val:0xfbff; valaddr_reg:x3; val_offset:366*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 366*FLEN/8, x4, x1, x2)

inst_123:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b6 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x152 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x74b6; op2val:0x6152;
op3val:0xfbff; valaddr_reg:x3; val_offset:369*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 369*FLEN/8, x4, x1, x2)

inst_124:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3bb and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1dc and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bbb; op2val:0x75dc;
op3val:0xfbff; valaddr_reg:x3; val_offset:372*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 372*FLEN/8, x4, x1, x2)

inst_125:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x21d and fs2 == 0 and fe2 == 0x1d and fm2 == 0x314 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x761d; op2val:0x7714;
op3val:0xfbff; valaddr_reg:x3; val_offset:375*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 375*FLEN/8, x4, x1, x2)

inst_126:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ee and fs2 == 0 and fe2 == 0x1e and fm2 == 0x130 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x74ee; op2val:0x7930;
op3val:0xfbff; valaddr_reg:x3; val_offset:378*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 378*FLEN/8, x4, x1, x2)

inst_127:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x350 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x784e; op2val:0x7b50;
op3val:0xfbff; valaddr_reg:x3; val_offset:381*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 381*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_2)

inst_128:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x297 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0dd and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a97; op2val:0x74dd;
op3val:0xfbff; valaddr_reg:x3; val_offset:384*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 384*FLEN/8, x4, x1, x2)

inst_129:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x139 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a5d; op2val:0x7939;
op3val:0xfbff; valaddr_reg:x3; val_offset:387*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 387*FLEN/8, x4, x1, x2)

inst_130:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b8 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x1f2 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ab8; op2val:0x6df2;
op3val:0xfbff; valaddr_reg:x3; val_offset:390*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 390*FLEN/8, x4, x1, x2)

inst_131:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x241 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x03d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7641; op2val:0x783d;
op3val:0xfbff; valaddr_reg:x3; val_offset:393*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 393*FLEN/8, x4, x1, x2)

inst_132:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x261 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x107 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a61; op2val:0x7907;
op3val:0xfbff; valaddr_reg:x3; val_offset:396*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 396*FLEN/8, x4, x1, x2)

inst_133:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x373 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x351 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7373; op2val:0x7751;
op3val:0xfbff; valaddr_reg:x3; val_offset:399*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 399*FLEN/8, x4, x1, x2)

inst_134:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x070 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a8 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7470; op2val:0x7ba8;
op3val:0xfbff; valaddr_reg:x3; val_offset:402*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 402*FLEN/8, x4, x1, x2)

inst_135:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28b and fs2 == 0 and fe2 == 0x1d and fm2 == 0x210 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a8b; op2val:0x7610;
op3val:0xfbff; valaddr_reg:x3; val_offset:405*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 405*FLEN/8, x4, x1, x2)

inst_136:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x117 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0f3 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7517; op2val:0x6cf3;
op3val:0xfbff; valaddr_reg:x3; val_offset:408*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 408*FLEN/8, x4, x1, x2)

inst_137:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x153 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x311 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7153; op2val:0x7711;
op3val:0xfbff; valaddr_reg:x3; val_offset:411*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 411*FLEN/8, x4, x1, x2)

inst_138:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x327 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x35e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b27; op2val:0x7b5e;
op3val:0xfbff; valaddr_reg:x3; val_offset:414*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 414*FLEN/8, x4, x1, x2)

inst_139:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x11d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x36e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x791d; op2val:0x7b6e;
op3val:0xfbff; valaddr_reg:x3; val_offset:417*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 417*FLEN/8, x4, x1, x2)

inst_140:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x25e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6e5e; op2val:0x739b;
op3val:0xfbff; valaddr_reg:x3; val_offset:420*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 420*FLEN/8, x4, x1, x2)

inst_141:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x16c and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1fa and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x796c; op2val:0x75fa;
op3val:0xfbff; valaddr_reg:x3; val_offset:423*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 423*FLEN/8, x4, x1, x2)

inst_142:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 0 and fe2 == 0x1c and fm2 == 0x375 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a5b; op2val:0x7375;
op3val:0xfbff; valaddr_reg:x3; val_offset:426*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 426*FLEN/8, x4, x1, x2)

inst_143:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x10f and fs2 == 0 and fe2 == 0x1d and fm2 == 0x266 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x790f; op2val:0x7666;
op3val:0xfbff; valaddr_reg:x3; val_offset:429*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 429*FLEN/8, x4, x1, x2)

inst_144:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x179 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x306 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7579; op2val:0x7b06;
op3val:0xfbff; valaddr_reg:x3; val_offset:432*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 432*FLEN/8, x4, x1, x2)

inst_145:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x184 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7804; op2val:0x7984;
op3val:0xfbff; valaddr_reg:x3; val_offset:435*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 435*FLEN/8, x4, x1, x2)

inst_146:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79f0; op2val:0x7a01;
op3val:0xfbff; valaddr_reg:x3; val_offset:438*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 438*FLEN/8, x4, x1, x2)

inst_147:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x206 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b7b; op2val:0x7a06;
op3val:0xfbff; valaddr_reg:x3; val_offset:441*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 441*FLEN/8, x4, x1, x2)

inst_148:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0fa and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x74a9; op2val:0x78fa;
op3val:0xfbff; valaddr_reg:x3; val_offset:444*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 444*FLEN/8, x4, x1, x2)

inst_149:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e0 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x251 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75e0; op2val:0x7651;
op3val:0xfbff; valaddr_reg:x3; val_offset:447*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 447*FLEN/8, x4, x1, x2)

inst_150:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a8 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1a9 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ba8; op2val:0x75a9;
op3val:0xfbff; valaddr_reg:x3; val_offset:450*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 450*FLEN/8, x4, x1, x2)

inst_151:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1f6 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b25; op2val:0x71f6;
op3val:0xfbff; valaddr_reg:x3; val_offset:453*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 453*FLEN/8, x4, x1, x2)

inst_152:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x010 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x32c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7010; op2val:0x672c;
op3val:0xfbff; valaddr_reg:x3; val_offset:456*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 456*FLEN/8, x4, x1, x2)

inst_153:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1be and fs2 == 0 and fe2 == 0x1e and fm2 == 0x356 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75be; op2val:0x7b56;
op3val:0xfbff; valaddr_reg:x3; val_offset:459*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 459*FLEN/8, x4, x1, x2)

inst_154:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x216 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2fa and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a16; op2val:0x76fa;
op3val:0xfbff; valaddr_reg:x3; val_offset:462*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 462*FLEN/8, x4, x1, x2)

inst_155:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x392 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2aa and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7392; op2val:0x7aaa;
op3val:0xfbff; valaddr_reg:x3; val_offset:465*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 465*FLEN/8, x4, x1, x2)

inst_156:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x08d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x119 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x748d; op2val:0x7919;
op3val:0xfbff; valaddr_reg:x3; val_offset:468*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 468*FLEN/8, x4, x1, x2)

inst_157:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x367 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x750f; op2val:0x7b67;
op3val:0xfbff; valaddr_reg:x3; val_offset:471*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 471*FLEN/8, x4, x1, x2)

inst_158:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x08c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x289 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x708c; op2val:0x7289;
op3val:0xfbff; valaddr_reg:x3; val_offset:474*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 474*FLEN/8, x4, x1, x2)

inst_159:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x76b9; op2val:0x7400;
op3val:0xfbff; valaddr_reg:x3; val_offset:477*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 477*FLEN/8, x4, x1, x2)

inst_160:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3e2 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3ad and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x73e2; op2val:0x73ad;
op3val:0xfbff; valaddr_reg:x3; val_offset:480*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 480*FLEN/8, x4, x1, x2)

inst_161:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x161 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1f6 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7561; op2val:0x75f6;
op3val:0xfbff; valaddr_reg:x3; val_offset:483*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 483*FLEN/8, x4, x1, x2)

inst_162:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3e4 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x09b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6be4; op2val:0x709b;
op3val:0xfbff; valaddr_reg:x3; val_offset:486*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 486*FLEN/8, x4, x1, x2)

inst_163:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2df and fs2 == 0 and fe2 == 0x1e and fm2 == 0x23a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x76df; op2val:0x7a3a;
op3val:0xfbff; valaddr_reg:x3; val_offset:489*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 489*FLEN/8, x4, x1, x2)

inst_164:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c2 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x782e; op2val:0x7ac2;
op3val:0xfbff; valaddr_reg:x3; val_offset:492*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 492*FLEN/8, x4, x1, x2)

inst_165:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x224 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0e1 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a24; op2val:0x78e1;
op3val:0xfbff; valaddr_reg:x3; val_offset:495*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 495*FLEN/8, x4, x1, x2)

inst_166:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f9 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x246 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bf9; op2val:0x7646;
op3val:0xfbff; valaddr_reg:x3; val_offset:498*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 498*FLEN/8, x4, x1, x2)

inst_167:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x111 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78f4; op2val:0x7511;
op3val:0xfbff; valaddr_reg:x3; val_offset:501*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 501*FLEN/8, x4, x1, x2)

inst_168:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0b3 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78c7; op2val:0x78b3;
op3val:0xfbff; valaddr_reg:x3; val_offset:504*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 504*FLEN/8, x4, x1, x2)

inst_169:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3e8 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7be0; op2val:0x7be8;
op3val:0xfbff; valaddr_reg:x3; val_offset:507*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 507*FLEN/8, x4, x1, x2)

inst_170:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x345 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x295 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7745; op2val:0x7695;
op3val:0xfbff; valaddr_reg:x3; val_offset:510*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 510*FLEN/8, x4, x1, x2)

inst_171:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x1e7 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2ec and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x69e7; op2val:0x6eec;
op3val:0xfbff; valaddr_reg:x3; val_offset:513*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 513*FLEN/8, x4, x1, x2)

inst_172:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x019 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x37e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7019; op2val:0x7b7e;
op3val:0xfbff; valaddr_reg:x3; val_offset:516*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 516*FLEN/8, x4, x1, x2)

inst_173:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x351 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0f2 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b51; op2val:0x6cf2;
op3val:0xfbff; valaddr_reg:x3; val_offset:519*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 519*FLEN/8, x4, x1, x2)

inst_174:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x261 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x086 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a61; op2val:0x6086;
op3val:0xfbff; valaddr_reg:x3; val_offset:522*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 522*FLEN/8, x4, x1, x2)

inst_175:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19b and fs2 == 0 and fe2 == 0x1c and fm2 == 0x189 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x759b; op2val:0x7189;
op3val:0xfbff; valaddr_reg:x3; val_offset:525*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 525*FLEN/8, x4, x1, x2)

inst_176:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15b and fs2 == 0 and fe2 == 0x1b and fm2 == 0x1e1 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x795b; op2val:0x6de1;
op3val:0xfbff; valaddr_reg:x3; val_offset:528*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 528*FLEN/8, x4, x1, x2)

inst_177:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x131 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x25d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7931; op2val:0x6a5d;
op3val:0xfbff; valaddr_reg:x3; val_offset:531*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 531*FLEN/8, x4, x1, x2)

inst_178:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3b9 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3b3 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x73b9; op2val:0x77b3;
op3val:0xfbff; valaddr_reg:x3; val_offset:534*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 534*FLEN/8, x4, x1, x2)

inst_179:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x06f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x003 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x706f; op2val:0x7803;
op3val:0xfbff; valaddr_reg:x3; val_offset:537*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 537*FLEN/8, x4, x1, x2)

inst_180:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x262 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x358 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7262; op2val:0x7b58;
op3val:0xfbff; valaddr_reg:x3; val_offset:540*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 540*FLEN/8, x4, x1, x2)

inst_181:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x173 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x782e; op2val:0x7973;
op3val:0xfbff; valaddr_reg:x3; val_offset:543*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 543*FLEN/8, x4, x1, x2)

inst_182:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x07a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3de and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x707a; op2val:0x77de;
op3val:0xfbff; valaddr_reg:x3; val_offset:546*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 546*FLEN/8, x4, x1, x2)

inst_183:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x374 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2ec and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6f74; op2val:0x6eec;
op3val:0xfbff; valaddr_reg:x3; val_offset:549*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 549*FLEN/8, x4, x1, x2)

inst_184:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x2cc and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2e2 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6acc; op2val:0x72e2;
op3val:0xfbff; valaddr_reg:x3; val_offset:552*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 552*FLEN/8, x4, x1, x2)

inst_185:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fa and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2dd and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78fa; op2val:0x7add;
op3val:0xfbff; valaddr_reg:x3; val_offset:555*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 555*FLEN/8, x4, x1, x2)

inst_186:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x00e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79bc; op2val:0x780e;
op3val:0xfbff; valaddr_reg:x3; val_offset:558*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 558*FLEN/8, x4, x1, x2)

inst_187:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x136 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2be and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7136; op2val:0x6ebe;
op3val:0xfbff; valaddr_reg:x3; val_offset:561*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 561*FLEN/8, x4, x1, x2)

inst_188:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x103 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2ba and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7903; op2val:0x72ba;
op3val:0xfbff; valaddr_reg:x3; val_offset:564*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 564*FLEN/8, x4, x1, x2)

inst_189:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0c1 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2e3 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x74c1; op2val:0x76e3;
op3val:0xfbff; valaddr_reg:x3; val_offset:567*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 567*FLEN/8, x4, x1, x2)

inst_190:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x25e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x260 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x765e; op2val:0x7a60;
op3val:0xfbff; valaddr_reg:x3; val_offset:570*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 570*FLEN/8, x4, x1, x2)

inst_191:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x07f and fs2 == 0 and fe2 == 0x1d and fm2 == 0x38f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x787f; op2val:0x778f;
op3val:0xfbff; valaddr_reg:x3; val_offset:573*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 573*FLEN/8, x4, x1, x2)

inst_192:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3e4 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a1e; op2val:0x7be4;
op3val:0xfbff; valaddr_reg:x3; val_offset:576*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 576*FLEN/8, x4, x1, x2)

inst_193:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x196 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x799f; op2val:0x7996;
op3val:0xfbff; valaddr_reg:x3; val_offset:579*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 579*FLEN/8, x4, x1, x2)

inst_194:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x3d5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x069 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x67d5; op2val:0x7869;
op3val:0xfbff; valaddr_reg:x3; val_offset:582*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 582*FLEN/8, x4, x1, x2)

inst_195:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x237 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0a2 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7237; op2val:0x78a2;
op3val:0xfbff; valaddr_reg:x3; val_offset:585*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 585*FLEN/8, x4, x1, x2)

inst_196:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1ef and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7900; op2val:0x79ef;
op3val:0xfbff; valaddr_reg:x3; val_offset:588*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 588*FLEN/8, x4, x1, x2)

inst_197:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x399 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x21d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7799; op2val:0x6a1d;
op3val:0xfbff; valaddr_reg:x3; val_offset:591*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 591*FLEN/8, x4, x1, x2)

inst_198:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x294 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a94; op2val:0x7aae;
op3val:0xfbff; valaddr_reg:x3; val_offset:594*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 594*FLEN/8, x4, x1, x2)

inst_199:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x0e2 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x243 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x68e2; op2val:0x7243;
op3val:0xfbff; valaddr_reg:x3; val_offset:597*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 597*FLEN/8, x4, x1, x2)

inst_200:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x394 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ba5; op2val:0x7b94;
op3val:0xfbff; valaddr_reg:x3; val_offset:600*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 600*FLEN/8, x4, x1, x2)

inst_201:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x16d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6d6d; op2val:0x7aae;
op3val:0xfbff; valaddr_reg:x3; val_offset:603*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 603*FLEN/8, x4, x1, x2)

inst_202:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0ed and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x795a; op2val:0x74ed;
op3val:0xfbff; valaddr_reg:x3; val_offset:606*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 606*FLEN/8, x4, x1, x2)

inst_203:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x24b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x76e3; op2val:0x764b;
op3val:0xfbff; valaddr_reg:x3; val_offset:609*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 609*FLEN/8, x4, x1, x2)

inst_204:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31d and fs2 == 0 and fe2 == 0x1d and fm2 == 0x04a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x771d; op2val:0x744a;
op3val:0xfbff; valaddr_reg:x3; val_offset:612*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 612*FLEN/8, x4, x1, x2)

inst_205:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x305 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x36f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6705; op2val:0x776f;
op3val:0xfbff; valaddr_reg:x3; val_offset:615*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 615*FLEN/8, x4, x1, x2)

inst_206:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x213 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x321 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7613; op2val:0x7b21;
op3val:0xfbff; valaddr_reg:x3; val_offset:618*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 618*FLEN/8, x4, x1, x2)

inst_207:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x07b and fs2 == 0 and fe2 == 0x1c and fm2 == 0x38d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x787b; op2val:0x738d;
op3val:0xfbff; valaddr_reg:x3; val_offset:621*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 621*FLEN/8, x4, x1, x2)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(31653,16,FLEN)
NAN_BOXED(31653,16,FLEN)
NAN_BOXED(31653,16,FLEN)
NAN_BOXED(28013,16,FLEN)
NAN_BOXED(31406,16,FLEN)
NAN_BOXED(31406,16,FLEN)
NAN_BOXED(31066,16,FLEN)
NAN_BOXED(31066,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30938,16,FLEN)
NAN_BOXED(30885,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30435,16,FLEN)
NAN_BOXED(30283,16,FLEN)
NAN_BOXED(30435,16,FLEN)
NAN_BOXED(31732,16,FLEN)
NAN_BOXED(31639,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30493,16,FLEN)
NAN_BOXED(30493,16,FLEN)
NAN_BOXED(30493,16,FLEN)
NAN_BOXED(26373,16,FLEN)
NAN_BOXED(30575,16,FLEN)
NAN_BOXED(30575,16,FLEN)
NAN_BOXED(30227,16,FLEN)
NAN_BOXED(31521,16,FLEN)
NAN_BOXED(30227,16,FLEN)
NAN_BOXED(30843,16,FLEN)
NAN_BOXED(30843,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30003,16,FLEN)
NAN_BOXED(28767,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31740,16,FLEN)
NAN_BOXED(31076,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31525,16,FLEN)
NAN_BOXED(31326,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31551,16,FLEN)
NAN_BOXED(31257,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30120,16,FLEN)
NAN_BOXED(31704,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(28967,16,FLEN)
NAN_BOXED(31239,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30560,16,FLEN)
NAN_BOXED(30781,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31589,16,FLEN)
NAN_BOXED(30721,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30120,16,FLEN)
NAN_BOXED(31503,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30559,16,FLEN)
NAN_BOXED(30858,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31177,16,FLEN)
NAN_BOXED(30664,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30001,16,FLEN)
NAN_BOXED(31128,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31554,16,FLEN)
NAN_BOXED(29769,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(29939,16,FLEN)
NAN_BOXED(31655,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30728,16,FLEN)
NAN_BOXED(30755,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30899,16,FLEN)
NAN_BOXED(29948,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30743,16,FLEN)
NAN_BOXED(31608,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(27858,16,FLEN)
NAN_BOXED(31375,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31553,16,FLEN)
NAN_BOXED(29215,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(27524,16,FLEN)
NAN_BOXED(31032,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(29503,16,FLEN)
NAN_BOXED(31488,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30765,16,FLEN)
NAN_BOXED(31444,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(29371,16,FLEN)
NAN_BOXED(31498,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31163,16,FLEN)
NAN_BOXED(26643,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(29055,16,FLEN)
NAN_BOXED(31073,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31649,16,FLEN)
NAN_BOXED(26236,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(25961,16,FLEN)
NAN_BOXED(29718,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(28934,16,FLEN)
NAN_BOXED(29152,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30250,16,FLEN)
NAN_BOXED(27013,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(28887,16,FLEN)
NAN_BOXED(26787,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30955,16,FLEN)
NAN_BOXED(31215,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30052,16,FLEN)
NAN_BOXED(26594,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31263,16,FLEN)
NAN_BOXED(31210,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31242,16,FLEN)
NAN_BOXED(31461,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30607,16,FLEN)
NAN_BOXED(29494,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(29966,16,FLEN)
NAN_BOXED(28295,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31486,16,FLEN)
NAN_BOXED(28692,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30280,16,FLEN)
NAN_BOXED(30749,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31660,16,FLEN)
NAN_BOXED(29732,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30390,16,FLEN)
NAN_BOXED(25757,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(28798,16,FLEN)
NAN_BOXED(27459,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(28967,16,FLEN)
NAN_BOXED(28193,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30736,16,FLEN)
NAN_BOXED(31709,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31731,16,FLEN)
NAN_BOXED(29551,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(29698,16,FLEN)
NAN_BOXED(30906,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31334,16,FLEN)
NAN_BOXED(31148,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30403,16,FLEN)
NAN_BOXED(30773,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(26762,16,FLEN)
NAN_BOXED(30345,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31177,16,FLEN)
NAN_BOXED(29620,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(29136,16,FLEN)
NAN_BOXED(29543,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30761,16,FLEN)
NAN_BOXED(30573,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31009,16,FLEN)
NAN_BOXED(29387,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31667,16,FLEN)
NAN_BOXED(31188,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30743,16,FLEN)
NAN_BOXED(30885,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30383,16,FLEN)
NAN_BOXED(30770,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(28159,16,FLEN)
NAN_BOXED(31339,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30758,16,FLEN)
NAN_BOXED(31582,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(29857,16,FLEN)
NAN_BOXED(31709,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(25824,16,FLEN)
NAN_BOXED(31098,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(29924,16,FLEN)
NAN_BOXED(31416,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(25605,16,FLEN)
NAN_BOXED(30520,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30661,16,FLEN)
NAN_BOXED(29353,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(27832,16,FLEN)
NAN_BOXED(29836,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31610,16,FLEN)
NAN_BOXED(27877,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(29223,16,FLEN)
NAN_BOXED(30865,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30568,16,FLEN)
NAN_BOXED(31238,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(28617,16,FLEN)
NAN_BOXED(28618,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31436,16,FLEN)
NAN_BOXED(31008,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31113,16,FLEN)
NAN_BOXED(26191,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31286,16,FLEN)
NAN_BOXED(31177,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30135,16,FLEN)
NAN_BOXED(30543,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(29773,16,FLEN)
NAN_BOXED(30773,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31650,16,FLEN)
NAN_BOXED(31342,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31407,16,FLEN)
NAN_BOXED(29886,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30673,16,FLEN)
NAN_BOXED(29734,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31086,16,FLEN)
NAN_BOXED(31576,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31370,16,FLEN)
NAN_BOXED(28195,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31738,16,FLEN)
NAN_BOXED(28847,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(27718,16,FLEN)
NAN_BOXED(28034,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31719,16,FLEN)
NAN_BOXED(31022,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(29885,16,FLEN)
NAN_BOXED(29545,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31090,16,FLEN)
NAN_BOXED(30468,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(28459,16,FLEN)
NAN_BOXED(30803,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31243,16,FLEN)
NAN_BOXED(28198,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31160,16,FLEN)
NAN_BOXED(29725,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30559,16,FLEN)
NAN_BOXED(31135,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31733,16,FLEN)
NAN_BOXED(31298,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(28833,16,FLEN)
NAN_BOXED(30478,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30914,16,FLEN)
NAN_BOXED(31501,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30740,16,FLEN)
NAN_BOXED(30647,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31150,16,FLEN)
NAN_BOXED(31613,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30606,16,FLEN)
NAN_BOXED(31665,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31222,16,FLEN)
NAN_BOXED(31043,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31440,16,FLEN)
NAN_BOXED(29490,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30320,16,FLEN)
NAN_BOXED(31061,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30995,16,FLEN)
NAN_BOXED(25072,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31152,16,FLEN)
NAN_BOXED(31503,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31366,16,FLEN)
NAN_BOXED(25698,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31189,16,FLEN)
NAN_BOXED(30937,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31506,16,FLEN)
NAN_BOXED(28269,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31266,16,FLEN)
NAN_BOXED(29281,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30896,16,FLEN)
NAN_BOXED(29215,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(28776,16,FLEN)
NAN_BOXED(30949,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(29710,16,FLEN)
NAN_BOXED(30854,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(29326,16,FLEN)
NAN_BOXED(31675,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(23095,16,FLEN)
NAN_BOXED(30659,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31043,16,FLEN)
NAN_BOXED(31240,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31077,16,FLEN)
NAN_BOXED(30043,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30725,16,FLEN)
NAN_BOXED(26379,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31239,16,FLEN)
NAN_BOXED(29070,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31301,16,FLEN)
NAN_BOXED(30327,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31307,16,FLEN)
NAN_BOXED(31464,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(28979,16,FLEN)
NAN_BOXED(30234,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(29878,16,FLEN)
NAN_BOXED(24914,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31675,16,FLEN)
NAN_BOXED(30172,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30237,16,FLEN)
NAN_BOXED(30484,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(29934,16,FLEN)
NAN_BOXED(31024,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30798,16,FLEN)
NAN_BOXED(31568,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31383,16,FLEN)
NAN_BOXED(29917,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31325,16,FLEN)
NAN_BOXED(31033,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31416,16,FLEN)
NAN_BOXED(28146,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30273,16,FLEN)
NAN_BOXED(30781,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31329,16,FLEN)
NAN_BOXED(30983,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(29555,16,FLEN)
NAN_BOXED(30545,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(29808,16,FLEN)
NAN_BOXED(31656,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31371,16,FLEN)
NAN_BOXED(30224,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(29975,16,FLEN)
NAN_BOXED(27891,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(29011,16,FLEN)
NAN_BOXED(30481,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31527,16,FLEN)
NAN_BOXED(31582,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31005,16,FLEN)
NAN_BOXED(31598,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(28254,16,FLEN)
NAN_BOXED(29595,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31084,16,FLEN)
NAN_BOXED(30202,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31323,16,FLEN)
NAN_BOXED(29557,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30991,16,FLEN)
NAN_BOXED(30310,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30073,16,FLEN)
NAN_BOXED(31494,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30724,16,FLEN)
NAN_BOXED(31108,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31216,16,FLEN)
NAN_BOXED(31233,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31611,16,FLEN)
NAN_BOXED(31238,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(29865,16,FLEN)
NAN_BOXED(30970,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30176,16,FLEN)
NAN_BOXED(30289,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31656,16,FLEN)
NAN_BOXED(30121,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31525,16,FLEN)
NAN_BOXED(29174,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(28688,16,FLEN)
NAN_BOXED(26412,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30142,16,FLEN)
NAN_BOXED(31574,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31254,16,FLEN)
NAN_BOXED(30458,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(29586,16,FLEN)
NAN_BOXED(31402,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(29837,16,FLEN)
NAN_BOXED(31001,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(29967,16,FLEN)
NAN_BOXED(31591,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(28812,16,FLEN)
NAN_BOXED(29321,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30393,16,FLEN)
NAN_BOXED(29696,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(29666,16,FLEN)
NAN_BOXED(29613,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30049,16,FLEN)
NAN_BOXED(30198,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(27620,16,FLEN)
NAN_BOXED(28827,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30431,16,FLEN)
NAN_BOXED(31290,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30766,16,FLEN)
NAN_BOXED(31426,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31268,16,FLEN)
NAN_BOXED(30945,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31737,16,FLEN)
NAN_BOXED(30278,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30964,16,FLEN)
NAN_BOXED(29969,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30919,16,FLEN)
NAN_BOXED(30899,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31712,16,FLEN)
NAN_BOXED(31720,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30533,16,FLEN)
NAN_BOXED(30357,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(27111,16,FLEN)
NAN_BOXED(28396,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(28697,16,FLEN)
NAN_BOXED(31614,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31569,16,FLEN)
NAN_BOXED(27890,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31329,16,FLEN)
NAN_BOXED(24710,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30107,16,FLEN)
NAN_BOXED(29065,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31067,16,FLEN)
NAN_BOXED(28129,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31025,16,FLEN)
NAN_BOXED(27229,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(29625,16,FLEN)
NAN_BOXED(30643,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(28783,16,FLEN)
NAN_BOXED(30723,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(29282,16,FLEN)
NAN_BOXED(31576,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30766,16,FLEN)
NAN_BOXED(31091,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(28794,16,FLEN)
NAN_BOXED(30686,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(28532,16,FLEN)
NAN_BOXED(28396,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(27340,16,FLEN)
NAN_BOXED(29410,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30970,16,FLEN)
NAN_BOXED(31453,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31164,16,FLEN)
NAN_BOXED(30734,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(28982,16,FLEN)
NAN_BOXED(28350,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30979,16,FLEN)
NAN_BOXED(29370,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(29889,16,FLEN)
NAN_BOXED(30435,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30302,16,FLEN)
NAN_BOXED(31328,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30847,16,FLEN)
NAN_BOXED(30607,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31262,16,FLEN)
NAN_BOXED(31716,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31135,16,FLEN)
NAN_BOXED(31126,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(26581,16,FLEN)
NAN_BOXED(30825,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(29239,16,FLEN)
NAN_BOXED(30882,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30976,16,FLEN)
NAN_BOXED(31215,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30617,16,FLEN)
NAN_BOXED(27165,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31380,16,FLEN)
NAN_BOXED(31406,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(26850,16,FLEN)
NAN_BOXED(29251,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31653,16,FLEN)
NAN_BOXED(31636,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(28013,16,FLEN)
NAN_BOXED(31406,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31066,16,FLEN)
NAN_BOXED(29933,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30435,16,FLEN)
NAN_BOXED(30283,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30493,16,FLEN)
NAN_BOXED(29770,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(26373,16,FLEN)
NAN_BOXED(30575,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30227,16,FLEN)
NAN_BOXED(31521,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30843,16,FLEN)
NAN_BOXED(29581,16,FLEN)
NAN_BOXED(64511,16,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;



signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_2:
    .fill 160*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;

mtrap_sigptr:
    .fill 64*XLEN/32,4,0xdeadbeef

tsig_end_canary:
CANARY;
#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif


sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
