
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.11.0
// timestamp : Sat May  6 11:14:00 2023 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fmul.cgf \
 \
//                  -- xlen 32  \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fmul.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fmul_b2 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fmul_b2)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_0:
// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==f30, rs2==f29, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x008 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x006 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x8; op2val:0x3006;
   valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)

inst_1:
// rs2 == rd != rs1, rs1==f31, rs2==f30, rd==f30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x00b and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1d1 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f31; op2:f30; dest:f30; op1val:0xb; op2val:0x31d1;
   valaddr_reg:x3; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f30, f31, f30, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2)

inst_2:
// rs1 == rs2 == rd, rs1==f28, rs2==f28, rd==f28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x016 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1d1 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f28; op2:f28; dest:f28; op1val:0x16; op2val:0x16;
   valaddr_reg:x3; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f28, f28, f28, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2)

inst_3:
// rs1 == rs2 != rd, rs1==f27, rs2==f27, rd==f29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x056 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1f4 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f27; op2:f27; dest:f29; op1val:0x56; op2val:0x56;
   valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f29, f27, f27, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2)

inst_4:
// rs1 == rd != rs2, rs1==f26, rs2==f31, rd==f26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x021 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3c1 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f26; op2:f31; dest:f26; op1val:0x21; op2val:0x37c1;
   valaddr_reg:x3; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f26, f26, f31, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2)

inst_5:
// rs1==f29, rs2==f26, rd==f27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x01c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x092 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f29; op2:f26; dest:f27; op1val:0x1c; op2val:0x3c92;
   valaddr_reg:x3; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f27, f29, f26, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2)

inst_6:
// rs1==f24, rs2==f23, rd==f25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x005 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x266 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f24; op2:f23; dest:f25; op1val:0x5; op2val:0x4a66;
   valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f25, f24, f23, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2)

inst_7:
// rs1==f23, rs2==f25, rd==f24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x058 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1d1 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f23; op2:f25; dest:f24; op1val:0x58; op2val:0x3dd1;
   valaddr_reg:x3; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f24, f23, f25, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2)

inst_8:
// rs1==f25, rs2==f24, rd==f23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x038 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x092 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f25; op2:f24; dest:f23; op1val:0x38; op2val:0x4492;
   valaddr_reg:x3; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f23, f25, f24, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2)

inst_9:
// rs1==f21, rs2==f20, rd==f22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x033 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x105 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f21; op2:f20; dest:f22; op1val:0x33; op2val:0x4905;
   valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f22, f21, f20, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2)

inst_10:
// rs1==f20, rs2==f22, rd==f21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x042 and fs2 == 1 and fe2 == 0x08 and fm2 == 0x3cf and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f20; op2:f22; dest:f21; op1val:0x42; op2val:0xa3cf;
   valaddr_reg:x3; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f21, f20, f22, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2)

inst_11:
// rs1==f22, rs2==f21, rd==f20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x046 and fs2 == 1 and fe2 == 0x09 and fm2 == 0x350 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f22; op2:f21; dest:f20; op1val:0x46; op2val:0xa750;
   valaddr_reg:x3; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f20, f22, f21, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2)

inst_12:
// rs1==f18, rs2==f17, rd==f19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x041 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x3e0 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f18; op2:f17; dest:f19; op1val:0x41; op2val:0xabe0;
   valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f19, f18, f17, dyn, 0, 0, x3, 24*FLEN/8, x4, x1, x2)

inst_13:
// rs1==f17, rs2==f19, rd==f18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x005 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x266 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f17; op2:f19; dest:f18; op1val:0x5; op2val:0xbe66;
   valaddr_reg:x3; val_offset:26*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f18, f17, f19, dyn, 0, 0, x3, 26*FLEN/8, x4, x1, x2)

inst_14:
// rs1==f19, rs2==f18, rd==f17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x02f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x172 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f19; op2:f18; dest:f17; op1val:0x2f; op2val:0xb572;
   valaddr_reg:x3; val_offset:28*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f17, f19, f18, dyn, 0, 0, x3, 28*FLEN/8, x4, x1, x2)

inst_15:
// rs1==f15, rs2==f14, rd==f16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x029 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x23e and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f15; op2:f14; dest:f16; op1val:0x29; op2val:0xba3e;
   valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f16, f15, f14, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)

inst_16:
// rs1==f14, rs2==f16, rd==f15,fs1 == 0 and fe1 == 0x00 and fm1 == 0x037 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0a7 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f14; op2:f16; dest:f15; op1val:0x37; op2val:0xbca7;
   valaddr_reg:x3; val_offset:32*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f15, f14, f16, dyn, 0, 0, x3, 32*FLEN/8, x4, x1, x2)

inst_17:
// rs1==f16, rs2==f15, rd==f14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x016 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1d1 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f16; op2:f15; dest:f14; op1val:0x16; op2val:0xc5d1;
   valaddr_reg:x3; val_offset:34*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f14, f16, f15, dyn, 0, 0, x3, 34*FLEN/8, x4, x1, x2)

inst_18:
// rs1==f12, rs2==f11, rd==f13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x017 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x190 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f12; op2:f11; dest:f13; op1val:0x17; op2val:0xc990;
   valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f13, f12, f11, dyn, 0, 0, x3, 36*FLEN/8, x4, x1, x2)

inst_19:
// rs1==f11, rs2==f13, rd==f12,fs1 == 0 and fe1 == 0x00 and fm1 == 0x01e and fs2 == 1 and fe2 == 0x13 and fm2 == 0x044 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f11; op2:f13; dest:f12; op1val:0x1e; op2val:0xcc44;
   valaddr_reg:x3; val_offset:38*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f12, f11, f13, dyn, 0, 0, x3, 38*FLEN/8, x4, x1, x2)

inst_20:
// rs1==f13, rs2==f12, rd==f11,fs1 == 0 and fe1 == 0x0f and fm1 == 0x017 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3d4 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f13; op2:f12; dest:f11; op1val:0x3c17; op2val:0x3bd4;
   valaddr_reg:x3; val_offset:40*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f11, f13, f12, dyn, 0, 0, x3, 40*FLEN/8, x4, x1, x2)

inst_21:
// rs1==f9, rs2==f8, rd==f10,fs1 == 0 and fe1 == 0x0f and fm1 == 0x017 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3d6 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f9; op2:f8; dest:f10; op1val:0x3c17; op2val:0x3bd6;
   valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f10, f9, f8, dyn, 0, 0, x3, 42*FLEN/8, x4, x1, x2)

inst_22:
// rs1==f8, rs2==f10, rd==f9,fs1 == 0 and fe1 == 0x0f and fm1 == 0x042 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x38b and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f8; op2:f10; dest:f9; op1val:0x3c42; op2val:0x3b8b;
   valaddr_reg:x3; val_offset:44*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f9, f8, f10, dyn, 0, 0, x3, 44*FLEN/8, x4, x1, x2)

inst_23:
// rs1==f10, rs2==f9, rd==f8,fs1 == 0 and fe1 == 0x0f and fm1 == 0x02f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3b5 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f10; op2:f9; dest:f8; op1val:0x3c2f; op2val:0x3bb5;
   valaddr_reg:x3; val_offset:46*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f8, f10, f9, dyn, 0, 0, x3, 46*FLEN/8, x4, x1, x2)

inst_24:
// rs1==f6, rs2==f5, rd==f7,fs1 == 0 and fe1 == 0x0f and fm1 == 0x057 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x37d and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f6; op2:f5; dest:f7; op1val:0x3c57; op2val:0x3b7d;
   valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f7, f6, f5, dyn, 0, 0, x3, 48*FLEN/8, x4, x1, x2)

inst_25:
// rs1==f5, rs2==f7, rd==f6,fs1 == 0 and fe1 == 0x0f and fm1 == 0x018 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x007 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f5; op2:f7; dest:f6; op1val:0x3c18; op2val:0x3c07;
   valaddr_reg:x3; val_offset:50*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f6, f5, f7, dyn, 0, 0, x3, 50*FLEN/8, x4, x1, x2)

inst_26:
// rs1==f7, rs2==f6, rd==f5,fs1 == 0 and fe1 == 0x0f and fm1 == 0x036 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x009 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f7; op2:f6; dest:f5; op1val:0x3c36; op2val:0x3c09;
   valaddr_reg:x3; val_offset:52*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f5, f7, f6, dyn, 0, 0, x3, 52*FLEN/8, x4, x1, x2)

inst_27:
// rs1==f3, rs2==f2, rd==f4,fs1 == 0 and fe1 == 0x0f and fm1 == 0x044 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x038 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f3; op2:f2; dest:f4; op1val:0x3c44; op2val:0x3c38;
   valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f4, f3, f2, dyn, 0, 0, x3, 54*FLEN/8, x4, x1, x2)

inst_28:
// rs1==f2, rs2==f4, rd==f3,fs1 == 0 and fe1 == 0x0f and fm1 == 0x02f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0c7 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f2; op2:f4; dest:f3; op1val:0x3c2f; op2val:0x3cc7;
   valaddr_reg:x3; val_offset:56*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f3, f2, f4, dyn, 0, 0, x3, 56*FLEN/8, x4, x1, x2)

inst_29:
// rs1==f4, rs2==f3, rd==f2,fs1 == 0 and fe1 == 0x0f and fm1 == 0x02e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1bd and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f4; op2:f3; dest:f2; op1val:0x3c2e; op2val:0x3dbd;
   valaddr_reg:x3; val_offset:58*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f2, f4, f3, dyn, 0, 0, x3, 58*FLEN/8, x4, x1, x2)

inst_30:
// rs1==f1,fs1 == 0 and fe1 == 0x0f and fm1 == 0x03a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x394 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f1; op2:f30; dest:f31; op1val:0x3c3a; op2val:0xbb94;
   valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f1, f30, dyn, 0, 0, x3, 60*FLEN/8, x4, x1, x2)

inst_31:
// rs1==f0,fs1 == 0 and fe1 == 0x0f and fm1 == 0x061 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x352 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f0; op2:f30; dest:f31; op1val:0x3c61; op2val:0xbb52;
   valaddr_reg:x3; val_offset:62*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f0, f30, dyn, 0, 0, x3, 62*FLEN/8, x4, x1, x2)

inst_32:
// rs2==f1,fs1 == 0 and fe1 == 0x0f and fm1 == 0x05c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x35e and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f1; dest:f31; op1val:0x3c5c; op2val:0xbb5e;
   valaddr_reg:x3; val_offset:64*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f1, dyn, 0, 0, x3, 64*FLEN/8, x4, x1, x2)

inst_33:
// rs2==f0,fs1 == 0 and fe1 == 0x0f and fm1 == 0x03c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x39d and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f0; dest:f31; op1val:0x3c3c; op2val:0xbb9d;
   valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f0, dyn, 0, 0, x3, 66*FLEN/8, x4, x1, x2)

inst_34:
// rd==f1,fs1 == 0 and fe1 == 0x0f and fm1 == 0x044 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x39e and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f31; op2:f30; dest:f1; op1val:0x3c44; op2val:0xbb9e;
   valaddr_reg:x3; val_offset:68*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f1, f31, f30, dyn, 0, 0, x3, 68*FLEN/8, x4, x1, x2)

inst_35:
// rd==f0,fs1 == 0 and fe1 == 0x0f and fm1 == 0x03f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3c5 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f31; op2:f30; dest:f0; op1val:0x3c3f; op2val:0xbbc5;
   valaddr_reg:x3; val_offset:70*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f0, f31, f30, dyn, 0, 0, x3, 70*FLEN/8, x4, x1, x2)

inst_36:
// fs1 == 0 and fe1 == 0x0f and fm1 == 0x040 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x3c40; op2val:0xbc00;
   valaddr_reg:x3; val_offset:72*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 72*FLEN/8, x4, x1, x2)

inst_37:
// fs1 == 0 and fe1 == 0x0f and fm1 == 0x042 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03a and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x3c42; op2val:0xbc3a;
   valaddr_reg:x3; val_offset:74*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 74*FLEN/8, x4, x1, x2)

inst_38:
// fs1 == 0 and fe1 == 0x0f and fm1 == 0x055 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x09d and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x3c55; op2val:0xbc9d;
   valaddr_reg:x3; val_offset:76*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 76*FLEN/8, x4, x1, x2)

inst_39:
// fs1 == 0 and fe1 == 0x0f and fm1 == 0x03c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1aa and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x3c3c; op2val:0xbdaa;
   valaddr_reg:x3; val_offset:78*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 78*FLEN/8, x4, x1, x2)

inst_40:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x049 and fs2 == 0 and fe2 == 0x08 and fm2 == 0x30f and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x49; op2val:0x230f;
   valaddr_reg:x3; val_offset:80*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 80*FLEN/8, x4, x1, x2)

inst_41:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x048 and fs2 == 0 and fe2 == 0x0a and fm2 == 0x155 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x48; op2val:0x2955;
   valaddr_reg:x3; val_offset:82*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 82*FLEN/8, x4, x1, x2)

inst_42:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03b and fs2 == 0 and fe2 == 0x0b and fm2 == 0x16c and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x3b; op2val:0x2d6c;
   valaddr_reg:x3; val_offset:84*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 84*FLEN/8, x4, x1, x2)

inst_43:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x055 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2c6 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x55; op2val:0x2ec6;
   valaddr_reg:x3; val_offset:86*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 86*FLEN/8, x4, x1, x2)

inst_44:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02a and fs2 == 0 and fe2 == 0x0d and fm2 == 0x279 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x2a; op2val:0x3679;
   valaddr_reg:x3; val_offset:88*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 88*FLEN/8, x4, x1, x2)

inst_45:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x016 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x200 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x16; op2val:0x3e00;
   valaddr_reg:x3; val_offset:90*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 90*FLEN/8, x4, x1, x2)

inst_46:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x023 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x36d and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x23; op2val:0x3f6d;
   valaddr_reg:x3; val_offset:92*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 92*FLEN/8, x4, x1, x2)

inst_47:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03e and fs2 == 0 and fe2 == 0x10 and fm2 == 0x029 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x3e; op2val:0x4029;
   valaddr_reg:x3; val_offset:94*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 94*FLEN/8, x4, x1, x2)

inst_48:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x027 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x296 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x27; op2val:0x4696;
   valaddr_reg:x3; val_offset:96*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 96*FLEN/8, x4, x1, x2)

inst_49:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x041 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x3e4 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x41; op2val:0x47e4;
   valaddr_reg:x3; val_offset:98*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 98*FLEN/8, x4, x1, x2)

inst_50:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x043 and fs2 == 1 and fe2 == 0x08 and fm2 == 0x3b1 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x43; op2val:0xa3b1;
   valaddr_reg:x3; val_offset:100*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 100*FLEN/8, x4, x1, x2)

inst_51:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x054 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x092 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x54; op2val:0xa892;
   valaddr_reg:x3; val_offset:102*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 102*FLEN/8, x4, x1, x2)

inst_52:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04c and fs2 == 1 and fe2 == 0x0b and fm2 == 0x035 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x4c; op2val:0xac35;
   valaddr_reg:x3; val_offset:104*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 104*FLEN/8, x4, x1, x2)

inst_53:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x028 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x333 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x28; op2val:0xb333;
   valaddr_reg:x3; val_offset:106*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 106*FLEN/8, x4, x1, x2)

inst_54:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x109 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x1b; op2val:0xb909;
   valaddr_reg:x3; val_offset:108*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 108*FLEN/8, x4, x1, x2)

inst_55:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x042 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x42; op2val:0xb800;
   valaddr_reg:x3; val_offset:110*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 110*FLEN/8, x4, x1, x2)

inst_56:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x058 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1e8 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x58; op2val:0xb9e8;
   valaddr_reg:x3; val_offset:112*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 112*FLEN/8, x4, x1, x2)

inst_57:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00a and fs2 == 1 and fe2 == 0x12 and fm2 == 0x273 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0xa; op2val:0xca73;
   valaddr_reg:x3; val_offset:114*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 114*FLEN/8, x4, x1, x2)

inst_58:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05d and fs2 == 1 and fe2 == 0x10 and fm2 == 0x186 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x5d; op2val:0xc186;
   valaddr_reg:x3; val_offset:116*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 116*FLEN/8, x4, x1, x2)

inst_59:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x019 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x121 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x19; op2val:0xcd21;
   valaddr_reg:x3; val_offset:118*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 118*FLEN/8, x4, x1, x2)

inst_60:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00e and fs2 == 0 and fe2 == 0x15 and fm2 == 0x090 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0xe; op2val:0x5490;
   valaddr_reg:x3; val_offset:120*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 120*FLEN/8, x4, x1, x2)

inst_61:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04a and fs2 == 0 and fe2 == 0x12 and fm2 == 0x2e6 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x4a; op2val:0x4ae6;
   valaddr_reg:x3; val_offset:122*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 122*FLEN/8, x4, x1, x2)

inst_62:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x007 and fs2 == 0 and fe2 == 0x16 and fm2 == 0x08c and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x7; op2val:0x588c;
   valaddr_reg:x3; val_offset:124*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 124*FLEN/8, x4, x1, x2)

inst_63:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04c and fs2 == 0 and fe2 == 0x12 and fm2 == 0x2ad and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x4c; op2val:0x4aad;
   valaddr_reg:x3; val_offset:126*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 126*FLEN/8, x4, x1, x2)

inst_64:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x058 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1b8 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x58; op2val:0x49b8;
   valaddr_reg:x3; val_offset:128*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 128*FLEN/8, x4, x1, x2)

inst_65:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x061 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x11b and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x61; op2val:0x491b;
   valaddr_reg:x3; val_offset:130*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 130*FLEN/8, x4, x1, x2)

inst_66:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x012 and fs2 == 0 and fe2 == 0x14 and fm2 == 0x2a8 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x12; op2val:0x52a8;
   valaddr_reg:x3; val_offset:132*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 132*FLEN/8, x4, x1, x2)

inst_67:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x020 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x2fe and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x20; op2val:0x4efe;
   valaddr_reg:x3; val_offset:134*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 134*FLEN/8, x4, x1, x2)

inst_68:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x008 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x1fe and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x8; op2val:0x55fe;
   valaddr_reg:x3; val_offset:136*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 136*FLEN/8, x4, x1, x2)

inst_69:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05c and fs2 == 0 and fe2 == 0x11 and fm2 == 0x18d and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x5c; op2val:0x458d;
   valaddr_reg:x3; val_offset:138*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 138*FLEN/8, x4, x1, x2)

inst_70:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x005 and fs2 == 1 and fe2 == 0x16 and fm2 == 0x263 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x5; op2val:0xda63;
   valaddr_reg:x3; val_offset:140*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 140*FLEN/8, x4, x1, x2)

inst_71:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02f and fs2 == 1 and fe2 == 0x13 and fm2 == 0x16e and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x2f; op2val:0xcd6e;
   valaddr_reg:x3; val_offset:142*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 142*FLEN/8, x4, x1, x2)

inst_72:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x017 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x189 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x17; op2val:0xd189;
   valaddr_reg:x3; val_offset:144*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 144*FLEN/8, x4, x1, x2)

inst_73:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x057 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x1d5 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x57; op2val:0xc9d5;
   valaddr_reg:x3; val_offset:146*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 146*FLEN/8, x4, x1, x2)

inst_74:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00b and fs2 == 1 and fe2 == 0x15 and fm2 == 0x1b8 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0xb; op2val:0xd5b8;
   valaddr_reg:x3; val_offset:148*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 148*FLEN/8, x4, x1, x2)

inst_75:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x009 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x2e1 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x9; op2val:0xd6e1;
   valaddr_reg:x3; val_offset:150*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 150*FLEN/8, x4, x1, x2)

inst_76:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x006 and fs2 == 1 and fe2 == 0x16 and fm2 == 0x0fe and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x6; op2val:0xd8fe;
   valaddr_reg:x3; val_offset:152*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 152*FLEN/8, x4, x1, x2)

inst_77:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x003 and fs2 == 1 and fe2 == 0x17 and fm2 == 0x0a9 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x3; op2val:0xdca9;
   valaddr_reg:x3; val_offset:154*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 154*FLEN/8, x4, x1, x2)

inst_78:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x021 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x1cf and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x21; op2val:0xcdcf;
   valaddr_reg:x3; val_offset:156*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 156*FLEN/8, x4, x1, x2)

inst_79:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x015 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x215 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x15; op2val:0xce15;
   valaddr_reg:x3; val_offset:158*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 158*FLEN/8, x4, x1, x2)

inst_80:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x018 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3d3 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x418; op2val:0x3bd3;
   valaddr_reg:x3; val_offset:160*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 160*FLEN/8, x4, x1, x2)

inst_81:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x059 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x35f and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x459; op2val:0x3b5f;
   valaddr_reg:x3; val_offset:162*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 162*FLEN/8, x4, x1, x2)

inst_82:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x032 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3a8 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x432; op2val:0x3ba8;
   valaddr_reg:x3; val_offset:164*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 164*FLEN/8, x4, x1, x2)

inst_83:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x006 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x001 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x406; op2val:0x3c01;
   valaddr_reg:x3; val_offset:166*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 166*FLEN/8, x4, x1, x2)

inst_84:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x014 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3f8 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x414; op2val:0x3bf8;
   valaddr_reg:x3; val_offset:168*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 168*FLEN/8, x4, x1, x2)

inst_85:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x01e and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x401; op2val:0x3c1e;
   valaddr_reg:x3; val_offset:170*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 170*FLEN/8, x4, x1, x2)

inst_86:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x04f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3e4 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x44f; op2val:0x3be4;
   valaddr_reg:x3; val_offset:172*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 172*FLEN/8, x4, x1, x2)

inst_87:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x060 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x01d and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x460; op2val:0x3c1d;
   valaddr_reg:x3; val_offset:174*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 174*FLEN/8, x4, x1, x2)

inst_88:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x00f and fs2 == 0 and fe2 == 0x0f and fm2 == 0x0ed and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x40f; op2val:0x3ced;
   valaddr_reg:x3; val_offset:176*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 176*FLEN/8, x4, x1, x2)

inst_89:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x02c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1c0 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x42c; op2val:0x3dc0;
   valaddr_reg:x3; val_offset:178*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 178*FLEN/8, x4, x1, x2)

inst_90:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x004 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3fa and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x404; op2val:0xbbfa;
   valaddr_reg:x3; val_offset:180*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 180*FLEN/8, x4, x1, x2)

inst_91:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x03a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x396 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x43a; op2val:0xbb96;
   valaddr_reg:x3; val_offset:182*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 182*FLEN/8, x4, x1, x2)

inst_92:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x063 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x352 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x463; op2val:0xbb52;
   valaddr_reg:x3; val_offset:184*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 184*FLEN/8, x4, x1, x2)

inst_93:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x05f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x360 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x45f; op2val:0xbb60;
   valaddr_reg:x3; val_offset:186*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 186*FLEN/8, x4, x1, x2)

inst_94:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x022 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3dd and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x422; op2val:0xbbdd;
   valaddr_reg:x3; val_offset:188*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 188*FLEN/8, x4, x1, x2)

inst_95:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x034 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3d9 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x434; op2val:0xbbd9;
   valaddr_reg:x3; val_offset:190*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 190*FLEN/8, x4, x1, x2)

inst_96:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x05b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ce and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x45b; op2val:0xbbce;
   valaddr_reg:x3; val_offset:192*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 192*FLEN/8, x4, x1, x2)

inst_97:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x03d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03f and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x43d; op2val:0xbc3f;
   valaddr_reg:x3; val_offset:194*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 194*FLEN/8, x4, x1, x2)

inst_98:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x00c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f1 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x40c; op2val:0xbcf1;
   valaddr_reg:x3; val_offset:196*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 196*FLEN/8, x4, x1, x2)

inst_99:
// fs1 == 0 and fe1 == 0x01 and fm1 == 0x058 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x186 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x458; op2val:0xbd86;
   valaddr_reg:x3; val_offset:198*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 198*FLEN/8, x4, x1, x2)

inst_100:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3e2 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x780e; op2val:0x3fe2;
   valaddr_reg:x3; val_offset:200*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 200*FLEN/8, x4, x1, x2)

inst_101:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x38f and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x783a; op2val:0x3f8f;
   valaddr_reg:x3; val_offset:202*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 202*FLEN/8, x4, x1, x2)

inst_102:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x043 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x37d and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x7843; op2val:0x3f7d;
   valaddr_reg:x3; val_offset:204*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 204*FLEN/8, x4, x1, x2)

inst_103:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x033 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x396 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x7833; op2val:0x3f96;
   valaddr_reg:x3; val_offset:206*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 206*FLEN/8, x4, x1, x2)

inst_104:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x042 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x374 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x7842; op2val:0x3f74;
   valaddr_reg:x3; val_offset:208*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 208*FLEN/8, x4, x1, x2)

inst_105:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x013 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3ba and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x7813; op2val:0x3fba;
   valaddr_reg:x3; val_offset:210*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 210*FLEN/8, x4, x1, x2)

inst_106:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x022 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x37f and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x7822; op2val:0x3f7f;
   valaddr_reg:x3; val_offset:212*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 212*FLEN/8, x4, x1, x2)

inst_107:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04e and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2f7 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x784e; op2val:0x3ef7;
   valaddr_reg:x3; val_offset:214*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 214*FLEN/8, x4, x1, x2)

inst_108:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x054 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x277 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x7854; op2val:0x3e77;
   valaddr_reg:x3; val_offset:216*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 216*FLEN/8, x4, x1, x2)

inst_109:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05a and fs2 == 0 and fe2 == 0x0f and fm2 == 0x182 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x785a; op2val:0x3d82;
   valaddr_reg:x3; val_offset:218*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 218*FLEN/8, x4, x1, x2)

inst_110:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x012 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3da and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x7812; op2val:0xbfda;
   valaddr_reg:x3; val_offset:220*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 220*FLEN/8, x4, x1, x2)

inst_111:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x008 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3ed and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x7808; op2val:0xbfed;
   valaddr_reg:x3; val_offset:222*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 222*FLEN/8, x4, x1, x2)

inst_112:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x005 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3f1 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x7805; op2val:0xbff1;
   valaddr_reg:x3; val_offset:224*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 224*FLEN/8, x4, x1, x2)

inst_113:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x015 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3ce and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x7815; op2val:0xbfce;
   valaddr_reg:x3; val_offset:226*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 226*FLEN/8, x4, x1, x2)

inst_114:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3d5 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x780d; op2val:0xbfd5;
   valaddr_reg:x3; val_offset:228*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 228*FLEN/8, x4, x1, x2)

inst_115:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x052 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x349 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x7852; op2val:0xbf49;
   valaddr_reg:x3; val_offset:230*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 230*FLEN/8, x4, x1, x2)

inst_116:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x042 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x346 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x7842; op2val:0xbf46;
   valaddr_reg:x3; val_offset:232*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 232*FLEN/8, x4, x1, x2)

inst_117:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x005 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x375 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x7805; op2val:0xbf75;
   valaddr_reg:x3; val_offset:234*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 234*FLEN/8, x4, x1, x2)

inst_118:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2cc and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x781e; op2val:0xbecc;
   valaddr_reg:x3; val_offset:236*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 236*FLEN/8, x4, x1, x2)

inst_119:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x039 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1ae and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x7839; op2val:0xbdae;
   valaddr_reg:x3; val_offset:238*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 238*FLEN/8, x4, x1, x2)

inst_120:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x016 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x1d1 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x16; op2val:0x31d1;
   valaddr_reg:x3; val_offset:240*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 240*FLEN/8, x4, x1, x2)

inst_121:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x056 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x1f4 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff  
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x56; op2val:0x2df4;
   valaddr_reg:x3; val_offset:242*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 242*FLEN/8, x4, x1, x2)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(8,16,FLEN)
NAN_BOXED(12294,16,FLEN)
NAN_BOXED(11,16,FLEN)
NAN_BOXED(12753,16,FLEN)
NAN_BOXED(22,16,FLEN)
NAN_BOXED(22,16,FLEN)
NAN_BOXED(86,16,FLEN)
NAN_BOXED(86,16,FLEN)
NAN_BOXED(33,16,FLEN)
NAN_BOXED(14273,16,FLEN)
NAN_BOXED(28,16,FLEN)
NAN_BOXED(15506,16,FLEN)
NAN_BOXED(5,16,FLEN)
NAN_BOXED(19046,16,FLEN)
NAN_BOXED(88,16,FLEN)
NAN_BOXED(15825,16,FLEN)
NAN_BOXED(56,16,FLEN)
NAN_BOXED(17554,16,FLEN)
NAN_BOXED(51,16,FLEN)
NAN_BOXED(18693,16,FLEN)
NAN_BOXED(66,16,FLEN)
NAN_BOXED(41935,16,FLEN)
NAN_BOXED(70,16,FLEN)
NAN_BOXED(42832,16,FLEN)
NAN_BOXED(65,16,FLEN)
NAN_BOXED(44000,16,FLEN)
NAN_BOXED(5,16,FLEN)
NAN_BOXED(48742,16,FLEN)
NAN_BOXED(47,16,FLEN)
NAN_BOXED(46450,16,FLEN)
NAN_BOXED(41,16,FLEN)
NAN_BOXED(47678,16,FLEN)
NAN_BOXED(55,16,FLEN)
NAN_BOXED(48295,16,FLEN)
NAN_BOXED(22,16,FLEN)
NAN_BOXED(50641,16,FLEN)
NAN_BOXED(23,16,FLEN)
NAN_BOXED(51600,16,FLEN)
NAN_BOXED(30,16,FLEN)
NAN_BOXED(52292,16,FLEN)
NAN_BOXED(15383,16,FLEN)
NAN_BOXED(15316,16,FLEN)
NAN_BOXED(15383,16,FLEN)
NAN_BOXED(15318,16,FLEN)
NAN_BOXED(15426,16,FLEN)
NAN_BOXED(15243,16,FLEN)
NAN_BOXED(15407,16,FLEN)
NAN_BOXED(15285,16,FLEN)
NAN_BOXED(15447,16,FLEN)
NAN_BOXED(15229,16,FLEN)
NAN_BOXED(15384,16,FLEN)
NAN_BOXED(15367,16,FLEN)
NAN_BOXED(15414,16,FLEN)
NAN_BOXED(15369,16,FLEN)
NAN_BOXED(15428,16,FLEN)
NAN_BOXED(15416,16,FLEN)
NAN_BOXED(15407,16,FLEN)
NAN_BOXED(15559,16,FLEN)
NAN_BOXED(15406,16,FLEN)
NAN_BOXED(15805,16,FLEN)
NAN_BOXED(15418,16,FLEN)
NAN_BOXED(48020,16,FLEN)
NAN_BOXED(15457,16,FLEN)
NAN_BOXED(47954,16,FLEN)
NAN_BOXED(15452,16,FLEN)
NAN_BOXED(47966,16,FLEN)
NAN_BOXED(15420,16,FLEN)
NAN_BOXED(48029,16,FLEN)
NAN_BOXED(15428,16,FLEN)
NAN_BOXED(48030,16,FLEN)
NAN_BOXED(15423,16,FLEN)
NAN_BOXED(48069,16,FLEN)
NAN_BOXED(15424,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(15426,16,FLEN)
NAN_BOXED(48186,16,FLEN)
NAN_BOXED(15445,16,FLEN)
NAN_BOXED(48285,16,FLEN)
NAN_BOXED(15420,16,FLEN)
NAN_BOXED(48554,16,FLEN)
NAN_BOXED(73,16,FLEN)
NAN_BOXED(8975,16,FLEN)
NAN_BOXED(72,16,FLEN)
NAN_BOXED(10581,16,FLEN)
NAN_BOXED(59,16,FLEN)
NAN_BOXED(11628,16,FLEN)
NAN_BOXED(85,16,FLEN)
NAN_BOXED(11974,16,FLEN)
NAN_BOXED(42,16,FLEN)
NAN_BOXED(13945,16,FLEN)
NAN_BOXED(22,16,FLEN)
NAN_BOXED(15872,16,FLEN)
NAN_BOXED(35,16,FLEN)
NAN_BOXED(16237,16,FLEN)
NAN_BOXED(62,16,FLEN)
NAN_BOXED(16425,16,FLEN)
NAN_BOXED(39,16,FLEN)
NAN_BOXED(18070,16,FLEN)
NAN_BOXED(65,16,FLEN)
NAN_BOXED(18404,16,FLEN)
NAN_BOXED(67,16,FLEN)
NAN_BOXED(41905,16,FLEN)
NAN_BOXED(84,16,FLEN)
NAN_BOXED(43154,16,FLEN)
NAN_BOXED(76,16,FLEN)
NAN_BOXED(44085,16,FLEN)
NAN_BOXED(40,16,FLEN)
NAN_BOXED(45875,16,FLEN)
NAN_BOXED(27,16,FLEN)
NAN_BOXED(47369,16,FLEN)
NAN_BOXED(66,16,FLEN)
NAN_BOXED(47104,16,FLEN)
NAN_BOXED(88,16,FLEN)
NAN_BOXED(47592,16,FLEN)
NAN_BOXED(10,16,FLEN)
NAN_BOXED(51827,16,FLEN)
NAN_BOXED(93,16,FLEN)
NAN_BOXED(49542,16,FLEN)
NAN_BOXED(25,16,FLEN)
NAN_BOXED(52513,16,FLEN)
NAN_BOXED(14,16,FLEN)
NAN_BOXED(21648,16,FLEN)
NAN_BOXED(74,16,FLEN)
NAN_BOXED(19174,16,FLEN)
NAN_BOXED(7,16,FLEN)
NAN_BOXED(22668,16,FLEN)
NAN_BOXED(76,16,FLEN)
NAN_BOXED(19117,16,FLEN)
NAN_BOXED(88,16,FLEN)
NAN_BOXED(18872,16,FLEN)
NAN_BOXED(97,16,FLEN)
NAN_BOXED(18715,16,FLEN)
NAN_BOXED(18,16,FLEN)
NAN_BOXED(21160,16,FLEN)
NAN_BOXED(32,16,FLEN)
NAN_BOXED(20222,16,FLEN)
NAN_BOXED(8,16,FLEN)
NAN_BOXED(22014,16,FLEN)
NAN_BOXED(92,16,FLEN)
NAN_BOXED(17805,16,FLEN)
NAN_BOXED(5,16,FLEN)
NAN_BOXED(55907,16,FLEN)
NAN_BOXED(47,16,FLEN)
NAN_BOXED(52590,16,FLEN)
NAN_BOXED(23,16,FLEN)
NAN_BOXED(53641,16,FLEN)
NAN_BOXED(87,16,FLEN)
NAN_BOXED(51669,16,FLEN)
NAN_BOXED(11,16,FLEN)
NAN_BOXED(54712,16,FLEN)
NAN_BOXED(9,16,FLEN)
NAN_BOXED(55009,16,FLEN)
NAN_BOXED(6,16,FLEN)
NAN_BOXED(55550,16,FLEN)
NAN_BOXED(3,16,FLEN)
NAN_BOXED(56489,16,FLEN)
NAN_BOXED(33,16,FLEN)
NAN_BOXED(52687,16,FLEN)
NAN_BOXED(21,16,FLEN)
NAN_BOXED(52757,16,FLEN)
NAN_BOXED(1048,16,FLEN)
NAN_BOXED(15315,16,FLEN)
NAN_BOXED(1113,16,FLEN)
NAN_BOXED(15199,16,FLEN)
NAN_BOXED(1074,16,FLEN)
NAN_BOXED(15272,16,FLEN)
NAN_BOXED(1030,16,FLEN)
NAN_BOXED(15361,16,FLEN)
NAN_BOXED(1044,16,FLEN)
NAN_BOXED(15352,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(15390,16,FLEN)
NAN_BOXED(1103,16,FLEN)
NAN_BOXED(15332,16,FLEN)
NAN_BOXED(1120,16,FLEN)
NAN_BOXED(15389,16,FLEN)
NAN_BOXED(1039,16,FLEN)
NAN_BOXED(15597,16,FLEN)
NAN_BOXED(1068,16,FLEN)
NAN_BOXED(15808,16,FLEN)
NAN_BOXED(1028,16,FLEN)
NAN_BOXED(48122,16,FLEN)
NAN_BOXED(1082,16,FLEN)
NAN_BOXED(48022,16,FLEN)
NAN_BOXED(1123,16,FLEN)
NAN_BOXED(47954,16,FLEN)
NAN_BOXED(1119,16,FLEN)
NAN_BOXED(47968,16,FLEN)
NAN_BOXED(1058,16,FLEN)
NAN_BOXED(48093,16,FLEN)
NAN_BOXED(1076,16,FLEN)
NAN_BOXED(48089,16,FLEN)
NAN_BOXED(1115,16,FLEN)
NAN_BOXED(48078,16,FLEN)
NAN_BOXED(1085,16,FLEN)
NAN_BOXED(48191,16,FLEN)
NAN_BOXED(1036,16,FLEN)
NAN_BOXED(48369,16,FLEN)
NAN_BOXED(1112,16,FLEN)
NAN_BOXED(48518,16,FLEN)
NAN_BOXED(30734,16,FLEN)
NAN_BOXED(16354,16,FLEN)
NAN_BOXED(30778,16,FLEN)
NAN_BOXED(16271,16,FLEN)
NAN_BOXED(30787,16,FLEN)
NAN_BOXED(16253,16,FLEN)
NAN_BOXED(30771,16,FLEN)
NAN_BOXED(16278,16,FLEN)
NAN_BOXED(30786,16,FLEN)
NAN_BOXED(16244,16,FLEN)
NAN_BOXED(30739,16,FLEN)
NAN_BOXED(16314,16,FLEN)
NAN_BOXED(30754,16,FLEN)
NAN_BOXED(16255,16,FLEN)
NAN_BOXED(30798,16,FLEN)
NAN_BOXED(16119,16,FLEN)
NAN_BOXED(30804,16,FLEN)
NAN_BOXED(15991,16,FLEN)
NAN_BOXED(30810,16,FLEN)
NAN_BOXED(15746,16,FLEN)
NAN_BOXED(30738,16,FLEN)
NAN_BOXED(49114,16,FLEN)
NAN_BOXED(30728,16,FLEN)
NAN_BOXED(49133,16,FLEN)
NAN_BOXED(30725,16,FLEN)
NAN_BOXED(49137,16,FLEN)
NAN_BOXED(30741,16,FLEN)
NAN_BOXED(49102,16,FLEN)
NAN_BOXED(30733,16,FLEN)
NAN_BOXED(49109,16,FLEN)
NAN_BOXED(30802,16,FLEN)
NAN_BOXED(48969,16,FLEN)
NAN_BOXED(30786,16,FLEN)
NAN_BOXED(48966,16,FLEN)
NAN_BOXED(30725,16,FLEN)
NAN_BOXED(49013,16,FLEN)
NAN_BOXED(30750,16,FLEN)
NAN_BOXED(48844,16,FLEN)
NAN_BOXED(30777,16,FLEN)
NAN_BOXED(48558,16,FLEN)
NAN_BOXED(22,16,FLEN)
NAN_BOXED(12753,16,FLEN)
NAN_BOXED(86,16,FLEN)
NAN_BOXED(11764,16,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;



signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 244*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;

mtrap_sigptr:
    .fill 64*XLEN/32,4,0xdeadbeef

tsig_end_canary:
CANARY;
#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif


sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
