
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.12.2
// timestamp : Wed Sep 25 04:50:26 2024 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fmul.cgf \
 \
//                  -- xlen 32  \
//                  --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fmul.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fmul_b5 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fmul_b5)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x13,test_dataset_0)
RVTEST_SIGBASE(x4,signature_x4_1)

inst_0:
// rs1 == rd != rs2, rs1==x0, rs2==x20, rd==x0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x0; op2:x20; dest:x0; op1val:0x0; op2val:0x0;
   valaddr_reg:x13; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x9
*/
TEST_FPRR_OP(fmul.h, x0, x0, x20, dyn, 0, 0, x13, 0*FLEN/8, x15, x4, x9)

inst_1:
// rs1 == rs2 == rd, rs1==x1, rs2==x1, rd==x1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x1; op2:x1; dest:x1; op1val:0x7ba5; op2val:0x7ba5;
   valaddr_reg:x13; val_offset:2*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x9
*/
TEST_FPRR_OP(fmul.h, x1, x1, x1, dyn, 32, 0, x13, 2*FLEN/8, x15, x4, x9)

inst_2:
// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==x7, rs2==x6, rd==x26,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x7; op2:x6; dest:x26; op1val:0x7ba5; op2val:0x0;
   valaddr_reg:x13; val_offset:4*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x9
*/
TEST_FPRR_OP(fmul.h, x26, x7, x6, dyn, 64, 0, x13, 4*FLEN/8, x15, x4, x9)

inst_3:
// rs1 == rs2 != rd, rs1==x2, rs2==x2, rd==x21,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x2; op2:x2; dest:x21; op1val:0x7ba5; op2val:0x7ba5;
   valaddr_reg:x13; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x9
*/
TEST_FPRR_OP(fmul.h, x21, x2, x2, dyn, 96, 0, x13, 6*FLEN/8, x15, x4, x9)

inst_4:
// rs2 == rd != rs1, rs1==x3, rs2==x30, rd==x30,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x3; op2:x30; dest:x30; op1val:0x7ba5; op2val:0x0;
   valaddr_reg:x13; val_offset:8*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x9
*/
TEST_FPRR_OP(fmul.h, x30, x3, x30, dyn, 128, 0, x13, 8*FLEN/8, x15, x4, x9)

inst_5:
// rs1==x20, rs2==x5, rd==x25,fs1 == 0 and fe1 == 0x1a and fm1 == 0x33c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x20; op2:x5; dest:x25; op1val:0x6b3c; op2val:0x0;
   valaddr_reg:x13; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x9
*/
TEST_FPRR_OP(fmul.h, x25, x20, x5, dyn, 0, 0, x13, 10*FLEN/8, x15, x4, x9)

inst_6:
// rs1==x21, rs2==x31, rd==x20,fs1 == 0 and fe1 == 0x1a and fm1 == 0x33c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x21; op2:x31; dest:x20; op1val:0x6b3c; op2val:0x0;
   valaddr_reg:x13; val_offset:12*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x9
*/
TEST_FPRR_OP(fmul.h, x20, x21, x31, dyn, 32, 0, x13, 12*FLEN/8, x15, x4, x9)

inst_7:
// rs1==x26, rs2==x3, rd==x22,fs1 == 0 and fe1 == 0x1a and fm1 == 0x33c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x26; op2:x3; dest:x22; op1val:0x6b3c; op2val:0x0;
   valaddr_reg:x13; val_offset:14*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x9
*/
TEST_FPRR_OP(fmul.h, x22, x26, x3, dyn, 64, 0, x13, 14*FLEN/8, x15, x4, x9)

inst_8:
// rs1==x5, rs2==x8, rd==x28,fs1 == 0 and fe1 == 0x1a and fm1 == 0x33c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x5; op2:x8; dest:x28; op1val:0x6b3c; op2val:0x0;
   valaddr_reg:x13; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x9
*/
TEST_FPRR_OP(fmul.h, x28, x5, x8, dyn, 96, 0, x13, 16*FLEN/8, x15, x4, x9)

inst_9:
// rs1==x23, rs2==x16, rd==x7,fs1 == 0 and fe1 == 0x1a and fm1 == 0x33c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x23; op2:x16; dest:x7; op1val:0x6b3c; op2val:0x0;
   valaddr_reg:x13; val_offset:18*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x9
*/
TEST_FPRR_OP(fmul.h, x7, x23, x16, dyn, 128, 0, x13, 18*FLEN/8, x15, x4, x9)

inst_10:
// rs1==x10, rs2==x7, rd==x24,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x10; op2:x7; dest:x24; op1val:0x7aae; op2val:0x0;
   valaddr_reg:x13; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x9
*/
TEST_FPRR_OP(fmul.h, x24, x10, x7, dyn, 0, 0, x13, 20*FLEN/8, x15, x4, x9)

inst_11:
// rs1==x6, rs2==x24, rd==x29,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x6; op2:x24; dest:x29; op1val:0x7aae; op2val:0x0;
   valaddr_reg:x13; val_offset:22*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x9
*/
TEST_FPRR_OP(fmul.h, x29, x6, x24, dyn, 32, 0, x13, 22*FLEN/8, x15, x4, x9)

inst_12:
// rs1==x16, rs2==x18, rd==x14,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x16; op2:x18; dest:x14; op1val:0x7aae; op2val:0x0;
   valaddr_reg:x13; val_offset:24*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x9
*/
TEST_FPRR_OP(fmul.h, x14, x16, x18, dyn, 64, 0, x13, 24*FLEN/8, x15, x4, x9)

inst_13:
// rs1==x22, rs2==x11, rd==x12,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x22; op2:x11; dest:x12; op1val:0x7aae; op2val:0x0;
   valaddr_reg:x13; val_offset:26*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x9
*/
TEST_FPRR_OP(fmul.h, x12, x22, x11, dyn, 96, 0, x13, 26*FLEN/8, x15, x4, x9)
RVTEST_VALBASEUPD(x3,test_dataset_1)

inst_14:
// rs1==x25, rs2==x28, rd==x13,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x25; op2:x28; dest:x13; op1val:0x7aae; op2val:0x0;
   valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x9
*/
TEST_FPRR_OP(fmul.h, x13, x25, x28, dyn, 128, 0, x3, 0*FLEN/8, x7, x4, x9)

inst_15:
// rs1==x31, rs2==x12, rd==x10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x15a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x31; op2:x12; dest:x10; op1val:0x795a; op2val:0x0;
   valaddr_reg:x3; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6
*/
TEST_FPRR_OP(fmul.h, x10, x31, x12, dyn, 0, 0, x3, 2*FLEN/8, x7, x4, x6)

inst_16:
// rs1==x8, rs2==x23, rd==x17,fs1 == 0 and fe1 == 0x1e and fm1 == 0x15a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x8; op2:x23; dest:x17; op1val:0x795a; op2val:0x0;
   valaddr_reg:x3; val_offset:4*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6
*/
TEST_FPRR_OP(fmul.h, x17, x8, x23, dyn, 32, 0, x3, 4*FLEN/8, x7, x4, x6)
RVTEST_SIGBASE(x1,signature_x1_0)

inst_17:
// rs1==x18, rs2==x26, rd==x5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x15a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x18; op2:x26; dest:x5; op1val:0x795a; op2val:0x0;
   valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6
*/
TEST_FPRR_OP(fmul.h, x5, x18, x26, dyn, 64, 0, x3, 6*FLEN/8, x7, x1, x6)

inst_18:
// rs1==x24, rs2==x9, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x15a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x24; op2:x9; dest:x19; op1val:0x795a; op2val:0x0;
   valaddr_reg:x3; val_offset:8*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6
*/
TEST_FPRR_OP(fmul.h, x19, x24, x9, dyn, 96, 0, x3, 8*FLEN/8, x7, x1, x6)

inst_19:
// rs1==x4, rs2==x25, rd==x11,fs1 == 0 and fe1 == 0x1e and fm1 == 0x15a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x4; op2:x25; dest:x11; op1val:0x795a; op2val:0x0;
   valaddr_reg:x3; val_offset:10*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6
*/
TEST_FPRR_OP(fmul.h, x11, x4, x25, dyn, 128, 0, x3, 10*FLEN/8, x7, x1, x6)

inst_20:
// rs1==x28, rs2==x29, rd==x4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x28; op2:x29; dest:x4; op1val:0x78d8; op2val:0x0;
   valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6
*/
TEST_FPRR_OP(fmul.h, x4, x28, x29, dyn, 0, 0, x3, 12*FLEN/8, x7, x1, x6)

inst_21:
// rs1==x9, rs2==x4, rd==x31,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x9; op2:x4; dest:x31; op1val:0x78d8; op2val:0x0;
   valaddr_reg:x3; val_offset:14*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6
*/
TEST_FPRR_OP(fmul.h, x31, x9, x4, dyn, 32, 0, x3, 14*FLEN/8, x7, x1, x6)

inst_22:
// rs1==x14, rs2==x10, rd==x27,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x14; op2:x10; dest:x27; op1val:0x78d8; op2val:0x0;
   valaddr_reg:x3; val_offset:16*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6
*/
TEST_FPRR_OP(fmul.h, x27, x14, x10, dyn, 64, 0, x3, 16*FLEN/8, x7, x1, x6)

inst_23:
// rs1==x19, rs2==x21, rd==x9,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x19; op2:x21; dest:x9; op1val:0x78d8; op2val:0x0;
   valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6
*/
TEST_FPRR_OP(fmul.h, x9, x19, x21, dyn, 96, 0, x3, 18*FLEN/8, x7, x1, x6)

inst_24:
// rs1==x27, rs2==x0, rd==x2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x27; op2:x0; dest:x2; op1val:0x78d8; op2val:0x0;
   valaddr_reg:x3; val_offset:20*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6
*/
TEST_FPRR_OP(fmul.h, x2, x27, x0, dyn, 128, 0, x3, 20*FLEN/8, x7, x1, x6)

inst_25:
// rs1==x11, rs2==x27, rd==x16,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x11; op2:x27; dest:x16; op1val:0x78a5; op2val:0x0;
   valaddr_reg:x3; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6
*/
TEST_FPRR_OP(fmul.h, x16, x11, x27, dyn, 0, 0, x3, 22*FLEN/8, x7, x1, x6)
RVTEST_VALBASEUPD(x4,test_dataset_2)

inst_26:
// rs1==x13, rs2==x14, rd==x23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x13; op2:x14; dest:x23; op1val:0x78a5; op2val:0x0;
   valaddr_reg:x4; val_offset:0*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6
*/
TEST_FPRR_OP(fmul.h, x23, x13, x14, dyn, 32, 0, x4, 0*FLEN/8, x5, x1, x6)

inst_27:
// rs1==x29, rs2==x17, rd==x15,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x29; op2:x17; dest:x15; op1val:0x78a5; op2val:0x0;
   valaddr_reg:x4; val_offset:2*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6
*/
TEST_FPRR_OP(fmul.h, x15, x29, x17, dyn, 64, 0, x4, 2*FLEN/8, x5, x1, x6)

inst_28:
// rs1==x12, rs2==x15, rd==x3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x12; op2:x15; dest:x3; op1val:0x78a5; op2val:0x0;
   valaddr_reg:x4; val_offset:4*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6
*/
TEST_FPRR_OP(fmul.h, x3, x12, x15, dyn, 96, 0, x4, 4*FLEN/8, x5, x1, x6)

inst_29:
// rs1==x30, rs2==x19, rd==x6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x19; dest:x6; op1val:0x78a5; op2val:0x0;
   valaddr_reg:x4; val_offset:6*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x6, x30, x19, dyn, 128, 0, x4, 6*FLEN/8, x5, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_30:
// rs1==x15, rs2==x22, rd==x8,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x15; op2:x22; dest:x8; op1val:0x76e3; op2val:0x0;
   valaddr_reg:x4; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x8, x15, x22, dyn, 0, 0, x4, 8*FLEN/8, x5, x1, x2)

inst_31:
// rs1==x17, rs2==x13, rd==x18,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x17; op2:x13; dest:x18; op1val:0x76e3; op2val:0x0;
   valaddr_reg:x4; val_offset:10*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x18, x17, x13, dyn, 32, 0, x4, 10*FLEN/8, x5, x1, x2)

inst_32:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e3; op2val:0x0;
   valaddr_reg:x4; val_offset:12*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 12*FLEN/8, x5, x1, x2)

inst_33:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e3; op2val:0x0;
   valaddr_reg:x4; val_offset:14*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 14*FLEN/8, x5, x1, x2)

inst_34:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x76e3; op2val:0x0;
   valaddr_reg:x4; val_offset:16*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 16*FLEN/8, x5, x1, x2)

inst_35:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c8; op2val:0x0;
   valaddr_reg:x4; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 18*FLEN/8, x5, x1, x2)

inst_36:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c8; op2val:0x0;
   valaddr_reg:x4; val_offset:20*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 20*FLEN/8, x5, x1, x2)

inst_37:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c8; op2val:0x0;
   valaddr_reg:x4; val_offset:22*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 22*FLEN/8, x5, x1, x2)

inst_38:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c8; op2val:0x0;
   valaddr_reg:x4; val_offset:24*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 24*FLEN/8, x5, x1, x2)

inst_39:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c8; op2val:0x0;
   valaddr_reg:x4; val_offset:26*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 26*FLEN/8, x5, x1, x2)

inst_40:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0x0;
   valaddr_reg:x4; val_offset:28*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 28*FLEN/8, x5, x1, x2)

inst_41:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0x0;
   valaddr_reg:x4; val_offset:30*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 30*FLEN/8, x5, x1, x2)

inst_42:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0x0;
   valaddr_reg:x4; val_offset:32*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 32*FLEN/8, x5, x1, x2)

inst_43:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0x0;
   valaddr_reg:x4; val_offset:34*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 34*FLEN/8, x5, x1, x2)

inst_44:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0x0;
   valaddr_reg:x4; val_offset:36*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 36*FLEN/8, x5, x1, x2)

inst_45:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x771d; op2val:0x0;
   valaddr_reg:x4; val_offset:38*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 38*FLEN/8, x5, x1, x2)

inst_46:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x771d; op2val:0x0;
   valaddr_reg:x4; val_offset:40*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 40*FLEN/8, x5, x1, x2)

inst_47:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x771d; op2val:0x0;
   valaddr_reg:x4; val_offset:42*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 42*FLEN/8, x5, x1, x2)

inst_48:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x771d; op2val:0x0;
   valaddr_reg:x4; val_offset:44*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 44*FLEN/8, x5, x1, x2)

inst_49:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x771d; op2val:0x0;
   valaddr_reg:x4; val_offset:46*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 46*FLEN/8, x5, x1, x2)

inst_50:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x099 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6899; op2val:0x0;
   valaddr_reg:x4; val_offset:48*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 48*FLEN/8, x5, x1, x2)

inst_51:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x099 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6899; op2val:0x0;
   valaddr_reg:x4; val_offset:50*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 50*FLEN/8, x5, x1, x2)

inst_52:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x099 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6899; op2val:0x0;
   valaddr_reg:x4; val_offset:52*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 52*FLEN/8, x5, x1, x2)

inst_53:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x099 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6899; op2val:0x0;
   valaddr_reg:x4; val_offset:54*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 54*FLEN/8, x5, x1, x2)

inst_54:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x099 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x6899; op2val:0x0;
   valaddr_reg:x4; val_offset:56*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 56*FLEN/8, x5, x1, x2)

inst_55:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x36f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x776f; op2val:0x0;
   valaddr_reg:x4; val_offset:58*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 58*FLEN/8, x5, x1, x2)

inst_56:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x36f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x776f; op2val:0x0;
   valaddr_reg:x4; val_offset:60*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 60*FLEN/8, x5, x1, x2)

inst_57:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x36f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x776f; op2val:0x0;
   valaddr_reg:x4; val_offset:62*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 62*FLEN/8, x5, x1, x2)

inst_58:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x36f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x776f; op2val:0x0;
   valaddr_reg:x4; val_offset:64*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 64*FLEN/8, x5, x1, x2)

inst_59:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x36f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x776f; op2val:0x0;
   valaddr_reg:x4; val_offset:66*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 66*FLEN/8, x5, x1, x2)

inst_60:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x213 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7613; op2val:0x0;
   valaddr_reg:x4; val_offset:68*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 68*FLEN/8, x5, x1, x2)

inst_61:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x213 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7613; op2val:0x0;
   valaddr_reg:x4; val_offset:70*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 70*FLEN/8, x5, x1, x2)

inst_62:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x213 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7613; op2val:0x0;
   valaddr_reg:x4; val_offset:72*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 72*FLEN/8, x5, x1, x2)

inst_63:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x213 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7613; op2val:0x0;
   valaddr_reg:x4; val_offset:74*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 74*FLEN/8, x5, x1, x2)

inst_64:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x213 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7613; op2val:0x0;
   valaddr_reg:x4; val_offset:76*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 76*FLEN/8, x5, x1, x2)

inst_65:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x034 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7834; op2val:0x0;
   valaddr_reg:x4; val_offset:78*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 78*FLEN/8, x5, x1, x2)

inst_66:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x034 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7834; op2val:0x0;
   valaddr_reg:x4; val_offset:80*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 80*FLEN/8, x5, x1, x2)

inst_67:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x034 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7834; op2val:0x0;
   valaddr_reg:x4; val_offset:82*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 82*FLEN/8, x5, x1, x2)

inst_68:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x034 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7834; op2val:0x0;
   valaddr_reg:x4; val_offset:84*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 84*FLEN/8, x5, x1, x2)

inst_69:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x034 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7834; op2val:0x0;
   valaddr_reg:x4; val_offset:86*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 86*FLEN/8, x5, x1, x2)

inst_70:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x38d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x738d; op2val:0x0;
   valaddr_reg:x4; val_offset:88*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 88*FLEN/8, x5, x1, x2)

inst_71:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x38d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x738d; op2val:0x0;
   valaddr_reg:x4; val_offset:90*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 90*FLEN/8, x5, x1, x2)

inst_72:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x38d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x738d; op2val:0x0;
   valaddr_reg:x4; val_offset:92*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 92*FLEN/8, x5, x1, x2)

inst_73:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x38d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x738d; op2val:0x0;
   valaddr_reg:x4; val_offset:94*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 94*FLEN/8, x5, x1, x2)

inst_74:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x38d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x738d; op2val:0x0;
   valaddr_reg:x4; val_offset:96*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 96*FLEN/8, x5, x1, x2)

inst_75:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7533; op2val:0x0;
   valaddr_reg:x4; val_offset:98*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 98*FLEN/8, x5, x1, x2)

inst_76:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7533; op2val:0x0;
   valaddr_reg:x4; val_offset:100*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 100*FLEN/8, x5, x1, x2)

inst_77:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7533; op2val:0x0;
   valaddr_reg:x4; val_offset:102*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 102*FLEN/8, x5, x1, x2)

inst_78:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7533; op2val:0x0;
   valaddr_reg:x4; val_offset:104*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 104*FLEN/8, x5, x1, x2)

inst_79:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7533; op2val:0x0;
   valaddr_reg:x4; val_offset:106*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 106*FLEN/8, x5, x1, x2)

inst_80:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x014 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7814; op2val:0x0;
   valaddr_reg:x4; val_offset:108*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 108*FLEN/8, x5, x1, x2)

inst_81:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x014 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7814; op2val:0x0;
   valaddr_reg:x4; val_offset:110*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 110*FLEN/8, x5, x1, x2)

inst_82:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x014 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7814; op2val:0x0;
   valaddr_reg:x4; val_offset:112*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 112*FLEN/8, x5, x1, x2)

inst_83:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x014 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7814; op2val:0x0;
   valaddr_reg:x4; val_offset:114*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 114*FLEN/8, x5, x1, x2)

inst_84:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x014 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7814; op2val:0x0;
   valaddr_reg:x4; val_offset:116*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 116*FLEN/8, x5, x1, x2)

inst_85:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x164 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7964; op2val:0x0;
   valaddr_reg:x4; val_offset:118*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 118*FLEN/8, x5, x1, x2)

inst_86:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x164 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7964; op2val:0x0;
   valaddr_reg:x4; val_offset:120*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 120*FLEN/8, x5, x1, x2)

inst_87:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x164 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7964; op2val:0x0;
   valaddr_reg:x4; val_offset:122*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 122*FLEN/8, x5, x1, x2)

inst_88:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x164 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7964; op2val:0x0;
   valaddr_reg:x4; val_offset:124*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 124*FLEN/8, x5, x1, x2)

inst_89:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x164 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7964; op2val:0x0;
   valaddr_reg:x4; val_offset:126*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 126*FLEN/8, x5, x1, x2)

inst_90:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b25; op2val:0x0;
   valaddr_reg:x4; val_offset:128*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 128*FLEN/8, x5, x1, x2)

inst_91:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b25; op2val:0x0;
   valaddr_reg:x4; val_offset:130*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 130*FLEN/8, x5, x1, x2)

inst_92:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b25; op2val:0x0;
   valaddr_reg:x4; val_offset:132*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 132*FLEN/8, x5, x1, x2)

inst_93:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b25; op2val:0x0;
   valaddr_reg:x4; val_offset:134*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 134*FLEN/8, x5, x1, x2)

inst_94:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b25; op2val:0x0;
   valaddr_reg:x4; val_offset:136*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 136*FLEN/8, x5, x1, x2)

inst_95:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1df and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79df; op2val:0x0;
   valaddr_reg:x4; val_offset:138*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 138*FLEN/8, x5, x1, x2)

inst_96:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1df and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79df; op2val:0x0;
   valaddr_reg:x4; val_offset:140*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 140*FLEN/8, x5, x1, x2)

inst_97:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1df and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79df; op2val:0x0;
   valaddr_reg:x4; val_offset:142*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 142*FLEN/8, x5, x1, x2)

inst_98:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1df and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79df; op2val:0x0;
   valaddr_reg:x4; val_offset:144*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 144*FLEN/8, x5, x1, x2)

inst_99:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1df and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79df; op2val:0x0;
   valaddr_reg:x4; val_offset:146*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 146*FLEN/8, x5, x1, x2)

inst_100:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x219 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a19; op2val:0x0;
   valaddr_reg:x4; val_offset:148*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 148*FLEN/8, x5, x1, x2)

inst_101:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x219 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a19; op2val:0x0;
   valaddr_reg:x4; val_offset:150*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 150*FLEN/8, x5, x1, x2)

inst_102:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x219 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a19; op2val:0x0;
   valaddr_reg:x4; val_offset:152*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 152*FLEN/8, x5, x1, x2)

inst_103:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x219 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a19; op2val:0x0;
   valaddr_reg:x4; val_offset:154*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 154*FLEN/8, x5, x1, x2)

inst_104:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x219 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a19; op2val:0x0;
   valaddr_reg:x4; val_offset:156*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 156*FLEN/8, x5, x1, x2)

inst_105:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a8; op2val:0x1;
   valaddr_reg:x4; val_offset:158*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 158*FLEN/8, x5, x1, x2)

inst_106:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a8; op2val:0x1;
   valaddr_reg:x4; val_offset:160*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 160*FLEN/8, x5, x1, x2)

inst_107:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a8; op2val:0x1;
   valaddr_reg:x4; val_offset:162*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 162*FLEN/8, x5, x1, x2)

inst_108:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a8; op2val:0x1;
   valaddr_reg:x4; val_offset:164*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 164*FLEN/8, x5, x1, x2)

inst_109:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a8; op2val:0x1;
   valaddr_reg:x4; val_offset:166*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 166*FLEN/8, x5, x1, x2)

inst_110:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb1; op2val:0x8000;
   valaddr_reg:x4; val_offset:168*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 168*FLEN/8, x5, x1, x2)

inst_111:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb1; op2val:0x8000;
   valaddr_reg:x4; val_offset:170*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 170*FLEN/8, x5, x1, x2)

inst_112:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb1; op2val:0x8000;
   valaddr_reg:x4; val_offset:172*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 172*FLEN/8, x5, x1, x2)

inst_113:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb1; op2val:0x8000;
   valaddr_reg:x4; val_offset:174*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 174*FLEN/8, x5, x1, x2)

inst_114:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb1; op2val:0x8000;
   valaddr_reg:x4; val_offset:176*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 176*FLEN/8, x5, x1, x2)

inst_115:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x207 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a07; op2val:0x8000;
   valaddr_reg:x4; val_offset:178*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 178*FLEN/8, x5, x1, x2)

inst_116:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x207 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a07; op2val:0x8000;
   valaddr_reg:x4; val_offset:180*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 180*FLEN/8, x5, x1, x2)

inst_117:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x207 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a07; op2val:0x8000;
   valaddr_reg:x4; val_offset:182*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 182*FLEN/8, x5, x1, x2)

inst_118:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x207 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a07; op2val:0x8000;
   valaddr_reg:x4; val_offset:184*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 184*FLEN/8, x5, x1, x2)

inst_119:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x207 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a07; op2val:0x8000;
   valaddr_reg:x4; val_offset:186*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 186*FLEN/8, x5, x1, x2)

inst_120:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x361 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7761; op2val:0x8000;
   valaddr_reg:x4; val_offset:188*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 188*FLEN/8, x5, x1, x2)

inst_121:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x361 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7761; op2val:0x8000;
   valaddr_reg:x4; val_offset:190*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 190*FLEN/8, x5, x1, x2)

inst_122:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x361 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7761; op2val:0x8000;
   valaddr_reg:x4; val_offset:192*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 192*FLEN/8, x5, x1, x2)

inst_123:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x361 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7761; op2val:0x8000;
   valaddr_reg:x4; val_offset:194*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 194*FLEN/8, x5, x1, x2)

inst_124:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x361 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7761; op2val:0x8000;
   valaddr_reg:x4; val_offset:196*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 196*FLEN/8, x5, x1, x2)

inst_125:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d6; op2val:0x8000;
   valaddr_reg:x4; val_offset:198*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 198*FLEN/8, x5, x1, x2)

inst_126:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d6; op2val:0x8000;
   valaddr_reg:x4; val_offset:200*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 200*FLEN/8, x5, x1, x2)

inst_127:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d6; op2val:0x8000;
   valaddr_reg:x4; val_offset:202*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 202*FLEN/8, x5, x1, x2)

inst_128:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d6; op2val:0x8000;
   valaddr_reg:x4; val_offset:204*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 204*FLEN/8, x5, x1, x2)

inst_129:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d6; op2val:0x8000;
   valaddr_reg:x4; val_offset:206*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 206*FLEN/8, x5, x1, x2)

inst_130:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7801; op2val:0x8000;
   valaddr_reg:x4; val_offset:208*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 208*FLEN/8, x5, x1, x2)

inst_131:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7801; op2val:0x8000;
   valaddr_reg:x4; val_offset:210*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 210*FLEN/8, x5, x1, x2)

inst_132:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7801; op2val:0x8000;
   valaddr_reg:x4; val_offset:212*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 212*FLEN/8, x5, x1, x2)

inst_133:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7801; op2val:0x8000;
   valaddr_reg:x4; val_offset:214*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 214*FLEN/8, x5, x1, x2)

inst_134:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7801; op2val:0x8000;
   valaddr_reg:x4; val_offset:216*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 216*FLEN/8, x5, x1, x2)

inst_135:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a9; op2val:0x8000;
   valaddr_reg:x4; val_offset:218*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 218*FLEN/8, x5, x1, x2)

inst_136:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a9; op2val:0x8000;
   valaddr_reg:x4; val_offset:220*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 220*FLEN/8, x5, x1, x2)

inst_137:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a9; op2val:0x8000;
   valaddr_reg:x4; val_offset:222*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 222*FLEN/8, x5, x1, x2)

inst_138:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a9; op2val:0x8000;
   valaddr_reg:x4; val_offset:224*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 224*FLEN/8, x5, x1, x2)

inst_139:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x75a9; op2val:0x8000;
   valaddr_reg:x4; val_offset:226*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 226*FLEN/8, x5, x1, x2)

inst_140:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b31; op2val:0x8000;
   valaddr_reg:x4; val_offset:228*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 228*FLEN/8, x5, x1, x2)

inst_141:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b31; op2val:0x8000;
   valaddr_reg:x4; val_offset:230*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 230*FLEN/8, x5, x1, x2)

inst_142:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b31; op2val:0x8000;
   valaddr_reg:x4; val_offset:232*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 232*FLEN/8, x5, x1, x2)

inst_143:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b31; op2val:0x8000;
   valaddr_reg:x4; val_offset:234*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 234*FLEN/8, x5, x1, x2)

inst_144:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b31; op2val:0x8000;
   valaddr_reg:x4; val_offset:236*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 236*FLEN/8, x5, x1, x2)

inst_145:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x788a; op2val:0x8000;
   valaddr_reg:x4; val_offset:238*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 238*FLEN/8, x5, x1, x2)

inst_146:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x788a; op2val:0x8000;
   valaddr_reg:x4; val_offset:240*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 240*FLEN/8, x5, x1, x2)

inst_147:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x788a; op2val:0x8000;
   valaddr_reg:x4; val_offset:242*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 242*FLEN/8, x5, x1, x2)

inst_148:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x788a; op2val:0x8000;
   valaddr_reg:x4; val_offset:244*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 244*FLEN/8, x5, x1, x2)

inst_149:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x788a; op2val:0x8000;
   valaddr_reg:x4; val_offset:246*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 246*FLEN/8, x5, x1, x2)

inst_150:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c9; op2val:0x8000;
   valaddr_reg:x4; val_offset:248*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 248*FLEN/8, x5, x1, x2)

inst_151:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c9; op2val:0x8000;
   valaddr_reg:x4; val_offset:250*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 250*FLEN/8, x5, x1, x2)

inst_152:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c9; op2val:0x8000;
   valaddr_reg:x4; val_offset:252*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 252*FLEN/8, x5, x1, x2)

inst_153:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c9; op2val:0x8000;
   valaddr_reg:x4; val_offset:254*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 254*FLEN/8, x5, x1, x2)

inst_154:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c9; op2val:0x8000;
   valaddr_reg:x4; val_offset:256*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 256*FLEN/8, x5, x1, x2)

inst_155:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x318 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7318; op2val:0x8000;
   valaddr_reg:x4; val_offset:258*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 258*FLEN/8, x5, x1, x2)

inst_156:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x318 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7318; op2val:0x8000;
   valaddr_reg:x4; val_offset:260*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 260*FLEN/8, x5, x1, x2)

inst_157:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x318 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7318; op2val:0x8000;
   valaddr_reg:x4; val_offset:262*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 262*FLEN/8, x5, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_2)

inst_158:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x318 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7318; op2val:0x8000;
   valaddr_reg:x4; val_offset:264*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 264*FLEN/8, x5, x1, x2)

inst_159:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x318 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7318; op2val:0x8000;
   valaddr_reg:x4; val_offset:266*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 266*FLEN/8, x5, x1, x2)

inst_160:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x198 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7998; op2val:0x8000;
   valaddr_reg:x4; val_offset:268*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 268*FLEN/8, x5, x1, x2)

inst_161:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x198 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7998; op2val:0x8000;
   valaddr_reg:x4; val_offset:270*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 270*FLEN/8, x5, x1, x2)

inst_162:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x198 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7998; op2val:0x8000;
   valaddr_reg:x4; val_offset:272*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 272*FLEN/8, x5, x1, x2)

inst_163:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x198 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7998; op2val:0x8000;
   valaddr_reg:x4; val_offset:274*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 274*FLEN/8, x5, x1, x2)

inst_164:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x198 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7998; op2val:0x8000;
   valaddr_reg:x4; val_offset:276*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 276*FLEN/8, x5, x1, x2)

inst_165:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x342 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b42; op2val:0x8000;
   valaddr_reg:x4; val_offset:278*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 278*FLEN/8, x5, x1, x2)

inst_166:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x342 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b42; op2val:0x8000;
   valaddr_reg:x4; val_offset:280*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 280*FLEN/8, x5, x1, x2)

inst_167:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x342 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b42; op2val:0x8000;
   valaddr_reg:x4; val_offset:282*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 282*FLEN/8, x5, x1, x2)

inst_168:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x342 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b42; op2val:0x8000;
   valaddr_reg:x4; val_offset:284*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 284*FLEN/8, x5, x1, x2)

inst_169:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x342 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b42; op2val:0x8000;
   valaddr_reg:x4; val_offset:286*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 286*FLEN/8, x5, x1, x2)

inst_170:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x349 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b49; op2val:0x8000;
   valaddr_reg:x4; val_offset:288*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 288*FLEN/8, x5, x1, x2)

inst_171:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x349 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b49; op2val:0x8000;
   valaddr_reg:x4; val_offset:290*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 290*FLEN/8, x5, x1, x2)

inst_172:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x349 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b49; op2val:0x8000;
   valaddr_reg:x4; val_offset:292*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 292*FLEN/8, x5, x1, x2)

inst_173:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x349 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b49; op2val:0x8000;
   valaddr_reg:x4; val_offset:294*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 294*FLEN/8, x5, x1, x2)

inst_174:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x349 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b49; op2val:0x8000;
   valaddr_reg:x4; val_offset:296*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 296*FLEN/8, x5, x1, x2)

inst_175:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba7; op2val:0x8000;
   valaddr_reg:x4; val_offset:298*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 298*FLEN/8, x5, x1, x2)

inst_176:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba7; op2val:0x8000;
   valaddr_reg:x4; val_offset:300*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 300*FLEN/8, x5, x1, x2)

inst_177:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba7; op2val:0x8000;
   valaddr_reg:x4; val_offset:302*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 302*FLEN/8, x5, x1, x2)

inst_178:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba7; op2val:0x8000;
   valaddr_reg:x4; val_offset:304*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 304*FLEN/8, x5, x1, x2)

inst_179:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba7; op2val:0x8000;
   valaddr_reg:x4; val_offset:306*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 306*FLEN/8, x5, x1, x2)

inst_180:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x008 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7808; op2val:0x8000;
   valaddr_reg:x4; val_offset:308*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 308*FLEN/8, x5, x1, x2)

inst_181:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x008 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7808; op2val:0x8000;
   valaddr_reg:x4; val_offset:310*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 310*FLEN/8, x5, x1, x2)

inst_182:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x008 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7808; op2val:0x8000;
   valaddr_reg:x4; val_offset:312*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 312*FLEN/8, x5, x1, x2)

inst_183:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x008 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7808; op2val:0x8000;
   valaddr_reg:x4; val_offset:314*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 314*FLEN/8, x5, x1, x2)

inst_184:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x008 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7808; op2val:0x8000;
   valaddr_reg:x4; val_offset:316*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 316*FLEN/8, x5, x1, x2)

inst_185:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7935; op2val:0x8000;
   valaddr_reg:x4; val_offset:318*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 318*FLEN/8, x5, x1, x2)

inst_186:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7935; op2val:0x8000;
   valaddr_reg:x4; val_offset:320*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 320*FLEN/8, x5, x1, x2)

inst_187:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7935; op2val:0x8000;
   valaddr_reg:x4; val_offset:322*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 322*FLEN/8, x5, x1, x2)

inst_188:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7935; op2val:0x8000;
   valaddr_reg:x4; val_offset:324*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 324*FLEN/8, x5, x1, x2)

inst_189:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7935; op2val:0x8000;
   valaddr_reg:x4; val_offset:326*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 326*FLEN/8, x5, x1, x2)

inst_190:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x74fc; op2val:0x8000;
   valaddr_reg:x4; val_offset:328*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 328*FLEN/8, x5, x1, x2)

inst_191:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x74fc; op2val:0x8000;
   valaddr_reg:x4; val_offset:330*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 330*FLEN/8, x5, x1, x2)

inst_192:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x74fc; op2val:0x8000;
   valaddr_reg:x4; val_offset:332*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 332*FLEN/8, x5, x1, x2)

inst_193:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x74fc; op2val:0x8000;
   valaddr_reg:x4; val_offset:334*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 334*FLEN/8, x5, x1, x2)

inst_194:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x74fc; op2val:0x8000;
   valaddr_reg:x4; val_offset:336*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 336*FLEN/8, x5, x1, x2)

inst_195:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x017 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7817; op2val:0x8000;
   valaddr_reg:x4; val_offset:338*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 338*FLEN/8, x5, x1, x2)

inst_196:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x017 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7817; op2val:0x8000;
   valaddr_reg:x4; val_offset:340*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 340*FLEN/8, x5, x1, x2)

inst_197:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x017 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7817; op2val:0x8000;
   valaddr_reg:x4; val_offset:342*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 342*FLEN/8, x5, x1, x2)

inst_198:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x017 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7817; op2val:0x8000;
   valaddr_reg:x4; val_offset:344*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 344*FLEN/8, x5, x1, x2)

inst_199:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x017 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7817; op2val:0x8000;
   valaddr_reg:x4; val_offset:346*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 346*FLEN/8, x5, x1, x2)

inst_200:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78fb; op2val:0x8000;
   valaddr_reg:x4; val_offset:348*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 348*FLEN/8, x5, x1, x2)

inst_201:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78fb; op2val:0x8000;
   valaddr_reg:x4; val_offset:350*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 350*FLEN/8, x5, x1, x2)

inst_202:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78fb; op2val:0x8000;
   valaddr_reg:x4; val_offset:352*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 352*FLEN/8, x5, x1, x2)

inst_203:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78fb; op2val:0x8000;
   valaddr_reg:x4; val_offset:354*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 354*FLEN/8, x5, x1, x2)

inst_204:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78fb; op2val:0x8000;
   valaddr_reg:x4; val_offset:356*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 356*FLEN/8, x5, x1, x2)

inst_205:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a8f; op2val:0x8000;
   valaddr_reg:x4; val_offset:358*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 358*FLEN/8, x5, x1, x2)

inst_206:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a8f; op2val:0x8000;
   valaddr_reg:x4; val_offset:360*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 360*FLEN/8, x5, x1, x2)

inst_207:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a8f; op2val:0x8000;
   valaddr_reg:x4; val_offset:362*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 362*FLEN/8, x5, x1, x2)

inst_208:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a8f; op2val:0x8000;
   valaddr_reg:x4; val_offset:364*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 364*FLEN/8, x5, x1, x2)

inst_209:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a8f; op2val:0x8000;
   valaddr_reg:x4; val_offset:366*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 366*FLEN/8, x5, x1, x2)

inst_210:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x341 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b41; op2val:0x8000;
   valaddr_reg:x4; val_offset:368*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 368*FLEN/8, x5, x1, x2)

inst_211:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x341 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b41; op2val:0x8000;
   valaddr_reg:x4; val_offset:370*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 370*FLEN/8, x5, x1, x2)

inst_212:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x341 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b41; op2val:0x8000;
   valaddr_reg:x4; val_offset:372*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 372*FLEN/8, x5, x1, x2)

inst_213:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x341 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b41; op2val:0x8000;
   valaddr_reg:x4; val_offset:374*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 374*FLEN/8, x5, x1, x2)

inst_214:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x341 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b41; op2val:0x8000;
   valaddr_reg:x4; val_offset:376*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 376*FLEN/8, x5, x1, x2)

inst_215:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f4; op2val:0x8000;
   valaddr_reg:x4; val_offset:378*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 378*FLEN/8, x5, x1, x2)

inst_216:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f4; op2val:0x8000;
   valaddr_reg:x4; val_offset:380*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 380*FLEN/8, x5, x1, x2)

inst_217:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f4; op2val:0x8000;
   valaddr_reg:x4; val_offset:382*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 64, 0, x4, 382*FLEN/8, x5, x1, x2)

inst_218:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f4; op2val:0x8000;
   valaddr_reg:x4; val_offset:384*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 384*FLEN/8, x5, x1, x2)

inst_219:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f4; op2val:0x8000;
   valaddr_reg:x4; val_offset:386*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 386*FLEN/8, x5, x1, x2)

inst_220:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba5; op2val:0x0;
   valaddr_reg:x4; val_offset:388*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 0, 0, x4, 388*FLEN/8, x5, x1, x2)

inst_221:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba5; op2val:0x0;
   valaddr_reg:x4; val_offset:390*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 32, 0, x4, 390*FLEN/8, x5, x1, x2)

inst_222:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba5; op2val:0x0;
   valaddr_reg:x4; val_offset:392*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 96, 0, x4, 392*FLEN/8, x5, x1, x2)

inst_223:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fmul.h ; op1:x30; op2:x29; dest:x31; op1val:0x78d8; op2val:0x0;
   valaddr_reg:x4; val_offset:394*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, x31, x30, x29, dyn, 128, 0, x4, 394*FLEN/8, x5, x1, x2)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(31653,32,FLEN)
NAN_BOXED(31653,32,FLEN)
NAN_BOXED(31653,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(31653,32,FLEN)
NAN_BOXED(31653,32,FLEN)
NAN_BOXED(31653,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(27452,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(27452,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(27452,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(27452,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(27452,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(31406,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(31406,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(31406,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(31406,32,FLEN)
NAN_BOXED(0,32,FLEN)
test_dataset_1:
NAN_BOXED(31406,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(31066,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(31066,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(31066,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(31066,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(31066,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(30936,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(30936,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(30936,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(30936,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(30936,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(30885,32,FLEN)
NAN_BOXED(0,32,FLEN)
test_dataset_2:
NAN_BOXED(30885,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30885,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30885,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30885,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30435,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30435,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30435,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30435,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30435,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31176,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31176,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31176,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31176,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31176,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31639,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31639,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31639,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31639,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31639,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30493,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30493,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30493,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30493,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30493,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(26777,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(26777,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(26777,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(26777,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(26777,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30575,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30575,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30575,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30575,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30575,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30227,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30227,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30227,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30227,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30227,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30772,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30772,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30772,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30772,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30772,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(29581,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(29581,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(29581,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(29581,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(29581,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30003,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30003,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30003,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30003,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30003,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30740,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30740,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30740,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30740,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30740,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31076,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31076,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31076,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31076,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31076,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31525,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31525,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31525,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31525,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31525,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31199,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31199,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31199,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31199,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31199,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31257,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31257,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31257,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31257,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31257,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30120,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(30120,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(30120,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(30120,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(30120,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(31665,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31665,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31665,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31665,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31665,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31239,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31239,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31239,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31239,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31239,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(30561,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(30561,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(30561,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(30561,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(30561,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(30678,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(30678,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(30678,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(30678,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(30678,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(30721,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(30721,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(30721,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(30721,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(30721,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(30121,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(30121,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(30121,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(30121,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(30121,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31537,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31537,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31537,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31537,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31537,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(30858,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(30858,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(30858,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(30858,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(30858,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31177,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31177,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31177,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31177,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31177,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(29464,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(29464,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(29464,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(29464,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(29464,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31128,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31128,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31128,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31128,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31128,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31554,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31554,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31554,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31554,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31554,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31561,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31561,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31561,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31561,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31561,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31655,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31655,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31655,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31655,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31655,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(30728,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(30728,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(30728,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(30728,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(30728,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31029,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31029,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31029,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31029,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31029,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(29948,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(29948,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(29948,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(29948,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(29948,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(30743,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(30743,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(30743,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(30743,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(30743,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(30971,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(30971,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(30971,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(30971,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(30971,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31375,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31375,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31375,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31375,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31375,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31553,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31553,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31553,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31553,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31553,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31220,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31220,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31220,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31220,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31220,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31653,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31653,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31653,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30936,16,FLEN)
NAN_BOXED(0,16,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;



signature_x4_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x4_1:
    .fill 34*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_0:
    .fill 26*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_2:
    .fill 132*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;

mtrap_sigptr:
    .fill 64*XLEN/32,4,0xdeadbeef

tsig_end_canary:
CANARY;
#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif


sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
