
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.12.2
// timestamp : Wed Sep 25 04:10:09 2024 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fmadd.cgf \
 \
//                  -- xlen 32  \
//                  --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fmadd.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fmadd_b3 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fmadd_b3)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x9,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_0:
// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x27, rs2==x27, rs3==x1, rd==x11,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ee and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x27; op2:x27; op3:x1; dest:x11; op1val:0x78fb; op2val:0x78fb;
op3val:0x79ee; valaddr_reg:x9; val_offset:0*FLEN/8; rmval:dyn;
testreg:x4; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x11, x27, x27, x1, dyn, 0, 0, x9, 0*FLEN/8, x13, x1, x4)

inst_1:
// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x14, rs2==x17, rs3==x14, rd==x24,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ee and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x14; op2:x17; op3:x14; dest:x24; op1val:0x78fb; op2val:0xbcc3;
op3val:0x78fb; valaddr_reg:x9; val_offset:3*FLEN/8; rmval:dyn;
testreg:x4; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x24, x14, x17, x14, dyn, 32, 0, x9, 3*FLEN/8, x13, x1, x4)

inst_2:
// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x3, rs2==x25, rs3==x9, rd==x3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ee and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x3; op2:x25; op3:x9; dest:x3; op1val:0x78fb; op2val:0xbcc3;
op3val:0x79ee; valaddr_reg:x9; val_offset:6*FLEN/8; rmval:dyn;
testreg:x4; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x3, x3, x25, x9, dyn, 64, 0, x9, 6*FLEN/8, x13, x1, x4)

inst_3:
// rs1 == rs2 == rs3 != rd, rs1==x18, rs2==x18, rs3==x18, rd==x12,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ee and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x18; op2:x18; op3:x18; dest:x12; op1val:0x78fb; op2val:0x78fb;
op3val:0x78fb; valaddr_reg:x9; val_offset:9*FLEN/8; rmval:dyn;
testreg:x4; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x12, x18, x18, x18, dyn, 96, 0, x9, 9*FLEN/8, x13, x1, x4)

inst_4:
// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x5, rs2==x2, rs3==x7, rd==x7,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ee and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x5; op2:x2; op3:x7; dest:x7; op1val:0x78fb; op2val:0xbcc3;
op3val:0x79ee; valaddr_reg:x9; val_offset:12*FLEN/8; rmval:dyn;
testreg:x4; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x7, x5, x2, x7, dyn, 128, 0, x9, 12*FLEN/8, x13, x1, x4)

inst_5:
// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x15, rs2==x26, rs3==x24, rd==x26,fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0bd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x389 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x15; op2:x26; op3:x24; dest:x26; op1val:0x7a5b; op2val:0xbcbd;
op3val:0x7b89; valaddr_reg:x9; val_offset:15*FLEN/8; rmval:dyn;
testreg:x4; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x26, x15, x26, x24, dyn, 0, 0, x9, 15*FLEN/8, x13, x1, x4)

inst_6:
// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x28, rs2==x12, rs3==x29, rd==x10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0bd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x389 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x28; op2:x12; op3:x29; dest:x10; op1val:0x7a5b; op2val:0xbcbd;
op3val:0x7b89; valaddr_reg:x9; val_offset:18*FLEN/8; rmval:dyn;
testreg:x4; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x10, x28, x12, x29, dyn, 32, 0, x9, 18*FLEN/8, x13, x1, x4)

inst_7:
// rd == rs2 == rs3 != rs1, rs1==x23, rs2==x30, rs3==x30, rd==x30,fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0bd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x389 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x23; op2:x30; op3:x30; dest:x30; op1val:0x7a5b; op2val:0xbcbd;
op3val:0xbcbd; valaddr_reg:x9; val_offset:21*FLEN/8; rmval:dyn;
testreg:x4; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x30, x23, x30, x30, dyn, 64, 0, x9, 21*FLEN/8, x13, x1, x4)

inst_8:
// rs1 == rd == rs3 != rs2, rs1==x6, rs2==x22, rs3==x6, rd==x6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0bd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x389 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x6; op2:x22; op3:x6; dest:x6; op1val:0x7a5b; op2val:0xbcbd;
op3val:0x7a5b; valaddr_reg:x9; val_offset:24*FLEN/8; rmval:dyn;
testreg:x4; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x6, x6, x22, x6, dyn, 96, 0, x9, 24*FLEN/8, x13, x1, x4)

inst_9:
// rs1 == rs2 == rs3 == rd, rs1==x19, rs2==x19, rs3==x19, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0bd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x389 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x19; op2:x19; op3:x19; dest:x19; op1val:0x7a5b; op2val:0x7a5b;
op3val:0x7a5b; valaddr_reg:x9; val_offset:27*FLEN/8; rmval:dyn;
testreg:x4; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x19, x19, x19, x19, dyn, 128, 0, x9, 27*FLEN/8, x13, x1, x4)

inst_10:
// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x8, rs2==x20, rs3==x20, rd==x22,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0fc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x360 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x8; op2:x20; op3:x20; dest:x22; op1val:0x79ea; op2val:0xbcfc;
op3val:0xbcfc; valaddr_reg:x9; val_offset:30*FLEN/8; rmval:dyn;
testreg:x4; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x22, x8, x20, x20, dyn, 0, 0, x9, 30*FLEN/8, x13, x1, x4)
RVTEST_VALBASEUPD(x6,test_dataset_1)

inst_11:
// rs1 == rs2 == rd != rs3, rs1==x29, rs2==x29, rs3==x23, rd==x29,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0fc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x360 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x29; op2:x29; op3:x23; dest:x29; op1val:0x79ea; op2val:0x79ea;
op3val:0x7b60; valaddr_reg:x6; val_offset:0*FLEN/8; rmval:dyn;
testreg:x4; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x29, x29, x29, x23, dyn, 32, 0, x6, 0*FLEN/8, x10, x1, x4)

inst_12:
// rs1==x4, rs2==x23, rs3==x28, rd==x8,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0fc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x360 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x4; op2:x23; op3:x28; dest:x8; op1val:0x79ea; op2val:0xbcfc;
op3val:0x7b60; valaddr_reg:x6; val_offset:3*FLEN/8; rmval:dyn;
testreg:x12; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x8, x4, x23, x28, dyn, 64, 0, x6, 3*FLEN/8, x10, x1, x12)
RVTEST_SIGBASE(x3,signature_x3_0)

inst_13:
// rs1==x21, rs2==x0, rs3==x3, rd==x17,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0fc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x360 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x21; op2:x0; op3:x3; dest:x17; op1val:0x79ea; op2val:0x0;
op3val:0x7b60; valaddr_reg:x6; val_offset:6*FLEN/8; rmval:dyn;
testreg:x12; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x17, x21, x0, x3, dyn, 96, 0, x6, 6*FLEN/8, x10, x3, x12)

inst_14:
// rs1==x16, rs2==x28, rs3==x2, rd==x5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0fc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x360 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x16; op2:x28; op3:x2; dest:x5; op1val:0x79ea; op2val:0xbcfc;
op3val:0x7b60; valaddr_reg:x6; val_offset:9*FLEN/8; rmval:dyn;
testreg:x12; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x5, x16, x28, x2, dyn, 128, 0, x6, 9*FLEN/8, x10, x3, x12)

inst_15:
// rs1==x20, rs2==x8, rs3==x21, rd==x13,fs1 == 0 and fe1 == 0x19 and fm1 == 0x36c and fs2 == 1 and fe2 == 0x13 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x372 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x20; op2:x8; op3:x21; dest:x13; op1val:0x676c; op2val:0xcc02;
op3val:0x7772; valaddr_reg:x6; val_offset:12*FLEN/8; rmval:dyn;
testreg:x12; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x13, x20, x8, x21, dyn, 0, 0, x6, 12*FLEN/8, x10, x3, x12)

inst_16:
// rs1==x11, rs2==x14, rs3==x12, rd==x28,fs1 == 0 and fe1 == 0x19 and fm1 == 0x36c and fs2 == 1 and fe2 == 0x13 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x372 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x11; op2:x14; op3:x12; dest:x28; op1val:0x676c; op2val:0xcc02;
op3val:0x7772; valaddr_reg:x6; val_offset:15*FLEN/8; rmval:dyn;
testreg:x12; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x28, x11, x14, x12, dyn, 32, 0, x6, 15*FLEN/8, x10, x3, x12)

inst_17:
// rs1==x2, rs2==x16, rs3==x4, rd==x20,fs1 == 0 and fe1 == 0x19 and fm1 == 0x36c and fs2 == 1 and fe2 == 0x13 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x372 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x2; op2:x16; op3:x4; dest:x20; op1val:0x676c; op2val:0xcc02;
op3val:0x7772; valaddr_reg:x6; val_offset:18*FLEN/8; rmval:dyn;
testreg:x12; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x20, x2, x16, x4, dyn, 64, 0, x6, 18*FLEN/8, x10, x3, x12)

inst_18:
// rs1==x17, rs2==x21, rs3==x25, rd==x31,fs1 == 0 and fe1 == 0x19 and fm1 == 0x36c and fs2 == 1 and fe2 == 0x13 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x372 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x17; op2:x21; op3:x25; dest:x31; op1val:0x676c; op2val:0xcc02;
op3val:0x7772; valaddr_reg:x6; val_offset:21*FLEN/8; rmval:dyn;
testreg:x12; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x17, x21, x25, dyn, 96, 0, x6, 21*FLEN/8, x10, x3, x12)

inst_19:
// rs1==x30, rs2==x1, rs3==x31, rd==x16,fs1 == 0 and fe1 == 0x19 and fm1 == 0x36c and fs2 == 1 and fe2 == 0x13 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x372 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x1; op3:x31; dest:x16; op1val:0x676c; op2val:0xcc02;
op3val:0x7772; valaddr_reg:x6; val_offset:24*FLEN/8; rmval:dyn;
testreg:x12; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x16, x30, x1, x31, dyn, 128, 0, x6, 24*FLEN/8, x10, x3, x12)

inst_20:
// rs1==x31, rs2==x11, rs3==x17, rd==x0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x38b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x180 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x130 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x31; op2:x11; op3:x17; dest:x0; op1val:0x7b8b; op2val:0xb980;
op3val:0x7930; valaddr_reg:x6; val_offset:27*FLEN/8; rmval:dyn;
testreg:x12; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x0, x31, x11, x17, dyn, 0, 0, x6, 27*FLEN/8, x10, x3, x12)

inst_21:
// rs1==x13, rs2==x9, rs3==x8, rd==x25,fs1 == 0 and fe1 == 0x1e and fm1 == 0x38b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x180 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x130 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x13; op2:x9; op3:x8; dest:x25; op1val:0x7b8b; op2val:0xb980;
op3val:0x7930; valaddr_reg:x6; val_offset:30*FLEN/8; rmval:dyn;
testreg:x12; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x25, x13, x9, x8, dyn, 32, 0, x6, 30*FLEN/8, x10, x3, x12)

inst_22:
// rs1==x22, rs2==x5, rs3==x13, rd==x27,fs1 == 0 and fe1 == 0x1e and fm1 == 0x38b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x180 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x130 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x22; op2:x5; op3:x13; dest:x27; op1val:0x7b8b; op2val:0xb980;
op3val:0x7930; valaddr_reg:x6; val_offset:33*FLEN/8; rmval:dyn;
testreg:x12; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x27, x22, x5, x13, dyn, 64, 0, x6, 33*FLEN/8, x10, x3, x12)

inst_23:
// rs1==x7, rs2==x31, rs3==x15, rd==x9,fs1 == 0 and fe1 == 0x1e and fm1 == 0x38b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x180 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x130 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x7; op2:x31; op3:x15; dest:x9; op1val:0x7b8b; op2val:0xb980;
op3val:0x7930; valaddr_reg:x6; val_offset:36*FLEN/8; rmval:dyn;
testreg:x12; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x9, x7, x31, x15, dyn, 96, 0, x6, 36*FLEN/8, x10, x3, x12)
RVTEST_VALBASEUPD(x8,test_dataset_2)

inst_24:
// rs1==x24, rs2==x10, rs3==x26, rd==x23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x38b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x180 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x130 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x24; op2:x10; op3:x26; dest:x23; op1val:0x7b8b; op2val:0xb980;
op3val:0x7930; valaddr_reg:x8; val_offset:0*FLEN/8; rmval:dyn;
testreg:x12; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x23, x24, x10, x26, dyn, 128, 0, x8, 0*FLEN/8, x11, x3, x12)

inst_25:
// rs1==x25, rs2==x6, rs3==x27, rd==x18,fs1 == 0 and fe1 == 0x1e and fm1 == 0x334 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x005 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x33e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x25; op2:x6; op3:x27; dest:x18; op1val:0x7b34; op2val:0xb005;
op3val:0x6f3e; valaddr_reg:x8; val_offset:3*FLEN/8; rmval:dyn;
testreg:x12; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x18, x25, x6, x27, dyn, 0, 0, x8, 3*FLEN/8, x11, x3, x12)

inst_26:
// rs1==x9, rs2==x24, rs3==x16, rd==x14,fs1 == 0 and fe1 == 0x1e and fm1 == 0x334 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x005 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x33e and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x9; op2:x24; op3:x16; dest:x14; op1val:0x7b34; op2val:0xb005;
op3val:0x6f3e; valaddr_reg:x8; val_offset:6*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x14, x9, x24, x16, dyn, 32, 0, x8, 6*FLEN/8, x11, x3, x6)

inst_27:
// rs1==x26, rs2==x13, rs3==x10, rd==x15,fs1 == 0 and fe1 == 0x1e and fm1 == 0x334 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x005 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x33e and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x26; op2:x13; op3:x10; dest:x15; op1val:0x7b34; op2val:0xb005;
op3val:0x6f3e; valaddr_reg:x8; val_offset:9*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x15, x26, x13, x10, dyn, 64, 0, x8, 9*FLEN/8, x11, x3, x6)
RVTEST_SIGBASE(x5,signature_x5_0)

inst_28:
// rs1==x1, rs2==x15, rs3==x22, rd==x21,fs1 == 0 and fe1 == 0x1e and fm1 == 0x334 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x005 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x33e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x1; op2:x15; op3:x22; dest:x21; op1val:0x7b34; op2val:0xb005;
op3val:0x6f3e; valaddr_reg:x8; val_offset:12*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x21, x1, x15, x22, dyn, 96, 0, x8, 12*FLEN/8, x11, x5, x6)

inst_29:
// rs1==x12, rs2==x7, rs3==x0, rd==x1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x334 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x005 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x33e and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x12; op2:x7; op3:x0; dest:x1; op1val:0x7b34; op2val:0xb005;
op3val:0x0; valaddr_reg:x8; val_offset:15*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x1, x12, x7, x0, dyn, 128, 0, x8, 15*FLEN/8, x11, x5, x6)

inst_30:
// rs1==x0, rs2==x3, rs3==x11, rd==x2,fs1 == 0 and fe1 == 0x1d and fm1 == 0x380 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x034 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3e3 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x0; op2:x3; op3:x11; dest:x2; op1val:0x0; op2val:0xb834;
op3val:0x73e3; valaddr_reg:x8; val_offset:18*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x2, x0, x3, x11, dyn, 0, 0, x8, 18*FLEN/8, x11, x5, x6)

inst_31:
// rs1==x10,fs1 == 0 and fe1 == 0x1d and fm1 == 0x380 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x034 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3e3 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x10; op2:x26; op3:x30; dest:x13; op1val:0x7780; op2val:0xb834;
op3val:0x73e3; valaddr_reg:x8; val_offset:21*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x13, x10, x26, x30, dyn, 32, 0, x8, 21*FLEN/8, x11, x5, x6)

inst_32:
// rs2==x4,fs1 == 0 and fe1 == 0x1d and fm1 == 0x380 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x034 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3e3 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x31; op2:x4; op3:x14; dest:x17; op1val:0x7780; op2val:0xb834;
op3val:0x73e3; valaddr_reg:x8; val_offset:24*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x17, x31, x4, x14, dyn, 64, 0, x8, 24*FLEN/8, x11, x5, x6)

inst_33:
// rs3==x5,fs1 == 0 and fe1 == 0x1d and fm1 == 0x380 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x034 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3e3 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x7; op2:x28; op3:x5; dest:x12; op1val:0x7780; op2val:0xb834;
op3val:0x73e3; valaddr_reg:x8; val_offset:27*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x12, x7, x28, x5, dyn, 96, 0, x8, 27*FLEN/8, x11, x5, x6)

inst_34:
// rd==x4,fs1 == 0 and fe1 == 0x1d and fm1 == 0x380 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x034 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3e3 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x22; op2:x19; op3:x14; dest:x4; op1val:0x7780; op2val:0xb834;
op3val:0x73e3; valaddr_reg:x8; val_offset:30*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x4, x22, x19, x14, dyn, 128, 0, x8, 30*FLEN/8, x11, x5, x6)
RVTEST_VALBASEUPD(x1,test_dataset_3)

inst_35:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x059 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x038 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x096 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7859; op2val:0xbc38;
op3val:0x7896; valaddr_reg:x1; val_offset:0*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 0*FLEN/8, x2, x5, x6)

inst_36:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x059 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x038 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x096 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7859; op2val:0xbc38;
op3val:0x7896; valaddr_reg:x1; val_offset:3*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3*FLEN/8, x2, x5, x6)

inst_37:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x059 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x038 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x096 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7859; op2val:0xbc38;
op3val:0x7896; valaddr_reg:x1; val_offset:6*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 6*FLEN/8, x2, x5, x6)

inst_38:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x059 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x038 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x096 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7859; op2val:0xbc38;
op3val:0x7896; valaddr_reg:x1; val_offset:9*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 9*FLEN/8, x2, x5, x6)

inst_39:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x059 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x038 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x096 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7859; op2val:0xbc38;
op3val:0x7896; valaddr_reg:x1; val_offset:12*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 12*FLEN/8, x2, x5, x6)

inst_40:
// fs1 == 0 and fe1 == 0x18 and fm1 == 0x2b8 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x020 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2ee and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x62b8; op2val:0xcc20;
op3val:0x72ee; valaddr_reg:x1; val_offset:15*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 15*FLEN/8, x2, x5, x6)

inst_41:
// fs1 == 0 and fe1 == 0x18 and fm1 == 0x2b8 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x020 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2ee and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x62b8; op2val:0xcc20;
op3val:0x72ee; valaddr_reg:x1; val_offset:18*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 18*FLEN/8, x2, x5, x6)

inst_42:
// fs1 == 0 and fe1 == 0x18 and fm1 == 0x2b8 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x020 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2ee and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x62b8; op2val:0xcc20;
op3val:0x72ee; valaddr_reg:x1; val_offset:21*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 21*FLEN/8, x2, x5, x6)

inst_43:
// fs1 == 0 and fe1 == 0x18 and fm1 == 0x2b8 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x020 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2ee and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x62b8; op2val:0xcc20;
op3val:0x72ee; valaddr_reg:x1; val_offset:24*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 24*FLEN/8, x2, x5, x6)

inst_44:
// fs1 == 0 and fe1 == 0x18 and fm1 == 0x2b8 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x020 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2ee and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x62b8; op2val:0xcc20;
op3val:0x72ee; valaddr_reg:x1; val_offset:27*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 27*FLEN/8, x2, x5, x6)

inst_45:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x078 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x28e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x353 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7478; op2val:0xc28e;
op3val:0x7b53; valaddr_reg:x1; val_offset:30*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 30*FLEN/8, x2, x5, x6)

inst_46:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x078 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x28e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x353 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7478; op2val:0xc28e;
op3val:0x7b53; valaddr_reg:x1; val_offset:33*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 33*FLEN/8, x2, x5, x6)

inst_47:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x078 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x28e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x353 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7478; op2val:0xc28e;
op3val:0x7b53; valaddr_reg:x1; val_offset:36*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 36*FLEN/8, x2, x5, x6)

inst_48:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x078 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x28e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x353 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7478; op2val:0xc28e;
op3val:0x7b53; valaddr_reg:x1; val_offset:39*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 39*FLEN/8, x2, x5, x6)

inst_49:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x078 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x28e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x353 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7478; op2val:0xc28e;
op3val:0x7b53; valaddr_reg:x1; val_offset:42*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 42*FLEN/8, x2, x5, x6)

inst_50:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2ab and fs3 == 0 and fe3 == 0x1c and fm3 == 0x11a and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a1f; op2val:0xb2ab;
op3val:0x711a; valaddr_reg:x1; val_offset:45*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 45*FLEN/8, x2, x5, x6)

inst_51:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2ab and fs3 == 0 and fe3 == 0x1c and fm3 == 0x11a and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a1f; op2val:0xb2ab;
op3val:0x711a; valaddr_reg:x1; val_offset:48*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 48*FLEN/8, x2, x5, x6)

inst_52:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2ab and fs3 == 0 and fe3 == 0x1c and fm3 == 0x11a and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a1f; op2val:0xb2ab;
op3val:0x711a; valaddr_reg:x1; val_offset:51*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 51*FLEN/8, x2, x5, x6)

inst_53:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2ab and fs3 == 0 and fe3 == 0x1c and fm3 == 0x11a and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a1f; op2val:0xb2ab;
op3val:0x711a; valaddr_reg:x1; val_offset:54*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 54*FLEN/8, x2, x5, x6)

inst_54:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2ab and fs3 == 0 and fe3 == 0x1c and fm3 == 0x11a and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a1f; op2val:0xb2ab;
op3val:0x711a; valaddr_reg:x1; val_offset:57*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 57*FLEN/8, x2, x5, x6)

inst_55:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x192 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x070 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5f; op2val:0xb192;
op3val:0x7070; valaddr_reg:x1; val_offset:60*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 60*FLEN/8, x2, x5, x6)

inst_56:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x192 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x070 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5f; op2val:0xb192;
op3val:0x7070; valaddr_reg:x1; val_offset:63*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 63*FLEN/8, x2, x5, x6)

inst_57:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x192 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x070 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5f; op2val:0xb192;
op3val:0x7070; valaddr_reg:x1; val_offset:66*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 66*FLEN/8, x2, x5, x6)

inst_58:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x192 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x070 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5f; op2val:0xb192;
op3val:0x7070; valaddr_reg:x1; val_offset:69*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 69*FLEN/8, x2, x5, x6)

inst_59:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x192 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x070 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5f; op2val:0xb192;
op3val:0x7070; valaddr_reg:x1; val_offset:72*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 72*FLEN/8, x2, x5, x6)

inst_60:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ef and fs2 == 1 and fe2 == 0x0c and fm2 == 0x291 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x00d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ef; op2val:0xb291;
op3val:0x700d; valaddr_reg:x1; val_offset:75*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 75*FLEN/8, x2, x5, x6)

inst_61:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ef and fs2 == 1 and fe2 == 0x0c and fm2 == 0x291 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x00d and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ef; op2val:0xb291;
op3val:0x700d; valaddr_reg:x1; val_offset:78*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 78*FLEN/8, x2, x5, x6)

inst_62:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ef and fs2 == 1 and fe2 == 0x0c and fm2 == 0x291 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x00d and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ef; op2val:0xb291;
op3val:0x700d; valaddr_reg:x1; val_offset:81*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 81*FLEN/8, x2, x5, x6)

inst_63:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ef and fs2 == 1 and fe2 == 0x0c and fm2 == 0x291 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x00d and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ef; op2val:0xb291;
op3val:0x700d; valaddr_reg:x1; val_offset:84*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 84*FLEN/8, x2, x5, x6)

inst_64:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ef and fs2 == 1 and fe2 == 0x0c and fm2 == 0x291 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x00d and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ef; op2val:0xb291;
op3val:0x700d; valaddr_reg:x1; val_offset:87*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 87*FLEN/8, x2, x5, x6)

inst_65:
// fs1 == 0 and fe1 == 0x15 and fm1 == 0x354 and fs2 == 1 and fe2 == 0x17 and fm2 == 0x39b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f7 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5754; op2val:0xdf9b;
op3val:0x7af7; valaddr_reg:x1; val_offset:90*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 90*FLEN/8, x2, x5, x6)

inst_66:
// fs1 == 0 and fe1 == 0x15 and fm1 == 0x354 and fs2 == 1 and fe2 == 0x17 and fm2 == 0x39b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f7 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5754; op2val:0xdf9b;
op3val:0x7af7; valaddr_reg:x1; val_offset:93*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 93*FLEN/8, x2, x5, x6)

inst_67:
// fs1 == 0 and fe1 == 0x15 and fm1 == 0x354 and fs2 == 1 and fe2 == 0x17 and fm2 == 0x39b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f7 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5754; op2val:0xdf9b;
op3val:0x7af7; valaddr_reg:x1; val_offset:96*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 96*FLEN/8, x2, x5, x6)

inst_68:
// fs1 == 0 and fe1 == 0x15 and fm1 == 0x354 and fs2 == 1 and fe2 == 0x17 and fm2 == 0x39b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f7 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5754; op2val:0xdf9b;
op3val:0x7af7; valaddr_reg:x1; val_offset:99*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 99*FLEN/8, x2, x5, x6)

inst_69:
// fs1 == 0 and fe1 == 0x15 and fm1 == 0x354 and fs2 == 1 and fe2 == 0x17 and fm2 == 0x39b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f7 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5754; op2val:0xdf9b;
op3val:0x7af7; valaddr_reg:x1; val_offset:102*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 102*FLEN/8, x2, x5, x6)

inst_70:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2b3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2e4 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72b3; op2val:0xbc1d;
op3val:0x72e4; valaddr_reg:x1; val_offset:105*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 105*FLEN/8, x2, x5, x6)

inst_71:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2b3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2e4 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72b3; op2val:0xbc1d;
op3val:0x72e4; valaddr_reg:x1; val_offset:108*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 108*FLEN/8, x2, x5, x6)

inst_72:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2b3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2e4 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72b3; op2val:0xbc1d;
op3val:0x72e4; valaddr_reg:x1; val_offset:111*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 111*FLEN/8, x2, x5, x6)

inst_73:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2b3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2e4 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72b3; op2val:0xbc1d;
op3val:0x72e4; valaddr_reg:x1; val_offset:114*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 114*FLEN/8, x2, x5, x6)

inst_74:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2b3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2e4 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72b3; op2val:0xbc1d;
op3val:0x72e4; valaddr_reg:x1; val_offset:117*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 117*FLEN/8, x2, x5, x6)

inst_75:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3db and fs2 == 1 and fe2 == 0x0e and fm2 == 0x31a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f9 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bdb; op2val:0xbb1a;
op3val:0x7af9; valaddr_reg:x1; val_offset:120*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 120*FLEN/8, x2, x5, x6)

inst_76:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3db and fs2 == 1 and fe2 == 0x0e and fm2 == 0x31a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f9 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bdb; op2val:0xbb1a;
op3val:0x7af9; valaddr_reg:x1; val_offset:123*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 123*FLEN/8, x2, x5, x6)

inst_77:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3db and fs2 == 1 and fe2 == 0x0e and fm2 == 0x31a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f9 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bdb; op2val:0xbb1a;
op3val:0x7af9; valaddr_reg:x1; val_offset:126*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 126*FLEN/8, x2, x5, x6)

inst_78:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3db and fs2 == 1 and fe2 == 0x0e and fm2 == 0x31a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f9 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bdb; op2val:0xbb1a;
op3val:0x7af9; valaddr_reg:x1; val_offset:129*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 129*FLEN/8, x2, x5, x6)

inst_79:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3db and fs2 == 1 and fe2 == 0x0e and fm2 == 0x31a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f9 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bdb; op2val:0xbb1a;
op3val:0x7af9; valaddr_reg:x1; val_offset:132*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 132*FLEN/8, x2, x5, x6)

inst_80:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2a5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b0 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74a0; op2val:0xc2a5;
op3val:0x7bb0; valaddr_reg:x1; val_offset:135*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 135*FLEN/8, x2, x5, x6)

inst_81:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2a5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b0 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74a0; op2val:0xc2a5;
op3val:0x7bb0; valaddr_reg:x1; val_offset:138*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 138*FLEN/8, x2, x5, x6)

inst_82:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2a5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b0 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74a0; op2val:0xc2a5;
op3val:0x7bb0; valaddr_reg:x1; val_offset:141*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 141*FLEN/8, x2, x5, x6)

inst_83:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2a5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b0 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74a0; op2val:0xc2a5;
op3val:0x7bb0; valaddr_reg:x1; val_offset:144*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 144*FLEN/8, x2, x5, x6)

inst_84:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2a5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b0 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74a0; op2val:0xc2a5;
op3val:0x7bb0; valaddr_reg:x1; val_offset:147*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 147*FLEN/8, x2, x5, x6)

inst_85:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x107 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x16b and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784f; op2val:0xbd07;
op3val:0x796b; valaddr_reg:x1; val_offset:150*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 150*FLEN/8, x2, x5, x6)

inst_86:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x107 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x16b and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784f; op2val:0xbd07;
op3val:0x796b; valaddr_reg:x1; val_offset:153*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 153*FLEN/8, x2, x5, x6)

inst_87:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x107 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x16b and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784f; op2val:0xbd07;
op3val:0x796b; valaddr_reg:x1; val_offset:156*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 156*FLEN/8, x2, x5, x6)

inst_88:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x107 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x16b and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784f; op2val:0xbd07;
op3val:0x796b; valaddr_reg:x1; val_offset:159*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 159*FLEN/8, x2, x5, x6)

inst_89:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x107 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x16b and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784f; op2val:0xbd07;
op3val:0x796b; valaddr_reg:x1; val_offset:162*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 162*FLEN/8, x2, x5, x6)

inst_90:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x28c and fs2 == 1 and fe2 == 0x11 and fm2 == 0x098 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x386 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x728c; op2val:0xc498;
op3val:0x7b86; valaddr_reg:x1; val_offset:165*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 165*FLEN/8, x2, x5, x6)

inst_91:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x28c and fs2 == 1 and fe2 == 0x11 and fm2 == 0x098 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x386 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x728c; op2val:0xc498;
op3val:0x7b86; valaddr_reg:x1; val_offset:168*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 168*FLEN/8, x2, x5, x6)

inst_92:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x28c and fs2 == 1 and fe2 == 0x11 and fm2 == 0x098 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x386 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x728c; op2val:0xc498;
op3val:0x7b86; valaddr_reg:x1; val_offset:171*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 171*FLEN/8, x2, x5, x6)

inst_93:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x28c and fs2 == 1 and fe2 == 0x11 and fm2 == 0x098 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x386 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x728c; op2val:0xc498;
op3val:0x7b86; valaddr_reg:x1; val_offset:174*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 174*FLEN/8, x2, x5, x6)

inst_94:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x28c and fs2 == 1 and fe2 == 0x11 and fm2 == 0x098 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x386 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x728c; op2val:0xc498;
op3val:0x7b86; valaddr_reg:x1; val_offset:177*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 177*FLEN/8, x2, x5, x6)

inst_95:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x185 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x199 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ba and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7985; op2val:0xbd99;
op3val:0x7bba; valaddr_reg:x1; val_offset:180*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 180*FLEN/8, x2, x5, x6)

inst_96:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x185 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x199 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ba and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7985; op2val:0xbd99;
op3val:0x7bba; valaddr_reg:x1; val_offset:183*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 183*FLEN/8, x2, x5, x6)

inst_97:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x185 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x199 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ba and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7985; op2val:0xbd99;
op3val:0x7bba; valaddr_reg:x1; val_offset:186*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 186*FLEN/8, x2, x5, x6)

inst_98:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x185 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x199 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ba and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7985; op2val:0xbd99;
op3val:0x7bba; valaddr_reg:x1; val_offset:189*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 189*FLEN/8, x2, x5, x6)

inst_99:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x185 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x199 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ba and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7985; op2val:0xbd99;
op3val:0x7bba; valaddr_reg:x1; val_offset:192*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 192*FLEN/8, x2, x5, x6)

inst_100:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x159 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0c7 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b25; op2val:0xb559;
op3val:0x74c7; valaddr_reg:x1; val_offset:195*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 195*FLEN/8, x2, x5, x6)

inst_101:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x159 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0c7 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b25; op2val:0xb559;
op3val:0x74c7; valaddr_reg:x1; val_offset:198*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 198*FLEN/8, x2, x5, x6)

inst_102:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x159 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0c7 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b25; op2val:0xb559;
op3val:0x74c7; valaddr_reg:x1; val_offset:201*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 201*FLEN/8, x2, x5, x6)

inst_103:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x159 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0c7 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b25; op2val:0xb559;
op3val:0x74c7; valaddr_reg:x1; val_offset:204*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 204*FLEN/8, x2, x5, x6)

inst_104:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x159 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0c7 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b25; op2val:0xb559;
op3val:0x74c7; valaddr_reg:x1; val_offset:207*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 207*FLEN/8, x2, x5, x6)

inst_105:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c6 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x35a and fs3 == 0 and fe3 == 0x1c and fm3 == 0x14e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c6; op2val:0xb75a;
op3val:0x714e; valaddr_reg:x1; val_offset:210*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 210*FLEN/8, x2, x5, x6)

inst_106:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c6 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x35a and fs3 == 0 and fe3 == 0x1c and fm3 == 0x14e and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c6; op2val:0xb75a;
op3val:0x714e; valaddr_reg:x1; val_offset:213*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 213*FLEN/8, x2, x5, x6)

inst_107:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c6 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x35a and fs3 == 0 and fe3 == 0x1c and fm3 == 0x14e and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c6; op2val:0xb75a;
op3val:0x714e; valaddr_reg:x1; val_offset:216*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 216*FLEN/8, x2, x5, x6)

inst_108:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c6 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x35a and fs3 == 0 and fe3 == 0x1c and fm3 == 0x14e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c6; op2val:0xb75a;
op3val:0x714e; valaddr_reg:x1; val_offset:219*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 219*FLEN/8, x2, x5, x6)

inst_109:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c6 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x35a and fs3 == 0 and fe3 == 0x1c and fm3 == 0x14e and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c6; op2val:0xb75a;
op3val:0x714e; valaddr_reg:x1; val_offset:222*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 222*FLEN/8, x2, x5, x6)

inst_110:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0a9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x327 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x02a and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70a9; op2val:0xb727;
op3val:0x6c2a; valaddr_reg:x1; val_offset:225*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 225*FLEN/8, x2, x5, x6)

inst_111:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0a9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x327 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x02a and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70a9; op2val:0xb727;
op3val:0x6c2a; valaddr_reg:x1; val_offset:228*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 228*FLEN/8, x2, x5, x6)

inst_112:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0a9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x327 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x02a and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70a9; op2val:0xb727;
op3val:0x6c2a; valaddr_reg:x1; val_offset:231*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 231*FLEN/8, x2, x5, x6)

inst_113:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0a9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x327 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x02a and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70a9; op2val:0xb727;
op3val:0x6c2a; valaddr_reg:x1; val_offset:234*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 234*FLEN/8, x2, x5, x6)

inst_114:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0a9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x327 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x02a and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70a9; op2val:0xb727;
op3val:0x6c2a; valaddr_reg:x1; val_offset:237*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 237*FLEN/8, x2, x5, x6)

inst_115:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0d2 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74d1; op2val:0xc000;
op3val:0x78d2; valaddr_reg:x1; val_offset:240*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 240*FLEN/8, x2, x5, x6)

inst_116:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0d2 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74d1; op2val:0xc000;
op3val:0x78d2; valaddr_reg:x1; val_offset:243*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 243*FLEN/8, x2, x5, x6)

inst_117:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0d2 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74d1; op2val:0xc000;
op3val:0x78d2; valaddr_reg:x1; val_offset:246*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 246*FLEN/8, x2, x5, x6)

inst_118:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0d2 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74d1; op2val:0xc000;
op3val:0x78d2; valaddr_reg:x1; val_offset:249*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 249*FLEN/8, x2, x5, x6)

inst_119:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0d2 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74d1; op2val:0xc000;
op3val:0x78d2; valaddr_reg:x1; val_offset:252*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 252*FLEN/8, x2, x5, x6)

inst_120:
// fs1 == 0 and fe1 == 0x16 and fm1 == 0x2f4 and fs2 == 1 and fe2 == 0x16 and fm2 == 0x23b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x16b and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5af4; op2val:0xda3b;
op3val:0x796b; valaddr_reg:x1; val_offset:255*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 255*FLEN/8, x2, x5, x6)

inst_121:
// fs1 == 0 and fe1 == 0x16 and fm1 == 0x2f4 and fs2 == 1 and fe2 == 0x16 and fm2 == 0x23b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x16b and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5af4; op2val:0xda3b;
op3val:0x796b; valaddr_reg:x1; val_offset:258*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 258*FLEN/8, x2, x5, x6)

inst_122:
// fs1 == 0 and fe1 == 0x16 and fm1 == 0x2f4 and fs2 == 1 and fe2 == 0x16 and fm2 == 0x23b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x16b and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5af4; op2val:0xda3b;
op3val:0x796b; valaddr_reg:x1; val_offset:261*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 261*FLEN/8, x2, x5, x6)

inst_123:
// fs1 == 0 and fe1 == 0x16 and fm1 == 0x2f4 and fs2 == 1 and fe2 == 0x16 and fm2 == 0x23b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x16b and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5af4; op2val:0xda3b;
op3val:0x796b; valaddr_reg:x1; val_offset:264*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 264*FLEN/8, x2, x5, x6)

inst_124:
// fs1 == 0 and fe1 == 0x16 and fm1 == 0x2f4 and fs2 == 1 and fe2 == 0x16 and fm2 == 0x23b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x16b and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5af4; op2val:0xda3b;
op3val:0x796b; valaddr_reg:x1; val_offset:267*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 267*FLEN/8, x2, x5, x6)

inst_125:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x167 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x356 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0f5 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7567; op2val:0xbb56;
op3val:0x74f5; valaddr_reg:x1; val_offset:270*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 270*FLEN/8, x2, x5, x6)

inst_126:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x167 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x356 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0f5 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7567; op2val:0xbb56;
op3val:0x74f5; valaddr_reg:x1; val_offset:273*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 273*FLEN/8, x2, x5, x6)

inst_127:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x167 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x356 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0f5 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7567; op2val:0xbb56;
op3val:0x74f5; valaddr_reg:x1; val_offset:276*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 276*FLEN/8, x2, x5, x6)

inst_128:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x167 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x356 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0f5 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7567; op2val:0xbb56;
op3val:0x74f5; valaddr_reg:x1; val_offset:279*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 279*FLEN/8, x2, x5, x6)

inst_129:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x167 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x356 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0f5 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7567; op2val:0xbb56;
op3val:0x74f5; valaddr_reg:x1; val_offset:282*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 282*FLEN/8, x2, x5, x6)

inst_130:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0b2 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b0 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8b; op2val:0xb8b2;
op3val:0x77b0; valaddr_reg:x1; val_offset:285*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 285*FLEN/8, x2, x5, x6)

inst_131:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0b2 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b0 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8b; op2val:0xb8b2;
op3val:0x77b0; valaddr_reg:x1; val_offset:288*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 288*FLEN/8, x2, x5, x6)

inst_132:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0b2 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b0 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8b; op2val:0xb8b2;
op3val:0x77b0; valaddr_reg:x1; val_offset:291*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 291*FLEN/8, x2, x5, x6)

inst_133:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0b2 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b0 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8b; op2val:0xb8b2;
op3val:0x77b0; valaddr_reg:x1; val_offset:294*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 294*FLEN/8, x2, x5, x6)

inst_134:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0b2 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b0 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8b; op2val:0xb8b2;
op3val:0x77b0; valaddr_reg:x1; val_offset:297*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 297*FLEN/8, x2, x5, x6)

inst_135:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x218 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b2 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x750c; op2val:0xbe18;
op3val:0x77b2; valaddr_reg:x1; val_offset:300*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 300*FLEN/8, x2, x5, x6)

inst_136:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x218 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b2 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x750c; op2val:0xbe18;
op3val:0x77b2; valaddr_reg:x1; val_offset:303*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 303*FLEN/8, x2, x5, x6)

inst_137:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x218 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b2 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x750c; op2val:0xbe18;
op3val:0x77b2; valaddr_reg:x1; val_offset:306*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 306*FLEN/8, x2, x5, x6)

inst_138:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x218 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b2 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x750c; op2val:0xbe18;
op3val:0x77b2; valaddr_reg:x1; val_offset:309*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 309*FLEN/8, x2, x5, x6)

inst_139:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x218 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b2 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x750c; op2val:0xbe18;
op3val:0x77b2; valaddr_reg:x1; val_offset:312*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 312*FLEN/8, x2, x5, x6)

inst_140:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a2 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x12d and fs3 == 0 and fe3 == 0x1a and fm3 == 0x34b and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a2; op2val:0xad2d;
op3val:0x6b4b; valaddr_reg:x1; val_offset:315*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 315*FLEN/8, x2, x5, x6)

inst_141:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a2 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x12d and fs3 == 0 and fe3 == 0x1a and fm3 == 0x34b and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a2; op2val:0xad2d;
op3val:0x6b4b; valaddr_reg:x1; val_offset:318*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 318*FLEN/8, x2, x5, x6)

inst_142:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a2 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x12d and fs3 == 0 and fe3 == 0x1a and fm3 == 0x34b and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a2; op2val:0xad2d;
op3val:0x6b4b; valaddr_reg:x1; val_offset:321*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 321*FLEN/8, x2, x5, x6)

inst_143:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a2 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x12d and fs3 == 0 and fe3 == 0x1a and fm3 == 0x34b and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a2; op2val:0xad2d;
op3val:0x6b4b; valaddr_reg:x1; val_offset:324*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 324*FLEN/8, x2, x5, x6)

inst_144:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a2 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x12d and fs3 == 0 and fe3 == 0x1a and fm3 == 0x34b and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a2; op2val:0xad2d;
op3val:0x6b4b; valaddr_reg:x1; val_offset:327*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 327*FLEN/8, x2, x5, x6)

inst_145:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3cc and fs2 == 1 and fe2 == 0x09 and fm2 == 0x201 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x1da and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bcc; op2val:0xa601;
op3val:0x65da; valaddr_reg:x1; val_offset:330*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 330*FLEN/8, x2, x5, x6)

inst_146:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3cc and fs2 == 1 and fe2 == 0x09 and fm2 == 0x201 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x1da and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bcc; op2val:0xa601;
op3val:0x65da; valaddr_reg:x1; val_offset:333*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 333*FLEN/8, x2, x5, x6)

inst_147:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3cc and fs2 == 1 and fe2 == 0x09 and fm2 == 0x201 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x1da and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bcc; op2val:0xa601;
op3val:0x65da; valaddr_reg:x1; val_offset:336*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 336*FLEN/8, x2, x5, x6)

inst_148:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3cc and fs2 == 1 and fe2 == 0x09 and fm2 == 0x201 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x1da and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bcc; op2val:0xa601;
op3val:0x65da; valaddr_reg:x1; val_offset:339*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 339*FLEN/8, x2, x5, x6)

inst_149:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3cc and fs2 == 1 and fe2 == 0x09 and fm2 == 0x201 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x1da and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bcc; op2val:0xa601;
op3val:0x65da; valaddr_reg:x1; val_offset:342*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 342*FLEN/8, x2, x5, x6)

inst_150:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x081 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2c1 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79fe; op2val:0xbc81;
op3val:0x7ac1; valaddr_reg:x1; val_offset:345*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 345*FLEN/8, x2, x5, x6)

inst_151:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x081 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2c1 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79fe; op2val:0xbc81;
op3val:0x7ac1; valaddr_reg:x1; val_offset:348*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 348*FLEN/8, x2, x5, x6)

inst_152:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x081 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2c1 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79fe; op2val:0xbc81;
op3val:0x7ac1; valaddr_reg:x1; val_offset:351*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 351*FLEN/8, x2, x5, x6)

inst_153:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x081 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2c1 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79fe; op2val:0xbc81;
op3val:0x7ac1; valaddr_reg:x1; val_offset:354*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 354*FLEN/8, x2, x5, x6)

inst_154:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x081 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2c1 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79fe; op2val:0xbc81;
op3val:0x7ac1; valaddr_reg:x1; val_offset:357*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 357*FLEN/8, x2, x5, x6)

inst_155:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x172 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x24c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x64a0; op2val:0xd172;
op3val:0x7a4c; valaddr_reg:x1; val_offset:360*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 360*FLEN/8, x2, x5, x6)
RVTEST_SIGBASE(x5,signature_x5_1)

inst_156:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x172 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x24c and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x64a0; op2val:0xd172;
op3val:0x7a4c; valaddr_reg:x1; val_offset:363*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 363*FLEN/8, x2, x5, x6)

inst_157:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x172 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x24c and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x64a0; op2val:0xd172;
op3val:0x7a4c; valaddr_reg:x1; val_offset:366*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 366*FLEN/8, x2, x5, x6)

inst_158:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x172 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x24c and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x64a0; op2val:0xd172;
op3val:0x7a4c; valaddr_reg:x1; val_offset:369*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 369*FLEN/8, x2, x5, x6)

inst_159:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x172 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x24c and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x64a0; op2val:0xd172;
op3val:0x7a4c; valaddr_reg:x1; val_offset:372*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 372*FLEN/8, x2, x5, x6)

inst_160:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1db and fs2 == 1 and fe2 == 0x0f and fm2 == 0x251 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a0 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75db; op2val:0xbe51;
op3val:0x78a0; valaddr_reg:x1; val_offset:375*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 375*FLEN/8, x2, x5, x6)

inst_161:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1db and fs2 == 1 and fe2 == 0x0f and fm2 == 0x251 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a0 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75db; op2val:0xbe51;
op3val:0x78a0; valaddr_reg:x1; val_offset:378*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 378*FLEN/8, x2, x5, x6)

inst_162:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1db and fs2 == 1 and fe2 == 0x0f and fm2 == 0x251 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a0 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75db; op2val:0xbe51;
op3val:0x78a0; valaddr_reg:x1; val_offset:381*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 381*FLEN/8, x2, x5, x6)

inst_163:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1db and fs2 == 1 and fe2 == 0x0f and fm2 == 0x251 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a0 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75db; op2val:0xbe51;
op3val:0x78a0; valaddr_reg:x1; val_offset:384*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 384*FLEN/8, x2, x5, x6)

inst_164:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1db and fs2 == 1 and fe2 == 0x0f and fm2 == 0x251 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a0 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75db; op2val:0xbe51;
op3val:0x78a0; valaddr_reg:x1; val_offset:387*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 387*FLEN/8, x2, x5, x6)

inst_165:
// fs1 == 0 and fe1 == 0x18 and fm1 == 0x0a7 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x123 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1fa and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x60a7; op2val:0xc523;
op3val:0x69fa; valaddr_reg:x1; val_offset:390*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 390*FLEN/8, x2, x5, x6)

inst_166:
// fs1 == 0 and fe1 == 0x18 and fm1 == 0x0a7 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x123 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1fa and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x60a7; op2val:0xc523;
op3val:0x69fa; valaddr_reg:x1; val_offset:393*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 393*FLEN/8, x2, x5, x6)

inst_167:
// fs1 == 0 and fe1 == 0x18 and fm1 == 0x0a7 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x123 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1fa and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x60a7; op2val:0xc523;
op3val:0x69fa; valaddr_reg:x1; val_offset:396*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 396*FLEN/8, x2, x5, x6)

inst_168:
// fs1 == 0 and fe1 == 0x18 and fm1 == 0x0a7 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x123 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1fa and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x60a7; op2val:0xc523;
op3val:0x69fa; valaddr_reg:x1; val_offset:399*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 399*FLEN/8, x2, x5, x6)

inst_169:
// fs1 == 0 and fe1 == 0x18 and fm1 == 0x0a7 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x123 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1fa and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x60a7; op2val:0xc523;
op3val:0x69fa; valaddr_reg:x1; val_offset:402*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 402*FLEN/8, x2, x5, x6)

inst_170:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1c9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x147 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3a3 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71c9; op2val:0xc547;
op3val:0x7ba3; valaddr_reg:x1; val_offset:405*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 405*FLEN/8, x2, x5, x6)

inst_171:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1c9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x147 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3a3 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71c9; op2val:0xc547;
op3val:0x7ba3; valaddr_reg:x1; val_offset:408*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 408*FLEN/8, x2, x5, x6)

inst_172:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1c9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x147 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3a3 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71c9; op2val:0xc547;
op3val:0x7ba3; valaddr_reg:x1; val_offset:411*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 411*FLEN/8, x2, x5, x6)

inst_173:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1c9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x147 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3a3 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71c9; op2val:0xc547;
op3val:0x7ba3; valaddr_reg:x1; val_offset:414*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 414*FLEN/8, x2, x5, x6)

inst_174:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1c9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x147 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3a3 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71c9; op2val:0xc547;
op3val:0x7ba3; valaddr_reg:x1; val_offset:417*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 417*FLEN/8, x2, x5, x6)

inst_175:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x249 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3b0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x20b and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7249; op2val:0xc3b0;
op3val:0x7a0b; valaddr_reg:x1; val_offset:420*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 420*FLEN/8, x2, x5, x6)

inst_176:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x249 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3b0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x20b and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7249; op2val:0xc3b0;
op3val:0x7a0b; valaddr_reg:x1; val_offset:423*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 423*FLEN/8, x2, x5, x6)

inst_177:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x249 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3b0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x20b and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7249; op2val:0xc3b0;
op3val:0x7a0b; valaddr_reg:x1; val_offset:426*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 426*FLEN/8, x2, x5, x6)

inst_178:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x249 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3b0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x20b and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7249; op2val:0xc3b0;
op3val:0x7a0b; valaddr_reg:x1; val_offset:429*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 429*FLEN/8, x2, x5, x6)

inst_179:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x249 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3b0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x20b and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7249; op2val:0xc3b0;
op3val:0x7a0b; valaddr_reg:x1; val_offset:432*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 432*FLEN/8, x2, x5, x6)

inst_180:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x36f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x388 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b6f; op2val:0xbc0d;
op3val:0x7b88; valaddr_reg:x1; val_offset:435*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 435*FLEN/8, x2, x5, x6)

inst_181:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x36f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x388 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b6f; op2val:0xbc0d;
op3val:0x7b88; valaddr_reg:x1; val_offset:438*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 438*FLEN/8, x2, x5, x6)

inst_182:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x36f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x388 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b6f; op2val:0xbc0d;
op3val:0x7b88; valaddr_reg:x1; val_offset:441*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 441*FLEN/8, x2, x5, x6)

inst_183:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x36f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x388 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b6f; op2val:0xbc0d;
op3val:0x7b88; valaddr_reg:x1; val_offset:444*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 444*FLEN/8, x2, x5, x6)

inst_184:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x36f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x388 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b6f; op2val:0xbc0d;
op3val:0x7b88; valaddr_reg:x1; val_offset:447*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 447*FLEN/8, x2, x5, x6)

inst_185:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x181 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1ac and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7581; op2val:0xbc1e;
op3val:0x75ac; valaddr_reg:x1; val_offset:450*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 450*FLEN/8, x2, x5, x6)

inst_186:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x181 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1ac and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7581; op2val:0xbc1e;
op3val:0x75ac; valaddr_reg:x1; val_offset:453*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 453*FLEN/8, x2, x5, x6)

inst_187:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x181 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1ac and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7581; op2val:0xbc1e;
op3val:0x75ac; valaddr_reg:x1; val_offset:456*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 456*FLEN/8, x2, x5, x6)

inst_188:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x181 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1ac and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7581; op2val:0xbc1e;
op3val:0x75ac; valaddr_reg:x1; val_offset:459*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 459*FLEN/8, x2, x5, x6)

inst_189:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x181 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1ac and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7581; op2val:0xbc1e;
op3val:0x75ac; valaddr_reg:x1; val_offset:462*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 462*FLEN/8, x2, x5, x6)

inst_190:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x032 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x233 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7832; op2val:0xbde9;
op3val:0x7a33; valaddr_reg:x1; val_offset:465*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 465*FLEN/8, x2, x5, x6)

inst_191:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x032 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x233 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7832; op2val:0xbde9;
op3val:0x7a33; valaddr_reg:x1; val_offset:468*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 468*FLEN/8, x2, x5, x6)

inst_192:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x032 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x233 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7832; op2val:0xbde9;
op3val:0x7a33; valaddr_reg:x1; val_offset:471*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 471*FLEN/8, x2, x5, x6)

inst_193:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x032 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x233 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7832; op2val:0xbde9;
op3val:0x7a33; valaddr_reg:x1; val_offset:474*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 474*FLEN/8, x2, x5, x6)

inst_194:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x032 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x233 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7832; op2val:0xbde9;
op3val:0x7a33; valaddr_reg:x1; val_offset:477*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 477*FLEN/8, x2, x5, x6)

inst_195:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2e9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2ec and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1fb and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ee9; op2val:0xc6ec;
op3val:0x79fb; valaddr_reg:x1; val_offset:480*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 480*FLEN/8, x2, x5, x6)

inst_196:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2e9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2ec and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1fb and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ee9; op2val:0xc6ec;
op3val:0x79fb; valaddr_reg:x1; val_offset:483*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 483*FLEN/8, x2, x5, x6)

inst_197:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2e9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2ec and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1fb and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ee9; op2val:0xc6ec;
op3val:0x79fb; valaddr_reg:x1; val_offset:486*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 486*FLEN/8, x2, x5, x6)

inst_198:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2e9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2ec and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1fb and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ee9; op2val:0xc6ec;
op3val:0x79fb; valaddr_reg:x1; val_offset:489*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 489*FLEN/8, x2, x5, x6)

inst_199:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2e9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2ec and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1fb and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ee9; op2val:0xc6ec;
op3val:0x79fb; valaddr_reg:x1; val_offset:492*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 492*FLEN/8, x2, x5, x6)

inst_200:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x050 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2df and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5f; op2val:0xbc50;
op3val:0x7adf; valaddr_reg:x1; val_offset:495*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 495*FLEN/8, x2, x5, x6)

inst_201:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x050 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2df and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5f; op2val:0xbc50;
op3val:0x7adf; valaddr_reg:x1; val_offset:498*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 498*FLEN/8, x2, x5, x6)

inst_202:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x050 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2df and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5f; op2val:0xbc50;
op3val:0x7adf; valaddr_reg:x1; val_offset:501*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 501*FLEN/8, x2, x5, x6)

inst_203:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x050 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2df and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5f; op2val:0xbc50;
op3val:0x7adf; valaddr_reg:x1; val_offset:504*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 504*FLEN/8, x2, x5, x6)

inst_204:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x050 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2df and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5f; op2val:0xbc50;
op3val:0x7adf; valaddr_reg:x1; val_offset:507*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 507*FLEN/8, x2, x5, x6)

inst_205:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x0b0 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x273 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x390 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x68b0; op2val:0xce73;
op3val:0x7b90; valaddr_reg:x1; val_offset:510*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 510*FLEN/8, x2, x5, x6)

inst_206:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x0b0 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x273 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x390 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x68b0; op2val:0xce73;
op3val:0x7b90; valaddr_reg:x1; val_offset:513*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 513*FLEN/8, x2, x5, x6)

inst_207:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x0b0 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x273 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x390 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x68b0; op2val:0xce73;
op3val:0x7b90; valaddr_reg:x1; val_offset:516*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 516*FLEN/8, x2, x5, x6)

inst_208:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x0b0 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x273 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x390 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x68b0; op2val:0xce73;
op3val:0x7b90; valaddr_reg:x1; val_offset:519*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 519*FLEN/8, x2, x5, x6)

inst_209:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x0b0 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x273 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x390 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x68b0; op2val:0xce73;
op3val:0x7b90; valaddr_reg:x1; val_offset:522*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 522*FLEN/8, x2, x5, x6)

inst_210:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x379 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x173 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dd5; op2val:0xc379;
op3val:0x7573; valaddr_reg:x1; val_offset:525*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 525*FLEN/8, x2, x5, x6)

inst_211:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x379 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x173 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dd5; op2val:0xc379;
op3val:0x7573; valaddr_reg:x1; val_offset:528*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 528*FLEN/8, x2, x5, x6)

inst_212:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x379 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x173 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dd5; op2val:0xc379;
op3val:0x7573; valaddr_reg:x1; val_offset:531*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 531*FLEN/8, x2, x5, x6)

inst_213:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x379 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x173 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dd5; op2val:0xc379;
op3val:0x7573; valaddr_reg:x1; val_offset:534*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 534*FLEN/8, x2, x5, x6)

inst_214:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x379 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x173 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dd5; op2val:0xc379;
op3val:0x7573; valaddr_reg:x1; val_offset:537*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 537*FLEN/8, x2, x5, x6)

inst_215:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e2 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x203 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x357 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e2; op2val:0xbe03;
op3val:0x7b57; valaddr_reg:x1; val_offset:540*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 540*FLEN/8, x2, x5, x6)

inst_216:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e2 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x203 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x357 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e2; op2val:0xbe03;
op3val:0x7b57; valaddr_reg:x1; val_offset:543*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 543*FLEN/8, x2, x5, x6)

inst_217:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e2 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x203 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x357 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e2; op2val:0xbe03;
op3val:0x7b57; valaddr_reg:x1; val_offset:546*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 546*FLEN/8, x2, x5, x6)

inst_218:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e2 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x203 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x357 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e2; op2val:0xbe03;
op3val:0x7b57; valaddr_reg:x1; val_offset:549*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 549*FLEN/8, x2, x5, x6)

inst_219:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e2 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x203 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x357 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e2; op2val:0xbe03;
op3val:0x7b57; valaddr_reg:x1; val_offset:552*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 552*FLEN/8, x2, x5, x6)

inst_220:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x16f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x363 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x756f; op2val:0xc16f;
op3val:0x7b63; valaddr_reg:x1; val_offset:555*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 555*FLEN/8, x2, x5, x6)

inst_221:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x16f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x363 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x756f; op2val:0xc16f;
op3val:0x7b63; valaddr_reg:x1; val_offset:558*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 558*FLEN/8, x2, x5, x6)

inst_222:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x16f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x363 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x756f; op2val:0xc16f;
op3val:0x7b63; valaddr_reg:x1; val_offset:561*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 561*FLEN/8, x2, x5, x6)

inst_223:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x16f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x363 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x756f; op2val:0xc16f;
op3val:0x7b63; valaddr_reg:x1; val_offset:564*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 564*FLEN/8, x2, x5, x6)

inst_224:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x16f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x363 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x756f; op2val:0xc16f;
op3val:0x7b63; valaddr_reg:x1; val_offset:567*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 567*FLEN/8, x2, x5, x6)

inst_225:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x095 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x785b; op2val:0xb895;
op3val:0x74ff; valaddr_reg:x1; val_offset:570*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 570*FLEN/8, x2, x5, x6)

inst_226:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x095 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0ff and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x785b; op2val:0xb895;
op3val:0x74ff; valaddr_reg:x1; val_offset:573*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 573*FLEN/8, x2, x5, x6)

inst_227:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x095 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0ff and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x785b; op2val:0xb895;
op3val:0x74ff; valaddr_reg:x1; val_offset:576*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 576*FLEN/8, x2, x5, x6)

inst_228:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x095 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0ff and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x785b; op2val:0xb895;
op3val:0x74ff; valaddr_reg:x1; val_offset:579*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 579*FLEN/8, x2, x5, x6)

inst_229:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x095 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0ff and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x785b; op2val:0xb895;
op3val:0x74ff; valaddr_reg:x1; val_offset:582*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 582*FLEN/8, x2, x5, x6)

inst_230:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x111 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x07b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1ad and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7511; op2val:0xb87b;
op3val:0x71ad; valaddr_reg:x1; val_offset:585*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 585*FLEN/8, x2, x5, x6)

inst_231:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x111 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x07b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1ad and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7511; op2val:0xb87b;
op3val:0x71ad; valaddr_reg:x1; val_offset:588*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 588*FLEN/8, x2, x5, x6)

inst_232:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x111 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x07b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1ad and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7511; op2val:0xb87b;
op3val:0x71ad; valaddr_reg:x1; val_offset:591*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 591*FLEN/8, x2, x5, x6)

inst_233:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x111 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x07b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1ad and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7511; op2val:0xb87b;
op3val:0x71ad; valaddr_reg:x1; val_offset:594*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 594*FLEN/8, x2, x5, x6)

inst_234:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x111 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x07b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1ad and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7511; op2val:0xb87b;
op3val:0x71ad; valaddr_reg:x1; val_offset:597*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 597*FLEN/8, x2, x5, x6)

inst_235:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x100 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x39d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0c3 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d00; op2val:0xbf9d;
op3val:0x70c3; valaddr_reg:x1; val_offset:600*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 600*FLEN/8, x2, x5, x6)

inst_236:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x100 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x39d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0c3 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d00; op2val:0xbf9d;
op3val:0x70c3; valaddr_reg:x1; val_offset:603*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 603*FLEN/8, x2, x5, x6)

inst_237:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x100 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x39d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0c3 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d00; op2val:0xbf9d;
op3val:0x70c3; valaddr_reg:x1; val_offset:606*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 606*FLEN/8, x2, x5, x6)

inst_238:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x100 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x39d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0c3 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d00; op2val:0xbf9d;
op3val:0x70c3; valaddr_reg:x1; val_offset:609*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 609*FLEN/8, x2, x5, x6)

inst_239:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x100 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x39d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0c3 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d00; op2val:0xbf9d;
op3val:0x70c3; valaddr_reg:x1; val_offset:612*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 612*FLEN/8, x2, x5, x6)

inst_240:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x182 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1c8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f8 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7982; op2val:0xbdc8;
op3val:0x7bf8; valaddr_reg:x1; val_offset:615*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 615*FLEN/8, x2, x5, x6)

inst_241:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x182 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1c8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f8 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7982; op2val:0xbdc8;
op3val:0x7bf8; valaddr_reg:x1; val_offset:618*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 618*FLEN/8, x2, x5, x6)

inst_242:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x182 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1c8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f8 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7982; op2val:0xbdc8;
op3val:0x7bf8; valaddr_reg:x1; val_offset:621*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 621*FLEN/8, x2, x5, x6)

inst_243:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x182 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1c8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f8 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7982; op2val:0xbdc8;
op3val:0x7bf8; valaddr_reg:x1; val_offset:624*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 624*FLEN/8, x2, x5, x6)

inst_244:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x182 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1c8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f8 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7982; op2val:0xbdc8;
op3val:0x7bf8; valaddr_reg:x1; val_offset:627*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 627*FLEN/8, x2, x5, x6)

inst_245:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x12a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0cf and fs3 == 0 and fe3 == 0x1a and fm3 == 0x236 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x712a; op2val:0xb4cf;
op3val:0x6a36; valaddr_reg:x1; val_offset:630*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 630*FLEN/8, x2, x5, x6)

inst_246:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x12a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0cf and fs3 == 0 and fe3 == 0x1a and fm3 == 0x236 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x712a; op2val:0xb4cf;
op3val:0x6a36; valaddr_reg:x1; val_offset:633*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 633*FLEN/8, x2, x5, x6)

inst_247:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x12a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0cf and fs3 == 0 and fe3 == 0x1a and fm3 == 0x236 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x712a; op2val:0xb4cf;
op3val:0x6a36; valaddr_reg:x1; val_offset:636*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 636*FLEN/8, x2, x5, x6)

inst_248:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x12a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0cf and fs3 == 0 and fe3 == 0x1a and fm3 == 0x236 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x712a; op2val:0xb4cf;
op3val:0x6a36; valaddr_reg:x1; val_offset:639*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 639*FLEN/8, x2, x5, x6)

inst_249:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x12a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0cf and fs3 == 0 and fe3 == 0x1a and fm3 == 0x236 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x712a; op2val:0xb4cf;
op3val:0x6a36; valaddr_reg:x1; val_offset:642*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 642*FLEN/8, x2, x5, x6)

inst_250:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x053 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x044 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be3; op2val:0xb853;
op3val:0x7844; valaddr_reg:x1; val_offset:645*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 645*FLEN/8, x2, x5, x6)

inst_251:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x053 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x044 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be3; op2val:0xb853;
op3val:0x7844; valaddr_reg:x1; val_offset:648*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 648*FLEN/8, x2, x5, x6)

inst_252:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x053 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x044 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be3; op2val:0xb853;
op3val:0x7844; valaddr_reg:x1; val_offset:651*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 651*FLEN/8, x2, x5, x6)

inst_253:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x053 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x044 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be3; op2val:0xb853;
op3val:0x7844; valaddr_reg:x1; val_offset:654*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 654*FLEN/8, x2, x5, x6)

inst_254:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x053 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x044 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be3; op2val:0xb853;
op3val:0x7844; valaddr_reg:x1; val_offset:657*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 657*FLEN/8, x2, x5, x6)

inst_255:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x27d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ad and fs3 == 0 and fe3 == 0x1c and fm3 == 0x397 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x767d; op2val:0xb8ad;
op3val:0x7397; valaddr_reg:x1; val_offset:660*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 660*FLEN/8, x2, x5, x6)

inst_256:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x27d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ad and fs3 == 0 and fe3 == 0x1c and fm3 == 0x397 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x767d; op2val:0xb8ad;
op3val:0x7397; valaddr_reg:x1; val_offset:663*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 663*FLEN/8, x2, x5, x6)

inst_257:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x27d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ad and fs3 == 0 and fe3 == 0x1c and fm3 == 0x397 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x767d; op2val:0xb8ad;
op3val:0x7397; valaddr_reg:x1; val_offset:666*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 666*FLEN/8, x2, x5, x6)

inst_258:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x27d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ad and fs3 == 0 and fe3 == 0x1c and fm3 == 0x397 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x767d; op2val:0xb8ad;
op3val:0x7397; valaddr_reg:x1; val_offset:669*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 669*FLEN/8, x2, x5, x6)

inst_259:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x27d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ad and fs3 == 0 and fe3 == 0x1c and fm3 == 0x397 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x767d; op2val:0xb8ad;
op3val:0x7397; valaddr_reg:x1; val_offset:672*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 672*FLEN/8, x2, x5, x6)

inst_260:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bf and fs2 == 1 and fe2 == 0x0f and fm2 == 0x190 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29b and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78bf; op2val:0xbd90;
op3val:0x7a9b; valaddr_reg:x1; val_offset:675*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 675*FLEN/8, x2, x5, x6)

inst_261:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bf and fs2 == 1 and fe2 == 0x0f and fm2 == 0x190 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29b and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78bf; op2val:0xbd90;
op3val:0x7a9b; valaddr_reg:x1; val_offset:678*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 678*FLEN/8, x2, x5, x6)

inst_262:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bf and fs2 == 1 and fe2 == 0x0f and fm2 == 0x190 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29b and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78bf; op2val:0xbd90;
op3val:0x7a9b; valaddr_reg:x1; val_offset:681*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 681*FLEN/8, x2, x5, x6)

inst_263:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bf and fs2 == 1 and fe2 == 0x0f and fm2 == 0x190 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29b and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78bf; op2val:0xbd90;
op3val:0x7a9b; valaddr_reg:x1; val_offset:684*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 684*FLEN/8, x2, x5, x6)

inst_264:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bf and fs2 == 1 and fe2 == 0x0f and fm2 == 0x190 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29b and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78bf; op2val:0xbd90;
op3val:0x7a9b; valaddr_reg:x1; val_offset:687*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 687*FLEN/8, x2, x5, x6)

inst_265:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x367 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2be and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7749; op2val:0xbb67;
op3val:0x76be; valaddr_reg:x1; val_offset:690*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 690*FLEN/8, x2, x5, x6)

inst_266:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x367 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2be and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7749; op2val:0xbb67;
op3val:0x76be; valaddr_reg:x1; val_offset:693*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 693*FLEN/8, x2, x5, x6)

inst_267:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x367 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2be and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7749; op2val:0xbb67;
op3val:0x76be; valaddr_reg:x1; val_offset:696*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 696*FLEN/8, x2, x5, x6)

inst_268:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x367 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2be and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7749; op2val:0xbb67;
op3val:0x76be; valaddr_reg:x1; val_offset:699*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 699*FLEN/8, x2, x5, x6)

inst_269:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x367 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2be and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7749; op2val:0xbb67;
op3val:0x76be; valaddr_reg:x1; val_offset:702*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 702*FLEN/8, x2, x5, x6)

inst_270:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x320 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x01c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x353 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6b20; op2val:0xcc1c;
op3val:0x7b53; valaddr_reg:x1; val_offset:705*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 705*FLEN/8, x2, x5, x6)

inst_271:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x320 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x01c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x353 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6b20; op2val:0xcc1c;
op3val:0x7b53; valaddr_reg:x1; val_offset:708*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 708*FLEN/8, x2, x5, x6)

inst_272:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x320 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x01c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x353 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6b20; op2val:0xcc1c;
op3val:0x7b53; valaddr_reg:x1; val_offset:711*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 711*FLEN/8, x2, x5, x6)

inst_273:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x320 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x01c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x353 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6b20; op2val:0xcc1c;
op3val:0x7b53; valaddr_reg:x1; val_offset:714*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 714*FLEN/8, x2, x5, x6)

inst_274:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x320 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x01c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x353 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6b20; op2val:0xcc1c;
op3val:0x7b53; valaddr_reg:x1; val_offset:717*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 717*FLEN/8, x2, x5, x6)

inst_275:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x030 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x389 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3e4 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6830; op2val:0xcb89;
op3val:0x77e4; valaddr_reg:x1; val_offset:720*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 720*FLEN/8, x2, x5, x6)

inst_276:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x030 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x389 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3e4 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6830; op2val:0xcb89;
op3val:0x77e4; valaddr_reg:x1; val_offset:723*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 723*FLEN/8, x2, x5, x6)

inst_277:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x030 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x389 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3e4 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6830; op2val:0xcb89;
op3val:0x77e4; valaddr_reg:x1; val_offset:726*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 726*FLEN/8, x2, x5, x6)

inst_278:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x030 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x389 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3e4 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6830; op2val:0xcb89;
op3val:0x77e4; valaddr_reg:x1; val_offset:729*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 729*FLEN/8, x2, x5, x6)

inst_279:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x030 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x389 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3e4 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6830; op2val:0xcb89;
op3val:0x77e4; valaddr_reg:x1; val_offset:732*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 732*FLEN/8, x2, x5, x6)

inst_280:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b4 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0fb and fs3 == 0 and fe3 == 0x1c and fm3 == 0x02d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab4; op2val:0xb0fb;
op3val:0x702d; valaddr_reg:x1; val_offset:735*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 735*FLEN/8, x2, x5, x6)

inst_281:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b4 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0fb and fs3 == 0 and fe3 == 0x1c and fm3 == 0x02d and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab4; op2val:0xb0fb;
op3val:0x702d; valaddr_reg:x1; val_offset:738*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 738*FLEN/8, x2, x5, x6)

inst_282:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b4 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0fb and fs3 == 0 and fe3 == 0x1c and fm3 == 0x02d and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab4; op2val:0xb0fb;
op3val:0x702d; valaddr_reg:x1; val_offset:741*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 741*FLEN/8, x2, x5, x6)

inst_283:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b4 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0fb and fs3 == 0 and fe3 == 0x1c and fm3 == 0x02d and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab4; op2val:0xb0fb;
op3val:0x702d; valaddr_reg:x1; val_offset:744*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 744*FLEN/8, x2, x5, x6)
RVTEST_SIGBASE(x5,signature_x5_2)

inst_284:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b4 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0fb and fs3 == 0 and fe3 == 0x1c and fm3 == 0x02d and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab4; op2val:0xb0fb;
op3val:0x702d; valaddr_reg:x1; val_offset:747*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 747*FLEN/8, x2, x5, x6)

inst_285:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d9 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x131 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x398 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d9; op2val:0xbd31;
op3val:0x7b98; valaddr_reg:x1; val_offset:750*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 750*FLEN/8, x2, x5, x6)

inst_286:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d9 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x131 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x398 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d9; op2val:0xbd31;
op3val:0x7b98; valaddr_reg:x1; val_offset:753*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 753*FLEN/8, x2, x5, x6)

inst_287:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d9 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x131 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x398 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d9; op2val:0xbd31;
op3val:0x7b98; valaddr_reg:x1; val_offset:756*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 756*FLEN/8, x2, x5, x6)

inst_288:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d9 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x131 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x398 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d9; op2val:0xbd31;
op3val:0x7b98; valaddr_reg:x1; val_offset:759*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 759*FLEN/8, x2, x5, x6)

inst_289:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d9 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x131 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x398 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d9; op2val:0xbd31;
op3val:0x7b98; valaddr_reg:x1; val_offset:762*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 762*FLEN/8, x2, x5, x6)

inst_290:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x10a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x100 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x24d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x790a; op2val:0xbd00;
op3val:0x7a4d; valaddr_reg:x1; val_offset:765*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 765*FLEN/8, x2, x5, x6)

inst_291:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x10a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x100 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x24d and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x790a; op2val:0xbd00;
op3val:0x7a4d; valaddr_reg:x1; val_offset:768*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 768*FLEN/8, x2, x5, x6)

inst_292:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x10a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x100 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x24d and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x790a; op2val:0xbd00;
op3val:0x7a4d; valaddr_reg:x1; val_offset:771*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 771*FLEN/8, x2, x5, x6)

inst_293:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x10a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x100 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x24d and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x790a; op2val:0xbd00;
op3val:0x7a4d; valaddr_reg:x1; val_offset:774*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 774*FLEN/8, x2, x5, x6)

inst_294:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x10a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x100 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x24d and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x790a; op2val:0xbd00;
op3val:0x7a4d; valaddr_reg:x1; val_offset:777*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 777*FLEN/8, x2, x5, x6)

inst_295:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2d2 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x013 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2f3 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ed2; op2val:0xc413;
op3val:0x76f3; valaddr_reg:x1; val_offset:780*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 780*FLEN/8, x2, x5, x6)

inst_296:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2d2 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x013 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2f3 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ed2; op2val:0xc413;
op3val:0x76f3; valaddr_reg:x1; val_offset:783*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 783*FLEN/8, x2, x5, x6)

inst_297:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2d2 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x013 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2f3 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ed2; op2val:0xc413;
op3val:0x76f3; valaddr_reg:x1; val_offset:786*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 786*FLEN/8, x2, x5, x6)

inst_298:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2d2 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x013 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2f3 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ed2; op2val:0xc413;
op3val:0x76f3; valaddr_reg:x1; val_offset:789*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 789*FLEN/8, x2, x5, x6)

inst_299:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2d2 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x013 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2f3 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ed2; op2val:0xc413;
op3val:0x76f3; valaddr_reg:x1; val_offset:792*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 792*FLEN/8, x2, x5, x6)

inst_300:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0c6 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2c1 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70c6; op2val:0xc5a8;
op3val:0x7ac1; valaddr_reg:x1; val_offset:795*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 795*FLEN/8, x2, x5, x6)

inst_301:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0c6 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2c1 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70c6; op2val:0xc5a8;
op3val:0x7ac1; valaddr_reg:x1; val_offset:798*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 798*FLEN/8, x2, x5, x6)

inst_302:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0c6 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2c1 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70c6; op2val:0xc5a8;
op3val:0x7ac1; valaddr_reg:x1; val_offset:801*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 801*FLEN/8, x2, x5, x6)

inst_303:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0c6 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2c1 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70c6; op2val:0xc5a8;
op3val:0x7ac1; valaddr_reg:x1; val_offset:804*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 804*FLEN/8, x2, x5, x6)

inst_304:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0c6 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2c1 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70c6; op2val:0xc5a8;
op3val:0x7ac1; valaddr_reg:x1; val_offset:807*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 807*FLEN/8, x2, x5, x6)

inst_305:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x225 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x33f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74b7; op2val:0xbe25;
op3val:0x773f; valaddr_reg:x1; val_offset:810*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 810*FLEN/8, x2, x5, x6)

inst_306:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x225 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x33f and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74b7; op2val:0xbe25;
op3val:0x773f; valaddr_reg:x1; val_offset:813*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 813*FLEN/8, x2, x5, x6)

inst_307:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x225 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x33f and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74b7; op2val:0xbe25;
op3val:0x773f; valaddr_reg:x1; val_offset:816*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 816*FLEN/8, x2, x5, x6)

inst_308:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x225 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x33f and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74b7; op2val:0xbe25;
op3val:0x773f; valaddr_reg:x1; val_offset:819*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 819*FLEN/8, x2, x5, x6)

inst_309:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x225 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x33f and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74b7; op2val:0xbe25;
op3val:0x773f; valaddr_reg:x1; val_offset:822*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 822*FLEN/8, x2, x5, x6)

inst_310:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2d2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2d0 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bfd; op2val:0xbad2;
op3val:0x7ad0; valaddr_reg:x1; val_offset:825*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 825*FLEN/8, x2, x5, x6)

inst_311:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2d2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2d0 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bfd; op2val:0xbad2;
op3val:0x7ad0; valaddr_reg:x1; val_offset:828*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 828*FLEN/8, x2, x5, x6)

inst_312:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2d2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2d0 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bfd; op2val:0xbad2;
op3val:0x7ad0; valaddr_reg:x1; val_offset:831*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 831*FLEN/8, x2, x5, x6)

inst_313:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2d2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2d0 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bfd; op2val:0xbad2;
op3val:0x7ad0; valaddr_reg:x1; val_offset:834*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 834*FLEN/8, x2, x5, x6)

inst_314:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2d2 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2d0 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bfd; op2val:0xbad2;
op3val:0x7ad0; valaddr_reg:x1; val_offset:837*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 837*FLEN/8, x2, x5, x6)

inst_315:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3cd and fs2 == 1 and fe2 == 0x0d and fm2 == 0x36f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x340 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bcd; op2val:0xb76f;
op3val:0x7740; valaddr_reg:x1; val_offset:840*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 840*FLEN/8, x2, x5, x6)

inst_316:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3cd and fs2 == 1 and fe2 == 0x0d and fm2 == 0x36f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x340 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bcd; op2val:0xb76f;
op3val:0x7740; valaddr_reg:x1; val_offset:843*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 843*FLEN/8, x2, x5, x6)

inst_317:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3cd and fs2 == 1 and fe2 == 0x0d and fm2 == 0x36f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x340 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bcd; op2val:0xb76f;
op3val:0x7740; valaddr_reg:x1; val_offset:846*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 846*FLEN/8, x2, x5, x6)

inst_318:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3cd and fs2 == 1 and fe2 == 0x0d and fm2 == 0x36f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x340 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bcd; op2val:0xb76f;
op3val:0x7740; valaddr_reg:x1; val_offset:849*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 849*FLEN/8, x2, x5, x6)

inst_319:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3cd and fs2 == 1 and fe2 == 0x0d and fm2 == 0x36f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x340 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bcd; op2val:0xb76f;
op3val:0x7740; valaddr_reg:x1; val_offset:852*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 852*FLEN/8, x2, x5, x6)

inst_320:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ce and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1fa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1d5 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77ce; op2val:0xbdfa;
op3val:0x79d5; valaddr_reg:x1; val_offset:855*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 855*FLEN/8, x2, x5, x6)

inst_321:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ce and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1fa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1d5 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77ce; op2val:0xbdfa;
op3val:0x79d5; valaddr_reg:x1; val_offset:858*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 858*FLEN/8, x2, x5, x6)

inst_322:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ce and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1fa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1d5 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77ce; op2val:0xbdfa;
op3val:0x79d5; valaddr_reg:x1; val_offset:861*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 861*FLEN/8, x2, x5, x6)

inst_323:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ce and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1fa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1d5 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77ce; op2val:0xbdfa;
op3val:0x79d5; valaddr_reg:x1; val_offset:864*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 864*FLEN/8, x2, x5, x6)

inst_324:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ce and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1fa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1d5 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77ce; op2val:0xbdfa;
op3val:0x79d5; valaddr_reg:x1; val_offset:867*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 867*FLEN/8, x2, x5, x6)

inst_325:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0dc and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a7 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77a9; op2val:0xb8dc;
op3val:0x74a7; valaddr_reg:x1; val_offset:870*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 870*FLEN/8, x2, x5, x6)

inst_326:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0dc and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a7 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77a9; op2val:0xb8dc;
op3val:0x74a7; valaddr_reg:x1; val_offset:873*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 873*FLEN/8, x2, x5, x6)

inst_327:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0dc and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a7 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77a9; op2val:0xb8dc;
op3val:0x74a7; valaddr_reg:x1; val_offset:876*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 876*FLEN/8, x2, x5, x6)

inst_328:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0dc and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a7 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77a9; op2val:0xb8dc;
op3val:0x74a7; valaddr_reg:x1; val_offset:879*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 879*FLEN/8, x2, x5, x6)

inst_329:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0dc and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a7 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77a9; op2val:0xb8dc;
op3val:0x74a7; valaddr_reg:x1; val_offset:882*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 882*FLEN/8, x2, x5, x6)

inst_330:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x275 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1ce and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0af and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7675; op2val:0xb5ce;
op3val:0x70af; valaddr_reg:x1; val_offset:885*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 885*FLEN/8, x2, x5, x6)

inst_331:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x275 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1ce and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0af and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7675; op2val:0xb5ce;
op3val:0x70af; valaddr_reg:x1; val_offset:888*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 888*FLEN/8, x2, x5, x6)

inst_332:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x275 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1ce and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0af and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7675; op2val:0xb5ce;
op3val:0x70af; valaddr_reg:x1; val_offset:891*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 891*FLEN/8, x2, x5, x6)

inst_333:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x275 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1ce and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0af and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7675; op2val:0xb5ce;
op3val:0x70af; valaddr_reg:x1; val_offset:894*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 894*FLEN/8, x2, x5, x6)

inst_334:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x275 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1ce and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0af and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7675; op2val:0xb5ce;
op3val:0x70af; valaddr_reg:x1; val_offset:897*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 897*FLEN/8, x2, x5, x6)

inst_335:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x207 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x13e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3e7 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7607; op2val:0xc13e;
op3val:0x7be7; valaddr_reg:x1; val_offset:900*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 900*FLEN/8, x2, x5, x6)

inst_336:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x207 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x13e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3e7 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7607; op2val:0xc13e;
op3val:0x7be7; valaddr_reg:x1; val_offset:903*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 903*FLEN/8, x2, x5, x6)

inst_337:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x207 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x13e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3e7 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7607; op2val:0xc13e;
op3val:0x7be7; valaddr_reg:x1; val_offset:906*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 906*FLEN/8, x2, x5, x6)

inst_338:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x207 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x13e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3e7 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7607; op2val:0xc13e;
op3val:0x7be7; valaddr_reg:x1; val_offset:909*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 909*FLEN/8, x2, x5, x6)

inst_339:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x207 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x13e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3e7 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7607; op2val:0xc13e;
op3val:0x7be7; valaddr_reg:x1; val_offset:912*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 912*FLEN/8, x2, x5, x6)

inst_340:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ac and fs2 == 1 and fe2 == 0x0e and fm2 == 0x139 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x103 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bac; op2val:0xb939;
op3val:0x7903; valaddr_reg:x1; val_offset:915*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 915*FLEN/8, x2, x5, x6)

inst_341:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ac and fs2 == 1 and fe2 == 0x0e and fm2 == 0x139 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x103 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bac; op2val:0xb939;
op3val:0x7903; valaddr_reg:x1; val_offset:918*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 918*FLEN/8, x2, x5, x6)

inst_342:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ac and fs2 == 1 and fe2 == 0x0e and fm2 == 0x139 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x103 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bac; op2val:0xb939;
op3val:0x7903; valaddr_reg:x1; val_offset:921*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 921*FLEN/8, x2, x5, x6)

inst_343:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ac and fs2 == 1 and fe2 == 0x0e and fm2 == 0x139 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x103 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bac; op2val:0xb939;
op3val:0x7903; valaddr_reg:x1; val_offset:924*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 924*FLEN/8, x2, x5, x6)

inst_344:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ac and fs2 == 1 and fe2 == 0x0e and fm2 == 0x139 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x103 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bac; op2val:0xb939;
op3val:0x7903; valaddr_reg:x1; val_offset:927*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 927*FLEN/8, x2, x5, x6)

inst_345:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x16c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x169 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77fc; op2val:0xb96c;
op3val:0x7569; valaddr_reg:x1; val_offset:930*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 930*FLEN/8, x2, x5, x6)

inst_346:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x16c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x169 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77fc; op2val:0xb96c;
op3val:0x7569; valaddr_reg:x1; val_offset:933*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 933*FLEN/8, x2, x5, x6)

inst_347:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x16c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x169 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77fc; op2val:0xb96c;
op3val:0x7569; valaddr_reg:x1; val_offset:936*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 936*FLEN/8, x2, x5, x6)

inst_348:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x16c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x169 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77fc; op2val:0xb96c;
op3val:0x7569; valaddr_reg:x1; val_offset:939*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 939*FLEN/8, x2, x5, x6)

inst_349:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x16c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x169 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77fc; op2val:0xb96c;
op3val:0x7569; valaddr_reg:x1; val_offset:942*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 942*FLEN/8, x2, x5, x6)

inst_350:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1b3 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x21b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x05a and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6db3; op2val:0xc21b;
op3val:0x745a; valaddr_reg:x1; val_offset:945*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 945*FLEN/8, x2, x5, x6)

inst_351:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1b3 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x21b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x05a and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6db3; op2val:0xc21b;
op3val:0x745a; valaddr_reg:x1; val_offset:948*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 948*FLEN/8, x2, x5, x6)

inst_352:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1b3 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x21b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x05a and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6db3; op2val:0xc21b;
op3val:0x745a; valaddr_reg:x1; val_offset:951*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 951*FLEN/8, x2, x5, x6)

inst_353:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1b3 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x21b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x05a and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6db3; op2val:0xc21b;
op3val:0x745a; valaddr_reg:x1; val_offset:954*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 954*FLEN/8, x2, x5, x6)

inst_354:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1b3 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x21b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x05a and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6db3; op2val:0xc21b;
op3val:0x745a; valaddr_reg:x1; val_offset:957*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 957*FLEN/8, x2, x5, x6)

inst_355:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x240 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x06f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ef and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a40; op2val:0xbc6f;
op3val:0x7aef; valaddr_reg:x1; val_offset:960*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 960*FLEN/8, x2, x5, x6)

inst_356:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x240 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x06f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ef and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a40; op2val:0xbc6f;
op3val:0x7aef; valaddr_reg:x1; val_offset:963*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 963*FLEN/8, x2, x5, x6)

inst_357:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x240 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x06f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ef and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a40; op2val:0xbc6f;
op3val:0x7aef; valaddr_reg:x1; val_offset:966*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 966*FLEN/8, x2, x5, x6)

inst_358:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x240 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x06f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ef and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a40; op2val:0xbc6f;
op3val:0x7aef; valaddr_reg:x1; val_offset:969*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 969*FLEN/8, x2, x5, x6)

inst_359:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x240 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x06f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ef and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a40; op2val:0xbc6f;
op3val:0x7aef; valaddr_reg:x1; val_offset:972*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 972*FLEN/8, x2, x5, x6)

inst_360:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c7 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x059 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x248 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c7; op2val:0xc059;
op3val:0x7a48; valaddr_reg:x1; val_offset:975*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 975*FLEN/8, x2, x5, x6)

inst_361:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c7 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x059 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x248 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c7; op2val:0xc059;
op3val:0x7a48; valaddr_reg:x1; val_offset:978*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 978*FLEN/8, x2, x5, x6)

inst_362:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c7 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x059 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x248 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c7; op2val:0xc059;
op3val:0x7a48; valaddr_reg:x1; val_offset:981*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 981*FLEN/8, x2, x5, x6)

inst_363:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c7 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x059 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x248 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c7; op2val:0xc059;
op3val:0x7a48; valaddr_reg:x1; val_offset:984*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 984*FLEN/8, x2, x5, x6)

inst_364:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c7 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x059 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x248 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75c7; op2val:0xc059;
op3val:0x7a48; valaddr_reg:x1; val_offset:987*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 987*FLEN/8, x2, x5, x6)

inst_365:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x232 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x32b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x18d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a32; op2val:0xbb2b;
op3val:0x798d; valaddr_reg:x1; val_offset:990*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 990*FLEN/8, x2, x5, x6)

inst_366:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x232 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x32b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x18d and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a32; op2val:0xbb2b;
op3val:0x798d; valaddr_reg:x1; val_offset:993*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 993*FLEN/8, x2, x5, x6)

inst_367:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x232 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x32b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x18d and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a32; op2val:0xbb2b;
op3val:0x798d; valaddr_reg:x1; val_offset:996*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 996*FLEN/8, x2, x5, x6)

inst_368:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x232 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x32b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x18d and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a32; op2val:0xbb2b;
op3val:0x798d; valaddr_reg:x1; val_offset:999*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 999*FLEN/8, x2, x5, x6)

inst_369:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x232 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x32b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x18d and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a32; op2val:0xbb2b;
op3val:0x798d; valaddr_reg:x1; val_offset:1002*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1002*FLEN/8, x2, x5, x6)

inst_370:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x093 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x212 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x794f; op2val:0xbc93;
op3val:0x7a12; valaddr_reg:x1; val_offset:1005*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1005*FLEN/8, x2, x5, x6)

inst_371:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x093 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x212 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x794f; op2val:0xbc93;
op3val:0x7a12; valaddr_reg:x1; val_offset:1008*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1008*FLEN/8, x2, x5, x6)

inst_372:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x093 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x212 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x794f; op2val:0xbc93;
op3val:0x7a12; valaddr_reg:x1; val_offset:1011*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1011*FLEN/8, x2, x5, x6)

inst_373:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x093 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x212 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x794f; op2val:0xbc93;
op3val:0x7a12; valaddr_reg:x1; val_offset:1014*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1014*FLEN/8, x2, x5, x6)

inst_374:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x14f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x093 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x212 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x794f; op2val:0xbc93;
op3val:0x7a12; valaddr_reg:x1; val_offset:1017*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1017*FLEN/8, x2, x5, x6)

inst_375:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1cf and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3c0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a2 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75cf; op2val:0xbfc0;
op3val:0x79a2; valaddr_reg:x1; val_offset:1020*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1020*FLEN/8, x2, x5, x6)

inst_376:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1cf and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3c0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a2 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75cf; op2val:0xbfc0;
op3val:0x79a2; valaddr_reg:x1; val_offset:1023*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1023*FLEN/8, x2, x5, x6)

inst_377:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1cf and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3c0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a2 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75cf; op2val:0xbfc0;
op3val:0x79a2; valaddr_reg:x1; val_offset:1026*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1026*FLEN/8, x2, x5, x6)

inst_378:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1cf and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3c0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a2 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75cf; op2val:0xbfc0;
op3val:0x79a2; valaddr_reg:x1; val_offset:1029*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1029*FLEN/8, x2, x5, x6)

inst_379:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1cf and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3c0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1a2 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75cf; op2val:0xbfc0;
op3val:0x79a2; valaddr_reg:x1; val_offset:1032*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1032*FLEN/8, x2, x5, x6)

inst_380:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x07d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3c4 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x747d; op2val:0xbeea;
op3val:0x77c4; valaddr_reg:x1; val_offset:1035*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1035*FLEN/8, x2, x5, x6)

inst_381:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x07d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3c4 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x747d; op2val:0xbeea;
op3val:0x77c4; valaddr_reg:x1; val_offset:1038*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1038*FLEN/8, x2, x5, x6)

inst_382:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x07d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3c4 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x747d; op2val:0xbeea;
op3val:0x77c4; valaddr_reg:x1; val_offset:1041*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1041*FLEN/8, x2, x5, x6)

inst_383:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x07d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3c4 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x747d; op2val:0xbeea;
op3val:0x77c4; valaddr_reg:x1; val_offset:1044*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1044*FLEN/8, x2, x5, x6)

inst_384:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x07d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3c4 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x747d; op2val:0xbeea;
op3val:0x77c4; valaddr_reg:x1; val_offset:1047*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1047*FLEN/8, x2, x5, x6)

inst_385:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x227 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x32e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x186 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a27; op2val:0xbb2e;
op3val:0x7986; valaddr_reg:x1; val_offset:1050*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1050*FLEN/8, x2, x5, x6)

inst_386:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x227 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x32e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x186 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a27; op2val:0xbb2e;
op3val:0x7986; valaddr_reg:x1; val_offset:1053*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1053*FLEN/8, x2, x5, x6)

inst_387:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x227 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x32e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x186 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a27; op2val:0xbb2e;
op3val:0x7986; valaddr_reg:x1; val_offset:1056*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1056*FLEN/8, x2, x5, x6)

inst_388:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x227 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x32e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x186 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a27; op2val:0xbb2e;
op3val:0x7986; valaddr_reg:x1; val_offset:1059*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1059*FLEN/8, x2, x5, x6)

inst_389:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x227 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x32e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x186 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a27; op2val:0xbb2e;
op3val:0x7986; valaddr_reg:x1; val_offset:1062*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1062*FLEN/8, x2, x5, x6)

inst_390:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b3 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x26f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x38f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74b3; op2val:0xc26f;
op3val:0x7b8f; valaddr_reg:x1; val_offset:1065*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1065*FLEN/8, x2, x5, x6)

inst_391:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b3 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x26f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x38f and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74b3; op2val:0xc26f;
op3val:0x7b8f; valaddr_reg:x1; val_offset:1068*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1068*FLEN/8, x2, x5, x6)

inst_392:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b3 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x26f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x38f and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74b3; op2val:0xc26f;
op3val:0x7b8f; valaddr_reg:x1; val_offset:1071*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1071*FLEN/8, x2, x5, x6)

inst_393:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b3 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x26f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x38f and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74b3; op2val:0xc26f;
op3val:0x7b8f; valaddr_reg:x1; val_offset:1074*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1074*FLEN/8, x2, x5, x6)

inst_394:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b3 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x26f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x38f and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74b3; op2val:0xc26f;
op3val:0x7b8f; valaddr_reg:x1; val_offset:1077*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1077*FLEN/8, x2, x5, x6)

inst_395:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x131 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x326 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a4 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7931; op2val:0xbb26;
op3val:0x78a4; valaddr_reg:x1; val_offset:1080*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1080*FLEN/8, x2, x5, x6)

inst_396:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x131 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x326 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a4 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7931; op2val:0xbb26;
op3val:0x78a4; valaddr_reg:x1; val_offset:1083*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1083*FLEN/8, x2, x5, x6)

inst_397:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x131 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x326 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a4 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7931; op2val:0xbb26;
op3val:0x78a4; valaddr_reg:x1; val_offset:1086*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1086*FLEN/8, x2, x5, x6)

inst_398:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x131 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x326 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a4 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7931; op2val:0xbb26;
op3val:0x78a4; valaddr_reg:x1; val_offset:1089*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1089*FLEN/8, x2, x5, x6)

inst_399:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x131 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x326 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a4 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7931; op2val:0xbb26;
op3val:0x78a4; valaddr_reg:x1; val_offset:1092*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1092*FLEN/8, x2, x5, x6)

inst_400:
// fs1 == 0 and fe1 == 0x18 and fm1 == 0x1ef and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x05f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x61ef; op2val:0xd1e5;
op3val:0x785f; valaddr_reg:x1; val_offset:1095*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1095*FLEN/8, x2, x5, x6)

inst_401:
// fs1 == 0 and fe1 == 0x18 and fm1 == 0x1ef and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x05f and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x61ef; op2val:0xd1e5;
op3val:0x785f; valaddr_reg:x1; val_offset:1098*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1098*FLEN/8, x2, x5, x6)

inst_402:
// fs1 == 0 and fe1 == 0x18 and fm1 == 0x1ef and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x05f and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x61ef; op2val:0xd1e5;
op3val:0x785f; valaddr_reg:x1; val_offset:1101*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1101*FLEN/8, x2, x5, x6)

inst_403:
// fs1 == 0 and fe1 == 0x18 and fm1 == 0x1ef and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x05f and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x61ef; op2val:0xd1e5;
op3val:0x785f; valaddr_reg:x1; val_offset:1104*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1104*FLEN/8, x2, x5, x6)

inst_404:
// fs1 == 0 and fe1 == 0x18 and fm1 == 0x1ef and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x05f and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x61ef; op2val:0xd1e5;
op3val:0x785f; valaddr_reg:x1; val_offset:1107*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1107*FLEN/8, x2, x5, x6)

inst_405:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x002 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x15b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x15e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7402; op2val:0xc15b;
op3val:0x795e; valaddr_reg:x1; val_offset:1110*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1110*FLEN/8, x2, x5, x6)

inst_406:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x002 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x15b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x15e and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7402; op2val:0xc15b;
op3val:0x795e; valaddr_reg:x1; val_offset:1113*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1113*FLEN/8, x2, x5, x6)

inst_407:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x002 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x15b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x15e and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7402; op2val:0xc15b;
op3val:0x795e; valaddr_reg:x1; val_offset:1116*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1116*FLEN/8, x2, x5, x6)

inst_408:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x002 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x15b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x15e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7402; op2val:0xc15b;
op3val:0x795e; valaddr_reg:x1; val_offset:1119*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1119*FLEN/8, x2, x5, x6)

inst_409:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x002 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x15b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x15e and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7402; op2val:0xc15b;
op3val:0x795e; valaddr_reg:x1; val_offset:1122*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1122*FLEN/8, x2, x5, x6)

inst_410:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x367 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x30e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x287 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7767; op2val:0xbf0e;
op3val:0x7a87; valaddr_reg:x1; val_offset:1125*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1125*FLEN/8, x2, x5, x6)

inst_411:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x367 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x30e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x287 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7767; op2val:0xbf0e;
op3val:0x7a87; valaddr_reg:x1; val_offset:1128*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1128*FLEN/8, x2, x5, x6)
RVTEST_SIGBASE(x5,signature_x5_3)

inst_412:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x367 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x30e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x287 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7767; op2val:0xbf0e;
op3val:0x7a87; valaddr_reg:x1; val_offset:1131*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1131*FLEN/8, x2, x5, x6)

inst_413:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x367 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x30e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x287 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7767; op2val:0xbf0e;
op3val:0x7a87; valaddr_reg:x1; val_offset:1134*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1134*FLEN/8, x2, x5, x6)

inst_414:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x367 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x30e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x287 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7767; op2val:0xbf0e;
op3val:0x7a87; valaddr_reg:x1; val_offset:1137*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1137*FLEN/8, x2, x5, x6)

inst_415:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1e and fm3 == 0x260 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x792d; op2val:0xbced;
op3val:0x7a60; valaddr_reg:x1; val_offset:1140*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1140*FLEN/8, x2, x5, x6)

inst_416:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1e and fm3 == 0x260 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x792d; op2val:0xbced;
op3val:0x7a60; valaddr_reg:x1; val_offset:1143*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1143*FLEN/8, x2, x5, x6)

inst_417:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1e and fm3 == 0x260 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x792d; op2val:0xbced;
op3val:0x7a60; valaddr_reg:x1; val_offset:1146*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1146*FLEN/8, x2, x5, x6)

inst_418:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1e and fm3 == 0x260 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x792d; op2val:0xbced;
op3val:0x7a60; valaddr_reg:x1; val_offset:1149*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1149*FLEN/8, x2, x5, x6)

inst_419:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1e and fm3 == 0x260 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x792d; op2val:0xbced;
op3val:0x7a60; valaddr_reg:x1; val_offset:1152*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1152*FLEN/8, x2, x5, x6)

inst_420:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x190 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x367 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x126 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7590; op2val:0xbf67;
op3val:0x7926; valaddr_reg:x1; val_offset:1155*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1155*FLEN/8, x2, x5, x6)

inst_421:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x190 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x367 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x126 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7590; op2val:0xbf67;
op3val:0x7926; valaddr_reg:x1; val_offset:1158*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1158*FLEN/8, x2, x5, x6)

inst_422:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x190 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x367 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x126 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7590; op2val:0xbf67;
op3val:0x7926; valaddr_reg:x1; val_offset:1161*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1161*FLEN/8, x2, x5, x6)

inst_423:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x190 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x367 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x126 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7590; op2val:0xbf67;
op3val:0x7926; valaddr_reg:x1; val_offset:1164*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1164*FLEN/8, x2, x5, x6)

inst_424:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x190 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x367 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x126 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7590; op2val:0xbf67;
op3val:0x7926; valaddr_reg:x1; val_offset:1167*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1167*FLEN/8, x2, x5, x6)

inst_425:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e6 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x07d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79e6; op2val:0xbc7d;
op3val:0x7a9f; valaddr_reg:x1; val_offset:1170*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1170*FLEN/8, x2, x5, x6)

inst_426:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e6 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x07d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29f and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79e6; op2val:0xbc7d;
op3val:0x7a9f; valaddr_reg:x1; val_offset:1173*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1173*FLEN/8, x2, x5, x6)

inst_427:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e6 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x07d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29f and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79e6; op2val:0xbc7d;
op3val:0x7a9f; valaddr_reg:x1; val_offset:1176*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1176*FLEN/8, x2, x5, x6)

inst_428:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e6 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x07d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29f and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79e6; op2val:0xbc7d;
op3val:0x7a9f; valaddr_reg:x1; val_offset:1179*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1179*FLEN/8, x2, x5, x6)

inst_429:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e6 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x07d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29f and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79e6; op2val:0xbc7d;
op3val:0x7a9f; valaddr_reg:x1; val_offset:1182*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1182*FLEN/8, x2, x5, x6)

inst_430:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x199 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0d0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2bd and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7599; op2val:0xc0d0;
op3val:0x7abd; valaddr_reg:x1; val_offset:1185*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1185*FLEN/8, x2, x5, x6)

inst_431:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x199 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0d0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2bd and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7599; op2val:0xc0d0;
op3val:0x7abd; valaddr_reg:x1; val_offset:1188*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1188*FLEN/8, x2, x5, x6)

inst_432:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x199 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0d0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2bd and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7599; op2val:0xc0d0;
op3val:0x7abd; valaddr_reg:x1; val_offset:1191*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1191*FLEN/8, x2, x5, x6)

inst_433:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x199 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0d0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2bd and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7599; op2val:0xc0d0;
op3val:0x7abd; valaddr_reg:x1; val_offset:1194*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1194*FLEN/8, x2, x5, x6)

inst_434:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x199 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0d0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2bd and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7599; op2val:0xc0d0;
op3val:0x7abd; valaddr_reg:x1; val_offset:1197*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1197*FLEN/8, x2, x5, x6)

inst_435:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x254 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x181 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7af4; op2val:0xba54;
op3val:0x7981; valaddr_reg:x1; val_offset:1200*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1200*FLEN/8, x2, x5, x6)

inst_436:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x254 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x181 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7af4; op2val:0xba54;
op3val:0x7981; valaddr_reg:x1; val_offset:1203*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1203*FLEN/8, x2, x5, x6)

inst_437:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x254 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x181 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7af4; op2val:0xba54;
op3val:0x7981; valaddr_reg:x1; val_offset:1206*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1206*FLEN/8, x2, x5, x6)

inst_438:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x254 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x181 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7af4; op2val:0xba54;
op3val:0x7981; valaddr_reg:x1; val_offset:1209*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1209*FLEN/8, x2, x5, x6)

inst_439:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x254 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x181 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7af4; op2val:0xba54;
op3val:0x7981; valaddr_reg:x1; val_offset:1212*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1212*FLEN/8, x2, x5, x6)

inst_440:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ce and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3d6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3a5 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bce; op2val:0xbbd6;
op3val:0x7ba5; valaddr_reg:x1; val_offset:1215*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1215*FLEN/8, x2, x5, x6)

inst_441:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ce and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3d6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3a5 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bce; op2val:0xbbd6;
op3val:0x7ba5; valaddr_reg:x1; val_offset:1218*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1218*FLEN/8, x2, x5, x6)

inst_442:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ce and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3d6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3a5 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bce; op2val:0xbbd6;
op3val:0x7ba5; valaddr_reg:x1; val_offset:1221*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1221*FLEN/8, x2, x5, x6)

inst_443:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ce and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3d6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3a5 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bce; op2val:0xbbd6;
op3val:0x7ba5; valaddr_reg:x1; val_offset:1224*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1224*FLEN/8, x2, x5, x6)

inst_444:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ce and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3d6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3a5 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bce; op2val:0xbbd6;
op3val:0x7ba5; valaddr_reg:x1; val_offset:1227*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1227*FLEN/8, x2, x5, x6)

inst_445:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x024 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x016 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03b and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7824; op2val:0xbc16;
op3val:0x783b; valaddr_reg:x1; val_offset:1230*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1230*FLEN/8, x2, x5, x6)

inst_446:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x024 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x016 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03b and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7824; op2val:0xbc16;
op3val:0x783b; valaddr_reg:x1; val_offset:1233*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1233*FLEN/8, x2, x5, x6)

inst_447:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x024 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x016 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03b and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7824; op2val:0xbc16;
op3val:0x783b; valaddr_reg:x1; val_offset:1236*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1236*FLEN/8, x2, x5, x6)

inst_448:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x024 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x016 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03b and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7824; op2val:0xbc16;
op3val:0x783b; valaddr_reg:x1; val_offset:1239*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1239*FLEN/8, x2, x5, x6)

inst_449:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x024 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x016 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03b and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7824; op2val:0xbc16;
op3val:0x783b; valaddr_reg:x1; val_offset:1242*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1242*FLEN/8, x2, x5, x6)

inst_450:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x150 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x108 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2b0 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7150; op2val:0xc508;
op3val:0x7ab0; valaddr_reg:x1; val_offset:1245*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1245*FLEN/8, x2, x5, x6)

inst_451:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x150 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x108 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2b0 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7150; op2val:0xc508;
op3val:0x7ab0; valaddr_reg:x1; val_offset:1248*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1248*FLEN/8, x2, x5, x6)

inst_452:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x150 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x108 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2b0 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7150; op2val:0xc508;
op3val:0x7ab0; valaddr_reg:x1; val_offset:1251*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1251*FLEN/8, x2, x5, x6)

inst_453:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x150 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x108 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2b0 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7150; op2val:0xc508;
op3val:0x7ab0; valaddr_reg:x1; val_offset:1254*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1254*FLEN/8, x2, x5, x6)

inst_454:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x150 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x108 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2b0 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7150; op2val:0xc508;
op3val:0x7ab0; valaddr_reg:x1; val_offset:1257*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1257*FLEN/8, x2, x5, x6)

inst_455:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x012 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3a1 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b7e; op2val:0xb812;
op3val:0x77a1; valaddr_reg:x1; val_offset:1260*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1260*FLEN/8, x2, x5, x6)

inst_456:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x012 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3a1 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b7e; op2val:0xb812;
op3val:0x77a1; valaddr_reg:x1; val_offset:1263*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1263*FLEN/8, x2, x5, x6)

inst_457:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x012 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3a1 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b7e; op2val:0xb812;
op3val:0x77a1; valaddr_reg:x1; val_offset:1266*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1266*FLEN/8, x2, x5, x6)

inst_458:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x012 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3a1 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b7e; op2val:0xb812;
op3val:0x77a1; valaddr_reg:x1; val_offset:1269*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1269*FLEN/8, x2, x5, x6)

inst_459:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x012 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3a1 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b7e; op2val:0xb812;
op3val:0x77a1; valaddr_reg:x1; val_offset:1272*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1272*FLEN/8, x2, x5, x6)

inst_460:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x187 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x029 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1c1 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7987; op2val:0xbc29;
op3val:0x79c1; valaddr_reg:x1; val_offset:1275*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1275*FLEN/8, x2, x5, x6)

inst_461:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x187 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x029 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1c1 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7987; op2val:0xbc29;
op3val:0x79c1; valaddr_reg:x1; val_offset:1278*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1278*FLEN/8, x2, x5, x6)

inst_462:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x187 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x029 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1c1 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7987; op2val:0xbc29;
op3val:0x79c1; valaddr_reg:x1; val_offset:1281*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1281*FLEN/8, x2, x5, x6)

inst_463:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x187 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x029 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1c1 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7987; op2val:0xbc29;
op3val:0x79c1; valaddr_reg:x1; val_offset:1284*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1284*FLEN/8, x2, x5, x6)

inst_464:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x187 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x029 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1c1 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7987; op2val:0xbc29;
op3val:0x79c1; valaddr_reg:x1; val_offset:1287*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1287*FLEN/8, x2, x5, x6)

inst_465:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d7 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x387 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x17f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d7; op2val:0xb387;
op3val:0x717f; valaddr_reg:x1; val_offset:1290*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1290*FLEN/8, x2, x5, x6)

inst_466:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d7 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x387 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x17f and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d7; op2val:0xb387;
op3val:0x717f; valaddr_reg:x1; val_offset:1293*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1293*FLEN/8, x2, x5, x6)

inst_467:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d7 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x387 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x17f and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d7; op2val:0xb387;
op3val:0x717f; valaddr_reg:x1; val_offset:1296*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1296*FLEN/8, x2, x5, x6)

inst_468:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d7 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x387 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x17f and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d7; op2val:0xb387;
op3val:0x717f; valaddr_reg:x1; val_offset:1299*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1299*FLEN/8, x2, x5, x6)

inst_469:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d7 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x387 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x17f and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79d7; op2val:0xb387;
op3val:0x717f; valaddr_reg:x1; val_offset:1302*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1302*FLEN/8, x2, x5, x6)

inst_470:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x23d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1f4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a5 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a3d; op2val:0xb9f4;
op3val:0x78a5; valaddr_reg:x1; val_offset:1305*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1305*FLEN/8, x2, x5, x6)

inst_471:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x23d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1f4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a5 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a3d; op2val:0xb9f4;
op3val:0x78a5; valaddr_reg:x1; val_offset:1308*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1308*FLEN/8, x2, x5, x6)

inst_472:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x23d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1f4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a5 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a3d; op2val:0xb9f4;
op3val:0x78a5; valaddr_reg:x1; val_offset:1311*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1311*FLEN/8, x2, x5, x6)

inst_473:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x23d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1f4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a5 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a3d; op2val:0xb9f4;
op3val:0x78a5; valaddr_reg:x1; val_offset:1314*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1314*FLEN/8, x2, x5, x6)

inst_474:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x23d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1f4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a5 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a3d; op2val:0xb9f4;
op3val:0x78a5; valaddr_reg:x1; val_offset:1317*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1317*FLEN/8, x2, x5, x6)

inst_475:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x152 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x10e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ba and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7952; op2val:0xb90e;
op3val:0x76ba; valaddr_reg:x1; val_offset:1320*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1320*FLEN/8, x2, x5, x6)

inst_476:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x152 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x10e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ba and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7952; op2val:0xb90e;
op3val:0x76ba; valaddr_reg:x1; val_offset:1323*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1323*FLEN/8, x2, x5, x6)

inst_477:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x152 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x10e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ba and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7952; op2val:0xb90e;
op3val:0x76ba; valaddr_reg:x1; val_offset:1326*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1326*FLEN/8, x2, x5, x6)

inst_478:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x152 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x10e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ba and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7952; op2val:0xb90e;
op3val:0x76ba; valaddr_reg:x1; val_offset:1329*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1329*FLEN/8, x2, x5, x6)

inst_479:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x152 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x10e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ba and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7952; op2val:0xb90e;
op3val:0x76ba; valaddr_reg:x1; val_offset:1332*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1332*FLEN/8, x2, x5, x6)

inst_480:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x231 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fc; op2val:0xbcf7;
op3val:0x7a31; valaddr_reg:x1; val_offset:1335*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1335*FLEN/8, x2, x5, x6)

inst_481:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x231 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fc; op2val:0xbcf7;
op3val:0x7a31; valaddr_reg:x1; val_offset:1338*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1338*FLEN/8, x2, x5, x6)

inst_482:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x231 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fc; op2val:0xbcf7;
op3val:0x7a31; valaddr_reg:x1; val_offset:1341*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1341*FLEN/8, x2, x5, x6)

inst_483:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x231 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fc; op2val:0xbcf7;
op3val:0x7a31; valaddr_reg:x1; val_offset:1344*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1344*FLEN/8, x2, x5, x6)

inst_484:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x231 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fc; op2val:0xbcf7;
op3val:0x7a31; valaddr_reg:x1; val_offset:1347*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1347*FLEN/8, x2, x5, x6)

inst_485:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x117 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x086 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1c2 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7917; op2val:0xbc86;
op3val:0x79c2; valaddr_reg:x1; val_offset:1350*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1350*FLEN/8, x2, x5, x6)

inst_486:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x117 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x086 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1c2 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7917; op2val:0xbc86;
op3val:0x79c2; valaddr_reg:x1; val_offset:1353*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1353*FLEN/8, x2, x5, x6)

inst_487:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x117 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x086 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1c2 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7917; op2val:0xbc86;
op3val:0x79c2; valaddr_reg:x1; val_offset:1356*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1356*FLEN/8, x2, x5, x6)

inst_488:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x117 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x086 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1c2 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7917; op2val:0xbc86;
op3val:0x79c2; valaddr_reg:x1; val_offset:1359*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1359*FLEN/8, x2, x5, x6)

inst_489:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x117 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x086 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1c2 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7917; op2val:0xbc86;
op3val:0x79c2; valaddr_reg:x1; val_offset:1362*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1362*FLEN/8, x2, x5, x6)

inst_490:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x312 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1ca and fs3 == 0 and fe3 == 0x1c and fm3 == 0x11e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6712; op2val:0xc5ca;
op3val:0x711e; valaddr_reg:x1; val_offset:1365*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1365*FLEN/8, x2, x5, x6)

inst_491:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x312 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1ca and fs3 == 0 and fe3 == 0x1c and fm3 == 0x11e and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6712; op2val:0xc5ca;
op3val:0x711e; valaddr_reg:x1; val_offset:1368*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1368*FLEN/8, x2, x5, x6)

inst_492:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x312 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1ca and fs3 == 0 and fe3 == 0x1c and fm3 == 0x11e and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6712; op2val:0xc5ca;
op3val:0x711e; valaddr_reg:x1; val_offset:1371*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1371*FLEN/8, x2, x5, x6)

inst_493:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x312 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1ca and fs3 == 0 and fe3 == 0x1c and fm3 == 0x11e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6712; op2val:0xc5ca;
op3val:0x711e; valaddr_reg:x1; val_offset:1374*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1374*FLEN/8, x2, x5, x6)

inst_494:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x312 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1ca and fs3 == 0 and fe3 == 0x1c and fm3 == 0x11e and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6712; op2val:0xc5ca;
op3val:0x711e; valaddr_reg:x1; val_offset:1377*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1377*FLEN/8, x2, x5, x6)

inst_495:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x30d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x132 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x770d; op2val:0xbde5;
op3val:0x7932; valaddr_reg:x1; val_offset:1380*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1380*FLEN/8, x2, x5, x6)

inst_496:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x30d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x132 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x770d; op2val:0xbde5;
op3val:0x7932; valaddr_reg:x1; val_offset:1383*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1383*FLEN/8, x2, x5, x6)

inst_497:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x30d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x132 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x770d; op2val:0xbde5;
op3val:0x7932; valaddr_reg:x1; val_offset:1386*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1386*FLEN/8, x2, x5, x6)

inst_498:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x30d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x132 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x770d; op2val:0xbde5;
op3val:0x7932; valaddr_reg:x1; val_offset:1389*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1389*FLEN/8, x2, x5, x6)

inst_499:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x30d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x132 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x770d; op2val:0xbde5;
op3val:0x7932; valaddr_reg:x1; val_offset:1392*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1392*FLEN/8, x2, x5, x6)

inst_500:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x301 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x243 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x17c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7301; op2val:0xc243;
op3val:0x797c; valaddr_reg:x1; val_offset:1395*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1395*FLEN/8, x2, x5, x6)

inst_501:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x301 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x243 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x17c and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7301; op2val:0xc243;
op3val:0x797c; valaddr_reg:x1; val_offset:1398*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1398*FLEN/8, x2, x5, x6)

inst_502:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x301 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x243 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x17c and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7301; op2val:0xc243;
op3val:0x797c; valaddr_reg:x1; val_offset:1401*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1401*FLEN/8, x2, x5, x6)

inst_503:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x301 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x243 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x17c and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7301; op2val:0xc243;
op3val:0x797c; valaddr_reg:x1; val_offset:1404*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1404*FLEN/8, x2, x5, x6)

inst_504:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x301 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x243 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x17c and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7301; op2val:0xc243;
op3val:0x797c; valaddr_reg:x1; val_offset:1407*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1407*FLEN/8, x2, x5, x6)

inst_505:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x10b and fs2 == 1 and fe2 == 0x0b and fm2 == 0x03f and fs3 == 0 and fe3 == 0x1a and fm3 == 0x15b and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x790b; op2val:0xac3f;
op3val:0x695b; valaddr_reg:x1; val_offset:1410*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1410*FLEN/8, x2, x5, x6)

inst_506:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x10b and fs2 == 1 and fe2 == 0x0b and fm2 == 0x03f and fs3 == 0 and fe3 == 0x1a and fm3 == 0x15b and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x790b; op2val:0xac3f;
op3val:0x695b; valaddr_reg:x1; val_offset:1413*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1413*FLEN/8, x2, x5, x6)

inst_507:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x10b and fs2 == 1 and fe2 == 0x0b and fm2 == 0x03f and fs3 == 0 and fe3 == 0x1a and fm3 == 0x15b and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x790b; op2val:0xac3f;
op3val:0x695b; valaddr_reg:x1; val_offset:1416*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1416*FLEN/8, x2, x5, x6)

inst_508:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x10b and fs2 == 1 and fe2 == 0x0b and fm2 == 0x03f and fs3 == 0 and fe3 == 0x1a and fm3 == 0x15b and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x790b; op2val:0xac3f;
op3val:0x695b; valaddr_reg:x1; val_offset:1419*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1419*FLEN/8, x2, x5, x6)

inst_509:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x10b and fs2 == 1 and fe2 == 0x0b and fm2 == 0x03f and fs3 == 0 and fe3 == 0x1a and fm3 == 0x15b and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x790b; op2val:0xac3f;
op3val:0x695b; valaddr_reg:x1; val_offset:1422*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1422*FLEN/8, x2, x5, x6)

inst_510:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x38a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3ad and fs3 == 0 and fe3 == 0x1c and fm3 == 0x33c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x778a; op2val:0xb7ad;
op3val:0x733c; valaddr_reg:x1; val_offset:1425*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1425*FLEN/8, x2, x5, x6)

inst_511:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x38a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3ad and fs3 == 0 and fe3 == 0x1c and fm3 == 0x33c and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x778a; op2val:0xb7ad;
op3val:0x733c; valaddr_reg:x1; val_offset:1428*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1428*FLEN/8, x2, x5, x6)

inst_512:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x38a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3ad and fs3 == 0 and fe3 == 0x1c and fm3 == 0x33c and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x778a; op2val:0xb7ad;
op3val:0x733c; valaddr_reg:x1; val_offset:1431*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1431*FLEN/8, x2, x5, x6)

inst_513:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x38a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3ad and fs3 == 0 and fe3 == 0x1c and fm3 == 0x33c and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x778a; op2val:0xb7ad;
op3val:0x733c; valaddr_reg:x1; val_offset:1434*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1434*FLEN/8, x2, x5, x6)

inst_514:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x38a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3ad and fs3 == 0 and fe3 == 0x1c and fm3 == 0x33c and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x778a; op2val:0xb7ad;
op3val:0x733c; valaddr_reg:x1; val_offset:1437*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1437*FLEN/8, x2, x5, x6)

inst_515:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x2ed and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ee and fs3 == 0 and fe3 == 0x1c and fm3 == 0x045 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6aed; op2val:0xc0ee;
op3val:0x7045; valaddr_reg:x1; val_offset:1440*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1440*FLEN/8, x2, x5, x6)

inst_516:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x2ed and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ee and fs3 == 0 and fe3 == 0x1c and fm3 == 0x045 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6aed; op2val:0xc0ee;
op3val:0x7045; valaddr_reg:x1; val_offset:1443*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1443*FLEN/8, x2, x5, x6)

inst_517:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x2ed and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ee and fs3 == 0 and fe3 == 0x1c and fm3 == 0x045 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6aed; op2val:0xc0ee;
op3val:0x7045; valaddr_reg:x1; val_offset:1446*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1446*FLEN/8, x2, x5, x6)

inst_518:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x2ed and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ee and fs3 == 0 and fe3 == 0x1c and fm3 == 0x045 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6aed; op2val:0xc0ee;
op3val:0x7045; valaddr_reg:x1; val_offset:1449*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1449*FLEN/8, x2, x5, x6)

inst_519:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x2ed and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ee and fs3 == 0 and fe3 == 0x1c and fm3 == 0x045 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6aed; op2val:0xc0ee;
op3val:0x7045; valaddr_reg:x1; val_offset:1452*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1452*FLEN/8, x2, x5, x6)

inst_520:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x113 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x093 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1ce and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7513; op2val:0xb893;
op3val:0x71ce; valaddr_reg:x1; val_offset:1455*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1455*FLEN/8, x2, x5, x6)

inst_521:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x113 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x093 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1ce and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7513; op2val:0xb893;
op3val:0x71ce; valaddr_reg:x1; val_offset:1458*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1458*FLEN/8, x2, x5, x6)

inst_522:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x113 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x093 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1ce and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7513; op2val:0xb893;
op3val:0x71ce; valaddr_reg:x1; val_offset:1461*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1461*FLEN/8, x2, x5, x6)

inst_523:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x113 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x093 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1ce and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7513; op2val:0xb893;
op3val:0x71ce; valaddr_reg:x1; val_offset:1464*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1464*FLEN/8, x2, x5, x6)

inst_524:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x113 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x093 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1ce and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7513; op2val:0xb893;
op3val:0x71ce; valaddr_reg:x1; val_offset:1467*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1467*FLEN/8, x2, x5, x6)

inst_525:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x22f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1e7 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x090 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x722f; op2val:0xb1e7;
op3val:0x6890; valaddr_reg:x1; val_offset:1470*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1470*FLEN/8, x2, x5, x6)

inst_526:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x22f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1e7 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x090 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x722f; op2val:0xb1e7;
op3val:0x6890; valaddr_reg:x1; val_offset:1473*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1473*FLEN/8, x2, x5, x6)

inst_527:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x22f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1e7 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x090 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x722f; op2val:0xb1e7;
op3val:0x6890; valaddr_reg:x1; val_offset:1476*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1476*FLEN/8, x2, x5, x6)

inst_528:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x22f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1e7 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x090 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x722f; op2val:0xb1e7;
op3val:0x6890; valaddr_reg:x1; val_offset:1479*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1479*FLEN/8, x2, x5, x6)

inst_529:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x22f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x1e7 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x090 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x722f; op2val:0xb1e7;
op3val:0x6890; valaddr_reg:x1; val_offset:1482*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1482*FLEN/8, x2, x5, x6)

inst_530:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x371 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x289 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x214 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7771; op2val:0xba89;
op3val:0x7614; valaddr_reg:x1; val_offset:1485*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1485*FLEN/8, x2, x5, x6)

inst_531:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x371 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x289 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x214 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7771; op2val:0xba89;
op3val:0x7614; valaddr_reg:x1; val_offset:1488*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1488*FLEN/8, x2, x5, x6)

inst_532:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x371 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x289 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x214 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7771; op2val:0xba89;
op3val:0x7614; valaddr_reg:x1; val_offset:1491*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1491*FLEN/8, x2, x5, x6)

inst_533:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x371 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x289 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x214 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7771; op2val:0xba89;
op3val:0x7614; valaddr_reg:x1; val_offset:1494*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1494*FLEN/8, x2, x5, x6)

inst_534:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x371 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x289 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x214 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7771; op2val:0xba89;
op3val:0x7614; valaddr_reg:x1; val_offset:1497*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1497*FLEN/8, x2, x5, x6)

inst_535:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b8 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e4; op2val:0xbbb7;
op3val:0x78b8; valaddr_reg:x1; val_offset:1500*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1500*FLEN/8, x2, x5, x6)

inst_536:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b8 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e4; op2val:0xbbb7;
op3val:0x78b8; valaddr_reg:x1; val_offset:1503*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1503*FLEN/8, x2, x5, x6)

inst_537:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b8 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e4; op2val:0xbbb7;
op3val:0x78b8; valaddr_reg:x1; val_offset:1506*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1506*FLEN/8, x2, x5, x6)

inst_538:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b8 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e4; op2val:0xbbb7;
op3val:0x78b8; valaddr_reg:x1; val_offset:1509*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1509*FLEN/8, x2, x5, x6)

inst_539:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b8 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e4; op2val:0xbbb7;
op3val:0x78b8; valaddr_reg:x1; val_offset:1512*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1512*FLEN/8, x2, x5, x6)
RVTEST_SIGBASE(x5,signature_x5_4)

inst_540:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x398 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x338 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x739b; op2val:0xc398;
op3val:0x7b38; valaddr_reg:x1; val_offset:1515*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1515*FLEN/8, x2, x5, x6)

inst_541:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x398 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x338 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x739b; op2val:0xc398;
op3val:0x7b38; valaddr_reg:x1; val_offset:1518*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1518*FLEN/8, x2, x5, x6)

inst_542:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x398 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x338 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x739b; op2val:0xc398;
op3val:0x7b38; valaddr_reg:x1; val_offset:1521*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1521*FLEN/8, x2, x5, x6)

inst_543:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x398 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x338 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x739b; op2val:0xc398;
op3val:0x7b38; valaddr_reg:x1; val_offset:1524*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1524*FLEN/8, x2, x5, x6)

inst_544:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x398 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x338 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x739b; op2val:0xc398;
op3val:0x7b38; valaddr_reg:x1; val_offset:1527*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1527*FLEN/8, x2, x5, x6)

inst_545:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x188 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x0af and fs3 == 0 and fe3 == 0x1d and fm3 == 0x27b and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5188; op2val:0xe0af;
op3val:0x767b; valaddr_reg:x1; val_offset:1530*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1530*FLEN/8, x2, x5, x6)

inst_546:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x188 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x0af and fs3 == 0 and fe3 == 0x1d and fm3 == 0x27b and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5188; op2val:0xe0af;
op3val:0x767b; valaddr_reg:x1; val_offset:1533*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1533*FLEN/8, x2, x5, x6)

inst_547:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x188 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x0af and fs3 == 0 and fe3 == 0x1d and fm3 == 0x27b and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5188; op2val:0xe0af;
op3val:0x767b; valaddr_reg:x1; val_offset:1536*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1536*FLEN/8, x2, x5, x6)

inst_548:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x188 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x0af and fs3 == 0 and fe3 == 0x1d and fm3 == 0x27b and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5188; op2val:0xe0af;
op3val:0x767b; valaddr_reg:x1; val_offset:1539*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1539*FLEN/8, x2, x5, x6)

inst_549:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x188 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x0af and fs3 == 0 and fe3 == 0x1d and fm3 == 0x27b and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5188; op2val:0xe0af;
op3val:0x767b; valaddr_reg:x1; val_offset:1542*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1542*FLEN/8, x2, x5, x6)

inst_550:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x074 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e3 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x28e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7474; op2val:0xbde3;
op3val:0x768e; valaddr_reg:x1; val_offset:1545*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1545*FLEN/8, x2, x5, x6)

inst_551:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x074 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e3 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x28e and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7474; op2val:0xbde3;
op3val:0x768e; valaddr_reg:x1; val_offset:1548*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1548*FLEN/8, x2, x5, x6)

inst_552:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x074 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e3 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x28e and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7474; op2val:0xbde3;
op3val:0x768e; valaddr_reg:x1; val_offset:1551*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1551*FLEN/8, x2, x5, x6)

inst_553:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x074 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e3 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x28e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7474; op2val:0xbde3;
op3val:0x768e; valaddr_reg:x1; val_offset:1554*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1554*FLEN/8, x2, x5, x6)

inst_554:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x074 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e3 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x28e and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7474; op2val:0xbde3;
op3val:0x768e; valaddr_reg:x1; val_offset:1557*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1557*FLEN/8, x2, x5, x6)

inst_555:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x35c and fs2 == 1 and fe2 == 0x11 and fm2 == 0x339 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a5 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f5c; op2val:0xc739;
op3val:0x7aa5; valaddr_reg:x1; val_offset:1560*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1560*FLEN/8, x2, x5, x6)

inst_556:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x35c and fs2 == 1 and fe2 == 0x11 and fm2 == 0x339 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a5 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f5c; op2val:0xc739;
op3val:0x7aa5; valaddr_reg:x1; val_offset:1563*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1563*FLEN/8, x2, x5, x6)

inst_557:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x35c and fs2 == 1 and fe2 == 0x11 and fm2 == 0x339 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a5 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f5c; op2val:0xc739;
op3val:0x7aa5; valaddr_reg:x1; val_offset:1566*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1566*FLEN/8, x2, x5, x6)

inst_558:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x35c and fs2 == 1 and fe2 == 0x11 and fm2 == 0x339 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a5 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f5c; op2val:0xc739;
op3val:0x7aa5; valaddr_reg:x1; val_offset:1569*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1569*FLEN/8, x2, x5, x6)

inst_559:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x35c and fs2 == 1 and fe2 == 0x11 and fm2 == 0x339 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a5 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f5c; op2val:0xc739;
op3val:0x7aa5; valaddr_reg:x1; val_offset:1572*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1572*FLEN/8, x2, x5, x6)

inst_560:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1fa and fs2 == 1 and fe2 == 0x0b and fm2 == 0x22c and fs3 == 0 and fe3 == 0x1a and fm3 == 0x09d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75fa; op2val:0xae2c;
op3val:0x689d; valaddr_reg:x1; val_offset:1575*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1575*FLEN/8, x2, x5, x6)

inst_561:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1fa and fs2 == 1 and fe2 == 0x0b and fm2 == 0x22c and fs3 == 0 and fe3 == 0x1a and fm3 == 0x09d and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75fa; op2val:0xae2c;
op3val:0x689d; valaddr_reg:x1; val_offset:1578*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1578*FLEN/8, x2, x5, x6)

inst_562:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1fa and fs2 == 1 and fe2 == 0x0b and fm2 == 0x22c and fs3 == 0 and fe3 == 0x1a and fm3 == 0x09d and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75fa; op2val:0xae2c;
op3val:0x689d; valaddr_reg:x1; val_offset:1581*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1581*FLEN/8, x2, x5, x6)

inst_563:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1fa and fs2 == 1 and fe2 == 0x0b and fm2 == 0x22c and fs3 == 0 and fe3 == 0x1a and fm3 == 0x09d and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75fa; op2val:0xae2c;
op3val:0x689d; valaddr_reg:x1; val_offset:1584*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1584*FLEN/8, x2, x5, x6)

inst_564:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1fa and fs2 == 1 and fe2 == 0x0b and fm2 == 0x22c and fs3 == 0 and fe3 == 0x1a and fm3 == 0x09d and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75fa; op2val:0xae2c;
op3val:0x689d; valaddr_reg:x1; val_offset:1587*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1587*FLEN/8, x2, x5, x6)

inst_565:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e7 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0f2 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x211 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e7; op2val:0xb0f2;
op3val:0x6e11; valaddr_reg:x1; val_offset:1590*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1590*FLEN/8, x2, x5, x6)

inst_566:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e7 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0f2 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x211 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e7; op2val:0xb0f2;
op3val:0x6e11; valaddr_reg:x1; val_offset:1593*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1593*FLEN/8, x2, x5, x6)

inst_567:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e7 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0f2 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x211 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e7; op2val:0xb0f2;
op3val:0x6e11; valaddr_reg:x1; val_offset:1596*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1596*FLEN/8, x2, x5, x6)

inst_568:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e7 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0f2 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x211 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e7; op2val:0xb0f2;
op3val:0x6e11; valaddr_reg:x1; val_offset:1599*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1599*FLEN/8, x2, x5, x6)

inst_569:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e7 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0f2 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x211 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e7; op2val:0xb0f2;
op3val:0x6e11; valaddr_reg:x1; val_offset:1602*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1602*FLEN/8, x2, x5, x6)

inst_570:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0fa and fs3 == 0 and fe3 == 0x1d and fm3 == 0x16d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x785c; op2val:0xb8fa;
op3val:0x756d; valaddr_reg:x1; val_offset:1605*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1605*FLEN/8, x2, x5, x6)

inst_571:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0fa and fs3 == 0 and fe3 == 0x1d and fm3 == 0x16d and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x785c; op2val:0xb8fa;
op3val:0x756d; valaddr_reg:x1; val_offset:1608*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1608*FLEN/8, x2, x5, x6)

inst_572:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0fa and fs3 == 0 and fe3 == 0x1d and fm3 == 0x16d and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x785c; op2val:0xb8fa;
op3val:0x756d; valaddr_reg:x1; val_offset:1611*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1611*FLEN/8, x2, x5, x6)

inst_573:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0fa and fs3 == 0 and fe3 == 0x1d and fm3 == 0x16d and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x785c; op2val:0xb8fa;
op3val:0x756d; valaddr_reg:x1; val_offset:1614*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1614*FLEN/8, x2, x5, x6)

inst_574:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0fa and fs3 == 0 and fe3 == 0x1d and fm3 == 0x16d and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x785c; op2val:0xb8fa;
op3val:0x756d; valaddr_reg:x1; val_offset:1617*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1617*FLEN/8, x2, x5, x6)

inst_575:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x299 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3a9 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78a5; op2val:0xbe99;
op3val:0x7ba9; valaddr_reg:x1; val_offset:1620*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1620*FLEN/8, x2, x5, x6)

inst_576:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x299 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3a9 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78a5; op2val:0xbe99;
op3val:0x7ba9; valaddr_reg:x1; val_offset:1623*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1623*FLEN/8, x2, x5, x6)

inst_577:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x299 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3a9 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78a5; op2val:0xbe99;
op3val:0x7ba9; valaddr_reg:x1; val_offset:1626*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1626*FLEN/8, x2, x5, x6)

inst_578:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x299 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3a9 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78a5; op2val:0xbe99;
op3val:0x7ba9; valaddr_reg:x1; val_offset:1629*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1629*FLEN/8, x2, x5, x6)

inst_579:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x299 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3a9 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78a5; op2val:0xbe99;
op3val:0x7ba9; valaddr_reg:x1; val_offset:1632*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1632*FLEN/8, x2, x5, x6)

inst_580:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x018 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2b3 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8b; op2val:0xb818;
op3val:0x76b3; valaddr_reg:x1; val_offset:1635*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1635*FLEN/8, x2, x5, x6)

inst_581:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x018 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2b3 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8b; op2val:0xb818;
op3val:0x76b3; valaddr_reg:x1; val_offset:1638*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1638*FLEN/8, x2, x5, x6)

inst_582:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x018 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2b3 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8b; op2val:0xb818;
op3val:0x76b3; valaddr_reg:x1; val_offset:1641*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1641*FLEN/8, x2, x5, x6)

inst_583:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x018 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2b3 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8b; op2val:0xb818;
op3val:0x76b3; valaddr_reg:x1; val_offset:1644*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1644*FLEN/8, x2, x5, x6)

inst_584:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x018 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2b3 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8b; op2val:0xb818;
op3val:0x76b3; valaddr_reg:x1; val_offset:1647*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1647*FLEN/8, x2, x5, x6)

inst_585:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x280 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x252 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x122 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a80; op2val:0xba52;
op3val:0x7922; valaddr_reg:x1; val_offset:1650*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1650*FLEN/8, x2, x5, x6)

inst_586:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x280 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x252 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x122 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a80; op2val:0xba52;
op3val:0x7922; valaddr_reg:x1; val_offset:1653*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1653*FLEN/8, x2, x5, x6)

inst_587:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x280 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x252 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x122 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a80; op2val:0xba52;
op3val:0x7922; valaddr_reg:x1; val_offset:1656*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1656*FLEN/8, x2, x5, x6)

inst_588:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x280 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x252 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x122 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a80; op2val:0xba52;
op3val:0x7922; valaddr_reg:x1; val_offset:1659*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1659*FLEN/8, x2, x5, x6)

inst_589:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x280 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x252 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x122 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a80; op2val:0xba52;
op3val:0x7922; valaddr_reg:x1; val_offset:1662*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1662*FLEN/8, x2, x5, x6)

inst_590:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e8 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x227 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x08b and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75e8; op2val:0xb627;
op3val:0x708b; valaddr_reg:x1; val_offset:1665*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1665*FLEN/8, x2, x5, x6)

inst_591:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e8 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x227 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x08b and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75e8; op2val:0xb627;
op3val:0x708b; valaddr_reg:x1; val_offset:1668*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1668*FLEN/8, x2, x5, x6)

inst_592:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e8 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x227 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x08b and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75e8; op2val:0xb627;
op3val:0x708b; valaddr_reg:x1; val_offset:1671*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1671*FLEN/8, x2, x5, x6)

inst_593:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e8 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x227 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x08b and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75e8; op2val:0xb627;
op3val:0x708b; valaddr_reg:x1; val_offset:1674*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1674*FLEN/8, x2, x5, x6)

inst_594:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e8 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x227 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x08b and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75e8; op2val:0xb627;
op3val:0x708b; valaddr_reg:x1; val_offset:1677*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1677*FLEN/8, x2, x5, x6)

inst_595:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x391 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x082 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78c3; op2val:0xbb91;
op3val:0x7882; valaddr_reg:x1; val_offset:1680*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1680*FLEN/8, x2, x5, x6)

inst_596:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x391 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x082 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78c3; op2val:0xbb91;
op3val:0x7882; valaddr_reg:x1; val_offset:1683*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1683*FLEN/8, x2, x5, x6)

inst_597:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x391 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x082 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78c3; op2val:0xbb91;
op3val:0x7882; valaddr_reg:x1; val_offset:1686*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1686*FLEN/8, x2, x5, x6)

inst_598:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x391 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x082 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78c3; op2val:0xbb91;
op3val:0x7882; valaddr_reg:x1; val_offset:1689*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1689*FLEN/8, x2, x5, x6)

inst_599:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x391 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x082 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78c3; op2val:0xbb91;
op3val:0x7882; valaddr_reg:x1; val_offset:1692*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1692*FLEN/8, x2, x5, x6)

inst_600:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3bd and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba7; op2val:0xbc0b;
op3val:0x7bbd; valaddr_reg:x1; val_offset:1695*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1695*FLEN/8, x2, x5, x6)

inst_601:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3bd and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba7; op2val:0xbc0b;
op3val:0x7bbd; valaddr_reg:x1; val_offset:1698*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1698*FLEN/8, x2, x5, x6)

inst_602:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3bd and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba7; op2val:0xbc0b;
op3val:0x7bbd; valaddr_reg:x1; val_offset:1701*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1701*FLEN/8, x2, x5, x6)

inst_603:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3bd and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba7; op2val:0xbc0b;
op3val:0x7bbd; valaddr_reg:x1; val_offset:1704*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1704*FLEN/8, x2, x5, x6)

inst_604:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3bd and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba7; op2val:0xbc0b;
op3val:0x7bbd; valaddr_reg:x1; val_offset:1707*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1707*FLEN/8, x2, x5, x6)

inst_605:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0dd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x09d and fs3 == 0 and fe3 == 0x1d and fm3 == 0x19d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78dd; op2val:0xb89d;
op3val:0x759d; valaddr_reg:x1; val_offset:1710*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1710*FLEN/8, x2, x5, x6)

inst_606:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0dd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x09d and fs3 == 0 and fe3 == 0x1d and fm3 == 0x19d and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78dd; op2val:0xb89d;
op3val:0x759d; valaddr_reg:x1; val_offset:1713*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1713*FLEN/8, x2, x5, x6)

inst_607:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0dd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x09d and fs3 == 0 and fe3 == 0x1d and fm3 == 0x19d and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78dd; op2val:0xb89d;
op3val:0x759d; valaddr_reg:x1; val_offset:1716*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1716*FLEN/8, x2, x5, x6)

inst_608:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0dd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x09d and fs3 == 0 and fe3 == 0x1d and fm3 == 0x19d and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78dd; op2val:0xb89d;
op3val:0x759d; valaddr_reg:x1; val_offset:1719*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1719*FLEN/8, x2, x5, x6)

inst_609:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0dd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x09d and fs3 == 0 and fe3 == 0x1d and fm3 == 0x19d and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78dd; op2val:0xb89d;
op3val:0x759d; valaddr_reg:x1; val_offset:1722*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1722*FLEN/8, x2, x5, x6)

inst_610:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x324 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x069 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x3e2 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b24; op2val:0x9469;
op3val:0x53e2; valaddr_reg:x1; val_offset:1725*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1725*FLEN/8, x2, x5, x6)

inst_611:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x324 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x069 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x3e2 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b24; op2val:0x9469;
op3val:0x53e2; valaddr_reg:x1; val_offset:1728*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1728*FLEN/8, x2, x5, x6)

inst_612:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x324 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x069 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x3e2 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b24; op2val:0x9469;
op3val:0x53e2; valaddr_reg:x1; val_offset:1731*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1731*FLEN/8, x2, x5, x6)

inst_613:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x324 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x069 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x3e2 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b24; op2val:0x9469;
op3val:0x53e2; valaddr_reg:x1; val_offset:1734*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1734*FLEN/8, x2, x5, x6)

inst_614:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x324 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x069 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x3e2 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b24; op2val:0x9469;
op3val:0x53e2; valaddr_reg:x1; val_offset:1737*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1737*FLEN/8, x2, x5, x6)

inst_615:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2e7 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x13e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x086 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ee7; op2val:0xc53e;
op3val:0x7886; valaddr_reg:x1; val_offset:1740*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1740*FLEN/8, x2, x5, x6)

inst_616:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2e7 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x13e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x086 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ee7; op2val:0xc53e;
op3val:0x7886; valaddr_reg:x1; val_offset:1743*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1743*FLEN/8, x2, x5, x6)

inst_617:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2e7 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x13e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x086 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ee7; op2val:0xc53e;
op3val:0x7886; valaddr_reg:x1; val_offset:1746*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1746*FLEN/8, x2, x5, x6)

inst_618:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2e7 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x13e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x086 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ee7; op2val:0xc53e;
op3val:0x7886; valaddr_reg:x1; val_offset:1749*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1749*FLEN/8, x2, x5, x6)

inst_619:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2e7 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x13e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x086 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ee7; op2val:0xc53e;
op3val:0x7886; valaddr_reg:x1; val_offset:1752*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1752*FLEN/8, x2, x5, x6)

inst_620:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0eb and fs2 == 1 and fe2 == 0x0c and fm2 == 0x351 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x080 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78eb; op2val:0xb351;
op3val:0x7080; valaddr_reg:x1; val_offset:1755*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1755*FLEN/8, x2, x5, x6)

inst_621:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0eb and fs2 == 1 and fe2 == 0x0c and fm2 == 0x351 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x080 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78eb; op2val:0xb351;
op3val:0x7080; valaddr_reg:x1; val_offset:1758*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1758*FLEN/8, x2, x5, x6)

inst_622:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0eb and fs2 == 1 and fe2 == 0x0c and fm2 == 0x351 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x080 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78eb; op2val:0xb351;
op3val:0x7080; valaddr_reg:x1; val_offset:1761*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1761*FLEN/8, x2, x5, x6)

inst_623:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0eb and fs2 == 1 and fe2 == 0x0c and fm2 == 0x351 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x080 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78eb; op2val:0xb351;
op3val:0x7080; valaddr_reg:x1; val_offset:1764*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1764*FLEN/8, x2, x5, x6)

inst_624:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0eb and fs2 == 1 and fe2 == 0x0c and fm2 == 0x351 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x080 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78eb; op2val:0xb351;
op3val:0x7080; valaddr_reg:x1; val_offset:1767*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1767*FLEN/8, x2, x5, x6)

inst_625:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x108 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1a9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x320 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7908; op2val:0xbda9;
op3val:0x7b20; valaddr_reg:x1; val_offset:1770*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1770*FLEN/8, x2, x5, x6)

inst_626:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x108 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1a9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x320 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7908; op2val:0xbda9;
op3val:0x7b20; valaddr_reg:x1; val_offset:1773*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1773*FLEN/8, x2, x5, x6)

inst_627:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x108 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1a9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x320 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7908; op2val:0xbda9;
op3val:0x7b20; valaddr_reg:x1; val_offset:1776*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1776*FLEN/8, x2, x5, x6)

inst_628:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x108 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1a9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x320 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7908; op2val:0xbda9;
op3val:0x7b20; valaddr_reg:x1; val_offset:1779*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1779*FLEN/8, x2, x5, x6)

inst_629:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x108 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1a9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x320 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7908; op2val:0xbda9;
op3val:0x7b20; valaddr_reg:x1; val_offset:1782*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1782*FLEN/8, x2, x5, x6)

inst_630:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x202 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x098 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2e7 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7602; op2val:0xbc98;
op3val:0x76e7; valaddr_reg:x1; val_offset:1785*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1785*FLEN/8, x2, x5, x6)

inst_631:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x202 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x098 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2e7 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7602; op2val:0xbc98;
op3val:0x76e7; valaddr_reg:x1; val_offset:1788*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1788*FLEN/8, x2, x5, x6)

inst_632:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x202 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x098 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2e7 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7602; op2val:0xbc98;
op3val:0x76e7; valaddr_reg:x1; val_offset:1791*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1791*FLEN/8, x2, x5, x6)

inst_633:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x202 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x098 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2e7 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7602; op2val:0xbc98;
op3val:0x76e7; valaddr_reg:x1; val_offset:1794*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1794*FLEN/8, x2, x5, x6)

inst_634:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x202 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x098 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2e7 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7602; op2val:0xbc98;
op3val:0x76e7; valaddr_reg:x1; val_offset:1797*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1797*FLEN/8, x2, x5, x6)

inst_635:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x33d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x126 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a9 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x733d; op2val:0xbd26;
op3val:0x74a9; valaddr_reg:x1; val_offset:1800*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1800*FLEN/8, x2, x5, x6)

inst_636:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x33d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x126 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a9 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x733d; op2val:0xbd26;
op3val:0x74a9; valaddr_reg:x1; val_offset:1803*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1803*FLEN/8, x2, x5, x6)

inst_637:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x33d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x126 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a9 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x733d; op2val:0xbd26;
op3val:0x74a9; valaddr_reg:x1; val_offset:1806*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1806*FLEN/8, x2, x5, x6)

inst_638:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x33d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x126 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a9 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x733d; op2val:0xbd26;
op3val:0x74a9; valaddr_reg:x1; val_offset:1809*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1809*FLEN/8, x2, x5, x6)

inst_639:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x33d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x126 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a9 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x733d; op2val:0xbd26;
op3val:0x74a9; valaddr_reg:x1; val_offset:1812*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1812*FLEN/8, x2, x5, x6)

inst_640:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c6 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x23f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x212 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc6; op2val:0xb63f;
op3val:0x7612; valaddr_reg:x1; val_offset:1815*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1815*FLEN/8, x2, x5, x6)

inst_641:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c6 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x23f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x212 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc6; op2val:0xb63f;
op3val:0x7612; valaddr_reg:x1; val_offset:1818*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1818*FLEN/8, x2, x5, x6)

inst_642:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c6 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x23f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x212 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc6; op2val:0xb63f;
op3val:0x7612; valaddr_reg:x1; val_offset:1821*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1821*FLEN/8, x2, x5, x6)

inst_643:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c6 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x23f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x212 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc6; op2val:0xb63f;
op3val:0x7612; valaddr_reg:x1; val_offset:1824*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1824*FLEN/8, x2, x5, x6)

inst_644:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c6 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x23f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x212 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc6; op2val:0xb63f;
op3val:0x7612; valaddr_reg:x1; val_offset:1827*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1827*FLEN/8, x2, x5, x6)

inst_645:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3af and fs2 == 1 and fe2 == 0x0e and fm2 == 0x39b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x34e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7baf; op2val:0xbb9b;
op3val:0x7b4e; valaddr_reg:x1; val_offset:1830*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1830*FLEN/8, x2, x5, x6)

inst_646:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3af and fs2 == 1 and fe2 == 0x0e and fm2 == 0x39b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x34e and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7baf; op2val:0xbb9b;
op3val:0x7b4e; valaddr_reg:x1; val_offset:1833*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1833*FLEN/8, x2, x5, x6)

inst_647:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3af and fs2 == 1 and fe2 == 0x0e and fm2 == 0x39b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x34e and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7baf; op2val:0xbb9b;
op3val:0x7b4e; valaddr_reg:x1; val_offset:1836*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1836*FLEN/8, x2, x5, x6)

inst_648:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3af and fs2 == 1 and fe2 == 0x0e and fm2 == 0x39b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x34e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7baf; op2val:0xbb9b;
op3val:0x7b4e; valaddr_reg:x1; val_offset:1839*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1839*FLEN/8, x2, x5, x6)

inst_649:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3af and fs2 == 1 and fe2 == 0x0e and fm2 == 0x39b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x34e and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7baf; op2val:0xbb9b;
op3val:0x7b4e; valaddr_reg:x1; val_offset:1842*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1842*FLEN/8, x2, x5, x6)

inst_650:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c3 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2fa and fs3 == 0 and fe3 == 0x1d and fm3 == 0x027 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78c3; op2val:0xb6fa;
op3val:0x7427; valaddr_reg:x1; val_offset:1845*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1845*FLEN/8, x2, x5, x6)

inst_651:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c3 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2fa and fs3 == 0 and fe3 == 0x1d and fm3 == 0x027 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78c3; op2val:0xb6fa;
op3val:0x7427; valaddr_reg:x1; val_offset:1848*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1848*FLEN/8, x2, x5, x6)

inst_652:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c3 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2fa and fs3 == 0 and fe3 == 0x1d and fm3 == 0x027 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78c3; op2val:0xb6fa;
op3val:0x7427; valaddr_reg:x1; val_offset:1851*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1851*FLEN/8, x2, x5, x6)

inst_653:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c3 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2fa and fs3 == 0 and fe3 == 0x1d and fm3 == 0x027 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78c3; op2val:0xb6fa;
op3val:0x7427; valaddr_reg:x1; val_offset:1854*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1854*FLEN/8, x2, x5, x6)

inst_654:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c3 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2fa and fs3 == 0 and fe3 == 0x1d and fm3 == 0x027 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78c3; op2val:0xb6fa;
op3val:0x7427; valaddr_reg:x1; val_offset:1857*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1857*FLEN/8, x2, x5, x6)

inst_655:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x00c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3ef and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd8; op2val:0xb80c;
op3val:0x77ef; valaddr_reg:x1; val_offset:1860*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1860*FLEN/8, x2, x5, x6)

inst_656:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x00c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3ef and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd8; op2val:0xb80c;
op3val:0x77ef; valaddr_reg:x1; val_offset:1863*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1863*FLEN/8, x2, x5, x6)

inst_657:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x00c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3ef and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd8; op2val:0xb80c;
op3val:0x77ef; valaddr_reg:x1; val_offset:1866*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1866*FLEN/8, x2, x5, x6)

inst_658:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x00c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3ef and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd8; op2val:0xb80c;
op3val:0x77ef; valaddr_reg:x1; val_offset:1869*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1869*FLEN/8, x2, x5, x6)

inst_659:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x00c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3ef and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd8; op2val:0xb80c;
op3val:0x77ef; valaddr_reg:x1; val_offset:1872*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1872*FLEN/8, x2, x5, x6)

inst_660:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x225 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x11a and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76a5; op2val:0xba25;
op3val:0x751a; valaddr_reg:x1; val_offset:1875*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1875*FLEN/8, x2, x5, x6)

inst_661:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x225 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x11a and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76a5; op2val:0xba25;
op3val:0x751a; valaddr_reg:x1; val_offset:1878*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1878*FLEN/8, x2, x5, x6)

inst_662:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x225 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x11a and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76a5; op2val:0xba25;
op3val:0x751a; valaddr_reg:x1; val_offset:1881*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1881*FLEN/8, x2, x5, x6)

inst_663:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x225 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x11a and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76a5; op2val:0xba25;
op3val:0x751a; valaddr_reg:x1; val_offset:1884*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1884*FLEN/8, x2, x5, x6)

inst_664:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x225 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x11a and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76a5; op2val:0xba25;
op3val:0x751a; valaddr_reg:x1; val_offset:1887*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1887*FLEN/8, x2, x5, x6)

inst_665:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3de and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3dd and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bde; op2val:0xb7fe;
op3val:0x77dd; valaddr_reg:x1; val_offset:1890*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1890*FLEN/8, x2, x5, x6)

inst_666:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3de and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3dd and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bde; op2val:0xb7fe;
op3val:0x77dd; valaddr_reg:x1; val_offset:1893*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1893*FLEN/8, x2, x5, x6)

inst_667:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3de and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3dd and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bde; op2val:0xb7fe;
op3val:0x77dd; valaddr_reg:x1; val_offset:1896*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1896*FLEN/8, x2, x5, x6)
RVTEST_SIGBASE(x5,signature_x5_5)

inst_668:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3de and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3dd and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bde; op2val:0xb7fe;
op3val:0x77dd; valaddr_reg:x1; val_offset:1899*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1899*FLEN/8, x2, x5, x6)

inst_669:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3de and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3dd and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bde; op2val:0xb7fe;
op3val:0x77dd; valaddr_reg:x1; val_offset:1902*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1902*FLEN/8, x2, x5, x6)

inst_670:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x094 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2a9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3a0 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7494; op2val:0xbea9;
op3val:0x77a0; valaddr_reg:x1; val_offset:1905*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1905*FLEN/8, x2, x5, x6)

inst_671:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x094 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2a9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3a0 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7494; op2val:0xbea9;
op3val:0x77a0; valaddr_reg:x1; val_offset:1908*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1908*FLEN/8, x2, x5, x6)

inst_672:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x094 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2a9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3a0 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7494; op2val:0xbea9;
op3val:0x77a0; valaddr_reg:x1; val_offset:1911*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1911*FLEN/8, x2, x5, x6)

inst_673:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x094 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2a9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3a0 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7494; op2val:0xbea9;
op3val:0x77a0; valaddr_reg:x1; val_offset:1914*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1914*FLEN/8, x2, x5, x6)

inst_674:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x094 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2a9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3a0 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7494; op2val:0xbea9;
op3val:0x77a0; valaddr_reg:x1; val_offset:1917*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1917*FLEN/8, x2, x5, x6)

inst_675:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3cc and fs2 == 1 and fe2 == 0x11 and fm2 == 0x119 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f8 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6fcc; op2val:0xc519;
op3val:0x78f8; valaddr_reg:x1; val_offset:1920*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1920*FLEN/8, x2, x5, x6)

inst_676:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3cc and fs2 == 1 and fe2 == 0x11 and fm2 == 0x119 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f8 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6fcc; op2val:0xc519;
op3val:0x78f8; valaddr_reg:x1; val_offset:1923*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1923*FLEN/8, x2, x5, x6)

inst_677:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3cc and fs2 == 1 and fe2 == 0x11 and fm2 == 0x119 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f8 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6fcc; op2val:0xc519;
op3val:0x78f8; valaddr_reg:x1; val_offset:1926*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1926*FLEN/8, x2, x5, x6)

inst_678:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3cc and fs2 == 1 and fe2 == 0x11 and fm2 == 0x119 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f8 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6fcc; op2val:0xc519;
op3val:0x78f8; valaddr_reg:x1; val_offset:1929*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1929*FLEN/8, x2, x5, x6)

inst_679:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3cc and fs2 == 1 and fe2 == 0x11 and fm2 == 0x119 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f8 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6fcc; op2val:0xc519;
op3val:0x78f8; valaddr_reg:x1; val_offset:1932*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1932*FLEN/8, x2, x5, x6)

inst_680:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x317 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x149 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0b0 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7717; op2val:0xb949;
op3val:0x74b0; valaddr_reg:x1; val_offset:1935*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1935*FLEN/8, x2, x5, x6)

inst_681:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x317 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x149 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0b0 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7717; op2val:0xb949;
op3val:0x74b0; valaddr_reg:x1; val_offset:1938*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1938*FLEN/8, x2, x5, x6)

inst_682:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x317 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x149 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0b0 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7717; op2val:0xb949;
op3val:0x74b0; valaddr_reg:x1; val_offset:1941*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1941*FLEN/8, x2, x5, x6)

inst_683:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x317 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x149 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0b0 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7717; op2val:0xb949;
op3val:0x74b0; valaddr_reg:x1; val_offset:1944*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1944*FLEN/8, x2, x5, x6)

inst_684:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x317 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x149 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0b0 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7717; op2val:0xb949;
op3val:0x74b0; valaddr_reg:x1; val_offset:1947*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1947*FLEN/8, x2, x5, x6)

inst_685:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x240 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a40; op2val:0xbc3b;
op3val:0x7a9c; valaddr_reg:x1; val_offset:1950*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1950*FLEN/8, x2, x5, x6)

inst_686:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x240 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29c and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a40; op2val:0xbc3b;
op3val:0x7a9c; valaddr_reg:x1; val_offset:1953*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1953*FLEN/8, x2, x5, x6)

inst_687:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x240 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29c and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a40; op2val:0xbc3b;
op3val:0x7a9c; valaddr_reg:x1; val_offset:1956*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1956*FLEN/8, x2, x5, x6)

inst_688:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x240 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29c and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a40; op2val:0xbc3b;
op3val:0x7a9c; valaddr_reg:x1; val_offset:1959*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1959*FLEN/8, x2, x5, x6)

inst_689:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x240 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29c and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a40; op2val:0xbc3b;
op3val:0x7a9c; valaddr_reg:x1; val_offset:1962*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1962*FLEN/8, x2, x5, x6)

inst_690:
// fs1 == 0 and fe1 == 0x18 and fm1 == 0x2c3 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x109 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x042 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x62c3; op2val:0xd109;
op3val:0x7842; valaddr_reg:x1; val_offset:1965*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1965*FLEN/8, x2, x5, x6)

inst_691:
// fs1 == 0 and fe1 == 0x18 and fm1 == 0x2c3 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x109 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x042 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x62c3; op2val:0xd109;
op3val:0x7842; valaddr_reg:x1; val_offset:1968*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1968*FLEN/8, x2, x5, x6)

inst_692:
// fs1 == 0 and fe1 == 0x18 and fm1 == 0x2c3 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x109 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x042 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x62c3; op2val:0xd109;
op3val:0x7842; valaddr_reg:x1; val_offset:1971*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1971*FLEN/8, x2, x5, x6)

inst_693:
// fs1 == 0 and fe1 == 0x18 and fm1 == 0x2c3 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x109 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x042 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x62c3; op2val:0xd109;
op3val:0x7842; valaddr_reg:x1; val_offset:1974*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1974*FLEN/8, x2, x5, x6)

inst_694:
// fs1 == 0 and fe1 == 0x18 and fm1 == 0x2c3 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x109 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x042 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x62c3; op2val:0xd109;
op3val:0x7842; valaddr_reg:x1; val_offset:1977*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1977*FLEN/8, x2, x5, x6)

inst_695:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x060 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2d4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x37a and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7460; op2val:0xc2d4;
op3val:0x7b7a; valaddr_reg:x1; val_offset:1980*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1980*FLEN/8, x2, x5, x6)

inst_696:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x060 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2d4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x37a and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7460; op2val:0xc2d4;
op3val:0x7b7a; valaddr_reg:x1; val_offset:1983*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1983*FLEN/8, x2, x5, x6)

inst_697:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x060 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2d4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x37a and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7460; op2val:0xc2d4;
op3val:0x7b7a; valaddr_reg:x1; val_offset:1986*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 1986*FLEN/8, x2, x5, x6)

inst_698:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x060 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2d4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x37a and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7460; op2val:0xc2d4;
op3val:0x7b7a; valaddr_reg:x1; val_offset:1989*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 1989*FLEN/8, x2, x5, x6)

inst_699:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x060 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2d4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x37a and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7460; op2val:0xc2d4;
op3val:0x7b7a; valaddr_reg:x1; val_offset:1992*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 1992*FLEN/8, x2, x5, x6)

inst_700:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x240 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x106 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3db and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a40; op2val:0xb506;
op3val:0x73db; valaddr_reg:x1; val_offset:1995*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 1995*FLEN/8, x2, x5, x6)

inst_701:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x240 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x106 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3db and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a40; op2val:0xb506;
op3val:0x73db; valaddr_reg:x1; val_offset:1998*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 1998*FLEN/8, x2, x5, x6)

inst_702:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x240 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x106 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3db and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a40; op2val:0xb506;
op3val:0x73db; valaddr_reg:x1; val_offset:2001*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2001*FLEN/8, x2, x5, x6)

inst_703:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x240 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x106 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3db and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a40; op2val:0xb506;
op3val:0x73db; valaddr_reg:x1; val_offset:2004*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2004*FLEN/8, x2, x5, x6)

inst_704:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x240 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x106 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3db and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a40; op2val:0xb506;
op3val:0x73db; valaddr_reg:x1; val_offset:2007*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2007*FLEN/8, x2, x5, x6)

inst_705:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x047 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0a0 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0f3 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7447; op2val:0xb8a0;
op3val:0x70f3; valaddr_reg:x1; val_offset:2010*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2010*FLEN/8, x2, x5, x6)

inst_706:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x047 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0a0 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0f3 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7447; op2val:0xb8a0;
op3val:0x70f3; valaddr_reg:x1; val_offset:2013*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2013*FLEN/8, x2, x5, x6)

inst_707:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x047 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0a0 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0f3 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7447; op2val:0xb8a0;
op3val:0x70f3; valaddr_reg:x1; val_offset:2016*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2016*FLEN/8, x2, x5, x6)

inst_708:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x047 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0a0 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0f3 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7447; op2val:0xb8a0;
op3val:0x70f3; valaddr_reg:x1; val_offset:2019*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2019*FLEN/8, x2, x5, x6)

inst_709:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x047 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0a0 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0f3 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7447; op2val:0xb8a0;
op3val:0x70f3; valaddr_reg:x1; val_offset:2022*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2022*FLEN/8, x2, x5, x6)

inst_710:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e8 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0be and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0b0 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be8; op2val:0xb4be;
op3val:0x74b0; valaddr_reg:x1; val_offset:2025*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2025*FLEN/8, x2, x5, x6)

inst_711:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e8 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0be and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0b0 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be8; op2val:0xb4be;
op3val:0x74b0; valaddr_reg:x1; val_offset:2028*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2028*FLEN/8, x2, x5, x6)

inst_712:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e8 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0be and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0b0 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be8; op2val:0xb4be;
op3val:0x74b0; valaddr_reg:x1; val_offset:2031*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2031*FLEN/8, x2, x5, x6)

inst_713:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e8 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0be and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0b0 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be8; op2val:0xb4be;
op3val:0x74b0; valaddr_reg:x1; val_offset:2034*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2034*FLEN/8, x2, x5, x6)

inst_714:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e8 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0be and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0b0 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be8; op2val:0xb4be;
op3val:0x74b0; valaddr_reg:x1; val_offset:2037*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2037*FLEN/8, x2, x5, x6)

inst_715:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0dc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x23e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x397 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78dc; op2val:0xba3e;
op3val:0x7797; valaddr_reg:x1; val_offset:2040*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2040*FLEN/8, x2, x5, x6)

inst_716:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0dc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x23e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x397 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78dc; op2val:0xba3e;
op3val:0x7797; valaddr_reg:x1; val_offset:2043*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2043*FLEN/8, x2, x5, x6)

inst_717:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0dc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x23e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x397 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78dc; op2val:0xba3e;
op3val:0x7797; valaddr_reg:x1; val_offset:2046*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2046*FLEN/8, x2, x5, x6)

inst_718:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0dc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x23e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x397 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78dc; op2val:0xba3e;
op3val:0x7797; valaddr_reg:x1; val_offset:2049*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2049*FLEN/8, x2, x5, x6)

inst_719:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0dc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x23e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x397 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78dc; op2val:0xba3e;
op3val:0x7797; valaddr_reg:x1; val_offset:2052*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2052*FLEN/8, x2, x5, x6)

inst_720:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x128 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x37d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0d4 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7928; op2val:0xbb7d;
op3val:0x78d4; valaddr_reg:x1; val_offset:2055*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2055*FLEN/8, x2, x5, x6)

inst_721:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x128 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x37d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0d4 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7928; op2val:0xbb7d;
op3val:0x78d4; valaddr_reg:x1; val_offset:2058*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2058*FLEN/8, x2, x5, x6)

inst_722:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x128 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x37d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0d4 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7928; op2val:0xbb7d;
op3val:0x78d4; valaddr_reg:x1; val_offset:2061*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2061*FLEN/8, x2, x5, x6)

inst_723:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x128 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x37d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0d4 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7928; op2val:0xbb7d;
op3val:0x78d4; valaddr_reg:x1; val_offset:2064*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2064*FLEN/8, x2, x5, x6)

inst_724:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x128 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x37d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0d4 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7928; op2val:0xbb7d;
op3val:0x78d4; valaddr_reg:x1; val_offset:2067*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2067*FLEN/8, x2, x5, x6)

inst_725:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f1 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x116 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x38f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f1; op2val:0xb116;
op3val:0x6f8f; valaddr_reg:x1; val_offset:2070*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2070*FLEN/8, x2, x5, x6)

inst_726:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f1 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x116 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x38f and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f1; op2val:0xb116;
op3val:0x6f8f; valaddr_reg:x1; val_offset:2073*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2073*FLEN/8, x2, x5, x6)

inst_727:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f1 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x116 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x38f and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f1; op2val:0xb116;
op3val:0x6f8f; valaddr_reg:x1; val_offset:2076*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2076*FLEN/8, x2, x5, x6)

inst_728:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f1 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x116 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x38f and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f1; op2val:0xb116;
op3val:0x6f8f; valaddr_reg:x1; val_offset:2079*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2079*FLEN/8, x2, x5, x6)

inst_729:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f1 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x116 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x38f and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f1; op2val:0xb116;
op3val:0x6f8f; valaddr_reg:x1; val_offset:2082*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2082*FLEN/8, x2, x5, x6)

inst_730:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x214 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x253 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0cf and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a14; op2val:0xb653;
op3val:0x74cf; valaddr_reg:x1; val_offset:2085*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2085*FLEN/8, x2, x5, x6)

inst_731:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x214 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x253 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0cf and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a14; op2val:0xb653;
op3val:0x74cf; valaddr_reg:x1; val_offset:2088*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2088*FLEN/8, x2, x5, x6)

inst_732:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x214 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x253 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0cf and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a14; op2val:0xb653;
op3val:0x74cf; valaddr_reg:x1; val_offset:2091*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2091*FLEN/8, x2, x5, x6)

inst_733:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x214 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x253 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0cf and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a14; op2val:0xb653;
op3val:0x74cf; valaddr_reg:x1; val_offset:2094*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2094*FLEN/8, x2, x5, x6)

inst_734:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x214 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x253 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0cf and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a14; op2val:0xb653;
op3val:0x74cf; valaddr_reg:x1; val_offset:2097*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2097*FLEN/8, x2, x5, x6)

inst_735:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x044 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x10a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x160 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7844; op2val:0xb90a;
op3val:0x7560; valaddr_reg:x1; val_offset:2100*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2100*FLEN/8, x2, x5, x6)

inst_736:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x044 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x10a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x160 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7844; op2val:0xb90a;
op3val:0x7560; valaddr_reg:x1; val_offset:2103*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2103*FLEN/8, x2, x5, x6)

inst_737:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x044 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x10a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x160 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7844; op2val:0xb90a;
op3val:0x7560; valaddr_reg:x1; val_offset:2106*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2106*FLEN/8, x2, x5, x6)

inst_738:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x044 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x10a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x160 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7844; op2val:0xb90a;
op3val:0x7560; valaddr_reg:x1; val_offset:2109*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2109*FLEN/8, x2, x5, x6)

inst_739:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x044 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x10a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x160 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7844; op2val:0xb90a;
op3val:0x7560; valaddr_reg:x1; val_offset:2112*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2112*FLEN/8, x2, x5, x6)

inst_740:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0bf and fs2 == 1 and fe2 == 0x0f and fm2 == 0x323 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74bf; op2val:0xbf23;
op3val:0x783c; valaddr_reg:x1; val_offset:2115*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2115*FLEN/8, x2, x5, x6)

inst_741:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0bf and fs2 == 1 and fe2 == 0x0f and fm2 == 0x323 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03c and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74bf; op2val:0xbf23;
op3val:0x783c; valaddr_reg:x1; val_offset:2118*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2118*FLEN/8, x2, x5, x6)

inst_742:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0bf and fs2 == 1 and fe2 == 0x0f and fm2 == 0x323 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03c and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74bf; op2val:0xbf23;
op3val:0x783c; valaddr_reg:x1; val_offset:2121*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2121*FLEN/8, x2, x5, x6)

inst_743:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0bf and fs2 == 1 and fe2 == 0x0f and fm2 == 0x323 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03c and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74bf; op2val:0xbf23;
op3val:0x783c; valaddr_reg:x1; val_offset:2124*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2124*FLEN/8, x2, x5, x6)

inst_744:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0bf and fs2 == 1 and fe2 == 0x0f and fm2 == 0x323 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03c and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74bf; op2val:0xbf23;
op3val:0x783c; valaddr_reg:x1; val_offset:2127*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2127*FLEN/8, x2, x5, x6)

inst_745:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x36d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x238 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1c6 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x776d; op2val:0xba38;
op3val:0x75c6; valaddr_reg:x1; val_offset:2130*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2130*FLEN/8, x2, x5, x6)

inst_746:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x36d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x238 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1c6 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x776d; op2val:0xba38;
op3val:0x75c6; valaddr_reg:x1; val_offset:2133*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2133*FLEN/8, x2, x5, x6)

inst_747:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x36d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x238 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1c6 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x776d; op2val:0xba38;
op3val:0x75c6; valaddr_reg:x1; val_offset:2136*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2136*FLEN/8, x2, x5, x6)

inst_748:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x36d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x238 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1c6 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x776d; op2val:0xba38;
op3val:0x75c6; valaddr_reg:x1; val_offset:2139*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2139*FLEN/8, x2, x5, x6)

inst_749:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x36d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x238 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1c6 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x776d; op2val:0xba38;
op3val:0x75c6; valaddr_reg:x1; val_offset:2142*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2142*FLEN/8, x2, x5, x6)

inst_750:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x258 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b9 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f5; op2val:0xba58;
op3val:0x78b9; valaddr_reg:x1; val_offset:2145*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2145*FLEN/8, x2, x5, x6)

inst_751:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x258 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b9 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f5; op2val:0xba58;
op3val:0x78b9; valaddr_reg:x1; val_offset:2148*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2148*FLEN/8, x2, x5, x6)

inst_752:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x258 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b9 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f5; op2val:0xba58;
op3val:0x78b9; valaddr_reg:x1; val_offset:2151*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2151*FLEN/8, x2, x5, x6)

inst_753:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x258 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b9 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f5; op2val:0xba58;
op3val:0x78b9; valaddr_reg:x1; val_offset:2154*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2154*FLEN/8, x2, x5, x6)

inst_754:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x258 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0b9 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f5; op2val:0xba58;
op3val:0x78b9; valaddr_reg:x1; val_offset:2157*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2157*FLEN/8, x2, x5, x6)

inst_755:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x0a9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2ed and fs3 == 0 and fe3 == 0x1d and fm3 == 0x009 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x68a9; op2val:0xc6ed;
op3val:0x7409; valaddr_reg:x1; val_offset:2160*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2160*FLEN/8, x2, x5, x6)

inst_756:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x0a9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2ed and fs3 == 0 and fe3 == 0x1d and fm3 == 0x009 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x68a9; op2val:0xc6ed;
op3val:0x7409; valaddr_reg:x1; val_offset:2163*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2163*FLEN/8, x2, x5, x6)

inst_757:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x0a9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2ed and fs3 == 0 and fe3 == 0x1d and fm3 == 0x009 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x68a9; op2val:0xc6ed;
op3val:0x7409; valaddr_reg:x1; val_offset:2166*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2166*FLEN/8, x2, x5, x6)

inst_758:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x0a9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2ed and fs3 == 0 and fe3 == 0x1d and fm3 == 0x009 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x68a9; op2val:0xc6ed;
op3val:0x7409; valaddr_reg:x1; val_offset:2169*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2169*FLEN/8, x2, x5, x6)

inst_759:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x0a9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2ed and fs3 == 0 and fe3 == 0x1d and fm3 == 0x009 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x68a9; op2val:0xc6ed;
op3val:0x7409; valaddr_reg:x1; val_offset:2172*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2172*FLEN/8, x2, x5, x6)

inst_760:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x005 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x354 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7749; op2val:0xc005;
op3val:0x7b54; valaddr_reg:x1; val_offset:2175*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2175*FLEN/8, x2, x5, x6)

inst_761:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x005 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x354 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7749; op2val:0xc005;
op3val:0x7b54; valaddr_reg:x1; val_offset:2178*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2178*FLEN/8, x2, x5, x6)

inst_762:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x005 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x354 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7749; op2val:0xc005;
op3val:0x7b54; valaddr_reg:x1; val_offset:2181*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2181*FLEN/8, x2, x5, x6)

inst_763:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x005 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x354 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7749; op2val:0xc005;
op3val:0x7b54; valaddr_reg:x1; val_offset:2184*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2184*FLEN/8, x2, x5, x6)

inst_764:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x005 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x354 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7749; op2val:0xc005;
op3val:0x7b54; valaddr_reg:x1; val_offset:2187*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2187*FLEN/8, x2, x5, x6)

inst_765:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x319 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ea and fs3 == 0 and fe3 == 0x1e and fm3 == 0x05c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b19; op2val:0xb8ea;
op3val:0x785c; valaddr_reg:x1; val_offset:2190*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2190*FLEN/8, x2, x5, x6)

inst_766:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x319 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ea and fs3 == 0 and fe3 == 0x1e and fm3 == 0x05c and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b19; op2val:0xb8ea;
op3val:0x785c; valaddr_reg:x1; val_offset:2193*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2193*FLEN/8, x2, x5, x6)

inst_767:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x319 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ea and fs3 == 0 and fe3 == 0x1e and fm3 == 0x05c and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b19; op2val:0xb8ea;
op3val:0x785c; valaddr_reg:x1; val_offset:2196*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2196*FLEN/8, x2, x5, x6)

inst_768:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x319 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ea and fs3 == 0 and fe3 == 0x1e and fm3 == 0x05c and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b19; op2val:0xb8ea;
op3val:0x785c; valaddr_reg:x1; val_offset:2199*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2199*FLEN/8, x2, x5, x6)

inst_769:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x319 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ea and fs3 == 0 and fe3 == 0x1e and fm3 == 0x05c and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b19; op2val:0xb8ea;
op3val:0x785c; valaddr_reg:x1; val_offset:2202*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2202*FLEN/8, x2, x5, x6)

inst_770:
// fs1 == 0 and fe1 == 0x18 and fm1 == 0x375 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x2ac and fs3 == 0 and fe3 == 0x1e and fm3 == 0x239 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6375; op2val:0xd2ac;
op3val:0x7a39; valaddr_reg:x1; val_offset:2205*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2205*FLEN/8, x2, x5, x6)

inst_771:
// fs1 == 0 and fe1 == 0x18 and fm1 == 0x375 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x2ac and fs3 == 0 and fe3 == 0x1e and fm3 == 0x239 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6375; op2val:0xd2ac;
op3val:0x7a39; valaddr_reg:x1; val_offset:2208*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2208*FLEN/8, x2, x5, x6)

inst_772:
// fs1 == 0 and fe1 == 0x18 and fm1 == 0x375 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x2ac and fs3 == 0 and fe3 == 0x1e and fm3 == 0x239 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6375; op2val:0xd2ac;
op3val:0x7a39; valaddr_reg:x1; val_offset:2211*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2211*FLEN/8, x2, x5, x6)

inst_773:
// fs1 == 0 and fe1 == 0x18 and fm1 == 0x375 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x2ac and fs3 == 0 and fe3 == 0x1e and fm3 == 0x239 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6375; op2val:0xd2ac;
op3val:0x7a39; valaddr_reg:x1; val_offset:2214*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2214*FLEN/8, x2, x5, x6)

inst_774:
// fs1 == 0 and fe1 == 0x18 and fm1 == 0x375 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x2ac and fs3 == 0 and fe3 == 0x1e and fm3 == 0x239 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6375; op2val:0xd2ac;
op3val:0x7a39; valaddr_reg:x1; val_offset:2217*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2217*FLEN/8, x2, x5, x6)

inst_775:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2d7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x162 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x09a and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76d7; op2val:0xbd62;
op3val:0x789a; valaddr_reg:x1; val_offset:2220*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2220*FLEN/8, x2, x5, x6)

inst_776:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2d7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x162 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x09a and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76d7; op2val:0xbd62;
op3val:0x789a; valaddr_reg:x1; val_offset:2223*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2223*FLEN/8, x2, x5, x6)

inst_777:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2d7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x162 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x09a and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76d7; op2val:0xbd62;
op3val:0x789a; valaddr_reg:x1; val_offset:2226*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2226*FLEN/8, x2, x5, x6)

inst_778:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2d7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x162 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x09a and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76d7; op2val:0xbd62;
op3val:0x789a; valaddr_reg:x1; val_offset:2229*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2229*FLEN/8, x2, x5, x6)

inst_779:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2d7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x162 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x09a and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76d7; op2val:0xbd62;
op3val:0x789a; valaddr_reg:x1; val_offset:2232*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2232*FLEN/8, x2, x5, x6)

inst_780:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x324 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x10e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a9; op2val:0xbb24;
op3val:0x790e; valaddr_reg:x1; val_offset:2235*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2235*FLEN/8, x2, x5, x6)

inst_781:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x324 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x10e and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a9; op2val:0xbb24;
op3val:0x790e; valaddr_reg:x1; val_offset:2238*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2238*FLEN/8, x2, x5, x6)

inst_782:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x324 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x10e and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a9; op2val:0xbb24;
op3val:0x790e; valaddr_reg:x1; val_offset:2241*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2241*FLEN/8, x2, x5, x6)

inst_783:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x324 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x10e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a9; op2val:0xbb24;
op3val:0x790e; valaddr_reg:x1; val_offset:2244*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2244*FLEN/8, x2, x5, x6)

inst_784:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x324 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x10e and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a9; op2val:0xbb24;
op3val:0x790e; valaddr_reg:x1; val_offset:2247*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2247*FLEN/8, x2, x5, x6)

inst_785:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3b4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x391 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x34a and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77b4; op2val:0xbf91;
op3val:0x7b4a; valaddr_reg:x1; val_offset:2250*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2250*FLEN/8, x2, x5, x6)

inst_786:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3b4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x391 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x34a and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77b4; op2val:0xbf91;
op3val:0x7b4a; valaddr_reg:x1; val_offset:2253*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2253*FLEN/8, x2, x5, x6)

inst_787:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3b4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x391 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x34a and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77b4; op2val:0xbf91;
op3val:0x7b4a; valaddr_reg:x1; val_offset:2256*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2256*FLEN/8, x2, x5, x6)

inst_788:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3b4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x391 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x34a and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77b4; op2val:0xbf91;
op3val:0x7b4a; valaddr_reg:x1; val_offset:2259*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2259*FLEN/8, x2, x5, x6)

inst_789:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3b4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x391 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x34a and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77b4; op2val:0xbf91;
op3val:0x7b4a; valaddr_reg:x1; val_offset:2262*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2262*FLEN/8, x2, x5, x6)

inst_790:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x010 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x244 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x762a; op2val:0xbc10;
op3val:0x7644; valaddr_reg:x1; val_offset:2265*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2265*FLEN/8, x2, x5, x6)

inst_791:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x010 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x244 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x762a; op2val:0xbc10;
op3val:0x7644; valaddr_reg:x1; val_offset:2268*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2268*FLEN/8, x2, x5, x6)

inst_792:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x010 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x244 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x762a; op2val:0xbc10;
op3val:0x7644; valaddr_reg:x1; val_offset:2271*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2271*FLEN/8, x2, x5, x6)

inst_793:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x010 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x244 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x762a; op2val:0xbc10;
op3val:0x7644; valaddr_reg:x1; val_offset:2274*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2274*FLEN/8, x2, x5, x6)

inst_794:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x010 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x244 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x762a; op2val:0xbc10;
op3val:0x7644; valaddr_reg:x1; val_offset:2277*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2277*FLEN/8, x2, x5, x6)

inst_795:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2cf and fs2 == 1 and fe2 == 0x0c and fm2 == 0x361 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x248 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7acf; op2val:0xb361;
op3val:0x7248; valaddr_reg:x1; val_offset:2280*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2280*FLEN/8, x2, x5, x6)
RVTEST_SIGBASE(x5,signature_x5_6)

inst_796:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2cf and fs2 == 1 and fe2 == 0x0c and fm2 == 0x361 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x248 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7acf; op2val:0xb361;
op3val:0x7248; valaddr_reg:x1; val_offset:2283*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2283*FLEN/8, x2, x5, x6)

inst_797:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2cf and fs2 == 1 and fe2 == 0x0c and fm2 == 0x361 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x248 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7acf; op2val:0xb361;
op3val:0x7248; valaddr_reg:x1; val_offset:2286*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2286*FLEN/8, x2, x5, x6)

inst_798:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2cf and fs2 == 1 and fe2 == 0x0c and fm2 == 0x361 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x248 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7acf; op2val:0xb361;
op3val:0x7248; valaddr_reg:x1; val_offset:2289*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2289*FLEN/8, x2, x5, x6)

inst_799:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2cf and fs2 == 1 and fe2 == 0x0c and fm2 == 0x361 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x248 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7acf; op2val:0xb361;
op3val:0x7248; valaddr_reg:x1; val_offset:2292*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2292*FLEN/8, x2, x5, x6)

inst_800:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x10 and fm2 == 0x199 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a3 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74bd; op2val:0xc199;
op3val:0x7aa3; valaddr_reg:x1; val_offset:2295*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2295*FLEN/8, x2, x5, x6)

inst_801:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x10 and fm2 == 0x199 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a3 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74bd; op2val:0xc199;
op3val:0x7aa3; valaddr_reg:x1; val_offset:2298*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2298*FLEN/8, x2, x5, x6)

inst_802:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x10 and fm2 == 0x199 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a3 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74bd; op2val:0xc199;
op3val:0x7aa3; valaddr_reg:x1; val_offset:2301*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2301*FLEN/8, x2, x5, x6)

inst_803:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x10 and fm2 == 0x199 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a3 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74bd; op2val:0xc199;
op3val:0x7aa3; valaddr_reg:x1; val_offset:2304*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2304*FLEN/8, x2, x5, x6)

inst_804:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x10 and fm2 == 0x199 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2a3 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74bd; op2val:0xc199;
op3val:0x7aa3; valaddr_reg:x1; val_offset:2307*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2307*FLEN/8, x2, x5, x6)

inst_805:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x039 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x254 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2af and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c39; op2val:0xca54;
op3val:0x7aaf; valaddr_reg:x1; val_offset:2310*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2310*FLEN/8, x2, x5, x6)

inst_806:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x039 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x254 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2af and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c39; op2val:0xca54;
op3val:0x7aaf; valaddr_reg:x1; val_offset:2313*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2313*FLEN/8, x2, x5, x6)

inst_807:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x039 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x254 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2af and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c39; op2val:0xca54;
op3val:0x7aaf; valaddr_reg:x1; val_offset:2316*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2316*FLEN/8, x2, x5, x6)

inst_808:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x039 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x254 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2af and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c39; op2val:0xca54;
op3val:0x7aaf; valaddr_reg:x1; val_offset:2319*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2319*FLEN/8, x2, x5, x6)

inst_809:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x039 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x254 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2af and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c39; op2val:0xca54;
op3val:0x7aaf; valaddr_reg:x1; val_offset:2322*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2322*FLEN/8, x2, x5, x6)

inst_810:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x18d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0fc and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ec and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x798d; op2val:0xb8fc;
op3val:0x76ec; valaddr_reg:x1; val_offset:2325*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2325*FLEN/8, x2, x5, x6)

inst_811:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x18d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0fc and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ec and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x798d; op2val:0xb8fc;
op3val:0x76ec; valaddr_reg:x1; val_offset:2328*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2328*FLEN/8, x2, x5, x6)

inst_812:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x18d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0fc and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ec and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x798d; op2val:0xb8fc;
op3val:0x76ec; valaddr_reg:x1; val_offset:2331*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2331*FLEN/8, x2, x5, x6)

inst_813:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x18d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0fc and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ec and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x798d; op2val:0xb8fc;
op3val:0x76ec; valaddr_reg:x1; val_offset:2334*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2334*FLEN/8, x2, x5, x6)

inst_814:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x18d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0fc and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ec and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x798d; op2val:0xb8fc;
op3val:0x76ec; valaddr_reg:x1; val_offset:2337*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2337*FLEN/8, x2, x5, x6)

inst_815:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x094 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x173 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7494; op2val:0xc173;
op3val:0x7a3e; valaddr_reg:x1; val_offset:2340*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2340*FLEN/8, x2, x5, x6)

inst_816:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x094 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x173 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23e and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7494; op2val:0xc173;
op3val:0x7a3e; valaddr_reg:x1; val_offset:2343*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2343*FLEN/8, x2, x5, x6)

inst_817:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x094 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x173 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23e and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7494; op2val:0xc173;
op3val:0x7a3e; valaddr_reg:x1; val_offset:2346*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2346*FLEN/8, x2, x5, x6)

inst_818:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x094 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x173 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7494; op2val:0xc173;
op3val:0x7a3e; valaddr_reg:x1; val_offset:2349*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2349*FLEN/8, x2, x5, x6)

inst_819:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x094 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x173 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x23e and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7494; op2val:0xc173;
op3val:0x7a3e; valaddr_reg:x1; val_offset:2352*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2352*FLEN/8, x2, x5, x6)

inst_820:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x348 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x103 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x090 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b48; op2val:0xb103;
op3val:0x7090; valaddr_reg:x1; val_offset:2355*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2355*FLEN/8, x2, x5, x6)

inst_821:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x348 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x103 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x090 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b48; op2val:0xb103;
op3val:0x7090; valaddr_reg:x1; val_offset:2358*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2358*FLEN/8, x2, x5, x6)

inst_822:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x348 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x103 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x090 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b48; op2val:0xb103;
op3val:0x7090; valaddr_reg:x1; val_offset:2361*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2361*FLEN/8, x2, x5, x6)

inst_823:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x348 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x103 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x090 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b48; op2val:0xb103;
op3val:0x7090; valaddr_reg:x1; val_offset:2364*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2364*FLEN/8, x2, x5, x6)

inst_824:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x348 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x103 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x090 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b48; op2val:0xb103;
op3val:0x7090; valaddr_reg:x1; val_offset:2367*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2367*FLEN/8, x2, x5, x6)

inst_825:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a6 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x097 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x064 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77a6; op2val:0xbc97;
op3val:0x7864; valaddr_reg:x1; val_offset:2370*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2370*FLEN/8, x2, x5, x6)

inst_826:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a6 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x097 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x064 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77a6; op2val:0xbc97;
op3val:0x7864; valaddr_reg:x1; val_offset:2373*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2373*FLEN/8, x2, x5, x6)

inst_827:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a6 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x097 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x064 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77a6; op2val:0xbc97;
op3val:0x7864; valaddr_reg:x1; val_offset:2376*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2376*FLEN/8, x2, x5, x6)

inst_828:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a6 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x097 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x064 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77a6; op2val:0xbc97;
op3val:0x7864; valaddr_reg:x1; val_offset:2379*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2379*FLEN/8, x2, x5, x6)

inst_829:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a6 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x097 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x064 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77a6; op2val:0xbc97;
op3val:0x7864; valaddr_reg:x1; val_offset:2382*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2382*FLEN/8, x2, x5, x6)

inst_830:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3f5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x151 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x14a and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77f5; op2val:0xb951;
op3val:0x754a; valaddr_reg:x1; val_offset:2385*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2385*FLEN/8, x2, x5, x6)

inst_831:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3f5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x151 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x14a and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77f5; op2val:0xb951;
op3val:0x754a; valaddr_reg:x1; val_offset:2388*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2388*FLEN/8, x2, x5, x6)

inst_832:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3f5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x151 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x14a and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77f5; op2val:0xb951;
op3val:0x754a; valaddr_reg:x1; val_offset:2391*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2391*FLEN/8, x2, x5, x6)

inst_833:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3f5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x151 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x14a and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77f5; op2val:0xb951;
op3val:0x754a; valaddr_reg:x1; val_offset:2394*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2394*FLEN/8, x2, x5, x6)

inst_834:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3f5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x151 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x14a and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77f5; op2val:0xb951;
op3val:0x754a; valaddr_reg:x1; val_offset:2397*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2397*FLEN/8, x2, x5, x6)

inst_835:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0e9 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3a1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0af and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70e9; op2val:0xc3a1;
op3val:0x78af; valaddr_reg:x1; val_offset:2400*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2400*FLEN/8, x2, x5, x6)

inst_836:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0e9 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3a1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0af and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70e9; op2val:0xc3a1;
op3val:0x78af; valaddr_reg:x1; val_offset:2403*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2403*FLEN/8, x2, x5, x6)

inst_837:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0e9 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3a1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0af and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70e9; op2val:0xc3a1;
op3val:0x78af; valaddr_reg:x1; val_offset:2406*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2406*FLEN/8, x2, x5, x6)

inst_838:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0e9 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3a1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0af and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70e9; op2val:0xc3a1;
op3val:0x78af; valaddr_reg:x1; val_offset:2409*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2409*FLEN/8, x2, x5, x6)

inst_839:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0e9 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3a1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0af and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70e9; op2val:0xc3a1;
op3val:0x78af; valaddr_reg:x1; val_offset:2412*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2412*FLEN/8, x2, x5, x6)

inst_840:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27d and fs2 == 1 and fe2 == 0x0b and fm2 == 0x151 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x060 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a7d; op2val:0xad51;
op3val:0x6c60; valaddr_reg:x1; val_offset:2415*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2415*FLEN/8, x2, x5, x6)

inst_841:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27d and fs2 == 1 and fe2 == 0x0b and fm2 == 0x151 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x060 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a7d; op2val:0xad51;
op3val:0x6c60; valaddr_reg:x1; val_offset:2418*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2418*FLEN/8, x2, x5, x6)

inst_842:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27d and fs2 == 1 and fe2 == 0x0b and fm2 == 0x151 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x060 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a7d; op2val:0xad51;
op3val:0x6c60; valaddr_reg:x1; val_offset:2421*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2421*FLEN/8, x2, x5, x6)

inst_843:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27d and fs2 == 1 and fe2 == 0x0b and fm2 == 0x151 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x060 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a7d; op2val:0xad51;
op3val:0x6c60; valaddr_reg:x1; val_offset:2424*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2424*FLEN/8, x2, x5, x6)

inst_844:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27d and fs2 == 1 and fe2 == 0x0b and fm2 == 0x151 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x060 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a7d; op2val:0xad51;
op3val:0x6c60; valaddr_reg:x1; val_offset:2427*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2427*FLEN/8, x2, x5, x6)

inst_845:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x35b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x31e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x28d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x735b; op2val:0xc31e;
op3val:0x7a8d; valaddr_reg:x1; val_offset:2430*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2430*FLEN/8, x2, x5, x6)

inst_846:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x35b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x31e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x28d and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x735b; op2val:0xc31e;
op3val:0x7a8d; valaddr_reg:x1; val_offset:2433*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2433*FLEN/8, x2, x5, x6)

inst_847:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x35b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x31e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x28d and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x735b; op2val:0xc31e;
op3val:0x7a8d; valaddr_reg:x1; val_offset:2436*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2436*FLEN/8, x2, x5, x6)

inst_848:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x35b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x31e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x28d and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x735b; op2val:0xc31e;
op3val:0x7a8d; valaddr_reg:x1; val_offset:2439*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2439*FLEN/8, x2, x5, x6)

inst_849:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x35b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x31e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x28d and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x735b; op2val:0xc31e;
op3val:0x7a8d; valaddr_reg:x1; val_offset:2442*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2442*FLEN/8, x2, x5, x6)

inst_850:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x254 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2b1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a54; op2val:0xbab1;
op3val:0x794e; valaddr_reg:x1; val_offset:2445*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2445*FLEN/8, x2, x5, x6)

inst_851:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x254 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2b1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14e and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a54; op2val:0xbab1;
op3val:0x794e; valaddr_reg:x1; val_offset:2448*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2448*FLEN/8, x2, x5, x6)

inst_852:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x254 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2b1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14e and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a54; op2val:0xbab1;
op3val:0x794e; valaddr_reg:x1; val_offset:2451*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2451*FLEN/8, x2, x5, x6)

inst_853:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x254 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2b1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a54; op2val:0xbab1;
op3val:0x794e; valaddr_reg:x1; val_offset:2454*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2454*FLEN/8, x2, x5, x6)

inst_854:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x254 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2b1 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14e and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a54; op2val:0xbab1;
op3val:0x794e; valaddr_reg:x1; val_offset:2457*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2457*FLEN/8, x2, x5, x6)

inst_855:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x28a and fs2 == 1 and fe2 == 0x13 and fm2 == 0x30e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1c7 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x668a; op2val:0xcf0e;
op3val:0x79c7; valaddr_reg:x1; val_offset:2460*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2460*FLEN/8, x2, x5, x6)

inst_856:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x28a and fs2 == 1 and fe2 == 0x13 and fm2 == 0x30e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1c7 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x668a; op2val:0xcf0e;
op3val:0x79c7; valaddr_reg:x1; val_offset:2463*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2463*FLEN/8, x2, x5, x6)

inst_857:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x28a and fs2 == 1 and fe2 == 0x13 and fm2 == 0x30e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1c7 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x668a; op2val:0xcf0e;
op3val:0x79c7; valaddr_reg:x1; val_offset:2466*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2466*FLEN/8, x2, x5, x6)

inst_858:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x28a and fs2 == 1 and fe2 == 0x13 and fm2 == 0x30e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1c7 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x668a; op2val:0xcf0e;
op3val:0x79c7; valaddr_reg:x1; val_offset:2469*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2469*FLEN/8, x2, x5, x6)

inst_859:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x28a and fs2 == 1 and fe2 == 0x13 and fm2 == 0x30e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1c7 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x668a; op2val:0xcf0e;
op3val:0x79c7; valaddr_reg:x1; val_offset:2472*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2472*FLEN/8, x2, x5, x6)

inst_860:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x013 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3fb and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd3; op2val:0xbc13;
op3val:0x7bfb; valaddr_reg:x1; val_offset:2475*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2475*FLEN/8, x2, x5, x6)

inst_861:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x013 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3fb and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd3; op2val:0xbc13;
op3val:0x7bfb; valaddr_reg:x1; val_offset:2478*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2478*FLEN/8, x2, x5, x6)

inst_862:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x013 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3fb and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd3; op2val:0xbc13;
op3val:0x7bfb; valaddr_reg:x1; val_offset:2481*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2481*FLEN/8, x2, x5, x6)

inst_863:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x013 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3fb and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd3; op2val:0xbc13;
op3val:0x7bfb; valaddr_reg:x1; val_offset:2484*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2484*FLEN/8, x2, x5, x6)

inst_864:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x013 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3fb and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bd3; op2val:0xbc13;
op3val:0x7bfb; valaddr_reg:x1; val_offset:2487*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2487*FLEN/8, x2, x5, x6)

inst_865:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19b and fs2 == 1 and fe2 == 0x0b and fm2 == 0x05f and fs3 == 0 and fe3 == 0x1a and fm3 == 0x241 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x799b; op2val:0xac5f;
op3val:0x6a41; valaddr_reg:x1; val_offset:2490*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2490*FLEN/8, x2, x5, x6)

inst_866:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19b and fs2 == 1 and fe2 == 0x0b and fm2 == 0x05f and fs3 == 0 and fe3 == 0x1a and fm3 == 0x241 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x799b; op2val:0xac5f;
op3val:0x6a41; valaddr_reg:x1; val_offset:2493*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2493*FLEN/8, x2, x5, x6)

inst_867:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19b and fs2 == 1 and fe2 == 0x0b and fm2 == 0x05f and fs3 == 0 and fe3 == 0x1a and fm3 == 0x241 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x799b; op2val:0xac5f;
op3val:0x6a41; valaddr_reg:x1; val_offset:2496*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2496*FLEN/8, x2, x5, x6)

inst_868:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19b and fs2 == 1 and fe2 == 0x0b and fm2 == 0x05f and fs3 == 0 and fe3 == 0x1a and fm3 == 0x241 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x799b; op2val:0xac5f;
op3val:0x6a41; valaddr_reg:x1; val_offset:2499*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2499*FLEN/8, x2, x5, x6)

inst_869:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19b and fs2 == 1 and fe2 == 0x0b and fm2 == 0x05f and fs3 == 0 and fe3 == 0x1a and fm3 == 0x241 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x799b; op2val:0xac5f;
op3val:0x6a41; valaddr_reg:x1; val_offset:2502*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2502*FLEN/8, x2, x5, x6)

inst_870:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2bb and fs2 == 1 and fe2 == 0x0d and fm2 == 0x025 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x303 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7abb; op2val:0xb425;
op3val:0x7303; valaddr_reg:x1; val_offset:2505*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2505*FLEN/8, x2, x5, x6)

inst_871:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2bb and fs2 == 1 and fe2 == 0x0d and fm2 == 0x025 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x303 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7abb; op2val:0xb425;
op3val:0x7303; valaddr_reg:x1; val_offset:2508*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2508*FLEN/8, x2, x5, x6)

inst_872:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2bb and fs2 == 1 and fe2 == 0x0d and fm2 == 0x025 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x303 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7abb; op2val:0xb425;
op3val:0x7303; valaddr_reg:x1; val_offset:2511*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2511*FLEN/8, x2, x5, x6)

inst_873:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2bb and fs2 == 1 and fe2 == 0x0d and fm2 == 0x025 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x303 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7abb; op2val:0xb425;
op3val:0x7303; valaddr_reg:x1; val_offset:2514*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2514*FLEN/8, x2, x5, x6)

inst_874:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2bb and fs2 == 1 and fe2 == 0x0d and fm2 == 0x025 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x303 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7abb; op2val:0xb425;
op3val:0x7303; valaddr_reg:x1; val_offset:2517*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2517*FLEN/8, x2, x5, x6)

inst_875:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x129 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x39d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7929; op2val:0xbde7;
op3val:0x7b9d; valaddr_reg:x1; val_offset:2520*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2520*FLEN/8, x2, x5, x6)

inst_876:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x129 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x39d and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7929; op2val:0xbde7;
op3val:0x7b9d; valaddr_reg:x1; val_offset:2523*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2523*FLEN/8, x2, x5, x6)

inst_877:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x129 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x39d and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7929; op2val:0xbde7;
op3val:0x7b9d; valaddr_reg:x1; val_offset:2526*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2526*FLEN/8, x2, x5, x6)

inst_878:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x129 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x39d and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7929; op2val:0xbde7;
op3val:0x7b9d; valaddr_reg:x1; val_offset:2529*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2529*FLEN/8, x2, x5, x6)

inst_879:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x129 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x39d and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7929; op2val:0xbde7;
op3val:0x7b9d; valaddr_reg:x1; val_offset:2532*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2532*FLEN/8, x2, x5, x6)

inst_880:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b2 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x217 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x04e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79b2; op2val:0xb217;
op3val:0x704e; valaddr_reg:x1; val_offset:2535*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2535*FLEN/8, x2, x5, x6)

inst_881:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b2 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x217 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x04e and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79b2; op2val:0xb217;
op3val:0x704e; valaddr_reg:x1; val_offset:2538*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2538*FLEN/8, x2, x5, x6)

inst_882:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b2 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x217 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x04e and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79b2; op2val:0xb217;
op3val:0x704e; valaddr_reg:x1; val_offset:2541*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2541*FLEN/8, x2, x5, x6)

inst_883:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b2 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x217 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x04e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79b2; op2val:0xb217;
op3val:0x704e; valaddr_reg:x1; val_offset:2544*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2544*FLEN/8, x2, x5, x6)

inst_884:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b2 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x217 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x04e and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79b2; op2val:0xb217;
op3val:0x704e; valaddr_reg:x1; val_offset:2547*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2547*FLEN/8, x2, x5, x6)

inst_885:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ad and fs2 == 1 and fe2 == 0x10 and fm2 == 0x248 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x357 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74ad; op2val:0xc248;
op3val:0x7b57; valaddr_reg:x1; val_offset:2550*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2550*FLEN/8, x2, x5, x6)

inst_886:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ad and fs2 == 1 and fe2 == 0x10 and fm2 == 0x248 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x357 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74ad; op2val:0xc248;
op3val:0x7b57; valaddr_reg:x1; val_offset:2553*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2553*FLEN/8, x2, x5, x6)

inst_887:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ad and fs2 == 1 and fe2 == 0x10 and fm2 == 0x248 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x357 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74ad; op2val:0xc248;
op3val:0x7b57; valaddr_reg:x1; val_offset:2556*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2556*FLEN/8, x2, x5, x6)

inst_888:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ad and fs2 == 1 and fe2 == 0x10 and fm2 == 0x248 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x357 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74ad; op2val:0xc248;
op3val:0x7b57; valaddr_reg:x1; val_offset:2559*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2559*FLEN/8, x2, x5, x6)

inst_889:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ad and fs2 == 1 and fe2 == 0x10 and fm2 == 0x248 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x357 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74ad; op2val:0xc248;
op3val:0x7b57; valaddr_reg:x1; val_offset:2562*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2562*FLEN/8, x2, x5, x6)

inst_890:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ca and fs2 == 1 and fe2 == 0x11 and fm2 == 0x015 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0e1 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70ca; op2val:0xc415;
op3val:0x78e1; valaddr_reg:x1; val_offset:2565*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2565*FLEN/8, x2, x5, x6)

inst_891:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ca and fs2 == 1 and fe2 == 0x11 and fm2 == 0x015 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0e1 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70ca; op2val:0xc415;
op3val:0x78e1; valaddr_reg:x1; val_offset:2568*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2568*FLEN/8, x2, x5, x6)

inst_892:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ca and fs2 == 1 and fe2 == 0x11 and fm2 == 0x015 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0e1 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70ca; op2val:0xc415;
op3val:0x78e1; valaddr_reg:x1; val_offset:2571*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2571*FLEN/8, x2, x5, x6)

inst_893:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ca and fs2 == 1 and fe2 == 0x11 and fm2 == 0x015 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0e1 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70ca; op2val:0xc415;
op3val:0x78e1; valaddr_reg:x1; val_offset:2574*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2574*FLEN/8, x2, x5, x6)

inst_894:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ca and fs2 == 1 and fe2 == 0x11 and fm2 == 0x015 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0e1 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70ca; op2val:0xc415;
op3val:0x78e1; valaddr_reg:x1; val_offset:2577*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2577*FLEN/8, x2, x5, x6)

inst_895:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x29e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x244 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x127 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x769e; op2val:0xb644;
op3val:0x7127; valaddr_reg:x1; val_offset:2580*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2580*FLEN/8, x2, x5, x6)

inst_896:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x29e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x244 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x127 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x769e; op2val:0xb644;
op3val:0x7127; valaddr_reg:x1; val_offset:2583*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2583*FLEN/8, x2, x5, x6)

inst_897:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x29e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x244 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x127 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x769e; op2val:0xb644;
op3val:0x7127; valaddr_reg:x1; val_offset:2586*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2586*FLEN/8, x2, x5, x6)

inst_898:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x29e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x244 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x127 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x769e; op2val:0xb644;
op3val:0x7127; valaddr_reg:x1; val_offset:2589*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2589*FLEN/8, x2, x5, x6)

inst_899:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x29e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x244 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x127 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x769e; op2val:0xb644;
op3val:0x7127; valaddr_reg:x1; val_offset:2592*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2592*FLEN/8, x2, x5, x6)

inst_900:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fa and fs2 == 1 and fe2 == 0x0b and fm2 == 0x094 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x193 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fa; op2val:0xac94;
op3val:0x6993; valaddr_reg:x1; val_offset:2595*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2595*FLEN/8, x2, x5, x6)

inst_901:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fa and fs2 == 1 and fe2 == 0x0b and fm2 == 0x094 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x193 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fa; op2val:0xac94;
op3val:0x6993; valaddr_reg:x1; val_offset:2598*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2598*FLEN/8, x2, x5, x6)

inst_902:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fa and fs2 == 1 and fe2 == 0x0b and fm2 == 0x094 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x193 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fa; op2val:0xac94;
op3val:0x6993; valaddr_reg:x1; val_offset:2601*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2601*FLEN/8, x2, x5, x6)

inst_903:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fa and fs2 == 1 and fe2 == 0x0b and fm2 == 0x094 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x193 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fa; op2val:0xac94;
op3val:0x6993; valaddr_reg:x1; val_offset:2604*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2604*FLEN/8, x2, x5, x6)

inst_904:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fa and fs2 == 1 and fe2 == 0x0b and fm2 == 0x094 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x193 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fa; op2val:0xac94;
op3val:0x6993; valaddr_reg:x1; val_offset:2607*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2607*FLEN/8, x2, x5, x6)

inst_905:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2ec and fs2 == 1 and fe2 == 0x10 and fm2 == 0x306 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x210 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6eec; op2val:0xc306;
op3val:0x7610; valaddr_reg:x1; val_offset:2610*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2610*FLEN/8, x2, x5, x6)

inst_906:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2ec and fs2 == 1 and fe2 == 0x10 and fm2 == 0x306 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x210 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6eec; op2val:0xc306;
op3val:0x7610; valaddr_reg:x1; val_offset:2613*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2613*FLEN/8, x2, x5, x6)

inst_907:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2ec and fs2 == 1 and fe2 == 0x10 and fm2 == 0x306 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x210 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6eec; op2val:0xc306;
op3val:0x7610; valaddr_reg:x1; val_offset:2616*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2616*FLEN/8, x2, x5, x6)

inst_908:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2ec and fs2 == 1 and fe2 == 0x10 and fm2 == 0x306 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x210 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6eec; op2val:0xc306;
op3val:0x7610; valaddr_reg:x1; val_offset:2619*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2619*FLEN/8, x2, x5, x6)

inst_909:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2ec and fs2 == 1 and fe2 == 0x10 and fm2 == 0x306 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x210 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6eec; op2val:0xc306;
op3val:0x7610; valaddr_reg:x1; val_offset:2622*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2622*FLEN/8, x2, x5, x6)

inst_910:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x09b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x281 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x35d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c9b; op2val:0xba81;
op3val:0x6b5d; valaddr_reg:x1; val_offset:2625*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2625*FLEN/8, x2, x5, x6)

inst_911:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x09b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x281 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x35d and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c9b; op2val:0xba81;
op3val:0x6b5d; valaddr_reg:x1; val_offset:2628*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2628*FLEN/8, x2, x5, x6)

inst_912:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x09b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x281 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x35d and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c9b; op2val:0xba81;
op3val:0x6b5d; valaddr_reg:x1; val_offset:2631*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2631*FLEN/8, x2, x5, x6)

inst_913:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x09b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x281 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x35d and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c9b; op2val:0xba81;
op3val:0x6b5d; valaddr_reg:x1; val_offset:2634*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2634*FLEN/8, x2, x5, x6)

inst_914:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x09b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x281 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x35d and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c9b; op2val:0xba81;
op3val:0x6b5d; valaddr_reg:x1; val_offset:2637*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2637*FLEN/8, x2, x5, x6)

inst_915:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x099 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x12b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ef and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7899; op2val:0xbd2b;
op3val:0x79ef; valaddr_reg:x1; val_offset:2640*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2640*FLEN/8, x2, x5, x6)

inst_916:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x099 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x12b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ef and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7899; op2val:0xbd2b;
op3val:0x79ef; valaddr_reg:x1; val_offset:2643*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2643*FLEN/8, x2, x5, x6)

inst_917:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x099 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x12b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ef and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7899; op2val:0xbd2b;
op3val:0x79ef; valaddr_reg:x1; val_offset:2646*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2646*FLEN/8, x2, x5, x6)

inst_918:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x099 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x12b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ef and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7899; op2val:0xbd2b;
op3val:0x79ef; valaddr_reg:x1; val_offset:2649*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2649*FLEN/8, x2, x5, x6)

inst_919:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x099 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x12b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ef and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7899; op2val:0xbd2b;
op3val:0x79ef; valaddr_reg:x1; val_offset:2652*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2652*FLEN/8, x2, x5, x6)

inst_920:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x306 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1c and fm3 == 0x04c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b06; op2val:0xb0ed;
op3val:0x704c; valaddr_reg:x1; val_offset:2655*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2655*FLEN/8, x2, x5, x6)

inst_921:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x306 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1c and fm3 == 0x04c and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b06; op2val:0xb0ed;
op3val:0x704c; valaddr_reg:x1; val_offset:2658*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2658*FLEN/8, x2, x5, x6)

inst_922:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x306 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1c and fm3 == 0x04c and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b06; op2val:0xb0ed;
op3val:0x704c; valaddr_reg:x1; val_offset:2661*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2661*FLEN/8, x2, x5, x6)

inst_923:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x306 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1c and fm3 == 0x04c and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b06; op2val:0xb0ed;
op3val:0x704c; valaddr_reg:x1; val_offset:2664*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2664*FLEN/8, x2, x5, x6)
RVTEST_SIGBASE(x5,signature_x5_7)

inst_924:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x306 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1c and fm3 == 0x04c and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b06; op2val:0xb0ed;
op3val:0x704c; valaddr_reg:x1; val_offset:2667*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2667*FLEN/8, x2, x5, x6)

inst_925:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1d9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x107 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76e7; op2val:0xb9d9;
op3val:0x7507; valaddr_reg:x1; val_offset:2670*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2670*FLEN/8, x2, x5, x6)

inst_926:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1d9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x107 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76e7; op2val:0xb9d9;
op3val:0x7507; valaddr_reg:x1; val_offset:2673*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2673*FLEN/8, x2, x5, x6)

inst_927:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1d9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x107 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76e7; op2val:0xb9d9;
op3val:0x7507; valaddr_reg:x1; val_offset:2676*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2676*FLEN/8, x2, x5, x6)

inst_928:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1d9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x107 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76e7; op2val:0xb9d9;
op3val:0x7507; valaddr_reg:x1; val_offset:2679*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2679*FLEN/8, x2, x5, x6)

inst_929:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1d9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x107 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76e7; op2val:0xb9d9;
op3val:0x7507; valaddr_reg:x1; val_offset:2682*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2682*FLEN/8, x2, x5, x6)

inst_930:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0cc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x289 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3d4 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78cc; op2val:0xba89;
op3val:0x77d4; valaddr_reg:x1; val_offset:2685*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2685*FLEN/8, x2, x5, x6)

inst_931:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0cc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x289 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3d4 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78cc; op2val:0xba89;
op3val:0x77d4; valaddr_reg:x1; val_offset:2688*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2688*FLEN/8, x2, x5, x6)

inst_932:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0cc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x289 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3d4 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78cc; op2val:0xba89;
op3val:0x77d4; valaddr_reg:x1; val_offset:2691*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2691*FLEN/8, x2, x5, x6)

inst_933:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0cc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x289 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3d4 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78cc; op2val:0xba89;
op3val:0x77d4; valaddr_reg:x1; val_offset:2694*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2694*FLEN/8, x2, x5, x6)

inst_934:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0cc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x289 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3d4 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78cc; op2val:0xba89;
op3val:0x77d4; valaddr_reg:x1; val_offset:2697*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2697*FLEN/8, x2, x5, x6)

inst_935:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x381 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x265 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1fc and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b81; op2val:0xb665;
op3val:0x75fc; valaddr_reg:x1; val_offset:2700*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2700*FLEN/8, x2, x5, x6)

inst_936:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x381 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x265 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1fc and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b81; op2val:0xb665;
op3val:0x75fc; valaddr_reg:x1; val_offset:2703*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2703*FLEN/8, x2, x5, x6)

inst_937:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x381 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x265 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1fc and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b81; op2val:0xb665;
op3val:0x75fc; valaddr_reg:x1; val_offset:2706*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2706*FLEN/8, x2, x5, x6)

inst_938:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x381 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x265 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1fc and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b81; op2val:0xb665;
op3val:0x75fc; valaddr_reg:x1; val_offset:2709*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2709*FLEN/8, x2, x5, x6)

inst_939:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x381 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x265 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1fc and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b81; op2val:0xb665;
op3val:0x75fc; valaddr_reg:x1; val_offset:2712*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2712*FLEN/8, x2, x5, x6)

inst_940:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x322 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x242 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x193 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6b22; op2val:0xca42;
op3val:0x7993; valaddr_reg:x1; val_offset:2715*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2715*FLEN/8, x2, x5, x6)

inst_941:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x322 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x242 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x193 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6b22; op2val:0xca42;
op3val:0x7993; valaddr_reg:x1; val_offset:2718*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2718*FLEN/8, x2, x5, x6)

inst_942:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x322 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x242 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x193 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6b22; op2val:0xca42;
op3val:0x7993; valaddr_reg:x1; val_offset:2721*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2721*FLEN/8, x2, x5, x6)

inst_943:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x322 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x242 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x193 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6b22; op2val:0xca42;
op3val:0x7993; valaddr_reg:x1; val_offset:2724*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2724*FLEN/8, x2, x5, x6)

inst_944:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x322 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x242 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x193 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6b22; op2val:0xca42;
op3val:0x7993; valaddr_reg:x1; val_offset:2727*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2727*FLEN/8, x2, x5, x6)

inst_945:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0d5 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x02b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x10c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70d5; op2val:0xc42b;
op3val:0x790c; valaddr_reg:x1; val_offset:2730*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2730*FLEN/8, x2, x5, x6)

inst_946:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0d5 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x02b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x10c and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70d5; op2val:0xc42b;
op3val:0x790c; valaddr_reg:x1; val_offset:2733*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2733*FLEN/8, x2, x5, x6)

inst_947:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0d5 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x02b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x10c and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70d5; op2val:0xc42b;
op3val:0x790c; valaddr_reg:x1; val_offset:2736*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2736*FLEN/8, x2, x5, x6)

inst_948:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0d5 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x02b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x10c and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70d5; op2val:0xc42b;
op3val:0x790c; valaddr_reg:x1; val_offset:2739*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2739*FLEN/8, x2, x5, x6)

inst_949:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0d5 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x02b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x10c and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70d5; op2val:0xc42b;
op3val:0x790c; valaddr_reg:x1; val_offset:2742*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2742*FLEN/8, x2, x5, x6)

inst_950:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x331 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x347 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x780b; op2val:0xbf31;
op3val:0x7b47; valaddr_reg:x1; val_offset:2745*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2745*FLEN/8, x2, x5, x6)

inst_951:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x331 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x347 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x780b; op2val:0xbf31;
op3val:0x7b47; valaddr_reg:x1; val_offset:2748*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2748*FLEN/8, x2, x5, x6)

inst_952:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x331 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x347 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x780b; op2val:0xbf31;
op3val:0x7b47; valaddr_reg:x1; val_offset:2751*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2751*FLEN/8, x2, x5, x6)

inst_953:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x331 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x347 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x780b; op2val:0xbf31;
op3val:0x7b47; valaddr_reg:x1; val_offset:2754*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2754*FLEN/8, x2, x5, x6)

inst_954:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x331 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x347 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x780b; op2val:0xbf31;
op3val:0x7b47; valaddr_reg:x1; val_offset:2757*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2757*FLEN/8, x2, x5, x6)

inst_955:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x06f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x077 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f6 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x786f; op2val:0xbc77;
op3val:0x78f6; valaddr_reg:x1; val_offset:2760*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2760*FLEN/8, x2, x5, x6)

inst_956:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x06f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x077 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f6 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x786f; op2val:0xbc77;
op3val:0x78f6; valaddr_reg:x1; val_offset:2763*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2763*FLEN/8, x2, x5, x6)

inst_957:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x06f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x077 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f6 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x786f; op2val:0xbc77;
op3val:0x78f6; valaddr_reg:x1; val_offset:2766*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2766*FLEN/8, x2, x5, x6)

inst_958:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x06f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x077 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f6 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x786f; op2val:0xbc77;
op3val:0x78f6; valaddr_reg:x1; val_offset:2769*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2769*FLEN/8, x2, x5, x6)

inst_959:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x06f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x077 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0f6 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x786f; op2val:0xbc77;
op3val:0x78f6; valaddr_reg:x1; val_offset:2772*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2772*FLEN/8, x2, x5, x6)

inst_960:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x035 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x02f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x069 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7435; op2val:0xc02f;
op3val:0x7869; valaddr_reg:x1; val_offset:2775*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2775*FLEN/8, x2, x5, x6)

inst_961:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x035 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x02f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x069 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7435; op2val:0xc02f;
op3val:0x7869; valaddr_reg:x1; val_offset:2778*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2778*FLEN/8, x2, x5, x6)

inst_962:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x035 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x02f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x069 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7435; op2val:0xc02f;
op3val:0x7869; valaddr_reg:x1; val_offset:2781*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2781*FLEN/8, x2, x5, x6)

inst_963:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x035 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x02f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x069 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7435; op2val:0xc02f;
op3val:0x7869; valaddr_reg:x1; val_offset:2784*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2784*FLEN/8, x2, x5, x6)

inst_964:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x035 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x02f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x069 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7435; op2val:0xc02f;
op3val:0x7869; valaddr_reg:x1; val_offset:2787*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2787*FLEN/8, x2, x5, x6)

inst_965:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x010 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x200 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7410; op2val:0xc1e5;
op3val:0x7a00; valaddr_reg:x1; val_offset:2790*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2790*FLEN/8, x2, x5, x6)

inst_966:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x010 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x200 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7410; op2val:0xc1e5;
op3val:0x7a00; valaddr_reg:x1; val_offset:2793*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2793*FLEN/8, x2, x5, x6)

inst_967:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x010 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x200 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7410; op2val:0xc1e5;
op3val:0x7a00; valaddr_reg:x1; val_offset:2796*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2796*FLEN/8, x2, x5, x6)

inst_968:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x010 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x200 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7410; op2val:0xc1e5;
op3val:0x7a00; valaddr_reg:x1; val_offset:2799*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2799*FLEN/8, x2, x5, x6)

inst_969:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x010 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x200 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7410; op2val:0xc1e5;
op3val:0x7a00; valaddr_reg:x1; val_offset:2802*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2802*FLEN/8, x2, x5, x6)

inst_970:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x022 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x01c and fs3 == 0 and fe3 == 0x1c and fm3 == 0x047 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7822; op2val:0xb41c;
op3val:0x7047; valaddr_reg:x1; val_offset:2805*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2805*FLEN/8, x2, x5, x6)

inst_971:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x022 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x01c and fs3 == 0 and fe3 == 0x1c and fm3 == 0x047 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7822; op2val:0xb41c;
op3val:0x7047; valaddr_reg:x1; val_offset:2808*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2808*FLEN/8, x2, x5, x6)

inst_972:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x022 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x01c and fs3 == 0 and fe3 == 0x1c and fm3 == 0x047 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7822; op2val:0xb41c;
op3val:0x7047; valaddr_reg:x1; val_offset:2811*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2811*FLEN/8, x2, x5, x6)

inst_973:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x022 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x01c and fs3 == 0 and fe3 == 0x1c and fm3 == 0x047 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7822; op2val:0xb41c;
op3val:0x7047; valaddr_reg:x1; val_offset:2814*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2814*FLEN/8, x2, x5, x6)

inst_974:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x022 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x01c and fs3 == 0 and fe3 == 0x1c and fm3 == 0x047 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7822; op2val:0xb41c;
op3val:0x7047; valaddr_reg:x1; val_offset:2817*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2817*FLEN/8, x2, x5, x6)

inst_975:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x37f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x251 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1ef and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x737f; op2val:0xbe51;
op3val:0x75ef; valaddr_reg:x1; val_offset:2820*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2820*FLEN/8, x2, x5, x6)

inst_976:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x37f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x251 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1ef and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x737f; op2val:0xbe51;
op3val:0x75ef; valaddr_reg:x1; val_offset:2823*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2823*FLEN/8, x2, x5, x6)

inst_977:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x37f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x251 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1ef and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x737f; op2val:0xbe51;
op3val:0x75ef; valaddr_reg:x1; val_offset:2826*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2826*FLEN/8, x2, x5, x6)

inst_978:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x37f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x251 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1ef and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x737f; op2val:0xbe51;
op3val:0x75ef; valaddr_reg:x1; val_offset:2829*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2829*FLEN/8, x2, x5, x6)

inst_979:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x37f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x251 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1ef and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x737f; op2val:0xbe51;
op3val:0x75ef; valaddr_reg:x1; val_offset:2832*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2832*FLEN/8, x2, x5, x6)

inst_980:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e4 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3c9 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1bc and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79e4; op2val:0xb3c9;
op3val:0x71bc; valaddr_reg:x1; val_offset:2835*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2835*FLEN/8, x2, x5, x6)

inst_981:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e4 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3c9 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1bc and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79e4; op2val:0xb3c9;
op3val:0x71bc; valaddr_reg:x1; val_offset:2838*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2838*FLEN/8, x2, x5, x6)

inst_982:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e4 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3c9 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1bc and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79e4; op2val:0xb3c9;
op3val:0x71bc; valaddr_reg:x1; val_offset:2841*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2841*FLEN/8, x2, x5, x6)

inst_983:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e4 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3c9 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1bc and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79e4; op2val:0xb3c9;
op3val:0x71bc; valaddr_reg:x1; val_offset:2844*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2844*FLEN/8, x2, x5, x6)

inst_984:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e4 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3c9 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1bc and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79e4; op2val:0xb3c9;
op3val:0x71bc; valaddr_reg:x1; val_offset:2847*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2847*FLEN/8, x2, x5, x6)

inst_985:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x358 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x13c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79b4; op2val:0xbb58;
op3val:0x793c; valaddr_reg:x1; val_offset:2850*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2850*FLEN/8, x2, x5, x6)

inst_986:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x358 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x13c and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79b4; op2val:0xbb58;
op3val:0x793c; valaddr_reg:x1; val_offset:2853*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2853*FLEN/8, x2, x5, x6)

inst_987:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x358 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x13c and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79b4; op2val:0xbb58;
op3val:0x793c; valaddr_reg:x1; val_offset:2856*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2856*FLEN/8, x2, x5, x6)

inst_988:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x358 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x13c and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79b4; op2val:0xbb58;
op3val:0x793c; valaddr_reg:x1; val_offset:2859*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2859*FLEN/8, x2, x5, x6)

inst_989:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x358 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x13c and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79b4; op2val:0xbb58;
op3val:0x793c; valaddr_reg:x1; val_offset:2862*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2862*FLEN/8, x2, x5, x6)

inst_990:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x174 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x3d5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x157 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d74; op2val:0xc7d5;
op3val:0x7957; valaddr_reg:x1; val_offset:2865*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2865*FLEN/8, x2, x5, x6)

inst_991:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x174 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x3d5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x157 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d74; op2val:0xc7d5;
op3val:0x7957; valaddr_reg:x1; val_offset:2868*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2868*FLEN/8, x2, x5, x6)

inst_992:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x174 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x3d5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x157 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d74; op2val:0xc7d5;
op3val:0x7957; valaddr_reg:x1; val_offset:2871*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2871*FLEN/8, x2, x5, x6)

inst_993:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x174 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x3d5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x157 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d74; op2val:0xc7d5;
op3val:0x7957; valaddr_reg:x1; val_offset:2874*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2874*FLEN/8, x2, x5, x6)

inst_994:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x174 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x3d5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x157 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d74; op2val:0xc7d5;
op3val:0x7957; valaddr_reg:x1; val_offset:2877*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2877*FLEN/8, x2, x5, x6)

inst_995:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x179 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x3fb and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dd5; op2val:0xbd79;
op3val:0x6ffb; valaddr_reg:x1; val_offset:2880*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2880*FLEN/8, x2, x5, x6)

inst_996:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x179 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x3fb and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dd5; op2val:0xbd79;
op3val:0x6ffb; valaddr_reg:x1; val_offset:2883*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2883*FLEN/8, x2, x5, x6)

inst_997:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x179 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x3fb and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dd5; op2val:0xbd79;
op3val:0x6ffb; valaddr_reg:x1; val_offset:2886*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2886*FLEN/8, x2, x5, x6)

inst_998:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x179 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x3fb and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dd5; op2val:0xbd79;
op3val:0x6ffb; valaddr_reg:x1; val_offset:2889*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2889*FLEN/8, x2, x5, x6)

inst_999:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x179 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x3fb and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6dd5; op2val:0xbd79;
op3val:0x6ffb; valaddr_reg:x1; val_offset:2892*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2892*FLEN/8, x2, x5, x6)

inst_1000:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bf and fs2 == 1 and fe2 == 0x0d and fm2 == 0x26d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3a1 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78bf; op2val:0xb66d;
op3val:0x73a1; valaddr_reg:x1; val_offset:2895*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2895*FLEN/8, x2, x5, x6)

inst_1001:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bf and fs2 == 1 and fe2 == 0x0d and fm2 == 0x26d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3a1 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78bf; op2val:0xb66d;
op3val:0x73a1; valaddr_reg:x1; val_offset:2898*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2898*FLEN/8, x2, x5, x6)

inst_1002:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bf and fs2 == 1 and fe2 == 0x0d and fm2 == 0x26d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3a1 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78bf; op2val:0xb66d;
op3val:0x73a1; valaddr_reg:x1; val_offset:2901*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2901*FLEN/8, x2, x5, x6)

inst_1003:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bf and fs2 == 1 and fe2 == 0x0d and fm2 == 0x26d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3a1 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78bf; op2val:0xb66d;
op3val:0x73a1; valaddr_reg:x1; val_offset:2904*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2904*FLEN/8, x2, x5, x6)

inst_1004:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bf and fs2 == 1 and fe2 == 0x0d and fm2 == 0x26d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3a1 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78bf; op2val:0xb66d;
op3val:0x73a1; valaddr_reg:x1; val_offset:2907*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2907*FLEN/8, x2, x5, x6)

inst_1005:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x303 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x062 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3af and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b03; op2val:0xb862;
op3val:0x77af; valaddr_reg:x1; val_offset:2910*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2910*FLEN/8, x2, x5, x6)

inst_1006:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x303 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x062 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3af and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b03; op2val:0xb862;
op3val:0x77af; valaddr_reg:x1; val_offset:2913*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2913*FLEN/8, x2, x5, x6)

inst_1007:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x303 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x062 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3af and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b03; op2val:0xb862;
op3val:0x77af; valaddr_reg:x1; val_offset:2916*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2916*FLEN/8, x2, x5, x6)

inst_1008:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x303 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x062 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3af and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b03; op2val:0xb862;
op3val:0x77af; valaddr_reg:x1; val_offset:2919*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2919*FLEN/8, x2, x5, x6)

inst_1009:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x303 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x062 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3af and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b03; op2val:0xb862;
op3val:0x77af; valaddr_reg:x1; val_offset:2922*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2922*FLEN/8, x2, x5, x6)

inst_1010:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x12b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1e and fm3 == 0x25e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x752b; op2val:0xc0ed;
op3val:0x7a5e; valaddr_reg:x1; val_offset:2925*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2925*FLEN/8, x2, x5, x6)

inst_1011:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x12b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1e and fm3 == 0x25e and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x752b; op2val:0xc0ed;
op3val:0x7a5e; valaddr_reg:x1; val_offset:2928*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2928*FLEN/8, x2, x5, x6)

inst_1012:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x12b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1e and fm3 == 0x25e and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x752b; op2val:0xc0ed;
op3val:0x7a5e; valaddr_reg:x1; val_offset:2931*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2931*FLEN/8, x2, x5, x6)

inst_1013:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x12b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1e and fm3 == 0x25e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x752b; op2val:0xc0ed;
op3val:0x7a5e; valaddr_reg:x1; val_offset:2934*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2934*FLEN/8, x2, x5, x6)

inst_1014:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x12b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ed and fs3 == 0 and fe3 == 0x1e and fm3 == 0x25e and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x752b; op2val:0xc0ed;
op3val:0x7a5e; valaddr_reg:x1; val_offset:2937*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2937*FLEN/8, x2, x5, x6)

inst_1015:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x38a and fs2 == 1 and fe2 == 0x13 and fm2 == 0x226 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1cc and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x678a; op2val:0xce26;
op3val:0x79cc; valaddr_reg:x1; val_offset:2940*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2940*FLEN/8, x2, x5, x6)

inst_1016:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x38a and fs2 == 1 and fe2 == 0x13 and fm2 == 0x226 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1cc and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x678a; op2val:0xce26;
op3val:0x79cc; valaddr_reg:x1; val_offset:2943*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2943*FLEN/8, x2, x5, x6)

inst_1017:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x38a and fs2 == 1 and fe2 == 0x13 and fm2 == 0x226 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1cc and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x678a; op2val:0xce26;
op3val:0x79cc; valaddr_reg:x1; val_offset:2946*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2946*FLEN/8, x2, x5, x6)

inst_1018:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x38a and fs2 == 1 and fe2 == 0x13 and fm2 == 0x226 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1cc and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x678a; op2val:0xce26;
op3val:0x79cc; valaddr_reg:x1; val_offset:2949*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2949*FLEN/8, x2, x5, x6)

inst_1019:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x38a and fs2 == 1 and fe2 == 0x13 and fm2 == 0x226 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1cc and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x678a; op2val:0xce26;
op3val:0x79cc; valaddr_reg:x1; val_offset:2952*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2952*FLEN/8, x2, x5, x6)

inst_1020:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x2dd and fs2 == 1 and fe2 == 0x10 and fm2 == 0x19e and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d2 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6add; op2val:0xc19e;
op3val:0x70d2; valaddr_reg:x1; val_offset:2955*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2955*FLEN/8, x2, x5, x6)

inst_1021:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x2dd and fs2 == 1 and fe2 == 0x10 and fm2 == 0x19e and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d2 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6add; op2val:0xc19e;
op3val:0x70d2; valaddr_reg:x1; val_offset:2958*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2958*FLEN/8, x2, x5, x6)

inst_1022:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x2dd and fs2 == 1 and fe2 == 0x10 and fm2 == 0x19e and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d2 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6add; op2val:0xc19e;
op3val:0x70d2; valaddr_reg:x1; val_offset:2961*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2961*FLEN/8, x2, x5, x6)

inst_1023:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x2dd and fs2 == 1 and fe2 == 0x10 and fm2 == 0x19e and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d2 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6add; op2val:0xc19e;
op3val:0x70d2; valaddr_reg:x1; val_offset:2964*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2964*FLEN/8, x2, x5, x6)

inst_1024:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x2dd and fs2 == 1 and fe2 == 0x10 and fm2 == 0x19e and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d2 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6add; op2val:0xc19e;
op3val:0x70d2; valaddr_reg:x1; val_offset:2967*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2967*FLEN/8, x2, x5, x6)

inst_1025:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x39c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x172 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b9c; op2val:0xb9b9;
op3val:0x7972; valaddr_reg:x1; val_offset:2970*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2970*FLEN/8, x2, x5, x6)

inst_1026:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x39c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x172 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b9c; op2val:0xb9b9;
op3val:0x7972; valaddr_reg:x1; val_offset:2973*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2973*FLEN/8, x2, x5, x6)

inst_1027:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x39c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x172 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b9c; op2val:0xb9b9;
op3val:0x7972; valaddr_reg:x1; val_offset:2976*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2976*FLEN/8, x2, x5, x6)

inst_1028:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x39c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x172 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b9c; op2val:0xb9b9;
op3val:0x7972; valaddr_reg:x1; val_offset:2979*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2979*FLEN/8, x2, x5, x6)

inst_1029:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x39c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x172 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b9c; op2val:0xb9b9;
op3val:0x7972; valaddr_reg:x1; val_offset:2982*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2982*FLEN/8, x2, x5, x6)

inst_1030:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x322 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x029 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x36d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7322; op2val:0xb829;
op3val:0x6f6d; valaddr_reg:x1; val_offset:2985*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 2985*FLEN/8, x2, x5, x6)

inst_1031:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x322 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x029 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x36d and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7322; op2val:0xb829;
op3val:0x6f6d; valaddr_reg:x1; val_offset:2988*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 2988*FLEN/8, x2, x5, x6)

inst_1032:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x322 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x029 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x36d and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7322; op2val:0xb829;
op3val:0x6f6d; valaddr_reg:x1; val_offset:2991*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 2991*FLEN/8, x2, x5, x6)

inst_1033:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x322 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x029 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x36d and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7322; op2val:0xb829;
op3val:0x6f6d; valaddr_reg:x1; val_offset:2994*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 2994*FLEN/8, x2, x5, x6)

inst_1034:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x322 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x029 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x36d and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7322; op2val:0xb829;
op3val:0x6f6d; valaddr_reg:x1; val_offset:2997*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 2997*FLEN/8, x2, x5, x6)

inst_1035:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x178 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x151 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc7; op2val:0xb978;
op3val:0x7951; valaddr_reg:x1; val_offset:3000*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3000*FLEN/8, x2, x5, x6)

inst_1036:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x178 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x151 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc7; op2val:0xb978;
op3val:0x7951; valaddr_reg:x1; val_offset:3003*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3003*FLEN/8, x2, x5, x6)

inst_1037:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x178 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x151 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc7; op2val:0xb978;
op3val:0x7951; valaddr_reg:x1; val_offset:3006*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3006*FLEN/8, x2, x5, x6)

inst_1038:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x178 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x151 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc7; op2val:0xb978;
op3val:0x7951; valaddr_reg:x1; val_offset:3009*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3009*FLEN/8, x2, x5, x6)

inst_1039:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x178 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x151 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc7; op2val:0xb978;
op3val:0x7951; valaddr_reg:x1; val_offset:3012*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3012*FLEN/8, x2, x5, x6)

inst_1040:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x173 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x078 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8f; op2val:0xb173;
op3val:0x7078; valaddr_reg:x1; val_offset:3015*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3015*FLEN/8, x2, x5, x6)

inst_1041:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x173 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x078 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8f; op2val:0xb173;
op3val:0x7078; valaddr_reg:x1; val_offset:3018*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3018*FLEN/8, x2, x5, x6)

inst_1042:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x173 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x078 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8f; op2val:0xb173;
op3val:0x7078; valaddr_reg:x1; val_offset:3021*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3021*FLEN/8, x2, x5, x6)

inst_1043:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x173 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x078 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8f; op2val:0xb173;
op3val:0x7078; valaddr_reg:x1; val_offset:3024*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3024*FLEN/8, x2, x5, x6)

inst_1044:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x173 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x078 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8f; op2val:0xb173;
op3val:0x7078; valaddr_reg:x1; val_offset:3027*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3027*FLEN/8, x2, x5, x6)

inst_1045:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fe and fs2 == 1 and fe2 == 0x0e and fm2 == 0x089 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1aa and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fe; op2val:0xb889;
op3val:0x75aa; valaddr_reg:x1; val_offset:3030*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3030*FLEN/8, x2, x5, x6)

inst_1046:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fe and fs2 == 1 and fe2 == 0x0e and fm2 == 0x089 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1aa and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fe; op2val:0xb889;
op3val:0x75aa; valaddr_reg:x1; val_offset:3033*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3033*FLEN/8, x2, x5, x6)

inst_1047:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fe and fs2 == 1 and fe2 == 0x0e and fm2 == 0x089 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1aa and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fe; op2val:0xb889;
op3val:0x75aa; valaddr_reg:x1; val_offset:3036*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3036*FLEN/8, x2, x5, x6)

inst_1048:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fe and fs2 == 1 and fe2 == 0x0e and fm2 == 0x089 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1aa and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fe; op2val:0xb889;
op3val:0x75aa; valaddr_reg:x1; val_offset:3039*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3039*FLEN/8, x2, x5, x6)

inst_1049:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fe and fs2 == 1 and fe2 == 0x0e and fm2 == 0x089 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1aa and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fe; op2val:0xb889;
op3val:0x75aa; valaddr_reg:x1; val_offset:3042*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3042*FLEN/8, x2, x5, x6)

inst_1050:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x384 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1ac and fs3 == 0 and fe3 == 0x1d and fm3 == 0x154 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7384; op2val:0xbdac;
op3val:0x7554; valaddr_reg:x1; val_offset:3045*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3045*FLEN/8, x2, x5, x6)

inst_1051:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x384 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1ac and fs3 == 0 and fe3 == 0x1d and fm3 == 0x154 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7384; op2val:0xbdac;
op3val:0x7554; valaddr_reg:x1; val_offset:3048*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3048*FLEN/8, x2, x5, x6)
RVTEST_SIGBASE(x5,signature_x5_8)

inst_1052:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x384 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1ac and fs3 == 0 and fe3 == 0x1d and fm3 == 0x154 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7384; op2val:0xbdac;
op3val:0x7554; valaddr_reg:x1; val_offset:3051*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3051*FLEN/8, x2, x5, x6)

inst_1053:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x384 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1ac and fs3 == 0 and fe3 == 0x1d and fm3 == 0x154 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7384; op2val:0xbdac;
op3val:0x7554; valaddr_reg:x1; val_offset:3054*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3054*FLEN/8, x2, x5, x6)

inst_1054:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x384 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1ac and fs3 == 0 and fe3 == 0x1d and fm3 == 0x154 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7384; op2val:0xbdac;
op3val:0x7554; valaddr_reg:x1; val_offset:3057*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3057*FLEN/8, x2, x5, x6)

inst_1055:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x08b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x193 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e8; op2val:0xb88b;
op3val:0x7593; valaddr_reg:x1; val_offset:3060*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3060*FLEN/8, x2, x5, x6)

inst_1056:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x08b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x193 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e8; op2val:0xb88b;
op3val:0x7593; valaddr_reg:x1; val_offset:3063*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3063*FLEN/8, x2, x5, x6)

inst_1057:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x08b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x193 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e8; op2val:0xb88b;
op3val:0x7593; valaddr_reg:x1; val_offset:3066*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3066*FLEN/8, x2, x5, x6)

inst_1058:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x08b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x193 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e8; op2val:0xb88b;
op3val:0x7593; valaddr_reg:x1; val_offset:3069*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3069*FLEN/8, x2, x5, x6)

inst_1059:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x08b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x193 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e8; op2val:0xb88b;
op3val:0x7593; valaddr_reg:x1; val_offset:3072*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3072*FLEN/8, x2, x5, x6)

inst_1060:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x05d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x762b; op2val:0xb5a8;
op3val:0x705d; valaddr_reg:x1; val_offset:3075*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3075*FLEN/8, x2, x5, x6)

inst_1061:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x05d and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x762b; op2val:0xb5a8;
op3val:0x705d; valaddr_reg:x1; val_offset:3078*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3078*FLEN/8, x2, x5, x6)

inst_1062:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x05d and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x762b; op2val:0xb5a8;
op3val:0x705d; valaddr_reg:x1; val_offset:3081*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3081*FLEN/8, x2, x5, x6)

inst_1063:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x05d and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x762b; op2val:0xb5a8;
op3val:0x705d; valaddr_reg:x1; val_offset:3084*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3084*FLEN/8, x2, x5, x6)

inst_1064:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1a8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x05d and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x762b; op2val:0xb5a8;
op3val:0x705d; valaddr_reg:x1; val_offset:3087*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3087*FLEN/8, x2, x5, x6)

inst_1065:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x23c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x12e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aa5; op2val:0xba3c;
op3val:0x792e; valaddr_reg:x1; val_offset:3090*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3090*FLEN/8, x2, x5, x6)

inst_1066:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x23c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x12e and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aa5; op2val:0xba3c;
op3val:0x792e; valaddr_reg:x1; val_offset:3093*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3093*FLEN/8, x2, x5, x6)

inst_1067:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x23c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x12e and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aa5; op2val:0xba3c;
op3val:0x792e; valaddr_reg:x1; val_offset:3096*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3096*FLEN/8, x2, x5, x6)

inst_1068:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x23c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x12e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aa5; op2val:0xba3c;
op3val:0x792e; valaddr_reg:x1; val_offset:3099*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3099*FLEN/8, x2, x5, x6)

inst_1069:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x23c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x12e and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aa5; op2val:0xba3c;
op3val:0x792e; valaddr_reg:x1; val_offset:3102*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3102*FLEN/8, x2, x5, x6)

inst_1070:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x04f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ee and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6e; op2val:0xb84f;
op3val:0x76ee; valaddr_reg:x1; val_offset:3105*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3105*FLEN/8, x2, x5, x6)

inst_1071:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x04f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ee and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6e; op2val:0xb84f;
op3val:0x76ee; valaddr_reg:x1; val_offset:3108*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3108*FLEN/8, x2, x5, x6)

inst_1072:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x04f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ee and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6e; op2val:0xb84f;
op3val:0x76ee; valaddr_reg:x1; val_offset:3111*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3111*FLEN/8, x2, x5, x6)

inst_1073:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x04f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ee and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6e; op2val:0xb84f;
op3val:0x76ee; valaddr_reg:x1; val_offset:3114*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3114*FLEN/8, x2, x5, x6)

inst_1074:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x04f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ee and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a6e; op2val:0xb84f;
op3val:0x76ee; valaddr_reg:x1; val_offset:3117*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3117*FLEN/8, x2, x5, x6)

inst_1075:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2cf and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0dc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x023 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7acf; op2val:0xb8dc;
op3val:0x7823; valaddr_reg:x1; val_offset:3120*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3120*FLEN/8, x2, x5, x6)

inst_1076:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2cf and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0dc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x023 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7acf; op2val:0xb8dc;
op3val:0x7823; valaddr_reg:x1; val_offset:3123*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3123*FLEN/8, x2, x5, x6)

inst_1077:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2cf and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0dc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x023 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7acf; op2val:0xb8dc;
op3val:0x7823; valaddr_reg:x1; val_offset:3126*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3126*FLEN/8, x2, x5, x6)

inst_1078:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2cf and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0dc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x023 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7acf; op2val:0xb8dc;
op3val:0x7823; valaddr_reg:x1; val_offset:3129*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3129*FLEN/8, x2, x5, x6)

inst_1079:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2cf and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0dc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x023 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7acf; op2val:0xb8dc;
op3val:0x7823; valaddr_reg:x1; val_offset:3132*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3132*FLEN/8, x2, x5, x6)

inst_1080:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3bd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x095 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78bd; op2val:0xbbbd;
op3val:0x7895; valaddr_reg:x1; val_offset:3135*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3135*FLEN/8, x2, x5, x6)

inst_1081:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3bd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x095 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78bd; op2val:0xbbbd;
op3val:0x7895; valaddr_reg:x1; val_offset:3138*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3138*FLEN/8, x2, x5, x6)

inst_1082:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3bd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x095 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78bd; op2val:0xbbbd;
op3val:0x7895; valaddr_reg:x1; val_offset:3141*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3141*FLEN/8, x2, x5, x6)

inst_1083:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3bd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x095 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78bd; op2val:0xbbbd;
op3val:0x7895; valaddr_reg:x1; val_offset:3144*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3144*FLEN/8, x2, x5, x6)

inst_1084:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3bd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x095 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78bd; op2val:0xbbbd;
op3val:0x7895; valaddr_reg:x1; val_offset:3147*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3147*FLEN/8, x2, x5, x6)

inst_1085:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1eb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x046 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x253 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79eb; op2val:0xb846;
op3val:0x7653; valaddr_reg:x1; val_offset:3150*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3150*FLEN/8, x2, x5, x6)

inst_1086:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1eb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x046 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x253 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79eb; op2val:0xb846;
op3val:0x7653; valaddr_reg:x1; val_offset:3153*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3153*FLEN/8, x2, x5, x6)

inst_1087:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1eb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x046 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x253 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79eb; op2val:0xb846;
op3val:0x7653; valaddr_reg:x1; val_offset:3156*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3156*FLEN/8, x2, x5, x6)

inst_1088:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1eb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x046 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x253 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79eb; op2val:0xb846;
op3val:0x7653; valaddr_reg:x1; val_offset:3159*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3159*FLEN/8, x2, x5, x6)

inst_1089:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1eb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x046 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x253 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79eb; op2val:0xb846;
op3val:0x7653; valaddr_reg:x1; val_offset:3162*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3162*FLEN/8, x2, x5, x6)

inst_1090:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x234 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x178 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x03e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e34; op2val:0xb578;
op3val:0x683e; valaddr_reg:x1; val_offset:3165*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3165*FLEN/8, x2, x5, x6)

inst_1091:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x234 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x178 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x03e and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e34; op2val:0xb578;
op3val:0x683e; valaddr_reg:x1; val_offset:3168*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3168*FLEN/8, x2, x5, x6)

inst_1092:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x234 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x178 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x03e and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e34; op2val:0xb578;
op3val:0x683e; valaddr_reg:x1; val_offset:3171*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3171*FLEN/8, x2, x5, x6)

inst_1093:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x234 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x178 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x03e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e34; op2val:0xb578;
op3val:0x683e; valaddr_reg:x1; val_offset:3174*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3174*FLEN/8, x2, x5, x6)

inst_1094:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x234 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x178 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x03e and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e34; op2val:0xb578;
op3val:0x683e; valaddr_reg:x1; val_offset:3177*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3177*FLEN/8, x2, x5, x6)

inst_1095:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x279 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x23d and fs3 == 0 and fe3 == 0x1a and fm3 == 0x10c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7279; op2val:0xb23d;
op3val:0x690c; valaddr_reg:x1; val_offset:3180*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3180*FLEN/8, x2, x5, x6)

inst_1096:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x279 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x23d and fs3 == 0 and fe3 == 0x1a and fm3 == 0x10c and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7279; op2val:0xb23d;
op3val:0x690c; valaddr_reg:x1; val_offset:3183*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3183*FLEN/8, x2, x5, x6)

inst_1097:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x279 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x23d and fs3 == 0 and fe3 == 0x1a and fm3 == 0x10c and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7279; op2val:0xb23d;
op3val:0x690c; valaddr_reg:x1; val_offset:3186*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3186*FLEN/8, x2, x5, x6)

inst_1098:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x279 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x23d and fs3 == 0 and fe3 == 0x1a and fm3 == 0x10c and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7279; op2val:0xb23d;
op3val:0x690c; valaddr_reg:x1; val_offset:3189*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3189*FLEN/8, x2, x5, x6)

inst_1099:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x279 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x23d and fs3 == 0 and fe3 == 0x1a and fm3 == 0x10c and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7279; op2val:0xb23d;
op3val:0x690c; valaddr_reg:x1; val_offset:3192*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3192*FLEN/8, x2, x5, x6)

inst_1100:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x31c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x053 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b1 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b1c; op2val:0xb853;
op3val:0x77b1; valaddr_reg:x1; val_offset:3195*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3195*FLEN/8, x2, x5, x6)

inst_1101:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x31c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x053 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b1 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b1c; op2val:0xb853;
op3val:0x77b1; valaddr_reg:x1; val_offset:3198*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3198*FLEN/8, x2, x5, x6)

inst_1102:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x31c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x053 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b1 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b1c; op2val:0xb853;
op3val:0x77b1; valaddr_reg:x1; val_offset:3201*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3201*FLEN/8, x2, x5, x6)

inst_1103:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x31c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x053 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b1 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b1c; op2val:0xb853;
op3val:0x77b1; valaddr_reg:x1; val_offset:3204*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3204*FLEN/8, x2, x5, x6)

inst_1104:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x31c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x053 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b1 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b1c; op2val:0xb853;
op3val:0x77b1; valaddr_reg:x1; val_offset:3207*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3207*FLEN/8, x2, x5, x6)

inst_1105:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x214 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x0e5 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x373 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a14; op2val:0x90e5;
op3val:0x4f73; valaddr_reg:x1; val_offset:3210*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3210*FLEN/8, x2, x5, x6)

inst_1106:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x214 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x0e5 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x373 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a14; op2val:0x90e5;
op3val:0x4f73; valaddr_reg:x1; val_offset:3213*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3213*FLEN/8, x2, x5, x6)

inst_1107:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x214 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x0e5 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x373 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a14; op2val:0x90e5;
op3val:0x4f73; valaddr_reg:x1; val_offset:3216*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3216*FLEN/8, x2, x5, x6)

inst_1108:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x214 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x0e5 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x373 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a14; op2val:0x90e5;
op3val:0x4f73; valaddr_reg:x1; val_offset:3219*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3219*FLEN/8, x2, x5, x6)

inst_1109:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x214 and fs2 == 1 and fe2 == 0x04 and fm2 == 0x0e5 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x373 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a14; op2val:0x90e5;
op3val:0x4f73; valaddr_reg:x1; val_offset:3222*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3222*FLEN/8, x2, x5, x6)

inst_1110:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x384 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x391 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x31d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7784; op2val:0xbf91;
op3val:0x7b1d; valaddr_reg:x1; val_offset:3225*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3225*FLEN/8, x2, x5, x6)

inst_1111:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x384 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x391 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x31d and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7784; op2val:0xbf91;
op3val:0x7b1d; valaddr_reg:x1; val_offset:3228*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3228*FLEN/8, x2, x5, x6)

inst_1112:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x384 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x391 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x31d and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7784; op2val:0xbf91;
op3val:0x7b1d; valaddr_reg:x1; val_offset:3231*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3231*FLEN/8, x2, x5, x6)

inst_1113:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x384 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x391 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x31d and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7784; op2val:0xbf91;
op3val:0x7b1d; valaddr_reg:x1; val_offset:3234*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3234*FLEN/8, x2, x5, x6)

inst_1114:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x384 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x391 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x31d and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7784; op2val:0xbf91;
op3val:0x7b1d; valaddr_reg:x1; val_offset:3237*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3237*FLEN/8, x2, x5, x6)

inst_1115:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x189 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2da and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78f4; op2val:0xb989;
op3val:0x76da; valaddr_reg:x1; val_offset:3240*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3240*FLEN/8, x2, x5, x6)

inst_1116:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x189 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2da and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78f4; op2val:0xb989;
op3val:0x76da; valaddr_reg:x1; val_offset:3243*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3243*FLEN/8, x2, x5, x6)

inst_1117:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x189 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2da and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78f4; op2val:0xb989;
op3val:0x76da; valaddr_reg:x1; val_offset:3246*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3246*FLEN/8, x2, x5, x6)

inst_1118:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x189 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2da and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78f4; op2val:0xb989;
op3val:0x76da; valaddr_reg:x1; val_offset:3249*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3249*FLEN/8, x2, x5, x6)

inst_1119:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x189 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2da and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78f4; op2val:0xb989;
op3val:0x76da; valaddr_reg:x1; val_offset:3252*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3252*FLEN/8, x2, x5, x6)

inst_1120:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ee and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fb; op2val:0xbcc3;
op3val:0x79ee; valaddr_reg:x1; val_offset:3255*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3255*FLEN/8, x2, x5, x6)

inst_1121:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ee and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fb; op2val:0xbcc3;
op3val:0x79ee; valaddr_reg:x1; val_offset:3258*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3258*FLEN/8, x2, x5, x6)

inst_1122:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ee and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fb; op2val:0xbcc3;
op3val:0x79ee; valaddr_reg:x1; val_offset:3261*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3261*FLEN/8, x2, x5, x6)

inst_1123:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0bd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x389 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5b; op2val:0xbcbd;
op3val:0x7b89; valaddr_reg:x1; val_offset:3264*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 64, 0, x1, 3264*FLEN/8, x2, x5, x6)

inst_1124:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0bd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x389 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5b; op2val:0xbcbd;
op3val:0x7b89; valaddr_reg:x1; val_offset:3267*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3267*FLEN/8, x2, x5, x6)

inst_1125:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0bd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x389 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5b; op2val:0xbcbd;
op3val:0x7b89; valaddr_reg:x1; val_offset:3270*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3270*FLEN/8, x2, x5, x6)

inst_1126:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0fc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x360 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79ea; op2val:0xbcfc;
op3val:0x7b60; valaddr_reg:x1; val_offset:3273*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3273*FLEN/8, x2, x5, x6)

inst_1127:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0fc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x360 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79ea; op2val:0xbcfc;
op3val:0x7b60; valaddr_reg:x1; val_offset:3276*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 32, 0, x1, 3276*FLEN/8, x2, x5, x6)

inst_1128:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0fc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x360 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79ea; op2val:0xbcfc;
op3val:0x7b60; valaddr_reg:x1; val_offset:3279*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 96, 0, x1, 3279*FLEN/8, x2, x5, x6)

inst_1129:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x38b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x180 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x130 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b8b; op2val:0xb980;
op3val:0x7930; valaddr_reg:x1; val_offset:3282*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3282*FLEN/8, x2, x5, x6)

inst_1130:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x334 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x005 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x33e and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b34; op2val:0xb005;
op3val:0x6f3e; valaddr_reg:x1; val_offset:3285*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 128, 0, x1, 3285*FLEN/8, x2, x5, x6)

inst_1131:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x380 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x034 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3e3 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7780; op2val:0xb834;
op3val:0x73e3; valaddr_reg:x1; val_offset:3288*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, x31, x30, x29, x28, dyn, 0, 0, x1, 3288*FLEN/8, x2, x5, x6)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(30971,32,FLEN)
NAN_BOXED(30971,16,FLEN)
NAN_BOXED(31214,32,FLEN)
NAN_BOXED(30971,32,FLEN)
NAN_BOXED(48323,16,FLEN)
NAN_BOXED(30971,32,FLEN)
NAN_BOXED(30971,32,FLEN)
NAN_BOXED(48323,16,FLEN)
NAN_BOXED(31214,32,FLEN)
NAN_BOXED(30971,32,FLEN)
NAN_BOXED(30971,16,FLEN)
NAN_BOXED(30971,32,FLEN)
NAN_BOXED(30971,32,FLEN)
NAN_BOXED(48323,16,FLEN)
NAN_BOXED(31214,32,FLEN)
NAN_BOXED(31323,32,FLEN)
NAN_BOXED(48317,16,FLEN)
NAN_BOXED(31625,32,FLEN)
NAN_BOXED(31323,32,FLEN)
NAN_BOXED(48317,16,FLEN)
NAN_BOXED(31625,32,FLEN)
NAN_BOXED(31323,32,FLEN)
NAN_BOXED(48317,16,FLEN)
NAN_BOXED(48317,32,FLEN)
NAN_BOXED(31323,32,FLEN)
NAN_BOXED(48317,16,FLEN)
NAN_BOXED(31323,32,FLEN)
NAN_BOXED(31323,32,FLEN)
NAN_BOXED(31323,16,FLEN)
NAN_BOXED(31323,32,FLEN)
NAN_BOXED(31210,32,FLEN)
NAN_BOXED(48380,16,FLEN)
NAN_BOXED(48380,32,FLEN)
test_dataset_1:
NAN_BOXED(31210,32,FLEN)
NAN_BOXED(31210,16,FLEN)
NAN_BOXED(31584,32,FLEN)
NAN_BOXED(31210,32,FLEN)
NAN_BOXED(48380,16,FLEN)
NAN_BOXED(31584,32,FLEN)
NAN_BOXED(31210,32,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31584,32,FLEN)
NAN_BOXED(31210,32,FLEN)
NAN_BOXED(48380,16,FLEN)
NAN_BOXED(31584,32,FLEN)
NAN_BOXED(26476,32,FLEN)
NAN_BOXED(52226,16,FLEN)
NAN_BOXED(30578,32,FLEN)
NAN_BOXED(26476,32,FLEN)
NAN_BOXED(52226,16,FLEN)
NAN_BOXED(30578,32,FLEN)
NAN_BOXED(26476,32,FLEN)
NAN_BOXED(52226,16,FLEN)
NAN_BOXED(30578,32,FLEN)
NAN_BOXED(26476,32,FLEN)
NAN_BOXED(52226,16,FLEN)
NAN_BOXED(30578,32,FLEN)
NAN_BOXED(26476,32,FLEN)
NAN_BOXED(52226,16,FLEN)
NAN_BOXED(30578,32,FLEN)
NAN_BOXED(31627,32,FLEN)
NAN_BOXED(47488,16,FLEN)
NAN_BOXED(31024,32,FLEN)
NAN_BOXED(31627,32,FLEN)
NAN_BOXED(47488,16,FLEN)
NAN_BOXED(31024,32,FLEN)
NAN_BOXED(31627,32,FLEN)
NAN_BOXED(47488,16,FLEN)
NAN_BOXED(31024,32,FLEN)
NAN_BOXED(31627,32,FLEN)
NAN_BOXED(47488,16,FLEN)
NAN_BOXED(31024,32,FLEN)
test_dataset_2:
NAN_BOXED(31627,32,FLEN)
NAN_BOXED(47488,16,FLEN)
NAN_BOXED(31024,32,FLEN)
NAN_BOXED(31540,32,FLEN)
NAN_BOXED(45061,16,FLEN)
NAN_BOXED(28478,32,FLEN)
NAN_BOXED(31540,32,FLEN)
NAN_BOXED(45061,16,FLEN)
NAN_BOXED(28478,32,FLEN)
NAN_BOXED(31540,32,FLEN)
NAN_BOXED(45061,16,FLEN)
NAN_BOXED(28478,32,FLEN)
NAN_BOXED(31540,32,FLEN)
NAN_BOXED(45061,16,FLEN)
NAN_BOXED(28478,32,FLEN)
NAN_BOXED(31540,32,FLEN)
NAN_BOXED(45061,16,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(47156,16,FLEN)
NAN_BOXED(29667,32,FLEN)
NAN_BOXED(30592,32,FLEN)
NAN_BOXED(47156,16,FLEN)
NAN_BOXED(29667,32,FLEN)
NAN_BOXED(30592,32,FLEN)
NAN_BOXED(47156,16,FLEN)
NAN_BOXED(29667,32,FLEN)
NAN_BOXED(30592,32,FLEN)
NAN_BOXED(47156,16,FLEN)
NAN_BOXED(29667,32,FLEN)
NAN_BOXED(30592,32,FLEN)
NAN_BOXED(47156,16,FLEN)
NAN_BOXED(29667,32,FLEN)
test_dataset_3:
NAN_BOXED(30809,16,FLEN)
NAN_BOXED(48184,16,FLEN)
NAN_BOXED(30870,16,FLEN)
NAN_BOXED(30809,16,FLEN)
NAN_BOXED(48184,16,FLEN)
NAN_BOXED(30870,16,FLEN)
NAN_BOXED(30809,16,FLEN)
NAN_BOXED(48184,16,FLEN)
NAN_BOXED(30870,16,FLEN)
NAN_BOXED(30809,16,FLEN)
NAN_BOXED(48184,16,FLEN)
NAN_BOXED(30870,16,FLEN)
NAN_BOXED(30809,16,FLEN)
NAN_BOXED(48184,16,FLEN)
NAN_BOXED(30870,16,FLEN)
NAN_BOXED(25272,16,FLEN)
NAN_BOXED(52256,16,FLEN)
NAN_BOXED(29422,16,FLEN)
NAN_BOXED(25272,16,FLEN)
NAN_BOXED(52256,16,FLEN)
NAN_BOXED(29422,16,FLEN)
NAN_BOXED(25272,16,FLEN)
NAN_BOXED(52256,16,FLEN)
NAN_BOXED(29422,16,FLEN)
NAN_BOXED(25272,16,FLEN)
NAN_BOXED(52256,16,FLEN)
NAN_BOXED(29422,16,FLEN)
NAN_BOXED(25272,16,FLEN)
NAN_BOXED(52256,16,FLEN)
NAN_BOXED(29422,16,FLEN)
NAN_BOXED(29816,16,FLEN)
NAN_BOXED(49806,16,FLEN)
NAN_BOXED(31571,16,FLEN)
NAN_BOXED(29816,16,FLEN)
NAN_BOXED(49806,16,FLEN)
NAN_BOXED(31571,16,FLEN)
NAN_BOXED(29816,16,FLEN)
NAN_BOXED(49806,16,FLEN)
NAN_BOXED(31571,16,FLEN)
NAN_BOXED(29816,16,FLEN)
NAN_BOXED(49806,16,FLEN)
NAN_BOXED(31571,16,FLEN)
NAN_BOXED(29816,16,FLEN)
NAN_BOXED(49806,16,FLEN)
NAN_BOXED(31571,16,FLEN)
NAN_BOXED(31263,16,FLEN)
NAN_BOXED(45739,16,FLEN)
NAN_BOXED(28954,16,FLEN)
NAN_BOXED(31263,16,FLEN)
NAN_BOXED(45739,16,FLEN)
NAN_BOXED(28954,16,FLEN)
NAN_BOXED(31263,16,FLEN)
NAN_BOXED(45739,16,FLEN)
NAN_BOXED(28954,16,FLEN)
NAN_BOXED(31263,16,FLEN)
NAN_BOXED(45739,16,FLEN)
NAN_BOXED(28954,16,FLEN)
NAN_BOXED(31263,16,FLEN)
NAN_BOXED(45739,16,FLEN)
NAN_BOXED(28954,16,FLEN)
NAN_BOXED(31327,16,FLEN)
NAN_BOXED(45458,16,FLEN)
NAN_BOXED(28784,16,FLEN)
NAN_BOXED(31327,16,FLEN)
NAN_BOXED(45458,16,FLEN)
NAN_BOXED(28784,16,FLEN)
NAN_BOXED(31327,16,FLEN)
NAN_BOXED(45458,16,FLEN)
NAN_BOXED(28784,16,FLEN)
NAN_BOXED(31327,16,FLEN)
NAN_BOXED(45458,16,FLEN)
NAN_BOXED(28784,16,FLEN)
NAN_BOXED(31327,16,FLEN)
NAN_BOXED(45458,16,FLEN)
NAN_BOXED(28784,16,FLEN)
NAN_BOXED(30959,16,FLEN)
NAN_BOXED(45713,16,FLEN)
NAN_BOXED(28685,16,FLEN)
NAN_BOXED(30959,16,FLEN)
NAN_BOXED(45713,16,FLEN)
NAN_BOXED(28685,16,FLEN)
NAN_BOXED(30959,16,FLEN)
NAN_BOXED(45713,16,FLEN)
NAN_BOXED(28685,16,FLEN)
NAN_BOXED(30959,16,FLEN)
NAN_BOXED(45713,16,FLEN)
NAN_BOXED(28685,16,FLEN)
NAN_BOXED(30959,16,FLEN)
NAN_BOXED(45713,16,FLEN)
NAN_BOXED(28685,16,FLEN)
NAN_BOXED(22356,16,FLEN)
NAN_BOXED(57243,16,FLEN)
NAN_BOXED(31479,16,FLEN)
NAN_BOXED(22356,16,FLEN)
NAN_BOXED(57243,16,FLEN)
NAN_BOXED(31479,16,FLEN)
NAN_BOXED(22356,16,FLEN)
NAN_BOXED(57243,16,FLEN)
NAN_BOXED(31479,16,FLEN)
NAN_BOXED(22356,16,FLEN)
NAN_BOXED(57243,16,FLEN)
NAN_BOXED(31479,16,FLEN)
NAN_BOXED(22356,16,FLEN)
NAN_BOXED(57243,16,FLEN)
NAN_BOXED(31479,16,FLEN)
NAN_BOXED(29363,16,FLEN)
NAN_BOXED(48157,16,FLEN)
NAN_BOXED(29412,16,FLEN)
NAN_BOXED(29363,16,FLEN)
NAN_BOXED(48157,16,FLEN)
NAN_BOXED(29412,16,FLEN)
NAN_BOXED(29363,16,FLEN)
NAN_BOXED(48157,16,FLEN)
NAN_BOXED(29412,16,FLEN)
NAN_BOXED(29363,16,FLEN)
NAN_BOXED(48157,16,FLEN)
NAN_BOXED(29412,16,FLEN)
NAN_BOXED(29363,16,FLEN)
NAN_BOXED(48157,16,FLEN)
NAN_BOXED(29412,16,FLEN)
NAN_BOXED(31707,16,FLEN)
NAN_BOXED(47898,16,FLEN)
NAN_BOXED(31481,16,FLEN)
NAN_BOXED(31707,16,FLEN)
NAN_BOXED(47898,16,FLEN)
NAN_BOXED(31481,16,FLEN)
NAN_BOXED(31707,16,FLEN)
NAN_BOXED(47898,16,FLEN)
NAN_BOXED(31481,16,FLEN)
NAN_BOXED(31707,16,FLEN)
NAN_BOXED(47898,16,FLEN)
NAN_BOXED(31481,16,FLEN)
NAN_BOXED(31707,16,FLEN)
NAN_BOXED(47898,16,FLEN)
NAN_BOXED(31481,16,FLEN)
NAN_BOXED(29856,16,FLEN)
NAN_BOXED(49829,16,FLEN)
NAN_BOXED(31664,16,FLEN)
NAN_BOXED(29856,16,FLEN)
NAN_BOXED(49829,16,FLEN)
NAN_BOXED(31664,16,FLEN)
NAN_BOXED(29856,16,FLEN)
NAN_BOXED(49829,16,FLEN)
NAN_BOXED(31664,16,FLEN)
NAN_BOXED(29856,16,FLEN)
NAN_BOXED(49829,16,FLEN)
NAN_BOXED(31664,16,FLEN)
NAN_BOXED(29856,16,FLEN)
NAN_BOXED(49829,16,FLEN)
NAN_BOXED(31664,16,FLEN)
NAN_BOXED(30799,16,FLEN)
NAN_BOXED(48391,16,FLEN)
NAN_BOXED(31083,16,FLEN)
NAN_BOXED(30799,16,FLEN)
NAN_BOXED(48391,16,FLEN)
NAN_BOXED(31083,16,FLEN)
NAN_BOXED(30799,16,FLEN)
NAN_BOXED(48391,16,FLEN)
NAN_BOXED(31083,16,FLEN)
NAN_BOXED(30799,16,FLEN)
NAN_BOXED(48391,16,FLEN)
NAN_BOXED(31083,16,FLEN)
NAN_BOXED(30799,16,FLEN)
NAN_BOXED(48391,16,FLEN)
NAN_BOXED(31083,16,FLEN)
NAN_BOXED(29324,16,FLEN)
NAN_BOXED(50328,16,FLEN)
NAN_BOXED(31622,16,FLEN)
NAN_BOXED(29324,16,FLEN)
NAN_BOXED(50328,16,FLEN)
NAN_BOXED(31622,16,FLEN)
NAN_BOXED(29324,16,FLEN)
NAN_BOXED(50328,16,FLEN)
NAN_BOXED(31622,16,FLEN)
NAN_BOXED(29324,16,FLEN)
NAN_BOXED(50328,16,FLEN)
NAN_BOXED(31622,16,FLEN)
NAN_BOXED(29324,16,FLEN)
NAN_BOXED(50328,16,FLEN)
NAN_BOXED(31622,16,FLEN)
NAN_BOXED(31109,16,FLEN)
NAN_BOXED(48537,16,FLEN)
NAN_BOXED(31674,16,FLEN)
NAN_BOXED(31109,16,FLEN)
NAN_BOXED(48537,16,FLEN)
NAN_BOXED(31674,16,FLEN)
NAN_BOXED(31109,16,FLEN)
NAN_BOXED(48537,16,FLEN)
NAN_BOXED(31674,16,FLEN)
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NAN_BOXED(47497,16,FLEN)
NAN_BOXED(30426,16,FLEN)
NAN_BOXED(30964,16,FLEN)
NAN_BOXED(47497,16,FLEN)
NAN_BOXED(30426,16,FLEN)
NAN_BOXED(30964,16,FLEN)
NAN_BOXED(47497,16,FLEN)
NAN_BOXED(30426,16,FLEN)
NAN_BOXED(30964,16,FLEN)
NAN_BOXED(47497,16,FLEN)
NAN_BOXED(30426,16,FLEN)
NAN_BOXED(30964,16,FLEN)
NAN_BOXED(47497,16,FLEN)
NAN_BOXED(30426,16,FLEN)
NAN_BOXED(30971,16,FLEN)
NAN_BOXED(48323,16,FLEN)
NAN_BOXED(31214,16,FLEN)
NAN_BOXED(30971,16,FLEN)
NAN_BOXED(48323,16,FLEN)
NAN_BOXED(31214,16,FLEN)
NAN_BOXED(30971,16,FLEN)
NAN_BOXED(48323,16,FLEN)
NAN_BOXED(31214,16,FLEN)
NAN_BOXED(31323,16,FLEN)
NAN_BOXED(48317,16,FLEN)
NAN_BOXED(31625,16,FLEN)
NAN_BOXED(31323,16,FLEN)
NAN_BOXED(48317,16,FLEN)
NAN_BOXED(31625,16,FLEN)
NAN_BOXED(31323,16,FLEN)
NAN_BOXED(48317,16,FLEN)
NAN_BOXED(31625,16,FLEN)
NAN_BOXED(31210,16,FLEN)
NAN_BOXED(48380,16,FLEN)
NAN_BOXED(31584,16,FLEN)
NAN_BOXED(31210,16,FLEN)
NAN_BOXED(48380,16,FLEN)
NAN_BOXED(31584,16,FLEN)
NAN_BOXED(31210,16,FLEN)
NAN_BOXED(48380,16,FLEN)
NAN_BOXED(31584,16,FLEN)
NAN_BOXED(31627,16,FLEN)
NAN_BOXED(47488,16,FLEN)
NAN_BOXED(31024,16,FLEN)
NAN_BOXED(31540,16,FLEN)
NAN_BOXED(45061,16,FLEN)
NAN_BOXED(28478,16,FLEN)
NAN_BOXED(30592,16,FLEN)
NAN_BOXED(47156,16,FLEN)
NAN_BOXED(29667,16,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;



signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 26*((SIGALIGN)/4),4,0xdeadbeef


signature_x3_0:
    .fill 30*((SIGALIGN)/4),4,0xdeadbeef


signature_x5_0:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x5_1:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x5_2:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x5_3:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x5_4:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x5_5:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x5_6:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x5_7:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x5_8:
    .fill 160*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;

mtrap_sigptr:
    .fill 64*XLEN/32,4,0xdeadbeef

tsig_end_canary:
CANARY;
#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif


sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
