
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.7.1
// timestamp : Fri Jun 17 14:03:51 2022 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /scratch/pawan/work/normalised/RV32D/fcvt.wu.d.cgf \
 \
//                  -- xlen 32  \
//                  --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.wu.d instruction of the RISC-V RV32FD_Zicsr,RV64FD_Zicsr extension for the fcvt.wu.d_b28 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*);def TEST_CASE_1=True;",fcvt.wu.d_b28)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x2,test_dataset_0)
RVTEST_SIGBASE(x8,signature_x8_1)

inst_0:// rs1==f26, rd==x21,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f26; dest:x21; op1val:0x0; valaddr_reg:x2;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x21, f26, dyn, 0, 0, x2, 0*FLEN/8, x12, x8, x6,FLREG)

inst_1:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x3fe and fm1 == 0x248ee18215dfa and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f17; dest:x17; op1val:0x3fe248ee18215dfa; valaddr_reg:x2;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x17, f17, dyn, 0, 0, x2, 1*FLEN/8, x12, x8, x6,FLREG)

inst_2:// rs1==f7, rd==x15,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f7; dest:x15; op1val:0x3ff0000000000000; valaddr_reg:x2;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x15, f7, dyn, 0, 0, x2, 2*FLEN/8, x12, x8, x6,FLREG)

inst_3:// rs1==f21, rd==x7,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x4000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f21; dest:x7; op1val:0x3ff4000000000000; valaddr_reg:x2;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x7, f21, dyn, 0, 0, x2, 3*FLEN/8, x12, x8, x6,FLREG)

inst_4:// rs1==f15, rd==x22,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x8000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f15; dest:x22; op1val:0x3ff8000000000000; valaddr_reg:x2;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x22, f15, dyn, 0, 0, x2, 4*FLEN/8, x12, x8, x6,FLREG)

inst_5:// rs1==f3, rd==x27,fs1 == 0 and fe1 == 0x3ff and fm1 == 0xc000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f3; dest:x27; op1val:0x3ffc000000000000; valaddr_reg:x2;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x27, f3, dyn, 0, 0, x2, 5*FLEN/8, x12, x8, x6,FLREG)

inst_6:// rs1==f1, rd==x14,fs1 == 0 and fe1 == 0x400 and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f1; dest:x14; op1val:0x4000000000000000; valaddr_reg:x2;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x14, f1, dyn, 0, 0, x2, 6*FLEN/8, x12, x8, x6,FLREG)

inst_7:// rs1==f18, rd==x16,fs1 == 0 and fe1 == 0x400 and fm1 == 0x2000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f18; dest:x16; op1val:0x4002000000000000; valaddr_reg:x2;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x16, f18, dyn, 0, 0, x2, 7*FLEN/8, x12, x8, x6,FLREG)

inst_8:// rs1==f30, rd==x28,fs1 == 0 and fe1 == 0x400 and fm1 == 0x4000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f30; dest:x28; op1val:0x4004000000000000; valaddr_reg:x2;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x28, f30, dyn, 0, 0, x2, 8*FLEN/8, x12, x8, x6,FLREG)

inst_9:// rs1==f9, rd==x26,fs1 == 0 and fe1 == 0x400 and fm1 == 0x6000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f9; dest:x26; op1val:0x4006000000000000; valaddr_reg:x2;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x26, f9, dyn, 0, 0, x2, 9*FLEN/8, x12, x8, x6,FLREG)

inst_10:// rs1==f11, rd==x9,fs1 == 0 and fe1 == 0x43c and fm1 == 0xb72eb13dc494a and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f11; dest:x9; op1val:0x43cb72eb13dc494a; valaddr_reg:x2;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x9, f11, dyn, 0, 0, x2, 10*FLEN/8, x12, x8, x6,FLREG)

inst_11:// rs1==f4, rd==x5,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f4; dest:x5; op1val:0x43e0000000000000; valaddr_reg:x2;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x5, f4, dyn, 0, 0, x2, 11*FLEN/8, x12, x8, x6,FLREG)

inst_12:// rs1==f16, rd==x4,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f16; dest:x4; op1val:0x7ff0000000000000; valaddr_reg:x2;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x4, f16, dyn, 0, 0, x2, 12*FLEN/8, x12, x8, x6,FLREG)

inst_13:// rs1==f8, rd==x13,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f8; dest:x13; op1val:0x7ff0000000000001; valaddr_reg:x2;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x13, f8, dyn, 0, 0, x2, 13*FLEN/8, x12, x8, x6,FLREG)

inst_14:// rs1==f2, rd==x11,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f2; dest:x11; op1val:0x7ff8000000000001; valaddr_reg:x2;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x11, f2, dyn, 0, 0, x2, 14*FLEN/8, x12, x8, x6,FLREG)

inst_15:// rs1==f23, rd==x3,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f23; dest:x3; op1val:0x8000000000000000; valaddr_reg:x2;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x3, f23, dyn, 0, 0, x2, 15*FLEN/8, x12, x8, x6,FLREG)

inst_16:// rs1==f14, rd==x29,fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f14; dest:x29; op1val:0xbf80000000000000; valaddr_reg:x2;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x29, f14, dyn, 0, 0, x2, 16*FLEN/8, x12, x8, x6,FLREG)

inst_17:// rs1==f13, rd==x31,fs1 == 1 and fe1 == 0x3fd and fm1 == 0xb008d57e19f88 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f13; dest:x31; op1val:0xbfdb008d57e19f88; valaddr_reg:x2;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x31, f13, dyn, 0, 0, x2, 17*FLEN/8, x12, x8, x6,FLREG)

inst_18:// rs1==f25, rd==x25,fs1 == 1 and fe1 == 0x3ff and fm1 == 0x4000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f25; dest:x25; op1val:0xbff4000000000000; valaddr_reg:x2;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x25, f25, dyn, 0, 0, x2, 18*FLEN/8, x12, x8, x6,FLREG)

inst_19:// rs1==f31, rd==x30,fs1 == 1 and fe1 == 0x3ff and fm1 == 0x8000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f31; dest:x30; op1val:0xbff8000000000000; valaddr_reg:x2;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x30, f31, dyn, 0, 0, x2, 19*FLEN/8, x12, x8, x6,FLREG)

inst_20:// rs1==f29, rd==x0,fs1 == 1 and fe1 == 0x3ff and fm1 == 0xc000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f29; dest:x0; op1val:0xbffc000000000000; valaddr_reg:x2;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x0, f29, dyn, 0, 0, x2, 20*FLEN/8, x12, x8, x6,FLREG)

inst_21:// rs1==f12, rd==x10,fs1 == 1 and fe1 == 0x400 and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f12; dest:x10; op1val:0xc000000000000000; valaddr_reg:x2;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x10, f12, dyn, 0, 0, x2, 21*FLEN/8, x12, x8, x6,FLREG)

inst_22:// rs1==f10, rd==x20,fs1 == 1 and fe1 == 0x400 and fm1 == 0x2000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f10; dest:x20; op1val:0xc002000000000000; valaddr_reg:x2;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x20, f10, dyn, 0, 0, x2, 22*FLEN/8, x12, x8, x6,FLREG)

inst_23:// rs1==f0, rd==x18,fs1 == 1 and fe1 == 0x400 and fm1 == 0x4000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f0; dest:x18; op1val:0xc004000000000000; valaddr_reg:x2;
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x18, f0, dyn, 0, 0, x2, 23*FLEN/8, x12, x8, x6,FLREG)

inst_24:// rs1==f24, rd==x1,fs1 == 1 and fe1 == 0x400 and fm1 == 0x6000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f24; dest:x1; op1val:0xc006000000000000; valaddr_reg:x2;
val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x1, f24, dyn, 0, 0, x2, 24*FLEN/8, x12, x8, x6,FLREG)
RVTEST_VALBASEUPD(x3,test_dataset_1)

inst_25:// rs1==f19, rd==x2,fs1 == 1 and fe1 == 0x43d and fm1 == 0x967a4ae26514c and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f19; dest:x2; op1val:0xc3d967a4ae26514c; valaddr_reg:x3;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x2, f19, dyn, 0, 0, x3, 0*FLEN/8, x4, x8, x6,FLREG)

inst_26:// rs1==f27, rd==x19,fs1 == 1 and fe1 == 0x43e and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f27; dest:x19; op1val:0xc3e0000000000000; valaddr_reg:x3;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x19, f27, dyn, 0, 0, x3, 1*FLEN/8, x4, x8, x6,FLREG)

inst_27:// rs1==f28, rd==x6,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f28; dest:x6; op1val:0xfff0000000000000; valaddr_reg:x3;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x6, f28, dyn, 0, 0, x3, 2*FLEN/8, x4, x8, x2,FLREG)
RVTEST_SIGBASE(x1,signature_x1_0)

inst_28:// rs1==f22, rd==x12,
/* opcode: fcvt.wu.d ; op1:f22; dest:x12; op1val:0x0; valaddr_reg:x3;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x12, f22, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)

inst_29:// rs1==f5, rd==x24,
/* opcode: fcvt.wu.d ; op1:f5; dest:x24; op1val:0x0; valaddr_reg:x3;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x24, f5, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)

inst_30:// rs1==f20, rd==x23,
/* opcode: fcvt.wu.d ; op1:f20; dest:x23; op1val:0x0; valaddr_reg:x3;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x23, f20, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)

inst_31:// rs1==f6, rd==x8,
/* opcode: fcvt.wu.d ; op1:f6; dest:x8; op1val:0x0; valaddr_reg:x3;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x8, f6, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)

inst_32:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0xc000000000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbffc000000000000; valaddr_reg:x3;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 0, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
.dword 0x0
.dword 0x3fe248ee18215dfa
.dword 0x3ff0000000000000
.dword 0x3ff4000000000000
.dword 0x3ff8000000000000
.dword 0x3ffc000000000000
.dword 0x4000000000000000
.dword 0x4002000000000000
.dword 0x4004000000000000
.dword 0x4006000000000000
.dword 0x43cb72eb13dc494a
.dword 0x43e0000000000000
.dword 0x7ff0000000000000
.dword 0x7ff0000000000001
.dword 0x7ff8000000000001
.dword 0x8000000000000000
.dword 0xbf80000000000000
.dword 0xbfdb008d57e19f88
.dword 0xbff4000000000000
.dword 0xbff8000000000000
.dword 0xbffc000000000000
.dword 0xc000000000000000
.dword 0xc002000000000000
.dword 0xc004000000000000
.dword 0xc006000000000000
test_dataset_1:
.dword 0xc3d967a4ae26514c
.dword 0xc3e0000000000000
.dword 0xfff0000000000000
.dword 0x0
.dword 0x0
.dword 0x0
.dword 0x0
.dword 0xbffc000000000000
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;


signature_x8_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x8_1:
    .fill 56*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_0:
    .fill 10*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine

tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
    .fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;

#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif

sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
