
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.11.0
// timestamp : Wed Jun 21 10:19:04 2023 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/riscv/update/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/riscv/update/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fsub.s.cgf \
 \
//                  -- xlen 64  \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fsub.s instruction of the RISC-V RV64_Zfinx,RV64_Zdinx extension for the fsub_b5 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV64I_Zfinx,RV64I_Zdinx")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*);def TEST_CASE_1=True;",fsub_b5)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_0:
// rs1 == rd != rs2, rs1==x31, rs2==x30, rd==x31,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x31; op2:x30; dest:x31; op1val:0x7dce622b; op2val:0x7dce622b;
   valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:0; testreg:x2
*/
TEST_FPRR_OP(fsub.s, x31, x31, x30, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)

inst_1:
// rs1 == rs2 == rd, rs1==x29, rs2==x29, rd==x29,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x29; op2:x29; dest:x29; op1val:0x7dce622b; op2val:0x7dce622b;
   valaddr_reg:x3; val_offset:2*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:0; testreg:x2
*/
TEST_FPRR_OP(fsub.s, x29, x29, x29, dyn, 32, 0, x3, 2*FLEN/8, x4, x1, x2)

inst_2:
// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==x28, rs2==x31, rd==x30,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x28; op2:x31; dest:x30; op1val:0x7dce622b; op2val:0x7dce622b;
   valaddr_reg:x3; val_offset:4*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:0; testreg:x2
*/
TEST_FPRR_OP(fsub.s, x30, x28, x31, dyn, 64, 0, x3, 4*FLEN/8, x4, x1, x2)

inst_3:
// rs1 == rs2 != rd, rs1==x27, rs2==x27, rd==x28,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x27; op2:x27; dest:x28; op1val:0x7dce622b; op2val:0x7dce622b;
   valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:0; testreg:x2
*/
TEST_FPRR_OP(fsub.s, x28, x27, x27, dyn, 96, 0, x3, 6*FLEN/8, x4, x1, x2)

inst_4:
// rs2 == rd != rs1, rs1==x30, rs2==x26, rd==x26,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x26; dest:x26; op1val:0x7dce622b; op2val:0x7dce622b;
   valaddr_reg:x3; val_offset:8*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:0; testreg:x2
*/
TEST_FPRR_OP(fsub.s, x26, x30, x26, dyn, 128, 0, x3, 8*FLEN/8, x4, x1, x2)

inst_5:
// rs1==x26, rs2==x28, rd==x27,fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a50c and fs2 == 0 and fe2 == 0xfe and fm2 == 0x12a50c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x26; op2:x28; dest:x27; op1val:0x7f12a50c; op2val:0x7f12a50c;
   valaddr_reg:x3; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:0; testreg:x2
*/
TEST_FPRR_OP(fsub.s, x27, x26, x28, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2)

inst_6:
// rs1==x24, rs2==x23, rd==x25,fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a50c and fs2 == 0 and fe2 == 0xfe and fm2 == 0x12a50c and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x24; op2:x23; dest:x25; op1val:0x7f12a50c; op2val:0x7f12a50c;
   valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:0; testreg:x2
*/
TEST_FPRR_OP(fsub.s, x25, x24, x23, dyn, 32, 0, x3, 12*FLEN/8, x4, x1, x2)

inst_7:
// rs1==x23, rs2==x25, rd==x24,fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a50c and fs2 == 0 and fe2 == 0xfe and fm2 == 0x12a50c and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x23; op2:x25; dest:x24; op1val:0x7f12a50c; op2val:0x7f12a50c;
   valaddr_reg:x3; val_offset:14*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:0; testreg:x2
*/
TEST_FPRR_OP(fsub.s, x24, x23, x25, dyn, 64, 0, x3, 14*FLEN/8, x4, x1, x2)

inst_8:
// rs1==x25, rs2==x24, rd==x23,fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a50c and fs2 == 0 and fe2 == 0xfe and fm2 == 0x12a50c and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x25; op2:x24; dest:x23; op1val:0x7f12a50c; op2val:0x7f12a50c;
   valaddr_reg:x3; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:0; testreg:x2
*/
TEST_FPRR_OP(fsub.s, x23, x25, x24, dyn, 96, 0, x3, 16*FLEN/8, x4, x1, x2)

inst_9:
// rs1==x21, rs2==x20, rd==x22,fs1 == 0 and fe1 == 0xfe and fm1 == 0x12a50c and fs2 == 0 and fe2 == 0xfe and fm2 == 0x12a50c and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x21; op2:x20; dest:x22; op1val:0x7f12a50c; op2val:0x7f12a50c;
   valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:0; testreg:x2
*/
TEST_FPRR_OP(fsub.s, x22, x21, x20, dyn, 128, 0, x3, 18*FLEN/8, x4, x1, x2)

inst_10:
// rs1==x20, rs2==x22, rd==x21,fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x20; op2:x22; dest:x21; op1val:0x7ebe3f3f; op2val:0x7ebe3f3f;
   valaddr_reg:x3; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:0; testreg:x2
*/
TEST_FPRR_OP(fsub.s, x21, x20, x22, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2)

inst_11:
// rs1==x22, rs2==x21, rd==x20,fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x22; op2:x21; dest:x20; op1val:0x7ebe3f3f; op2val:0x7ebe3f3f;
   valaddr_reg:x3; val_offset:22*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:0; testreg:x2
*/
TEST_FPRR_OP(fsub.s, x20, x22, x21, dyn, 32, 0, x3, 22*FLEN/8, x4, x1, x2)

inst_12:
// rs1==x18, rs2==x17, rd==x19,fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x18; op2:x17; dest:x19; op1val:0x7ebe3f3f; op2val:0x7ebe3f3f;
   valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:0; testreg:x2
*/
TEST_FPRR_OP(fsub.s, x19, x18, x17, dyn, 64, 0, x3, 24*FLEN/8, x4, x1, x2)

inst_13:
// rs1==x17, rs2==x19, rd==x18,fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x17; op2:x19; dest:x18; op1val:0x7ebe3f3f; op2val:0x7ebe3f3f;
   valaddr_reg:x3; val_offset:26*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:0; testreg:x2
*/
TEST_FPRR_OP(fsub.s, x18, x17, x19, dyn, 96, 0, x3, 26*FLEN/8, x4, x1, x2)

inst_14:
// rs1==x19, rs2==x18, rd==x17,fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x19; op2:x18; dest:x17; op1val:0x7ebe3f3f; op2val:0x7ebe3f3f;
   valaddr_reg:x3; val_offset:28*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:0; testreg:x2
*/
TEST_FPRR_OP(fsub.s, x17, x19, x18, dyn, 128, 0, x3, 28*FLEN/8, x4, x1, x2)

inst_15:
// rs1==x15, rs2==x14, rd==x16,fs1 == 0 and fe1 == 0xfd and fm1 == 0x7a3631 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7a3631 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x15; op2:x14; dest:x16; op1val:0x7efa3631; op2val:0x7efa3631;
   valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:0; testreg:x2
*/
TEST_FPRR_OP(fsub.s, x16, x15, x14, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)

inst_16:
// rs1==x14, rs2==x16, rd==x15,fs1 == 0 and fe1 == 0xfd and fm1 == 0x7a3631 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7a3631 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x14; op2:x16; dest:x15; op1val:0x7efa3631; op2val:0x7efa3631;
   valaddr_reg:x3; val_offset:32*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:0; testreg:x2
*/
TEST_FPRR_OP(fsub.s, x15, x14, x16, dyn, 32, 0, x3, 32*FLEN/8, x4, x1, x2)

inst_17:
// rs1==x16, rs2==x15, rd==x14,fs1 == 0 and fe1 == 0xfd and fm1 == 0x7a3631 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7a3631 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x16; op2:x15; dest:x14; op1val:0x7efa3631; op2val:0x7efa3631;
   valaddr_reg:x3; val_offset:34*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:0; testreg:x2
*/
TEST_FPRR_OP(fsub.s, x14, x16, x15, dyn, 64, 0, x3, 34*FLEN/8, x4, x1, x2)

inst_18:
// rs1==x12, rs2==x11, rd==x13,fs1 == 0 and fe1 == 0xfd and fm1 == 0x7a3631 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7a3631 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x12; op2:x11; dest:x13; op1val:0x7efa3631; op2val:0x7efa3631;
   valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:0; testreg:x2
*/
TEST_FPRR_OP(fsub.s, x13, x12, x11, dyn, 96, 0, x3, 36*FLEN/8, x4, x1, x2)

inst_19:
// rs1==x11, rs2==x13, rd==x12,fs1 == 0 and fe1 == 0xfd and fm1 == 0x7a3631 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7a3631 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x11; op2:x13; dest:x12; op1val:0x7efa3631; op2val:0x7efa3631;
   valaddr_reg:x3; val_offset:38*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:0; testreg:x2
*/
TEST_FPRR_OP(fsub.s, x12, x11, x13, dyn, 128, 0, x3, 38*FLEN/8, x4, x1, x2)

inst_20:
// rs1==x13, rs2==x12, rd==x11,fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x13; op2:x12; dest:x11; op1val:0x7d902b16; op2val:0x7d902b16;
   valaddr_reg:x3; val_offset:40*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:0; testreg:x2
*/
TEST_FPRR_OP(fsub.s, x11, x13, x12, dyn, 0, 0, x3, 40*FLEN/8, x4, x1, x2)

inst_21:
// rs1==x9, rs2==x8, rd==x10,fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x9; op2:x8; dest:x10; op1val:0x7d902b16; op2val:0x7d902b16;
   valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:0; testreg:x2
*/
TEST_FPRR_OP(fsub.s, x10, x9, x8, dyn, 32, 0, x3, 42*FLEN/8, x4, x1, x2)
RVTEST_VALBASEUPD(x11,test_dataset_1)

inst_22:
// rs1==x8, rs2==x10, rd==x9,fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x8; op2:x10; dest:x9; op1val:0x7d902b16; op2val:0x7d902b16;
   valaddr_reg:x11; val_offset:0*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:0; testreg:x2
*/
TEST_FPRR_OP(fsub.s, x9, x8, x10, dyn, 64, 0, x11, 0*FLEN/8, x12, x1, x2)

inst_23:
// rs1==x10, rs2==x9, rd==x8,fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x10; op2:x9; dest:x8; op1val:0x7d902b16; op2val:0x7d902b16;
   valaddr_reg:x11; val_offset:2*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:0; testreg:x2
*/
TEST_FPRR_OP(fsub.s, x8, x10, x9, dyn, 96, 0, x11, 2*FLEN/8, x12, x1, x2)

inst_24:
// rs1==x6, rs2==x5, rd==x7,fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x6; op2:x5; dest:x7; op1val:0x7d902b16; op2val:0x7d902b16;
   valaddr_reg:x11; val_offset:4*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:0; testreg:x2
*/
TEST_FPRR_OP(fsub.s, x7, x6, x5, dyn, 128, 0, x11, 4*FLEN/8, x12, x1, x2)
RVTEST_SIGBASE(x8,signature_x8_0)

inst_25:
// rs1==x5, rs2==x7, rd==x6,fs1 == 0 and fe1 == 0xfe and fm1 == 0x207786 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x207786 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x5; op2:x7; dest:x6; op1val:0x7f207786; op2val:0x7f207786;
   valaddr_reg:x11; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x6, x5, x7, dyn, 0, 0, x11, 6*FLEN/8, x12, x8, x9)

inst_26:
// rs1==x7, rs2==x6, rd==x5,fs1 == 0 and fe1 == 0xfe and fm1 == 0x207786 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x207786 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x7; op2:x6; dest:x5; op1val:0x7f207786; op2val:0x7f207786;
   valaddr_reg:x11; val_offset:8*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x5, x7, x6, dyn, 32, 0, x11, 8*FLEN/8, x12, x8, x9)

inst_27:
// rs1==x3, rs2==x2, rd==x4,fs1 == 0 and fe1 == 0xfe and fm1 == 0x207786 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x207786 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x3; op2:x2; dest:x4; op1val:0x7f207786; op2val:0x7f207786;
   valaddr_reg:x11; val_offset:10*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x4, x3, x2, dyn, 64, 0, x11, 10*FLEN/8, x12, x8, x9)

inst_28:
// rs1==x2, rs2==x4, rd==x3,fs1 == 0 and fe1 == 0xfe and fm1 == 0x207786 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x207786 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x2; op2:x4; dest:x3; op1val:0x7f207786; op2val:0x7f207786;
   valaddr_reg:x11; val_offset:12*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x3, x2, x4, dyn, 96, 0, x11, 12*FLEN/8, x12, x8, x9)

inst_29:
// rs1==x4, rs2==x3, rd==x2,fs1 == 0 and fe1 == 0xfe and fm1 == 0x207786 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x207786 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x4; op2:x3; dest:x2; op1val:0x7f207786; op2val:0x7f207786;
   valaddr_reg:x11; val_offset:14*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x2, x4, x3, dyn, 128, 0, x11, 14*FLEN/8, x12, x8, x9)

inst_30:
// rs1==x1,fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x1; op2:x30; dest:x31; op1val:0x7f125b96; op2val:0x7f125b96;
   valaddr_reg:x11; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x1, x30, dyn, 0, 0, x11, 16*FLEN/8, x12, x8, x9)

inst_31:
// rs1==x0,fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x0; op2:x30; dest:x31; op1val:0x0; op2val:0x7f125b96;
   valaddr_reg:x11; val_offset:18*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x0, x30, dyn, 32, 0, x11, 18*FLEN/8, x12, x8, x9)

inst_32:
// rs2==x1,fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x1; dest:x31; op1val:0x7f125b96; op2val:0x7f125b96;
   valaddr_reg:x11; val_offset:20*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x1, dyn, 64, 0, x11, 20*FLEN/8, x12, x8, x9)

inst_33:
// rs2==x0,fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x0; dest:x31; op1val:0x7f125b96; op2val:0x0;
   valaddr_reg:x11; val_offset:22*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x0, dyn, 96, 0, x11, 22*FLEN/8, x12, x8, x9)

inst_34:
// rd==x1,fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x31; op2:x30; dest:x1; op1val:0x7f125b96; op2val:0x7f125b96;
   valaddr_reg:x11; val_offset:24*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x1, x31, x30, dyn, 128, 0, x11, 24*FLEN/8, x12, x8, x9)

inst_35:
// rd==x0,fs1 == 0 and fe1 == 0xfd and fm1 == 0x2b0757 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x2b0757 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x31; op2:x30; dest:x0; op1val:0x7eab0757; op2val:0x7eab0757;
   valaddr_reg:x11; val_offset:26*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x0, x31, x30, dyn, 0, 0, x11, 26*FLEN/8, x12, x8, x9)

inst_36:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2b0757 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x2b0757 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7eab0757; op2val:0x7eab0757;
   valaddr_reg:x11; val_offset:28*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 32, 0, x11, 28*FLEN/8, x12, x8, x9)

inst_37:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2b0757 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x2b0757 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7eab0757; op2val:0x7eab0757;
   valaddr_reg:x11; val_offset:30*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 64, 0, x11, 30*FLEN/8, x12, x8, x9)

inst_38:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2b0757 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x2b0757 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7eab0757; op2val:0x7eab0757;
   valaddr_reg:x11; val_offset:32*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 96, 0, x11, 32*FLEN/8, x12, x8, x9)

inst_39:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2b0757 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x2b0757 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7eab0757; op2val:0x7eab0757;
   valaddr_reg:x11; val_offset:34*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 128, 0, x11, 34*FLEN/8, x12, x8, x9)

inst_40:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7e2fb07b; op2val:0x7e2fb07b;
   valaddr_reg:x11; val_offset:36*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 0, 0, x11, 36*FLEN/8, x12, x8, x9)

inst_41:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7e2fb07b; op2val:0x7e2fb07b;
   valaddr_reg:x11; val_offset:38*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 32, 0, x11, 38*FLEN/8, x12, x8, x9)

inst_42:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7e2fb07b; op2val:0x7e2fb07b;
   valaddr_reg:x11; val_offset:40*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 64, 0, x11, 40*FLEN/8, x12, x8, x9)

inst_43:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7e2fb07b; op2val:0x7e2fb07b;
   valaddr_reg:x11; val_offset:42*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 96, 0, x11, 42*FLEN/8, x12, x8, x9)

inst_44:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7e2fb07b; op2val:0x7e2fb07b;
   valaddr_reg:x11; val_offset:44*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 128, 0, x11, 44*FLEN/8, x12, x8, x9)

inst_45:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2d12f5 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2d12f5 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f2d12f5; op2val:0x7f2d12f5;
   valaddr_reg:x11; val_offset:46*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 0, 0, x11, 46*FLEN/8, x12, x8, x9)

inst_46:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2d12f5 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2d12f5 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f2d12f5; op2val:0x7f2d12f5;
   valaddr_reg:x11; val_offset:48*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 32, 0, x11, 48*FLEN/8, x12, x8, x9)

inst_47:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2d12f5 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2d12f5 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f2d12f5; op2val:0x7f2d12f5;
   valaddr_reg:x11; val_offset:50*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 64, 0, x11, 50*FLEN/8, x12, x8, x9)

inst_48:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2d12f5 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2d12f5 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f2d12f5; op2val:0x7f2d12f5;
   valaddr_reg:x11; val_offset:52*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 96, 0, x11, 52*FLEN/8, x12, x8, x9)

inst_49:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2d12f5 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2d12f5 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f2d12f5; op2val:0x7f2d12f5;
   valaddr_reg:x11; val_offset:54*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 128, 0, x11, 54*FLEN/8, x12, x8, x9)

inst_50:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x1c56e0 and fs2 == 0 and fe2 == 0xf9 and fm2 == 0x1c56e0 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7c9c56e0; op2val:0x7c9c56e0;
   valaddr_reg:x11; val_offset:56*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 0, 0, x11, 56*FLEN/8, x12, x8, x9)

inst_51:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x1c56e0 and fs2 == 0 and fe2 == 0xf9 and fm2 == 0x1c56e0 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7c9c56e0; op2val:0x7c9c56e0;
   valaddr_reg:x11; val_offset:58*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 32, 0, x11, 58*FLEN/8, x12, x8, x9)

inst_52:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x1c56e0 and fs2 == 0 and fe2 == 0xf9 and fm2 == 0x1c56e0 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7c9c56e0; op2val:0x7c9c56e0;
   valaddr_reg:x11; val_offset:60*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 64, 0, x11, 60*FLEN/8, x12, x8, x9)

inst_53:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x1c56e0 and fs2 == 0 and fe2 == 0xf9 and fm2 == 0x1c56e0 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7c9c56e0; op2val:0x7c9c56e0;
   valaddr_reg:x11; val_offset:62*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 96, 0, x11, 62*FLEN/8, x12, x8, x9)

inst_54:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x1c56e0 and fs2 == 0 and fe2 == 0xf9 and fm2 == 0x1c56e0 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7c9c56e0; op2val:0x7c9c56e0;
   valaddr_reg:x11; val_offset:64*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 128, 0, x11, 64*FLEN/8, x12, x8, x9)

inst_55:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x34510e and fs2 == 0 and fe2 == 0xfe and fm2 == 0x34510e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f34510e; op2val:0x7f34510e;
   valaddr_reg:x11; val_offset:66*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 0, 0, x11, 66*FLEN/8, x12, x8, x9)

inst_56:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x34510e and fs2 == 0 and fe2 == 0xfe and fm2 == 0x34510e and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f34510e; op2val:0x7f34510e;
   valaddr_reg:x11; val_offset:68*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 32, 0, x11, 68*FLEN/8, x12, x8, x9)

inst_57:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x34510e and fs2 == 0 and fe2 == 0xfe and fm2 == 0x34510e and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f34510e; op2val:0x7f34510e;
   valaddr_reg:x11; val_offset:70*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 64, 0, x11, 70*FLEN/8, x12, x8, x9)

inst_58:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x34510e and fs2 == 0 and fe2 == 0xfe and fm2 == 0x34510e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f34510e; op2val:0x7f34510e;
   valaddr_reg:x11; val_offset:72*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 96, 0, x11, 72*FLEN/8, x12, x8, x9)

inst_59:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x34510e and fs2 == 0 and fe2 == 0xfe and fm2 == 0x34510e and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f34510e; op2val:0x7f34510e;
   valaddr_reg:x11; val_offset:74*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 128, 0, x11, 74*FLEN/8, x12, x8, x9)

inst_60:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x26592c and fs2 == 0 and fe2 == 0xfc and fm2 == 0x26592c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7e26592c; op2val:0x7e26592c;
   valaddr_reg:x11; val_offset:76*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 0, 0, x11, 76*FLEN/8, x12, x8, x9)

inst_61:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x26592c and fs2 == 0 and fe2 == 0xfc and fm2 == 0x26592c and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7e26592c; op2val:0x7e26592c;
   valaddr_reg:x11; val_offset:78*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 32, 0, x11, 78*FLEN/8, x12, x8, x9)

inst_62:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x26592c and fs2 == 0 and fe2 == 0xfc and fm2 == 0x26592c and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7e26592c; op2val:0x7e26592c;
   valaddr_reg:x11; val_offset:80*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 64, 0, x11, 80*FLEN/8, x12, x8, x9)

inst_63:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x26592c and fs2 == 0 and fe2 == 0xfc and fm2 == 0x26592c and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7e26592c; op2val:0x7e26592c;
   valaddr_reg:x11; val_offset:82*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 96, 0, x11, 82*FLEN/8, x12, x8, x9)

inst_64:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x26592c and fs2 == 0 and fe2 == 0xfc and fm2 == 0x26592c and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7e26592c; op2val:0x7e26592c;
   valaddr_reg:x11; val_offset:84*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 128, 0, x11, 84*FLEN/8, x12, x8, x9)

inst_65:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x326d35 and fs2 == 0 and fe2 == 0xf9 and fm2 == 0x326d35 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7cb26d35; op2val:0x7cb26d35;
   valaddr_reg:x11; val_offset:86*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 0, 0, x11, 86*FLEN/8, x12, x8, x9)

inst_66:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x326d35 and fs2 == 0 and fe2 == 0xf9 and fm2 == 0x326d35 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7cb26d35; op2val:0x7cb26d35;
   valaddr_reg:x11; val_offset:88*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 32, 0, x11, 88*FLEN/8, x12, x8, x9)

inst_67:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x326d35 and fs2 == 0 and fe2 == 0xf9 and fm2 == 0x326d35 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7cb26d35; op2val:0x7cb26d35;
   valaddr_reg:x11; val_offset:90*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 64, 0, x11, 90*FLEN/8, x12, x8, x9)

inst_68:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x326d35 and fs2 == 0 and fe2 == 0xf9 and fm2 == 0x326d35 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7cb26d35; op2val:0x7cb26d35;
   valaddr_reg:x11; val_offset:92*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 96, 0, x11, 92*FLEN/8, x12, x8, x9)

inst_69:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x326d35 and fs2 == 0 and fe2 == 0xf9 and fm2 == 0x326d35 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7cb26d35; op2val:0x7cb26d35;
   valaddr_reg:x11; val_offset:94*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 128, 0, x11, 94*FLEN/8, x12, x8, x9)

inst_70:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x282619 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x282619 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7ea82619; op2val:0x7ea82619;
   valaddr_reg:x11; val_offset:96*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 0, 0, x11, 96*FLEN/8, x12, x8, x9)

inst_71:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x282619 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x282619 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7ea82619; op2val:0x7ea82619;
   valaddr_reg:x11; val_offset:98*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 32, 0, x11, 98*FLEN/8, x12, x8, x9)

inst_72:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x282619 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x282619 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7ea82619; op2val:0x7ea82619;
   valaddr_reg:x11; val_offset:100*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 64, 0, x11, 100*FLEN/8, x12, x8, x9)

inst_73:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x282619 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x282619 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7ea82619; op2val:0x7ea82619;
   valaddr_reg:x11; val_offset:102*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 96, 0, x11, 102*FLEN/8, x12, x8, x9)

inst_74:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x282619 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x282619 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7ea82619; op2val:0x7ea82619;
   valaddr_reg:x11; val_offset:104*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 128, 0, x11, 104*FLEN/8, x12, x8, x9)

inst_75:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x330244 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x330244 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7e330244; op2val:0x7e330244;
   valaddr_reg:x11; val_offset:106*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 0, 0, x11, 106*FLEN/8, x12, x8, x9)

inst_76:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x330244 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x330244 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7e330244; op2val:0x7e330244;
   valaddr_reg:x11; val_offset:108*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 32, 0, x11, 108*FLEN/8, x12, x8, x9)

inst_77:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x330244 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x330244 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7e330244; op2val:0x7e330244;
   valaddr_reg:x11; val_offset:110*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 64, 0, x11, 110*FLEN/8, x12, x8, x9)

inst_78:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x330244 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x330244 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7e330244; op2val:0x7e330244;
   valaddr_reg:x11; val_offset:112*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 96, 0, x11, 112*FLEN/8, x12, x8, x9)

inst_79:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x330244 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x330244 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7e330244; op2val:0x7e330244;
   valaddr_reg:x11; val_offset:114*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 128, 0, x11, 114*FLEN/8, x12, x8, x9)

inst_80:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x280619 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x280619 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7e280619; op2val:0x7e280619;
   valaddr_reg:x11; val_offset:116*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 0, 0, x11, 116*FLEN/8, x12, x8, x9)

inst_81:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x280619 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x280619 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7e280619; op2val:0x7e280619;
   valaddr_reg:x11; val_offset:118*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 32, 0, x11, 118*FLEN/8, x12, x8, x9)

inst_82:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x280619 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x280619 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7e280619; op2val:0x7e280619;
   valaddr_reg:x11; val_offset:120*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 64, 0, x11, 120*FLEN/8, x12, x8, x9)

inst_83:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x280619 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x280619 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7e280619; op2val:0x7e280619;
   valaddr_reg:x11; val_offset:122*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 96, 0, x11, 122*FLEN/8, x12, x8, x9)

inst_84:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x280619 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x280619 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7e280619; op2val:0x7e280619;
   valaddr_reg:x11; val_offset:124*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 128, 0, x11, 124*FLEN/8, x12, x8, x9)

inst_85:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5e8d61 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x5e8d61 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7e5e8d61; op2val:0x7e5e8d61;
   valaddr_reg:x11; val_offset:126*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 0, 0, x11, 126*FLEN/8, x12, x8, x9)

inst_86:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5e8d61 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x5e8d61 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7e5e8d61; op2val:0x7e5e8d61;
   valaddr_reg:x11; val_offset:128*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 32, 0, x11, 128*FLEN/8, x12, x8, x9)

inst_87:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5e8d61 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x5e8d61 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7e5e8d61; op2val:0x7e5e8d61;
   valaddr_reg:x11; val_offset:130*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 64, 0, x11, 130*FLEN/8, x12, x8, x9)

inst_88:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5e8d61 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x5e8d61 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7e5e8d61; op2val:0x7e5e8d61;
   valaddr_reg:x11; val_offset:132*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 96, 0, x11, 132*FLEN/8, x12, x8, x9)

inst_89:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5e8d61 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x5e8d61 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7e5e8d61; op2val:0x7e5e8d61;
   valaddr_reg:x11; val_offset:134*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 128, 0, x11, 134*FLEN/8, x12, x8, x9)

inst_90:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20d0a1 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x20d0a1 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f20d0a1; op2val:0x7f20d0a1;
   valaddr_reg:x11; val_offset:136*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 0, 0, x11, 136*FLEN/8, x12, x8, x9)

inst_91:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20d0a1 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x20d0a1 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f20d0a1; op2val:0x7f20d0a1;
   valaddr_reg:x11; val_offset:138*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 32, 0, x11, 138*FLEN/8, x12, x8, x9)

inst_92:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20d0a1 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x20d0a1 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f20d0a1; op2val:0x7f20d0a1;
   valaddr_reg:x11; val_offset:140*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 64, 0, x11, 140*FLEN/8, x12, x8, x9)

inst_93:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20d0a1 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x20d0a1 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f20d0a1; op2val:0x7f20d0a1;
   valaddr_reg:x11; val_offset:142*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 96, 0, x11, 142*FLEN/8, x12, x8, x9)

inst_94:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20d0a1 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x20d0a1 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f20d0a1; op2val:0x7f20d0a1;
   valaddr_reg:x11; val_offset:144*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 128, 0, x11, 144*FLEN/8, x12, x8, x9)

inst_95:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x76a41a and fs2 == 0 and fe2 == 0xfd and fm2 == 0x76a41a and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7ef6a41a; op2val:0x7ef6a41a;
   valaddr_reg:x11; val_offset:146*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 0, 0, x11, 146*FLEN/8, x12, x8, x9)

inst_96:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x76a41a and fs2 == 0 and fe2 == 0xfd and fm2 == 0x76a41a and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7ef6a41a; op2val:0x7ef6a41a;
   valaddr_reg:x11; val_offset:148*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 32, 0, x11, 148*FLEN/8, x12, x8, x9)

inst_97:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x76a41a and fs2 == 0 and fe2 == 0xfd and fm2 == 0x76a41a and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7ef6a41a; op2val:0x7ef6a41a;
   valaddr_reg:x11; val_offset:150*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 64, 0, x11, 150*FLEN/8, x12, x8, x9)

inst_98:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x76a41a and fs2 == 0 and fe2 == 0xfd and fm2 == 0x76a41a and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7ef6a41a; op2val:0x7ef6a41a;
   valaddr_reg:x11; val_offset:152*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 96, 0, x11, 152*FLEN/8, x12, x8, x9)

inst_99:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x76a41a and fs2 == 0 and fe2 == 0xfd and fm2 == 0x76a41a and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7ef6a41a; op2val:0x7ef6a41a;
   valaddr_reg:x11; val_offset:154*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 128, 0, x11, 154*FLEN/8, x12, x8, x9)

inst_100:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3e917d and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3e917d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f3e917d; op2val:0x7f3e917d;
   valaddr_reg:x11; val_offset:156*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 0, 0, x11, 156*FLEN/8, x12, x8, x9)

inst_101:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3e917d and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3e917d and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f3e917d; op2val:0x7f3e917d;
   valaddr_reg:x11; val_offset:158*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 32, 0, x11, 158*FLEN/8, x12, x8, x9)

inst_102:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3e917d and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3e917d and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f3e917d; op2val:0x7f3e917d;
   valaddr_reg:x11; val_offset:160*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 64, 0, x11, 160*FLEN/8, x12, x8, x9)

inst_103:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3e917d and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3e917d and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f3e917d; op2val:0x7f3e917d;
   valaddr_reg:x11; val_offset:162*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 96, 0, x11, 162*FLEN/8, x12, x8, x9)

inst_104:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3e917d and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3e917d and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f3e917d; op2val:0x7f3e917d;
   valaddr_reg:x11; val_offset:164*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 128, 0, x11, 164*FLEN/8, x12, x8, x9)

inst_105:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x39afdd and fs2 == 0 and fe2 == 0xfb and fm2 == 0x39afdd and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7db9afdd; op2val:0x7db9afdd;
   valaddr_reg:x11; val_offset:166*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 0, 0, x11, 166*FLEN/8, x12, x8, x9)

inst_106:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x39afdd and fs2 == 0 and fe2 == 0xfb and fm2 == 0x39afdd and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7db9afdd; op2val:0x7db9afdd;
   valaddr_reg:x11; val_offset:168*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 32, 0, x11, 168*FLEN/8, x12, x8, x9)

inst_107:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x39afdd and fs2 == 0 and fe2 == 0xfb and fm2 == 0x39afdd and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7db9afdd; op2val:0x7db9afdd;
   valaddr_reg:x11; val_offset:170*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 64, 0, x11, 170*FLEN/8, x12, x8, x9)

inst_108:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x39afdd and fs2 == 0 and fe2 == 0xfb and fm2 == 0x39afdd and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7db9afdd; op2val:0x7db9afdd;
   valaddr_reg:x11; val_offset:172*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 96, 0, x11, 172*FLEN/8, x12, x8, x9)

inst_109:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x39afdd and fs2 == 0 and fe2 == 0xfb and fm2 == 0x39afdd and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7db9afdd; op2val:0x7db9afdd;
   valaddr_reg:x11; val_offset:174*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 128, 0, x11, 174*FLEN/8, x12, x8, x9)

inst_110:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0a8666 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x0a8666 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f0a8666; op2val:0x7f0a8666;
   valaddr_reg:x11; val_offset:176*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 0, 0, x11, 176*FLEN/8, x12, x8, x9)

inst_111:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0a8666 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x0a8666 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f0a8666; op2val:0x7f0a8666;
   valaddr_reg:x11; val_offset:178*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 32, 0, x11, 178*FLEN/8, x12, x8, x9)

inst_112:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0a8666 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x0a8666 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f0a8666; op2val:0x7f0a8666;
   valaddr_reg:x11; val_offset:180*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 64, 0, x11, 180*FLEN/8, x12, x8, x9)

inst_113:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0a8666 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x0a8666 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f0a8666; op2val:0x7f0a8666;
   valaddr_reg:x11; val_offset:182*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 96, 0, x11, 182*FLEN/8, x12, x8, x9)

inst_114:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0a8666 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x0a8666 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f0a8666; op2val:0x7f0a8666;
   valaddr_reg:x11; val_offset:184*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 128, 0, x11, 184*FLEN/8, x12, x8, x9)

inst_115:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x33cbed and fs2 == 0 and fe2 == 0xfe and fm2 == 0x33cbed and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f33cbed; op2val:0x7f33cbed;
   valaddr_reg:x11; val_offset:186*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 0, 0, x11, 186*FLEN/8, x12, x8, x9)

inst_116:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x33cbed and fs2 == 0 and fe2 == 0xfe and fm2 == 0x33cbed and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f33cbed; op2val:0x7f33cbed;
   valaddr_reg:x11; val_offset:188*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 32, 0, x11, 188*FLEN/8, x12, x8, x9)

inst_117:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x33cbed and fs2 == 0 and fe2 == 0xfe and fm2 == 0x33cbed and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f33cbed; op2val:0x7f33cbed;
   valaddr_reg:x11; val_offset:190*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 64, 0, x11, 190*FLEN/8, x12, x8, x9)

inst_118:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x33cbed and fs2 == 0 and fe2 == 0xfe and fm2 == 0x33cbed and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f33cbed; op2val:0x7f33cbed;
   valaddr_reg:x11; val_offset:192*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 96, 0, x11, 192*FLEN/8, x12, x8, x9)

inst_119:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x33cbed and fs2 == 0 and fe2 == 0xfe and fm2 == 0x33cbed and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f33cbed; op2val:0x7f33cbed;
   valaddr_reg:x11; val_offset:194*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 128, 0, x11, 194*FLEN/8, x12, x8, x9)

inst_120:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f5de9 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x1f5de9 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f1f5de9; op2val:0x7f1f5de9;
   valaddr_reg:x11; val_offset:196*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 0, 0, x11, 196*FLEN/8, x12, x8, x9)

inst_121:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f5de9 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x1f5de9 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f1f5de9; op2val:0x7f1f5de9;
   valaddr_reg:x11; val_offset:198*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 32, 0, x11, 198*FLEN/8, x12, x8, x9)

inst_122:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f5de9 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x1f5de9 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f1f5de9; op2val:0x7f1f5de9;
   valaddr_reg:x11; val_offset:200*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 64, 0, x11, 200*FLEN/8, x12, x8, x9)

inst_123:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f5de9 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x1f5de9 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f1f5de9; op2val:0x7f1f5de9;
   valaddr_reg:x11; val_offset:202*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 96, 0, x11, 202*FLEN/8, x12, x8, x9)

inst_124:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f5de9 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x1f5de9 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f1f5de9; op2val:0x7f1f5de9;
   valaddr_reg:x11; val_offset:204*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 128, 0, x11, 204*FLEN/8, x12, x8, x9)

inst_125:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x68fcac and fs2 == 0 and fe2 == 0xfc and fm2 == 0x68fcac and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7e68fcac; op2val:0x7e68fcac;
   valaddr_reg:x11; val_offset:206*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 0, 0, x11, 206*FLEN/8, x12, x8, x9)

inst_126:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x68fcac and fs2 == 0 and fe2 == 0xfc and fm2 == 0x68fcac and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7e68fcac; op2val:0x7e68fcac;
   valaddr_reg:x11; val_offset:208*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 32, 0, x11, 208*FLEN/8, x12, x8, x9)

inst_127:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x68fcac and fs2 == 0 and fe2 == 0xfc and fm2 == 0x68fcac and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7e68fcac; op2val:0x7e68fcac;
   valaddr_reg:x11; val_offset:210*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 64, 0, x11, 210*FLEN/8, x12, x8, x9)

inst_128:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x68fcac and fs2 == 0 and fe2 == 0xfc and fm2 == 0x68fcac and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7e68fcac; op2val:0x7e68fcac;
   valaddr_reg:x11; val_offset:212*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 96, 0, x11, 212*FLEN/8, x12, x8, x9)

inst_129:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x68fcac and fs2 == 0 and fe2 == 0xfc and fm2 == 0x68fcac and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7e68fcac; op2val:0x7e68fcac;
   valaddr_reg:x11; val_offset:214*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 128, 0, x11, 214*FLEN/8, x12, x8, x9)

inst_130:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x296f9b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x296f9b and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f296f9b; op2val:0x7f296f9b;
   valaddr_reg:x11; val_offset:216*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 0, 0, x11, 216*FLEN/8, x12, x8, x9)

inst_131:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x296f9b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x296f9b and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f296f9b; op2val:0x7f296f9b;
   valaddr_reg:x11; val_offset:218*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 32, 0, x11, 218*FLEN/8, x12, x8, x9)

inst_132:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x296f9b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x296f9b and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f296f9b; op2val:0x7f296f9b;
   valaddr_reg:x11; val_offset:220*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 64, 0, x11, 220*FLEN/8, x12, x8, x9)

inst_133:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x296f9b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x296f9b and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f296f9b; op2val:0x7f296f9b;
   valaddr_reg:x11; val_offset:222*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 96, 0, x11, 222*FLEN/8, x12, x8, x9)

inst_134:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x296f9b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x296f9b and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f296f9b; op2val:0x7f296f9b;
   valaddr_reg:x11; val_offset:224*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 128, 0, x11, 224*FLEN/8, x12, x8, x9)

inst_135:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x42076b and fs2 == 0 and fe2 == 0xfd and fm2 == 0x42076b and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7ec2076b; op2val:0x7ec2076b;
   valaddr_reg:x11; val_offset:226*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 0, 0, x11, 226*FLEN/8, x12, x8, x9)

inst_136:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x42076b and fs2 == 0 and fe2 == 0xfd and fm2 == 0x42076b and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7ec2076b; op2val:0x7ec2076b;
   valaddr_reg:x11; val_offset:228*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 32, 0, x11, 228*FLEN/8, x12, x8, x9)

inst_137:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x42076b and fs2 == 0 and fe2 == 0xfd and fm2 == 0x42076b and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7ec2076b; op2val:0x7ec2076b;
   valaddr_reg:x11; val_offset:230*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 64, 0, x11, 230*FLEN/8, x12, x8, x9)

inst_138:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x42076b and fs2 == 0 and fe2 == 0xfd and fm2 == 0x42076b and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7ec2076b; op2val:0x7ec2076b;
   valaddr_reg:x11; val_offset:232*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 96, 0, x11, 232*FLEN/8, x12, x8, x9)

inst_139:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x42076b and fs2 == 0 and fe2 == 0xfd and fm2 == 0x42076b and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7ec2076b; op2val:0x7ec2076b;
   valaddr_reg:x11; val_offset:234*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 128, 0, x11, 234*FLEN/8, x12, x8, x9)

inst_140:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x54206e and fs2 == 0 and fe2 == 0xf9 and fm2 == 0x54206e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7cd4206e; op2val:0x7cd4206e;
   valaddr_reg:x11; val_offset:236*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 0, 0, x11, 236*FLEN/8, x12, x8, x9)

inst_141:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x54206e and fs2 == 0 and fe2 == 0xf9 and fm2 == 0x54206e and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7cd4206e; op2val:0x7cd4206e;
   valaddr_reg:x11; val_offset:238*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 32, 0, x11, 238*FLEN/8, x12, x8, x9)

inst_142:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x54206e and fs2 == 0 and fe2 == 0xf9 and fm2 == 0x54206e and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7cd4206e; op2val:0x7cd4206e;
   valaddr_reg:x11; val_offset:240*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 64, 0, x11, 240*FLEN/8, x12, x8, x9)

inst_143:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x54206e and fs2 == 0 and fe2 == 0xf9 and fm2 == 0x54206e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7cd4206e; op2val:0x7cd4206e;
   valaddr_reg:x11; val_offset:242*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 96, 0, x11, 242*FLEN/8, x12, x8, x9)

inst_144:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x54206e and fs2 == 0 and fe2 == 0xf9 and fm2 == 0x54206e and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7cd4206e; op2val:0x7cd4206e;
   valaddr_reg:x11; val_offset:244*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 128, 0, x11, 244*FLEN/8, x12, x8, x9)

inst_145:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191a03 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x191a03 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f191a03; op2val:0x7f191a03;
   valaddr_reg:x11; val_offset:246*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 0, 0, x11, 246*FLEN/8, x12, x8, x9)

inst_146:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191a03 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x191a03 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f191a03; op2val:0x7f191a03;
   valaddr_reg:x11; val_offset:248*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 32, 0, x11, 248*FLEN/8, x12, x8, x9)

inst_147:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191a03 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x191a03 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f191a03; op2val:0x7f191a03;
   valaddr_reg:x11; val_offset:250*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 64, 0, x11, 250*FLEN/8, x12, x8, x9)

inst_148:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191a03 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x191a03 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f191a03; op2val:0x7f191a03;
   valaddr_reg:x11; val_offset:252*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 96, 0, x11, 252*FLEN/8, x12, x8, x9)

inst_149:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x191a03 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x191a03 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f191a03; op2val:0x7f191a03;
   valaddr_reg:x11; val_offset:254*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 128, 0, x11, 254*FLEN/8, x12, x8, x9)

inst_150:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x04dea3 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x04dea3 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7e04dea3; op2val:0x7e04dea3;
   valaddr_reg:x11; val_offset:256*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 0, 0, x11, 256*FLEN/8, x12, x8, x9)

inst_151:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x04dea3 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x04dea3 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7e04dea3; op2val:0x7e04dea3;
   valaddr_reg:x11; val_offset:258*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 32, 0, x11, 258*FLEN/8, x12, x8, x9)

inst_152:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x04dea3 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x04dea3 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7e04dea3; op2val:0x7e04dea3;
   valaddr_reg:x11; val_offset:260*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 64, 0, x11, 260*FLEN/8, x12, x8, x9)
RVTEST_SIGBASE(x8,signature_x8_1)

inst_153:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x04dea3 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x04dea3 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7e04dea3; op2val:0x7e04dea3;
   valaddr_reg:x11; val_offset:262*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 96, 0, x11, 262*FLEN/8, x12, x8, x9)

inst_154:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x04dea3 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x04dea3 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7e04dea3; op2val:0x7e04dea3;
   valaddr_reg:x11; val_offset:264*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 128, 0, x11, 264*FLEN/8, x12, x8, x9)

inst_155:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06fbdb and fs2 == 0 and fe2 == 0xfe and fm2 == 0x06fbdb and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f06fbdb; op2val:0x7f06fbdb;
   valaddr_reg:x11; val_offset:266*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 0, 0, x11, 266*FLEN/8, x12, x8, x9)

inst_156:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06fbdb and fs2 == 0 and fe2 == 0xfe and fm2 == 0x06fbdb and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f06fbdb; op2val:0x7f06fbdb;
   valaddr_reg:x11; val_offset:268*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 32, 0, x11, 268*FLEN/8, x12, x8, x9)

inst_157:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06fbdb and fs2 == 0 and fe2 == 0xfe and fm2 == 0x06fbdb and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f06fbdb; op2val:0x7f06fbdb;
   valaddr_reg:x11; val_offset:270*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 64, 0, x11, 270*FLEN/8, x12, x8, x9)

inst_158:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06fbdb and fs2 == 0 and fe2 == 0xfe and fm2 == 0x06fbdb and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f06fbdb; op2val:0x7f06fbdb;
   valaddr_reg:x11; val_offset:272*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 96, 0, x11, 272*FLEN/8, x12, x8, x9)

inst_159:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06fbdb and fs2 == 0 and fe2 == 0xfe and fm2 == 0x06fbdb and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f06fbdb; op2val:0x7f06fbdb;
   valaddr_reg:x11; val_offset:274*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 128, 0, x11, 274*FLEN/8, x12, x8, x9)

inst_160:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0fe2cd and fs2 == 0 and fe2 == 0xfd and fm2 == 0x0fe2cd and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7e8fe2cd; op2val:0x7e8fe2cd;
   valaddr_reg:x11; val_offset:276*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 0, 0, x11, 276*FLEN/8, x12, x8, x9)

inst_161:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0fe2cd and fs2 == 0 and fe2 == 0xfd and fm2 == 0x0fe2cd and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7e8fe2cd; op2val:0x7e8fe2cd;
   valaddr_reg:x11; val_offset:278*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 32, 0, x11, 278*FLEN/8, x12, x8, x9)

inst_162:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0fe2cd and fs2 == 0 and fe2 == 0xfd and fm2 == 0x0fe2cd and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7e8fe2cd; op2val:0x7e8fe2cd;
   valaddr_reg:x11; val_offset:280*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 64, 0, x11, 280*FLEN/8, x12, x8, x9)

inst_163:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0fe2cd and fs2 == 0 and fe2 == 0xfd and fm2 == 0x0fe2cd and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7e8fe2cd; op2val:0x7e8fe2cd;
   valaddr_reg:x11; val_offset:282*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 96, 0, x11, 282*FLEN/8, x12, x8, x9)

inst_164:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0fe2cd and fs2 == 0 and fe2 == 0xfd and fm2 == 0x0fe2cd and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7e8fe2cd; op2val:0x7e8fe2cd;
   valaddr_reg:x11; val_offset:284*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 128, 0, x11, 284*FLEN/8, x12, x8, x9)

inst_165:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x433c5b and fs2 == 0 and fe2 == 0xfd and fm2 == 0x433c5b and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7ec33c5b; op2val:0x7ec33c5b;
   valaddr_reg:x11; val_offset:286*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 0, 0, x11, 286*FLEN/8, x12, x8, x9)

inst_166:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x433c5b and fs2 == 0 and fe2 == 0xfd and fm2 == 0x433c5b and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7ec33c5b; op2val:0x7ec33c5b;
   valaddr_reg:x11; val_offset:288*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 32, 0, x11, 288*FLEN/8, x12, x8, x9)

inst_167:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x433c5b and fs2 == 0 and fe2 == 0xfd and fm2 == 0x433c5b and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7ec33c5b; op2val:0x7ec33c5b;
   valaddr_reg:x11; val_offset:290*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 64, 0, x11, 290*FLEN/8, x12, x8, x9)

inst_168:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x433c5b and fs2 == 0 and fe2 == 0xfd and fm2 == 0x433c5b and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7ec33c5b; op2val:0x7ec33c5b;
   valaddr_reg:x11; val_offset:292*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 96, 0, x11, 292*FLEN/8, x12, x8, x9)

inst_169:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x433c5b and fs2 == 0 and fe2 == 0xfd and fm2 == 0x433c5b and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7ec33c5b; op2val:0x7ec33c5b;
   valaddr_reg:x11; val_offset:294*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 128, 0, x11, 294*FLEN/8, x12, x8, x9)

inst_170:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x480a54 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x480a54 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7ec80a54; op2val:0x7ec80a54;
   valaddr_reg:x11; val_offset:296*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 0, 0, x11, 296*FLEN/8, x12, x8, x9)

inst_171:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x480a54 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x480a54 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7ec80a54; op2val:0x7ec80a54;
   valaddr_reg:x11; val_offset:298*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 32, 0, x11, 298*FLEN/8, x12, x8, x9)

inst_172:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x480a54 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x480a54 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7ec80a54; op2val:0x7ec80a54;
   valaddr_reg:x11; val_offset:300*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 64, 0, x11, 300*FLEN/8, x12, x8, x9)

inst_173:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x480a54 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x480a54 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7ec80a54; op2val:0x7ec80a54;
   valaddr_reg:x11; val_offset:302*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 96, 0, x11, 302*FLEN/8, x12, x8, x9)

inst_174:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x480a54 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x480a54 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7ec80a54; op2val:0x7ec80a54;
   valaddr_reg:x11; val_offset:304*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 128, 0, x11, 304*FLEN/8, x12, x8, x9)

inst_175:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3c0ad4 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3c0ad4 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7ebc0ad4; op2val:0x7ebc0ad4;
   valaddr_reg:x11; val_offset:306*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 0, 0, x11, 306*FLEN/8, x12, x8, x9)

inst_176:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3c0ad4 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3c0ad4 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7ebc0ad4; op2val:0x7ebc0ad4;
   valaddr_reg:x11; val_offset:308*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 32, 0, x11, 308*FLEN/8, x12, x8, x9)

inst_177:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3c0ad4 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3c0ad4 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7ebc0ad4; op2val:0x7ebc0ad4;
   valaddr_reg:x11; val_offset:310*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 64, 0, x11, 310*FLEN/8, x12, x8, x9)

inst_178:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3c0ad4 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3c0ad4 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7ebc0ad4; op2val:0x7ebc0ad4;
   valaddr_reg:x11; val_offset:312*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 96, 0, x11, 312*FLEN/8, x12, x8, x9)

inst_179:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3c0ad4 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3c0ad4 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7ebc0ad4; op2val:0x7ebc0ad4;
   valaddr_reg:x11; val_offset:314*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 128, 0, x11, 314*FLEN/8, x12, x8, x9)

inst_180:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0xfa and fm2 == 0x0597cb and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7d0597cb; op2val:0x7d0597cb;
   valaddr_reg:x11; val_offset:316*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 0, 0, x11, 316*FLEN/8, x12, x8, x9)

inst_181:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0xfa and fm2 == 0x0597cb and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7d0597cb; op2val:0x7d0597cb;
   valaddr_reg:x11; val_offset:318*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 32, 0, x11, 318*FLEN/8, x12, x8, x9)

inst_182:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0xfa and fm2 == 0x0597cb and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7d0597cb; op2val:0x7d0597cb;
   valaddr_reg:x11; val_offset:320*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 64, 0, x11, 320*FLEN/8, x12, x8, x9)

inst_183:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0xfa and fm2 == 0x0597cb and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7d0597cb; op2val:0x7d0597cb;
   valaddr_reg:x11; val_offset:322*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 96, 0, x11, 322*FLEN/8, x12, x8, x9)

inst_184:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x0597cb and fs2 == 0 and fe2 == 0xfa and fm2 == 0x0597cb and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7d0597cb; op2val:0x7d0597cb;
   valaddr_reg:x11; val_offset:324*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 128, 0, x11, 324*FLEN/8, x12, x8, x9)

inst_185:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3cc5a4 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3cc5a4 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f3cc5a4; op2val:0x7f3cc5a4;
   valaddr_reg:x11; val_offset:326*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 0, 0, x11, 326*FLEN/8, x12, x8, x9)

inst_186:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3cc5a4 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3cc5a4 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f3cc5a4; op2val:0x7f3cc5a4;
   valaddr_reg:x11; val_offset:328*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 32, 0, x11, 328*FLEN/8, x12, x8, x9)

inst_187:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3cc5a4 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3cc5a4 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f3cc5a4; op2val:0x7f3cc5a4;
   valaddr_reg:x11; val_offset:330*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 64, 0, x11, 330*FLEN/8, x12, x8, x9)

inst_188:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3cc5a4 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3cc5a4 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f3cc5a4; op2val:0x7f3cc5a4;
   valaddr_reg:x11; val_offset:332*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 96, 0, x11, 332*FLEN/8, x12, x8, x9)

inst_189:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3cc5a4 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3cc5a4 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f3cc5a4; op2val:0x7f3cc5a4;
   valaddr_reg:x11; val_offset:334*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 128, 0, x11, 334*FLEN/8, x12, x8, x9)

inst_190:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17246c and fs2 == 0 and fe2 == 0xfd and fm2 == 0x17246c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7e97246c; op2val:0x7e97246c;
   valaddr_reg:x11; val_offset:336*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 0, 0, x11, 336*FLEN/8, x12, x8, x9)

inst_191:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17246c and fs2 == 0 and fe2 == 0xfd and fm2 == 0x17246c and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7e97246c; op2val:0x7e97246c;
   valaddr_reg:x11; val_offset:338*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 32, 0, x11, 338*FLEN/8, x12, x8, x9)

inst_192:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17246c and fs2 == 0 and fe2 == 0xfd and fm2 == 0x17246c and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7e97246c; op2val:0x7e97246c;
   valaddr_reg:x11; val_offset:340*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 64, 0, x11, 340*FLEN/8, x12, x8, x9)

inst_193:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17246c and fs2 == 0 and fe2 == 0xfd and fm2 == 0x17246c and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7e97246c; op2val:0x7e97246c;
   valaddr_reg:x11; val_offset:342*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 96, 0, x11, 342*FLEN/8, x12, x8, x9)

inst_194:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17246c and fs2 == 0 and fe2 == 0xfd and fm2 == 0x17246c and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7e97246c; op2val:0x7e97246c;
   valaddr_reg:x11; val_offset:344*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 128, 0, x11, 344*FLEN/8, x12, x8, x9)

inst_195:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x40dc0e and fs2 == 0 and fe2 == 0xfd and fm2 == 0x40dc0e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7ec0dc0e; op2val:0x7ec0dc0e;
   valaddr_reg:x11; val_offset:346*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 0, 0, x11, 346*FLEN/8, x12, x8, x9)

inst_196:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x40dc0e and fs2 == 0 and fe2 == 0xfd and fm2 == 0x40dc0e and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7ec0dc0e; op2val:0x7ec0dc0e;
   valaddr_reg:x11; val_offset:348*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 32, 0, x11, 348*FLEN/8, x12, x8, x9)

inst_197:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x40dc0e and fs2 == 0 and fe2 == 0xfd and fm2 == 0x40dc0e and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7ec0dc0e; op2val:0x7ec0dc0e;
   valaddr_reg:x11; val_offset:350*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 64, 0, x11, 350*FLEN/8, x12, x8, x9)

inst_198:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x40dc0e and fs2 == 0 and fe2 == 0xfd and fm2 == 0x40dc0e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7ec0dc0e; op2val:0x7ec0dc0e;
   valaddr_reg:x11; val_offset:352*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 96, 0, x11, 352*FLEN/8, x12, x8, x9)

inst_199:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x40dc0e and fs2 == 0 and fe2 == 0xfd and fm2 == 0x40dc0e and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7ec0dc0e; op2val:0x7ec0dc0e;
   valaddr_reg:x11; val_offset:354*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 128, 0, x11, 354*FLEN/8, x12, x8, x9)

inst_200:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x13f0c0 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x13f0c0 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f13f0c0; op2val:0x7f13f0c0;
   valaddr_reg:x11; val_offset:356*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 0, 0, x11, 356*FLEN/8, x12, x8, x9)

inst_201:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x13f0c0 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x13f0c0 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f13f0c0; op2val:0x7f13f0c0;
   valaddr_reg:x11; val_offset:358*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 32, 0, x11, 358*FLEN/8, x12, x8, x9)

inst_202:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x13f0c0 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x13f0c0 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f13f0c0; op2val:0x7f13f0c0;
   valaddr_reg:x11; val_offset:360*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 64, 0, x11, 360*FLEN/8, x12, x8, x9)

inst_203:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x13f0c0 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x13f0c0 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f13f0c0; op2val:0x7f13f0c0;
   valaddr_reg:x11; val_offset:362*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 96, 0, x11, 362*FLEN/8, x12, x8, x9)

inst_204:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x13f0c0 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x13f0c0 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f13f0c0; op2val:0x7f13f0c0;
   valaddr_reg:x11; val_offset:364*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 128, 0, x11, 364*FLEN/8, x12, x8, x9)

inst_205:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x252cf6 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x252cf6 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f252cf6; op2val:0x7f252cf6;
   valaddr_reg:x11; val_offset:366*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 0, 0, x11, 366*FLEN/8, x12, x8, x9)

inst_206:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x252cf6 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x252cf6 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f252cf6; op2val:0x7f252cf6;
   valaddr_reg:x11; val_offset:368*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 32, 0, x11, 368*FLEN/8, x12, x8, x9)

inst_207:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x252cf6 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x252cf6 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f252cf6; op2val:0x7f252cf6;
   valaddr_reg:x11; val_offset:370*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 64, 0, x11, 370*FLEN/8, x12, x8, x9)

inst_208:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x252cf6 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x252cf6 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f252cf6; op2val:0x7f252cf6;
   valaddr_reg:x11; val_offset:372*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 96, 0, x11, 372*FLEN/8, x12, x8, x9)

inst_209:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x252cf6 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x252cf6 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f252cf6; op2val:0x7f252cf6;
   valaddr_reg:x11; val_offset:374*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 128, 0, x11, 374*FLEN/8, x12, x8, x9)

inst_210:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4549ce and fs2 == 0 and fe2 == 0xfd and fm2 == 0x4549ce and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7ec549ce; op2val:0x7ec549ce;
   valaddr_reg:x11; val_offset:376*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 0, 0, x11, 376*FLEN/8, x12, x8, x9)

inst_211:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4549ce and fs2 == 0 and fe2 == 0xfd and fm2 == 0x4549ce and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7ec549ce; op2val:0x7ec549ce;
   valaddr_reg:x11; val_offset:378*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 32, 0, x11, 378*FLEN/8, x12, x8, x9)

inst_212:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4549ce and fs2 == 0 and fe2 == 0xfd and fm2 == 0x4549ce and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7ec549ce; op2val:0x7ec549ce;
   valaddr_reg:x11; val_offset:380*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 64, 0, x11, 380*FLEN/8, x12, x8, x9)

inst_213:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4549ce and fs2 == 0 and fe2 == 0xfd and fm2 == 0x4549ce and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7ec549ce; op2val:0x7ec549ce;
   valaddr_reg:x11; val_offset:382*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 96, 0, x11, 382*FLEN/8, x12, x8, x9)

inst_214:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4549ce and fs2 == 0 and fe2 == 0xfd and fm2 == 0x4549ce and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7ec549ce; op2val:0x7ec549ce;
   valaddr_reg:x11; val_offset:384*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 128, 0, x11, 384*FLEN/8, x12, x8, x9)

inst_215:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5ddf89 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x5ddf89 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7edddf89; op2val:0x7edddf89;
   valaddr_reg:x11; val_offset:386*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 0, 0, x11, 386*FLEN/8, x12, x8, x9)

inst_216:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5ddf89 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x5ddf89 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7edddf89; op2val:0x7edddf89;
   valaddr_reg:x11; val_offset:388*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 32, 0, x11, 388*FLEN/8, x12, x8, x9)

inst_217:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5ddf89 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x5ddf89 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7edddf89; op2val:0x7edddf89;
   valaddr_reg:x11; val_offset:390*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 64, 0, x11, 390*FLEN/8, x12, x8, x9)

inst_218:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5ddf89 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x5ddf89 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7edddf89; op2val:0x7edddf89;
   valaddr_reg:x11; val_offset:392*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 96, 0, x11, 392*FLEN/8, x12, x8, x9)

inst_219:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5ddf89 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x5ddf89 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7edddf89; op2val:0x7edddf89;
   valaddr_reg:x11; val_offset:394*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 128, 0, x11, 394*FLEN/8, x12, x8, x9)

inst_220:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7dce622b; op2val:0x7dce622b;
   valaddr_reg:x11; val_offset:396*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 32, 0, x11, 396*FLEN/8, x12, x8, x9)

inst_221:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7dce622b; op2val:0x7dce622b;
   valaddr_reg:x11; val_offset:398*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 96, 0, x11, 398*FLEN/8, x12, x8, x9)

inst_222:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f125b96; op2val:0x7f125b96;
   valaddr_reg:x11; val_offset:400*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 32, 0, x11, 400*FLEN/8, x12, x8, x9)

inst_223:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7f125b96; op2val:0x7f125b96;
   valaddr_reg:x11; val_offset:402*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 96, 0, x11, 402*FLEN/8, x12, x8, x9)

inst_224:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2b0757 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x2b0757 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000  
/* opcode: fsub.s ; op1:x30; op2:x29; dest:x31; op1val:0x7eab0757; op2val:0x7eab0757;
   valaddr_reg:x11; val_offset:404*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:0; testreg:x9
*/
TEST_FPRR_OP(fsub.s, x31, x30, x29, dyn, 0, 0, x11, 404*FLEN/8, x12, x8, x9)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(2110677547,64,FLEN)
NAN_BOXED(2110677547,64,FLEN)
NAN_BOXED(2110677547,64,FLEN)
NAN_BOXED(2110677547,64,FLEN)
NAN_BOXED(2110677547,64,FLEN)
NAN_BOXED(2110677547,64,FLEN)
NAN_BOXED(2110677547,64,FLEN)
NAN_BOXED(2110677547,64,FLEN)
NAN_BOXED(2110677547,64,FLEN)
NAN_BOXED(2110677547,64,FLEN)
NAN_BOXED(2131928332,64,FLEN)
NAN_BOXED(2131928332,64,FLEN)
NAN_BOXED(2131928332,64,FLEN)
NAN_BOXED(2131928332,64,FLEN)
NAN_BOXED(2131928332,64,FLEN)
NAN_BOXED(2131928332,64,FLEN)
NAN_BOXED(2131928332,64,FLEN)
NAN_BOXED(2131928332,64,FLEN)
NAN_BOXED(2131928332,64,FLEN)
NAN_BOXED(2131928332,64,FLEN)
NAN_BOXED(2126397247,64,FLEN)
NAN_BOXED(2126397247,64,FLEN)
NAN_BOXED(2126397247,64,FLEN)
NAN_BOXED(2126397247,64,FLEN)
NAN_BOXED(2126397247,64,FLEN)
NAN_BOXED(2126397247,64,FLEN)
NAN_BOXED(2126397247,64,FLEN)
NAN_BOXED(2126397247,64,FLEN)
NAN_BOXED(2126397247,64,FLEN)
NAN_BOXED(2126397247,64,FLEN)
NAN_BOXED(2130327089,64,FLEN)
NAN_BOXED(2130327089,64,FLEN)
NAN_BOXED(2130327089,64,FLEN)
NAN_BOXED(2130327089,64,FLEN)
NAN_BOXED(2130327089,64,FLEN)
NAN_BOXED(2130327089,64,FLEN)
NAN_BOXED(2130327089,64,FLEN)
NAN_BOXED(2130327089,64,FLEN)
NAN_BOXED(2130327089,64,FLEN)
NAN_BOXED(2130327089,64,FLEN)
NAN_BOXED(2106600214,64,FLEN)
NAN_BOXED(2106600214,64,FLEN)
NAN_BOXED(2106600214,64,FLEN)
NAN_BOXED(2106600214,64,FLEN)
test_dataset_1:
NAN_BOXED(2106600214,32,FLEN)
NAN_BOXED(2106600214,32,FLEN)
NAN_BOXED(2106600214,32,FLEN)
NAN_BOXED(2106600214,32,FLEN)
NAN_BOXED(2106600214,32,FLEN)
NAN_BOXED(2106600214,32,FLEN)
NAN_BOXED(2132834182,32,FLEN)
NAN_BOXED(2132834182,32,FLEN)
NAN_BOXED(2132834182,32,FLEN)
NAN_BOXED(2132834182,32,FLEN)
NAN_BOXED(2132834182,32,FLEN)
NAN_BOXED(2132834182,32,FLEN)
NAN_BOXED(2132834182,32,FLEN)
NAN_BOXED(2132834182,32,FLEN)
NAN_BOXED(2132834182,32,FLEN)
NAN_BOXED(2132834182,32,FLEN)
NAN_BOXED(2131909526,32,FLEN)
NAN_BOXED(2131909526,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2131909526,32,FLEN)
NAN_BOXED(2131909526,32,FLEN)
NAN_BOXED(2131909526,32,FLEN)
NAN_BOXED(2131909526,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2131909526,32,FLEN)
NAN_BOXED(2131909526,32,FLEN)
NAN_BOXED(2125137751,32,FLEN)
NAN_BOXED(2125137751,32,FLEN)
NAN_BOXED(2125137751,32,FLEN)
NAN_BOXED(2125137751,32,FLEN)
NAN_BOXED(2125137751,32,FLEN)
NAN_BOXED(2125137751,32,FLEN)
NAN_BOXED(2125137751,32,FLEN)
NAN_BOXED(2125137751,32,FLEN)
NAN_BOXED(2125137751,32,FLEN)
NAN_BOXED(2125137751,32,FLEN)
NAN_BOXED(2117054587,32,FLEN)
NAN_BOXED(2117054587,32,FLEN)
NAN_BOXED(2117054587,32,FLEN)
NAN_BOXED(2117054587,32,FLEN)
NAN_BOXED(2117054587,32,FLEN)
NAN_BOXED(2117054587,32,FLEN)
NAN_BOXED(2117054587,32,FLEN)
NAN_BOXED(2117054587,32,FLEN)
NAN_BOXED(2117054587,32,FLEN)
NAN_BOXED(2117054587,32,FLEN)
NAN_BOXED(2133660405,32,FLEN)
NAN_BOXED(2133660405,32,FLEN)
NAN_BOXED(2133660405,32,FLEN)
NAN_BOXED(2133660405,32,FLEN)
NAN_BOXED(2133660405,32,FLEN)
NAN_BOXED(2133660405,32,FLEN)
NAN_BOXED(2133660405,32,FLEN)
NAN_BOXED(2133660405,32,FLEN)
NAN_BOXED(2133660405,32,FLEN)
NAN_BOXED(2133660405,32,FLEN)
NAN_BOXED(2090620640,32,FLEN)
NAN_BOXED(2090620640,32,FLEN)
NAN_BOXED(2090620640,32,FLEN)
NAN_BOXED(2090620640,32,FLEN)
NAN_BOXED(2090620640,32,FLEN)
NAN_BOXED(2090620640,32,FLEN)
NAN_BOXED(2090620640,32,FLEN)
NAN_BOXED(2090620640,32,FLEN)
NAN_BOXED(2090620640,32,FLEN)
NAN_BOXED(2090620640,32,FLEN)
NAN_BOXED(2134135054,32,FLEN)
NAN_BOXED(2134135054,32,FLEN)
NAN_BOXED(2134135054,32,FLEN)
NAN_BOXED(2134135054,32,FLEN)
NAN_BOXED(2134135054,32,FLEN)
NAN_BOXED(2134135054,32,FLEN)
NAN_BOXED(2134135054,32,FLEN)
NAN_BOXED(2134135054,32,FLEN)
NAN_BOXED(2134135054,32,FLEN)
NAN_BOXED(2134135054,32,FLEN)
NAN_BOXED(2116442412,32,FLEN)
NAN_BOXED(2116442412,32,FLEN)
NAN_BOXED(2116442412,32,FLEN)
NAN_BOXED(2116442412,32,FLEN)
NAN_BOXED(2116442412,32,FLEN)
NAN_BOXED(2116442412,32,FLEN)
NAN_BOXED(2116442412,32,FLEN)
NAN_BOXED(2116442412,32,FLEN)
NAN_BOXED(2116442412,32,FLEN)
NAN_BOXED(2116442412,32,FLEN)
NAN_BOXED(2092068149,32,FLEN)
NAN_BOXED(2092068149,32,FLEN)
NAN_BOXED(2092068149,32,FLEN)
NAN_BOXED(2092068149,32,FLEN)
NAN_BOXED(2092068149,32,FLEN)
NAN_BOXED(2092068149,32,FLEN)
NAN_BOXED(2092068149,32,FLEN)
NAN_BOXED(2092068149,32,FLEN)
NAN_BOXED(2092068149,32,FLEN)
NAN_BOXED(2092068149,32,FLEN)
NAN_BOXED(2124949017,32,FLEN)
NAN_BOXED(2124949017,32,FLEN)
NAN_BOXED(2124949017,32,FLEN)
NAN_BOXED(2124949017,32,FLEN)
NAN_BOXED(2124949017,32,FLEN)
NAN_BOXED(2124949017,32,FLEN)
NAN_BOXED(2124949017,32,FLEN)
NAN_BOXED(2124949017,32,FLEN)
NAN_BOXED(2124949017,32,FLEN)
NAN_BOXED(2124949017,32,FLEN)
NAN_BOXED(2117272132,32,FLEN)
NAN_BOXED(2117272132,32,FLEN)
NAN_BOXED(2117272132,32,FLEN)
NAN_BOXED(2117272132,32,FLEN)
NAN_BOXED(2117272132,32,FLEN)
NAN_BOXED(2117272132,32,FLEN)
NAN_BOXED(2117272132,32,FLEN)
NAN_BOXED(2117272132,32,FLEN)
NAN_BOXED(2117272132,32,FLEN)
NAN_BOXED(2117272132,32,FLEN)
NAN_BOXED(2116552217,32,FLEN)
NAN_BOXED(2116552217,32,FLEN)
NAN_BOXED(2116552217,32,FLEN)
NAN_BOXED(2116552217,32,FLEN)
NAN_BOXED(2116552217,32,FLEN)
NAN_BOXED(2116552217,32,FLEN)
NAN_BOXED(2116552217,32,FLEN)
NAN_BOXED(2116552217,32,FLEN)
NAN_BOXED(2116552217,32,FLEN)
NAN_BOXED(2116552217,32,FLEN)
NAN_BOXED(2120125793,32,FLEN)
NAN_BOXED(2120125793,32,FLEN)
NAN_BOXED(2120125793,32,FLEN)
NAN_BOXED(2120125793,32,FLEN)
NAN_BOXED(2120125793,32,FLEN)
NAN_BOXED(2120125793,32,FLEN)
NAN_BOXED(2120125793,32,FLEN)
NAN_BOXED(2120125793,32,FLEN)
NAN_BOXED(2120125793,32,FLEN)
NAN_BOXED(2120125793,32,FLEN)
NAN_BOXED(2132856993,32,FLEN)
NAN_BOXED(2132856993,32,FLEN)
NAN_BOXED(2132856993,32,FLEN)
NAN_BOXED(2132856993,32,FLEN)
NAN_BOXED(2132856993,32,FLEN)
NAN_BOXED(2132856993,32,FLEN)
NAN_BOXED(2132856993,32,FLEN)
NAN_BOXED(2132856993,32,FLEN)
NAN_BOXED(2132856993,32,FLEN)
NAN_BOXED(2132856993,32,FLEN)
NAN_BOXED(2130093082,32,FLEN)
NAN_BOXED(2130093082,32,FLEN)
NAN_BOXED(2130093082,32,FLEN)
NAN_BOXED(2130093082,32,FLEN)
NAN_BOXED(2130093082,32,FLEN)
NAN_BOXED(2130093082,32,FLEN)
NAN_BOXED(2130093082,32,FLEN)
NAN_BOXED(2130093082,32,FLEN)
NAN_BOXED(2130093082,32,FLEN)
NAN_BOXED(2130093082,32,FLEN)
NAN_BOXED(2134806909,32,FLEN)
NAN_BOXED(2134806909,32,FLEN)
NAN_BOXED(2134806909,32,FLEN)
NAN_BOXED(2134806909,32,FLEN)
NAN_BOXED(2134806909,32,FLEN)
NAN_BOXED(2134806909,32,FLEN)
NAN_BOXED(2134806909,32,FLEN)
NAN_BOXED(2134806909,32,FLEN)
NAN_BOXED(2134806909,32,FLEN)
NAN_BOXED(2134806909,32,FLEN)
NAN_BOXED(2109321181,32,FLEN)
NAN_BOXED(2109321181,32,FLEN)
NAN_BOXED(2109321181,32,FLEN)
NAN_BOXED(2109321181,32,FLEN)
NAN_BOXED(2109321181,32,FLEN)
NAN_BOXED(2109321181,32,FLEN)
NAN_BOXED(2109321181,32,FLEN)
NAN_BOXED(2109321181,32,FLEN)
NAN_BOXED(2109321181,32,FLEN)
NAN_BOXED(2109321181,32,FLEN)
NAN_BOXED(2131396198,32,FLEN)
NAN_BOXED(2131396198,32,FLEN)
NAN_BOXED(2131396198,32,FLEN)
NAN_BOXED(2131396198,32,FLEN)
NAN_BOXED(2131396198,32,FLEN)
NAN_BOXED(2131396198,32,FLEN)
NAN_BOXED(2131396198,32,FLEN)
NAN_BOXED(2131396198,32,FLEN)
NAN_BOXED(2131396198,32,FLEN)
NAN_BOXED(2131396198,32,FLEN)
NAN_BOXED(2134100973,32,FLEN)
NAN_BOXED(2134100973,32,FLEN)
NAN_BOXED(2134100973,32,FLEN)
NAN_BOXED(2134100973,32,FLEN)
NAN_BOXED(2134100973,32,FLEN)
NAN_BOXED(2134100973,32,FLEN)
NAN_BOXED(2134100973,32,FLEN)
NAN_BOXED(2134100973,32,FLEN)
NAN_BOXED(2134100973,32,FLEN)
NAN_BOXED(2134100973,32,FLEN)
NAN_BOXED(2132762089,32,FLEN)
NAN_BOXED(2132762089,32,FLEN)
NAN_BOXED(2132762089,32,FLEN)
NAN_BOXED(2132762089,32,FLEN)
NAN_BOXED(2132762089,32,FLEN)
NAN_BOXED(2132762089,32,FLEN)
NAN_BOXED(2132762089,32,FLEN)
NAN_BOXED(2132762089,32,FLEN)
NAN_BOXED(2132762089,32,FLEN)
NAN_BOXED(2132762089,32,FLEN)
NAN_BOXED(2120809644,32,FLEN)
NAN_BOXED(2120809644,32,FLEN)
NAN_BOXED(2120809644,32,FLEN)
NAN_BOXED(2120809644,32,FLEN)
NAN_BOXED(2120809644,32,FLEN)
NAN_BOXED(2120809644,32,FLEN)
NAN_BOXED(2120809644,32,FLEN)
NAN_BOXED(2120809644,32,FLEN)
NAN_BOXED(2120809644,32,FLEN)
NAN_BOXED(2120809644,32,FLEN)
NAN_BOXED(2133421979,32,FLEN)
NAN_BOXED(2133421979,32,FLEN)
NAN_BOXED(2133421979,32,FLEN)
NAN_BOXED(2133421979,32,FLEN)
NAN_BOXED(2133421979,32,FLEN)
NAN_BOXED(2133421979,32,FLEN)
NAN_BOXED(2133421979,32,FLEN)
NAN_BOXED(2133421979,32,FLEN)
NAN_BOXED(2133421979,32,FLEN)
NAN_BOXED(2133421979,32,FLEN)
NAN_BOXED(2126645099,32,FLEN)
NAN_BOXED(2126645099,32,FLEN)
NAN_BOXED(2126645099,32,FLEN)
NAN_BOXED(2126645099,32,FLEN)
NAN_BOXED(2126645099,32,FLEN)
NAN_BOXED(2126645099,32,FLEN)
NAN_BOXED(2126645099,32,FLEN)
NAN_BOXED(2126645099,32,FLEN)
NAN_BOXED(2126645099,32,FLEN)
NAN_BOXED(2126645099,32,FLEN)
NAN_BOXED(2094276718,32,FLEN)
NAN_BOXED(2094276718,32,FLEN)
NAN_BOXED(2094276718,32,FLEN)
NAN_BOXED(2094276718,32,FLEN)
NAN_BOXED(2094276718,32,FLEN)
NAN_BOXED(2094276718,32,FLEN)
NAN_BOXED(2094276718,32,FLEN)
NAN_BOXED(2094276718,32,FLEN)
NAN_BOXED(2094276718,32,FLEN)
NAN_BOXED(2094276718,32,FLEN)
NAN_BOXED(2132351491,32,FLEN)
NAN_BOXED(2132351491,32,FLEN)
NAN_BOXED(2132351491,32,FLEN)
NAN_BOXED(2132351491,32,FLEN)
NAN_BOXED(2132351491,32,FLEN)
NAN_BOXED(2132351491,32,FLEN)
NAN_BOXED(2132351491,32,FLEN)
NAN_BOXED(2132351491,32,FLEN)
NAN_BOXED(2132351491,32,FLEN)
NAN_BOXED(2132351491,32,FLEN)
NAN_BOXED(2114248355,32,FLEN)
NAN_BOXED(2114248355,32,FLEN)
NAN_BOXED(2114248355,32,FLEN)
NAN_BOXED(2114248355,32,FLEN)
NAN_BOXED(2114248355,32,FLEN)
NAN_BOXED(2114248355,32,FLEN)
NAN_BOXED(2114248355,32,FLEN)
NAN_BOXED(2114248355,32,FLEN)
NAN_BOXED(2114248355,32,FLEN)
NAN_BOXED(2114248355,32,FLEN)
NAN_BOXED(2131164123,32,FLEN)
NAN_BOXED(2131164123,32,FLEN)
NAN_BOXED(2131164123,32,FLEN)
NAN_BOXED(2131164123,32,FLEN)
NAN_BOXED(2131164123,32,FLEN)
NAN_BOXED(2131164123,32,FLEN)
NAN_BOXED(2131164123,32,FLEN)
NAN_BOXED(2131164123,32,FLEN)
NAN_BOXED(2131164123,32,FLEN)
NAN_BOXED(2131164123,32,FLEN)
NAN_BOXED(2123358925,32,FLEN)
NAN_BOXED(2123358925,32,FLEN)
NAN_BOXED(2123358925,32,FLEN)
NAN_BOXED(2123358925,32,FLEN)
NAN_BOXED(2123358925,32,FLEN)
NAN_BOXED(2123358925,32,FLEN)
NAN_BOXED(2123358925,32,FLEN)
NAN_BOXED(2123358925,32,FLEN)
NAN_BOXED(2123358925,32,FLEN)
NAN_BOXED(2123358925,32,FLEN)
NAN_BOXED(2126724187,32,FLEN)
NAN_BOXED(2126724187,32,FLEN)
NAN_BOXED(2126724187,32,FLEN)
NAN_BOXED(2126724187,32,FLEN)
NAN_BOXED(2126724187,32,FLEN)
NAN_BOXED(2126724187,32,FLEN)
NAN_BOXED(2126724187,32,FLEN)
NAN_BOXED(2126724187,32,FLEN)
NAN_BOXED(2126724187,32,FLEN)
NAN_BOXED(2126724187,32,FLEN)
NAN_BOXED(2127039060,32,FLEN)
NAN_BOXED(2127039060,32,FLEN)
NAN_BOXED(2127039060,32,FLEN)
NAN_BOXED(2127039060,32,FLEN)
NAN_BOXED(2127039060,32,FLEN)
NAN_BOXED(2127039060,32,FLEN)
NAN_BOXED(2127039060,32,FLEN)
NAN_BOXED(2127039060,32,FLEN)
NAN_BOXED(2127039060,32,FLEN)
NAN_BOXED(2127039060,32,FLEN)
NAN_BOXED(2126252756,32,FLEN)
NAN_BOXED(2126252756,32,FLEN)
NAN_BOXED(2126252756,32,FLEN)
NAN_BOXED(2126252756,32,FLEN)
NAN_BOXED(2126252756,32,FLEN)
NAN_BOXED(2126252756,32,FLEN)
NAN_BOXED(2126252756,32,FLEN)
NAN_BOXED(2126252756,32,FLEN)
NAN_BOXED(2126252756,32,FLEN)
NAN_BOXED(2126252756,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(2097518539,32,FLEN)
NAN_BOXED(2134689188,32,FLEN)
NAN_BOXED(2134689188,32,FLEN)
NAN_BOXED(2134689188,32,FLEN)
NAN_BOXED(2134689188,32,FLEN)
NAN_BOXED(2134689188,32,FLEN)
NAN_BOXED(2134689188,32,FLEN)
NAN_BOXED(2134689188,32,FLEN)
NAN_BOXED(2134689188,32,FLEN)
NAN_BOXED(2134689188,32,FLEN)
NAN_BOXED(2134689188,32,FLEN)
NAN_BOXED(2123834476,32,FLEN)
NAN_BOXED(2123834476,32,FLEN)
NAN_BOXED(2123834476,32,FLEN)
NAN_BOXED(2123834476,32,FLEN)
NAN_BOXED(2123834476,32,FLEN)
NAN_BOXED(2123834476,32,FLEN)
NAN_BOXED(2123834476,32,FLEN)
NAN_BOXED(2123834476,32,FLEN)
NAN_BOXED(2123834476,32,FLEN)
NAN_BOXED(2123834476,32,FLEN)
NAN_BOXED(2126568462,32,FLEN)
NAN_BOXED(2126568462,32,FLEN)
NAN_BOXED(2126568462,32,FLEN)
NAN_BOXED(2126568462,32,FLEN)
NAN_BOXED(2126568462,32,FLEN)
NAN_BOXED(2126568462,32,FLEN)
NAN_BOXED(2126568462,32,FLEN)
NAN_BOXED(2126568462,32,FLEN)
NAN_BOXED(2126568462,32,FLEN)
NAN_BOXED(2126568462,32,FLEN)
NAN_BOXED(2132013248,32,FLEN)
NAN_BOXED(2132013248,32,FLEN)
NAN_BOXED(2132013248,32,FLEN)
NAN_BOXED(2132013248,32,FLEN)
NAN_BOXED(2132013248,32,FLEN)
NAN_BOXED(2132013248,32,FLEN)
NAN_BOXED(2132013248,32,FLEN)
NAN_BOXED(2132013248,32,FLEN)
NAN_BOXED(2132013248,32,FLEN)
NAN_BOXED(2132013248,32,FLEN)
NAN_BOXED(2133142774,32,FLEN)
NAN_BOXED(2133142774,32,FLEN)
NAN_BOXED(2133142774,32,FLEN)
NAN_BOXED(2133142774,32,FLEN)
NAN_BOXED(2133142774,32,FLEN)
NAN_BOXED(2133142774,32,FLEN)
NAN_BOXED(2133142774,32,FLEN)
NAN_BOXED(2133142774,32,FLEN)
NAN_BOXED(2133142774,32,FLEN)
NAN_BOXED(2133142774,32,FLEN)
NAN_BOXED(2126858702,32,FLEN)
NAN_BOXED(2126858702,32,FLEN)
NAN_BOXED(2126858702,32,FLEN)
NAN_BOXED(2126858702,32,FLEN)
NAN_BOXED(2126858702,32,FLEN)
NAN_BOXED(2126858702,32,FLEN)
NAN_BOXED(2126858702,32,FLEN)
NAN_BOXED(2126858702,32,FLEN)
NAN_BOXED(2126858702,32,FLEN)
NAN_BOXED(2126858702,32,FLEN)
NAN_BOXED(2128469897,32,FLEN)
NAN_BOXED(2128469897,32,FLEN)
NAN_BOXED(2128469897,32,FLEN)
NAN_BOXED(2128469897,32,FLEN)
NAN_BOXED(2128469897,32,FLEN)
NAN_BOXED(2128469897,32,FLEN)
NAN_BOXED(2128469897,32,FLEN)
NAN_BOXED(2128469897,32,FLEN)
NAN_BOXED(2128469897,32,FLEN)
NAN_BOXED(2128469897,32,FLEN)
NAN_BOXED(2110677547,32,FLEN)
NAN_BOXED(2110677547,32,FLEN)
NAN_BOXED(2110677547,32,FLEN)
NAN_BOXED(2110677547,32,FLEN)
NAN_BOXED(2131909526,32,FLEN)
NAN_BOXED(2131909526,32,FLEN)
NAN_BOXED(2131909526,32,FLEN)
NAN_BOXED(2131909526,32,FLEN)
NAN_BOXED(2125137751,32,FLEN)
NAN_BOXED(2125137751,32,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;



signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 50*((SIGALIGN)/4),4,0xdeadbeef


signature_x8_0:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x8_1:
    .fill 144*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;

mtrap_sigptr:
    .fill 64*XLEN/32,4,0xdeadbeef

tsig_end_canary:
CANARY;
#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif


sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
