
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.12.2
// timestamp : Wed Sep 25 05:22:24 2024 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fdiv.cgf \
 \
//                  -- xlen 32  \
//                  --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fdiv.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fdiv_b4 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fdiv_b4)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x13,test_dataset_0)
RVTEST_SIGBASE(x6,signature_x6_1)

inst_0:
// rs1 == rd != rs2, rs1==x3, rs2==x19, rd==x3,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x0c and fm2 == 0x39d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x3; op2:x19; dest:x3; op1val:0x739c; op2val:0x339d;
   valaddr_reg:x13; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x11
*/
TEST_FPRR_OP(fdiv.h, x3, x3, x19, dyn, 0, 0, x13, 0*FLEN/8, x17, x6, x11)

inst_1:
// rs1 == rs2 != rd, rs1==x26, rs2==x26, rd==x28,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x0c and fm2 == 0x39d and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x26; op2:x26; dest:x28; op1val:0x739c; op2val:0x739c;
   valaddr_reg:x13; val_offset:2*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x11
*/
TEST_FPRR_OP(fdiv.h, x28, x26, x26, dyn, 32, 0, x13, 2*FLEN/8, x17, x6, x11)

inst_2:
// rs1 == rs2 == rd, rs1==x25, rs2==x25, rd==x25,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x0c and fm2 == 0x39d and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x25; op2:x25; dest:x25; op1val:0x739c; op2val:0x739c;
   valaddr_reg:x13; val_offset:4*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x11
*/
TEST_FPRR_OP(fdiv.h, x25, x25, x25, dyn, 64, 0, x13, 4*FLEN/8, x17, x6, x11)

inst_3:
// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==x2, rs2==x10, rd==x29,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x0c and fm2 == 0x39d and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x2; op2:x10; dest:x29; op1val:0x739c; op2val:0x339d;
   valaddr_reg:x13; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x11
*/
TEST_FPRR_OP(fdiv.h, x29, x2, x10, dyn, 96, 0, x13, 6*FLEN/8, x17, x6, x11)

inst_4:
// rs2 == rd != rs1, rs1==x24, rs2==x1, rd==x1,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x0c and fm2 == 0x39d and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x24; op2:x1; dest:x1; op1val:0x739c; op2val:0x339d;
   valaddr_reg:x13; val_offset:8*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x11
*/
TEST_FPRR_OP(fdiv.h, x1, x24, x1, dyn, 128, 0, x13, 8*FLEN/8, x17, x6, x11)

inst_5:
// rs1==x19, rs2==x16, rd==x22,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1eb and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x19; op2:x16; dest:x22; op1val:0x75ea; op2val:0xb5eb;
   valaddr_reg:x13; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x11
*/
TEST_FPRR_OP(fdiv.h, x22, x19, x16, dyn, 0, 0, x13, 10*FLEN/8, x17, x6, x11)

inst_6:
// rs1==x15, rs2==x21, rd==x8,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1eb and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x15; op2:x21; dest:x8; op1val:0x75ea; op2val:0xb5eb;
   valaddr_reg:x13; val_offset:12*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x11
*/
TEST_FPRR_OP(fdiv.h, x8, x15, x21, dyn, 32, 0, x13, 12*FLEN/8, x17, x6, x11)

inst_7:
// rs1==x12, rs2==x20, rd==x16,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1eb and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x12; op2:x20; dest:x16; op1val:0x75ea; op2val:0xb5eb;
   valaddr_reg:x13; val_offset:14*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x11
*/
TEST_FPRR_OP(fdiv.h, x16, x12, x20, dyn, 64, 0, x13, 14*FLEN/8, x17, x6, x11)

inst_8:
// rs1==x9, rs2==x2, rd==x26,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1eb and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x9; op2:x2; dest:x26; op1val:0x75ea; op2val:0xb5eb;
   valaddr_reg:x13; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x11
*/
TEST_FPRR_OP(fdiv.h, x26, x9, x2, dyn, 96, 0, x13, 16*FLEN/8, x17, x6, x11)

inst_9:
// rs1==x1, rs2==x31, rd==x10,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1eb and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x1; op2:x31; dest:x10; op1val:0x75ea; op2val:0xb5eb;
   valaddr_reg:x13; val_offset:18*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x11
*/
TEST_FPRR_OP(fdiv.h, x10, x1, x31, dyn, 128, 0, x13, 18*FLEN/8, x17, x6, x11)

inst_10:
// rs1==x7, rs2==x14, rd==x5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x101 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x7; op2:x14; dest:x5; op1val:0x7900; op2val:0x3901;
   valaddr_reg:x13; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x11
*/
TEST_FPRR_OP(fdiv.h, x5, x7, x14, dyn, 0, 0, x13, 20*FLEN/8, x17, x6, x11)

inst_11:
// rs1==x4, rs2==x22, rd==x21,fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x101 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x4; op2:x22; dest:x21; op1val:0x7900; op2val:0x3901;
   valaddr_reg:x13; val_offset:22*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x11
*/
TEST_FPRR_OP(fdiv.h, x21, x4, x22, dyn, 32, 0, x13, 22*FLEN/8, x17, x6, x11)
RVTEST_VALBASEUPD(x4,test_dataset_1)

inst_12:
// rs1==x18, rs2==x7, rd==x12,fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x101 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x18; op2:x7; dest:x12; op1val:0x7900; op2val:0x3901;
   valaddr_reg:x4; val_offset:0*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x11
*/
TEST_FPRR_OP(fdiv.h, x12, x18, x7, dyn, 64, 0, x4, 0*FLEN/8, x8, x6, x11)

inst_13:
// rs1==x17, rs2==x0, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x101 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x17; op2:x0; dest:x19; op1val:0x7900; op2val:0x0;
   valaddr_reg:x4; val_offset:2*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x11
*/
TEST_FPRR_OP(fdiv.h, x19, x17, x0, dyn, 96, 0, x4, 2*FLEN/8, x8, x6, x11)

inst_14:
// rs1==x22, rs2==x9, rd==x30,fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x101 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x22; op2:x9; dest:x30; op1val:0x7900; op2val:0x3901;
   valaddr_reg:x4; val_offset:4*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x3
*/
TEST_FPRR_OP(fdiv.h, x30, x22, x9, dyn, 128, 0, x4, 4*FLEN/8, x8, x6, x3)
RVTEST_SIGBASE(x1,signature_x1_0)

inst_15:
// rs1==x20, rs2==x24, rd==x31,fs1 == 0 and fe1 == 0x18 and fm1 == 0x2bf and fs2 == 1 and fe2 == 0x08 and fm2 == 0x2bf and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x20; op2:x24; dest:x31; op1val:0x62bf; op2val:0xa2bf;
   valaddr_reg:x4; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x3
*/
TEST_FPRR_OP(fdiv.h, x31, x20, x24, dyn, 0, 0, x4, 6*FLEN/8, x8, x1, x3)

inst_16:
// rs1==x28, rs2==x5, rd==x27,fs1 == 0 and fe1 == 0x18 and fm1 == 0x2bf and fs2 == 1 and fe2 == 0x08 and fm2 == 0x2bf and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x28; op2:x5; dest:x27; op1val:0x62bf; op2val:0xa2bf;
   valaddr_reg:x4; val_offset:8*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x3
*/
TEST_FPRR_OP(fdiv.h, x27, x28, x5, dyn, 32, 0, x4, 8*FLEN/8, x8, x1, x3)

inst_17:
// rs1==x6, rs2==x27, rd==x2,fs1 == 0 and fe1 == 0x18 and fm1 == 0x2bf and fs2 == 1 and fe2 == 0x08 and fm2 == 0x2bf and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x6; op2:x27; dest:x2; op1val:0x62bf; op2val:0xa2bf;
   valaddr_reg:x4; val_offset:10*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x3
*/
TEST_FPRR_OP(fdiv.h, x2, x6, x27, dyn, 64, 0, x4, 10*FLEN/8, x8, x1, x3)

inst_18:
// rs1==x27, rs2==x28, rd==x20,fs1 == 0 and fe1 == 0x18 and fm1 == 0x2bf and fs2 == 1 and fe2 == 0x08 and fm2 == 0x2bf and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x27; op2:x28; dest:x20; op1val:0x62bf; op2val:0xa2bf;
   valaddr_reg:x4; val_offset:12*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x3
*/
TEST_FPRR_OP(fdiv.h, x20, x27, x28, dyn, 96, 0, x4, 12*FLEN/8, x8, x1, x3)

inst_19:
// rs1==x21, rs2==x12, rd==x0,fs1 == 0 and fe1 == 0x18 and fm1 == 0x2bf and fs2 == 1 and fe2 == 0x08 and fm2 == 0x2bf and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x21; op2:x12; dest:x0; op1val:0x62bf; op2val:0xa2bf;
   valaddr_reg:x4; val_offset:14*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x3
*/
TEST_FPRR_OP(fdiv.h, x0, x21, x12, dyn, 128, 0, x4, 14*FLEN/8, x8, x1, x3)

inst_20:
// rs1==x5, rs2==x18, rd==x6,fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x026 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x5; op2:x18; dest:x6; op1val:0x7425; op2val:0x3426;
   valaddr_reg:x4; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x3
*/
TEST_FPRR_OP(fdiv.h, x6, x5, x18, dyn, 0, 0, x4, 16*FLEN/8, x8, x1, x3)

inst_21:
// rs1==x13, rs2==x15, rd==x9,fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x026 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x13; op2:x15; dest:x9; op1val:0x7425; op2val:0x3426;
   valaddr_reg:x4; val_offset:18*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x3
*/
TEST_FPRR_OP(fdiv.h, x9, x13, x15, dyn, 32, 0, x4, 18*FLEN/8, x8, x1, x3)

inst_22:
// rs1==x10, rs2==x6, rd==x17,fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x026 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x10; op2:x6; dest:x17; op1val:0x7425; op2val:0x3426;
   valaddr_reg:x4; val_offset:20*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x3
*/
TEST_FPRR_OP(fdiv.h, x17, x10, x6, dyn, 64, 0, x4, 20*FLEN/8, x8, x1, x3)

inst_23:
// rs1==x14, rs2==x23, rd==x13,fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x026 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x14; op2:x23; dest:x13; op1val:0x7425; op2val:0x3426;
   valaddr_reg:x4; val_offset:22*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x3
*/
TEST_FPRR_OP(fdiv.h, x13, x14, x23, dyn, 96, 0, x4, 22*FLEN/8, x8, x1, x3)
RVTEST_VALBASEUPD(x5,test_dataset_2)

inst_24:
// rs1==x16, rs2==x13, rd==x18,fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x026 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x16; op2:x13; dest:x18; op1val:0x7425; op2val:0x3426;
   valaddr_reg:x5; val_offset:0*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x3
*/
TEST_FPRR_OP(fdiv.h, x18, x16, x13, dyn, 128, 0, x5, 0*FLEN/8, x6, x1, x3)

inst_25:
// rs1==x29, rs2==x17, rd==x23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f6 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3f7 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x29; op2:x17; dest:x23; op1val:0x7bf6; op2val:0xbbf7;
   valaddr_reg:x5; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x3
*/
TEST_FPRR_OP(fdiv.h, x23, x29, x17, dyn, 0, 0, x5, 2*FLEN/8, x6, x1, x3)

inst_26:
// rs1==x8, rs2==x29, rd==x15,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f6 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3f7 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x8; op2:x29; dest:x15; op1val:0x7bf6; op2val:0xbbf7;
   valaddr_reg:x5; val_offset:4*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x3
*/
TEST_FPRR_OP(fdiv.h, x15, x8, x29, dyn, 32, 0, x5, 4*FLEN/8, x6, x1, x3)

inst_27:
// rs1==x30, rs2==x4, rd==x7,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f6 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3f7 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x4; dest:x7; op1val:0x7bf6; op2val:0xbbf7;
   valaddr_reg:x5; val_offset:6*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x3
*/
TEST_FPRR_OP(fdiv.h, x7, x30, x4, dyn, 64, 0, x5, 6*FLEN/8, x6, x1, x3)

inst_28:
// rs1==x11, rs2==x3, rd==x24,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f6 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3f7 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x11; op2:x3; dest:x24; op1val:0x7bf6; op2val:0xbbf7;
   valaddr_reg:x5; val_offset:8*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x24, x11, x3, dyn, 96, 0, x5, 8*FLEN/8, x6, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_29:
// rs1==x0, rs2==x30, rd==x14,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f6 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3f7 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x0; op2:x30; dest:x14; op1val:0x0; op2val:0xbbf7;
   valaddr_reg:x5; val_offset:10*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x14, x0, x30, dyn, 128, 0, x5, 10*FLEN/8, x6, x1, x2)

inst_30:
// rs1==x31, rs2==x11, rd==x4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b1 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x31; op2:x11; dest:x4; op1val:0x7ab0; op2val:0x3ab1;
   valaddr_reg:x5; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x4, x31, x11, dyn, 0, 0, x5, 12*FLEN/8, x6, x1, x2)

inst_31:
// rs1==x23, rs2==x8, rd==x11,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b1 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x23; op2:x8; dest:x11; op1val:0x7ab0; op2val:0x3ab1;
   valaddr_reg:x5; val_offset:14*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x11, x23, x8, dyn, 32, 0, x5, 14*FLEN/8, x6, x1, x2)

inst_32:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b1 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0x3ab1;
   valaddr_reg:x5; val_offset:16*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x5, 16*FLEN/8, x6, x1, x2)

inst_33:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b1 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0x3ab1;
   valaddr_reg:x5; val_offset:18*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x5, 18*FLEN/8, x6, x1, x2)

inst_34:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2b1 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab0; op2val:0x3ab1;
   valaddr_reg:x5; val_offset:20*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x5, 20*FLEN/8, x6, x1, x2)

inst_35:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x11c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x11c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x791c; op2val:0xb91c;
   valaddr_reg:x5; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x5, 22*FLEN/8, x6, x1, x2)

inst_36:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x11c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x11c and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x791c; op2val:0xb91c;
   valaddr_reg:x5; val_offset:24*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x5, 24*FLEN/8, x6, x1, x2)

inst_37:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x11c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x11c and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x791c; op2val:0xb91c;
   valaddr_reg:x5; val_offset:26*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x5, 26*FLEN/8, x6, x1, x2)

inst_38:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x11c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x11c and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x791c; op2val:0xb91c;
   valaddr_reg:x5; val_offset:28*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x5, 28*FLEN/8, x6, x1, x2)

inst_39:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x11c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x11c and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x791c; op2val:0xb91c;
   valaddr_reg:x5; val_offset:30*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x5, 30*FLEN/8, x6, x1, x2)

inst_40:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x114 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0x3914;
   valaddr_reg:x5; val_offset:32*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x5, 32*FLEN/8, x6, x1, x2)

inst_41:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x114 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0x3914;
   valaddr_reg:x5; val_offset:34*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x5, 34*FLEN/8, x6, x1, x2)

inst_42:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x114 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0x3914;
   valaddr_reg:x5; val_offset:36*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x5, 36*FLEN/8, x6, x1, x2)

inst_43:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x114 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0x3914;
   valaddr_reg:x5; val_offset:38*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x5, 38*FLEN/8, x6, x1, x2)

inst_44:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x114 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7913; op2val:0x3914;
   valaddr_reg:x5; val_offset:40*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x5, 40*FLEN/8, x6, x1, x2)

inst_45:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x02f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x782e; op2val:0xb82f;
   valaddr_reg:x5; val_offset:42*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x5, 42*FLEN/8, x6, x1, x2)

inst_46:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x02f and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x782e; op2val:0xb82f;
   valaddr_reg:x5; val_offset:44*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x5, 44*FLEN/8, x6, x1, x2)

inst_47:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x02f and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x782e; op2val:0xb82f;
   valaddr_reg:x5; val_offset:46*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x5, 46*FLEN/8, x6, x1, x2)

inst_48:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x02f and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x782e; op2val:0xb82f;
   valaddr_reg:x5; val_offset:48*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x5, 48*FLEN/8, x6, x1, x2)

inst_49:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x02f and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x782e; op2val:0xb82f;
   valaddr_reg:x5; val_offset:50*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x5, 50*FLEN/8, x6, x1, x2)

inst_50:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x15f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x795e; op2val:0x395f;
   valaddr_reg:x5; val_offset:52*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x5, 52*FLEN/8, x6, x1, x2)

inst_51:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x15f and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x795e; op2val:0x395f;
   valaddr_reg:x5; val_offset:54*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x5, 54*FLEN/8, x6, x1, x2)

inst_52:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x15f and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x795e; op2val:0x395f;
   valaddr_reg:x5; val_offset:56*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x5, 56*FLEN/8, x6, x1, x2)

inst_53:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x15f and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x795e; op2val:0x395f;
   valaddr_reg:x5; val_offset:58*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x5, 58*FLEN/8, x6, x1, x2)

inst_54:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x15f and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x795e; op2val:0x395f;
   valaddr_reg:x5; val_offset:60*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x5, 60*FLEN/8, x6, x1, x2)

inst_55:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x210 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x210 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a10; op2val:0xba10;
   valaddr_reg:x5; val_offset:62*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x5, 62*FLEN/8, x6, x1, x2)

inst_56:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x210 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x210 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a10; op2val:0xba10;
   valaddr_reg:x5; val_offset:64*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x5, 64*FLEN/8, x6, x1, x2)

inst_57:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x210 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x210 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a10; op2val:0xba10;
   valaddr_reg:x5; val_offset:66*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x5, 66*FLEN/8, x6, x1, x2)

inst_58:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x210 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x210 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a10; op2val:0xba10;
   valaddr_reg:x5; val_offset:68*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x5, 68*FLEN/8, x6, x1, x2)

inst_59:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x210 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x210 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a10; op2val:0xba10;
   valaddr_reg:x5; val_offset:70*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x5, 70*FLEN/8, x6, x1, x2)

inst_60:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0d2 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74d1; op2val:0x34d2;
   valaddr_reg:x5; val_offset:72*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x5, 72*FLEN/8, x6, x1, x2)

inst_61:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0d2 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74d1; op2val:0x34d2;
   valaddr_reg:x5; val_offset:74*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x5, 74*FLEN/8, x6, x1, x2)

inst_62:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0d2 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74d1; op2val:0x34d2;
   valaddr_reg:x5; val_offset:76*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x5, 76*FLEN/8, x6, x1, x2)

inst_63:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0d2 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74d1; op2val:0x34d2;
   valaddr_reg:x5; val_offset:78*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x5, 78*FLEN/8, x6, x1, x2)

inst_64:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0d2 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x74d1; op2val:0x34d2;
   valaddr_reg:x5; val_offset:80*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x5, 80*FLEN/8, x6, x1, x2)

inst_65:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2eb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2ec and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aeb; op2val:0xbaec;
   valaddr_reg:x5; val_offset:82*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x5, 82*FLEN/8, x6, x1, x2)

inst_66:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2eb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2ec and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aeb; op2val:0xbaec;
   valaddr_reg:x5; val_offset:84*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x5, 84*FLEN/8, x6, x1, x2)

inst_67:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2eb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2ec and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aeb; op2val:0xbaec;
   valaddr_reg:x5; val_offset:86*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x5, 86*FLEN/8, x6, x1, x2)

inst_68:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2eb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2ec and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aeb; op2val:0xbaec;
   valaddr_reg:x5; val_offset:88*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x5, 88*FLEN/8, x6, x1, x2)

inst_69:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2eb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2ec and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aeb; op2val:0xbaec;
   valaddr_reg:x5; val_offset:90*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x5, 90*FLEN/8, x6, x1, x2)

inst_70:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bf and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1c0 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79bf; op2val:0x45c0;
   valaddr_reg:x5; val_offset:92*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x5, 92*FLEN/8, x6, x1, x2)

inst_71:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bf and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1c0 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79bf; op2val:0x45c0;
   valaddr_reg:x5; val_offset:94*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x5, 94*FLEN/8, x6, x1, x2)

inst_72:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bf and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1c0 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79bf; op2val:0x45c0;
   valaddr_reg:x5; val_offset:96*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x5, 96*FLEN/8, x6, x1, x2)

inst_73:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bf and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1c0 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79bf; op2val:0x45c0;
   valaddr_reg:x5; val_offset:98*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x5, 98*FLEN/8, x6, x1, x2)

inst_74:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bf and fs2 == 0 and fe2 == 0x11 and fm2 == 0x1c0 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79bf; op2val:0x45c0;
   valaddr_reg:x5; val_offset:100*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x5, 100*FLEN/8, x6, x1, x2)

inst_75:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b5 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1b6 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b5; op2val:0xc5b6;
   valaddr_reg:x5; val_offset:102*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x5, 102*FLEN/8, x6, x1, x2)

inst_76:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b5 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1b6 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b5; op2val:0xc5b6;
   valaddr_reg:x5; val_offset:104*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x5, 104*FLEN/8, x6, x1, x2)

inst_77:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b5 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1b6 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b5; op2val:0xc5b6;
   valaddr_reg:x5; val_offset:106*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x5, 106*FLEN/8, x6, x1, x2)

inst_78:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b5 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1b6 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b5; op2val:0xc5b6;
   valaddr_reg:x5; val_offset:108*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x5, 108*FLEN/8, x6, x1, x2)

inst_79:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b5 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1b6 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b5; op2val:0xc5b6;
   valaddr_reg:x5; val_offset:110*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x5, 110*FLEN/8, x6, x1, x2)

inst_80:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x251 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x251 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7651; op2val:0x3e51;
   valaddr_reg:x5; val_offset:112*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x5, 112*FLEN/8, x6, x1, x2)

inst_81:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x251 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x251 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7651; op2val:0x3e51;
   valaddr_reg:x5; val_offset:114*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x5, 114*FLEN/8, x6, x1, x2)

inst_82:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x251 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x251 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7651; op2val:0x3e51;
   valaddr_reg:x5; val_offset:116*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x5, 116*FLEN/8, x6, x1, x2)

inst_83:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x251 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x251 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7651; op2val:0x3e51;
   valaddr_reg:x5; val_offset:118*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x5, 118*FLEN/8, x6, x1, x2)

inst_84:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x251 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x251 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7651; op2val:0x3e51;
   valaddr_reg:x5; val_offset:120*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x5, 120*FLEN/8, x6, x1, x2)

inst_85:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x31d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x771c; op2val:0xbf1d;
   valaddr_reg:x5; val_offset:122*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x5, 122*FLEN/8, x6, x1, x2)

inst_86:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x31d and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x771c; op2val:0xbf1d;
   valaddr_reg:x5; val_offset:124*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x5, 124*FLEN/8, x6, x1, x2)

inst_87:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x31d and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x771c; op2val:0xbf1d;
   valaddr_reg:x5; val_offset:126*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x5, 126*FLEN/8, x6, x1, x2)

inst_88:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x31d and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x771c; op2val:0xbf1d;
   valaddr_reg:x5; val_offset:128*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x5, 128*FLEN/8, x6, x1, x2)

inst_89:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x31d and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x771c; op2val:0xbf1d;
   valaddr_reg:x5; val_offset:130*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x5, 130*FLEN/8, x6, x1, x2)

inst_90:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x307 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x307 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b07; op2val:0x3f07;
   valaddr_reg:x5; val_offset:132*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x5, 132*FLEN/8, x6, x1, x2)

inst_91:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x307 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x307 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b07; op2val:0x3f07;
   valaddr_reg:x5; val_offset:134*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x5, 134*FLEN/8, x6, x1, x2)

inst_92:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x307 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x307 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b07; op2val:0x3f07;
   valaddr_reg:x5; val_offset:136*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x5, 136*FLEN/8, x6, x1, x2)

inst_93:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x307 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x307 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b07; op2val:0x3f07;
   valaddr_reg:x5; val_offset:138*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x5, 138*FLEN/8, x6, x1, x2)

inst_94:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x307 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x307 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b07; op2val:0x3f07;
   valaddr_reg:x5; val_offset:140*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x5, 140*FLEN/8, x6, x1, x2)

inst_95:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x059 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x059 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7059; op2val:0xb459;
   valaddr_reg:x5; val_offset:142*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x5, 142*FLEN/8, x6, x1, x2)

inst_96:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x059 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x059 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7059; op2val:0xb459;
   valaddr_reg:x5; val_offset:144*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x5, 144*FLEN/8, x6, x1, x2)

inst_97:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x059 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x059 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7059; op2val:0xb459;
   valaddr_reg:x5; val_offset:146*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x5, 146*FLEN/8, x6, x1, x2)

inst_98:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x059 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x059 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7059; op2val:0xb459;
   valaddr_reg:x5; val_offset:148*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x5, 148*FLEN/8, x6, x1, x2)

inst_99:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x059 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x059 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7059; op2val:0xb459;
   valaddr_reg:x5; val_offset:150*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x5, 150*FLEN/8, x6, x1, x2)

inst_100:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3b9 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb8; op2val:0x3bb9;
   valaddr_reg:x5; val_offset:152*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x5, 152*FLEN/8, x6, x1, x2)

inst_101:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3b9 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb8; op2val:0x3bb9;
   valaddr_reg:x5; val_offset:154*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x5, 154*FLEN/8, x6, x1, x2)

inst_102:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3b9 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb8; op2val:0x3bb9;
   valaddr_reg:x5; val_offset:156*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x5, 156*FLEN/8, x6, x1, x2)

inst_103:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3b9 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb8; op2val:0x3bb9;
   valaddr_reg:x5; val_offset:158*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x5, 158*FLEN/8, x6, x1, x2)

inst_104:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b8 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x3b9 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb8; op2val:0x3bb9;
   valaddr_reg:x5; val_offset:160*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x5, 160*FLEN/8, x6, x1, x2)

inst_105:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x102 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x103 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7902; op2val:0xb903;
   valaddr_reg:x5; val_offset:162*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x5, 162*FLEN/8, x6, x1, x2)

inst_106:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x102 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x103 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7902; op2val:0xb903;
   valaddr_reg:x5; val_offset:164*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x5, 164*FLEN/8, x6, x1, x2)

inst_107:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x102 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x103 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7902; op2val:0xb903;
   valaddr_reg:x5; val_offset:166*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x5, 166*FLEN/8, x6, x1, x2)

inst_108:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x102 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x103 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7902; op2val:0xb903;
   valaddr_reg:x5; val_offset:168*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x5, 168*FLEN/8, x6, x1, x2)

inst_109:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x102 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x103 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7902; op2val:0xb903;
   valaddr_reg:x5; val_offset:170*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x5, 170*FLEN/8, x6, x1, x2)

inst_110:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00e and fs2 == 0 and fe2 == 0x0d and fm2 == 0x00e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x780e; op2val:0x340e;
   valaddr_reg:x5; val_offset:172*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x5, 172*FLEN/8, x6, x1, x2)

inst_111:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00e and fs2 == 0 and fe2 == 0x0d and fm2 == 0x00e and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x780e; op2val:0x340e;
   valaddr_reg:x5; val_offset:174*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x5, 174*FLEN/8, x6, x1, x2)

inst_112:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00e and fs2 == 0 and fe2 == 0x0d and fm2 == 0x00e and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x780e; op2val:0x340e;
   valaddr_reg:x5; val_offset:176*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x5, 176*FLEN/8, x6, x1, x2)

inst_113:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00e and fs2 == 0 and fe2 == 0x0d and fm2 == 0x00e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x780e; op2val:0x340e;
   valaddr_reg:x5; val_offset:178*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x5, 178*FLEN/8, x6, x1, x2)

inst_114:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00e and fs2 == 0 and fe2 == 0x0d and fm2 == 0x00e and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x780e; op2val:0x340e;
   valaddr_reg:x5; val_offset:180*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x5, 180*FLEN/8, x6, x1, x2)

inst_115:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x19d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x759c; op2val:0xb19d;
   valaddr_reg:x5; val_offset:182*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x5, 182*FLEN/8, x6, x1, x2)

inst_116:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x19d and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x759c; op2val:0xb19d;
   valaddr_reg:x5; val_offset:184*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x5, 184*FLEN/8, x6, x1, x2)

inst_117:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x19d and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x759c; op2val:0xb19d;
   valaddr_reg:x5; val_offset:186*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x5, 186*FLEN/8, x6, x1, x2)

inst_118:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x19d and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x759c; op2val:0xb19d;
   valaddr_reg:x5; val_offset:188*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x5, 188*FLEN/8, x6, x1, x2)

inst_119:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x19c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x19d and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x759c; op2val:0xb19d;
   valaddr_reg:x5; val_offset:190*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x5, 190*FLEN/8, x6, x1, x2)

inst_120:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ab and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0ac and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78ab; op2val:0x30ac;
   valaddr_reg:x5; val_offset:192*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x5, 192*FLEN/8, x6, x1, x2)

inst_121:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ab and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0ac and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78ab; op2val:0x30ac;
   valaddr_reg:x5; val_offset:194*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x5, 194*FLEN/8, x6, x1, x2)

inst_122:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ab and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0ac and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78ab; op2val:0x30ac;
   valaddr_reg:x5; val_offset:196*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x5, 196*FLEN/8, x6, x1, x2)

inst_123:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ab and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0ac and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78ab; op2val:0x30ac;
   valaddr_reg:x5; val_offset:198*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x5, 198*FLEN/8, x6, x1, x2)

inst_124:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ab and fs2 == 0 and fe2 == 0x0c and fm2 == 0x0ac and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x78ab; op2val:0x30ac;
   valaddr_reg:x5; val_offset:200*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x5, 200*FLEN/8, x6, x1, x2)

inst_125:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x174 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x174 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7974; op2val:0xb174;
   valaddr_reg:x5; val_offset:202*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x5, 202*FLEN/8, x6, x1, x2)

inst_126:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x174 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x174 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7974; op2val:0xb174;
   valaddr_reg:x5; val_offset:204*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x5, 204*FLEN/8, x6, x1, x2)

inst_127:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x174 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x174 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7974; op2val:0xb174;
   valaddr_reg:x5; val_offset:206*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x5, 206*FLEN/8, x6, x1, x2)

inst_128:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x174 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x174 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7974; op2val:0xb174;
   valaddr_reg:x5; val_offset:208*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x5, 208*FLEN/8, x6, x1, x2)

inst_129:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x174 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x174 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7974; op2val:0xb174;
   valaddr_reg:x5; val_offset:210*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x5, 210*FLEN/8, x6, x1, x2)

inst_130:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d9 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2d9 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad9; op2val:0x2ed9;
   valaddr_reg:x5; val_offset:212*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x5, 212*FLEN/8, x6, x1, x2)

inst_131:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d9 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2d9 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad9; op2val:0x2ed9;
   valaddr_reg:x5; val_offset:214*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x5, 214*FLEN/8, x6, x1, x2)

inst_132:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d9 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2d9 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad9; op2val:0x2ed9;
   valaddr_reg:x5; val_offset:216*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x5, 216*FLEN/8, x6, x1, x2)

inst_133:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d9 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2d9 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad9; op2val:0x2ed9;
   valaddr_reg:x5; val_offset:218*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x5, 218*FLEN/8, x6, x1, x2)

inst_134:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d9 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x2d9 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad9; op2val:0x2ed9;
   valaddr_reg:x5; val_offset:220*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x5, 220*FLEN/8, x6, x1, x2)

inst_135:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15e and fs2 == 1 and fe2 == 0x0b and fm2 == 0x15e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x795e; op2val:0xad5e;
   valaddr_reg:x5; val_offset:222*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 0, 0, x5, 222*FLEN/8, x6, x1, x2)

inst_136:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15e and fs2 == 1 and fe2 == 0x0b and fm2 == 0x15e and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x795e; op2val:0xad5e;
   valaddr_reg:x5; val_offset:224*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x5, 224*FLEN/8, x6, x1, x2)

inst_137:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15e and fs2 == 1 and fe2 == 0x0b and fm2 == 0x15e and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x795e; op2val:0xad5e;
   valaddr_reg:x5; val_offset:226*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x5, 226*FLEN/8, x6, x1, x2)

inst_138:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15e and fs2 == 1 and fe2 == 0x0b and fm2 == 0x15e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x795e; op2val:0xad5e;
   valaddr_reg:x5; val_offset:228*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x5, 228*FLEN/8, x6, x1, x2)

inst_139:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15e and fs2 == 1 and fe2 == 0x0b and fm2 == 0x15e and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x795e; op2val:0xad5e;
   valaddr_reg:x5; val_offset:230*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x5, 230*FLEN/8, x6, x1, x2)

inst_140:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x0c and fm2 == 0x39d and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x739c; op2val:0x339d;
   valaddr_reg:x5; val_offset:232*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 32, 0, x5, 232*FLEN/8, x6, x1, x2)

inst_141:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x0c and fm2 == 0x39d and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x739c; op2val:0x339d;
   valaddr_reg:x5; val_offset:234*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 64, 0, x5, 234*FLEN/8, x6, x1, x2)

inst_142:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x101 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7900; op2val:0x3901;
   valaddr_reg:x5; val_offset:236*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 96, 0, x5, 236*FLEN/8, x6, x1, x2)

inst_143:
// fs1 == 0 and fe1 == 0x18 and fm1 == 0x2bf and fs2 == 1 and fe2 == 0x08 and fm2 == 0x2bf and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x62bf; op2val:0xa2bf;
   valaddr_reg:x5; val_offset:238*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x5, 238*FLEN/8, x6, x1, x2)

inst_144:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f6 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3f7 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff  
/* opcode: fdiv.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bf6; op2val:0xbbf7;
   valaddr_reg:x5; val_offset:240*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, x31, x30, x29, dyn, 128, 0, x5, 240*FLEN/8, x6, x1, x2)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(29596,32,FLEN)
NAN_BOXED(13213,32,FLEN)
NAN_BOXED(29596,32,FLEN)
NAN_BOXED(29596,32,FLEN)
NAN_BOXED(29596,32,FLEN)
NAN_BOXED(29596,32,FLEN)
NAN_BOXED(29596,32,FLEN)
NAN_BOXED(13213,32,FLEN)
NAN_BOXED(29596,32,FLEN)
NAN_BOXED(13213,32,FLEN)
NAN_BOXED(30186,32,FLEN)
NAN_BOXED(46571,16,FLEN)
NAN_BOXED(30186,32,FLEN)
NAN_BOXED(46571,16,FLEN)
NAN_BOXED(30186,32,FLEN)
NAN_BOXED(46571,16,FLEN)
NAN_BOXED(30186,32,FLEN)
NAN_BOXED(46571,16,FLEN)
NAN_BOXED(30186,32,FLEN)
NAN_BOXED(46571,16,FLEN)
NAN_BOXED(30976,32,FLEN)
NAN_BOXED(14593,32,FLEN)
NAN_BOXED(30976,32,FLEN)
NAN_BOXED(14593,32,FLEN)
test_dataset_1:
NAN_BOXED(30976,32,FLEN)
NAN_BOXED(14593,32,FLEN)
NAN_BOXED(30976,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(30976,32,FLEN)
NAN_BOXED(14593,32,FLEN)
NAN_BOXED(25279,32,FLEN)
NAN_BOXED(41663,16,FLEN)
NAN_BOXED(25279,32,FLEN)
NAN_BOXED(41663,16,FLEN)
NAN_BOXED(25279,32,FLEN)
NAN_BOXED(41663,16,FLEN)
NAN_BOXED(25279,32,FLEN)
NAN_BOXED(41663,16,FLEN)
NAN_BOXED(25279,32,FLEN)
NAN_BOXED(41663,16,FLEN)
NAN_BOXED(29733,32,FLEN)
NAN_BOXED(13350,32,FLEN)
NAN_BOXED(29733,32,FLEN)
NAN_BOXED(13350,32,FLEN)
NAN_BOXED(29733,32,FLEN)
NAN_BOXED(13350,32,FLEN)
NAN_BOXED(29733,32,FLEN)
NAN_BOXED(13350,32,FLEN)
test_dataset_2:
NAN_BOXED(29733,16,FLEN)
NAN_BOXED(13350,16,FLEN)
NAN_BOXED(31734,16,FLEN)
NAN_BOXED(48119,16,FLEN)
NAN_BOXED(31734,16,FLEN)
NAN_BOXED(48119,16,FLEN)
NAN_BOXED(31734,16,FLEN)
NAN_BOXED(48119,16,FLEN)
NAN_BOXED(31734,16,FLEN)
NAN_BOXED(48119,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(48119,16,FLEN)
NAN_BOXED(31408,16,FLEN)
NAN_BOXED(15025,16,FLEN)
NAN_BOXED(31408,16,FLEN)
NAN_BOXED(15025,16,FLEN)
NAN_BOXED(31408,16,FLEN)
NAN_BOXED(15025,16,FLEN)
NAN_BOXED(31408,16,FLEN)
NAN_BOXED(15025,16,FLEN)
NAN_BOXED(31408,16,FLEN)
NAN_BOXED(15025,16,FLEN)
NAN_BOXED(31004,16,FLEN)
NAN_BOXED(47388,16,FLEN)
NAN_BOXED(31004,16,FLEN)
NAN_BOXED(47388,16,FLEN)
NAN_BOXED(31004,16,FLEN)
NAN_BOXED(47388,16,FLEN)
NAN_BOXED(31004,16,FLEN)
NAN_BOXED(47388,16,FLEN)
NAN_BOXED(31004,16,FLEN)
NAN_BOXED(47388,16,FLEN)
NAN_BOXED(30995,16,FLEN)
NAN_BOXED(14612,16,FLEN)
NAN_BOXED(30995,16,FLEN)
NAN_BOXED(14612,16,FLEN)
NAN_BOXED(30995,16,FLEN)
NAN_BOXED(14612,16,FLEN)
NAN_BOXED(30995,16,FLEN)
NAN_BOXED(14612,16,FLEN)
NAN_BOXED(30995,16,FLEN)
NAN_BOXED(14612,16,FLEN)
NAN_BOXED(30766,16,FLEN)
NAN_BOXED(47151,16,FLEN)
NAN_BOXED(30766,16,FLEN)
NAN_BOXED(47151,16,FLEN)
NAN_BOXED(30766,16,FLEN)
NAN_BOXED(47151,16,FLEN)
NAN_BOXED(30766,16,FLEN)
NAN_BOXED(47151,16,FLEN)
NAN_BOXED(30766,16,FLEN)
NAN_BOXED(47151,16,FLEN)
NAN_BOXED(31070,16,FLEN)
NAN_BOXED(14687,16,FLEN)
NAN_BOXED(31070,16,FLEN)
NAN_BOXED(14687,16,FLEN)
NAN_BOXED(31070,16,FLEN)
NAN_BOXED(14687,16,FLEN)
NAN_BOXED(31070,16,FLEN)
NAN_BOXED(14687,16,FLEN)
NAN_BOXED(31070,16,FLEN)
NAN_BOXED(14687,16,FLEN)
NAN_BOXED(31248,16,FLEN)
NAN_BOXED(47632,16,FLEN)
NAN_BOXED(31248,16,FLEN)
NAN_BOXED(47632,16,FLEN)
NAN_BOXED(31248,16,FLEN)
NAN_BOXED(47632,16,FLEN)
NAN_BOXED(31248,16,FLEN)
NAN_BOXED(47632,16,FLEN)
NAN_BOXED(31248,16,FLEN)
NAN_BOXED(47632,16,FLEN)
NAN_BOXED(29905,16,FLEN)
NAN_BOXED(13522,16,FLEN)
NAN_BOXED(29905,16,FLEN)
NAN_BOXED(13522,16,FLEN)
NAN_BOXED(29905,16,FLEN)
NAN_BOXED(13522,16,FLEN)
NAN_BOXED(29905,16,FLEN)
NAN_BOXED(13522,16,FLEN)
NAN_BOXED(29905,16,FLEN)
NAN_BOXED(13522,16,FLEN)
NAN_BOXED(31467,16,FLEN)
NAN_BOXED(47852,16,FLEN)
NAN_BOXED(31467,16,FLEN)
NAN_BOXED(47852,16,FLEN)
NAN_BOXED(31467,16,FLEN)
NAN_BOXED(47852,16,FLEN)
NAN_BOXED(31467,16,FLEN)
NAN_BOXED(47852,16,FLEN)
NAN_BOXED(31467,16,FLEN)
NAN_BOXED(47852,16,FLEN)
NAN_BOXED(31167,16,FLEN)
NAN_BOXED(17856,16,FLEN)
NAN_BOXED(31167,16,FLEN)
NAN_BOXED(17856,16,FLEN)
NAN_BOXED(31167,16,FLEN)
NAN_BOXED(17856,16,FLEN)
NAN_BOXED(31167,16,FLEN)
NAN_BOXED(17856,16,FLEN)
NAN_BOXED(31167,16,FLEN)
NAN_BOXED(17856,16,FLEN)
NAN_BOXED(31157,16,FLEN)
NAN_BOXED(50614,16,FLEN)
NAN_BOXED(31157,16,FLEN)
NAN_BOXED(50614,16,FLEN)
NAN_BOXED(31157,16,FLEN)
NAN_BOXED(50614,16,FLEN)
NAN_BOXED(31157,16,FLEN)
NAN_BOXED(50614,16,FLEN)
NAN_BOXED(31157,16,FLEN)
NAN_BOXED(50614,16,FLEN)
NAN_BOXED(30289,16,FLEN)
NAN_BOXED(15953,16,FLEN)
NAN_BOXED(30289,16,FLEN)
NAN_BOXED(15953,16,FLEN)
NAN_BOXED(30289,16,FLEN)
NAN_BOXED(15953,16,FLEN)
NAN_BOXED(30289,16,FLEN)
NAN_BOXED(15953,16,FLEN)
NAN_BOXED(30289,16,FLEN)
NAN_BOXED(15953,16,FLEN)
NAN_BOXED(30492,16,FLEN)
NAN_BOXED(48925,16,FLEN)
NAN_BOXED(30492,16,FLEN)
NAN_BOXED(48925,16,FLEN)
NAN_BOXED(30492,16,FLEN)
NAN_BOXED(48925,16,FLEN)
NAN_BOXED(30492,16,FLEN)
NAN_BOXED(48925,16,FLEN)
NAN_BOXED(30492,16,FLEN)
NAN_BOXED(48925,16,FLEN)
NAN_BOXED(31495,16,FLEN)
NAN_BOXED(16135,16,FLEN)
NAN_BOXED(31495,16,FLEN)
NAN_BOXED(16135,16,FLEN)
NAN_BOXED(31495,16,FLEN)
NAN_BOXED(16135,16,FLEN)
NAN_BOXED(31495,16,FLEN)
NAN_BOXED(16135,16,FLEN)
NAN_BOXED(31495,16,FLEN)
NAN_BOXED(16135,16,FLEN)
NAN_BOXED(28761,16,FLEN)
NAN_BOXED(46169,16,FLEN)
NAN_BOXED(28761,16,FLEN)
NAN_BOXED(46169,16,FLEN)
NAN_BOXED(28761,16,FLEN)
NAN_BOXED(46169,16,FLEN)
NAN_BOXED(28761,16,FLEN)
NAN_BOXED(46169,16,FLEN)
NAN_BOXED(28761,16,FLEN)
NAN_BOXED(46169,16,FLEN)
NAN_BOXED(31672,16,FLEN)
NAN_BOXED(15289,16,FLEN)
NAN_BOXED(31672,16,FLEN)
NAN_BOXED(15289,16,FLEN)
NAN_BOXED(31672,16,FLEN)
NAN_BOXED(15289,16,FLEN)
NAN_BOXED(31672,16,FLEN)
NAN_BOXED(15289,16,FLEN)
NAN_BOXED(31672,16,FLEN)
NAN_BOXED(15289,16,FLEN)
NAN_BOXED(30978,16,FLEN)
NAN_BOXED(47363,16,FLEN)
NAN_BOXED(30978,16,FLEN)
NAN_BOXED(47363,16,FLEN)
NAN_BOXED(30978,16,FLEN)
NAN_BOXED(47363,16,FLEN)
NAN_BOXED(30978,16,FLEN)
NAN_BOXED(47363,16,FLEN)
NAN_BOXED(30978,16,FLEN)
NAN_BOXED(47363,16,FLEN)
NAN_BOXED(30734,16,FLEN)
NAN_BOXED(13326,16,FLEN)
NAN_BOXED(30734,16,FLEN)
NAN_BOXED(13326,16,FLEN)
NAN_BOXED(30734,16,FLEN)
NAN_BOXED(13326,16,FLEN)
NAN_BOXED(30734,16,FLEN)
NAN_BOXED(13326,16,FLEN)
NAN_BOXED(30734,16,FLEN)
NAN_BOXED(13326,16,FLEN)
NAN_BOXED(30108,16,FLEN)
NAN_BOXED(45469,16,FLEN)
NAN_BOXED(30108,16,FLEN)
NAN_BOXED(45469,16,FLEN)
NAN_BOXED(30108,16,FLEN)
NAN_BOXED(45469,16,FLEN)
NAN_BOXED(30108,16,FLEN)
NAN_BOXED(45469,16,FLEN)
NAN_BOXED(30108,16,FLEN)
NAN_BOXED(45469,16,FLEN)
NAN_BOXED(30891,16,FLEN)
NAN_BOXED(12460,16,FLEN)
NAN_BOXED(30891,16,FLEN)
NAN_BOXED(12460,16,FLEN)
NAN_BOXED(30891,16,FLEN)
NAN_BOXED(12460,16,FLEN)
NAN_BOXED(30891,16,FLEN)
NAN_BOXED(12460,16,FLEN)
NAN_BOXED(30891,16,FLEN)
NAN_BOXED(12460,16,FLEN)
NAN_BOXED(31092,16,FLEN)
NAN_BOXED(45428,16,FLEN)
NAN_BOXED(31092,16,FLEN)
NAN_BOXED(45428,16,FLEN)
NAN_BOXED(31092,16,FLEN)
NAN_BOXED(45428,16,FLEN)
NAN_BOXED(31092,16,FLEN)
NAN_BOXED(45428,16,FLEN)
NAN_BOXED(31092,16,FLEN)
NAN_BOXED(45428,16,FLEN)
NAN_BOXED(31449,16,FLEN)
NAN_BOXED(11993,16,FLEN)
NAN_BOXED(31449,16,FLEN)
NAN_BOXED(11993,16,FLEN)
NAN_BOXED(31449,16,FLEN)
NAN_BOXED(11993,16,FLEN)
NAN_BOXED(31449,16,FLEN)
NAN_BOXED(11993,16,FLEN)
NAN_BOXED(31449,16,FLEN)
NAN_BOXED(11993,16,FLEN)
NAN_BOXED(31070,16,FLEN)
NAN_BOXED(44382,16,FLEN)
NAN_BOXED(31070,16,FLEN)
NAN_BOXED(44382,16,FLEN)
NAN_BOXED(31070,16,FLEN)
NAN_BOXED(44382,16,FLEN)
NAN_BOXED(31070,16,FLEN)
NAN_BOXED(44382,16,FLEN)
NAN_BOXED(31070,16,FLEN)
NAN_BOXED(44382,16,FLEN)
NAN_BOXED(29596,16,FLEN)
NAN_BOXED(13213,16,FLEN)
NAN_BOXED(29596,16,FLEN)
NAN_BOXED(13213,16,FLEN)
NAN_BOXED(30976,16,FLEN)
NAN_BOXED(14593,16,FLEN)
NAN_BOXED(25279,16,FLEN)
NAN_BOXED(41663,16,FLEN)
NAN_BOXED(31734,16,FLEN)
NAN_BOXED(48119,16,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;



signature_x6_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x6_1:
    .fill 30*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_0:
    .fill 28*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 232*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;

mtrap_sigptr:
    .fill 64*XLEN/32,4,0xdeadbeef

tsig_end_canary:
CANARY;
#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif


sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
