
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.7.1
// timestamp : Fri Jun 17 14:17:59 2022 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /scratch/pawan/work/normalised/RV32F/fmadd.s.cgf \
 \
//                  -- xlen 32  \
//                  --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fmadd.s instruction of the RISC-V RV32F_Zicsr,RV32FD_Zicsr,RV64F_Zicsr,RV64FD_Zicsr extension for the fmadd_b18 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*);def TEST_CASE_1=True;",fmadd_b18)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_0:
// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==f21, rs2==f24, rs3==f25, rd==f24,fs1 == 0 and fe1 == 0xf4 and fm1 == 0x60affa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f21; op2:f24; op3:f25; dest:f24; op1val:0x7a60affa; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f24, f21, f24, f25, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)

inst_1:
// rs1 == rs2 == rs3 == rd, rs1==f15, rs2==f15, rs3==f15, rd==f15,fs1 == 0 and fe1 == 0xf5 and fm1 == 0x15d64c and fs2 == 1 and fe2 == 0x33 and fm2 == 0x5ab0da and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f15; op2:f15; op3:f15; dest:f15; op1val:0x7a95d64c; op2val:0x7a95d64c;
op3val:0x7a95d64c; valaddr_reg:x3; val_offset:3*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f15, f15, f15, f15, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2)

inst_2:
// rs1 == rs2 == rd != rs3, rs1==f0, rs2==f0, rs3==f12, rd==f0,fs1 == 0 and fe1 == 0xf5 and fm1 == 0x67c20e and fs2 == 0 and fe2 == 0x87 and fm2 == 0x54154f and fs3 == 1 and fe3 == 0xfe and fm3 == 0x3ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f0; op2:f0; op3:f12; dest:f0; op1val:0x7ae7c20e; op2val:0x7ae7c20e;
op3val:0xff3ffffe; valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f0, f0, f0, f12, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2)

inst_3:
// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==f27, rs2==f17, rs3==f2, rd==f23,fs1 == 0 and fe1 == 0xf7 and fm1 == 0x5aa799 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f27; op2:f17; op3:f2; dest:f23; op1val:0x7bdaa799; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:9*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f23, f27, f17, f2, dyn, 0, 0, x3, 9*FLEN/8, x4, x1, x2)

inst_4:
// rs1 == rs2 == rs3 != rd, rs1==f30, rs2==f30, rs3==f30, rd==f2,fs1 == 0 and fe1 == 0xf8 and fm1 == 0x18d146 and fs2 == 0 and fe2 == 0x30 and fm2 == 0x566cfd and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f30; op3:f30; dest:f2; op1val:0x7c18d146; op2val:0x7c18d146;
op3val:0x7c18d146; valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f2, f30, f30, f30, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2)

inst_5:
// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==f17, rs2==f31, rs3==f20, rd==f17,fs1 == 0 and fe1 == 0xf8 and fm1 == 0x2c8b5e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f17; op2:f31; op3:f20; dest:f17; op1val:0x7c2c8b5e; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:15*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f17, f17, f31, f20, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2)

inst_6:
// rd == rs2 == rs3 != rs1, rs1==f23, rs2==f8, rs3==f8, rd==f8,fs1 == 0 and fe1 == 0xf8 and fm1 == 0x643dc7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f23; op2:f8; op3:f8; dest:f8; op1val:0x7c643dc7; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f8, f23, f8, f8, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2)

inst_7:
// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==f22, rs2==f22, rs3==f1, rd==f31,fs1 == 0 and fe1 == 0xf9 and fm1 == 0x04ef49 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f22; op2:f22; op3:f1; dest:f31; op1val:0x7c84ef49; op2val:0x7c84ef49;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:21*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f22, f22, f1, dyn, 0, 0, x3, 21*FLEN/8, x4, x1, x2)

inst_8:
// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==f31, rs2==f5, rs3==f5, rd==f14,fs1 == 0 and fe1 == 0xf9 and fm1 == 0x0bf9e4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f31; op2:f5; op3:f5; dest:f14; op1val:0x7c8bf9e4; op2val:0x80000000;
op3val:0x80000000; valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f14, f31, f5, f5, dyn, 0, 0, x3, 24*FLEN/8, x4, x1, x2)

inst_9:
// rs1 == rd == rs3 != rs2, rs1==f28, rs2==f18, rs3==f28, rd==f28,fs1 == 0 and fe1 == 0xf9 and fm1 == 0x24066c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f28; op2:f18; op3:f28; dest:f28; op1val:0x7ca4066c; op2val:0x0;
op3val:0x7ca4066c; valaddr_reg:x3; val_offset:27*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f28, f28, f18, f28, dyn, 0, 0, x3, 27*FLEN/8, x4, x1, x2)

inst_10:
// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==f3, rs2==f29, rs3==f3, rd==f9,fs1 == 0 and fe1 == 0xf9 and fm1 == 0x5f97b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f3; op2:f29; op3:f3; dest:f9; op1val:0x7cdf97b9; op2val:0x80000000;
op3val:0x7cdf97b9; valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f9, f3, f29, f3, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)

inst_11:
// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==f19, rs2==f13, rs3==f21, rd==f21,fs1 == 0 and fe1 == 0xf9 and fm1 == 0x71f159 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f19; op2:f13; op3:f21; dest:f21; op1val:0x7cf1f159; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:33*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f21, f19, f13, f21, dyn, 0, 0, x3, 33*FLEN/8, x4, x1, x2)

inst_12:
// rs1==f10, rs2==f20, rs3==f26, rd==f19,fs1 == 0 and fe1 == 0xf9 and fm1 == 0x79d5cb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f10; op2:f20; op3:f26; dest:f19; op1val:0x7cf9d5cb; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f19, f10, f20, f26, dyn, 0, 0, x3, 36*FLEN/8, x4, x1, x2)

inst_13:
// rs1==f26, rs2==f19, rs3==f23, rd==f20,fs1 == 0 and fe1 == 0xfa and fm1 == 0x0109b4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f26; op2:f19; op3:f23; dest:f20; op1val:0x7d0109b4; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:39*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f20, f26, f19, f23, dyn, 0, 0, x3, 39*FLEN/8, x4, x1, x2)

inst_14:
// rs1==f9, rs2==f4, rs3==f17, rd==f27,fs1 == 0 and fe1 == 0xfa and fm1 == 0x0af584 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f9; op2:f4; op3:f17; dest:f27; op1val:0x7d0af584; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f27, f9, f4, f17, dyn, 0, 0, x3, 42*FLEN/8, x4, x1, x2)

inst_15:
// rs1==f7, rs2==f12, rs3==f9, rd==f25,fs1 == 0 and fe1 == 0xfa and fm1 == 0x0c612e and fs2 == 0 and fe2 == 0x2e and fm2 == 0x696c97 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f7; op2:f12; op3:f9; dest:f25; op1val:0x7d0c612e; op2val:0x17696c97;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:45*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f25, f7, f12, f9, dyn, 0, 0, x3, 45*FLEN/8, x4, x1, x2)

inst_16:
// rs1==f2, rs2==f1, rs3==f6, rd==f7,fs1 == 0 and fe1 == 0xfa and fm1 == 0x0fb50a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f2; op2:f1; op3:f6; dest:f7; op1val:0x7d0fb50a; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f7, f2, f1, f6, dyn, 0, 0, x3, 48*FLEN/8, x4, x1, x2)

inst_17:
// rs1==f13, rs2==f3, rs3==f31, rd==f11,fs1 == 0 and fe1 == 0xfa and fm1 == 0x32551e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f13; op2:f3; op3:f31; dest:f11; op1val:0x7d32551e; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:51*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f11, f13, f3, f31, dyn, 0, 0, x3, 51*FLEN/8, x4, x1, x2)

inst_18:
// rs1==f5, rs2==f10, rs3==f29, rd==f26,fs1 == 0 and fe1 == 0xfa and fm1 == 0x772129 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f5; op2:f10; op3:f29; dest:f26; op1val:0x7d772129; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f26, f5, f10, f29, dyn, 0, 0, x3, 54*FLEN/8, x4, x1, x2)

inst_19:
// rs1==f6, rs2==f9, rs3==f19, rd==f4,fs1 == 0 and fe1 == 0xfa and fm1 == 0x79e4a2 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x44b12c and fs3 == 1 and fe3 == 0xfe and fm3 == 0x3ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f6; op2:f9; op3:f19; dest:f4; op1val:0x7d79e4a2; op2val:0x4144b12c;
op3val:0xff3ffffe; valaddr_reg:x3; val_offset:57*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f4, f6, f9, f19, dyn, 0, 0, x3, 57*FLEN/8, x4, x1, x2)

inst_20:
// rs1==f29, rs2==f2, rs3==f4, rd==f6,fs1 == 0 and fe1 == 0xfa and fm1 == 0x7d0cc0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f29; op2:f2; op3:f4; dest:f6; op1val:0x7d7d0cc0; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f6, f29, f2, f4, dyn, 0, 0, x3, 60*FLEN/8, x4, x1, x2)

inst_21:
// rs1==f14, rs2==f26, rs3==f22, rd==f18,fs1 == 0 and fe1 == 0xfb and fm1 == 0x003494 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f14; op2:f26; op3:f22; dest:f18; op1val:0x7d803494; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:63*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f18, f14, f26, f22, dyn, 0, 0, x3, 63*FLEN/8, x4, x1, x2)

inst_22:
// rs1==f4, rs2==f27, rs3==f0, rd==f16,fs1 == 0 and fe1 == 0xfb and fm1 == 0x09f85f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f4; op2:f27; op3:f0; dest:f16; op1val:0x7d89f85f; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f16, f4, f27, f0, dyn, 0, 0, x3, 66*FLEN/8, x4, x1, x2)

inst_23:
// rs1==f1, rs2==f16, rs3==f27, rd==f30,fs1 == 0 and fe1 == 0xfb and fm1 == 0x16325d and fs2 == 0 and fe2 == 0x82 and fm2 == 0x23a019 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f1; op2:f16; op3:f27; dest:f30; op1val:0x7d96325d; op2val:0x4123a019;
op3val:0xff3fffff; valaddr_reg:x3; val_offset:69*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f30, f1, f16, f27, dyn, 0, 0, x3, 69*FLEN/8, x4, x1, x2)

inst_24:
// rs1==f16, rs2==f7, rs3==f10, rd==f22,fs1 == 0 and fe1 == 0xfb and fm1 == 0x19e0a5 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x1fb61f and fs3 == 1 and fe3 == 0xfe and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f16; op2:f7; op3:f10; dest:f22; op1val:0x7d99e0a5; op2val:0x411fb61f;
op3val:0xff3fffff; valaddr_reg:x3; val_offset:72*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f22, f16, f7, f10, dyn, 0, 0, x3, 72*FLEN/8, x4, x1, x2)

inst_25:
// rs1==f8, rs2==f23, rs3==f18, rd==f1,fs1 == 0 and fe1 == 0xfb and fm1 == 0x1a887c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f8; op2:f23; op3:f18; dest:f1; op1val:0x7d9a887c; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:75*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f1, f8, f23, f18, dyn, 0, 0, x3, 75*FLEN/8, x4, x1, x2)

inst_26:
// rs1==f20, rs2==f6, rs3==f13, rd==f29,fs1 == 0 and fe1 == 0xfb and fm1 == 0x1aad53 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f20; op2:f6; op3:f13; dest:f29; op1val:0x7d9aad53; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:78*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f29, f20, f6, f13, dyn, 0, 0, x3, 78*FLEN/8, x4, x1, x2)

inst_27:
// rs1==f18, rs2==f25, rs3==f24, rd==f5,fs1 == 0 and fe1 == 0xfb and fm1 == 0x1b03d8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f18; op2:f25; op3:f24; dest:f5; op1val:0x7d9b03d8; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:81*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f5, f18, f25, f24, dyn, 0, 0, x3, 81*FLEN/8, x4, x1, x2)

inst_28:
// rs1==f12, rs2==f14, rs3==f11, rd==f10,fs1 == 0 and fe1 == 0xfb and fm1 == 0x1be782 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f12; op2:f14; op3:f11; dest:f10; op1val:0x7d9be782; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:84*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f10, f12, f14, f11, dyn, 0, 0, x3, 84*FLEN/8, x4, x1, x2)

inst_29:
// rs1==f24, rs2==f28, rs3==f16, rd==f3,fs1 == 0 and fe1 == 0xfb and fm1 == 0x278349 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f24; op2:f28; op3:f16; dest:f3; op1val:0x7da78349; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:87*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f3, f24, f28, f16, dyn, 0, 0, x3, 87*FLEN/8, x4, x1, x2)

inst_30:
// rs1==f11, rs2==f21, rs3==f7, rd==f13,fs1 == 0 and fe1 == 0xfb and fm1 == 0x33eb13 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f11; op2:f21; op3:f7; dest:f13; op1val:0x7db3eb13; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:90*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f13, f11, f21, f7, dyn, 0, 0, x3, 90*FLEN/8, x4, x1, x2)

inst_31:
// rs1==f25, rs2==f11, rs3==f14, rd==f12,fs1 == 0 and fe1 == 0xfb and fm1 == 0x36a2e9 and fs2 == 0 and fe2 == 0x82 and fm2 == 0x068ffc and fs3 == 1 and fe3 == 0xfe and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f25; op2:f11; op3:f14; dest:f12; op1val:0x7db6a2e9; op2val:0x41068ffc;
op3val:0xff3fffff; valaddr_reg:x3; val_offset:93*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f12, f25, f11, f14, dyn, 0, 0, x3, 93*FLEN/8, x4, x1, x2)

inst_32:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x3e4d8f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dbe4d8f; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:96*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 96*FLEN/8, x4, x1, x2)

inst_33:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4cef18 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7dccef18; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:99*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 99*FLEN/8, x4, x1, x2)

inst_34:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x60ce7f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7de0ce7f; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:102*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 102*FLEN/8, x4, x1, x2)

inst_35:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x67f8b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7de7f8b9; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:105*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 105*FLEN/8, x4, x1, x2)

inst_36:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7234e1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7df234e1; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:108*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 108*FLEN/8, x4, x1, x2)

inst_37:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x021e3b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e021e3b; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:111*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111*FLEN/8, x4, x1, x2)

inst_38:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0642e8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e0642e8; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:114*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 114*FLEN/8, x4, x1, x2)

inst_39:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0a7bf0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e0a7bf0; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:117*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 117*FLEN/8, x4, x1, x2)

inst_40:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0e0ef6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e0e0ef6; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:120*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 120*FLEN/8, x4, x1, x2)

inst_41:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0f6884 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e0f6884; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:123*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 123*FLEN/8, x4, x1, x2)

inst_42:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x10628e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e10628e; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:126*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 126*FLEN/8, x4, x1, x2)

inst_43:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x1173d9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e1173d9; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:129*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 129*FLEN/8, x4, x1, x2)

inst_44:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x12bd51 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e12bd51; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:132*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 132*FLEN/8, x4, x1, x2)

inst_45:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x13b197 and fs2 == 1 and fe2 == 0x2c and fm2 == 0x5ddd52 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e13b197; op2val:0x965ddd52;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:135*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 135*FLEN/8, x4, x1, x2)

inst_46:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x191af1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e191af1; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:138*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 138*FLEN/8, x4, x1, x2)

inst_47:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x1f9fcf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e1f9fcf; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:141*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 141*FLEN/8, x4, x1, x2)

inst_48:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x21b906 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e21b906; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:144*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 144*FLEN/8, x4, x1, x2)

inst_49:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x23fca7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e23fca7; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:147*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 147*FLEN/8, x4, x1, x2)

inst_50:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x29504d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e29504d; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:150*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 150*FLEN/8, x4, x1, x2)

inst_51:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2998cc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e2998cc; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:153*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 153*FLEN/8, x4, x1, x2)

inst_52:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x3741cc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e3741cc; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:156*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 156*FLEN/8, x4, x1, x2)

inst_53:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x37df17 and fs2 == 0 and fe2 == 0x2c and fm2 == 0x323622 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e37df17; op2val:0x16323622;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:159*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 159*FLEN/8, x4, x1, x2)

inst_54:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x386b8e and fs2 == 0 and fe2 == 0x2c and fm2 == 0x31ae65 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e386b8e; op2val:0x1631ae65;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:162*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 162*FLEN/8, x4, x1, x2)

inst_55:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x3aa6be and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e3aa6be; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:165*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 165*FLEN/8, x4, x1, x2)

inst_56:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x3b52d3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e3b52d3; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:168*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 168*FLEN/8, x4, x1, x2)

inst_57:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x40638c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e40638c; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:171*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 171*FLEN/8, x4, x1, x2)

inst_58:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x408722 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e408722; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:174*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 174*FLEN/8, x4, x1, x2)

inst_59:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x40b75e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e40b75e; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:177*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 177*FLEN/8, x4, x1, x2)

inst_60:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x46d91a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e46d91a; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:180*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 180*FLEN/8, x4, x1, x2)

inst_61:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x471615 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e471615; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:183*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 183*FLEN/8, x4, x1, x2)

inst_62:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x479e53 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e479e53; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:186*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 186*FLEN/8, x4, x1, x2)

inst_63:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x480ede and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e480ede; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:189*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 189*FLEN/8, x4, x1, x2)

inst_64:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x52faef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e52faef; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:192*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 192*FLEN/8, x4, x1, x2)

inst_65:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x53afdf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e53afdf; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:195*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 195*FLEN/8, x4, x1, x2)

inst_66:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x55d198 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e55d198; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:198*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 198*FLEN/8, x4, x1, x2)

inst_67:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5706d8 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6495e4 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5706d8; op2val:0x406495e4;
op3val:0xff3fffff; valaddr_reg:x3; val_offset:201*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 201*FLEN/8, x4, x1, x2)

inst_68:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x57b7df and fs2 == 0 and fe2 == 0x2c and fm2 == 0x17e6de and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e57b7df; op2val:0x1617e6de;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:204*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 204*FLEN/8, x4, x1, x2)

inst_69:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e587392; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:207*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 207*FLEN/8, x4, x1, x2)

inst_70:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5d1719 and fs2 == 1 and fe2 == 0x2c and fm2 == 0x143603 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5d1719; op2val:0x96143603;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:210*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 210*FLEN/8, x4, x1, x2)

inst_71:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x5ef919 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e5ef919; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:213*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 213*FLEN/8, x4, x1, x2)

inst_72:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x68f1b4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e68f1b4; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:216*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 216*FLEN/8, x4, x1, x2)

inst_73:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6e317d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e6e317d; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:219*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 219*FLEN/8, x4, x1, x2)

inst_74:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6f30c5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e6f30c5; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:222*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 222*FLEN/8, x4, x1, x2)

inst_75:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6fa925 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e6fa925; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:225*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 225*FLEN/8, x4, x1, x2)

inst_76:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72d2f3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72d2f3; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:228*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 228*FLEN/8, x4, x1, x2)

inst_77:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75cd4b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75cd4b; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:231*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 231*FLEN/8, x4, x1, x2)

inst_78:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x79c1c6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e79c1c6; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:234*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 234*FLEN/8, x4, x1, x2)

inst_79:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7f6343 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7f6343; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:237*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 237*FLEN/8, x4, x1, x2)

inst_80:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x000760 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e800760; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:240*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 240*FLEN/8, x4, x1, x2)

inst_81:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x006905 and fs2 == 1 and fe2 == 0x2b and fm2 == 0x7f2ea0 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e806905; op2val:0x95ff2ea0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:243*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 243*FLEN/8, x4, x1, x2)

inst_82:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x00fdf0 and fs2 == 0 and fe2 == 0x2b and fm2 == 0x7e0807 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e80fdf0; op2val:0x15fe0807;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:246*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 246*FLEN/8, x4, x1, x2)

inst_83:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0372b0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8372b0; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:249*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 249*FLEN/8, x4, x1, x2)

inst_84:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0544b2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8544b2; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:252*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 252*FLEN/8, x4, x1, x2)

inst_85:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x06834b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e86834b; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:255*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 255*FLEN/8, x4, x1, x2)

inst_86:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x07412e and fs2 == 1 and fe2 == 0x2b and fm2 == 0x7244dd and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e87412e; op2val:0x95f244dd;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:258*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 258*FLEN/8, x4, x1, x2)

inst_87:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x092570 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e892570; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:261*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 261*FLEN/8, x4, x1, x2)

inst_88:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x09af6b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e89af6b; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:264*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 264*FLEN/8, x4, x1, x2)

inst_89:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x09eee9 and fs2 == 1 and fe2 == 0x2b and fm2 == 0x6d906e and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e89eee9; op2val:0x95ed906e;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:267*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 267*FLEN/8, x4, x1, x2)

inst_90:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e223c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e223c; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:270*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 270*FLEN/8, x4, x1, x2)

inst_91:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0f0540 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8f0540; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:273*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 273*FLEN/8, x4, x1, x2)

inst_92:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11669e and fs2 == 0 and fe2 == 0x2b and fm2 == 0x615cfa and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91669e; op2val:0x15e15cfa;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:276*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 276*FLEN/8, x4, x1, x2)

inst_93:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x13cd52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e93cd52; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:279*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 279*FLEN/8, x4, x1, x2)

inst_94:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14ffa5 and fs2 == 1 and fe2 == 0x2b and fm2 == 0x5bebe8 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94ffa5; op2val:0x95dbebe8;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:282*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 282*FLEN/8, x4, x1, x2)

inst_95:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163972 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963972; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:285*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 285*FLEN/8, x4, x1, x2)

inst_96:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1641f7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9641f7; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:288*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 288*FLEN/8, x4, x1, x2)

inst_97:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1854d1 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x215521 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9854d1; op2val:0x40215521;
op3val:0xff3fffff; valaddr_reg:x3; val_offset:291*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 291*FLEN/8, x4, x1, x2)

inst_98:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:294*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 294*FLEN/8, x4, x1, x2)

inst_99:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a4c33 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a4c33; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:297*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 297*FLEN/8, x4, x1, x2)

inst_100:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a7876 and fs2 == 0 and fe2 == 0x2b and fm2 == 0x54218c and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a7876; op2val:0x15d4218c;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:300*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 300*FLEN/8, x4, x1, x2)

inst_101:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1b7ea4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9b7ea4; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:303*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 303*FLEN/8, x4, x1, x2)

inst_102:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d6756 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9d6756; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:306*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 306*FLEN/8, x4, x1, x2)

inst_103:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f21ce and fs2 == 0 and fe2 == 0x2b and fm2 == 0x4deac2 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f21ce; op2val:0x15cdeac2;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:309*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 309*FLEN/8, x4, x1, x2)

inst_104:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f22f1 and fs2 == 1 and fe2 == 0x2b and fm2 == 0x4de949 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f22f1; op2val:0x95cde949;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:312*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 312*FLEN/8, x4, x1, x2)

inst_105:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x209957 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea09957; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:315*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 315*FLEN/8, x4, x1, x2)

inst_106:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x217fdd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea17fdd; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:318*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 318*FLEN/8, x4, x1, x2)

inst_107:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x237008 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea37008; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:321*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 321*FLEN/8, x4, x1, x2)

inst_108:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x26b8d3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea6b8d3; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:324*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 324*FLEN/8, x4, x1, x2)

inst_109:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x29d93c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea9d93c; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:327*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 327*FLEN/8, x4, x1, x2)

inst_110:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2ae033 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eaae033; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:330*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 330*FLEN/8, x4, x1, x2)

inst_111:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2b03e6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eab03e6; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:333*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 333*FLEN/8, x4, x1, x2)

inst_112:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2c0532 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eac0532; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:336*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 336*FLEN/8, x4, x1, x2)

inst_113:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2d0427 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ead0427; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:339*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 339*FLEN/8, x4, x1, x2)

inst_114:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2df190 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eadf190; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:342*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 342*FLEN/8, x4, x1, x2)

inst_115:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33495f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3495f; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:345*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 345*FLEN/8, x4, x1, x2)

inst_116:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x351aa9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb51aa9; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:348*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 348*FLEN/8, x4, x1, x2)

inst_117:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x354d84 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb54d84; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:351*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 351*FLEN/8, x4, x1, x2)

inst_118:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36fce6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6fce6; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:354*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 354*FLEN/8, x4, x1, x2)

inst_119:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70362; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:357*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 357*FLEN/8, x4, x1, x2)

inst_120:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x372bf7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb72bf7; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:360*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 360*FLEN/8, x4, x1, x2)

inst_121:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3acb68 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ebacb68; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:363*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 363*FLEN/8, x4, x1, x2)

inst_122:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3b1c27 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ebb1c27; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:366*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 366*FLEN/8, x4, x1, x2)

inst_123:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3d88ad and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ebd88ad; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:369*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 369*FLEN/8, x4, x1, x2)

inst_124:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3deb73 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ebdeb73; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:372*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 372*FLEN/8, x4, x1, x2)

inst_125:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x41657b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ec1657b; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:375*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 375*FLEN/8, x4, x1, x2)

inst_126:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x41ccbc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ec1ccbc; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:378*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 378*FLEN/8, x4, x1, x2)

inst_127:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x430c98 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ec30c98; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:381*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 381*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_2)

inst_128:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x434d6c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ec34d6c; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:384*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 384*FLEN/8, x4, x1, x2)

inst_129:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ec45459; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:387*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 387*FLEN/8, x4, x1, x2)

inst_130:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x480329 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ec80329; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:390*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 390*FLEN/8, x4, x1, x2)

inst_131:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4a968c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eca968c; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:393*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 393*FLEN/8, x4, x1, x2)

inst_132:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4ae285 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x7243f7 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ecae285; op2val:0x3ff243f7;
op3val:0xff3fffff; valaddr_reg:x3; val_offset:396*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 396*FLEN/8, x4, x1, x2)

inst_133:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4d21cb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ecd21cb; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:399*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 399*FLEN/8, x4, x1, x2)

inst_134:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4e908c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ece908c; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:402*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 402*FLEN/8, x4, x1, x2)

inst_135:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4f7809 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ecf7809; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:405*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 405*FLEN/8, x4, x1, x2)

inst_136:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4f9722 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ecf9722; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:408*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 408*FLEN/8, x4, x1, x2)

inst_137:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5237a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ed237a1; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:411*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 411*FLEN/8, x4, x1, x2)

inst_138:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x52b355 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ed2b355; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:414*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 414*FLEN/8, x4, x1, x2)

inst_139:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x53afc5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ed3afc5; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:417*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 417*FLEN/8, x4, x1, x2)

inst_140:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x566899 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ed66899; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:420*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 420*FLEN/8, x4, x1, x2)

inst_141:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x57453d and fs2 == 0 and fe2 == 0x2b and fm2 == 0x1837c2 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ed7453d; op2val:0x159837c2;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:423*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 423*FLEN/8, x4, x1, x2)

inst_142:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x579458 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ed79458; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:426*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 426*FLEN/8, x4, x1, x2)

inst_143:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x59ec92 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ed9ec92; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:429*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 429*FLEN/8, x4, x1, x2)

inst_144:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5a2b8e and fs2 == 0 and fe2 == 0x2b and fm2 == 0x1631d8 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eda2b8e; op2val:0x159631d8;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:432*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 432*FLEN/8, x4, x1, x2)

inst_145:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5a8a0e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eda8a0e; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:435*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 435*FLEN/8, x4, x1, x2)

inst_146:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5c5d53 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7edc5d53; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:438*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 438*FLEN/8, x4, x1, x2)

inst_147:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5d0ccb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7edd0ccb; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:441*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 441*FLEN/8, x4, x1, x2)

inst_148:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5d2a79 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7edd2a79; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:444*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 444*FLEN/8, x4, x1, x2)

inst_149:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e9a56 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ede9a56; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:447*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 447*FLEN/8, x4, x1, x2)

inst_150:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6004c9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee004c9; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:450*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 450*FLEN/8, x4, x1, x2)

inst_151:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6174c8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee174c8; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:453*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 453*FLEN/8, x4, x1, x2)

inst_152:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x61a51b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee1a51b; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:456*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 456*FLEN/8, x4, x1, x2)

inst_153:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x627bd0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee27bd0; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:459*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 459*FLEN/8, x4, x1, x2)

inst_154:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x64f961 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee4f961; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:462*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 462*FLEN/8, x4, x1, x2)

inst_155:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x652afa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee52afa; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:465*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 465*FLEN/8, x4, x1, x2)

inst_156:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x679f8e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee79f8e; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:468*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 468*FLEN/8, x4, x1, x2)

inst_157:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68d57d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ee8d57d; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:471*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 471*FLEN/8, x4, x1, x2)

inst_158:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6a94a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eea94a1; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:474*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 474*FLEN/8, x4, x1, x2)

inst_159:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6b4e0d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeb4e0d; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:477*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 477*FLEN/8, x4, x1, x2)

inst_160:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6b4f07 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eeb4f07; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:480*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 480*FLEN/8, x4, x1, x2)

inst_161:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6d7424 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eed7424; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:483*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 483*FLEN/8, x4, x1, x2)

inst_162:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e7e55 and fs2 == 1 and fe2 == 0x2b and fm2 == 0x096551 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eee7e55; op2val:0x95896551;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:486*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 486*FLEN/8, x4, x1, x2)

inst_163:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x71fa00 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef1fa00; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:489*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 489*FLEN/8, x4, x1, x2)

inst_164:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x731b27 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef31b27; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:492*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 492*FLEN/8, x4, x1, x2)

inst_165:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x735bf2 and fs2 == 1 and fe2 == 0x2b and fm2 == 0x06a612 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef35bf2; op2val:0x9586a612;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:495*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 495*FLEN/8, x4, x1, x2)

inst_166:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73d707 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef3d707; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:498*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 498*FLEN/8, x4, x1, x2)

inst_167:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x74c2e8 and fs2 == 0 and fe2 == 0x2b and fm2 == 0x05e099 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef4c2e8; op2val:0x1585e099;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:501*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 501*FLEN/8, x4, x1, x2)

inst_168:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x75d070 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef5d070; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:504*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 504*FLEN/8, x4, x1, x2)

inst_169:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x786b62 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef86b62; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:507*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 507*FLEN/8, x4, x1, x2)

inst_170:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x795162 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x452558 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef95162; op2val:0x3fc52558;
op3val:0xff3fffff; valaddr_reg:x3; val_offset:510*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 510*FLEN/8, x4, x1, x2)

inst_171:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x79e697 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef9e697; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:513*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 513*FLEN/8, x4, x1, x2)

inst_172:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x79eb78 and fs2 == 1 and fe2 == 0x2b and fm2 == 0x031d33 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ef9eb78; op2val:0x95831d33;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:516*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 516*FLEN/8, x4, x1, x2)

inst_173:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7ba8b0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7efba8b0; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:519*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 519*FLEN/8, x4, x1, x2)

inst_174:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7c283d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7efc283d; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:522*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 522*FLEN/8, x4, x1, x2)

inst_175:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7d88c2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7efd88c2; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:525*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 525*FLEN/8, x4, x1, x2)

inst_176:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7e4880 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7efe4880; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:528*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 528*FLEN/8, x4, x1, x2)

inst_177:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x004910 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f004910; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:531*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 531*FLEN/8, x4, x1, x2)

inst_178:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0125a0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0125a0; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:534*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 534*FLEN/8, x4, x1, x2)

inst_179:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x01d4ab and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f01d4ab; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:537*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 537*FLEN/8, x4, x1, x2)

inst_180:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x02465e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f02465e; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:540*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 540*FLEN/8, x4, x1, x2)

inst_181:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x02ac50 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f02ac50; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:543*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 543*FLEN/8, x4, x1, x2)

inst_182:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x02c05a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f02c05a; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:546*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 546*FLEN/8, x4, x1, x2)

inst_183:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x03532d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f03532d; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:549*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 549*FLEN/8, x4, x1, x2)

inst_184:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x05f3e7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f05f3e7; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:552*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 552*FLEN/8, x4, x1, x2)

inst_185:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06a784 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f06a784; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:555*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 555*FLEN/8, x4, x1, x2)

inst_186:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06c054 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f06c054; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:558*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 558*FLEN/8, x4, x1, x2)

inst_187:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x076a16 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f076a16; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:561*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 561*FLEN/8, x4, x1, x2)

inst_188:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x07a8e7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f07a8e7; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:564*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 564*FLEN/8, x4, x1, x2)

inst_189:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x08c5cd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f08c5cd; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:567*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 567*FLEN/8, x4, x1, x2)

inst_190:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x09661e and fs2 == 1 and fe2 == 0x2a and fm2 == 0x6e7cf1 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f09661e; op2val:0x956e7cf1;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:570*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 570*FLEN/8, x4, x1, x2)

inst_191:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x09b9ea and fs2 == 0 and fe2 == 0x7f and fm2 == 0x3270e2 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f09b9ea; op2val:0x3fb270e2;
op3val:0xff3fffff; valaddr_reg:x3; val_offset:573*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 573*FLEN/8, x4, x1, x2)

inst_192:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0a2eec and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0a2eec; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:576*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 576*FLEN/8, x4, x1, x2)

inst_193:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0b4e72 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0b4e72; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:579*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 579*FLEN/8, x4, x1, x2)

inst_194:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0c20b0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0c20b0; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:582*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 582*FLEN/8, x4, x1, x2)

inst_195:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0c7228 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0c7228; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:585*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 585*FLEN/8, x4, x1, x2)

inst_196:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0c7784 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0c7784; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:588*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 588*FLEN/8, x4, x1, x2)

inst_197:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0e61dc and fs2 == 0 and fe2 == 0x2a and fm2 == 0x662419 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0e61dc; op2val:0x15662419;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:591*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 591*FLEN/8, x4, x1, x2)

inst_198:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fd579 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fd579; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:594*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 594*FLEN/8, x4, x1, x2)

inst_199:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x110d95 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f110d95; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:597*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 597*FLEN/8, x4, x1, x2)

inst_200:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x111d49 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f111d49; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:600*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 600*FLEN/8, x4, x1, x2)

inst_201:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1175bf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1175bf; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:603*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 603*FLEN/8, x4, x1, x2)

inst_202:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1186f9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1186f9; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:606*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 606*FLEN/8, x4, x1, x2)

inst_203:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x167d44 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f167d44; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:609*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 609*FLEN/8, x4, x1, x2)

inst_204:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x179b8e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f179b8e; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:612*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 612*FLEN/8, x4, x1, x2)

inst_205:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x18212b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f18212b; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:615*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 615*FLEN/8, x4, x1, x2)

inst_206:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x185183 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f185183; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:618*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 618*FLEN/8, x4, x1, x2)

inst_207:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x188f57 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f188f57; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:621*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 621*FLEN/8, x4, x1, x2)

inst_208:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x19be4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f19be4b; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:624*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 624*FLEN/8, x4, x1, x2)

inst_209:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1a35e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1a35e0; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:627*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 627*FLEN/8, x4, x1, x2)

inst_210:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1a90b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1a90b9; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:630*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 630*FLEN/8, x4, x1, x2)

inst_211:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1b5638 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1b5638; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:633*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 633*FLEN/8, x4, x1, x2)

inst_212:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1b8fcb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1b8fcb; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:636*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 636*FLEN/8, x4, x1, x2)

inst_213:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1bd52c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1bd52c; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:639*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 639*FLEN/8, x4, x1, x2)

inst_214:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1bfbd1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1bfbd1; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:642*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 642*FLEN/8, x4, x1, x2)

inst_215:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1c60ac and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1c60ac; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:645*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 645*FLEN/8, x4, x1, x2)

inst_216:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1ca7c2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1ca7c2; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:648*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 648*FLEN/8, x4, x1, x2)

inst_217:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1df6e4 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x1b944e and fs3 == 1 and fe3 == 0xfe and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1df6e4; op2val:0x3f9b944e;
op3val:0xff3fffff; valaddr_reg:x3; val_offset:651*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 651*FLEN/8, x4, x1, x2)

inst_218:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1e5ec7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1e5ec7; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:654*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 654*FLEN/8, x4, x1, x2)

inst_219:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20d4b8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20d4b8; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:657*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 657*FLEN/8, x4, x1, x2)

inst_220:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x20f56c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f20f56c; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:660*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 660*FLEN/8, x4, x1, x2)

inst_221:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21c09a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f21c09a; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:663*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 663*FLEN/8, x4, x1, x2)

inst_222:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f222105; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:666*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 666*FLEN/8, x4, x1, x2)

inst_223:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x224140 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f224140; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:669*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 669*FLEN/8, x4, x1, x2)

inst_224:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x22524e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f22524e; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:672*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 672*FLEN/8, x4, x1, x2)

inst_225:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2319ee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2319ee; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:675*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 675*FLEN/8, x4, x1, x2)

inst_226:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x23f4c3 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x15e4cd and fs3 == 1 and fe3 == 0xfe and fm3 == 0x3ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f23f4c3; op2val:0x3f95e4cd;
op3val:0xff3ffffe; valaddr_reg:x3; val_offset:678*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 678*FLEN/8, x4, x1, x2)

inst_227:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x25618f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f25618f; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:681*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 681*FLEN/8, x4, x1, x2)

inst_228:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2623b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2623b6; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:684*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 684*FLEN/8, x4, x1, x2)

inst_229:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x269468 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f269468; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:687*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 687*FLEN/8, x4, x1, x2)

inst_230:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x272166 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f272166; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:690*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 690*FLEN/8, x4, x1, x2)

inst_231:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2765d9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2765d9; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:693*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 693*FLEN/8, x4, x1, x2)

inst_232:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x27bdd4 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x1282d8 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f27bdd4; op2val:0x3f9282d8;
op3val:0xff3fffff; valaddr_reg:x3; val_offset:696*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 696*FLEN/8, x4, x1, x2)

inst_233:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2800cd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2800cd; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:699*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 699*FLEN/8, x4, x1, x2)

inst_234:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2814cf and fs2 == 0 and fe2 == 0x2a and fm2 == 0x42f40b and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2814cf; op2val:0x1542f40b;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:702*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 702*FLEN/8, x4, x1, x2)

inst_235:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x285703 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f285703; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:705*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 705*FLEN/8, x4, x1, x2)

inst_236:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x29b43a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f29b43a; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:708*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 708*FLEN/8, x4, x1, x2)

inst_237:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2bd8f4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2bd8f4; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:711*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 711*FLEN/8, x4, x1, x2)

inst_238:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2c7300 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2c7300; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:714*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 714*FLEN/8, x4, x1, x2)

inst_239:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2c93b2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2c93b2; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:717*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 717*FLEN/8, x4, x1, x2)

inst_240:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2d3742 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2d3742; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:720*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 720*FLEN/8, x4, x1, x2)

inst_241:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2d5201 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2d5201; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:723*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 723*FLEN/8, x4, x1, x2)

inst_242:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2e5b90 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2e5b90; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:726*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 726*FLEN/8, x4, x1, x2)

inst_243:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2eabd8; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:729*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 729*FLEN/8, x4, x1, x2)

inst_244:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eb100 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2eb100; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:732*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 732*FLEN/8, x4, x1, x2)

inst_245:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eb91a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2eb91a; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:735*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 735*FLEN/8, x4, x1, x2)

inst_246:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2f4c51 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f2f4c51; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:738*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 738*FLEN/8, x4, x1, x2)

inst_247:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x300d7e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f300d7e; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:741*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 741*FLEN/8, x4, x1, x2)

inst_248:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x30593a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f30593a; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:744*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 744*FLEN/8, x4, x1, x2)

inst_249:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x313b58 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f313b58; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:747*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 747*FLEN/8, x4, x1, x2)

inst_250:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x314a05 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f314a05; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:750*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 750*FLEN/8, x4, x1, x2)

inst_251:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x331aa5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f331aa5; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:753*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 753*FLEN/8, x4, x1, x2)

inst_252:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x33e5e8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f33e5e8; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:756*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 756*FLEN/8, x4, x1, x2)

inst_253:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x342e24 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f342e24; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:759*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 759*FLEN/8, x4, x1, x2)

inst_254:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x35ba7d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f35ba7d; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:762*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 762*FLEN/8, x4, x1, x2)

inst_255:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x35ce50 and fs2 == 1 and fe2 == 0x2a and fm2 == 0x343c75 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f35ce50; op2val:0x95343c75;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:765*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 765*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_3)

inst_256:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x365ad7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f365ad7; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:768*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 768*FLEN/8, x4, x1, x2)

inst_257:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x370036 and fs2 == 1 and fe2 == 0x2a and fm2 == 0x330f2e and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f370036; op2val:0x95330f2e;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:771*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 771*FLEN/8, x4, x1, x2)

inst_258:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x38849b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f38849b; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:774*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 774*FLEN/8, x4, x1, x2)

inst_259:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x390e97 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f390e97; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:777*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 777*FLEN/8, x4, x1, x2)

inst_260:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3993cf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3993cf; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:780*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 780*FLEN/8, x4, x1, x2)

inst_261:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3996a2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3996a2; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:783*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 783*FLEN/8, x4, x1, x2)

inst_262:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x39c489 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f39c489; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:786*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 786*FLEN/8, x4, x1, x2)

inst_263:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3bdff9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x02cf78 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x3ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3bdff9; op2val:0x3f82cf78;
op3val:0xff3ffffe; valaddr_reg:x3; val_offset:789*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 789*FLEN/8, x4, x1, x2)

inst_264:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c425a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c425a; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:792*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 792*FLEN/8, x4, x1, x2)

inst_265:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3cb1de and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3cb1de; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:795*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 795*FLEN/8, x4, x1, x2)

inst_266:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d783f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3d783f; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:798*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 798*FLEN/8, x4, x1, x2)

inst_267:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3dbdbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3dbdbb; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:801*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 801*FLEN/8, x4, x1, x2)

inst_268:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3f4810 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3f4810; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:804*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 804*FLEN/8, x4, x1, x2)

inst_269:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3fe381 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3fe381; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:807*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 807*FLEN/8, x4, x1, x2)

inst_270:
// fs1 == 0 and fe1 == 0xf4 and fm1 == 0x60affa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a60affa; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:810*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 810*FLEN/8, x4, x1, x2)

inst_271:
// fs1 == 0 and fe1 == 0xf5 and fm1 == 0x15d64c and fs2 == 1 and fe2 == 0x33 and fm2 == 0x5ab0da and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a95d64c; op2val:0x99dab0da;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:813*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 813*FLEN/8, x4, x1, x2)

inst_272:
// fs1 == 0 and fe1 == 0xf5 and fm1 == 0x67c20e and fs2 == 0 and fe2 == 0x87 and fm2 == 0x54154f and fs3 == 1 and fe3 == 0xfe and fm3 == 0x3ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ae7c20e; op2val:0x43d4154f;
op3val:0xff3ffffe; valaddr_reg:x3; val_offset:816*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 816*FLEN/8, x4, x1, x2)

inst_273:
// fs1 == 0 and fe1 == 0xf8 and fm1 == 0x18d146 and fs2 == 0 and fe2 == 0x30 and fm2 == 0x566cfd and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c18d146; op2val:0x18566cfd;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:819*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 819*FLEN/8, x4, x1, x2)

inst_274:
// fs1 == 0 and fe1 == 0xf8 and fm1 == 0x2c8b5e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c2c8b5e; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:822*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 822*FLEN/8, x4, x1, x2)

inst_275:
// fs1 == 0 and fe1 == 0xf8 and fm1 == 0x643dc7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c643dc7; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:825*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 825*FLEN/8, x4, x1, x2)

inst_276:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x04ef49 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c84ef49; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:828*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 828*FLEN/8, x4, x1, x2)

inst_277:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x0bf9e4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7c8bf9e4; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:831*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 831*FLEN/8, x4, x1, x2)

inst_278:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x24066c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ca4066c; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:834*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 834*FLEN/8, x4, x1, x2)

inst_279:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x5f97b9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7cdf97b9; op2val:0x80000000;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:837*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 837*FLEN/8, x4, x1, x2)

inst_280:
// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x71f159 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7cf1f159; op2val:0x0;
op3val:0x71bffff8; valaddr_reg:x3; val_offset:840*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 840*FLEN/8, x4, x1, x2)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0x7a60affa053156858,32,FLEN)
NAN_BOXED(0x80000000147483648,32,FLEN)
NAN_BOXED(0x71bffff8908408312,32,FLEN)
NAN_BOXED(0x7a95d64c056640076,32,FLEN)
NAN_BOXED(0x7a95d64c056640076,32,FLEN)
NAN_BOXED(0x7a95d64c056640076,32,FLEN)
NAN_BOXED(0x7ae7c20e062008846,32,FLEN)
NAN_BOXED(0x7ae7c20e062008846,32,FLEN)
NAN_BOXED(0xff3ffffe282384382,32,FLEN)
NAN_BOXED(0x7bdaa799077927321,32,FLEN)
NAN_BOXED(0x80000000147483648,32,FLEN)
NAN_BOXED(0x71bffff8908408312,32,FLEN)
NAN_BOXED(0x7c18d146082001222,32,FLEN)
NAN_BOXED(0x7c18d146082001222,32,FLEN)
NAN_BOXED(0x7c18d146082001222,32,FLEN)
NAN_BOXED(0x7c2c8b5e083294046,32,FLEN)
NAN_BOXED(0x80000000147483648,32,FLEN)
NAN_BOXED(0x71bffff8908408312,32,FLEN)
NAN_BOXED(0x7c643dc7086944199,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7c84ef49089086793,32,FLEN)
NAN_BOXED(0x7c84ef49089086793,32,FLEN)
NAN_BOXED(0x71bffff8908408312,32,FLEN)
NAN_BOXED(0x7c8bf9e4089548260,32,FLEN)
NAN_BOXED(0x80000000147483648,32,FLEN)
NAN_BOXED(0x80000000147483648,32,FLEN)
NAN_BOXED(0x7ca4066c091124332,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ca4066c091124332,32,FLEN)
NAN_BOXED(0x7cdf97b9095028153,32,FLEN)
NAN_BOXED(0x80000000147483648,32,FLEN)
NAN_BOXED(0x7cdf97b9095028153,32,FLEN)
NAN_BOXED(0x7cf1f159096230745,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x71bffff8908408312,32,FLEN)
NAN_BOXED(0x7cf9d5cb096747979,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x71bffff8908408312,32,FLEN)
NAN_BOXED(0x7d0109b4097220020,32,FLEN)
NAN_BOXED(0x80000000147483648,32,FLEN)
NAN_BOXED(0x71bffff8908408312,32,FLEN)
NAN_BOXED(0x7d0af584097870212,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x71bffff8908408312,32,FLEN)
NAN_BOXED(0x7d0c612e097963310,32,FLEN)
NAN_BOXED(0x17696c9792785047,32,FLEN)
NAN_BOXED(0x71bffff8908408312,32,FLEN)
NAN_BOXED(0x7d0fb50a098181386,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x71bffff8908408312,32,FLEN)
NAN_BOXED(0x7d32551e100450590,32,FLEN)
NAN_BOXED(0x80000000147483648,32,FLEN)
NAN_BOXED(0x71bffff8908408312,32,FLEN)
NAN_BOXED(0x7d772129104959273,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x71bffff8908408312,32,FLEN)
NAN_BOXED(0x7d79e4a2105140386,32,FLEN)
NAN_BOXED(0x4144b12c095020844,32,FLEN)
NAN_BOXED(0xff3ffffe282384382,32,FLEN)
NAN_BOXED(0x7d7d0cc0105347264,32,FLEN)
NAN_BOXED(0x80000000147483648,32,FLEN)
NAN_BOXED(0x71bffff8908408312,32,FLEN)
NAN_BOXED(0x7d803494105554068,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x71bffff8908408312,32,FLEN)
NAN_BOXED(0x7d89f85f106194015,32,FLEN)
NAN_BOXED(0x80000000147483648,32,FLEN)
NAN_BOXED(0x71bffff8908408312,32,FLEN)
NAN_BOXED(0x7d96325d106995293,32,FLEN)
NAN_BOXED(0x4123a019092853785,32,FLEN)
NAN_BOXED(0xff3fffff282384383,32,FLEN)
NAN_BOXED(0x7d99e0a5107236517,32,FLEN)
NAN_BOXED(0x411fb61f092597279,32,FLEN)
NAN_BOXED(0xff3fffff282384383,32,FLEN)
NAN_BOXED(0x7d9a887c107279484,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x71bffff8908408312,32,FLEN)
NAN_BOXED(0x7d9aad53107288915,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x71bffff8908408312,32,FLEN)
NAN_BOXED(0x7d9b03d8107311064,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x71bffff8908408312,32,FLEN)
NAN_BOXED(0x7d9be782107369346,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x71bffff8908408312,32,FLEN)
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NAN_BOXED(0x7f3bdff9134630393,32,FLEN)
NAN_BOXED(0x3f82cf78065537400,32,FLEN)
NAN_BOXED(0xff3ffffe282384382,32,FLEN)
NAN_BOXED(0x7f3c425a134655578,32,FLEN)
NAN_BOXED(0x80000000147483648,32,FLEN)
NAN_BOXED(0x71bffff8908408312,32,FLEN)
NAN_BOXED(0x7f3cb1de134684126,32,FLEN)
NAN_BOXED(0x80000000147483648,32,FLEN)
NAN_BOXED(0x71bffff8908408312,32,FLEN)
NAN_BOXED(0x7f3d783f134734911,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x71bffff8908408312,32,FLEN)
NAN_BOXED(0x7f3dbdbb134752699,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x71bffff8908408312,32,FLEN)
NAN_BOXED(0x7f3f4810134853648,32,FLEN)
NAN_BOXED(0x80000000147483648,32,FLEN)
NAN_BOXED(0x71bffff8908408312,32,FLEN)
NAN_BOXED(0x7f3fe381134893441,32,FLEN)
NAN_BOXED(0x80000000147483648,32,FLEN)
NAN_BOXED(0x71bffff8908408312,32,FLEN)
NAN_BOXED(0x7a60affa053156858,32,FLEN)
NAN_BOXED(0x80000000147483648,32,FLEN)
NAN_BOXED(0x71bffff8908408312,32,FLEN)
NAN_BOXED(0x7a95d64c056640076,32,FLEN)
NAN_BOXED(0x99dab0da581246170,32,FLEN)
NAN_BOXED(0x71bffff8908408312,32,FLEN)
NAN_BOXED(0x7ae7c20e062008846,32,FLEN)
NAN_BOXED(0x43d4154f137972559,32,FLEN)
NAN_BOXED(0xff3ffffe282384382,32,FLEN)
NAN_BOXED(0x7c18d146082001222,32,FLEN)
NAN_BOXED(0x18566cfd08317181,32,FLEN)
NAN_BOXED(0x71bffff8908408312,32,FLEN)
NAN_BOXED(0x7c2c8b5e083294046,32,FLEN)
NAN_BOXED(0x80000000147483648,32,FLEN)
NAN_BOXED(0x71bffff8908408312,32,FLEN)
NAN_BOXED(0x7c643dc7086944199,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x71bffff8908408312,32,FLEN)
NAN_BOXED(0x7c84ef49089086793,32,FLEN)
NAN_BOXED(0x80000000147483648,32,FLEN)
NAN_BOXED(0x71bffff8908408312,32,FLEN)
NAN_BOXED(0x7c8bf9e4089548260,32,FLEN)
NAN_BOXED(0x80000000147483648,32,FLEN)
NAN_BOXED(0x71bffff8908408312,32,FLEN)
NAN_BOXED(0x7ca4066c091124332,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x71bffff8908408312,32,FLEN)
NAN_BOXED(0x7cdf97b9095028153,32,FLEN)
NAN_BOXED(0x80000000147483648,32,FLEN)
NAN_BOXED(0x71bffff8908408312,32,FLEN)
NAN_BOXED(0x7cf1f159096230745,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x71bffff8908408312,32,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;


signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_2:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_3:
    .fill 50*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine

tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
    .fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;

#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif

sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
