
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.10.0
// timestamp : Fri Jul 14 06:20:22 2023 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/eman/riscof/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/eman/riscof/riscv-ctg/sample_cgfs/rv32e_priv.cgf \
 \
//                  -- xlen 32  \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the bltu instruction of the RISC-V RV32 extension for the misalign-bltu covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32E_Zicsr")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",misalign-bltu)

RVTEST_CASE(1,"//check ISA:=regex(.*E.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True ;def RVTEST_E = True;def TEST_CASE_1=True;",misalign-bltu)

RVTEST_SIGBASE(x1,signature_x1_1)

inst_0:
//  rs1_val<rs2_val and ea_align == 2, 
// opcode: bltu, op1:x10; op2:x11; op1val:0x10000; op2val:0x66666667; immval:0x4; align:2
TEST_BRANCH_OP(bltu, x2, x10, x11, 0x10000, 0x66666667, 0x4, 1b, x1, 0*XLEN/8,2)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;


signature_x1_0:
    .fill 0*((XLEN/8)/4),4,0xdeadbeef


signature_x1_1:
    .fill 1*((XLEN/8)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
mtrap_sigptr:
    .fill 64*XLEN/32,4,0xdeadbeef
tsig_end_canary:
CANARY;
#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
