
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.12.2
// timestamp : Wed Sep 25 06:03:37 2024 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fnmadd.cgf \
 \
//                  -- xlen 32  \
//                  --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fnmadd.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fnmadd_b18 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fnmadd_b18)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x14,test_dataset_0)
RVTEST_SIGBASE(x2,signature_x2_1)

inst_0:
// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x26, rs2==x7, rs3==x26, rd==x23,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x26; op2:x7; op3:x26; dest:x23; op1val:0x704c; op2val:0x8000;
op3val:0x704c; valaddr_reg:x14; val_offset:0*FLEN/8; rmval:dyn;
testreg:x11; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x23, x26, x7, x26, dyn, 0, 0, x14, 0*FLEN/8, x16, x2, x11)

inst_1:
// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x1, rs2==x15, rs3==x15, rd==x12,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x1; op2:x15; op3:x15; dest:x12; op1val:0x7ac6; op2val:0x8000;
op3val:0x8000; valaddr_reg:x14; val_offset:3*FLEN/8; rmval:dyn;
testreg:x11; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x12, x1, x15, x15, dyn, 0, 0, x14, 3*FLEN/8, x16, x2, x11)

inst_2:
// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x9, rs2==x26, rs3==x12, rd==x21,fs1 == 0 and fe1 == 0x1e and fm1 == 0x21b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x9; op2:x26; op3:x12; dest:x21; op1val:0x7a1b; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x14; val_offset:6*FLEN/8; rmval:dyn;
testreg:x11; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x21, x9, x26, x12, dyn, 0, 0, x14, 6*FLEN/8, x16, x2, x11)

inst_3:
// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x13, rs2==x3, rs3==x27, rd==x3,fs1 == 0 and fe1 == 0x1d and fm1 == 0x014 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x13; op2:x3; op3:x27; dest:x3; op1val:0x7414; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x14; val_offset:9*FLEN/8; rmval:dyn;
testreg:x11; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x3, x13, x3, x27, dyn, 0, 0, x14, 9*FLEN/8, x16, x2, x11)

inst_4:
// rs1 == rd == rs3 != rs2, rs1==x6, rs2==x8, rs3==x6, rd==x6,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x6; op2:x8; op3:x6; dest:x6; op1val:0x77ec; op2val:0x8000;
op3val:0x77ec; valaddr_reg:x14; val_offset:12*FLEN/8; rmval:dyn;
testreg:x11; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x6, x6, x8, x6, dyn, 0, 0, x14, 12*FLEN/8, x16, x2, x11)

inst_5:
// rs1 == rs2 == rs3 != rd, rs1==x10, rs2==x10, rs3==x10, rd==x24,fs1 == 0 and fe1 == 0x1d and fm1 == 0x330 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x10; op2:x10; op3:x10; dest:x24; op1val:0x7730; op2val:0x7730;
op3val:0x7730; valaddr_reg:x14; val_offset:15*FLEN/8; rmval:dyn;
testreg:x11; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x24, x10, x10, x10, dyn, 0, 0, x14, 15*FLEN/8, x16, x2, x11)

inst_6:
// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x4, rs2==x4, rs3==x16, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x4; op2:x4; op3:x16; dest:x19; op1val:0x7935; op2val:0x7935;
op3val:0xfbff; valaddr_reg:x14; val_offset:18*FLEN/8; rmval:dyn;
testreg:x11; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x19, x4, x4, x16, dyn, 0, 0, x14, 18*FLEN/8, x16, x2, x11)

inst_7:
// rd == rs2 == rs3 != rs1, rs1==x8, rs2==x29, rs3==x29, rd==x29,fs1 == 0 and fe1 == 0x1e and fm1 == 0x24e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x8; op2:x29; op3:x29; dest:x29; op1val:0x7a4e; op2val:0x0;
op3val:0x0; valaddr_reg:x14; val_offset:21*FLEN/8; rmval:dyn;
testreg:x11; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x29, x8, x29, x29, dyn, 0, 0, x14, 21*FLEN/8, x16, x2, x11)

inst_8:
// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x22, rs2==x0, rs3==x18, rd==x22,fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x22; op2:x0; op3:x18; dest:x22; op1val:0x6e01; op2val:0x0;
op3val:0xfbff; valaddr_reg:x14; val_offset:24*FLEN/8; rmval:dyn;
testreg:x11; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x22, x22, x0, x18, dyn, 0, 0, x14, 24*FLEN/8, x16, x2, x11)

inst_9:
// rs1 == rs2 == rs3 == rd, rs1==x25, rs2==x25, rs3==x25, rd==x25,fs1 == 0 and fe1 == 0x19 and fm1 == 0x341 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x25; op2:x25; op3:x25; dest:x25; op1val:0x6741; op2val:0x6741;
op3val:0x6741; valaddr_reg:x14; val_offset:27*FLEN/8; rmval:dyn;
testreg:x11; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x25, x25, x25, x25, dyn, 0, 0, x14, 27*FLEN/8, x16, x2, x11)

inst_10:
// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x12, rs2==x6, rs3==x1, rd==x1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x12; op2:x6; op3:x1; dest:x1; op1val:0x7aae; op2val:0x0;
op3val:0xfbff; valaddr_reg:x14; val_offset:30*FLEN/8; rmval:dyn;
testreg:x11; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x1, x12, x6, x1, dyn, 0, 0, x14, 30*FLEN/8, x16, x2, x11)

inst_11:
// rs1 == rs2 == rd != rs3, rs1==x27, rs2==x27, rs3==x31, rd==x27,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2eb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x27; op2:x27; op3:x31; dest:x27; op1val:0x76eb; op2val:0x76eb;
op3val:0xfbff; valaddr_reg:x14; val_offset:33*FLEN/8; rmval:dyn;
testreg:x11; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x27, x27, x27, x31, dyn, 0, 0, x14, 33*FLEN/8, x16, x2, x11)

inst_12:
// rs1==x0, rs2==x20, rs3==x23, rd==x4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x0; op2:x20; op3:x23; dest:x4; op1val:0x0; op2val:0x0;
op3val:0xfbff; valaddr_reg:x14; val_offset:36*FLEN/8; rmval:dyn;
testreg:x11; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x4, x0, x20, x23, dyn, 0, 0, x14, 36*FLEN/8, x16, x2, x11)

inst_13:
// rs1==x5, rs2==x18, rs3==x24, rd==x31,fs1 == 0 and fe1 == 0x16 and fm1 == 0x057 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x5; op2:x18; op3:x24; dest:x31; op1val:0x5857; op2val:0x0;
op3val:0xfbff; valaddr_reg:x14; val_offset:39*FLEN/8; rmval:dyn;
testreg:x11; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x5, x18, x24, dyn, 0, 0, x14, 39*FLEN/8, x16, x2, x11)
RVTEST_VALBASEUPD(x10,test_dataset_1)

inst_14:
// rs1==x28, rs2==x30, rs3==x19, rd==x7,fs1 == 0 and fe1 == 0x1d and fm1 == 0x31f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x28; op2:x30; op3:x19; dest:x7; op1val:0x771f; op2val:0x0;
op3val:0xfbff; valaddr_reg:x10; val_offset:0*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x7, x28, x30, x19, dyn, 0, 0, x10, 0*FLEN/8, x19, x2, x6)
RVTEST_SIGBASE(x4,signature_x4_0)

inst_15:
// rs1==x21, rs2==x13, rs3==x22, rd==x28,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x21; op2:x13; op3:x22; dest:x28; op1val:0x79c5; op2val:0x0;
op3val:0xfbff; valaddr_reg:x10; val_offset:3*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x28, x21, x13, x22, dyn, 0, 0, x10, 3*FLEN/8, x19, x4, x6)

inst_16:
// rs1==x23, rs2==x17, rs3==x9, rd==x15,fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x23; op2:x17; op3:x9; dest:x15; op1val:0x7351; op2val:0x0;
op3val:0xfbff; valaddr_reg:x10; val_offset:6*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x15, x23, x17, x9, dyn, 0, 0, x10, 6*FLEN/8, x19, x4, x6)

inst_17:
// rs1==x2, rs2==x21, rs3==x5, rd==x8,fs1 == 0 and fe1 == 0x1e and fm1 == 0x38e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x2; op2:x21; op3:x5; dest:x8; op1val:0x7b8e; op2val:0x0;
op3val:0xfbff; valaddr_reg:x10; val_offset:9*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x8, x2, x21, x5, dyn, 0, 0, x10, 9*FLEN/8, x19, x4, x6)

inst_18:
// rs1==x20, rs2==x24, rs3==x11, rd==x5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x335 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x20; op2:x24; op3:x11; dest:x5; op1val:0x7b35; op2val:0x0;
op3val:0xfbff; valaddr_reg:x10; val_offset:12*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x5, x20, x24, x11, dyn, 0, 0, x10, 12*FLEN/8, x19, x4, x6)

inst_19:
// rs1==x11, rs2==x5, rs3==x21, rd==x26,fs1 == 0 and fe1 == 0x19 and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x11; op2:x5; op3:x21; dest:x26; op1val:0x67d4; op2val:0x0;
op3val:0xfbff; valaddr_reg:x10; val_offset:15*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x26, x11, x5, x21, dyn, 0, 0, x10, 15*FLEN/8, x19, x4, x6)

inst_20:
// rs1==x15, rs2==x28, rs3==x2, rd==x9,fs1 == 0 and fe1 == 0x19 and fm1 == 0x283 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x15; op2:x28; op3:x2; dest:x9; op1val:0x6683; op2val:0x0;
op3val:0xfbff; valaddr_reg:x10; val_offset:18*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x9, x15, x28, x2, dyn, 0, 0, x10, 18*FLEN/8, x19, x4, x6)

inst_21:
// rs1==x30, rs2==x11, rs3==x13, rd==x0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x054 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x11; op3:x13; dest:x0; op1val:0x7854; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x10; val_offset:21*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x0, x30, x11, x13, dyn, 0, 0, x10, 21*FLEN/8, x19, x4, x6)

inst_22:
// rs1==x7, rs2==x16, rs3==x17, rd==x11,fs1 == 0 and fe1 == 0x1e and fm1 == 0x382 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x7; op2:x16; op3:x17; dest:x11; op1val:0x7b82; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x10; val_offset:24*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x11, x7, x16, x17, dyn, 0, 0, x10, 24*FLEN/8, x19, x4, x6)

inst_23:
// rs1==x3, rs2==x22, rs3==x30, rd==x14,fs1 == 0 and fe1 == 0x1d and fm1 == 0x218 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x3; op2:x22; op3:x30; dest:x14; op1val:0x7618; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x10; val_offset:27*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x14, x3, x22, x30, dyn, 0, 0, x10, 27*FLEN/8, x19, x4, x6)

inst_24:
// rs1==x14, rs2==x1, rs3==x8, rd==x30,fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ed and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x14; op2:x1; op3:x8; dest:x30; op1val:0x72ed; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x10; val_offset:30*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x30, x14, x1, x8, dyn, 0, 0, x10, 30*FLEN/8, x19, x4, x6)

inst_25:
// rs1==x18, rs2==x12, rs3==x0, rd==x20,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x18; op2:x12; op3:x0; dest:x20; op1val:0x76c0; op2val:0x8000;
op3val:0x0; valaddr_reg:x10; val_offset:33*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x20, x18, x12, x0, dyn, 0, 0, x10, 33*FLEN/8, x19, x4, x6)
RVTEST_VALBASEUPD(x5,test_dataset_2)

inst_26:
// rs1==x17, rs2==x9, rs3==x20, rd==x13,fs1 == 0 and fe1 == 0x19 and fm1 == 0x36f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x17; op2:x9; op3:x20; dest:x13; op1val:0x676f; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:0*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x13, x17, x9, x20, dyn, 0, 0, x5, 0*FLEN/8, x7, x4, x6)

inst_27:
// rs1==x31, rs2==x2, rs3==x7, rd==x10,fs1 == 0 and fe1 == 0x1c and fm1 == 0x317 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x31; op2:x2; op3:x7; dest:x10; op1val:0x7317; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:3*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x10, x31, x2, x7, dyn, 0, 0, x5, 3*FLEN/8, x7, x4, x6)
RVTEST_SIGBASE(x1,signature_x1_0)

inst_28:
// rs1==x29, rs2==x31, rs3==x4, rd==x2,fs1 == 0 and fe1 == 0x1d and fm1 == 0x300 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x29; op2:x31; op3:x4; dest:x2; op1val:0x7700; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:6*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x2, x29, x31, x4, dyn, 0, 0, x5, 6*FLEN/8, x7, x1, x3)

inst_29:
// rs1==x19, rs2==x14, rs3==x28, rd==x18,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ed and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x19; op2:x14; op3:x28; dest:x18; op1val:0x77ed; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:9*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x18, x19, x14, x28, dyn, 0, 0, x5, 9*FLEN/8, x7, x1, x3)

inst_30:
// rs1==x24, rs2==x19, rs3==x3, rd==x16,fs1 == 0 and fe1 == 0x1c and fm1 == 0x374 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x24; op2:x19; op3:x3; dest:x16; op1val:0x7374; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:12*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x16, x24, x19, x3, dyn, 0, 0, x5, 12*FLEN/8, x7, x1, x3)

inst_31:
// rs1==x16, rs2==x23, rs3==x14, rd==x17,fs1 == 0 and fe1 == 0x1c and fm1 == 0x362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x16; op2:x23; op3:x14; dest:x17; op1val:0x7362; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:15*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x17, x16, x23, x14, dyn, 0, 0, x5, 15*FLEN/8, x7, x1, x3)

inst_32:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72ff; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:18*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 18*FLEN/8, x7, x1, x3)

inst_33:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x359 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7759; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:21*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 21*FLEN/8, x7, x1, x3)

inst_34:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74a2; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:24*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 24*FLEN/8, x7, x1, x3)

inst_35:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x180 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6580; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:27*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 27*FLEN/8, x7, x1, x3)

inst_36:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab2; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:30*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 30*FLEN/8, x7, x1, x3)

inst_37:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x073 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7873; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:33*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 33*FLEN/8, x7, x1, x3)

inst_38:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x122 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7922; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:36*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 36*FLEN/8, x7, x1, x3)

inst_39:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1f2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71f2; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:39*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 39*FLEN/8, x7, x1, x3)

inst_40:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bef; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:42*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 42*FLEN/8, x7, x1, x3)

inst_41:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ae0; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:45*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 45*FLEN/8, x7, x1, x3)

inst_42:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3bb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6fbb; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:48*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 48*FLEN/8, x7, x1, x3)

inst_43:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x152 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7552; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:51*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 51*FLEN/8, x7, x1, x3)

inst_44:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79c4; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:54*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 54*FLEN/8, x7, x1, x3)

inst_45:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1af and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79af; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:57*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 57*FLEN/8, x7, x1, x3)

inst_46:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b7c; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:60*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 60*FLEN/8, x7, x1, x3)

inst_47:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76c0; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:63*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 63*FLEN/8, x7, x1, x3)

inst_48:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aa3; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:66*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 66*FLEN/8, x7, x1, x3)

inst_49:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x795c; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:69*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 69*FLEN/8, x7, x1, x3)

inst_50:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0da and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74da; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:72*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 72*FLEN/8, x7, x1, x3)

inst_51:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78b2; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:75*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 75*FLEN/8, x7, x1, x3)

inst_52:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b0e; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:78*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 78*FLEN/8, x7, x1, x3)

inst_53:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ac4; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:81*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 81*FLEN/8, x7, x1, x3)

inst_54:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x780a; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:84*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 84*FLEN/8, x7, x1, x3)

inst_55:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78b5; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:87*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 87*FLEN/8, x7, x1, x3)

inst_56:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x06b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x686b; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:90*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 90*FLEN/8, x7, x1, x3)

inst_57:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3c3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73c3; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:93*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 93*FLEN/8, x7, x1, x3)

inst_58:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x260 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a60; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:96*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 96*FLEN/8, x7, x1, x3)

inst_59:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76a0; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:99*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 99*FLEN/8, x7, x1, x3)

inst_60:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x188 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7188; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:102*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 102*FLEN/8, x7, x1, x3)

inst_61:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x063 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7863; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:105*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 105*FLEN/8, x7, x1, x3)

inst_62:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x799f; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:108*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 108*FLEN/8, x7, x1, x3)

inst_63:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x164 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7964; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:111*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 111*FLEN/8, x7, x1, x3)

inst_64:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75fe; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:114*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 114*FLEN/8, x7, x1, x3)

inst_65:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x305 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7705; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:117*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 117*FLEN/8, x7, x1, x3)

inst_66:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x010 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7810; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:120*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 120*FLEN/8, x7, x1, x3)

inst_67:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x239 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a39; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:123*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 123*FLEN/8, x7, x1, x3)

inst_68:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x782a; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:126*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 126*FLEN/8, x7, x1, x3)

inst_69:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x764a; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:129*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 129*FLEN/8, x7, x1, x3)

inst_70:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77d4; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:132*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 132*FLEN/8, x7, x1, x3)

inst_71:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x392 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6792; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:135*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 135*FLEN/8, x7, x1, x3)

inst_72:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x190 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6990; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:138*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 138*FLEN/8, x7, x1, x3)

inst_73:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x799f; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:141*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 141*FLEN/8, x7, x1, x3)

inst_74:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3dc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bdc; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:144*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 144*FLEN/8, x7, x1, x3)

inst_75:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0be and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78be; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:147*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 147*FLEN/8, x7, x1, x3)

inst_76:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x24b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x764b; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:150*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 150*FLEN/8, x7, x1, x3)

inst_77:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x172 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7172; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:153*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 153*FLEN/8, x7, x1, x3)

inst_78:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7804; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:156*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 156*FLEN/8, x7, x1, x3)

inst_79:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3da and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bda; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:159*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 159*FLEN/8, x7, x1, x3)

inst_80:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x229 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a29; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:162*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 162*FLEN/8, x7, x1, x3)

inst_81:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x050 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7850; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:165*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 165*FLEN/8, x7, x1, x3)

inst_82:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ae1; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:168*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 168*FLEN/8, x7, x1, x3)

inst_83:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x36d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x736d; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:171*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 171*FLEN/8, x7, x1, x3)

inst_84:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x781b; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:174*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 174*FLEN/8, x7, x1, x3)

inst_85:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x39d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b9d; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:177*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 177*FLEN/8, x7, x1, x3)

inst_86:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x789e; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:180*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 180*FLEN/8, x7, x1, x3)

inst_87:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x357 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7757; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:183*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 183*FLEN/8, x7, x1, x3)

inst_88:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x04e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x744e; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:186*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 186*FLEN/8, x7, x1, x3)

inst_89:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x061 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7861; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:189*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 189*FLEN/8, x7, x1, x3)

inst_90:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba7; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:192*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 192*FLEN/8, x7, x1, x3)

inst_91:
// fs1 == 0 and fe1 == 0x17 and fm1 == 0x1db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5ddb; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:195*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 195*FLEN/8, x7, x1, x3)

inst_92:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a44; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:198*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 198*FLEN/8, x7, x1, x3)

inst_93:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8f; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:201*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 201*FLEN/8, x7, x1, x3)

inst_94:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x316 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b16; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:204*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 204*FLEN/8, x7, x1, x3)

inst_95:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1eb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79eb; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:207*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 207*FLEN/8, x7, x1, x3)

inst_96:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x278 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a78; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:210*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 210*FLEN/8, x7, x1, x3)

inst_97:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x025 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7825; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:213*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 213*FLEN/8, x7, x1, x3)

inst_98:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x07d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x787d; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:216*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 216*FLEN/8, x7, x1, x3)

inst_99:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76d0; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:219*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 219*FLEN/8, x7, x1, x3)

inst_100:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x32e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6b2e; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:222*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 222*FLEN/8, x7, x1, x3)

inst_101:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7af4; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:225*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 225*FLEN/8, x7, x1, x3)

inst_102:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x788e; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:228*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 228*FLEN/8, x7, x1, x3)

inst_103:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x264 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7264; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:231*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 231*FLEN/8, x7, x1, x3)

inst_104:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x009 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7809; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:234*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 234*FLEN/8, x7, x1, x3)

inst_105:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3c1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77c1; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:237*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 237*FLEN/8, x7, x1, x3)

inst_106:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75b4; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:240*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 240*FLEN/8, x7, x1, x3)

inst_107:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x188 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7588; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:243*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 243*FLEN/8, x7, x1, x3)

inst_108:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x784e; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:246*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 246*FLEN/8, x7, x1, x3)

inst_109:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fc; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:249*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 249*FLEN/8, x7, x1, x3)

inst_110:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78e5; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:252*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 252*FLEN/8, x7, x1, x3)

inst_111:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x353 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7753; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:255*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 255*FLEN/8, x7, x1, x3)

inst_112:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x329 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6729; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:258*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 258*FLEN/8, x7, x1, x3)

inst_113:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x358 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7358; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:261*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 261*FLEN/8, x7, x1, x3)

inst_114:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1ab and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x71ab; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:264*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 264*FLEN/8, x7, x1, x3)

inst_115:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ac and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78ac; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:267*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 267*FLEN/8, x7, x1, x3)

inst_116:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ae2; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:270*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 270*FLEN/8, x7, x1, x3)

inst_117:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x262 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a62; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:273*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 273*FLEN/8, x7, x1, x3)

inst_118:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a5f; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:276*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 276*FLEN/8, x7, x1, x3)

inst_119:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x287 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a87; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:279*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 279*FLEN/8, x7, x1, x3)

inst_120:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x015 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7415; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:282*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 282*FLEN/8, x7, x1, x3)

inst_121:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2bb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7abb; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:285*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 285*FLEN/8, x7, x1, x3)

inst_122:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x161 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7961; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:288*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 288*FLEN/8, x7, x1, x3)

inst_123:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x153 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d53; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:291*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 291*FLEN/8, x7, x1, x3)

inst_124:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x046 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6446; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:294*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 294*FLEN/8, x7, x1, x3)

inst_125:
// fs1 == 0 and fe1 == 0x18 and fm1 == 0x375 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6375; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:297*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 297*FLEN/8, x7, x1, x3)

inst_126:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a0a; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:300*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 300*FLEN/8, x7, x1, x3)

inst_127:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3fb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73fb; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:303*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 303*FLEN/8, x7, x1, x3)

inst_128:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x301 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f01; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:306*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 306*FLEN/8, x7, x1, x3)

inst_129:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78fe; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:309*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 309*FLEN/8, x7, x1, x3)

inst_130:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x182 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7582; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:312*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 312*FLEN/8, x7, x1, x3)

inst_131:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x072 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6c72; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:315*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 315*FLEN/8, x7, x1, x3)

inst_132:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x11b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x711b; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:318*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 318*FLEN/8, x7, x1, x3)

inst_133:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x037 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7837; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:321*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 321*FLEN/8, x7, x1, x3)

inst_134:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x160 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7160; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:324*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 324*FLEN/8, x7, x1, x3)

inst_135:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x05d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x745d; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:327*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 327*FLEN/8, x7, x1, x3)

inst_136:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79b0; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:330*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 330*FLEN/8, x7, x1, x3)

inst_137:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x345 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7745; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:333*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 333*FLEN/8, x7, x1, x3)

inst_138:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x126 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7526; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:336*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 336*FLEN/8, x7, x1, x3)

inst_139:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x393 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7793; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:339*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 339*FLEN/8, x7, x1, x3)

inst_140:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x20d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x660d; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:342*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 342*FLEN/8, x7, x1, x3)

inst_141:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x762e; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:345*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 345*FLEN/8, x7, x1, x3)

inst_142:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76bb; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:348*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 348*FLEN/8, x7, x1, x3)

inst_143:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x203 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7203; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:351*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 351*FLEN/8, x7, x1, x3)

inst_144:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2f5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ef5; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:354*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 354*FLEN/8, x7, x1, x3)

inst_145:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b31; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:357*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 357*FLEN/8, x7, x1, x3)

inst_146:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x014 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7814; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:360*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 360*FLEN/8, x7, x1, x3)

inst_147:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72b0; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:363*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 363*FLEN/8, x7, x1, x3)

inst_148:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78d7; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:366*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 366*FLEN/8, x7, x1, x3)

inst_149:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x288 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a88; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:369*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 369*FLEN/8, x7, x1, x3)

inst_150:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x154 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6554; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:372*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 372*FLEN/8, x7, x1, x3)

inst_151:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x093 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6493; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:375*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 375*FLEN/8, x7, x1, x3)

inst_152:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0af and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x70af; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:378*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 378*FLEN/8, x7, x1, x3)

inst_153:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79bf; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:381*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 381*FLEN/8, x7, x1, x3)

inst_154:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x120 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7120; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:384*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 384*FLEN/8, x7, x1, x3)

inst_155:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a2; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:387*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 387*FLEN/8, x7, x1, x3)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_156:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x16c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x796c; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:390*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 390*FLEN/8, x7, x1, x3)

inst_157:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x785b; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:393*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 393*FLEN/8, x7, x1, x3)

inst_158:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x730e; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:396*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 396*FLEN/8, x7, x1, x3)

inst_159:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3cd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bcd; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:399*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 399*FLEN/8, x7, x1, x3)

inst_160:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x261 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a61; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:402*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 402*FLEN/8, x7, x1, x3)

inst_161:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x021 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7821; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:405*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 405*FLEN/8, x7, x1, x3)

inst_162:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x323 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7323; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:408*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 408*FLEN/8, x7, x1, x3)

inst_163:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x792f; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:411*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 411*FLEN/8, x7, x1, x3)

inst_164:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x250 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7650; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:414*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 414*FLEN/8, x7, x1, x3)

inst_165:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x789a; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:417*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 417*FLEN/8, x7, x1, x3)

inst_166:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x123 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7523; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:420*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 420*FLEN/8, x7, x1, x3)

inst_167:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x10b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x790b; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:423*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 423*FLEN/8, x7, x1, x3)

inst_168:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x385 and fs2 == 1 and fe2 == 0x09 and fm2 == 0x151 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6b85; op2val:0xa551;
op3val:0xfbff; valaddr_reg:x5; val_offset:426*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 426*FLEN/8, x7, x1, x3)

inst_169:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0c6 and fs2 == 1 and fe2 == 0x07 and fm2 == 0x030 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74c6; op2val:0x9c30;
op3val:0xfbff; valaddr_reg:x5; val_offset:429*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 429*FLEN/8, x7, x1, x3)

inst_170:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3bd and fs2 == 1 and fe2 == 0x05 and fm2 == 0x12b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bbd; op2val:0x952b;
op3val:0xfbff; valaddr_reg:x5; val_offset:432*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 432*FLEN/8, x7, x1, x3)

inst_171:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x300 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x1b6 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b00; op2val:0x95b6;
op3val:0xfbff; valaddr_reg:x5; val_offset:435*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 435*FLEN/8, x7, x1, x3)

inst_172:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0e6 and fs2 == 1 and fe2 == 0x07 and fm2 == 0x014 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74e6; op2val:0x9c14;
op3val:0xfbff; valaddr_reg:x5; val_offset:438*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 438*FLEN/8, x7, x1, x3)

inst_173:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2dd and fs2 == 1 and fe2 == 0x05 and fm2 == 0x1d3 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7add; op2val:0x95d3;
op3val:0xfbff; valaddr_reg:x5; val_offset:441*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 441*FLEN/8, x7, x1, x3)

inst_174:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f6 and fs2 == 1 and fe2 == 0x07 and fm2 == 0x007 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74f6; op2val:0x9c07;
op3val:0xfbff; valaddr_reg:x5; val_offset:444*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 444*FLEN/8, x7, x1, x3)

inst_175:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x382 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x153 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b82; op2val:0x1553;
op3val:0xfbff; valaddr_reg:x5; val_offset:447*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 447*FLEN/8, x7, x1, x3)

inst_176:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f2 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x2b9 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f2; op2val:0x16b9;
op3val:0xfbff; valaddr_reg:x5; val_offset:450*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 450*FLEN/8, x7, x1, x3)

inst_177:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2a7 and fs2 == 0 and fe2 == 0x06 and fm2 == 0x202 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76a7; op2val:0x1a02;
op3val:0xfbff; valaddr_reg:x5; val_offset:453*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 453*FLEN/8, x7, x1, x3)

inst_178:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x009 and fs2 == 0 and fe2 == 0x07 and fm2 == 0x0f4 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7409; op2val:0x1cf4;
op3val:0xfbff; valaddr_reg:x5; val_offset:456*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 456*FLEN/8, x7, x1, x3)

inst_179:
// fs1 == 0 and fe1 == 0x18 and fm1 == 0x058 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x099 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6058; op2val:0x3099;
op3val:0xfbff; valaddr_reg:x5; val_offset:459*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 459*FLEN/8, x7, x1, x3)

inst_180:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x306 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x1b1 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b06; op2val:0x15b1;
op3val:0xfbff; valaddr_reg:x5; val_offset:462*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 462*FLEN/8, x7, x1, x3)

inst_181:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x0da and fs2 == 0 and fe2 == 0x0a and fm2 == 0x01f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x68da; op2val:0x281f;
op3val:0xfbff; valaddr_reg:x5; val_offset:465*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 465*FLEN/8, x7, x1, x3)

inst_182:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28d and fs2 == 0 and fe2 == 0x05 and fm2 == 0x21a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a8d; op2val:0x161a;
op3val:0xfbff; valaddr_reg:x5; val_offset:468*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 468*FLEN/8, x7, x1, x3)

inst_183:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b1 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x132 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bb1; op2val:0x1532;
op3val:0xfbff; valaddr_reg:x5; val_offset:471*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 471*FLEN/8, x7, x1, x3)

inst_184:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08f and fs2 == 0 and fe2 == 0x06 and fm2 == 0x062 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x788f; op2val:0x1862;
op3val:0xfbff; valaddr_reg:x5; val_offset:474*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 474*FLEN/8, x7, x1, x3)

inst_185:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x17c and fs2 == 0 and fe2 == 0x07 and fm2 == 0x34a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x717c; op2val:0x1f4a;
op3val:0xfbff; valaddr_reg:x5; val_offset:477*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 477*FLEN/8, x7, x1, x3)

inst_186:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x1c3 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7af0; op2val:0x15c3;
op3val:0xfbff; valaddr_reg:x5; val_offset:480*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 480*FLEN/8, x7, x1, x3)

inst_187:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c9 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x123 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc9; op2val:0x1523;
op3val:0xfbff; valaddr_reg:x5; val_offset:483*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 483*FLEN/8, x7, x1, x3)

inst_188:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a1 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x31a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79a1; op2val:0x171a;
op3val:0xfbff; valaddr_reg:x5; val_offset:486*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 486*FLEN/8, x7, x1, x3)

inst_189:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x011 and fs2 == 1 and fe2 == 0x06 and fm2 == 0x0ea and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7811; op2val:0x98ea;
op3val:0xfbff; valaddr_reg:x5; val_offset:489*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 489*FLEN/8, x7, x1, x3)

inst_190:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20b and fs2 == 1 and fe2 == 0x06 and fm2 == 0x29e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x760b; op2val:0x9a9e;
op3val:0xfbff; valaddr_reg:x5; val_offset:492*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 492*FLEN/8, x7, x1, x3)

inst_191:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x18c and fs2 == 1 and fe2 == 0x06 and fm2 == 0x335 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x758c; op2val:0x9b35;
op3val:0xfbff; valaddr_reg:x5; val_offset:495*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 495*FLEN/8, x7, x1, x3)

inst_192:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x294 and fs2 == 1 and fe2 == 0x07 and fm2 == 0x213 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7294; op2val:0x9e13;
op3val:0xfbff; valaddr_reg:x5; val_offset:498*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 498*FLEN/8, x7, x1, x3)

inst_193:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x164 and fs2 == 1 and fe2 == 0x05 and fm2 == 0x36b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7964; op2val:0x976b;
op3val:0xfbff; valaddr_reg:x5; val_offset:501*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 501*FLEN/8, x7, x1, x3)

inst_194:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ec and fs2 == 1 and fe2 == 0x06 and fm2 == 0x1c6 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76ec; op2val:0x99c6;
op3val:0xfbff; valaddr_reg:x5; val_offset:504*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 504*FLEN/8, x7, x1, x3)

inst_195:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x235 and fs2 == 1 and fe2 == 0x07 and fm2 == 0x271 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7235; op2val:0x9e71;
op3val:0xfbff; valaddr_reg:x5; val_offset:507*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 507*FLEN/8, x7, x1, x3)

inst_196:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2ae and fs2 == 1 and fe2 == 0x00 and fm2 == 0x072 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6eae; op2val:0x8072;
op3val:0xfbff; valaddr_reg:x5; val_offset:510*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 510*FLEN/8, x7, x1, x3)

inst_197:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x153 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x012 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7953; op2val:0x8012;
op3val:0xfbff; valaddr_reg:x5; val_offset:513*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 513*FLEN/8, x7, x1, x3)

inst_198:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0bc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x028 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74bc; op2val:0x8028;
op3val:0xfbff; valaddr_reg:x5; val_offset:516*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 516*FLEN/8, x7, x1, x3)

inst_199:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x018 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77fe; op2val:0x8018;
op3val:0xfbff; valaddr_reg:x5; val_offset:519*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 519*FLEN/8, x7, x1, x3)

inst_200:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x134 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x024 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7534; op2val:0x8024;
op3val:0xfbff; valaddr_reg:x5; val_offset:522*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 522*FLEN/8, x7, x1, x3)

inst_201:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7af8; op2val:0x800d;
op3val:0xfbff; valaddr_reg:x5; val_offset:525*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 525*FLEN/8, x7, x1, x3)

inst_202:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b31; op2val:0x800d;
op3val:0xfbff; valaddr_reg:x5; val_offset:528*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 528*FLEN/8, x7, x1, x3)

inst_203:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x297 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x64a2; op2val:0x297;
op3val:0xfbff; valaddr_reg:x5; val_offset:531*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 531*FLEN/8, x7, x1, x3)

inst_204:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x26c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x726c; op2val:0x3b;
op3val:0xfbff; valaddr_reg:x5; val_offset:534*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 534*FLEN/8, x7, x1, x3)

inst_205:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x13d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x024 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x753d; op2val:0x24;
op3val:0xfbff; valaddr_reg:x5; val_offset:537*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 537*FLEN/8, x7, x1, x3)

inst_206:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be4; op2val:0xc;
op3val:0xfbff; valaddr_reg:x5; val_offset:540*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 540*FLEN/8, x7, x1, x3)

inst_207:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x242 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a42; op2val:0xf;
op3val:0xfbff; valaddr_reg:x5; val_offset:543*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 543*FLEN/8, x7, x1, x3)

inst_208:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x023 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x756c; op2val:0x23;
op3val:0xfbff; valaddr_reg:x5; val_offset:546*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 546*FLEN/8, x7, x1, x3)

inst_209:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2d0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x038 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72d0; op2val:0x38;
op3val:0xfbff; valaddr_reg:x5; val_offset:549*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 549*FLEN/8, x7, x1, x3)

inst_210:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x164 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x011 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7964; op2val:0x11;
op3val:0xfbff; valaddr_reg:x5; val_offset:552*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 552*FLEN/8, x7, x1, x3)

inst_211:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab2; op2val:0xe;
op3val:0xfbff; valaddr_reg:x5; val_offset:555*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 555*FLEN/8, x7, x1, x3)

inst_212:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x374 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b74; op2val:0xc;
op3val:0xfbff; valaddr_reg:x5; val_offset:558*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 558*FLEN/8, x7, x1, x3)

inst_213:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x17f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x022 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x757f; op2val:0x22;
op3val:0xfbff; valaddr_reg:x5; val_offset:561*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 561*FLEN/8, x7, x1, x3)

inst_214:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b0e; op2val:0xd;
op3val:0xfbff; valaddr_reg:x5; val_offset:564*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 564*FLEN/8, x7, x1, x3)

inst_215:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x17e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x011 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x797e; op2val:0x11;
op3val:0xfbff; valaddr_reg:x5; val_offset:567*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 567*FLEN/8, x7, x1, x3)

inst_216:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3bf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x018 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77bf; op2val:0x18;
op3val:0xfbff; valaddr_reg:x5; val_offset:570*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 570*FLEN/8, x7, x1, x3)

inst_217:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be1; op2val:0x800c;
op3val:0xfbff; valaddr_reg:x5; val_offset:573*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 573*FLEN/8, x7, x1, x3)

inst_218:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x381 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x033 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7381; op2val:0x8033;
op3val:0xfbff; valaddr_reg:x5; val_offset:576*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 576*FLEN/8, x7, x1, x3)

inst_219:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1cd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x010 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79cd; op2val:0x8010;
op3val:0xfbff; valaddr_reg:x5; val_offset:579*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 579*FLEN/8, x7, x1, x3)

inst_220:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x16a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x08d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d6a; op2val:0x808d;
op3val:0xfbff; valaddr_reg:x5; val_offset:582*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 582*FLEN/8, x7, x1, x3)

inst_221:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x16d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x046 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x716d; op2val:0x8046;
op3val:0xfbff; valaddr_reg:x5; val_offset:585*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 585*FLEN/8, x7, x1, x3)

inst_222:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x348 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b48; op2val:0x800d;
op3val:0xfbff; valaddr_reg:x5; val_offset:588*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 588*FLEN/8, x7, x1, x3)

inst_223:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2cf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x038 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x72cf; op2val:0x8038;
op3val:0xfbff; valaddr_reg:x5; val_offset:591*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 591*FLEN/8, x7, x1, x3)

inst_224:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x211 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x144 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a11; op2val:0xbd44;
op3val:0xfbff; valaddr_reg:x5; val_offset:594*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 594*FLEN/8, x7, x1, x3)

inst_225:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0cc and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2aa and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78cc; op2val:0x3eaa;
op3val:0xfbff; valaddr_reg:x5; val_offset:597*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 597*FLEN/8, x7, x1, x3)

inst_226:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b9 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c1 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ab9; op2val:0xbcc1;
op3val:0xfbff; valaddr_reg:x5; val_offset:600*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 600*FLEN/8, x7, x1, x3)

inst_227:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e3 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x16e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x75e3; op2val:0x416e;
op3val:0xfbff; valaddr_reg:x5; val_offset:603*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 603*FLEN/8, x7, x1, x3)

inst_228:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x171 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e0 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7571; op2val:0xc1e0;
op3val:0xfbff; valaddr_reg:x5; val_offset:606*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 606*FLEN/8, x7, x1, x3)

inst_229:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a8 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2de and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74a8; op2val:0x42de;
op3val:0xfbff; valaddr_reg:x5; val_offset:609*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 609*FLEN/8, x7, x1, x3)

inst_230:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x0f and fm2 == 0x09c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aef; op2val:0xbc9c;
op3val:0xfbff; valaddr_reg:x5; val_offset:612*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 612*FLEN/8, x7, x1, x3)

inst_231:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d4 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x29f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78d4; op2val:0x3e9f;
op3val:0xfbff; valaddr_reg:x5; val_offset:615*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 615*FLEN/8, x7, x1, x3)

inst_232:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x031 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ba1; op2val:0xbc31;
op3val:0xfbff; valaddr_reg:x5; val_offset:618*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 618*FLEN/8, x7, x1, x3)

inst_233:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x318 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x082 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b18; op2val:0x3c82;
op3val:0xfbff; valaddr_reg:x5; val_offset:621*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 621*FLEN/8, x7, x1, x3)

inst_234:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x054 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x363 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7054; op2val:0xc763;
op3val:0xfbff; valaddr_reg:x5; val_offset:624*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 624*FLEN/8, x7, x1, x3)

inst_235:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x068 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x341 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7868; op2val:0x3f41;
op3val:0xfbff; valaddr_reg:x5; val_offset:627*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 627*FLEN/8, x7, x1, x3)

inst_236:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2ab and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0cb and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6eab; op2val:0xc8cb;
op3val:0xfbff; valaddr_reg:x5; val_offset:630*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 630*FLEN/8, x7, x1, x3)

inst_237:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x102 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x262 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6902; op2val:0x4e62;
op3val:0xfbff; valaddr_reg:x5; val_offset:633*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 633*FLEN/8, x7, x1, x3)

inst_238:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0ae and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2d4 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6cae; op2val:0xbed4;
op3val:0xfbff; valaddr_reg:x5; val_offset:636*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 636*FLEN/8, x7, x1, x3)

inst_239:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ed and fs2 == 0 and fe2 == 0x0c and fm2 == 0x09e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7aed; op2val:0x309e;
op3val:0xfbff; valaddr_reg:x5; val_offset:639*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 639*FLEN/8, x7, x1, x3)

inst_240:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x24d and fs2 == 1 and fe2 == 0x0d and fm2 == 0x113 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a4d; op2val:0xb513;
op3val:0xfbff; valaddr_reg:x5; val_offset:642*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 642*FLEN/8, x7, x1, x3)

inst_241:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x29f and fs2 == 0 and fe2 == 0x0d and fm2 == 0x0d3 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a9f; op2val:0x34d3;
op3val:0xfbff; valaddr_reg:x5; val_offset:645*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 645*FLEN/8, x7, x1, x3)

inst_242:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x173 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1dd and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7573; op2val:0xbddd;
op3val:0xfbff; valaddr_reg:x5; val_offset:648*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 648*FLEN/8, x7, x1, x3)

inst_243:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0eb and fs2 == 0 and fe2 == 0x0e and fm2 == 0x280 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x78eb; op2val:0x3a80;
op3val:0xfbff; valaddr_reg:x5; val_offset:651*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 651*FLEN/8, x7, x1, x3)

inst_244:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x240 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x11d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a40; op2val:0xbd1d;
op3val:0xfbff; valaddr_reg:x5; val_offset:654*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 654*FLEN/8, x7, x1, x3)

inst_245:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20b and fs2 == 0 and fe2 == 0x10 and fm2 == 0x14a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x760b; op2val:0x414a;
op3val:0xfbff; valaddr_reg:x5; val_offset:657*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 657*FLEN/8, x7, x1, x3)

inst_246:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x090 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x302 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7890; op2val:0xc302;
op3val:0xfbff; valaddr_reg:x5; val_offset:660*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 660*FLEN/8, x7, x1, x3)

inst_247:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x327 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x078 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7327; op2val:0x4878;
op3val:0xfbff; valaddr_reg:x5; val_offset:663*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 663*FLEN/8, x7, x1, x3)

inst_248:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x13a and fs2 == 1 and fe2 == 0x14 and fm2 == 0x21d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6d3a; op2val:0xd21d;
op3val:0xfbff; valaddr_reg:x5; val_offset:666*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 666*FLEN/8, x7, x1, x3)

inst_249:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x044 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x37f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7444; op2val:0x4b7f;
op3val:0xfbff; valaddr_reg:x5; val_offset:669*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 669*FLEN/8, x7, x1, x3)

inst_250:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x31f and fs2 == 1 and fe2 == 0x12 and fm2 == 0x07d and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b1f; op2val:0xc87d;
op3val:0xfbff; valaddr_reg:x5; val_offset:672*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 672*FLEN/8, x7, x1, x3)

inst_251:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x083 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x316 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7883; op2val:0x4b16;
op3val:0xfbff; valaddr_reg:x5; val_offset:675*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 675*FLEN/8, x7, x1, x3)

inst_252:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x365 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b65; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:678*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 678*FLEN/8, x7, x1, x3)

inst_253:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x352 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7752; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:681*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 681*FLEN/8, x7, x1, x3)

inst_254:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x06e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x746e; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:684*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 684*FLEN/8, x7, x1, x3)

inst_255:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x24b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a4b; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:687*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 687*FLEN/8, x7, x1, x3)

inst_256:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x29e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a9e; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:690*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 690*FLEN/8, x7, x1, x3)

inst_257:
// fs1 == 0 and fe1 == 0x18 and fm1 == 0x258 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6258; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:693*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 693*FLEN/8, x7, x1, x3)

inst_258:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1dd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6ddd; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:696*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 696*FLEN/8, x7, x1, x3)

inst_259:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x35d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f5d; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:699*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 699*FLEN/8, x7, x1, x3)

inst_260:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x313 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b13; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:702*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 702*FLEN/8, x7, x1, x3)

inst_261:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x11f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x691f; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:705*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 705*FLEN/8, x7, x1, x3)

inst_262:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73aa; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:708*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 708*FLEN/8, x7, x1, x3)

inst_263:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7be6; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:711*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 711*FLEN/8, x7, x1, x3)

inst_264:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x364 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6f64; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:714*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 714*FLEN/8, x7, x1, x3)

inst_265:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x15a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x715a; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:717*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 717*FLEN/8, x7, x1, x3)

inst_266:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3b8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x73b8; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:720*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 720*FLEN/8, x7, x1, x3)

inst_267:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x79f2; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:723*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 723*FLEN/8, x7, x1, x3)

inst_268:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x294 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e94; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:726*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 726*FLEN/8, x7, x1, x3)

inst_269:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x348 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b48; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:729*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 729*FLEN/8, x7, x1, x3)

inst_270:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x760c; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:732*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 732*FLEN/8, x7, x1, x3)

inst_271:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bc2; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:735*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 735*FLEN/8, x7, x1, x3)

inst_272:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x345 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7b45; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:738*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 738*FLEN/8, x7, x1, x3)

inst_273:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74b3; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:741*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 741*FLEN/8, x7, x1, x3)

inst_274:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x00d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x740d; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:744*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 744*FLEN/8, x7, x1, x3)

inst_275:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77a0; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:747*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 747*FLEN/8, x7, x1, x3)

inst_276:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x267 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e67; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:750*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 750*FLEN/8, x7, x1, x3)

inst_277:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x136 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7936; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:753*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 753*FLEN/8, x7, x1, x3)

inst_278:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x112 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6912; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:756*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 756*FLEN/8, x7, x1, x3)

inst_279:
// fs1 == 0 and fe1 == 0x18 and fm1 == 0x162 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6162; op2val:0x1;
op3val:0xfbff; valaddr_reg:x5; val_offset:759*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 759*FLEN/8, x7, x1, x3)

inst_280:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7bdb; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:762*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 762*FLEN/8, x7, x1, x3)

inst_281:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ba and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x74ba; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:765*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 765*FLEN/8, x7, x1, x3)

inst_282:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x704c; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:768*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 768*FLEN/8, x7, x1, x3)

inst_283:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ac6; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:771*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 771*FLEN/8, x7, x1, x3)
RVTEST_SIGBASE(x1,signature_x1_2)

inst_284:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x77ec; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:774*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 774*FLEN/8, x7, x1, x3)

inst_285:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x330 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7730; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:777*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 777*FLEN/8, x7, x1, x3)

inst_286:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7935; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:780*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 780*FLEN/8, x7, x1, x3)

inst_287:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x24e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a4e; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:783*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 783*FLEN/8, x7, x1, x3)

inst_288:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6e01; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:786*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 786*FLEN/8, x7, x1, x3)

inst_289:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x341 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x6741; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:789*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 789*FLEN/8, x7, x1, x3)

inst_290:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2eb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76eb; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:792*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 792*FLEN/8, x7, x1, x3)

inst_291:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000 and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7a18; op2val:0x0;
op3val:0xfbff; valaddr_reg:x5; val_offset:795*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 795*FLEN/8, x7, x1, x3)

inst_292:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x054 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7854; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:798*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 798*FLEN/8, x7, x1, x3)

inst_293:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x76c0; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x5; val_offset:801*FLEN/8; rmval:dyn;
testreg:x3; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, x31, x30, x29, x28, dyn, 0, 0, x5, 801*FLEN/8, x7, x1, x3)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(28748,32,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(28748,16,FLEN)
NAN_BOXED(31430,32,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31259,32,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(29716,32,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30700,32,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(30700,16,FLEN)
NAN_BOXED(30512,32,FLEN)
NAN_BOXED(30512,16,FLEN)
NAN_BOXED(30512,16,FLEN)
NAN_BOXED(31029,32,FLEN)
NAN_BOXED(31029,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31310,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(28161,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(26433,32,FLEN)
NAN_BOXED(26433,32,FLEN)
NAN_BOXED(26433,16,FLEN)
NAN_BOXED(31406,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30443,32,FLEN)
NAN_BOXED(30443,32,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(22615,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(64511,16,FLEN)
test_dataset_1:
NAN_BOXED(30495,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31173,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(29521,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31630,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31541,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(26580,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(26243,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30804,32,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31618,32,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30232,32,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(29421,32,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30400,32,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(0,16,FLEN)
test_dataset_2:
NAN_BOXED(26479,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(29463,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30464,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30701,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(29556,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(29538,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(29439,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30553,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(29858,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(25984,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31410,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30835,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31010,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(29170,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31727,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31456,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(28603,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30034,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31172,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31151,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31612,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30400,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31395,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31068,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(29914,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30898,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31502,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31428,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30730,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30901,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(26731,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(29635,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31328,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30368,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(29064,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30819,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31135,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31076,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30206,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30469,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30736,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31289,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30762,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30282,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30676,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(26514,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(27024,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31135,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31708,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30910,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30283,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(29042,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30724,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31706,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31273,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30800,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31457,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(29549,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30747,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31645,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30878,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30551,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(29774,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30817,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31655,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(24027,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31300,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31375,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31510,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31211,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31352,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30757,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30845,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30416,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(27438,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31476,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30862,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(29284,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30729,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30657,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30132,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30088,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30798,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30972,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30949,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30547,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(26409,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(29528,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(29099,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30892,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31458,16,FLEN)
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NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31310,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(28161,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(26433,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30443,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31256,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30804,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30400,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(64511,16,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;



signature_x2_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x2_1:
    .fill 30*((SIGALIGN)/4),4,0xdeadbeef


signature_x4_0:
    .fill 26*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_0:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_2:
    .fill 20*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;

mtrap_sigptr:
    .fill 64*XLEN/32,4,0xdeadbeef

tsig_end_canary:
CANARY;
#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif


sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
