
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.7.1
// timestamp : Fri Jun 17 14:18:09 2022 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /scratch/pawan/work/normalised/RV32F/fnmadd.s.cgf \
 \
//                  -- xlen 32  \
//                  --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fnmadd.s instruction of the RISC-V RV32F_Zicsr,RV32FD_Zicsr,RV64F_Zicsr,RV64FD_Zicsr extension for the fnmadd_b15 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*);def TEST_CASE_1=True;",fnmadd_b15)
RVTEST_CASE(1,"//check ISA:=regex(.*E.*F.*);def TEST_CASE_1=True;",fnmadd_b15)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_36864:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a0e48 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a0e48; op2val:0x0;
op3val:0xb7fe000; valaddr_reg:x3; val_offset:110592*0 + 3*-1*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110592*0 + 3*0*FLEN/8, x4, x1, x2)

inst_36865:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a0e48 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a0e48; op2val:0x0;
op3val:0xb7ff000; valaddr_reg:x3; val_offset:110595*0 + 3*0*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110595*0 + 3*1*FLEN/8, x4, x1, x2)

inst_36866:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a0e48 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a0e48; op2val:0x0;
op3val:0xb7ff800; valaddr_reg:x3; val_offset:110598*0 + 3*1*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110598*0 + 3*2*FLEN/8, x4, x1, x2)

inst_36867:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a0e48 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a0e48; op2val:0x0;
op3val:0xb7ffc00; valaddr_reg:x3; val_offset:110601*0 + 3*2*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110601*0 + 3*3*FLEN/8, x4, x1, x2)

inst_36868:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a0e48 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a0e48; op2val:0x0;
op3val:0xb7ffe00; valaddr_reg:x3; val_offset:110604*0 + 3*3*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110604*0 + 3*4*FLEN/8, x4, x1, x2)

inst_36869:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a0e48 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a0e48; op2val:0x0;
op3val:0xb7fff00; valaddr_reg:x3; val_offset:110607*0 + 3*4*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110607*0 + 3*5*FLEN/8, x4, x1, x2)

inst_36870:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a0e48 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a0e48; op2val:0x0;
op3val:0xb7fff80; valaddr_reg:x3; val_offset:110610*0 + 3*5*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110610*0 + 3*6*FLEN/8, x4, x1, x2)

inst_36871:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a0e48 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a0e48; op2val:0x0;
op3val:0xb7fffc0; valaddr_reg:x3; val_offset:110613*0 + 3*6*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110613*0 + 3*7*FLEN/8, x4, x1, x2)

inst_36872:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a0e48 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a0e48; op2val:0x0;
op3val:0xb7fffe0; valaddr_reg:x3; val_offset:110616*0 + 3*7*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110616*0 + 3*8*FLEN/8, x4, x1, x2)

inst_36873:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a0e48 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a0e48; op2val:0x0;
op3val:0xb7ffff0; valaddr_reg:x3; val_offset:110619*0 + 3*8*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110619*0 + 3*9*FLEN/8, x4, x1, x2)

inst_36874:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a0e48 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a0e48; op2val:0x0;
op3val:0xb7ffff8; valaddr_reg:x3; val_offset:110622*0 + 3*9*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110622*0 + 3*10*FLEN/8, x4, x1, x2)

inst_36875:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a0e48 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a0e48; op2val:0x0;
op3val:0xb7ffffc; valaddr_reg:x3; val_offset:110625*0 + 3*10*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110625*0 + 3*11*FLEN/8, x4, x1, x2)

inst_36876:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a0e48 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a0e48; op2val:0x0;
op3val:0xb7ffffe; valaddr_reg:x3; val_offset:110628*0 + 3*11*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110628*0 + 3*12*FLEN/8, x4, x1, x2)

inst_36877:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a0e48 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a0e48; op2val:0x0;
op3val:0xb7fffff; valaddr_reg:x3; val_offset:110631*0 + 3*12*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110631*0 + 3*13*FLEN/8, x4, x1, x2)

inst_36878:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x1; valaddr_reg:x3; val_offset:110634*0 + 3*13*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110634*0 + 3*14*FLEN/8, x4, x1, x2)

inst_36879:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x3; valaddr_reg:x3; val_offset:110637*0 + 3*14*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110637*0 + 3*15*FLEN/8, x4, x1, x2)

inst_36880:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x7; valaddr_reg:x3; val_offset:110640*0 + 3*15*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110640*0 + 3*16*FLEN/8, x4, x1, x2)

inst_36881:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x199999; valaddr_reg:x3; val_offset:110643*0 + 3*16*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110643*0 + 3*17*FLEN/8, x4, x1, x2)

inst_36882:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x249249; valaddr_reg:x3; val_offset:110646*0 + 3*17*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110646*0 + 3*18*FLEN/8, x4, x1, x2)

inst_36883:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x333333; valaddr_reg:x3; val_offset:110649*0 + 3*18*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110649*0 + 3*19*FLEN/8, x4, x1, x2)

inst_36884:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x36db6d; valaddr_reg:x3; val_offset:110652*0 + 3*19*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110652*0 + 3*20*FLEN/8, x4, x1, x2)

inst_36885:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x3bbbbb; valaddr_reg:x3; val_offset:110655*0 + 3*20*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110655*0 + 3*21*FLEN/8, x4, x1, x2)

inst_36886:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x444444; valaddr_reg:x3; val_offset:110658*0 + 3*21*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110658*0 + 3*22*FLEN/8, x4, x1, x2)

inst_36887:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x4ccccc; valaddr_reg:x3; val_offset:110661*0 + 3*22*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110661*0 + 3*23*FLEN/8, x4, x1, x2)

inst_36888:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x5b6db6; valaddr_reg:x3; val_offset:110664*0 + 3*23*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110664*0 + 3*24*FLEN/8, x4, x1, x2)

inst_36889:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x666666; valaddr_reg:x3; val_offset:110667*0 + 3*24*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110667*0 + 3*25*FLEN/8, x4, x1, x2)

inst_36890:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x6db6db; valaddr_reg:x3; val_offset:110670*0 + 3*25*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110670*0 + 3*26*FLEN/8, x4, x1, x2)

inst_36891:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x7ffff8; valaddr_reg:x3; val_offset:110673*0 + 3*26*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110673*0 + 3*27*FLEN/8, x4, x1, x2)

inst_36892:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x7ffffc; valaddr_reg:x3; val_offset:110676*0 + 3*27*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110676*0 + 3*28*FLEN/8, x4, x1, x2)

inst_36893:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x7ffffe; valaddr_reg:x3; val_offset:110679*0 + 3*28*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110679*0 + 3*29*FLEN/8, x4, x1, x2)

inst_36894:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x7000000; valaddr_reg:x3; val_offset:110682*0 + 3*29*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110682*0 + 3*30*FLEN/8, x4, x1, x2)

inst_36895:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x7000001; valaddr_reg:x3; val_offset:110685*0 + 3*30*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110685*0 + 3*31*FLEN/8, x4, x1, x2)

inst_36896:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x7000003; valaddr_reg:x3; val_offset:110688*0 + 3*31*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110688*0 + 3*32*FLEN/8, x4, x1, x2)

inst_36897:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x7000007; valaddr_reg:x3; val_offset:110691*0 + 3*32*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110691*0 + 3*33*FLEN/8, x4, x1, x2)

inst_36898:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x700000f; valaddr_reg:x3; val_offset:110694*0 + 3*33*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110694*0 + 3*34*FLEN/8, x4, x1, x2)

inst_36899:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x700001f; valaddr_reg:x3; val_offset:110697*0 + 3*34*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110697*0 + 3*35*FLEN/8, x4, x1, x2)

inst_36900:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x700003f; valaddr_reg:x3; val_offset:110700*0 + 3*35*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110700*0 + 3*36*FLEN/8, x4, x1, x2)

inst_36901:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x700007f; valaddr_reg:x3; val_offset:110703*0 + 3*36*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110703*0 + 3*37*FLEN/8, x4, x1, x2)

inst_36902:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x70000ff; valaddr_reg:x3; val_offset:110706*0 + 3*37*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110706*0 + 3*38*FLEN/8, x4, x1, x2)

inst_36903:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x70001ff; valaddr_reg:x3; val_offset:110709*0 + 3*38*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110709*0 + 3*39*FLEN/8, x4, x1, x2)

inst_36904:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x70003ff; valaddr_reg:x3; val_offset:110712*0 + 3*39*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110712*0 + 3*40*FLEN/8, x4, x1, x2)

inst_36905:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x70007ff; valaddr_reg:x3; val_offset:110715*0 + 3*40*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110715*0 + 3*41*FLEN/8, x4, x1, x2)

inst_36906:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x7000fff; valaddr_reg:x3; val_offset:110718*0 + 3*41*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110718*0 + 3*42*FLEN/8, x4, x1, x2)

inst_36907:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x7001fff; valaddr_reg:x3; val_offset:110721*0 + 3*42*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110721*0 + 3*43*FLEN/8, x4, x1, x2)

inst_36908:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x7003fff; valaddr_reg:x3; val_offset:110724*0 + 3*43*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110724*0 + 3*44*FLEN/8, x4, x1, x2)

inst_36909:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x7007fff; valaddr_reg:x3; val_offset:110727*0 + 3*44*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110727*0 + 3*45*FLEN/8, x4, x1, x2)

inst_36910:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x700ffff; valaddr_reg:x3; val_offset:110730*0 + 3*45*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110730*0 + 3*46*FLEN/8, x4, x1, x2)

inst_36911:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x701ffff; valaddr_reg:x3; val_offset:110733*0 + 3*46*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110733*0 + 3*47*FLEN/8, x4, x1, x2)

inst_36912:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x703ffff; valaddr_reg:x3; val_offset:110736*0 + 3*47*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110736*0 + 3*48*FLEN/8, x4, x1, x2)

inst_36913:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x707ffff; valaddr_reg:x3; val_offset:110739*0 + 3*48*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110739*0 + 3*49*FLEN/8, x4, x1, x2)

inst_36914:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x70fffff; valaddr_reg:x3; val_offset:110742*0 + 3*49*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110742*0 + 3*50*FLEN/8, x4, x1, x2)

inst_36915:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x71fffff; valaddr_reg:x3; val_offset:110745*0 + 3*50*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110745*0 + 3*51*FLEN/8, x4, x1, x2)

inst_36916:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x73fffff; valaddr_reg:x3; val_offset:110748*0 + 3*51*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110748*0 + 3*52*FLEN/8, x4, x1, x2)

inst_36917:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x7400000; valaddr_reg:x3; val_offset:110751*0 + 3*52*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110751*0 + 3*53*FLEN/8, x4, x1, x2)

inst_36918:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x7600000; valaddr_reg:x3; val_offset:110754*0 + 3*53*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110754*0 + 3*54*FLEN/8, x4, x1, x2)

inst_36919:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x7700000; valaddr_reg:x3; val_offset:110757*0 + 3*54*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110757*0 + 3*55*FLEN/8, x4, x1, x2)

inst_36920:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x7780000; valaddr_reg:x3; val_offset:110760*0 + 3*55*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110760*0 + 3*56*FLEN/8, x4, x1, x2)

inst_36921:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x77c0000; valaddr_reg:x3; val_offset:110763*0 + 3*56*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110763*0 + 3*57*FLEN/8, x4, x1, x2)

inst_36922:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x77e0000; valaddr_reg:x3; val_offset:110766*0 + 3*57*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110766*0 + 3*58*FLEN/8, x4, x1, x2)

inst_36923:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x77f0000; valaddr_reg:x3; val_offset:110769*0 + 3*58*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110769*0 + 3*59*FLEN/8, x4, x1, x2)

inst_36924:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x77f8000; valaddr_reg:x3; val_offset:110772*0 + 3*59*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110772*0 + 3*60*FLEN/8, x4, x1, x2)

inst_36925:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x77fc000; valaddr_reg:x3; val_offset:110775*0 + 3*60*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110775*0 + 3*61*FLEN/8, x4, x1, x2)

inst_36926:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x77fe000; valaddr_reg:x3; val_offset:110778*0 + 3*61*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110778*0 + 3*62*FLEN/8, x4, x1, x2)

inst_36927:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x77ff000; valaddr_reg:x3; val_offset:110781*0 + 3*62*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110781*0 + 3*63*FLEN/8, x4, x1, x2)

inst_36928:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x77ff800; valaddr_reg:x3; val_offset:110784*0 + 3*63*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110784*0 + 3*64*FLEN/8, x4, x1, x2)

inst_36929:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x77ffc00; valaddr_reg:x3; val_offset:110787*0 + 3*64*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110787*0 + 3*65*FLEN/8, x4, x1, x2)

inst_36930:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x77ffe00; valaddr_reg:x3; val_offset:110790*0 + 3*65*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110790*0 + 3*66*FLEN/8, x4, x1, x2)

inst_36931:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x77fff00; valaddr_reg:x3; val_offset:110793*0 + 3*66*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110793*0 + 3*67*FLEN/8, x4, x1, x2)

inst_36932:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x77fff80; valaddr_reg:x3; val_offset:110796*0 + 3*67*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110796*0 + 3*68*FLEN/8, x4, x1, x2)

inst_36933:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x77fffc0; valaddr_reg:x3; val_offset:110799*0 + 3*68*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110799*0 + 3*69*FLEN/8, x4, x1, x2)

inst_36934:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x77fffe0; valaddr_reg:x3; val_offset:110802*0 + 3*69*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110802*0 + 3*70*FLEN/8, x4, x1, x2)

inst_36935:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x77ffff0; valaddr_reg:x3; val_offset:110805*0 + 3*70*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110805*0 + 3*71*FLEN/8, x4, x1, x2)

inst_36936:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x77ffff8; valaddr_reg:x3; val_offset:110808*0 + 3*71*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110808*0 + 3*72*FLEN/8, x4, x1, x2)

inst_36937:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x77ffffc; valaddr_reg:x3; val_offset:110811*0 + 3*72*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110811*0 + 3*73*FLEN/8, x4, x1, x2)

inst_36938:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x77ffffe; valaddr_reg:x3; val_offset:110814*0 + 3*73*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110814*0 + 3*74*FLEN/8, x4, x1, x2)

inst_36939:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a336f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a336f; op2val:0x0;
op3val:0x77fffff; valaddr_reg:x3; val_offset:110817*0 + 3*74*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110817*0 + 3*75*FLEN/8, x4, x1, x2)

inst_36940:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x1; valaddr_reg:x3; val_offset:110820*0 + 3*75*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110820*0 + 3*76*FLEN/8, x4, x1, x2)

inst_36941:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x3; valaddr_reg:x3; val_offset:110823*0 + 3*76*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110823*0 + 3*77*FLEN/8, x4, x1, x2)

inst_36942:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x7; valaddr_reg:x3; val_offset:110826*0 + 3*77*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110826*0 + 3*78*FLEN/8, x4, x1, x2)

inst_36943:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x199999; valaddr_reg:x3; val_offset:110829*0 + 3*78*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110829*0 + 3*79*FLEN/8, x4, x1, x2)

inst_36944:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x249249; valaddr_reg:x3; val_offset:110832*0 + 3*79*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110832*0 + 3*80*FLEN/8, x4, x1, x2)

inst_36945:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x333333; valaddr_reg:x3; val_offset:110835*0 + 3*80*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110835*0 + 3*81*FLEN/8, x4, x1, x2)

inst_36946:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x36db6d; valaddr_reg:x3; val_offset:110838*0 + 3*81*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110838*0 + 3*82*FLEN/8, x4, x1, x2)

inst_36947:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x3bbbbb; valaddr_reg:x3; val_offset:110841*0 + 3*82*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110841*0 + 3*83*FLEN/8, x4, x1, x2)

inst_36948:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x444444; valaddr_reg:x3; val_offset:110844*0 + 3*83*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110844*0 + 3*84*FLEN/8, x4, x1, x2)

inst_36949:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x4ccccc; valaddr_reg:x3; val_offset:110847*0 + 3*84*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110847*0 + 3*85*FLEN/8, x4, x1, x2)

inst_36950:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x5b6db6; valaddr_reg:x3; val_offset:110850*0 + 3*85*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110850*0 + 3*86*FLEN/8, x4, x1, x2)

inst_36951:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x666666; valaddr_reg:x3; val_offset:110853*0 + 3*86*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110853*0 + 3*87*FLEN/8, x4, x1, x2)

inst_36952:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x6db6db; valaddr_reg:x3; val_offset:110856*0 + 3*87*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110856*0 + 3*88*FLEN/8, x4, x1, x2)

inst_36953:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x7ffff8; valaddr_reg:x3; val_offset:110859*0 + 3*88*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110859*0 + 3*89*FLEN/8, x4, x1, x2)

inst_36954:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x7ffffc; valaddr_reg:x3; val_offset:110862*0 + 3*89*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110862*0 + 3*90*FLEN/8, x4, x1, x2)

inst_36955:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x7ffffe; valaddr_reg:x3; val_offset:110865*0 + 3*90*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110865*0 + 3*91*FLEN/8, x4, x1, x2)

inst_36956:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x6800000; valaddr_reg:x3; val_offset:110868*0 + 3*91*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110868*0 + 3*92*FLEN/8, x4, x1, x2)

inst_36957:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x6800001; valaddr_reg:x3; val_offset:110871*0 + 3*92*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110871*0 + 3*93*FLEN/8, x4, x1, x2)

inst_36958:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x6800003; valaddr_reg:x3; val_offset:110874*0 + 3*93*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110874*0 + 3*94*FLEN/8, x4, x1, x2)

inst_36959:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x6800007; valaddr_reg:x3; val_offset:110877*0 + 3*94*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110877*0 + 3*95*FLEN/8, x4, x1, x2)

inst_36960:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x680000f; valaddr_reg:x3; val_offset:110880*0 + 3*95*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110880*0 + 3*96*FLEN/8, x4, x1, x2)

inst_36961:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x680001f; valaddr_reg:x3; val_offset:110883*0 + 3*96*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110883*0 + 3*97*FLEN/8, x4, x1, x2)

inst_36962:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x680003f; valaddr_reg:x3; val_offset:110886*0 + 3*97*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110886*0 + 3*98*FLEN/8, x4, x1, x2)

inst_36963:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x680007f; valaddr_reg:x3; val_offset:110889*0 + 3*98*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110889*0 + 3*99*FLEN/8, x4, x1, x2)

inst_36964:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x68000ff; valaddr_reg:x3; val_offset:110892*0 + 3*99*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110892*0 + 3*100*FLEN/8, x4, x1, x2)

inst_36965:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x68001ff; valaddr_reg:x3; val_offset:110895*0 + 3*100*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110895*0 + 3*101*FLEN/8, x4, x1, x2)

inst_36966:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x68003ff; valaddr_reg:x3; val_offset:110898*0 + 3*101*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110898*0 + 3*102*FLEN/8, x4, x1, x2)

inst_36967:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x68007ff; valaddr_reg:x3; val_offset:110901*0 + 3*102*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110901*0 + 3*103*FLEN/8, x4, x1, x2)

inst_36968:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x6800fff; valaddr_reg:x3; val_offset:110904*0 + 3*103*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110904*0 + 3*104*FLEN/8, x4, x1, x2)

inst_36969:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x6801fff; valaddr_reg:x3; val_offset:110907*0 + 3*104*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110907*0 + 3*105*FLEN/8, x4, x1, x2)

inst_36970:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x6803fff; valaddr_reg:x3; val_offset:110910*0 + 3*105*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110910*0 + 3*106*FLEN/8, x4, x1, x2)

inst_36971:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x6807fff; valaddr_reg:x3; val_offset:110913*0 + 3*106*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110913*0 + 3*107*FLEN/8, x4, x1, x2)

inst_36972:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x680ffff; valaddr_reg:x3; val_offset:110916*0 + 3*107*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110916*0 + 3*108*FLEN/8, x4, x1, x2)

inst_36973:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x681ffff; valaddr_reg:x3; val_offset:110919*0 + 3*108*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110919*0 + 3*109*FLEN/8, x4, x1, x2)

inst_36974:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x683ffff; valaddr_reg:x3; val_offset:110922*0 + 3*109*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110922*0 + 3*110*FLEN/8, x4, x1, x2)

inst_36975:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x687ffff; valaddr_reg:x3; val_offset:110925*0 + 3*110*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110925*0 + 3*111*FLEN/8, x4, x1, x2)

inst_36976:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x68fffff; valaddr_reg:x3; val_offset:110928*0 + 3*111*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110928*0 + 3*112*FLEN/8, x4, x1, x2)

inst_36977:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x69fffff; valaddr_reg:x3; val_offset:110931*0 + 3*112*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110931*0 + 3*113*FLEN/8, x4, x1, x2)

inst_36978:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x6bfffff; valaddr_reg:x3; val_offset:110934*0 + 3*113*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110934*0 + 3*114*FLEN/8, x4, x1, x2)

inst_36979:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x6c00000; valaddr_reg:x3; val_offset:110937*0 + 3*114*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110937*0 + 3*115*FLEN/8, x4, x1, x2)

inst_36980:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x6e00000; valaddr_reg:x3; val_offset:110940*0 + 3*115*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110940*0 + 3*116*FLEN/8, x4, x1, x2)

inst_36981:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x6f00000; valaddr_reg:x3; val_offset:110943*0 + 3*116*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110943*0 + 3*117*FLEN/8, x4, x1, x2)

inst_36982:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x6f80000; valaddr_reg:x3; val_offset:110946*0 + 3*117*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110946*0 + 3*118*FLEN/8, x4, x1, x2)

inst_36983:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x6fc0000; valaddr_reg:x3; val_offset:110949*0 + 3*118*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110949*0 + 3*119*FLEN/8, x4, x1, x2)

inst_36984:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x6fe0000; valaddr_reg:x3; val_offset:110952*0 + 3*119*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110952*0 + 3*120*FLEN/8, x4, x1, x2)

inst_36985:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x6ff0000; valaddr_reg:x3; val_offset:110955*0 + 3*120*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110955*0 + 3*121*FLEN/8, x4, x1, x2)

inst_36986:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x6ff8000; valaddr_reg:x3; val_offset:110958*0 + 3*121*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110958*0 + 3*122*FLEN/8, x4, x1, x2)

inst_36987:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x6ffc000; valaddr_reg:x3; val_offset:110961*0 + 3*122*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110961*0 + 3*123*FLEN/8, x4, x1, x2)

inst_36988:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x6ffe000; valaddr_reg:x3; val_offset:110964*0 + 3*123*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110964*0 + 3*124*FLEN/8, x4, x1, x2)

inst_36989:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x6fff000; valaddr_reg:x3; val_offset:110967*0 + 3*124*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110967*0 + 3*125*FLEN/8, x4, x1, x2)

inst_36990:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x6fff800; valaddr_reg:x3; val_offset:110970*0 + 3*125*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110970*0 + 3*126*FLEN/8, x4, x1, x2)

inst_36991:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x6fffc00; valaddr_reg:x3; val_offset:110973*0 + 3*126*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110973*0 + 3*127*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_2)

inst_36992:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x6fffe00; valaddr_reg:x3; val_offset:110976*0 + 3*127*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110976*0 + 3*128*FLEN/8, x4, x1, x2)

inst_36993:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x6ffff00; valaddr_reg:x3; val_offset:110979*0 + 3*128*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110979*0 + 3*129*FLEN/8, x4, x1, x2)

inst_36994:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x6ffff80; valaddr_reg:x3; val_offset:110982*0 + 3*129*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110982*0 + 3*130*FLEN/8, x4, x1, x2)

inst_36995:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x6ffffc0; valaddr_reg:x3; val_offset:110985*0 + 3*130*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110985*0 + 3*131*FLEN/8, x4, x1, x2)

inst_36996:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x6ffffe0; valaddr_reg:x3; val_offset:110988*0 + 3*131*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110988*0 + 3*132*FLEN/8, x4, x1, x2)

inst_36997:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x6fffff0; valaddr_reg:x3; val_offset:110991*0 + 3*132*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110991*0 + 3*133*FLEN/8, x4, x1, x2)

inst_36998:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x6fffff8; valaddr_reg:x3; val_offset:110994*0 + 3*133*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110994*0 + 3*134*FLEN/8, x4, x1, x2)

inst_36999:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x6fffffc; valaddr_reg:x3; val_offset:110997*0 + 3*134*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 110997*0 + 3*135*FLEN/8, x4, x1, x2)

inst_37000:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x6fffffe; valaddr_reg:x3; val_offset:111000*0 + 3*135*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111000*0 + 3*136*FLEN/8, x4, x1, x2)

inst_37001:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a3442 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a3442; op2val:0x0;
op3val:0x6ffffff; valaddr_reg:x3; val_offset:111003*0 + 3*136*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111003*0 + 3*137*FLEN/8, x4, x1, x2)

inst_37002:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0x800001; valaddr_reg:x3; val_offset:111006*0 + 3*137*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111006*0 + 3*138*FLEN/8, x4, x1, x2)

inst_37003:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0x800003; valaddr_reg:x3; val_offset:111009*0 + 3*138*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111009*0 + 3*139*FLEN/8, x4, x1, x2)

inst_37004:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0x800007; valaddr_reg:x3; val_offset:111012*0 + 3*139*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111012*0 + 3*140*FLEN/8, x4, x1, x2)

inst_37005:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0x999999; valaddr_reg:x3; val_offset:111015*0 + 3*140*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111015*0 + 3*141*FLEN/8, x4, x1, x2)

inst_37006:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xa49249; valaddr_reg:x3; val_offset:111018*0 + 3*141*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111018*0 + 3*142*FLEN/8, x4, x1, x2)

inst_37007:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xb33333; valaddr_reg:x3; val_offset:111021*0 + 3*142*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111021*0 + 3*143*FLEN/8, x4, x1, x2)

inst_37008:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xb6db6d; valaddr_reg:x3; val_offset:111024*0 + 3*143*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111024*0 + 3*144*FLEN/8, x4, x1, x2)

inst_37009:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xbbbbbb; valaddr_reg:x3; val_offset:111027*0 + 3*144*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111027*0 + 3*145*FLEN/8, x4, x1, x2)

inst_37010:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xc44444; valaddr_reg:x3; val_offset:111030*0 + 3*145*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111030*0 + 3*146*FLEN/8, x4, x1, x2)

inst_37011:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xcccccc; valaddr_reg:x3; val_offset:111033*0 + 3*146*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111033*0 + 3*147*FLEN/8, x4, x1, x2)

inst_37012:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xdb6db6; valaddr_reg:x3; val_offset:111036*0 + 3*147*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111036*0 + 3*148*FLEN/8, x4, x1, x2)

inst_37013:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xe66666; valaddr_reg:x3; val_offset:111039*0 + 3*148*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111039*0 + 3*149*FLEN/8, x4, x1, x2)

inst_37014:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xedb6db; valaddr_reg:x3; val_offset:111042*0 + 3*149*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111042*0 + 3*150*FLEN/8, x4, x1, x2)

inst_37015:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xfffff8; valaddr_reg:x3; val_offset:111045*0 + 3*150*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111045*0 + 3*151*FLEN/8, x4, x1, x2)

inst_37016:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xfffffc; valaddr_reg:x3; val_offset:111048*0 + 3*151*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111048*0 + 3*152*FLEN/8, x4, x1, x2)

inst_37017:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xfffffe; valaddr_reg:x3; val_offset:111051*0 + 3*152*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111051*0 + 3*153*FLEN/8, x4, x1, x2)

inst_37018:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xf000000; valaddr_reg:x3; val_offset:111054*0 + 3*153*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111054*0 + 3*154*FLEN/8, x4, x1, x2)

inst_37019:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xf000001; valaddr_reg:x3; val_offset:111057*0 + 3*154*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111057*0 + 3*155*FLEN/8, x4, x1, x2)

inst_37020:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xf000003; valaddr_reg:x3; val_offset:111060*0 + 3*155*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111060*0 + 3*156*FLEN/8, x4, x1, x2)

inst_37021:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xf000007; valaddr_reg:x3; val_offset:111063*0 + 3*156*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111063*0 + 3*157*FLEN/8, x4, x1, x2)

inst_37022:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xf00000f; valaddr_reg:x3; val_offset:111066*0 + 3*157*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111066*0 + 3*158*FLEN/8, x4, x1, x2)

inst_37023:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xf00001f; valaddr_reg:x3; val_offset:111069*0 + 3*158*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111069*0 + 3*159*FLEN/8, x4, x1, x2)

inst_37024:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xf00003f; valaddr_reg:x3; val_offset:111072*0 + 3*159*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111072*0 + 3*160*FLEN/8, x4, x1, x2)

inst_37025:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xf00007f; valaddr_reg:x3; val_offset:111075*0 + 3*160*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111075*0 + 3*161*FLEN/8, x4, x1, x2)

inst_37026:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xf0000ff; valaddr_reg:x3; val_offset:111078*0 + 3*161*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111078*0 + 3*162*FLEN/8, x4, x1, x2)

inst_37027:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xf0001ff; valaddr_reg:x3; val_offset:111081*0 + 3*162*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111081*0 + 3*163*FLEN/8, x4, x1, x2)

inst_37028:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xf0003ff; valaddr_reg:x3; val_offset:111084*0 + 3*163*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111084*0 + 3*164*FLEN/8, x4, x1, x2)

inst_37029:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xf0007ff; valaddr_reg:x3; val_offset:111087*0 + 3*164*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111087*0 + 3*165*FLEN/8, x4, x1, x2)

inst_37030:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xf000fff; valaddr_reg:x3; val_offset:111090*0 + 3*165*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111090*0 + 3*166*FLEN/8, x4, x1, x2)

inst_37031:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xf001fff; valaddr_reg:x3; val_offset:111093*0 + 3*166*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111093*0 + 3*167*FLEN/8, x4, x1, x2)

inst_37032:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xf003fff; valaddr_reg:x3; val_offset:111096*0 + 3*167*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111096*0 + 3*168*FLEN/8, x4, x1, x2)

inst_37033:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xf007fff; valaddr_reg:x3; val_offset:111099*0 + 3*168*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111099*0 + 3*169*FLEN/8, x4, x1, x2)

inst_37034:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xf00ffff; valaddr_reg:x3; val_offset:111102*0 + 3*169*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111102*0 + 3*170*FLEN/8, x4, x1, x2)

inst_37035:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xf01ffff; valaddr_reg:x3; val_offset:111105*0 + 3*170*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111105*0 + 3*171*FLEN/8, x4, x1, x2)

inst_37036:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xf03ffff; valaddr_reg:x3; val_offset:111108*0 + 3*171*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111108*0 + 3*172*FLEN/8, x4, x1, x2)

inst_37037:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xf07ffff; valaddr_reg:x3; val_offset:111111*0 + 3*172*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111111*0 + 3*173*FLEN/8, x4, x1, x2)

inst_37038:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xf0fffff; valaddr_reg:x3; val_offset:111114*0 + 3*173*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111114*0 + 3*174*FLEN/8, x4, x1, x2)

inst_37039:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xf1fffff; valaddr_reg:x3; val_offset:111117*0 + 3*174*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111117*0 + 3*175*FLEN/8, x4, x1, x2)

inst_37040:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xf3fffff; valaddr_reg:x3; val_offset:111120*0 + 3*175*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111120*0 + 3*176*FLEN/8, x4, x1, x2)

inst_37041:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xf400000; valaddr_reg:x3; val_offset:111123*0 + 3*176*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111123*0 + 3*177*FLEN/8, x4, x1, x2)

inst_37042:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xf600000; valaddr_reg:x3; val_offset:111126*0 + 3*177*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111126*0 + 3*178*FLEN/8, x4, x1, x2)

inst_37043:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xf700000; valaddr_reg:x3; val_offset:111129*0 + 3*178*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111129*0 + 3*179*FLEN/8, x4, x1, x2)

inst_37044:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xf780000; valaddr_reg:x3; val_offset:111132*0 + 3*179*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111132*0 + 3*180*FLEN/8, x4, x1, x2)

inst_37045:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xf7c0000; valaddr_reg:x3; val_offset:111135*0 + 3*180*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111135*0 + 3*181*FLEN/8, x4, x1, x2)

inst_37046:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xf7e0000; valaddr_reg:x3; val_offset:111138*0 + 3*181*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111138*0 + 3*182*FLEN/8, x4, x1, x2)

inst_37047:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xf7f0000; valaddr_reg:x3; val_offset:111141*0 + 3*182*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111141*0 + 3*183*FLEN/8, x4, x1, x2)

inst_37048:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xf7f8000; valaddr_reg:x3; val_offset:111144*0 + 3*183*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111144*0 + 3*184*FLEN/8, x4, x1, x2)

inst_37049:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xf7fc000; valaddr_reg:x3; val_offset:111147*0 + 3*184*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111147*0 + 3*185*FLEN/8, x4, x1, x2)

inst_37050:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xf7fe000; valaddr_reg:x3; val_offset:111150*0 + 3*185*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111150*0 + 3*186*FLEN/8, x4, x1, x2)

inst_37051:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xf7ff000; valaddr_reg:x3; val_offset:111153*0 + 3*186*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111153*0 + 3*187*FLEN/8, x4, x1, x2)

inst_37052:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xf7ff800; valaddr_reg:x3; val_offset:111156*0 + 3*187*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111156*0 + 3*188*FLEN/8, x4, x1, x2)

inst_37053:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xf7ffc00; valaddr_reg:x3; val_offset:111159*0 + 3*188*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111159*0 + 3*189*FLEN/8, x4, x1, x2)

inst_37054:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xf7ffe00; valaddr_reg:x3; val_offset:111162*0 + 3*189*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111162*0 + 3*190*FLEN/8, x4, x1, x2)

inst_37055:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xf7fff00; valaddr_reg:x3; val_offset:111165*0 + 3*190*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111165*0 + 3*191*FLEN/8, x4, x1, x2)

inst_37056:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xf7fff80; valaddr_reg:x3; val_offset:111168*0 + 3*191*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111168*0 + 3*192*FLEN/8, x4, x1, x2)

inst_37057:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xf7fffc0; valaddr_reg:x3; val_offset:111171*0 + 3*192*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111171*0 + 3*193*FLEN/8, x4, x1, x2)

inst_37058:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xf7fffe0; valaddr_reg:x3; val_offset:111174*0 + 3*193*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111174*0 + 3*194*FLEN/8, x4, x1, x2)

inst_37059:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xf7ffff0; valaddr_reg:x3; val_offset:111177*0 + 3*194*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111177*0 + 3*195*FLEN/8, x4, x1, x2)

inst_37060:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xf7ffff8; valaddr_reg:x3; val_offset:111180*0 + 3*195*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111180*0 + 3*196*FLEN/8, x4, x1, x2)

inst_37061:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xf7ffffc; valaddr_reg:x3; val_offset:111183*0 + 3*196*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111183*0 + 3*197*FLEN/8, x4, x1, x2)

inst_37062:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xf7ffffe; valaddr_reg:x3; val_offset:111186*0 + 3*197*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111186*0 + 3*198*FLEN/8, x4, x1, x2)

inst_37063:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3a78ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3a78ca; op2val:0x0;
op3val:0xf7fffff; valaddr_reg:x3; val_offset:111189*0 + 3*198*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111189*0 + 3*199*FLEN/8, x4, x1, x2)

inst_37064:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x3; val_offset:111192*0 + 3*199*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111192*0 + 3*200*FLEN/8, x4, x1, x2)

inst_37065:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x80000003; valaddr_reg:x3; val_offset:111195*0 + 3*200*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111195*0 + 3*201*FLEN/8, x4, x1, x2)

inst_37066:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x80000007; valaddr_reg:x3; val_offset:111198*0 + 3*201*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111198*0 + 3*202*FLEN/8, x4, x1, x2)

inst_37067:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x80199999; valaddr_reg:x3; val_offset:111201*0 + 3*202*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111201*0 + 3*203*FLEN/8, x4, x1, x2)

inst_37068:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x80249249; valaddr_reg:x3; val_offset:111204*0 + 3*203*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111204*0 + 3*204*FLEN/8, x4, x1, x2)

inst_37069:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x80333333; valaddr_reg:x3; val_offset:111207*0 + 3*204*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111207*0 + 3*205*FLEN/8, x4, x1, x2)

inst_37070:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x8036db6d; valaddr_reg:x3; val_offset:111210*0 + 3*205*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111210*0 + 3*206*FLEN/8, x4, x1, x2)

inst_37071:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x803bbbbb; valaddr_reg:x3; val_offset:111213*0 + 3*206*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111213*0 + 3*207*FLEN/8, x4, x1, x2)

inst_37072:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x80444444; valaddr_reg:x3; val_offset:111216*0 + 3*207*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111216*0 + 3*208*FLEN/8, x4, x1, x2)

inst_37073:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x804ccccc; valaddr_reg:x3; val_offset:111219*0 + 3*208*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111219*0 + 3*209*FLEN/8, x4, x1, x2)

inst_37074:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x805b6db6; valaddr_reg:x3; val_offset:111222*0 + 3*209*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111222*0 + 3*210*FLEN/8, x4, x1, x2)

inst_37075:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x80666666; valaddr_reg:x3; val_offset:111225*0 + 3*210*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111225*0 + 3*211*FLEN/8, x4, x1, x2)

inst_37076:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x806db6db; valaddr_reg:x3; val_offset:111228*0 + 3*211*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111228*0 + 3*212*FLEN/8, x4, x1, x2)

inst_37077:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x807ffff8; valaddr_reg:x3; val_offset:111231*0 + 3*212*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111231*0 + 3*213*FLEN/8, x4, x1, x2)

inst_37078:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x807ffffc; valaddr_reg:x3; val_offset:111234*0 + 3*213*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111234*0 + 3*214*FLEN/8, x4, x1, x2)

inst_37079:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x3; val_offset:111237*0 + 3*214*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111237*0 + 3*215*FLEN/8, x4, x1, x2)

inst_37080:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x8a000000; valaddr_reg:x3; val_offset:111240*0 + 3*215*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111240*0 + 3*216*FLEN/8, x4, x1, x2)

inst_37081:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x8a000001; valaddr_reg:x3; val_offset:111243*0 + 3*216*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111243*0 + 3*217*FLEN/8, x4, x1, x2)

inst_37082:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x8a000003; valaddr_reg:x3; val_offset:111246*0 + 3*217*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111246*0 + 3*218*FLEN/8, x4, x1, x2)

inst_37083:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x8a000007; valaddr_reg:x3; val_offset:111249*0 + 3*218*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111249*0 + 3*219*FLEN/8, x4, x1, x2)

inst_37084:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x8a00000f; valaddr_reg:x3; val_offset:111252*0 + 3*219*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111252*0 + 3*220*FLEN/8, x4, x1, x2)

inst_37085:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x8a00001f; valaddr_reg:x3; val_offset:111255*0 + 3*220*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111255*0 + 3*221*FLEN/8, x4, x1, x2)

inst_37086:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x8a00003f; valaddr_reg:x3; val_offset:111258*0 + 3*221*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111258*0 + 3*222*FLEN/8, x4, x1, x2)

inst_37087:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x8a00007f; valaddr_reg:x3; val_offset:111261*0 + 3*222*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111261*0 + 3*223*FLEN/8, x4, x1, x2)

inst_37088:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x8a0000ff; valaddr_reg:x3; val_offset:111264*0 + 3*223*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111264*0 + 3*224*FLEN/8, x4, x1, x2)

inst_37089:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x8a0001ff; valaddr_reg:x3; val_offset:111267*0 + 3*224*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111267*0 + 3*225*FLEN/8, x4, x1, x2)

inst_37090:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x8a0003ff; valaddr_reg:x3; val_offset:111270*0 + 3*225*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111270*0 + 3*226*FLEN/8, x4, x1, x2)

inst_37091:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x8a0007ff; valaddr_reg:x3; val_offset:111273*0 + 3*226*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111273*0 + 3*227*FLEN/8, x4, x1, x2)

inst_37092:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x8a000fff; valaddr_reg:x3; val_offset:111276*0 + 3*227*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111276*0 + 3*228*FLEN/8, x4, x1, x2)

inst_37093:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x8a001fff; valaddr_reg:x3; val_offset:111279*0 + 3*228*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111279*0 + 3*229*FLEN/8, x4, x1, x2)

inst_37094:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x8a003fff; valaddr_reg:x3; val_offset:111282*0 + 3*229*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111282*0 + 3*230*FLEN/8, x4, x1, x2)

inst_37095:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x8a007fff; valaddr_reg:x3; val_offset:111285*0 + 3*230*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111285*0 + 3*231*FLEN/8, x4, x1, x2)

inst_37096:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x8a00ffff; valaddr_reg:x3; val_offset:111288*0 + 3*231*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111288*0 + 3*232*FLEN/8, x4, x1, x2)

inst_37097:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x8a01ffff; valaddr_reg:x3; val_offset:111291*0 + 3*232*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111291*0 + 3*233*FLEN/8, x4, x1, x2)

inst_37098:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x8a03ffff; valaddr_reg:x3; val_offset:111294*0 + 3*233*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111294*0 + 3*234*FLEN/8, x4, x1, x2)

inst_37099:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x8a07ffff; valaddr_reg:x3; val_offset:111297*0 + 3*234*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111297*0 + 3*235*FLEN/8, x4, x1, x2)

inst_37100:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x8a0fffff; valaddr_reg:x3; val_offset:111300*0 + 3*235*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111300*0 + 3*236*FLEN/8, x4, x1, x2)

inst_37101:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x8a1fffff; valaddr_reg:x3; val_offset:111303*0 + 3*236*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111303*0 + 3*237*FLEN/8, x4, x1, x2)

inst_37102:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x8a3fffff; valaddr_reg:x3; val_offset:111306*0 + 3*237*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111306*0 + 3*238*FLEN/8, x4, x1, x2)

inst_37103:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x8a400000; valaddr_reg:x3; val_offset:111309*0 + 3*238*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111309*0 + 3*239*FLEN/8, x4, x1, x2)

inst_37104:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x8a600000; valaddr_reg:x3; val_offset:111312*0 + 3*239*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111312*0 + 3*240*FLEN/8, x4, x1, x2)

inst_37105:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x8a700000; valaddr_reg:x3; val_offset:111315*0 + 3*240*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111315*0 + 3*241*FLEN/8, x4, x1, x2)

inst_37106:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x8a780000; valaddr_reg:x3; val_offset:111318*0 + 3*241*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111318*0 + 3*242*FLEN/8, x4, x1, x2)

inst_37107:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x8a7c0000; valaddr_reg:x3; val_offset:111321*0 + 3*242*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111321*0 + 3*243*FLEN/8, x4, x1, x2)

inst_37108:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x8a7e0000; valaddr_reg:x3; val_offset:111324*0 + 3*243*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111324*0 + 3*244*FLEN/8, x4, x1, x2)

inst_37109:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x8a7f0000; valaddr_reg:x3; val_offset:111327*0 + 3*244*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111327*0 + 3*245*FLEN/8, x4, x1, x2)

inst_37110:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x8a7f8000; valaddr_reg:x3; val_offset:111330*0 + 3*245*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111330*0 + 3*246*FLEN/8, x4, x1, x2)

inst_37111:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x8a7fc000; valaddr_reg:x3; val_offset:111333*0 + 3*246*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111333*0 + 3*247*FLEN/8, x4, x1, x2)

inst_37112:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x8a7fe000; valaddr_reg:x3; val_offset:111336*0 + 3*247*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111336*0 + 3*248*FLEN/8, x4, x1, x2)

inst_37113:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x8a7ff000; valaddr_reg:x3; val_offset:111339*0 + 3*248*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111339*0 + 3*249*FLEN/8, x4, x1, x2)

inst_37114:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x8a7ff800; valaddr_reg:x3; val_offset:111342*0 + 3*249*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111342*0 + 3*250*FLEN/8, x4, x1, x2)

inst_37115:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x8a7ffc00; valaddr_reg:x3; val_offset:111345*0 + 3*250*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111345*0 + 3*251*FLEN/8, x4, x1, x2)

inst_37116:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x8a7ffe00; valaddr_reg:x3; val_offset:111348*0 + 3*251*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111348*0 + 3*252*FLEN/8, x4, x1, x2)

inst_37117:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x8a7fff00; valaddr_reg:x3; val_offset:111351*0 + 3*252*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111351*0 + 3*253*FLEN/8, x4, x1, x2)

inst_37118:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x8a7fff80; valaddr_reg:x3; val_offset:111354*0 + 3*253*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111354*0 + 3*254*FLEN/8, x4, x1, x2)

inst_37119:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x8a7fffc0; valaddr_reg:x3; val_offset:111357*0 + 3*254*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111357*0 + 3*255*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_3)

inst_37120:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x8a7fffe0; valaddr_reg:x3; val_offset:111360*0 + 3*256*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111360*0 + 3*256*FLEN/8, x4, x1, x2)

inst_37121:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x8a7ffff0; valaddr_reg:x3; val_offset:111363*0 + 3*257*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111363*0 + 3*257*FLEN/8, x4, x1, x2)

inst_37122:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x8a7ffff8; valaddr_reg:x3; val_offset:111366*0 + 3*258*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111366*0 + 3*258*FLEN/8, x4, x1, x2)

inst_37123:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x8a7ffffc; valaddr_reg:x3; val_offset:111369*0 + 3*259*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111369*0 + 3*259*FLEN/8, x4, x1, x2)

inst_37124:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x8a7ffffe; valaddr_reg:x3; val_offset:111372*0 + 3*260*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111372*0 + 3*260*FLEN/8, x4, x1, x2)

inst_37125:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ab121 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x14 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ab121; op2val:0x80000000;
op3val:0x8a7fffff; valaddr_reg:x3; val_offset:111375*0 + 3*261*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111375*0 + 3*261*FLEN/8, x4, x1, x2)

inst_37126:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x80800001; valaddr_reg:x3; val_offset:111378*0 + 3*262*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111378*0 + 3*262*FLEN/8, x4, x1, x2)

inst_37127:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x80800003; valaddr_reg:x3; val_offset:111381*0 + 3*263*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111381*0 + 3*263*FLEN/8, x4, x1, x2)

inst_37128:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x80800007; valaddr_reg:x3; val_offset:111384*0 + 3*264*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111384*0 + 3*264*FLEN/8, x4, x1, x2)

inst_37129:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x80999999; valaddr_reg:x3; val_offset:111387*0 + 3*265*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111387*0 + 3*265*FLEN/8, x4, x1, x2)

inst_37130:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x80a49249; valaddr_reg:x3; val_offset:111390*0 + 3*266*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111390*0 + 3*266*FLEN/8, x4, x1, x2)

inst_37131:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x80b33333; valaddr_reg:x3; val_offset:111393*0 + 3*267*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111393*0 + 3*267*FLEN/8, x4, x1, x2)

inst_37132:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x80b6db6d; valaddr_reg:x3; val_offset:111396*0 + 3*268*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111396*0 + 3*268*FLEN/8, x4, x1, x2)

inst_37133:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x80bbbbbb; valaddr_reg:x3; val_offset:111399*0 + 3*269*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111399*0 + 3*269*FLEN/8, x4, x1, x2)

inst_37134:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x80c44444; valaddr_reg:x3; val_offset:111402*0 + 3*270*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111402*0 + 3*270*FLEN/8, x4, x1, x2)

inst_37135:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x80cccccc; valaddr_reg:x3; val_offset:111405*0 + 3*271*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111405*0 + 3*271*FLEN/8, x4, x1, x2)

inst_37136:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x80db6db6; valaddr_reg:x3; val_offset:111408*0 + 3*272*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111408*0 + 3*272*FLEN/8, x4, x1, x2)

inst_37137:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x80e66666; valaddr_reg:x3; val_offset:111411*0 + 3*273*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111411*0 + 3*273*FLEN/8, x4, x1, x2)

inst_37138:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x80edb6db; valaddr_reg:x3; val_offset:111414*0 + 3*274*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111414*0 + 3*274*FLEN/8, x4, x1, x2)

inst_37139:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x80fffff8; valaddr_reg:x3; val_offset:111417*0 + 3*275*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111417*0 + 3*275*FLEN/8, x4, x1, x2)

inst_37140:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x80fffffc; valaddr_reg:x3; val_offset:111420*0 + 3*276*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111420*0 + 3*276*FLEN/8, x4, x1, x2)

inst_37141:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x80fffffe; valaddr_reg:x3; val_offset:111423*0 + 3*277*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111423*0 + 3*277*FLEN/8, x4, x1, x2)

inst_37142:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x87000000; valaddr_reg:x3; val_offset:111426*0 + 3*278*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111426*0 + 3*278*FLEN/8, x4, x1, x2)

inst_37143:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x87000001; valaddr_reg:x3; val_offset:111429*0 + 3*279*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111429*0 + 3*279*FLEN/8, x4, x1, x2)

inst_37144:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x87000003; valaddr_reg:x3; val_offset:111432*0 + 3*280*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111432*0 + 3*280*FLEN/8, x4, x1, x2)

inst_37145:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x87000007; valaddr_reg:x3; val_offset:111435*0 + 3*281*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111435*0 + 3*281*FLEN/8, x4, x1, x2)

inst_37146:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x8700000f; valaddr_reg:x3; val_offset:111438*0 + 3*282*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111438*0 + 3*282*FLEN/8, x4, x1, x2)

inst_37147:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x8700001f; valaddr_reg:x3; val_offset:111441*0 + 3*283*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111441*0 + 3*283*FLEN/8, x4, x1, x2)

inst_37148:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x8700003f; valaddr_reg:x3; val_offset:111444*0 + 3*284*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111444*0 + 3*284*FLEN/8, x4, x1, x2)

inst_37149:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x8700007f; valaddr_reg:x3; val_offset:111447*0 + 3*285*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111447*0 + 3*285*FLEN/8, x4, x1, x2)

inst_37150:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x870000ff; valaddr_reg:x3; val_offset:111450*0 + 3*286*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111450*0 + 3*286*FLEN/8, x4, x1, x2)

inst_37151:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x870001ff; valaddr_reg:x3; val_offset:111453*0 + 3*287*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111453*0 + 3*287*FLEN/8, x4, x1, x2)

inst_37152:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x870003ff; valaddr_reg:x3; val_offset:111456*0 + 3*288*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111456*0 + 3*288*FLEN/8, x4, x1, x2)

inst_37153:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x870007ff; valaddr_reg:x3; val_offset:111459*0 + 3*289*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111459*0 + 3*289*FLEN/8, x4, x1, x2)

inst_37154:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x87000fff; valaddr_reg:x3; val_offset:111462*0 + 3*290*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111462*0 + 3*290*FLEN/8, x4, x1, x2)

inst_37155:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x87001fff; valaddr_reg:x3; val_offset:111465*0 + 3*291*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111465*0 + 3*291*FLEN/8, x4, x1, x2)

inst_37156:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x87003fff; valaddr_reg:x3; val_offset:111468*0 + 3*292*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111468*0 + 3*292*FLEN/8, x4, x1, x2)

inst_37157:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x87007fff; valaddr_reg:x3; val_offset:111471*0 + 3*293*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111471*0 + 3*293*FLEN/8, x4, x1, x2)

inst_37158:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x8700ffff; valaddr_reg:x3; val_offset:111474*0 + 3*294*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111474*0 + 3*294*FLEN/8, x4, x1, x2)

inst_37159:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x8701ffff; valaddr_reg:x3; val_offset:111477*0 + 3*295*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111477*0 + 3*295*FLEN/8, x4, x1, x2)

inst_37160:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x8703ffff; valaddr_reg:x3; val_offset:111480*0 + 3*296*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111480*0 + 3*296*FLEN/8, x4, x1, x2)

inst_37161:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x8707ffff; valaddr_reg:x3; val_offset:111483*0 + 3*297*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111483*0 + 3*297*FLEN/8, x4, x1, x2)

inst_37162:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x870fffff; valaddr_reg:x3; val_offset:111486*0 + 3*298*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111486*0 + 3*298*FLEN/8, x4, x1, x2)

inst_37163:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x871fffff; valaddr_reg:x3; val_offset:111489*0 + 3*299*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111489*0 + 3*299*FLEN/8, x4, x1, x2)

inst_37164:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x873fffff; valaddr_reg:x3; val_offset:111492*0 + 3*300*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111492*0 + 3*300*FLEN/8, x4, x1, x2)

inst_37165:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x87400000; valaddr_reg:x3; val_offset:111495*0 + 3*301*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111495*0 + 3*301*FLEN/8, x4, x1, x2)

inst_37166:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x87600000; valaddr_reg:x3; val_offset:111498*0 + 3*302*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111498*0 + 3*302*FLEN/8, x4, x1, x2)

inst_37167:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x87700000; valaddr_reg:x3; val_offset:111501*0 + 3*303*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111501*0 + 3*303*FLEN/8, x4, x1, x2)

inst_37168:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x87780000; valaddr_reg:x3; val_offset:111504*0 + 3*304*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111504*0 + 3*304*FLEN/8, x4, x1, x2)

inst_37169:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x877c0000; valaddr_reg:x3; val_offset:111507*0 + 3*305*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111507*0 + 3*305*FLEN/8, x4, x1, x2)

inst_37170:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x877e0000; valaddr_reg:x3; val_offset:111510*0 + 3*306*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111510*0 + 3*306*FLEN/8, x4, x1, x2)

inst_37171:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x877f0000; valaddr_reg:x3; val_offset:111513*0 + 3*307*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111513*0 + 3*307*FLEN/8, x4, x1, x2)

inst_37172:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x877f8000; valaddr_reg:x3; val_offset:111516*0 + 3*308*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111516*0 + 3*308*FLEN/8, x4, x1, x2)

inst_37173:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x877fc000; valaddr_reg:x3; val_offset:111519*0 + 3*309*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111519*0 + 3*309*FLEN/8, x4, x1, x2)

inst_37174:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x877fe000; valaddr_reg:x3; val_offset:111522*0 + 3*310*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111522*0 + 3*310*FLEN/8, x4, x1, x2)

inst_37175:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x877ff000; valaddr_reg:x3; val_offset:111525*0 + 3*311*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111525*0 + 3*311*FLEN/8, x4, x1, x2)

inst_37176:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x877ff800; valaddr_reg:x3; val_offset:111528*0 + 3*312*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111528*0 + 3*312*FLEN/8, x4, x1, x2)

inst_37177:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x877ffc00; valaddr_reg:x3; val_offset:111531*0 + 3*313*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111531*0 + 3*313*FLEN/8, x4, x1, x2)

inst_37178:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x877ffe00; valaddr_reg:x3; val_offset:111534*0 + 3*314*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111534*0 + 3*314*FLEN/8, x4, x1, x2)

inst_37179:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x877fff00; valaddr_reg:x3; val_offset:111537*0 + 3*315*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111537*0 + 3*315*FLEN/8, x4, x1, x2)

inst_37180:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x877fff80; valaddr_reg:x3; val_offset:111540*0 + 3*316*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111540*0 + 3*316*FLEN/8, x4, x1, x2)

inst_37181:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x877fffc0; valaddr_reg:x3; val_offset:111543*0 + 3*317*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111543*0 + 3*317*FLEN/8, x4, x1, x2)

inst_37182:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x877fffe0; valaddr_reg:x3; val_offset:111546*0 + 3*318*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111546*0 + 3*318*FLEN/8, x4, x1, x2)

inst_37183:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x877ffff0; valaddr_reg:x3; val_offset:111549*0 + 3*319*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111549*0 + 3*319*FLEN/8, x4, x1, x2)

inst_37184:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x877ffff8; valaddr_reg:x3; val_offset:111552*0 + 3*320*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111552*0 + 3*320*FLEN/8, x4, x1, x2)

inst_37185:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x877ffffc; valaddr_reg:x3; val_offset:111555*0 + 3*321*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111555*0 + 3*321*FLEN/8, x4, x1, x2)

inst_37186:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x877ffffe; valaddr_reg:x3; val_offset:111558*0 + 3*322*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111558*0 + 3*322*FLEN/8, x4, x1, x2)

inst_37187:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ad563 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ad563; op2val:0x80000000;
op3val:0x877fffff; valaddr_reg:x3; val_offset:111561*0 + 3*323*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111561*0 + 3*323*FLEN/8, x4, x1, x2)

inst_37188:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x3; val_offset:111564*0 + 3*324*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111564*0 + 3*324*FLEN/8, x4, x1, x2)

inst_37189:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x80000003; valaddr_reg:x3; val_offset:111567*0 + 3*325*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111567*0 + 3*325*FLEN/8, x4, x1, x2)

inst_37190:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x80000007; valaddr_reg:x3; val_offset:111570*0 + 3*326*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111570*0 + 3*326*FLEN/8, x4, x1, x2)

inst_37191:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x80199999; valaddr_reg:x3; val_offset:111573*0 + 3*327*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111573*0 + 3*327*FLEN/8, x4, x1, x2)

inst_37192:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x80249249; valaddr_reg:x3; val_offset:111576*0 + 3*328*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111576*0 + 3*328*FLEN/8, x4, x1, x2)

inst_37193:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x80333333; valaddr_reg:x3; val_offset:111579*0 + 3*329*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111579*0 + 3*329*FLEN/8, x4, x1, x2)

inst_37194:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x8036db6d; valaddr_reg:x3; val_offset:111582*0 + 3*330*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111582*0 + 3*330*FLEN/8, x4, x1, x2)

inst_37195:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x803bbbbb; valaddr_reg:x3; val_offset:111585*0 + 3*331*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111585*0 + 3*331*FLEN/8, x4, x1, x2)

inst_37196:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x80444444; valaddr_reg:x3; val_offset:111588*0 + 3*332*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111588*0 + 3*332*FLEN/8, x4, x1, x2)

inst_37197:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x804ccccc; valaddr_reg:x3; val_offset:111591*0 + 3*333*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111591*0 + 3*333*FLEN/8, x4, x1, x2)

inst_37198:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x805b6db6; valaddr_reg:x3; val_offset:111594*0 + 3*334*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111594*0 + 3*334*FLEN/8, x4, x1, x2)

inst_37199:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x80666666; valaddr_reg:x3; val_offset:111597*0 + 3*335*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111597*0 + 3*335*FLEN/8, x4, x1, x2)

inst_37200:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x806db6db; valaddr_reg:x3; val_offset:111600*0 + 3*336*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111600*0 + 3*336*FLEN/8, x4, x1, x2)

inst_37201:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x807ffff8; valaddr_reg:x3; val_offset:111603*0 + 3*337*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111603*0 + 3*337*FLEN/8, x4, x1, x2)

inst_37202:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x807ffffc; valaddr_reg:x3; val_offset:111606*0 + 3*338*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111606*0 + 3*338*FLEN/8, x4, x1, x2)

inst_37203:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x3; val_offset:111609*0 + 3*339*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111609*0 + 3*339*FLEN/8, x4, x1, x2)

inst_37204:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x83000000; valaddr_reg:x3; val_offset:111612*0 + 3*340*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111612*0 + 3*340*FLEN/8, x4, x1, x2)

inst_37205:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x83000001; valaddr_reg:x3; val_offset:111615*0 + 3*341*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111615*0 + 3*341*FLEN/8, x4, x1, x2)

inst_37206:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x83000003; valaddr_reg:x3; val_offset:111618*0 + 3*342*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111618*0 + 3*342*FLEN/8, x4, x1, x2)

inst_37207:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x83000007; valaddr_reg:x3; val_offset:111621*0 + 3*343*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111621*0 + 3*343*FLEN/8, x4, x1, x2)

inst_37208:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x8300000f; valaddr_reg:x3; val_offset:111624*0 + 3*344*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111624*0 + 3*344*FLEN/8, x4, x1, x2)

inst_37209:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x8300001f; valaddr_reg:x3; val_offset:111627*0 + 3*345*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111627*0 + 3*345*FLEN/8, x4, x1, x2)

inst_37210:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x8300003f; valaddr_reg:x3; val_offset:111630*0 + 3*346*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111630*0 + 3*346*FLEN/8, x4, x1, x2)

inst_37211:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x8300007f; valaddr_reg:x3; val_offset:111633*0 + 3*347*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111633*0 + 3*347*FLEN/8, x4, x1, x2)

inst_37212:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x830000ff; valaddr_reg:x3; val_offset:111636*0 + 3*348*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111636*0 + 3*348*FLEN/8, x4, x1, x2)

inst_37213:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x830001ff; valaddr_reg:x3; val_offset:111639*0 + 3*349*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111639*0 + 3*349*FLEN/8, x4, x1, x2)

inst_37214:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x830003ff; valaddr_reg:x3; val_offset:111642*0 + 3*350*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111642*0 + 3*350*FLEN/8, x4, x1, x2)

inst_37215:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x830007ff; valaddr_reg:x3; val_offset:111645*0 + 3*351*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111645*0 + 3*351*FLEN/8, x4, x1, x2)

inst_37216:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x83000fff; valaddr_reg:x3; val_offset:111648*0 + 3*352*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111648*0 + 3*352*FLEN/8, x4, x1, x2)

inst_37217:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x83001fff; valaddr_reg:x3; val_offset:111651*0 + 3*353*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111651*0 + 3*353*FLEN/8, x4, x1, x2)

inst_37218:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x83003fff; valaddr_reg:x3; val_offset:111654*0 + 3*354*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111654*0 + 3*354*FLEN/8, x4, x1, x2)

inst_37219:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x83007fff; valaddr_reg:x3; val_offset:111657*0 + 3*355*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111657*0 + 3*355*FLEN/8, x4, x1, x2)

inst_37220:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x8300ffff; valaddr_reg:x3; val_offset:111660*0 + 3*356*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111660*0 + 3*356*FLEN/8, x4, x1, x2)

inst_37221:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x8301ffff; valaddr_reg:x3; val_offset:111663*0 + 3*357*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111663*0 + 3*357*FLEN/8, x4, x1, x2)

inst_37222:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x8303ffff; valaddr_reg:x3; val_offset:111666*0 + 3*358*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111666*0 + 3*358*FLEN/8, x4, x1, x2)

inst_37223:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x8307ffff; valaddr_reg:x3; val_offset:111669*0 + 3*359*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111669*0 + 3*359*FLEN/8, x4, x1, x2)

inst_37224:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x830fffff; valaddr_reg:x3; val_offset:111672*0 + 3*360*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111672*0 + 3*360*FLEN/8, x4, x1, x2)

inst_37225:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x831fffff; valaddr_reg:x3; val_offset:111675*0 + 3*361*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111675*0 + 3*361*FLEN/8, x4, x1, x2)

inst_37226:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x833fffff; valaddr_reg:x3; val_offset:111678*0 + 3*362*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111678*0 + 3*362*FLEN/8, x4, x1, x2)

inst_37227:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x83400000; valaddr_reg:x3; val_offset:111681*0 + 3*363*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111681*0 + 3*363*FLEN/8, x4, x1, x2)

inst_37228:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x83600000; valaddr_reg:x3; val_offset:111684*0 + 3*364*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111684*0 + 3*364*FLEN/8, x4, x1, x2)

inst_37229:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x83700000; valaddr_reg:x3; val_offset:111687*0 + 3*365*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111687*0 + 3*365*FLEN/8, x4, x1, x2)

inst_37230:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x83780000; valaddr_reg:x3; val_offset:111690*0 + 3*366*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111690*0 + 3*366*FLEN/8, x4, x1, x2)

inst_37231:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x837c0000; valaddr_reg:x3; val_offset:111693*0 + 3*367*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111693*0 + 3*367*FLEN/8, x4, x1, x2)

inst_37232:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x837e0000; valaddr_reg:x3; val_offset:111696*0 + 3*368*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111696*0 + 3*368*FLEN/8, x4, x1, x2)

inst_37233:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x837f0000; valaddr_reg:x3; val_offset:111699*0 + 3*369*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111699*0 + 3*369*FLEN/8, x4, x1, x2)

inst_37234:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x837f8000; valaddr_reg:x3; val_offset:111702*0 + 3*370*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111702*0 + 3*370*FLEN/8, x4, x1, x2)

inst_37235:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x837fc000; valaddr_reg:x3; val_offset:111705*0 + 3*371*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111705*0 + 3*371*FLEN/8, x4, x1, x2)

inst_37236:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x837fe000; valaddr_reg:x3; val_offset:111708*0 + 3*372*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111708*0 + 3*372*FLEN/8, x4, x1, x2)

inst_37237:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x837ff000; valaddr_reg:x3; val_offset:111711*0 + 3*373*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111711*0 + 3*373*FLEN/8, x4, x1, x2)

inst_37238:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x837ff800; valaddr_reg:x3; val_offset:111714*0 + 3*374*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111714*0 + 3*374*FLEN/8, x4, x1, x2)

inst_37239:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x837ffc00; valaddr_reg:x3; val_offset:111717*0 + 3*375*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111717*0 + 3*375*FLEN/8, x4, x1, x2)

inst_37240:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x837ffe00; valaddr_reg:x3; val_offset:111720*0 + 3*376*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111720*0 + 3*376*FLEN/8, x4, x1, x2)

inst_37241:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x837fff00; valaddr_reg:x3; val_offset:111723*0 + 3*377*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111723*0 + 3*377*FLEN/8, x4, x1, x2)

inst_37242:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x837fff80; valaddr_reg:x3; val_offset:111726*0 + 3*378*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111726*0 + 3*378*FLEN/8, x4, x1, x2)

inst_37243:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x837fffc0; valaddr_reg:x3; val_offset:111729*0 + 3*379*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111729*0 + 3*379*FLEN/8, x4, x1, x2)

inst_37244:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x837fffe0; valaddr_reg:x3; val_offset:111732*0 + 3*380*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111732*0 + 3*380*FLEN/8, x4, x1, x2)

inst_37245:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x837ffff0; valaddr_reg:x3; val_offset:111735*0 + 3*381*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111735*0 + 3*381*FLEN/8, x4, x1, x2)

inst_37246:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x837ffff8; valaddr_reg:x3; val_offset:111738*0 + 3*382*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111738*0 + 3*382*FLEN/8, x4, x1, x2)

inst_37247:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x837ffffc; valaddr_reg:x3; val_offset:111741*0 + 3*383*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111741*0 + 3*383*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_4)

inst_37248:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x837ffffe; valaddr_reg:x3; val_offset:111744*0 + 3*384*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111744*0 + 3*384*FLEN/8, x4, x1, x2)

inst_37249:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3add4b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x06 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3add4b; op2val:0x80000000;
op3val:0x837fffff; valaddr_reg:x3; val_offset:111747*0 + 3*385*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111747*0 + 3*385*FLEN/8, x4, x1, x2)

inst_37250:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x3; val_offset:111750*0 + 3*386*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111750*0 + 3*386*FLEN/8, x4, x1, x2)

inst_37251:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x80000003; valaddr_reg:x3; val_offset:111753*0 + 3*387*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111753*0 + 3*387*FLEN/8, x4, x1, x2)

inst_37252:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x80000007; valaddr_reg:x3; val_offset:111756*0 + 3*388*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111756*0 + 3*388*FLEN/8, x4, x1, x2)

inst_37253:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x80199999; valaddr_reg:x3; val_offset:111759*0 + 3*389*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111759*0 + 3*389*FLEN/8, x4, x1, x2)

inst_37254:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x80249249; valaddr_reg:x3; val_offset:111762*0 + 3*390*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111762*0 + 3*390*FLEN/8, x4, x1, x2)

inst_37255:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x80333333; valaddr_reg:x3; val_offset:111765*0 + 3*391*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111765*0 + 3*391*FLEN/8, x4, x1, x2)

inst_37256:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x8036db6d; valaddr_reg:x3; val_offset:111768*0 + 3*392*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111768*0 + 3*392*FLEN/8, x4, x1, x2)

inst_37257:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x803bbbbb; valaddr_reg:x3; val_offset:111771*0 + 3*393*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111771*0 + 3*393*FLEN/8, x4, x1, x2)

inst_37258:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x80444444; valaddr_reg:x3; val_offset:111774*0 + 3*394*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111774*0 + 3*394*FLEN/8, x4, x1, x2)

inst_37259:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x804ccccc; valaddr_reg:x3; val_offset:111777*0 + 3*395*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111777*0 + 3*395*FLEN/8, x4, x1, x2)

inst_37260:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x805b6db6; valaddr_reg:x3; val_offset:111780*0 + 3*396*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111780*0 + 3*396*FLEN/8, x4, x1, x2)

inst_37261:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x80666666; valaddr_reg:x3; val_offset:111783*0 + 3*397*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111783*0 + 3*397*FLEN/8, x4, x1, x2)

inst_37262:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x806db6db; valaddr_reg:x3; val_offset:111786*0 + 3*398*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111786*0 + 3*398*FLEN/8, x4, x1, x2)

inst_37263:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x807ffff8; valaddr_reg:x3; val_offset:111789*0 + 3*399*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111789*0 + 3*399*FLEN/8, x4, x1, x2)

inst_37264:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x807ffffc; valaddr_reg:x3; val_offset:111792*0 + 3*400*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111792*0 + 3*400*FLEN/8, x4, x1, x2)

inst_37265:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x3; val_offset:111795*0 + 3*401*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111795*0 + 3*401*FLEN/8, x4, x1, x2)

inst_37266:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x86800000; valaddr_reg:x3; val_offset:111798*0 + 3*402*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111798*0 + 3*402*FLEN/8, x4, x1, x2)

inst_37267:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x86800001; valaddr_reg:x3; val_offset:111801*0 + 3*403*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111801*0 + 3*403*FLEN/8, x4, x1, x2)

inst_37268:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x86800003; valaddr_reg:x3; val_offset:111804*0 + 3*404*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111804*0 + 3*404*FLEN/8, x4, x1, x2)

inst_37269:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x86800007; valaddr_reg:x3; val_offset:111807*0 + 3*405*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111807*0 + 3*405*FLEN/8, x4, x1, x2)

inst_37270:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x8680000f; valaddr_reg:x3; val_offset:111810*0 + 3*406*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111810*0 + 3*406*FLEN/8, x4, x1, x2)

inst_37271:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x8680001f; valaddr_reg:x3; val_offset:111813*0 + 3*407*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111813*0 + 3*407*FLEN/8, x4, x1, x2)

inst_37272:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x8680003f; valaddr_reg:x3; val_offset:111816*0 + 3*408*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111816*0 + 3*408*FLEN/8, x4, x1, x2)

inst_37273:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x8680007f; valaddr_reg:x3; val_offset:111819*0 + 3*409*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111819*0 + 3*409*FLEN/8, x4, x1, x2)

inst_37274:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x868000ff; valaddr_reg:x3; val_offset:111822*0 + 3*410*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111822*0 + 3*410*FLEN/8, x4, x1, x2)

inst_37275:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x868001ff; valaddr_reg:x3; val_offset:111825*0 + 3*411*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111825*0 + 3*411*FLEN/8, x4, x1, x2)

inst_37276:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x868003ff; valaddr_reg:x3; val_offset:111828*0 + 3*412*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111828*0 + 3*412*FLEN/8, x4, x1, x2)

inst_37277:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x868007ff; valaddr_reg:x3; val_offset:111831*0 + 3*413*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111831*0 + 3*413*FLEN/8, x4, x1, x2)

inst_37278:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x86800fff; valaddr_reg:x3; val_offset:111834*0 + 3*414*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111834*0 + 3*414*FLEN/8, x4, x1, x2)

inst_37279:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x86801fff; valaddr_reg:x3; val_offset:111837*0 + 3*415*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111837*0 + 3*415*FLEN/8, x4, x1, x2)

inst_37280:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x86803fff; valaddr_reg:x3; val_offset:111840*0 + 3*416*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111840*0 + 3*416*FLEN/8, x4, x1, x2)

inst_37281:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x86807fff; valaddr_reg:x3; val_offset:111843*0 + 3*417*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111843*0 + 3*417*FLEN/8, x4, x1, x2)

inst_37282:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x8680ffff; valaddr_reg:x3; val_offset:111846*0 + 3*418*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111846*0 + 3*418*FLEN/8, x4, x1, x2)

inst_37283:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x8681ffff; valaddr_reg:x3; val_offset:111849*0 + 3*419*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111849*0 + 3*419*FLEN/8, x4, x1, x2)

inst_37284:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x8683ffff; valaddr_reg:x3; val_offset:111852*0 + 3*420*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111852*0 + 3*420*FLEN/8, x4, x1, x2)

inst_37285:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x8687ffff; valaddr_reg:x3; val_offset:111855*0 + 3*421*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111855*0 + 3*421*FLEN/8, x4, x1, x2)

inst_37286:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x868fffff; valaddr_reg:x3; val_offset:111858*0 + 3*422*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111858*0 + 3*422*FLEN/8, x4, x1, x2)

inst_37287:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x869fffff; valaddr_reg:x3; val_offset:111861*0 + 3*423*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111861*0 + 3*423*FLEN/8, x4, x1, x2)

inst_37288:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x86bfffff; valaddr_reg:x3; val_offset:111864*0 + 3*424*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111864*0 + 3*424*FLEN/8, x4, x1, x2)

inst_37289:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x86c00000; valaddr_reg:x3; val_offset:111867*0 + 3*425*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111867*0 + 3*425*FLEN/8, x4, x1, x2)

inst_37290:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x86e00000; valaddr_reg:x3; val_offset:111870*0 + 3*426*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111870*0 + 3*426*FLEN/8, x4, x1, x2)

inst_37291:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x86f00000; valaddr_reg:x3; val_offset:111873*0 + 3*427*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111873*0 + 3*427*FLEN/8, x4, x1, x2)

inst_37292:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x86f80000; valaddr_reg:x3; val_offset:111876*0 + 3*428*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111876*0 + 3*428*FLEN/8, x4, x1, x2)

inst_37293:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x86fc0000; valaddr_reg:x3; val_offset:111879*0 + 3*429*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111879*0 + 3*429*FLEN/8, x4, x1, x2)

inst_37294:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x86fe0000; valaddr_reg:x3; val_offset:111882*0 + 3*430*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111882*0 + 3*430*FLEN/8, x4, x1, x2)

inst_37295:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x86ff0000; valaddr_reg:x3; val_offset:111885*0 + 3*431*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111885*0 + 3*431*FLEN/8, x4, x1, x2)

inst_37296:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x86ff8000; valaddr_reg:x3; val_offset:111888*0 + 3*432*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111888*0 + 3*432*FLEN/8, x4, x1, x2)

inst_37297:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x86ffc000; valaddr_reg:x3; val_offset:111891*0 + 3*433*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111891*0 + 3*433*FLEN/8, x4, x1, x2)

inst_37298:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x86ffe000; valaddr_reg:x3; val_offset:111894*0 + 3*434*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111894*0 + 3*434*FLEN/8, x4, x1, x2)

inst_37299:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x86fff000; valaddr_reg:x3; val_offset:111897*0 + 3*435*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111897*0 + 3*435*FLEN/8, x4, x1, x2)

inst_37300:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x86fff800; valaddr_reg:x3; val_offset:111900*0 + 3*436*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111900*0 + 3*436*FLEN/8, x4, x1, x2)

inst_37301:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x86fffc00; valaddr_reg:x3; val_offset:111903*0 + 3*437*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111903*0 + 3*437*FLEN/8, x4, x1, x2)

inst_37302:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x86fffe00; valaddr_reg:x3; val_offset:111906*0 + 3*438*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111906*0 + 3*438*FLEN/8, x4, x1, x2)

inst_37303:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x86ffff00; valaddr_reg:x3; val_offset:111909*0 + 3*439*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111909*0 + 3*439*FLEN/8, x4, x1, x2)

inst_37304:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x86ffff80; valaddr_reg:x3; val_offset:111912*0 + 3*440*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111912*0 + 3*440*FLEN/8, x4, x1, x2)

inst_37305:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x86ffffc0; valaddr_reg:x3; val_offset:111915*0 + 3*441*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111915*0 + 3*441*FLEN/8, x4, x1, x2)

inst_37306:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x86ffffe0; valaddr_reg:x3; val_offset:111918*0 + 3*442*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111918*0 + 3*442*FLEN/8, x4, x1, x2)

inst_37307:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x86fffff0; valaddr_reg:x3; val_offset:111921*0 + 3*443*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111921*0 + 3*443*FLEN/8, x4, x1, x2)

inst_37308:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x86fffff8; valaddr_reg:x3; val_offset:111924*0 + 3*444*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111924*0 + 3*444*FLEN/8, x4, x1, x2)

inst_37309:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x86fffffc; valaddr_reg:x3; val_offset:111927*0 + 3*445*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111927*0 + 3*445*FLEN/8, x4, x1, x2)

inst_37310:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x86fffffe; valaddr_reg:x3; val_offset:111930*0 + 3*446*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111930*0 + 3*446*FLEN/8, x4, x1, x2)

inst_37311:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3ae714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3ae714; op2val:0x80000000;
op3val:0x86ffffff; valaddr_reg:x3; val_offset:111933*0 + 3*447*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111933*0 + 3*447*FLEN/8, x4, x1, x2)

inst_37312:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xc0 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x60000000; valaddr_reg:x3; val_offset:111936*0 + 3*448*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111936*0 + 3*448*FLEN/8, x4, x1, x2)

inst_37313:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xc0 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x60000001; valaddr_reg:x3; val_offset:111939*0 + 3*449*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111939*0 + 3*449*FLEN/8, x4, x1, x2)

inst_37314:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xc0 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x60000003; valaddr_reg:x3; val_offset:111942*0 + 3*450*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111942*0 + 3*450*FLEN/8, x4, x1, x2)

inst_37315:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xc0 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x60000007; valaddr_reg:x3; val_offset:111945*0 + 3*451*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111945*0 + 3*451*FLEN/8, x4, x1, x2)

inst_37316:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xc0 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x6000000f; valaddr_reg:x3; val_offset:111948*0 + 3*452*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111948*0 + 3*452*FLEN/8, x4, x1, x2)

inst_37317:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xc0 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x6000001f; valaddr_reg:x3; val_offset:111951*0 + 3*453*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111951*0 + 3*453*FLEN/8, x4, x1, x2)

inst_37318:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xc0 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x6000003f; valaddr_reg:x3; val_offset:111954*0 + 3*454*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111954*0 + 3*454*FLEN/8, x4, x1, x2)

inst_37319:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xc0 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x6000007f; valaddr_reg:x3; val_offset:111957*0 + 3*455*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111957*0 + 3*455*FLEN/8, x4, x1, x2)

inst_37320:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xc0 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x600000ff; valaddr_reg:x3; val_offset:111960*0 + 3*456*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111960*0 + 3*456*FLEN/8, x4, x1, x2)

inst_37321:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xc0 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x600001ff; valaddr_reg:x3; val_offset:111963*0 + 3*457*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111963*0 + 3*457*FLEN/8, x4, x1, x2)

inst_37322:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xc0 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x600003ff; valaddr_reg:x3; val_offset:111966*0 + 3*458*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111966*0 + 3*458*FLEN/8, x4, x1, x2)

inst_37323:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xc0 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x600007ff; valaddr_reg:x3; val_offset:111969*0 + 3*459*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111969*0 + 3*459*FLEN/8, x4, x1, x2)

inst_37324:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xc0 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x60000fff; valaddr_reg:x3; val_offset:111972*0 + 3*460*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111972*0 + 3*460*FLEN/8, x4, x1, x2)

inst_37325:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xc0 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x60001fff; valaddr_reg:x3; val_offset:111975*0 + 3*461*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111975*0 + 3*461*FLEN/8, x4, x1, x2)

inst_37326:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xc0 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x60003fff; valaddr_reg:x3; val_offset:111978*0 + 3*462*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111978*0 + 3*462*FLEN/8, x4, x1, x2)

inst_37327:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xc0 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x60007fff; valaddr_reg:x3; val_offset:111981*0 + 3*463*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111981*0 + 3*463*FLEN/8, x4, x1, x2)

inst_37328:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xc0 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x6000ffff; valaddr_reg:x3; val_offset:111984*0 + 3*464*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111984*0 + 3*464*FLEN/8, x4, x1, x2)

inst_37329:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xc0 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x6001ffff; valaddr_reg:x3; val_offset:111987*0 + 3*465*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111987*0 + 3*465*FLEN/8, x4, x1, x2)

inst_37330:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xc0 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x6003ffff; valaddr_reg:x3; val_offset:111990*0 + 3*466*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111990*0 + 3*466*FLEN/8, x4, x1, x2)

inst_37331:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xc0 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x6007ffff; valaddr_reg:x3; val_offset:111993*0 + 3*467*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111993*0 + 3*467*FLEN/8, x4, x1, x2)

inst_37332:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xc0 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x600fffff; valaddr_reg:x3; val_offset:111996*0 + 3*468*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111996*0 + 3*468*FLEN/8, x4, x1, x2)

inst_37333:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xc0 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x601fffff; valaddr_reg:x3; val_offset:111999*0 + 3*469*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 111999*0 + 3*469*FLEN/8, x4, x1, x2)

inst_37334:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xc0 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x603fffff; valaddr_reg:x3; val_offset:112002*0 + 3*470*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112002*0 + 3*470*FLEN/8, x4, x1, x2)

inst_37335:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xc0 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x60400000; valaddr_reg:x3; val_offset:112005*0 + 3*471*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112005*0 + 3*471*FLEN/8, x4, x1, x2)

inst_37336:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xc0 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x60600000; valaddr_reg:x3; val_offset:112008*0 + 3*472*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112008*0 + 3*472*FLEN/8, x4, x1, x2)

inst_37337:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xc0 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x60700000; valaddr_reg:x3; val_offset:112011*0 + 3*473*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112011*0 + 3*473*FLEN/8, x4, x1, x2)

inst_37338:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xc0 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x60780000; valaddr_reg:x3; val_offset:112014*0 + 3*474*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112014*0 + 3*474*FLEN/8, x4, x1, x2)

inst_37339:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xc0 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x607c0000; valaddr_reg:x3; val_offset:112017*0 + 3*475*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112017*0 + 3*475*FLEN/8, x4, x1, x2)

inst_37340:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xc0 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x607e0000; valaddr_reg:x3; val_offset:112020*0 + 3*476*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112020*0 + 3*476*FLEN/8, x4, x1, x2)

inst_37341:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xc0 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x607f0000; valaddr_reg:x3; val_offset:112023*0 + 3*477*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112023*0 + 3*477*FLEN/8, x4, x1, x2)

inst_37342:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xc0 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x607f8000; valaddr_reg:x3; val_offset:112026*0 + 3*478*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112026*0 + 3*478*FLEN/8, x4, x1, x2)

inst_37343:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xc0 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x607fc000; valaddr_reg:x3; val_offset:112029*0 + 3*479*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112029*0 + 3*479*FLEN/8, x4, x1, x2)

inst_37344:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xc0 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x607fe000; valaddr_reg:x3; val_offset:112032*0 + 3*480*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112032*0 + 3*480*FLEN/8, x4, x1, x2)

inst_37345:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xc0 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x607ff000; valaddr_reg:x3; val_offset:112035*0 + 3*481*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112035*0 + 3*481*FLEN/8, x4, x1, x2)

inst_37346:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xc0 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x607ff800; valaddr_reg:x3; val_offset:112038*0 + 3*482*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112038*0 + 3*482*FLEN/8, x4, x1, x2)

inst_37347:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xc0 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x607ffc00; valaddr_reg:x3; val_offset:112041*0 + 3*483*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112041*0 + 3*483*FLEN/8, x4, x1, x2)

inst_37348:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xc0 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x607ffe00; valaddr_reg:x3; val_offset:112044*0 + 3*484*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112044*0 + 3*484*FLEN/8, x4, x1, x2)

inst_37349:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xc0 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x607fff00; valaddr_reg:x3; val_offset:112047*0 + 3*485*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112047*0 + 3*485*FLEN/8, x4, x1, x2)

inst_37350:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xc0 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x607fff80; valaddr_reg:x3; val_offset:112050*0 + 3*486*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112050*0 + 3*486*FLEN/8, x4, x1, x2)

inst_37351:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xc0 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x607fffc0; valaddr_reg:x3; val_offset:112053*0 + 3*487*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112053*0 + 3*487*FLEN/8, x4, x1, x2)

inst_37352:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xc0 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x607fffe0; valaddr_reg:x3; val_offset:112056*0 + 3*488*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112056*0 + 3*488*FLEN/8, x4, x1, x2)

inst_37353:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xc0 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x607ffff0; valaddr_reg:x3; val_offset:112059*0 + 3*489*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112059*0 + 3*489*FLEN/8, x4, x1, x2)

inst_37354:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xc0 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x607ffff8; valaddr_reg:x3; val_offset:112062*0 + 3*490*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112062*0 + 3*490*FLEN/8, x4, x1, x2)

inst_37355:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xc0 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x607ffffc; valaddr_reg:x3; val_offset:112065*0 + 3*491*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112065*0 + 3*491*FLEN/8, x4, x1, x2)

inst_37356:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xc0 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x607ffffe; valaddr_reg:x3; val_offset:112068*0 + 3*492*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112068*0 + 3*492*FLEN/8, x4, x1, x2)

inst_37357:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xc0 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x607fffff; valaddr_reg:x3; val_offset:112071*0 + 3*493*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112071*0 + 3*493*FLEN/8, x4, x1, x2)

inst_37358:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x7f000001; valaddr_reg:x3; val_offset:112074*0 + 3*494*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112074*0 + 3*494*FLEN/8, x4, x1, x2)

inst_37359:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x7f000003; valaddr_reg:x3; val_offset:112077*0 + 3*495*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112077*0 + 3*495*FLEN/8, x4, x1, x2)

inst_37360:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x7f000007; valaddr_reg:x3; val_offset:112080*0 + 3*496*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112080*0 + 3*496*FLEN/8, x4, x1, x2)

inst_37361:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x7f199999; valaddr_reg:x3; val_offset:112083*0 + 3*497*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112083*0 + 3*497*FLEN/8, x4, x1, x2)

inst_37362:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x7f249249; valaddr_reg:x3; val_offset:112086*0 + 3*498*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112086*0 + 3*498*FLEN/8, x4, x1, x2)

inst_37363:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x7f333333; valaddr_reg:x3; val_offset:112089*0 + 3*499*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112089*0 + 3*499*FLEN/8, x4, x1, x2)

inst_37364:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x7f36db6d; valaddr_reg:x3; val_offset:112092*0 + 3*500*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112092*0 + 3*500*FLEN/8, x4, x1, x2)

inst_37365:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x7f3bbbbb; valaddr_reg:x3; val_offset:112095*0 + 3*501*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112095*0 + 3*501*FLEN/8, x4, x1, x2)

inst_37366:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x7f444444; valaddr_reg:x3; val_offset:112098*0 + 3*502*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112098*0 + 3*502*FLEN/8, x4, x1, x2)

inst_37367:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x7f4ccccc; valaddr_reg:x3; val_offset:112101*0 + 3*503*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112101*0 + 3*503*FLEN/8, x4, x1, x2)

inst_37368:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x7f5b6db6; valaddr_reg:x3; val_offset:112104*0 + 3*504*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112104*0 + 3*504*FLEN/8, x4, x1, x2)

inst_37369:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x7f666666; valaddr_reg:x3; val_offset:112107*0 + 3*505*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112107*0 + 3*505*FLEN/8, x4, x1, x2)

inst_37370:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x7f6db6db; valaddr_reg:x3; val_offset:112110*0 + 3*506*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112110*0 + 3*506*FLEN/8, x4, x1, x2)

inst_37371:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x7f7ffff8; valaddr_reg:x3; val_offset:112113*0 + 3*507*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112113*0 + 3*507*FLEN/8, x4, x1, x2)

inst_37372:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x7f7ffffc; valaddr_reg:x3; val_offset:112116*0 + 3*508*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112116*0 + 3*508*FLEN/8, x4, x1, x2)

inst_37373:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3aea71 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2f4f12 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3aea71; op2val:0x3faf4f12;
op3val:0x7f7ffffe; valaddr_reg:x3; val_offset:112119*0 + 3*509*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112119*0 + 3*509*FLEN/8, x4, x1, x2)

inst_37374:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x3f800001; valaddr_reg:x3; val_offset:112122*0 + 3*510*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112122*0 + 3*510*FLEN/8, x4, x1, x2)

inst_37375:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x3f800003; valaddr_reg:x3; val_offset:112125*0 + 3*511*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112125*0 + 3*511*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_5)

inst_37376:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x3f800007; valaddr_reg:x3; val_offset:112128*0 + 3*512*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112128*0 + 3*512*FLEN/8, x4, x1, x2)

inst_37377:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x3f999999; valaddr_reg:x3; val_offset:112131*0 + 3*513*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112131*0 + 3*513*FLEN/8, x4, x1, x2)

inst_37378:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x3fa49249; valaddr_reg:x3; val_offset:112134*0 + 3*514*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112134*0 + 3*514*FLEN/8, x4, x1, x2)

inst_37379:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x3fb33333; valaddr_reg:x3; val_offset:112137*0 + 3*515*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112137*0 + 3*515*FLEN/8, x4, x1, x2)

inst_37380:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x3fb6db6d; valaddr_reg:x3; val_offset:112140*0 + 3*516*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112140*0 + 3*516*FLEN/8, x4, x1, x2)

inst_37381:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x3fbbbbbb; valaddr_reg:x3; val_offset:112143*0 + 3*517*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112143*0 + 3*517*FLEN/8, x4, x1, x2)

inst_37382:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x3fc44444; valaddr_reg:x3; val_offset:112146*0 + 3*518*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112146*0 + 3*518*FLEN/8, x4, x1, x2)

inst_37383:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x3fcccccc; valaddr_reg:x3; val_offset:112149*0 + 3*519*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112149*0 + 3*519*FLEN/8, x4, x1, x2)

inst_37384:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x3fdb6db6; valaddr_reg:x3; val_offset:112152*0 + 3*520*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112152*0 + 3*520*FLEN/8, x4, x1, x2)

inst_37385:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x3fe66666; valaddr_reg:x3; val_offset:112155*0 + 3*521*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112155*0 + 3*521*FLEN/8, x4, x1, x2)

inst_37386:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x3fedb6db; valaddr_reg:x3; val_offset:112158*0 + 3*522*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112158*0 + 3*522*FLEN/8, x4, x1, x2)

inst_37387:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x3ffffff8; valaddr_reg:x3; val_offset:112161*0 + 3*523*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112161*0 + 3*523*FLEN/8, x4, x1, x2)

inst_37388:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x3ffffffc; valaddr_reg:x3; val_offset:112164*0 + 3*524*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112164*0 + 3*524*FLEN/8, x4, x1, x2)

inst_37389:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x3ffffffe; valaddr_reg:x3; val_offset:112167*0 + 3*525*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112167*0 + 3*525*FLEN/8, x4, x1, x2)

inst_37390:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x89 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x44800000; valaddr_reg:x3; val_offset:112170*0 + 3*526*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112170*0 + 3*526*FLEN/8, x4, x1, x2)

inst_37391:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x89 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x44800001; valaddr_reg:x3; val_offset:112173*0 + 3*527*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112173*0 + 3*527*FLEN/8, x4, x1, x2)

inst_37392:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x89 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x44800003; valaddr_reg:x3; val_offset:112176*0 + 3*528*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112176*0 + 3*528*FLEN/8, x4, x1, x2)

inst_37393:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x89 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x44800007; valaddr_reg:x3; val_offset:112179*0 + 3*529*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112179*0 + 3*529*FLEN/8, x4, x1, x2)

inst_37394:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x89 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x4480000f; valaddr_reg:x3; val_offset:112182*0 + 3*530*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112182*0 + 3*530*FLEN/8, x4, x1, x2)

inst_37395:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x89 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x4480001f; valaddr_reg:x3; val_offset:112185*0 + 3*531*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112185*0 + 3*531*FLEN/8, x4, x1, x2)

inst_37396:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x89 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x4480003f; valaddr_reg:x3; val_offset:112188*0 + 3*532*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112188*0 + 3*532*FLEN/8, x4, x1, x2)

inst_37397:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x89 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x4480007f; valaddr_reg:x3; val_offset:112191*0 + 3*533*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112191*0 + 3*533*FLEN/8, x4, x1, x2)

inst_37398:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x89 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x448000ff; valaddr_reg:x3; val_offset:112194*0 + 3*534*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112194*0 + 3*534*FLEN/8, x4, x1, x2)

inst_37399:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x89 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x448001ff; valaddr_reg:x3; val_offset:112197*0 + 3*535*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112197*0 + 3*535*FLEN/8, x4, x1, x2)

inst_37400:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x89 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x448003ff; valaddr_reg:x3; val_offset:112200*0 + 3*536*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112200*0 + 3*536*FLEN/8, x4, x1, x2)

inst_37401:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x89 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x448007ff; valaddr_reg:x3; val_offset:112203*0 + 3*537*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112203*0 + 3*537*FLEN/8, x4, x1, x2)

inst_37402:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x89 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x44800fff; valaddr_reg:x3; val_offset:112206*0 + 3*538*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112206*0 + 3*538*FLEN/8, x4, x1, x2)

inst_37403:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x89 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x44801fff; valaddr_reg:x3; val_offset:112209*0 + 3*539*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112209*0 + 3*539*FLEN/8, x4, x1, x2)

inst_37404:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x89 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x44803fff; valaddr_reg:x3; val_offset:112212*0 + 3*540*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112212*0 + 3*540*FLEN/8, x4, x1, x2)

inst_37405:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x89 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x44807fff; valaddr_reg:x3; val_offset:112215*0 + 3*541*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112215*0 + 3*541*FLEN/8, x4, x1, x2)

inst_37406:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x89 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x4480ffff; valaddr_reg:x3; val_offset:112218*0 + 3*542*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112218*0 + 3*542*FLEN/8, x4, x1, x2)

inst_37407:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x89 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x4481ffff; valaddr_reg:x3; val_offset:112221*0 + 3*543*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112221*0 + 3*543*FLEN/8, x4, x1, x2)

inst_37408:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x89 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x4483ffff; valaddr_reg:x3; val_offset:112224*0 + 3*544*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112224*0 + 3*544*FLEN/8, x4, x1, x2)

inst_37409:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x89 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x4487ffff; valaddr_reg:x3; val_offset:112227*0 + 3*545*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112227*0 + 3*545*FLEN/8, x4, x1, x2)

inst_37410:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x89 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x448fffff; valaddr_reg:x3; val_offset:112230*0 + 3*546*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112230*0 + 3*546*FLEN/8, x4, x1, x2)

inst_37411:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x89 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x449fffff; valaddr_reg:x3; val_offset:112233*0 + 3*547*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112233*0 + 3*547*FLEN/8, x4, x1, x2)

inst_37412:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x89 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x44bfffff; valaddr_reg:x3; val_offset:112236*0 + 3*548*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112236*0 + 3*548*FLEN/8, x4, x1, x2)

inst_37413:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x89 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x44c00000; valaddr_reg:x3; val_offset:112239*0 + 3*549*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112239*0 + 3*549*FLEN/8, x4, x1, x2)

inst_37414:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x89 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x44e00000; valaddr_reg:x3; val_offset:112242*0 + 3*550*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112242*0 + 3*550*FLEN/8, x4, x1, x2)

inst_37415:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x89 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x44f00000; valaddr_reg:x3; val_offset:112245*0 + 3*551*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112245*0 + 3*551*FLEN/8, x4, x1, x2)

inst_37416:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x89 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x44f80000; valaddr_reg:x3; val_offset:112248*0 + 3*552*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112248*0 + 3*552*FLEN/8, x4, x1, x2)

inst_37417:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x89 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x44fc0000; valaddr_reg:x3; val_offset:112251*0 + 3*553*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112251*0 + 3*553*FLEN/8, x4, x1, x2)

inst_37418:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x89 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x44fe0000; valaddr_reg:x3; val_offset:112254*0 + 3*554*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112254*0 + 3*554*FLEN/8, x4, x1, x2)

inst_37419:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x89 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x44ff0000; valaddr_reg:x3; val_offset:112257*0 + 3*555*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112257*0 + 3*555*FLEN/8, x4, x1, x2)

inst_37420:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x89 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x44ff8000; valaddr_reg:x3; val_offset:112260*0 + 3*556*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112260*0 + 3*556*FLEN/8, x4, x1, x2)

inst_37421:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x89 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x44ffc000; valaddr_reg:x3; val_offset:112263*0 + 3*557*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112263*0 + 3*557*FLEN/8, x4, x1, x2)

inst_37422:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x89 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x44ffe000; valaddr_reg:x3; val_offset:112266*0 + 3*558*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112266*0 + 3*558*FLEN/8, x4, x1, x2)

inst_37423:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x89 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x44fff000; valaddr_reg:x3; val_offset:112269*0 + 3*559*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112269*0 + 3*559*FLEN/8, x4, x1, x2)

inst_37424:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x89 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x44fff800; valaddr_reg:x3; val_offset:112272*0 + 3*560*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112272*0 + 3*560*FLEN/8, x4, x1, x2)

inst_37425:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x89 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x44fffc00; valaddr_reg:x3; val_offset:112275*0 + 3*561*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112275*0 + 3*561*FLEN/8, x4, x1, x2)

inst_37426:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x89 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x44fffe00; valaddr_reg:x3; val_offset:112278*0 + 3*562*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112278*0 + 3*562*FLEN/8, x4, x1, x2)

inst_37427:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x89 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x44ffff00; valaddr_reg:x3; val_offset:112281*0 + 3*563*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112281*0 + 3*563*FLEN/8, x4, x1, x2)

inst_37428:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x89 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x44ffff80; valaddr_reg:x3; val_offset:112284*0 + 3*564*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112284*0 + 3*564*FLEN/8, x4, x1, x2)

inst_37429:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x89 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x44ffffc0; valaddr_reg:x3; val_offset:112287*0 + 3*565*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112287*0 + 3*565*FLEN/8, x4, x1, x2)

inst_37430:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x89 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x44ffffe0; valaddr_reg:x3; val_offset:112290*0 + 3*566*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112290*0 + 3*566*FLEN/8, x4, x1, x2)

inst_37431:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x89 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x44fffff0; valaddr_reg:x3; val_offset:112293*0 + 3*567*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112293*0 + 3*567*FLEN/8, x4, x1, x2)

inst_37432:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x89 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x44fffff8; valaddr_reg:x3; val_offset:112296*0 + 3*568*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112296*0 + 3*568*FLEN/8, x4, x1, x2)

inst_37433:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x89 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x44fffffc; valaddr_reg:x3; val_offset:112299*0 + 3*569*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112299*0 + 3*569*FLEN/8, x4, x1, x2)

inst_37434:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x89 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x44fffffe; valaddr_reg:x3; val_offset:112302*0 + 3*570*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112302*0 + 3*570*FLEN/8, x4, x1, x2)

inst_37435:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b4e66 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bbc61 and fs3 == 0 and fe3 == 0x89 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b4e66; op2val:0x2bbc61;
op3val:0x44ffffff; valaddr_reg:x3; val_offset:112305*0 + 3*571*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112305*0 + 3*571*FLEN/8, x4, x1, x2)

inst_37436:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x3f800001; valaddr_reg:x3; val_offset:112308*0 + 3*572*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112308*0 + 3*572*FLEN/8, x4, x1, x2)

inst_37437:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x3f800003; valaddr_reg:x3; val_offset:112311*0 + 3*573*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112311*0 + 3*573*FLEN/8, x4, x1, x2)

inst_37438:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x3f800007; valaddr_reg:x3; val_offset:112314*0 + 3*574*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112314*0 + 3*574*FLEN/8, x4, x1, x2)

inst_37439:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x7f and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x3f999999; valaddr_reg:x3; val_offset:112317*0 + 3*575*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112317*0 + 3*575*FLEN/8, x4, x1, x2)

inst_37440:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x7f and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x3fa49249; valaddr_reg:x3; val_offset:112320*0 + 3*576*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112320*0 + 3*576*FLEN/8, x4, x1, x2)

inst_37441:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x7f and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x3fb33333; valaddr_reg:x3; val_offset:112323*0 + 3*577*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112323*0 + 3*577*FLEN/8, x4, x1, x2)

inst_37442:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x7f and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x3fb6db6d; valaddr_reg:x3; val_offset:112326*0 + 3*578*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112326*0 + 3*578*FLEN/8, x4, x1, x2)

inst_37443:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x7f and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x3fbbbbbb; valaddr_reg:x3; val_offset:112329*0 + 3*579*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112329*0 + 3*579*FLEN/8, x4, x1, x2)

inst_37444:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x7f and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x3fc44444; valaddr_reg:x3; val_offset:112332*0 + 3*580*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112332*0 + 3*580*FLEN/8, x4, x1, x2)

inst_37445:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x7f and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x3fcccccc; valaddr_reg:x3; val_offset:112335*0 + 3*581*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112335*0 + 3*581*FLEN/8, x4, x1, x2)

inst_37446:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x7f and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x3fdb6db6; valaddr_reg:x3; val_offset:112338*0 + 3*582*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112338*0 + 3*582*FLEN/8, x4, x1, x2)

inst_37447:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x7f and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x3fe66666; valaddr_reg:x3; val_offset:112341*0 + 3*583*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112341*0 + 3*583*FLEN/8, x4, x1, x2)

inst_37448:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x7f and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x3fedb6db; valaddr_reg:x3; val_offset:112344*0 + 3*584*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112344*0 + 3*584*FLEN/8, x4, x1, x2)

inst_37449:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x3ffffff8; valaddr_reg:x3; val_offset:112347*0 + 3*585*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112347*0 + 3*585*FLEN/8, x4, x1, x2)

inst_37450:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x3ffffffc; valaddr_reg:x3; val_offset:112350*0 + 3*586*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112350*0 + 3*586*FLEN/8, x4, x1, x2)

inst_37451:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x3ffffffe; valaddr_reg:x3; val_offset:112353*0 + 3*587*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112353*0 + 3*587*FLEN/8, x4, x1, x2)

inst_37452:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x86 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x43000000; valaddr_reg:x3; val_offset:112356*0 + 3*588*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112356*0 + 3*588*FLEN/8, x4, x1, x2)

inst_37453:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x86 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x43000001; valaddr_reg:x3; val_offset:112359*0 + 3*589*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112359*0 + 3*589*FLEN/8, x4, x1, x2)

inst_37454:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x86 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x43000003; valaddr_reg:x3; val_offset:112362*0 + 3*590*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112362*0 + 3*590*FLEN/8, x4, x1, x2)

inst_37455:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x86 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x43000007; valaddr_reg:x3; val_offset:112365*0 + 3*591*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112365*0 + 3*591*FLEN/8, x4, x1, x2)

inst_37456:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x86 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x4300000f; valaddr_reg:x3; val_offset:112368*0 + 3*592*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112368*0 + 3*592*FLEN/8, x4, x1, x2)

inst_37457:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x86 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x4300001f; valaddr_reg:x3; val_offset:112371*0 + 3*593*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112371*0 + 3*593*FLEN/8, x4, x1, x2)

inst_37458:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x86 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x4300003f; valaddr_reg:x3; val_offset:112374*0 + 3*594*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112374*0 + 3*594*FLEN/8, x4, x1, x2)

inst_37459:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x86 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x4300007f; valaddr_reg:x3; val_offset:112377*0 + 3*595*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112377*0 + 3*595*FLEN/8, x4, x1, x2)

inst_37460:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x86 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x430000ff; valaddr_reg:x3; val_offset:112380*0 + 3*596*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112380*0 + 3*596*FLEN/8, x4, x1, x2)

inst_37461:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x86 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x430001ff; valaddr_reg:x3; val_offset:112383*0 + 3*597*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112383*0 + 3*597*FLEN/8, x4, x1, x2)

inst_37462:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x86 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x430003ff; valaddr_reg:x3; val_offset:112386*0 + 3*598*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112386*0 + 3*598*FLEN/8, x4, x1, x2)

inst_37463:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x86 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x430007ff; valaddr_reg:x3; val_offset:112389*0 + 3*599*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112389*0 + 3*599*FLEN/8, x4, x1, x2)

inst_37464:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x86 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x43000fff; valaddr_reg:x3; val_offset:112392*0 + 3*600*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112392*0 + 3*600*FLEN/8, x4, x1, x2)

inst_37465:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x86 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x43001fff; valaddr_reg:x3; val_offset:112395*0 + 3*601*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112395*0 + 3*601*FLEN/8, x4, x1, x2)

inst_37466:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x86 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x43003fff; valaddr_reg:x3; val_offset:112398*0 + 3*602*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112398*0 + 3*602*FLEN/8, x4, x1, x2)

inst_37467:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x86 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x43007fff; valaddr_reg:x3; val_offset:112401*0 + 3*603*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112401*0 + 3*603*FLEN/8, x4, x1, x2)

inst_37468:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x86 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x4300ffff; valaddr_reg:x3; val_offset:112404*0 + 3*604*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112404*0 + 3*604*FLEN/8, x4, x1, x2)

inst_37469:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x86 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x4301ffff; valaddr_reg:x3; val_offset:112407*0 + 3*605*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112407*0 + 3*605*FLEN/8, x4, x1, x2)

inst_37470:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x86 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x4303ffff; valaddr_reg:x3; val_offset:112410*0 + 3*606*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112410*0 + 3*606*FLEN/8, x4, x1, x2)

inst_37471:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x86 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x4307ffff; valaddr_reg:x3; val_offset:112413*0 + 3*607*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112413*0 + 3*607*FLEN/8, x4, x1, x2)

inst_37472:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x86 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x430fffff; valaddr_reg:x3; val_offset:112416*0 + 3*608*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112416*0 + 3*608*FLEN/8, x4, x1, x2)

inst_37473:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x86 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x431fffff; valaddr_reg:x3; val_offset:112419*0 + 3*609*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112419*0 + 3*609*FLEN/8, x4, x1, x2)

inst_37474:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x86 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x433fffff; valaddr_reg:x3; val_offset:112422*0 + 3*610*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112422*0 + 3*610*FLEN/8, x4, x1, x2)

inst_37475:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x86 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x43400000; valaddr_reg:x3; val_offset:112425*0 + 3*611*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112425*0 + 3*611*FLEN/8, x4, x1, x2)

inst_37476:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x86 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x43600000; valaddr_reg:x3; val_offset:112428*0 + 3*612*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112428*0 + 3*612*FLEN/8, x4, x1, x2)

inst_37477:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x86 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x43700000; valaddr_reg:x3; val_offset:112431*0 + 3*613*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112431*0 + 3*613*FLEN/8, x4, x1, x2)

inst_37478:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x86 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x43780000; valaddr_reg:x3; val_offset:112434*0 + 3*614*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112434*0 + 3*614*FLEN/8, x4, x1, x2)

inst_37479:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x86 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x437c0000; valaddr_reg:x3; val_offset:112437*0 + 3*615*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112437*0 + 3*615*FLEN/8, x4, x1, x2)

inst_37480:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x86 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x437e0000; valaddr_reg:x3; val_offset:112440*0 + 3*616*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112440*0 + 3*616*FLEN/8, x4, x1, x2)

inst_37481:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x86 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x437f0000; valaddr_reg:x3; val_offset:112443*0 + 3*617*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112443*0 + 3*617*FLEN/8, x4, x1, x2)

inst_37482:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x86 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x437f8000; valaddr_reg:x3; val_offset:112446*0 + 3*618*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112446*0 + 3*618*FLEN/8, x4, x1, x2)

inst_37483:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x86 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x437fc000; valaddr_reg:x3; val_offset:112449*0 + 3*619*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112449*0 + 3*619*FLEN/8, x4, x1, x2)

inst_37484:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x86 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x437fe000; valaddr_reg:x3; val_offset:112452*0 + 3*620*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112452*0 + 3*620*FLEN/8, x4, x1, x2)

inst_37485:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x86 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x437ff000; valaddr_reg:x3; val_offset:112455*0 + 3*621*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112455*0 + 3*621*FLEN/8, x4, x1, x2)

inst_37486:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x86 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x437ff800; valaddr_reg:x3; val_offset:112458*0 + 3*622*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112458*0 + 3*622*FLEN/8, x4, x1, x2)

inst_37487:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x86 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x437ffc00; valaddr_reg:x3; val_offset:112461*0 + 3*623*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112461*0 + 3*623*FLEN/8, x4, x1, x2)

inst_37488:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x86 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x437ffe00; valaddr_reg:x3; val_offset:112464*0 + 3*624*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112464*0 + 3*624*FLEN/8, x4, x1, x2)

inst_37489:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x86 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x437fff00; valaddr_reg:x3; val_offset:112467*0 + 3*625*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112467*0 + 3*625*FLEN/8, x4, x1, x2)

inst_37490:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x86 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x437fff80; valaddr_reg:x3; val_offset:112470*0 + 3*626*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112470*0 + 3*626*FLEN/8, x4, x1, x2)

inst_37491:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x86 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x437fffc0; valaddr_reg:x3; val_offset:112473*0 + 3*627*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112473*0 + 3*627*FLEN/8, x4, x1, x2)

inst_37492:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x86 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x437fffe0; valaddr_reg:x3; val_offset:112476*0 + 3*628*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112476*0 + 3*628*FLEN/8, x4, x1, x2)

inst_37493:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x86 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x437ffff0; valaddr_reg:x3; val_offset:112479*0 + 3*629*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112479*0 + 3*629*FLEN/8, x4, x1, x2)

inst_37494:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x86 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x437ffff8; valaddr_reg:x3; val_offset:112482*0 + 3*630*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112482*0 + 3*630*FLEN/8, x4, x1, x2)

inst_37495:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x86 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x437ffffc; valaddr_reg:x3; val_offset:112485*0 + 3*631*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112485*0 + 3*631*FLEN/8, x4, x1, x2)

inst_37496:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x86 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x437ffffe; valaddr_reg:x3; val_offset:112488*0 + 3*632*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112488*0 + 3*632*FLEN/8, x4, x1, x2)

inst_37497:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b88a3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2baecc and fs3 == 0 and fe3 == 0x86 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b88a3; op2val:0x2baecc;
op3val:0x437fffff; valaddr_reg:x3; val_offset:112491*0 + 3*633*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112491*0 + 3*633*FLEN/8, x4, x1, x2)

inst_37498:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x3f800001; valaddr_reg:x3; val_offset:112494*0 + 3*634*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112494*0 + 3*634*FLEN/8, x4, x1, x2)

inst_37499:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x3f800003; valaddr_reg:x3; val_offset:112497*0 + 3*635*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112497*0 + 3*635*FLEN/8, x4, x1, x2)

inst_37500:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x3f800007; valaddr_reg:x3; val_offset:112500*0 + 3*636*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112500*0 + 3*636*FLEN/8, x4, x1, x2)

inst_37501:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x3f999999; valaddr_reg:x3; val_offset:112503*0 + 3*637*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112503*0 + 3*637*FLEN/8, x4, x1, x2)

inst_37502:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x3fa49249; valaddr_reg:x3; val_offset:112506*0 + 3*638*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112506*0 + 3*638*FLEN/8, x4, x1, x2)

inst_37503:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x3fb33333; valaddr_reg:x3; val_offset:112509*0 + 3*639*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112509*0 + 3*639*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_6)

inst_37504:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x3fb6db6d; valaddr_reg:x3; val_offset:112512*0 + 3*640*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112512*0 + 3*640*FLEN/8, x4, x1, x2)

inst_37505:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x3fbbbbbb; valaddr_reg:x3; val_offset:112515*0 + 3*641*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112515*0 + 3*641*FLEN/8, x4, x1, x2)

inst_37506:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x3fc44444; valaddr_reg:x3; val_offset:112518*0 + 3*642*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112518*0 + 3*642*FLEN/8, x4, x1, x2)

inst_37507:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x3fcccccc; valaddr_reg:x3; val_offset:112521*0 + 3*643*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112521*0 + 3*643*FLEN/8, x4, x1, x2)

inst_37508:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x3fdb6db6; valaddr_reg:x3; val_offset:112524*0 + 3*644*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112524*0 + 3*644*FLEN/8, x4, x1, x2)

inst_37509:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x3fe66666; valaddr_reg:x3; val_offset:112527*0 + 3*645*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112527*0 + 3*645*FLEN/8, x4, x1, x2)

inst_37510:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x3fedb6db; valaddr_reg:x3; val_offset:112530*0 + 3*646*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112530*0 + 3*646*FLEN/8, x4, x1, x2)

inst_37511:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x3ffffff8; valaddr_reg:x3; val_offset:112533*0 + 3*647*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112533*0 + 3*647*FLEN/8, x4, x1, x2)

inst_37512:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x3ffffffc; valaddr_reg:x3; val_offset:112536*0 + 3*648*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112536*0 + 3*648*FLEN/8, x4, x1, x2)

inst_37513:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x3ffffffe; valaddr_reg:x3; val_offset:112539*0 + 3*649*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112539*0 + 3*649*FLEN/8, x4, x1, x2)

inst_37514:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x92 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x49000000; valaddr_reg:x3; val_offset:112542*0 + 3*650*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112542*0 + 3*650*FLEN/8, x4, x1, x2)

inst_37515:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x92 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x49000001; valaddr_reg:x3; val_offset:112545*0 + 3*651*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112545*0 + 3*651*FLEN/8, x4, x1, x2)

inst_37516:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x92 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x49000003; valaddr_reg:x3; val_offset:112548*0 + 3*652*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112548*0 + 3*652*FLEN/8, x4, x1, x2)

inst_37517:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x92 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x49000007; valaddr_reg:x3; val_offset:112551*0 + 3*653*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112551*0 + 3*653*FLEN/8, x4, x1, x2)

inst_37518:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x92 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x4900000f; valaddr_reg:x3; val_offset:112554*0 + 3*654*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112554*0 + 3*654*FLEN/8, x4, x1, x2)

inst_37519:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x92 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x4900001f; valaddr_reg:x3; val_offset:112557*0 + 3*655*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112557*0 + 3*655*FLEN/8, x4, x1, x2)

inst_37520:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x92 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x4900003f; valaddr_reg:x3; val_offset:112560*0 + 3*656*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112560*0 + 3*656*FLEN/8, x4, x1, x2)

inst_37521:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x92 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x4900007f; valaddr_reg:x3; val_offset:112563*0 + 3*657*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112563*0 + 3*657*FLEN/8, x4, x1, x2)

inst_37522:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x92 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x490000ff; valaddr_reg:x3; val_offset:112566*0 + 3*658*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112566*0 + 3*658*FLEN/8, x4, x1, x2)

inst_37523:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x92 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x490001ff; valaddr_reg:x3; val_offset:112569*0 + 3*659*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112569*0 + 3*659*FLEN/8, x4, x1, x2)

inst_37524:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x92 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x490003ff; valaddr_reg:x3; val_offset:112572*0 + 3*660*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112572*0 + 3*660*FLEN/8, x4, x1, x2)

inst_37525:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x92 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x490007ff; valaddr_reg:x3; val_offset:112575*0 + 3*661*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112575*0 + 3*661*FLEN/8, x4, x1, x2)

inst_37526:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x92 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x49000fff; valaddr_reg:x3; val_offset:112578*0 + 3*662*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112578*0 + 3*662*FLEN/8, x4, x1, x2)

inst_37527:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x92 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x49001fff; valaddr_reg:x3; val_offset:112581*0 + 3*663*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112581*0 + 3*663*FLEN/8, x4, x1, x2)

inst_37528:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x92 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x49003fff; valaddr_reg:x3; val_offset:112584*0 + 3*664*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112584*0 + 3*664*FLEN/8, x4, x1, x2)

inst_37529:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x92 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x49007fff; valaddr_reg:x3; val_offset:112587*0 + 3*665*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112587*0 + 3*665*FLEN/8, x4, x1, x2)

inst_37530:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x92 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x4900ffff; valaddr_reg:x3; val_offset:112590*0 + 3*666*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112590*0 + 3*666*FLEN/8, x4, x1, x2)

inst_37531:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x92 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x4901ffff; valaddr_reg:x3; val_offset:112593*0 + 3*667*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112593*0 + 3*667*FLEN/8, x4, x1, x2)

inst_37532:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x92 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x4903ffff; valaddr_reg:x3; val_offset:112596*0 + 3*668*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112596*0 + 3*668*FLEN/8, x4, x1, x2)

inst_37533:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x92 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x4907ffff; valaddr_reg:x3; val_offset:112599*0 + 3*669*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112599*0 + 3*669*FLEN/8, x4, x1, x2)

inst_37534:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x92 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x490fffff; valaddr_reg:x3; val_offset:112602*0 + 3*670*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112602*0 + 3*670*FLEN/8, x4, x1, x2)

inst_37535:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x92 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x491fffff; valaddr_reg:x3; val_offset:112605*0 + 3*671*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112605*0 + 3*671*FLEN/8, x4, x1, x2)

inst_37536:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x92 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x493fffff; valaddr_reg:x3; val_offset:112608*0 + 3*672*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112608*0 + 3*672*FLEN/8, x4, x1, x2)

inst_37537:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x92 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x49400000; valaddr_reg:x3; val_offset:112611*0 + 3*673*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112611*0 + 3*673*FLEN/8, x4, x1, x2)

inst_37538:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x92 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x49600000; valaddr_reg:x3; val_offset:112614*0 + 3*674*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112614*0 + 3*674*FLEN/8, x4, x1, x2)

inst_37539:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x92 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x49700000; valaddr_reg:x3; val_offset:112617*0 + 3*675*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112617*0 + 3*675*FLEN/8, x4, x1, x2)

inst_37540:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x92 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x49780000; valaddr_reg:x3; val_offset:112620*0 + 3*676*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112620*0 + 3*676*FLEN/8, x4, x1, x2)

inst_37541:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x92 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x497c0000; valaddr_reg:x3; val_offset:112623*0 + 3*677*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112623*0 + 3*677*FLEN/8, x4, x1, x2)

inst_37542:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x92 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x497e0000; valaddr_reg:x3; val_offset:112626*0 + 3*678*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112626*0 + 3*678*FLEN/8, x4, x1, x2)

inst_37543:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x92 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x497f0000; valaddr_reg:x3; val_offset:112629*0 + 3*679*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112629*0 + 3*679*FLEN/8, x4, x1, x2)

inst_37544:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x92 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x497f8000; valaddr_reg:x3; val_offset:112632*0 + 3*680*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112632*0 + 3*680*FLEN/8, x4, x1, x2)

inst_37545:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x92 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x497fc000; valaddr_reg:x3; val_offset:112635*0 + 3*681*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112635*0 + 3*681*FLEN/8, x4, x1, x2)

inst_37546:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x92 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x497fe000; valaddr_reg:x3; val_offset:112638*0 + 3*682*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112638*0 + 3*682*FLEN/8, x4, x1, x2)

inst_37547:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x92 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x497ff000; valaddr_reg:x3; val_offset:112641*0 + 3*683*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112641*0 + 3*683*FLEN/8, x4, x1, x2)

inst_37548:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x92 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x497ff800; valaddr_reg:x3; val_offset:112644*0 + 3*684*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112644*0 + 3*684*FLEN/8, x4, x1, x2)

inst_37549:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x92 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x497ffc00; valaddr_reg:x3; val_offset:112647*0 + 3*685*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112647*0 + 3*685*FLEN/8, x4, x1, x2)

inst_37550:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x92 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x497ffe00; valaddr_reg:x3; val_offset:112650*0 + 3*686*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112650*0 + 3*686*FLEN/8, x4, x1, x2)

inst_37551:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x92 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x497fff00; valaddr_reg:x3; val_offset:112653*0 + 3*687*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112653*0 + 3*687*FLEN/8, x4, x1, x2)

inst_37552:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x92 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x497fff80; valaddr_reg:x3; val_offset:112656*0 + 3*688*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112656*0 + 3*688*FLEN/8, x4, x1, x2)

inst_37553:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x92 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x497fffc0; valaddr_reg:x3; val_offset:112659*0 + 3*689*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112659*0 + 3*689*FLEN/8, x4, x1, x2)

inst_37554:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x92 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x497fffe0; valaddr_reg:x3; val_offset:112662*0 + 3*690*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112662*0 + 3*690*FLEN/8, x4, x1, x2)

inst_37555:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x92 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x497ffff0; valaddr_reg:x3; val_offset:112665*0 + 3*691*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112665*0 + 3*691*FLEN/8, x4, x1, x2)

inst_37556:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x92 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x497ffff8; valaddr_reg:x3; val_offset:112668*0 + 3*692*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112668*0 + 3*692*FLEN/8, x4, x1, x2)

inst_37557:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x92 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x497ffffc; valaddr_reg:x3; val_offset:112671*0 + 3*693*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112671*0 + 3*693*FLEN/8, x4, x1, x2)

inst_37558:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x92 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x497ffffe; valaddr_reg:x3; val_offset:112674*0 + 3*694*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112674*0 + 3*694*FLEN/8, x4, x1, x2)

inst_37559:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3b9454 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2bac13 and fs3 == 0 and fe3 == 0x92 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3b9454; op2val:0x2bac13;
op3val:0x497fffff; valaddr_reg:x3; val_offset:112677*0 + 3*695*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112677*0 + 3*695*FLEN/8, x4, x1, x2)

inst_37560:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x1; valaddr_reg:x3; val_offset:112680*0 + 3*696*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112680*0 + 3*696*FLEN/8, x4, x1, x2)

inst_37561:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x3; valaddr_reg:x3; val_offset:112683*0 + 3*697*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112683*0 + 3*697*FLEN/8, x4, x1, x2)

inst_37562:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x7; valaddr_reg:x3; val_offset:112686*0 + 3*698*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112686*0 + 3*698*FLEN/8, x4, x1, x2)

inst_37563:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x199999; valaddr_reg:x3; val_offset:112689*0 + 3*699*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112689*0 + 3*699*FLEN/8, x4, x1, x2)

inst_37564:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x249249; valaddr_reg:x3; val_offset:112692*0 + 3*700*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112692*0 + 3*700*FLEN/8, x4, x1, x2)

inst_37565:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x333333; valaddr_reg:x3; val_offset:112695*0 + 3*701*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112695*0 + 3*701*FLEN/8, x4, x1, x2)

inst_37566:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x36db6d; valaddr_reg:x3; val_offset:112698*0 + 3*702*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112698*0 + 3*702*FLEN/8, x4, x1, x2)

inst_37567:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x3bbbbb; valaddr_reg:x3; val_offset:112701*0 + 3*703*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112701*0 + 3*703*FLEN/8, x4, x1, x2)

inst_37568:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x444444; valaddr_reg:x3; val_offset:112704*0 + 3*704*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112704*0 + 3*704*FLEN/8, x4, x1, x2)

inst_37569:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x4ccccc; valaddr_reg:x3; val_offset:112707*0 + 3*705*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112707*0 + 3*705*FLEN/8, x4, x1, x2)

inst_37570:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x5b6db6; valaddr_reg:x3; val_offset:112710*0 + 3*706*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112710*0 + 3*706*FLEN/8, x4, x1, x2)

inst_37571:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x666666; valaddr_reg:x3; val_offset:112713*0 + 3*707*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112713*0 + 3*707*FLEN/8, x4, x1, x2)

inst_37572:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x6db6db; valaddr_reg:x3; val_offset:112716*0 + 3*708*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112716*0 + 3*708*FLEN/8, x4, x1, x2)

inst_37573:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x7ffff8; valaddr_reg:x3; val_offset:112719*0 + 3*709*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112719*0 + 3*709*FLEN/8, x4, x1, x2)

inst_37574:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x7ffffc; valaddr_reg:x3; val_offset:112722*0 + 3*710*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112722*0 + 3*710*FLEN/8, x4, x1, x2)

inst_37575:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x7ffffe; valaddr_reg:x3; val_offset:112725*0 + 3*711*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112725*0 + 3*711*FLEN/8, x4, x1, x2)

inst_37576:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x9000000; valaddr_reg:x3; val_offset:112728*0 + 3*712*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112728*0 + 3*712*FLEN/8, x4, x1, x2)

inst_37577:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x9000001; valaddr_reg:x3; val_offset:112731*0 + 3*713*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112731*0 + 3*713*FLEN/8, x4, x1, x2)

inst_37578:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x9000003; valaddr_reg:x3; val_offset:112734*0 + 3*714*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112734*0 + 3*714*FLEN/8, x4, x1, x2)

inst_37579:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x9000007; valaddr_reg:x3; val_offset:112737*0 + 3*715*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112737*0 + 3*715*FLEN/8, x4, x1, x2)

inst_37580:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x900000f; valaddr_reg:x3; val_offset:112740*0 + 3*716*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112740*0 + 3*716*FLEN/8, x4, x1, x2)

inst_37581:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x900001f; valaddr_reg:x3; val_offset:112743*0 + 3*717*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112743*0 + 3*717*FLEN/8, x4, x1, x2)

inst_37582:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x900003f; valaddr_reg:x3; val_offset:112746*0 + 3*718*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112746*0 + 3*718*FLEN/8, x4, x1, x2)

inst_37583:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x900007f; valaddr_reg:x3; val_offset:112749*0 + 3*719*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112749*0 + 3*719*FLEN/8, x4, x1, x2)

inst_37584:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x90000ff; valaddr_reg:x3; val_offset:112752*0 + 3*720*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112752*0 + 3*720*FLEN/8, x4, x1, x2)

inst_37585:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x90001ff; valaddr_reg:x3; val_offset:112755*0 + 3*721*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112755*0 + 3*721*FLEN/8, x4, x1, x2)

inst_37586:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x90003ff; valaddr_reg:x3; val_offset:112758*0 + 3*722*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112758*0 + 3*722*FLEN/8, x4, x1, x2)

inst_37587:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x90007ff; valaddr_reg:x3; val_offset:112761*0 + 3*723*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112761*0 + 3*723*FLEN/8, x4, x1, x2)

inst_37588:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x9000fff; valaddr_reg:x3; val_offset:112764*0 + 3*724*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112764*0 + 3*724*FLEN/8, x4, x1, x2)

inst_37589:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x9001fff; valaddr_reg:x3; val_offset:112767*0 + 3*725*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112767*0 + 3*725*FLEN/8, x4, x1, x2)

inst_37590:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x9003fff; valaddr_reg:x3; val_offset:112770*0 + 3*726*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112770*0 + 3*726*FLEN/8, x4, x1, x2)

inst_37591:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x9007fff; valaddr_reg:x3; val_offset:112773*0 + 3*727*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112773*0 + 3*727*FLEN/8, x4, x1, x2)

inst_37592:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x900ffff; valaddr_reg:x3; val_offset:112776*0 + 3*728*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112776*0 + 3*728*FLEN/8, x4, x1, x2)

inst_37593:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x901ffff; valaddr_reg:x3; val_offset:112779*0 + 3*729*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112779*0 + 3*729*FLEN/8, x4, x1, x2)

inst_37594:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x903ffff; valaddr_reg:x3; val_offset:112782*0 + 3*730*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112782*0 + 3*730*FLEN/8, x4, x1, x2)

inst_37595:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x907ffff; valaddr_reg:x3; val_offset:112785*0 + 3*731*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112785*0 + 3*731*FLEN/8, x4, x1, x2)

inst_37596:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x90fffff; valaddr_reg:x3; val_offset:112788*0 + 3*732*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112788*0 + 3*732*FLEN/8, x4, x1, x2)

inst_37597:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x91fffff; valaddr_reg:x3; val_offset:112791*0 + 3*733*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112791*0 + 3*733*FLEN/8, x4, x1, x2)

inst_37598:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x93fffff; valaddr_reg:x3; val_offset:112794*0 + 3*734*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112794*0 + 3*734*FLEN/8, x4, x1, x2)

inst_37599:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x9400000; valaddr_reg:x3; val_offset:112797*0 + 3*735*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112797*0 + 3*735*FLEN/8, x4, x1, x2)

inst_37600:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x9600000; valaddr_reg:x3; val_offset:112800*0 + 3*736*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112800*0 + 3*736*FLEN/8, x4, x1, x2)

inst_37601:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x9700000; valaddr_reg:x3; val_offset:112803*0 + 3*737*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112803*0 + 3*737*FLEN/8, x4, x1, x2)

inst_37602:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x9780000; valaddr_reg:x3; val_offset:112806*0 + 3*738*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112806*0 + 3*738*FLEN/8, x4, x1, x2)

inst_37603:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x97c0000; valaddr_reg:x3; val_offset:112809*0 + 3*739*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112809*0 + 3*739*FLEN/8, x4, x1, x2)

inst_37604:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x97e0000; valaddr_reg:x3; val_offset:112812*0 + 3*740*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112812*0 + 3*740*FLEN/8, x4, x1, x2)

inst_37605:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x97f0000; valaddr_reg:x3; val_offset:112815*0 + 3*741*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112815*0 + 3*741*FLEN/8, x4, x1, x2)

inst_37606:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x97f8000; valaddr_reg:x3; val_offset:112818*0 + 3*742*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112818*0 + 3*742*FLEN/8, x4, x1, x2)

inst_37607:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x97fc000; valaddr_reg:x3; val_offset:112821*0 + 3*743*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112821*0 + 3*743*FLEN/8, x4, x1, x2)

inst_37608:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x97fe000; valaddr_reg:x3; val_offset:112824*0 + 3*744*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112824*0 + 3*744*FLEN/8, x4, x1, x2)

inst_37609:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x97ff000; valaddr_reg:x3; val_offset:112827*0 + 3*745*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112827*0 + 3*745*FLEN/8, x4, x1, x2)

inst_37610:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x97ff800; valaddr_reg:x3; val_offset:112830*0 + 3*746*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112830*0 + 3*746*FLEN/8, x4, x1, x2)

inst_37611:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x97ffc00; valaddr_reg:x3; val_offset:112833*0 + 3*747*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112833*0 + 3*747*FLEN/8, x4, x1, x2)

inst_37612:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x97ffe00; valaddr_reg:x3; val_offset:112836*0 + 3*748*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112836*0 + 3*748*FLEN/8, x4, x1, x2)

inst_37613:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x97fff00; valaddr_reg:x3; val_offset:112839*0 + 3*749*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112839*0 + 3*749*FLEN/8, x4, x1, x2)

inst_37614:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x97fff80; valaddr_reg:x3; val_offset:112842*0 + 3*750*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112842*0 + 3*750*FLEN/8, x4, x1, x2)

inst_37615:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x97fffc0; valaddr_reg:x3; val_offset:112845*0 + 3*751*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112845*0 + 3*751*FLEN/8, x4, x1, x2)

inst_37616:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x97fffe0; valaddr_reg:x3; val_offset:112848*0 + 3*752*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112848*0 + 3*752*FLEN/8, x4, x1, x2)

inst_37617:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x97ffff0; valaddr_reg:x3; val_offset:112851*0 + 3*753*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112851*0 + 3*753*FLEN/8, x4, x1, x2)

inst_37618:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x97ffff8; valaddr_reg:x3; val_offset:112854*0 + 3*754*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112854*0 + 3*754*FLEN/8, x4, x1, x2)

inst_37619:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x97ffffc; valaddr_reg:x3; val_offset:112857*0 + 3*755*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112857*0 + 3*755*FLEN/8, x4, x1, x2)

inst_37620:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x97ffffe; valaddr_reg:x3; val_offset:112860*0 + 3*756*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112860*0 + 3*756*FLEN/8, x4, x1, x2)

inst_37621:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c26a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c26a4; op2val:0x0;
op3val:0x97fffff; valaddr_reg:x3; val_offset:112863*0 + 3*757*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112863*0 + 3*757*FLEN/8, x4, x1, x2)

inst_37622:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c64f9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c64f9; op2val:0x0;
op3val:0x800001; valaddr_reg:x3; val_offset:112866*0 + 3*758*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112866*0 + 3*758*FLEN/8, x4, x1, x2)

inst_37623:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c64f9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c64f9; op2val:0x0;
op3val:0x800003; valaddr_reg:x3; val_offset:112869*0 + 3*759*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112869*0 + 3*759*FLEN/8, x4, x1, x2)

inst_37624:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c64f9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c64f9; op2val:0x0;
op3val:0x800007; valaddr_reg:x3; val_offset:112872*0 + 3*760*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112872*0 + 3*760*FLEN/8, x4, x1, x2)

inst_37625:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c64f9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c64f9; op2val:0x0;
op3val:0x999999; valaddr_reg:x3; val_offset:112875*0 + 3*761*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112875*0 + 3*761*FLEN/8, x4, x1, x2)

inst_37626:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c64f9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c64f9; op2val:0x0;
op3val:0xa49249; valaddr_reg:x3; val_offset:112878*0 + 3*762*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112878*0 + 3*762*FLEN/8, x4, x1, x2)

inst_37627:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c64f9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c64f9; op2val:0x0;
op3val:0xb33333; valaddr_reg:x3; val_offset:112881*0 + 3*763*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112881*0 + 3*763*FLEN/8, x4, x1, x2)

inst_37628:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c64f9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c64f9; op2val:0x0;
op3val:0xb6db6d; valaddr_reg:x3; val_offset:112884*0 + 3*764*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112884*0 + 3*764*FLEN/8, x4, x1, x2)

inst_37629:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c64f9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c64f9; op2val:0x0;
op3val:0xbbbbbb; valaddr_reg:x3; val_offset:112887*0 + 3*765*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112887*0 + 3*765*FLEN/8, x4, x1, x2)

inst_37630:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c64f9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c64f9; op2val:0x0;
op3val:0xc44444; valaddr_reg:x3; val_offset:112890*0 + 3*766*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112890*0 + 3*766*FLEN/8, x4, x1, x2)

inst_37631:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3c64f9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f3c64f9; op2val:0x0;
op3val:0xcccccc; valaddr_reg:x3; val_offset:112893*0 + 3*767*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 112893*0 + 3*767*FLEN/8, x4, x1, x2)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0x7f3a0e48,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb7fe000,32,FLEN)
NAN_BOXED(0x7f3a0e48,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb7ff000,32,FLEN)
NAN_BOXED(0x7f3a0e48,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb7ff800,32,FLEN)
NAN_BOXED(0x7f3a0e48,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb7ffc00,32,FLEN)
NAN_BOXED(0x7f3a0e48,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb7ffe00,32,FLEN)
NAN_BOXED(0x7f3a0e48,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb7fff00,32,FLEN)
NAN_BOXED(0x7f3a0e48,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb7fff80,32,FLEN)
NAN_BOXED(0x7f3a0e48,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb7fffc0,32,FLEN)
NAN_BOXED(0x7f3a0e48,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb7fffe0,32,FLEN)
NAN_BOXED(0x7f3a0e48,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb7ffff0,32,FLEN)
NAN_BOXED(0x7f3a0e48,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb7ffff8,32,FLEN)
NAN_BOXED(0x7f3a0e48,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb7ffffc,32,FLEN)
NAN_BOXED(0x7f3a0e48,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb7ffffe,32,FLEN)
NAN_BOXED(0x7f3a0e48,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb7fffff,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x199999,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x249249,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x333333,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x36db6d,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3bbbbb,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x444444,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4ccccc,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5b6db6,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x666666,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6db6db,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffff8,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffc,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffe,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7000000,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7000001,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7000003,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7000007,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x700000f,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x700001f,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x700003f,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x700007f,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x70000ff,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x70001ff,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x70003ff,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x70007ff,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7000fff,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7001fff,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7003fff,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7007fff,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x700ffff,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x701ffff,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x703ffff,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x707ffff,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x70fffff,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x71fffff,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x73fffff,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7400000,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7600000,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7700000,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7780000,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x77c0000,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x77e0000,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x77f0000,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x77f8000,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x77fc000,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x77fe000,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x77ff000,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x77ff800,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x77ffc00,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x77ffe00,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x77fff00,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x77fff80,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x77fffc0,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x77fffe0,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x77ffff0,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x77ffff8,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x77ffffc,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x77ffffe,32,FLEN)
NAN_BOXED(0x7f3a336f,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x77fffff,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x199999,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x249249,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x333333,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x36db6d,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3bbbbb,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x444444,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4ccccc,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5b6db6,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x666666,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6db6db,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffff8,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffc,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffe,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6800000,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6800001,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6800003,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6800007,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x680000f,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x680001f,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x680003f,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x680007f,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x68000ff,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x68001ff,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x68003ff,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x68007ff,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6800fff,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6801fff,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6803fff,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6807fff,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x680ffff,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x681ffff,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x683ffff,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x687ffff,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x68fffff,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x69fffff,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6bfffff,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6c00000,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6e00000,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6f00000,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6f80000,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6fc0000,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6fe0000,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6ff0000,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6ff8000,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6ffc000,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6ffe000,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6fff000,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6fff800,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6fffc00,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6fffe00,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6ffff00,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6ffff80,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6ffffc0,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6ffffe0,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6fffff0,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6fffff8,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6fffffc,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6fffffe,32,FLEN)
NAN_BOXED(0x7f3a3442,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6ffffff,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800001,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800003,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800007,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x999999,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa49249,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb33333,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb6db6d,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbbbbbb,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xc44444,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xcccccc,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xdb6db6,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe66666,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xedb6db,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffff8,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffffc,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffffe,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf000000,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf000001,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf000003,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf000007,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf00000f,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf00001f,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf00003f,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf00007f,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf0000ff,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf0001ff,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf0003ff,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf0007ff,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf000fff,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf001fff,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf003fff,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf007fff,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf00ffff,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf01ffff,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf03ffff,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf07ffff,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf0fffff,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf1fffff,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf3fffff,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf400000,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf600000,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf700000,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf780000,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7c0000,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7e0000,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7f0000,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7f8000,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7fc000,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7fe000,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7ff000,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7ff800,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7ffc00,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7ffe00,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7fff00,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7fff80,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7fffc0,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7fffe0,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7ffff0,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7ffff8,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7ffffc,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7ffffe,32,FLEN)
NAN_BOXED(0x7f3a78ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7fffff,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000001,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000003,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000007,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80199999,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80249249,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80333333,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8036db6d,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x803bbbbb,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80444444,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x804ccccc,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x805b6db6,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80666666,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x806db6db,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffff8,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffc,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffe,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a000000,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a000001,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a000003,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a000007,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a00000f,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a00001f,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a00003f,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a00007f,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a0000ff,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a0001ff,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a0003ff,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a0007ff,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a000fff,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a001fff,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a003fff,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a007fff,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a00ffff,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a01ffff,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a03ffff,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a07ffff,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a0fffff,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a1fffff,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a3fffff,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a400000,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a600000,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a700000,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a780000,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a7c0000,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a7e0000,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a7f0000,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a7f8000,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a7fc000,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a7fe000,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a7ff000,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a7ff800,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a7ffc00,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a7ffe00,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a7fff00,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a7fff80,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a7fffc0,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a7fffe0,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a7ffff0,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a7ffff8,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a7ffffc,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a7ffffe,32,FLEN)
NAN_BOXED(0x7f3ab121,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a7fffff,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80800001,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80800003,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80800007,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80999999,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80a49249,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80b33333,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80b6db6d,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80bbbbbb,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80c44444,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80cccccc,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80db6db6,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80e66666,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80edb6db,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80fffff8,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80fffffc,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80fffffe,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x87000000,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x87000001,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x87000003,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x87000007,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8700000f,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8700001f,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8700003f,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8700007f,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x870000ff,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x870001ff,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x870003ff,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x870007ff,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x87000fff,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x87001fff,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x87003fff,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x87007fff,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8700ffff,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8701ffff,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8703ffff,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8707ffff,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x870fffff,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x871fffff,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x873fffff,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x87400000,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x87600000,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x87700000,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x87780000,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877c0000,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877e0000,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877f0000,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877f8000,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877fc000,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877fe000,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877ff000,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877ff800,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877ffc00,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877ffe00,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877fff00,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877fff80,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877fffc0,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877fffe0,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877ffff0,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877ffff8,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877ffffc,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877ffffe,32,FLEN)
NAN_BOXED(0x7f3ad563,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x877fffff,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000001,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000003,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000007,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80199999,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80249249,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80333333,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8036db6d,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x803bbbbb,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80444444,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x804ccccc,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x805b6db6,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80666666,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x806db6db,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffff8,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffc,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffe,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83000000,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83000001,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83000003,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83000007,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8300000f,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8300001f,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8300003f,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8300007f,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x830000ff,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x830001ff,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x830003ff,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x830007ff,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83000fff,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83001fff,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83003fff,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83007fff,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8300ffff,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8301ffff,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8303ffff,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8307ffff,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x830fffff,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x831fffff,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x833fffff,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83400000,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83600000,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83700000,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83780000,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837c0000,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837e0000,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837f0000,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837f8000,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837fc000,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837fe000,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837ff000,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837ff800,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837ffc00,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837ffe00,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837fff00,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837fff80,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837fffc0,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837fffe0,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837ffff0,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837ffff8,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837ffffc,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837ffffe,32,FLEN)
NAN_BOXED(0x7f3add4b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x837fffff,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000001,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000003,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000007,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80199999,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80249249,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80333333,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8036db6d,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x803bbbbb,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80444444,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x804ccccc,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x805b6db6,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80666666,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x806db6db,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffff8,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffc,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffe,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86800000,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86800001,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86800003,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86800007,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8680000f,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8680001f,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8680003f,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8680007f,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x868000ff,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x868001ff,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x868003ff,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x868007ff,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86800fff,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86801fff,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86803fff,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86807fff,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8680ffff,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8681ffff,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8683ffff,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8687ffff,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x868fffff,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x869fffff,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86bfffff,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86c00000,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86e00000,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86f00000,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86f80000,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86fc0000,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86fe0000,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86ff0000,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86ff8000,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86ffc000,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86ffe000,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86fff000,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86fff800,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86fffc00,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86fffe00,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86ffff00,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86ffff80,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86ffffc0,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86ffffe0,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86fffff0,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86fffff8,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86fffffc,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86fffffe,32,FLEN)
NAN_BOXED(0x7f3ae714,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x86ffffff,32,FLEN)
NAN_BOXED(0x7f3aea71,32,FLEN)
NAN_BOXED(0x3faf4f12,32,FLEN)
NAN_BOXED(0x60000000,32,FLEN)
NAN_BOXED(0x7f3aea71,32,FLEN)
NAN_BOXED(0x3faf4f12,32,FLEN)
NAN_BOXED(0x60000001,32,FLEN)
NAN_BOXED(0x7f3aea71,32,FLEN)
NAN_BOXED(0x3faf4f12,32,FLEN)
NAN_BOXED(0x60000003,32,FLEN)
NAN_BOXED(0x7f3aea71,32,FLEN)
NAN_BOXED(0x3faf4f12,32,FLEN)
NAN_BOXED(0x60000007,32,FLEN)
NAN_BOXED(0x7f3aea71,32,FLEN)
NAN_BOXED(0x3faf4f12,32,FLEN)
NAN_BOXED(0x6000000f,32,FLEN)
NAN_BOXED(0x7f3aea71,32,FLEN)
NAN_BOXED(0x3faf4f12,32,FLEN)
NAN_BOXED(0x6000001f,32,FLEN)
NAN_BOXED(0x7f3aea71,32,FLEN)
NAN_BOXED(0x3faf4f12,32,FLEN)
NAN_BOXED(0x6000003f,32,FLEN)
NAN_BOXED(0x7f3aea71,32,FLEN)
NAN_BOXED(0x3faf4f12,32,FLEN)
NAN_BOXED(0x6000007f,32,FLEN)
NAN_BOXED(0x7f3aea71,32,FLEN)
NAN_BOXED(0x3faf4f12,32,FLEN)
NAN_BOXED(0x600000ff,32,FLEN)
NAN_BOXED(0x7f3aea71,32,FLEN)
NAN_BOXED(0x3faf4f12,32,FLEN)
NAN_BOXED(0x600001ff,32,FLEN)
NAN_BOXED(0x7f3aea71,32,FLEN)
NAN_BOXED(0x3faf4f12,32,FLEN)
NAN_BOXED(0x600003ff,32,FLEN)
NAN_BOXED(0x7f3aea71,32,FLEN)
NAN_BOXED(0x3faf4f12,32,FLEN)
NAN_BOXED(0x600007ff,32,FLEN)
NAN_BOXED(0x7f3aea71,32,FLEN)
NAN_BOXED(0x3faf4f12,32,FLEN)
NAN_BOXED(0x60000fff,32,FLEN)
NAN_BOXED(0x7f3aea71,32,FLEN)
NAN_BOXED(0x3faf4f12,32,FLEN)
NAN_BOXED(0x60001fff,32,FLEN)
NAN_BOXED(0x7f3aea71,32,FLEN)
NAN_BOXED(0x3faf4f12,32,FLEN)
NAN_BOXED(0x60003fff,32,FLEN)
NAN_BOXED(0x7f3aea71,32,FLEN)
NAN_BOXED(0x3faf4f12,32,FLEN)
NAN_BOXED(0x60007fff,32,FLEN)
NAN_BOXED(0x7f3aea71,32,FLEN)
NAN_BOXED(0x3faf4f12,32,FLEN)
NAN_BOXED(0x6000ffff,32,FLEN)
NAN_BOXED(0x7f3aea71,32,FLEN)
NAN_BOXED(0x3faf4f12,32,FLEN)
NAN_BOXED(0x6001ffff,32,FLEN)
NAN_BOXED(0x7f3aea71,32,FLEN)
NAN_BOXED(0x3faf4f12,32,FLEN)
NAN_BOXED(0x6003ffff,32,FLEN)
NAN_BOXED(0x7f3aea71,32,FLEN)
NAN_BOXED(0x3faf4f12,32,FLEN)
NAN_BOXED(0x6007ffff,32,FLEN)
NAN_BOXED(0x7f3aea71,32,FLEN)
NAN_BOXED(0x3faf4f12,32,FLEN)
NAN_BOXED(0x600fffff,32,FLEN)
NAN_BOXED(0x7f3aea71,32,FLEN)
NAN_BOXED(0x3faf4f12,32,FLEN)
NAN_BOXED(0x601fffff,32,FLEN)
NAN_BOXED(0x7f3aea71,32,FLEN)
NAN_BOXED(0x3faf4f12,32,FLEN)
NAN_BOXED(0x603fffff,32,FLEN)
NAN_BOXED(0x7f3aea71,32,FLEN)
NAN_BOXED(0x3faf4f12,32,FLEN)
NAN_BOXED(0x60400000,32,FLEN)
NAN_BOXED(0x7f3aea71,32,FLEN)
NAN_BOXED(0x3faf4f12,32,FLEN)
NAN_BOXED(0x60600000,32,FLEN)
NAN_BOXED(0x7f3aea71,32,FLEN)
NAN_BOXED(0x3faf4f12,32,FLEN)
NAN_BOXED(0x60700000,32,FLEN)
NAN_BOXED(0x7f3aea71,32,FLEN)
NAN_BOXED(0x3faf4f12,32,FLEN)
NAN_BOXED(0x60780000,32,FLEN)
NAN_BOXED(0x7f3aea71,32,FLEN)
NAN_BOXED(0x3faf4f12,32,FLEN)
NAN_BOXED(0x607c0000,32,FLEN)
NAN_BOXED(0x7f3aea71,32,FLEN)
NAN_BOXED(0x3faf4f12,32,FLEN)
NAN_BOXED(0x607e0000,32,FLEN)
NAN_BOXED(0x7f3aea71,32,FLEN)
NAN_BOXED(0x3faf4f12,32,FLEN)
NAN_BOXED(0x607f0000,32,FLEN)
NAN_BOXED(0x7f3aea71,32,FLEN)
NAN_BOXED(0x3faf4f12,32,FLEN)
NAN_BOXED(0x607f8000,32,FLEN)
NAN_BOXED(0x7f3aea71,32,FLEN)
NAN_BOXED(0x3faf4f12,32,FLEN)
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NAN_BOXED(0x7f3aea71,32,FLEN)
NAN_BOXED(0x3faf4f12,32,FLEN)
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NAN_BOXED(0x7f3aea71,32,FLEN)
NAN_BOXED(0x3faf4f12,32,FLEN)
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NAN_BOXED(0x7f3aea71,32,FLEN)
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NAN_BOXED(0x3faf4f12,32,FLEN)
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NAN_BOXED(0x7f3aea71,32,FLEN)
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NAN_BOXED(0x7f3aea71,32,FLEN)
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NAN_BOXED(0x7f3aea71,32,FLEN)
NAN_BOXED(0x3faf4f12,32,FLEN)
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NAN_BOXED(0x7f3aea71,32,FLEN)
NAN_BOXED(0x3faf4f12,32,FLEN)
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NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x3f800001,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x3f800003,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x3f800007,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x3f999999,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x3fa49249,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x3fb33333,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x3fb6db6d,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x3fbbbbbb,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x3fc44444,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x3fcccccc,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x3fdb6db6,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x3fe66666,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x3fedb6db,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x3ffffff8,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x3ffffffc,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x3ffffffe,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x44800000,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x44800001,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x44800003,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x44800007,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x4480000f,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x4480001f,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x4480003f,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x4480007f,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x448000ff,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x448001ff,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x448003ff,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x448007ff,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x44800fff,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x44801fff,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x44803fff,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x44807fff,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x4480ffff,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x4481ffff,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x4483ffff,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x4487ffff,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x448fffff,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x449fffff,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x44bfffff,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x44c00000,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x44e00000,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x44f00000,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x44f80000,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x44fc0000,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x44fe0000,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x44ff0000,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x44ff8000,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x44ffc000,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x44ffe000,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x44fff000,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x44fff800,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x44fffc00,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x44fffe00,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x44ffff00,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x44ffff80,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x44ffffc0,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x44ffffe0,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x44fffff0,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x44fffff8,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x44fffffc,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x44fffffe,32,FLEN)
NAN_BOXED(0x7f3b4e66,32,FLEN)
NAN_BOXED(0x2bbc61,32,FLEN)
NAN_BOXED(0x44ffffff,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x3f800001,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x3f800003,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x3f800007,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x3f999999,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x3fa49249,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x3fb33333,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x3fb6db6d,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x3fbbbbbb,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x3fc44444,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x3fcccccc,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x3fdb6db6,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x3fe66666,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x3fedb6db,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x3ffffff8,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x3ffffffc,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x3ffffffe,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x43000000,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x43000001,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x43000003,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x43000007,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x4300000f,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x4300001f,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x4300003f,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x4300007f,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x430000ff,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x430001ff,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x430003ff,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x430007ff,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x43000fff,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x43001fff,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x43003fff,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x43007fff,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x4300ffff,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x4301ffff,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x4303ffff,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x4307ffff,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x430fffff,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x431fffff,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x433fffff,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x43400000,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x43600000,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x43700000,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x43780000,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x437c0000,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x437e0000,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x437f0000,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x437f8000,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x437fc000,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x437fe000,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
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NAN_BOXED(0x437ff000,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
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NAN_BOXED(0x437ff800,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
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NAN_BOXED(0x437ffc00,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x437ffe00,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x437fff00,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x437fff80,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x437fffc0,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x437fffe0,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x437ffff0,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x437ffff8,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x437ffffc,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x437ffffe,32,FLEN)
NAN_BOXED(0x7f3b88a3,32,FLEN)
NAN_BOXED(0x2baecc,32,FLEN)
NAN_BOXED(0x437fffff,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x3f800001,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x3f800003,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x3f800007,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x3f999999,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x3fa49249,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x3fb33333,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x3fb6db6d,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x3fbbbbbb,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x3fc44444,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x3fcccccc,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x3fdb6db6,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x3fe66666,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x3fedb6db,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x3ffffff8,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x3ffffffc,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x3ffffffe,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x49000000,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x49000001,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x49000003,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x49000007,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x4900000f,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x4900001f,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x4900003f,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x4900007f,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x490000ff,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x490001ff,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x490003ff,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x490007ff,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x49000fff,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x49001fff,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x49003fff,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x49007fff,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x4900ffff,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x4901ffff,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x4903ffff,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x4907ffff,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x490fffff,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x491fffff,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x493fffff,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x49400000,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x49600000,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x49700000,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x49780000,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x497c0000,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x497e0000,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x497f0000,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x497f8000,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x497fc000,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x497fe000,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x497ff000,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x497ff800,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x497ffc00,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x497ffe00,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x497fff00,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x497fff80,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x497fffc0,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x497fffe0,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x497ffff0,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x497ffff8,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x497ffffc,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x497ffffe,32,FLEN)
NAN_BOXED(0x7f3b9454,32,FLEN)
NAN_BOXED(0x2bac13,32,FLEN)
NAN_BOXED(0x497fffff,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x199999,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x249249,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x333333,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x36db6d,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3bbbbb,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x444444,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4ccccc,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5b6db6,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x666666,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6db6db,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffff8,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffc,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffe,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x9000000,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x9000001,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x9000003,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x9000007,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x900000f,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x900001f,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x900003f,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x900007f,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x90000ff,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x90001ff,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x90003ff,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x90007ff,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x9000fff,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x9001fff,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x9003fff,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x9007fff,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x900ffff,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x901ffff,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x903ffff,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x907ffff,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x90fffff,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x91fffff,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x93fffff,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x9400000,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x9600000,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x9700000,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x9780000,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x97c0000,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x97e0000,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x97f0000,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x97f8000,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x97fc000,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x97fe000,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x97ff000,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x97ff800,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x97ffc00,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x97ffe00,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x97fff00,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x97fff80,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x97fffc0,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x97fffe0,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x97ffff0,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x97ffff8,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x97ffffc,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x97ffffe,32,FLEN)
NAN_BOXED(0x7f3c26a4,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x97fffff,32,FLEN)
NAN_BOXED(0x7f3c64f9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800001,32,FLEN)
NAN_BOXED(0x7f3c64f9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800003,32,FLEN)
NAN_BOXED(0x7f3c64f9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800007,32,FLEN)
NAN_BOXED(0x7f3c64f9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x999999,32,FLEN)
NAN_BOXED(0x7f3c64f9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa49249,32,FLEN)
NAN_BOXED(0x7f3c64f9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb33333,32,FLEN)
NAN_BOXED(0x7f3c64f9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb6db6d,32,FLEN)
NAN_BOXED(0x7f3c64f9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbbbbbb,32,FLEN)
NAN_BOXED(0x7f3c64f9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xc44444,32,FLEN)
NAN_BOXED(0x7f3c64f9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xcccccc,32,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;


signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_2:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_3:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_4:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_5:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_6:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine

tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
    .fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;

#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif

sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
