
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.7.1
// timestamp : Fri Jun 17 14:18:09 2022 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /scratch/pawan/work/normalised/RV32F/fnmadd.s.cgf \
 \
//                  -- xlen 32  \
//                  --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fnmadd.s instruction of the RISC-V RV32F_Zicsr,RV32FD_Zicsr,RV64F_Zicsr,RV64FD_Zicsr extension for the fnmadd_b15 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*);def TEST_CASE_1=True;",fnmadd_b15)
RVTEST_CASE(1,"//check ISA:=regex(.*E.*F.*);def TEST_CASE_1=True;",fnmadd_b15)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_27648:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0eaf24 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0eaf24; op2val:0x80000000;
op3val:0x807ffff8; valaddr_reg:x3; val_offset:82944*0 + 3*-1*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 82944*0 + 3*0*FLEN/8, x4, x1, x2)

inst_27649:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0eaf24 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0eaf24; op2val:0x80000000;
op3val:0x807ffffc; valaddr_reg:x3; val_offset:82947*0 + 3*0*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 82947*0 + 3*1*FLEN/8, x4, x1, x2)

inst_27650:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0eaf24 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0eaf24; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x3; val_offset:82950*0 + 3*1*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 82950*0 + 3*2*FLEN/8, x4, x1, x2)

inst_27651:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0eaf24 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x04 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0eaf24; op2val:0x80000000;
op3val:0x82000000; valaddr_reg:x3; val_offset:82953*0 + 3*2*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 82953*0 + 3*3*FLEN/8, x4, x1, x2)

inst_27652:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0eaf24 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x04 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0eaf24; op2val:0x80000000;
op3val:0x82000001; valaddr_reg:x3; val_offset:82956*0 + 3*3*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 82956*0 + 3*4*FLEN/8, x4, x1, x2)

inst_27653:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0eaf24 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x04 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0eaf24; op2val:0x80000000;
op3val:0x82000003; valaddr_reg:x3; val_offset:82959*0 + 3*4*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 82959*0 + 3*5*FLEN/8, x4, x1, x2)

inst_27654:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0eaf24 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x04 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0eaf24; op2val:0x80000000;
op3val:0x82000007; valaddr_reg:x3; val_offset:82962*0 + 3*5*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 82962*0 + 3*6*FLEN/8, x4, x1, x2)

inst_27655:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0eaf24 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x04 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0eaf24; op2val:0x80000000;
op3val:0x8200000f; valaddr_reg:x3; val_offset:82965*0 + 3*6*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 82965*0 + 3*7*FLEN/8, x4, x1, x2)

inst_27656:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0eaf24 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x04 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0eaf24; op2val:0x80000000;
op3val:0x8200001f; valaddr_reg:x3; val_offset:82968*0 + 3*7*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 82968*0 + 3*8*FLEN/8, x4, x1, x2)

inst_27657:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0eaf24 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x04 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0eaf24; op2val:0x80000000;
op3val:0x8200003f; valaddr_reg:x3; val_offset:82971*0 + 3*8*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 82971*0 + 3*9*FLEN/8, x4, x1, x2)

inst_27658:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0eaf24 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x04 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0eaf24; op2val:0x80000000;
op3val:0x8200007f; valaddr_reg:x3; val_offset:82974*0 + 3*9*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 82974*0 + 3*10*FLEN/8, x4, x1, x2)

inst_27659:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0eaf24 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x04 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0eaf24; op2val:0x80000000;
op3val:0x820000ff; valaddr_reg:x3; val_offset:82977*0 + 3*10*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 82977*0 + 3*11*FLEN/8, x4, x1, x2)

inst_27660:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0eaf24 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x04 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0eaf24; op2val:0x80000000;
op3val:0x820001ff; valaddr_reg:x3; val_offset:82980*0 + 3*11*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 82980*0 + 3*12*FLEN/8, x4, x1, x2)

inst_27661:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0eaf24 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x04 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0eaf24; op2val:0x80000000;
op3val:0x820003ff; valaddr_reg:x3; val_offset:82983*0 + 3*12*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 82983*0 + 3*13*FLEN/8, x4, x1, x2)

inst_27662:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0eaf24 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x04 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0eaf24; op2val:0x80000000;
op3val:0x820007ff; valaddr_reg:x3; val_offset:82986*0 + 3*13*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 82986*0 + 3*14*FLEN/8, x4, x1, x2)

inst_27663:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0eaf24 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x04 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0eaf24; op2val:0x80000000;
op3val:0x82000fff; valaddr_reg:x3; val_offset:82989*0 + 3*14*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 82989*0 + 3*15*FLEN/8, x4, x1, x2)

inst_27664:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0eaf24 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x04 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0eaf24; op2val:0x80000000;
op3val:0x82001fff; valaddr_reg:x3; val_offset:82992*0 + 3*15*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 82992*0 + 3*16*FLEN/8, x4, x1, x2)

inst_27665:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0eaf24 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x04 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0eaf24; op2val:0x80000000;
op3val:0x82003fff; valaddr_reg:x3; val_offset:82995*0 + 3*16*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 82995*0 + 3*17*FLEN/8, x4, x1, x2)

inst_27666:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0eaf24 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x04 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0eaf24; op2val:0x80000000;
op3val:0x82007fff; valaddr_reg:x3; val_offset:82998*0 + 3*17*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 82998*0 + 3*18*FLEN/8, x4, x1, x2)

inst_27667:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0eaf24 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x04 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0eaf24; op2val:0x80000000;
op3val:0x8200ffff; valaddr_reg:x3; val_offset:83001*0 + 3*18*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83001*0 + 3*19*FLEN/8, x4, x1, x2)

inst_27668:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0eaf24 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x04 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0eaf24; op2val:0x80000000;
op3val:0x8201ffff; valaddr_reg:x3; val_offset:83004*0 + 3*19*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83004*0 + 3*20*FLEN/8, x4, x1, x2)

inst_27669:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0eaf24 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x04 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0eaf24; op2val:0x80000000;
op3val:0x8203ffff; valaddr_reg:x3; val_offset:83007*0 + 3*20*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83007*0 + 3*21*FLEN/8, x4, x1, x2)

inst_27670:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0eaf24 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x04 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0eaf24; op2val:0x80000000;
op3val:0x8207ffff; valaddr_reg:x3; val_offset:83010*0 + 3*21*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83010*0 + 3*22*FLEN/8, x4, x1, x2)

inst_27671:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0eaf24 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x04 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0eaf24; op2val:0x80000000;
op3val:0x820fffff; valaddr_reg:x3; val_offset:83013*0 + 3*22*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83013*0 + 3*23*FLEN/8, x4, x1, x2)

inst_27672:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0eaf24 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x04 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0eaf24; op2val:0x80000000;
op3val:0x821fffff; valaddr_reg:x3; val_offset:83016*0 + 3*23*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83016*0 + 3*24*FLEN/8, x4, x1, x2)

inst_27673:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0eaf24 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x04 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0eaf24; op2val:0x80000000;
op3val:0x823fffff; valaddr_reg:x3; val_offset:83019*0 + 3*24*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83019*0 + 3*25*FLEN/8, x4, x1, x2)

inst_27674:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0eaf24 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x04 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0eaf24; op2val:0x80000000;
op3val:0x82400000; valaddr_reg:x3; val_offset:83022*0 + 3*25*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83022*0 + 3*26*FLEN/8, x4, x1, x2)

inst_27675:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0eaf24 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x04 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0eaf24; op2val:0x80000000;
op3val:0x82600000; valaddr_reg:x3; val_offset:83025*0 + 3*26*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83025*0 + 3*27*FLEN/8, x4, x1, x2)

inst_27676:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0eaf24 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x04 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0eaf24; op2val:0x80000000;
op3val:0x82700000; valaddr_reg:x3; val_offset:83028*0 + 3*27*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83028*0 + 3*28*FLEN/8, x4, x1, x2)

inst_27677:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0eaf24 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x04 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0eaf24; op2val:0x80000000;
op3val:0x82780000; valaddr_reg:x3; val_offset:83031*0 + 3*28*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83031*0 + 3*29*FLEN/8, x4, x1, x2)

inst_27678:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0eaf24 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x04 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0eaf24; op2val:0x80000000;
op3val:0x827c0000; valaddr_reg:x3; val_offset:83034*0 + 3*29*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83034*0 + 3*30*FLEN/8, x4, x1, x2)

inst_27679:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0eaf24 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x04 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0eaf24; op2val:0x80000000;
op3val:0x827e0000; valaddr_reg:x3; val_offset:83037*0 + 3*30*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83037*0 + 3*31*FLEN/8, x4, x1, x2)

inst_27680:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0eaf24 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x04 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0eaf24; op2val:0x80000000;
op3val:0x827f0000; valaddr_reg:x3; val_offset:83040*0 + 3*31*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83040*0 + 3*32*FLEN/8, x4, x1, x2)

inst_27681:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0eaf24 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x04 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0eaf24; op2val:0x80000000;
op3val:0x827f8000; valaddr_reg:x3; val_offset:83043*0 + 3*32*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83043*0 + 3*33*FLEN/8, x4, x1, x2)

inst_27682:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0eaf24 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x04 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0eaf24; op2val:0x80000000;
op3val:0x827fc000; valaddr_reg:x3; val_offset:83046*0 + 3*33*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83046*0 + 3*34*FLEN/8, x4, x1, x2)

inst_27683:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0eaf24 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x04 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0eaf24; op2val:0x80000000;
op3val:0x827fe000; valaddr_reg:x3; val_offset:83049*0 + 3*34*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83049*0 + 3*35*FLEN/8, x4, x1, x2)

inst_27684:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0eaf24 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x04 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0eaf24; op2val:0x80000000;
op3val:0x827ff000; valaddr_reg:x3; val_offset:83052*0 + 3*35*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83052*0 + 3*36*FLEN/8, x4, x1, x2)

inst_27685:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0eaf24 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x04 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0eaf24; op2val:0x80000000;
op3val:0x827ff800; valaddr_reg:x3; val_offset:83055*0 + 3*36*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83055*0 + 3*37*FLEN/8, x4, x1, x2)

inst_27686:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0eaf24 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x04 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0eaf24; op2val:0x80000000;
op3val:0x827ffc00; valaddr_reg:x3; val_offset:83058*0 + 3*37*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83058*0 + 3*38*FLEN/8, x4, x1, x2)

inst_27687:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0eaf24 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x04 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0eaf24; op2val:0x80000000;
op3val:0x827ffe00; valaddr_reg:x3; val_offset:83061*0 + 3*38*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83061*0 + 3*39*FLEN/8, x4, x1, x2)

inst_27688:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0eaf24 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x04 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0eaf24; op2val:0x80000000;
op3val:0x827fff00; valaddr_reg:x3; val_offset:83064*0 + 3*39*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83064*0 + 3*40*FLEN/8, x4, x1, x2)

inst_27689:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0eaf24 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x04 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0eaf24; op2val:0x80000000;
op3val:0x827fff80; valaddr_reg:x3; val_offset:83067*0 + 3*40*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83067*0 + 3*41*FLEN/8, x4, x1, x2)

inst_27690:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0eaf24 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x04 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0eaf24; op2val:0x80000000;
op3val:0x827fffc0; valaddr_reg:x3; val_offset:83070*0 + 3*41*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83070*0 + 3*42*FLEN/8, x4, x1, x2)

inst_27691:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0eaf24 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x04 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0eaf24; op2val:0x80000000;
op3val:0x827fffe0; valaddr_reg:x3; val_offset:83073*0 + 3*42*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83073*0 + 3*43*FLEN/8, x4, x1, x2)

inst_27692:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0eaf24 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x04 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0eaf24; op2val:0x80000000;
op3val:0x827ffff0; valaddr_reg:x3; val_offset:83076*0 + 3*43*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83076*0 + 3*44*FLEN/8, x4, x1, x2)

inst_27693:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0eaf24 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x04 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0eaf24; op2val:0x80000000;
op3val:0x827ffff8; valaddr_reg:x3; val_offset:83079*0 + 3*44*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83079*0 + 3*45*FLEN/8, x4, x1, x2)

inst_27694:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0eaf24 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x04 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0eaf24; op2val:0x80000000;
op3val:0x827ffffc; valaddr_reg:x3; val_offset:83082*0 + 3*45*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83082*0 + 3*46*FLEN/8, x4, x1, x2)

inst_27695:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0eaf24 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x04 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0eaf24; op2val:0x80000000;
op3val:0x827ffffe; valaddr_reg:x3; val_offset:83085*0 + 3*46*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83085*0 + 3*47*FLEN/8, x4, x1, x2)

inst_27696:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0eaf24 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x04 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0eaf24; op2val:0x80000000;
op3val:0x827fffff; valaddr_reg:x3; val_offset:83088*0 + 3*47*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83088*0 + 3*48*FLEN/8, x4, x1, x2)

inst_27697:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x3; val_offset:83091*0 + 3*48*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83091*0 + 3*49*FLEN/8, x4, x1, x2)

inst_27698:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x80000003; valaddr_reg:x3; val_offset:83094*0 + 3*49*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83094*0 + 3*50*FLEN/8, x4, x1, x2)

inst_27699:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x80000007; valaddr_reg:x3; val_offset:83097*0 + 3*50*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83097*0 + 3*51*FLEN/8, x4, x1, x2)

inst_27700:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x80199999; valaddr_reg:x3; val_offset:83100*0 + 3*51*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83100*0 + 3*52*FLEN/8, x4, x1, x2)

inst_27701:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x80249249; valaddr_reg:x3; val_offset:83103*0 + 3*52*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83103*0 + 3*53*FLEN/8, x4, x1, x2)

inst_27702:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x80333333; valaddr_reg:x3; val_offset:83106*0 + 3*53*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83106*0 + 3*54*FLEN/8, x4, x1, x2)

inst_27703:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x8036db6d; valaddr_reg:x3; val_offset:83109*0 + 3*54*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83109*0 + 3*55*FLEN/8, x4, x1, x2)

inst_27704:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x803bbbbb; valaddr_reg:x3; val_offset:83112*0 + 3*55*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83112*0 + 3*56*FLEN/8, x4, x1, x2)

inst_27705:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x80444444; valaddr_reg:x3; val_offset:83115*0 + 3*56*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83115*0 + 3*57*FLEN/8, x4, x1, x2)

inst_27706:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x804ccccc; valaddr_reg:x3; val_offset:83118*0 + 3*57*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83118*0 + 3*58*FLEN/8, x4, x1, x2)

inst_27707:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x805b6db6; valaddr_reg:x3; val_offset:83121*0 + 3*58*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83121*0 + 3*59*FLEN/8, x4, x1, x2)

inst_27708:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x80666666; valaddr_reg:x3; val_offset:83124*0 + 3*59*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83124*0 + 3*60*FLEN/8, x4, x1, x2)

inst_27709:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x806db6db; valaddr_reg:x3; val_offset:83127*0 + 3*60*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83127*0 + 3*61*FLEN/8, x4, x1, x2)

inst_27710:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x807ffff8; valaddr_reg:x3; val_offset:83130*0 + 3*61*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83130*0 + 3*62*FLEN/8, x4, x1, x2)

inst_27711:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x807ffffc; valaddr_reg:x3; val_offset:83133*0 + 3*62*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83133*0 + 3*63*FLEN/8, x4, x1, x2)

inst_27712:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x3; val_offset:83136*0 + 3*63*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83136*0 + 3*64*FLEN/8, x4, x1, x2)

inst_27713:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x89800000; valaddr_reg:x3; val_offset:83139*0 + 3*64*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83139*0 + 3*65*FLEN/8, x4, x1, x2)

inst_27714:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x89800001; valaddr_reg:x3; val_offset:83142*0 + 3*65*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83142*0 + 3*66*FLEN/8, x4, x1, x2)

inst_27715:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x89800003; valaddr_reg:x3; val_offset:83145*0 + 3*66*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83145*0 + 3*67*FLEN/8, x4, x1, x2)

inst_27716:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x89800007; valaddr_reg:x3; val_offset:83148*0 + 3*67*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83148*0 + 3*68*FLEN/8, x4, x1, x2)

inst_27717:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x8980000f; valaddr_reg:x3; val_offset:83151*0 + 3*68*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83151*0 + 3*69*FLEN/8, x4, x1, x2)

inst_27718:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x8980001f; valaddr_reg:x3; val_offset:83154*0 + 3*69*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83154*0 + 3*70*FLEN/8, x4, x1, x2)

inst_27719:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x8980003f; valaddr_reg:x3; val_offset:83157*0 + 3*70*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83157*0 + 3*71*FLEN/8, x4, x1, x2)

inst_27720:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x8980007f; valaddr_reg:x3; val_offset:83160*0 + 3*71*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83160*0 + 3*72*FLEN/8, x4, x1, x2)

inst_27721:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x898000ff; valaddr_reg:x3; val_offset:83163*0 + 3*72*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83163*0 + 3*73*FLEN/8, x4, x1, x2)

inst_27722:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x898001ff; valaddr_reg:x3; val_offset:83166*0 + 3*73*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83166*0 + 3*74*FLEN/8, x4, x1, x2)

inst_27723:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x898003ff; valaddr_reg:x3; val_offset:83169*0 + 3*74*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83169*0 + 3*75*FLEN/8, x4, x1, x2)

inst_27724:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x898007ff; valaddr_reg:x3; val_offset:83172*0 + 3*75*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83172*0 + 3*76*FLEN/8, x4, x1, x2)

inst_27725:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x89800fff; valaddr_reg:x3; val_offset:83175*0 + 3*76*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83175*0 + 3*77*FLEN/8, x4, x1, x2)

inst_27726:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x89801fff; valaddr_reg:x3; val_offset:83178*0 + 3*77*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83178*0 + 3*78*FLEN/8, x4, x1, x2)

inst_27727:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x89803fff; valaddr_reg:x3; val_offset:83181*0 + 3*78*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83181*0 + 3*79*FLEN/8, x4, x1, x2)

inst_27728:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x89807fff; valaddr_reg:x3; val_offset:83184*0 + 3*79*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83184*0 + 3*80*FLEN/8, x4, x1, x2)

inst_27729:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x8980ffff; valaddr_reg:x3; val_offset:83187*0 + 3*80*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83187*0 + 3*81*FLEN/8, x4, x1, x2)

inst_27730:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x8981ffff; valaddr_reg:x3; val_offset:83190*0 + 3*81*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83190*0 + 3*82*FLEN/8, x4, x1, x2)

inst_27731:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x8983ffff; valaddr_reg:x3; val_offset:83193*0 + 3*82*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83193*0 + 3*83*FLEN/8, x4, x1, x2)

inst_27732:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x8987ffff; valaddr_reg:x3; val_offset:83196*0 + 3*83*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83196*0 + 3*84*FLEN/8, x4, x1, x2)

inst_27733:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x898fffff; valaddr_reg:x3; val_offset:83199*0 + 3*84*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83199*0 + 3*85*FLEN/8, x4, x1, x2)

inst_27734:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x899fffff; valaddr_reg:x3; val_offset:83202*0 + 3*85*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83202*0 + 3*86*FLEN/8, x4, x1, x2)

inst_27735:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x89bfffff; valaddr_reg:x3; val_offset:83205*0 + 3*86*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83205*0 + 3*87*FLEN/8, x4, x1, x2)

inst_27736:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x89c00000; valaddr_reg:x3; val_offset:83208*0 + 3*87*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83208*0 + 3*88*FLEN/8, x4, x1, x2)

inst_27737:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x89e00000; valaddr_reg:x3; val_offset:83211*0 + 3*88*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83211*0 + 3*89*FLEN/8, x4, x1, x2)

inst_27738:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x89f00000; valaddr_reg:x3; val_offset:83214*0 + 3*89*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83214*0 + 3*90*FLEN/8, x4, x1, x2)

inst_27739:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x89f80000; valaddr_reg:x3; val_offset:83217*0 + 3*90*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83217*0 + 3*91*FLEN/8, x4, x1, x2)

inst_27740:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x89fc0000; valaddr_reg:x3; val_offset:83220*0 + 3*91*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83220*0 + 3*92*FLEN/8, x4, x1, x2)

inst_27741:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x89fe0000; valaddr_reg:x3; val_offset:83223*0 + 3*92*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83223*0 + 3*93*FLEN/8, x4, x1, x2)

inst_27742:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x89ff0000; valaddr_reg:x3; val_offset:83226*0 + 3*93*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83226*0 + 3*94*FLEN/8, x4, x1, x2)

inst_27743:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x89ff8000; valaddr_reg:x3; val_offset:83229*0 + 3*94*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83229*0 + 3*95*FLEN/8, x4, x1, x2)

inst_27744:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x89ffc000; valaddr_reg:x3; val_offset:83232*0 + 3*95*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83232*0 + 3*96*FLEN/8, x4, x1, x2)

inst_27745:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x89ffe000; valaddr_reg:x3; val_offset:83235*0 + 3*96*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83235*0 + 3*97*FLEN/8, x4, x1, x2)

inst_27746:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x89fff000; valaddr_reg:x3; val_offset:83238*0 + 3*97*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83238*0 + 3*98*FLEN/8, x4, x1, x2)

inst_27747:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x89fff800; valaddr_reg:x3; val_offset:83241*0 + 3*98*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83241*0 + 3*99*FLEN/8, x4, x1, x2)

inst_27748:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x89fffc00; valaddr_reg:x3; val_offset:83244*0 + 3*99*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83244*0 + 3*100*FLEN/8, x4, x1, x2)

inst_27749:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x89fffe00; valaddr_reg:x3; val_offset:83247*0 + 3*100*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83247*0 + 3*101*FLEN/8, x4, x1, x2)

inst_27750:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x89ffff00; valaddr_reg:x3; val_offset:83250*0 + 3*101*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83250*0 + 3*102*FLEN/8, x4, x1, x2)

inst_27751:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x89ffff80; valaddr_reg:x3; val_offset:83253*0 + 3*102*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83253*0 + 3*103*FLEN/8, x4, x1, x2)

inst_27752:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x89ffffc0; valaddr_reg:x3; val_offset:83256*0 + 3*103*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83256*0 + 3*104*FLEN/8, x4, x1, x2)

inst_27753:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x89ffffe0; valaddr_reg:x3; val_offset:83259*0 + 3*104*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83259*0 + 3*105*FLEN/8, x4, x1, x2)

inst_27754:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x89fffff0; valaddr_reg:x3; val_offset:83262*0 + 3*105*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83262*0 + 3*106*FLEN/8, x4, x1, x2)

inst_27755:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x89fffff8; valaddr_reg:x3; val_offset:83265*0 + 3*106*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83265*0 + 3*107*FLEN/8, x4, x1, x2)

inst_27756:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x89fffffc; valaddr_reg:x3; val_offset:83268*0 + 3*107*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83268*0 + 3*108*FLEN/8, x4, x1, x2)

inst_27757:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x89fffffe; valaddr_reg:x3; val_offset:83271*0 + 3*108*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83271*0 + 3*109*FLEN/8, x4, x1, x2)

inst_27758:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ecbd9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x13 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ecbd9; op2val:0x80000000;
op3val:0x89ffffff; valaddr_reg:x3; val_offset:83274*0 + 3*109*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83274*0 + 3*110*FLEN/8, x4, x1, x2)

inst_27759:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6e800000; valaddr_reg:x3; val_offset:83277*0 + 3*110*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83277*0 + 3*111*FLEN/8, x4, x1, x2)

inst_27760:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6e800001; valaddr_reg:x3; val_offset:83280*0 + 3*111*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83280*0 + 3*112*FLEN/8, x4, x1, x2)

inst_27761:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6e800003; valaddr_reg:x3; val_offset:83283*0 + 3*112*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83283*0 + 3*113*FLEN/8, x4, x1, x2)

inst_27762:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6e800007; valaddr_reg:x3; val_offset:83286*0 + 3*113*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83286*0 + 3*114*FLEN/8, x4, x1, x2)

inst_27763:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6e80000f; valaddr_reg:x3; val_offset:83289*0 + 3*114*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83289*0 + 3*115*FLEN/8, x4, x1, x2)

inst_27764:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6e80001f; valaddr_reg:x3; val_offset:83292*0 + 3*115*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83292*0 + 3*116*FLEN/8, x4, x1, x2)

inst_27765:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6e80003f; valaddr_reg:x3; val_offset:83295*0 + 3*116*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83295*0 + 3*117*FLEN/8, x4, x1, x2)

inst_27766:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6e80007f; valaddr_reg:x3; val_offset:83298*0 + 3*117*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83298*0 + 3*118*FLEN/8, x4, x1, x2)

inst_27767:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6e8000ff; valaddr_reg:x3; val_offset:83301*0 + 3*118*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83301*0 + 3*119*FLEN/8, x4, x1, x2)

inst_27768:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6e8001ff; valaddr_reg:x3; val_offset:83304*0 + 3*119*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83304*0 + 3*120*FLEN/8, x4, x1, x2)

inst_27769:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6e8003ff; valaddr_reg:x3; val_offset:83307*0 + 3*120*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83307*0 + 3*121*FLEN/8, x4, x1, x2)

inst_27770:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6e8007ff; valaddr_reg:x3; val_offset:83310*0 + 3*121*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83310*0 + 3*122*FLEN/8, x4, x1, x2)

inst_27771:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6e800fff; valaddr_reg:x3; val_offset:83313*0 + 3*122*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83313*0 + 3*123*FLEN/8, x4, x1, x2)

inst_27772:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6e801fff; valaddr_reg:x3; val_offset:83316*0 + 3*123*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83316*0 + 3*124*FLEN/8, x4, x1, x2)

inst_27773:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6e803fff; valaddr_reg:x3; val_offset:83319*0 + 3*124*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83319*0 + 3*125*FLEN/8, x4, x1, x2)

inst_27774:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6e807fff; valaddr_reg:x3; val_offset:83322*0 + 3*125*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83322*0 + 3*126*FLEN/8, x4, x1, x2)

inst_27775:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6e80ffff; valaddr_reg:x3; val_offset:83325*0 + 3*126*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83325*0 + 3*127*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_2)

inst_27776:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6e81ffff; valaddr_reg:x3; val_offset:83328*0 + 3*127*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83328*0 + 3*128*FLEN/8, x4, x1, x2)

inst_27777:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6e83ffff; valaddr_reg:x3; val_offset:83331*0 + 3*128*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83331*0 + 3*129*FLEN/8, x4, x1, x2)

inst_27778:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6e87ffff; valaddr_reg:x3; val_offset:83334*0 + 3*129*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83334*0 + 3*130*FLEN/8, x4, x1, x2)

inst_27779:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6e8fffff; valaddr_reg:x3; val_offset:83337*0 + 3*130*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83337*0 + 3*131*FLEN/8, x4, x1, x2)

inst_27780:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6e9fffff; valaddr_reg:x3; val_offset:83340*0 + 3*131*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83340*0 + 3*132*FLEN/8, x4, x1, x2)

inst_27781:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6ebfffff; valaddr_reg:x3; val_offset:83343*0 + 3*132*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83343*0 + 3*133*FLEN/8, x4, x1, x2)

inst_27782:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6ec00000; valaddr_reg:x3; val_offset:83346*0 + 3*133*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83346*0 + 3*134*FLEN/8, x4, x1, x2)

inst_27783:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6ee00000; valaddr_reg:x3; val_offset:83349*0 + 3*134*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83349*0 + 3*135*FLEN/8, x4, x1, x2)

inst_27784:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6ef00000; valaddr_reg:x3; val_offset:83352*0 + 3*135*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83352*0 + 3*136*FLEN/8, x4, x1, x2)

inst_27785:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6ef80000; valaddr_reg:x3; val_offset:83355*0 + 3*136*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83355*0 + 3*137*FLEN/8, x4, x1, x2)

inst_27786:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6efc0000; valaddr_reg:x3; val_offset:83358*0 + 3*137*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83358*0 + 3*138*FLEN/8, x4, x1, x2)

inst_27787:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6efe0000; valaddr_reg:x3; val_offset:83361*0 + 3*138*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83361*0 + 3*139*FLEN/8, x4, x1, x2)

inst_27788:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6eff0000; valaddr_reg:x3; val_offset:83364*0 + 3*139*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83364*0 + 3*140*FLEN/8, x4, x1, x2)

inst_27789:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6eff8000; valaddr_reg:x3; val_offset:83367*0 + 3*140*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83367*0 + 3*141*FLEN/8, x4, x1, x2)

inst_27790:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6effc000; valaddr_reg:x3; val_offset:83370*0 + 3*141*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83370*0 + 3*142*FLEN/8, x4, x1, x2)

inst_27791:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6effe000; valaddr_reg:x3; val_offset:83373*0 + 3*142*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83373*0 + 3*143*FLEN/8, x4, x1, x2)

inst_27792:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6efff000; valaddr_reg:x3; val_offset:83376*0 + 3*143*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83376*0 + 3*144*FLEN/8, x4, x1, x2)

inst_27793:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6efff800; valaddr_reg:x3; val_offset:83379*0 + 3*144*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83379*0 + 3*145*FLEN/8, x4, x1, x2)

inst_27794:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6efffc00; valaddr_reg:x3; val_offset:83382*0 + 3*145*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83382*0 + 3*146*FLEN/8, x4, x1, x2)

inst_27795:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6efffe00; valaddr_reg:x3; val_offset:83385*0 + 3*146*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83385*0 + 3*147*FLEN/8, x4, x1, x2)

inst_27796:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6effff00; valaddr_reg:x3; val_offset:83388*0 + 3*147*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83388*0 + 3*148*FLEN/8, x4, x1, x2)

inst_27797:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6effff80; valaddr_reg:x3; val_offset:83391*0 + 3*148*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83391*0 + 3*149*FLEN/8, x4, x1, x2)

inst_27798:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6effffc0; valaddr_reg:x3; val_offset:83394*0 + 3*149*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83394*0 + 3*150*FLEN/8, x4, x1, x2)

inst_27799:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6effffe0; valaddr_reg:x3; val_offset:83397*0 + 3*150*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83397*0 + 3*151*FLEN/8, x4, x1, x2)

inst_27800:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6efffff0; valaddr_reg:x3; val_offset:83400*0 + 3*151*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83400*0 + 3*152*FLEN/8, x4, x1, x2)

inst_27801:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6efffff8; valaddr_reg:x3; val_offset:83403*0 + 3*152*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83403*0 + 3*153*FLEN/8, x4, x1, x2)

inst_27802:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6efffffc; valaddr_reg:x3; val_offset:83406*0 + 3*153*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83406*0 + 3*154*FLEN/8, x4, x1, x2)

inst_27803:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6efffffe; valaddr_reg:x3; val_offset:83409*0 + 3*154*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83409*0 + 3*155*FLEN/8, x4, x1, x2)

inst_27804:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6effffff; valaddr_reg:x3; val_offset:83412*0 + 3*155*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83412*0 + 3*156*FLEN/8, x4, x1, x2)

inst_27805:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x7f000001; valaddr_reg:x3; val_offset:83415*0 + 3*156*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83415*0 + 3*157*FLEN/8, x4, x1, x2)

inst_27806:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x7f000003; valaddr_reg:x3; val_offset:83418*0 + 3*157*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83418*0 + 3*158*FLEN/8, x4, x1, x2)

inst_27807:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x7f000007; valaddr_reg:x3; val_offset:83421*0 + 3*158*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83421*0 + 3*159*FLEN/8, x4, x1, x2)

inst_27808:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x7f199999; valaddr_reg:x3; val_offset:83424*0 + 3*159*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83424*0 + 3*160*FLEN/8, x4, x1, x2)

inst_27809:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x7f249249; valaddr_reg:x3; val_offset:83427*0 + 3*160*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83427*0 + 3*161*FLEN/8, x4, x1, x2)

inst_27810:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x7f333333; valaddr_reg:x3; val_offset:83430*0 + 3*161*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83430*0 + 3*162*FLEN/8, x4, x1, x2)

inst_27811:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x7f36db6d; valaddr_reg:x3; val_offset:83433*0 + 3*162*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83433*0 + 3*163*FLEN/8, x4, x1, x2)

inst_27812:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x7f3bbbbb; valaddr_reg:x3; val_offset:83436*0 + 3*163*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83436*0 + 3*164*FLEN/8, x4, x1, x2)

inst_27813:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x7f444444; valaddr_reg:x3; val_offset:83439*0 + 3*164*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83439*0 + 3*165*FLEN/8, x4, x1, x2)

inst_27814:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x7f4ccccc; valaddr_reg:x3; val_offset:83442*0 + 3*165*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83442*0 + 3*166*FLEN/8, x4, x1, x2)

inst_27815:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x7f5b6db6; valaddr_reg:x3; val_offset:83445*0 + 3*166*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83445*0 + 3*167*FLEN/8, x4, x1, x2)

inst_27816:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x7f666666; valaddr_reg:x3; val_offset:83448*0 + 3*167*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83448*0 + 3*168*FLEN/8, x4, x1, x2)

inst_27817:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x7f6db6db; valaddr_reg:x3; val_offset:83451*0 + 3*168*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83451*0 + 3*169*FLEN/8, x4, x1, x2)

inst_27818:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x7f7ffff8; valaddr_reg:x3; val_offset:83454*0 + 3*169*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83454*0 + 3*170*FLEN/8, x4, x1, x2)

inst_27819:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x7f7ffffc; valaddr_reg:x3; val_offset:83457*0 + 3*170*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83457*0 + 3*171*FLEN/8, x4, x1, x2)

inst_27820:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x7f7ffffe; valaddr_reg:x3; val_offset:83460*0 + 3*171*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83460*0 + 3*172*FLEN/8, x4, x1, x2)

inst_27821:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xee and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x77000000; valaddr_reg:x3; val_offset:83463*0 + 3*172*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83463*0 + 3*173*FLEN/8, x4, x1, x2)

inst_27822:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xee and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x77000001; valaddr_reg:x3; val_offset:83466*0 + 3*173*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83466*0 + 3*174*FLEN/8, x4, x1, x2)

inst_27823:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xee and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x77000003; valaddr_reg:x3; val_offset:83469*0 + 3*174*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83469*0 + 3*175*FLEN/8, x4, x1, x2)

inst_27824:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xee and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x77000007; valaddr_reg:x3; val_offset:83472*0 + 3*175*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83472*0 + 3*176*FLEN/8, x4, x1, x2)

inst_27825:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xee and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x7700000f; valaddr_reg:x3; val_offset:83475*0 + 3*176*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83475*0 + 3*177*FLEN/8, x4, x1, x2)

inst_27826:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xee and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x7700001f; valaddr_reg:x3; val_offset:83478*0 + 3*177*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83478*0 + 3*178*FLEN/8, x4, x1, x2)

inst_27827:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xee and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x7700003f; valaddr_reg:x3; val_offset:83481*0 + 3*178*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83481*0 + 3*179*FLEN/8, x4, x1, x2)

inst_27828:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xee and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x7700007f; valaddr_reg:x3; val_offset:83484*0 + 3*179*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83484*0 + 3*180*FLEN/8, x4, x1, x2)

inst_27829:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xee and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x770000ff; valaddr_reg:x3; val_offset:83487*0 + 3*180*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83487*0 + 3*181*FLEN/8, x4, x1, x2)

inst_27830:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xee and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x770001ff; valaddr_reg:x3; val_offset:83490*0 + 3*181*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83490*0 + 3*182*FLEN/8, x4, x1, x2)

inst_27831:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xee and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x770003ff; valaddr_reg:x3; val_offset:83493*0 + 3*182*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83493*0 + 3*183*FLEN/8, x4, x1, x2)

inst_27832:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xee and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x770007ff; valaddr_reg:x3; val_offset:83496*0 + 3*183*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83496*0 + 3*184*FLEN/8, x4, x1, x2)

inst_27833:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xee and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x77000fff; valaddr_reg:x3; val_offset:83499*0 + 3*184*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83499*0 + 3*185*FLEN/8, x4, x1, x2)

inst_27834:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xee and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x77001fff; valaddr_reg:x3; val_offset:83502*0 + 3*185*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83502*0 + 3*186*FLEN/8, x4, x1, x2)

inst_27835:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xee and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x77003fff; valaddr_reg:x3; val_offset:83505*0 + 3*186*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83505*0 + 3*187*FLEN/8, x4, x1, x2)

inst_27836:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xee and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x77007fff; valaddr_reg:x3; val_offset:83508*0 + 3*187*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83508*0 + 3*188*FLEN/8, x4, x1, x2)

inst_27837:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xee and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x7700ffff; valaddr_reg:x3; val_offset:83511*0 + 3*188*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83511*0 + 3*189*FLEN/8, x4, x1, x2)

inst_27838:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xee and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x7701ffff; valaddr_reg:x3; val_offset:83514*0 + 3*189*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83514*0 + 3*190*FLEN/8, x4, x1, x2)

inst_27839:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xee and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x7703ffff; valaddr_reg:x3; val_offset:83517*0 + 3*190*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83517*0 + 3*191*FLEN/8, x4, x1, x2)

inst_27840:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xee and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x7707ffff; valaddr_reg:x3; val_offset:83520*0 + 3*191*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83520*0 + 3*192*FLEN/8, x4, x1, x2)

inst_27841:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xee and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x770fffff; valaddr_reg:x3; val_offset:83523*0 + 3*192*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83523*0 + 3*193*FLEN/8, x4, x1, x2)

inst_27842:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xee and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x771fffff; valaddr_reg:x3; val_offset:83526*0 + 3*193*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83526*0 + 3*194*FLEN/8, x4, x1, x2)

inst_27843:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xee and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x773fffff; valaddr_reg:x3; val_offset:83529*0 + 3*194*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83529*0 + 3*195*FLEN/8, x4, x1, x2)

inst_27844:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xee and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x77400000; valaddr_reg:x3; val_offset:83532*0 + 3*195*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83532*0 + 3*196*FLEN/8, x4, x1, x2)

inst_27845:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xee and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x77600000; valaddr_reg:x3; val_offset:83535*0 + 3*196*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83535*0 + 3*197*FLEN/8, x4, x1, x2)

inst_27846:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xee and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x77700000; valaddr_reg:x3; val_offset:83538*0 + 3*197*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83538*0 + 3*198*FLEN/8, x4, x1, x2)

inst_27847:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xee and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x77780000; valaddr_reg:x3; val_offset:83541*0 + 3*198*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83541*0 + 3*199*FLEN/8, x4, x1, x2)

inst_27848:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xee and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x777c0000; valaddr_reg:x3; val_offset:83544*0 + 3*199*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83544*0 + 3*200*FLEN/8, x4, x1, x2)

inst_27849:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xee and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x777e0000; valaddr_reg:x3; val_offset:83547*0 + 3*200*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83547*0 + 3*201*FLEN/8, x4, x1, x2)

inst_27850:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xee and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x777f0000; valaddr_reg:x3; val_offset:83550*0 + 3*201*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83550*0 + 3*202*FLEN/8, x4, x1, x2)

inst_27851:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xee and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x777f8000; valaddr_reg:x3; val_offset:83553*0 + 3*202*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83553*0 + 3*203*FLEN/8, x4, x1, x2)

inst_27852:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xee and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x777fc000; valaddr_reg:x3; val_offset:83556*0 + 3*203*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83556*0 + 3*204*FLEN/8, x4, x1, x2)

inst_27853:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xee and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x777fe000; valaddr_reg:x3; val_offset:83559*0 + 3*204*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83559*0 + 3*205*FLEN/8, x4, x1, x2)

inst_27854:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xee and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x777ff000; valaddr_reg:x3; val_offset:83562*0 + 3*205*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83562*0 + 3*206*FLEN/8, x4, x1, x2)

inst_27855:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xee and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x777ff800; valaddr_reg:x3; val_offset:83565*0 + 3*206*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83565*0 + 3*207*FLEN/8, x4, x1, x2)

inst_27856:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xee and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x777ffc00; valaddr_reg:x3; val_offset:83568*0 + 3*207*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83568*0 + 3*208*FLEN/8, x4, x1, x2)

inst_27857:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xee and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x777ffe00; valaddr_reg:x3; val_offset:83571*0 + 3*208*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83571*0 + 3*209*FLEN/8, x4, x1, x2)

inst_27858:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xee and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x777fff00; valaddr_reg:x3; val_offset:83574*0 + 3*209*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83574*0 + 3*210*FLEN/8, x4, x1, x2)

inst_27859:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xee and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x777fff80; valaddr_reg:x3; val_offset:83577*0 + 3*210*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83577*0 + 3*211*FLEN/8, x4, x1, x2)

inst_27860:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xee and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x777fffc0; valaddr_reg:x3; val_offset:83580*0 + 3*211*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83580*0 + 3*212*FLEN/8, x4, x1, x2)

inst_27861:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xee and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x777fffe0; valaddr_reg:x3; val_offset:83583*0 + 3*212*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83583*0 + 3*213*FLEN/8, x4, x1, x2)

inst_27862:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xee and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x777ffff0; valaddr_reg:x3; val_offset:83586*0 + 3*213*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83586*0 + 3*214*FLEN/8, x4, x1, x2)

inst_27863:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xee and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x777ffff8; valaddr_reg:x3; val_offset:83589*0 + 3*214*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83589*0 + 3*215*FLEN/8, x4, x1, x2)

inst_27864:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xee and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x777ffffc; valaddr_reg:x3; val_offset:83592*0 + 3*215*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83592*0 + 3*216*FLEN/8, x4, x1, x2)

inst_27865:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xee and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x777ffffe; valaddr_reg:x3; val_offset:83595*0 + 3*216*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83595*0 + 3*217*FLEN/8, x4, x1, x2)

inst_27866:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xee and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x777fffff; valaddr_reg:x3; val_offset:83598*0 + 3*217*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83598*0 + 3*218*FLEN/8, x4, x1, x2)

inst_27867:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x7f000001; valaddr_reg:x3; val_offset:83601*0 + 3*218*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83601*0 + 3*219*FLEN/8, x4, x1, x2)

inst_27868:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x7f000003; valaddr_reg:x3; val_offset:83604*0 + 3*219*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83604*0 + 3*220*FLEN/8, x4, x1, x2)

inst_27869:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x7f000007; valaddr_reg:x3; val_offset:83607*0 + 3*220*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83607*0 + 3*221*FLEN/8, x4, x1, x2)

inst_27870:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x7f199999; valaddr_reg:x3; val_offset:83610*0 + 3*221*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83610*0 + 3*222*FLEN/8, x4, x1, x2)

inst_27871:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x7f249249; valaddr_reg:x3; val_offset:83613*0 + 3*222*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83613*0 + 3*223*FLEN/8, x4, x1, x2)

inst_27872:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x7f333333; valaddr_reg:x3; val_offset:83616*0 + 3*223*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83616*0 + 3*224*FLEN/8, x4, x1, x2)

inst_27873:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x7f36db6d; valaddr_reg:x3; val_offset:83619*0 + 3*224*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83619*0 + 3*225*FLEN/8, x4, x1, x2)

inst_27874:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x7f3bbbbb; valaddr_reg:x3; val_offset:83622*0 + 3*225*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83622*0 + 3*226*FLEN/8, x4, x1, x2)

inst_27875:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x7f444444; valaddr_reg:x3; val_offset:83625*0 + 3*226*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83625*0 + 3*227*FLEN/8, x4, x1, x2)

inst_27876:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x7f4ccccc; valaddr_reg:x3; val_offset:83628*0 + 3*227*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83628*0 + 3*228*FLEN/8, x4, x1, x2)

inst_27877:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x7f5b6db6; valaddr_reg:x3; val_offset:83631*0 + 3*228*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83631*0 + 3*229*FLEN/8, x4, x1, x2)

inst_27878:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x7f666666; valaddr_reg:x3; val_offset:83634*0 + 3*229*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83634*0 + 3*230*FLEN/8, x4, x1, x2)

inst_27879:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x7f6db6db; valaddr_reg:x3; val_offset:83637*0 + 3*230*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83637*0 + 3*231*FLEN/8, x4, x1, x2)

inst_27880:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x7f7ffff8; valaddr_reg:x3; val_offset:83640*0 + 3*231*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83640*0 + 3*232*FLEN/8, x4, x1, x2)

inst_27881:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x7f7ffffc; valaddr_reg:x3; val_offset:83643*0 + 3*232*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83643*0 + 3*233*FLEN/8, x4, x1, x2)

inst_27882:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f3001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x64d8c4 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f3001; op2val:0x3fe4d8c4;
op3val:0x7f7ffffe; valaddr_reg:x3; val_offset:83646*0 + 3*233*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83646*0 + 3*234*FLEN/8, x4, x1, x2)

inst_27883:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x1; valaddr_reg:x3; val_offset:83649*0 + 3*234*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83649*0 + 3*235*FLEN/8, x4, x1, x2)

inst_27884:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x3; valaddr_reg:x3; val_offset:83652*0 + 3*235*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83652*0 + 3*236*FLEN/8, x4, x1, x2)

inst_27885:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x7; valaddr_reg:x3; val_offset:83655*0 + 3*236*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83655*0 + 3*237*FLEN/8, x4, x1, x2)

inst_27886:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x199999; valaddr_reg:x3; val_offset:83658*0 + 3*237*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83658*0 + 3*238*FLEN/8, x4, x1, x2)

inst_27887:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x249249; valaddr_reg:x3; val_offset:83661*0 + 3*238*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83661*0 + 3*239*FLEN/8, x4, x1, x2)

inst_27888:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x333333; valaddr_reg:x3; val_offset:83664*0 + 3*239*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83664*0 + 3*240*FLEN/8, x4, x1, x2)

inst_27889:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x36db6d; valaddr_reg:x3; val_offset:83667*0 + 3*240*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83667*0 + 3*241*FLEN/8, x4, x1, x2)

inst_27890:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x3bbbbb; valaddr_reg:x3; val_offset:83670*0 + 3*241*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83670*0 + 3*242*FLEN/8, x4, x1, x2)

inst_27891:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x444444; valaddr_reg:x3; val_offset:83673*0 + 3*242*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83673*0 + 3*243*FLEN/8, x4, x1, x2)

inst_27892:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x4ccccc; valaddr_reg:x3; val_offset:83676*0 + 3*243*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83676*0 + 3*244*FLEN/8, x4, x1, x2)

inst_27893:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x5b6db6; valaddr_reg:x3; val_offset:83679*0 + 3*244*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83679*0 + 3*245*FLEN/8, x4, x1, x2)

inst_27894:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x666666; valaddr_reg:x3; val_offset:83682*0 + 3*245*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83682*0 + 3*246*FLEN/8, x4, x1, x2)

inst_27895:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x6db6db; valaddr_reg:x3; val_offset:83685*0 + 3*246*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83685*0 + 3*247*FLEN/8, x4, x1, x2)

inst_27896:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x7ffff8; valaddr_reg:x3; val_offset:83688*0 + 3*247*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83688*0 + 3*248*FLEN/8, x4, x1, x2)

inst_27897:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x7ffffc; valaddr_reg:x3; val_offset:83691*0 + 3*248*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83691*0 + 3*249*FLEN/8, x4, x1, x2)

inst_27898:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x7ffffe; valaddr_reg:x3; val_offset:83694*0 + 3*249*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83694*0 + 3*250*FLEN/8, x4, x1, x2)

inst_27899:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x4000000; valaddr_reg:x3; val_offset:83697*0 + 3*250*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83697*0 + 3*251*FLEN/8, x4, x1, x2)

inst_27900:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x4000001; valaddr_reg:x3; val_offset:83700*0 + 3*251*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83700*0 + 3*252*FLEN/8, x4, x1, x2)

inst_27901:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x4000003; valaddr_reg:x3; val_offset:83703*0 + 3*252*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83703*0 + 3*253*FLEN/8, x4, x1, x2)

inst_27902:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x4000007; valaddr_reg:x3; val_offset:83706*0 + 3*253*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83706*0 + 3*254*FLEN/8, x4, x1, x2)

inst_27903:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x400000f; valaddr_reg:x3; val_offset:83709*0 + 3*254*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83709*0 + 3*255*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_3)

inst_27904:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x400001f; valaddr_reg:x3; val_offset:83712*0 + 3*256*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83712*0 + 3*256*FLEN/8, x4, x1, x2)

inst_27905:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x400003f; valaddr_reg:x3; val_offset:83715*0 + 3*257*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83715*0 + 3*257*FLEN/8, x4, x1, x2)

inst_27906:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x400007f; valaddr_reg:x3; val_offset:83718*0 + 3*258*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83718*0 + 3*258*FLEN/8, x4, x1, x2)

inst_27907:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x40000ff; valaddr_reg:x3; val_offset:83721*0 + 3*259*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83721*0 + 3*259*FLEN/8, x4, x1, x2)

inst_27908:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x40001ff; valaddr_reg:x3; val_offset:83724*0 + 3*260*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83724*0 + 3*260*FLEN/8, x4, x1, x2)

inst_27909:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x40003ff; valaddr_reg:x3; val_offset:83727*0 + 3*261*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83727*0 + 3*261*FLEN/8, x4, x1, x2)

inst_27910:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x40007ff; valaddr_reg:x3; val_offset:83730*0 + 3*262*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83730*0 + 3*262*FLEN/8, x4, x1, x2)

inst_27911:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x4000fff; valaddr_reg:x3; val_offset:83733*0 + 3*263*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83733*0 + 3*263*FLEN/8, x4, x1, x2)

inst_27912:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x4001fff; valaddr_reg:x3; val_offset:83736*0 + 3*264*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83736*0 + 3*264*FLEN/8, x4, x1, x2)

inst_27913:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x4003fff; valaddr_reg:x3; val_offset:83739*0 + 3*265*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83739*0 + 3*265*FLEN/8, x4, x1, x2)

inst_27914:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x4007fff; valaddr_reg:x3; val_offset:83742*0 + 3*266*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83742*0 + 3*266*FLEN/8, x4, x1, x2)

inst_27915:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x400ffff; valaddr_reg:x3; val_offset:83745*0 + 3*267*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83745*0 + 3*267*FLEN/8, x4, x1, x2)

inst_27916:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x401ffff; valaddr_reg:x3; val_offset:83748*0 + 3*268*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83748*0 + 3*268*FLEN/8, x4, x1, x2)

inst_27917:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x403ffff; valaddr_reg:x3; val_offset:83751*0 + 3*269*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83751*0 + 3*269*FLEN/8, x4, x1, x2)

inst_27918:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x407ffff; valaddr_reg:x3; val_offset:83754*0 + 3*270*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83754*0 + 3*270*FLEN/8, x4, x1, x2)

inst_27919:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x40fffff; valaddr_reg:x3; val_offset:83757*0 + 3*271*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83757*0 + 3*271*FLEN/8, x4, x1, x2)

inst_27920:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x41fffff; valaddr_reg:x3; val_offset:83760*0 + 3*272*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83760*0 + 3*272*FLEN/8, x4, x1, x2)

inst_27921:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x43fffff; valaddr_reg:x3; val_offset:83763*0 + 3*273*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83763*0 + 3*273*FLEN/8, x4, x1, x2)

inst_27922:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x4400000; valaddr_reg:x3; val_offset:83766*0 + 3*274*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83766*0 + 3*274*FLEN/8, x4, x1, x2)

inst_27923:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x4600000; valaddr_reg:x3; val_offset:83769*0 + 3*275*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83769*0 + 3*275*FLEN/8, x4, x1, x2)

inst_27924:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x4700000; valaddr_reg:x3; val_offset:83772*0 + 3*276*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83772*0 + 3*276*FLEN/8, x4, x1, x2)

inst_27925:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x4780000; valaddr_reg:x3; val_offset:83775*0 + 3*277*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83775*0 + 3*277*FLEN/8, x4, x1, x2)

inst_27926:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x47c0000; valaddr_reg:x3; val_offset:83778*0 + 3*278*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83778*0 + 3*278*FLEN/8, x4, x1, x2)

inst_27927:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x47e0000; valaddr_reg:x3; val_offset:83781*0 + 3*279*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83781*0 + 3*279*FLEN/8, x4, x1, x2)

inst_27928:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x47f0000; valaddr_reg:x3; val_offset:83784*0 + 3*280*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83784*0 + 3*280*FLEN/8, x4, x1, x2)

inst_27929:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x47f8000; valaddr_reg:x3; val_offset:83787*0 + 3*281*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83787*0 + 3*281*FLEN/8, x4, x1, x2)

inst_27930:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x47fc000; valaddr_reg:x3; val_offset:83790*0 + 3*282*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83790*0 + 3*282*FLEN/8, x4, x1, x2)

inst_27931:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x47fe000; valaddr_reg:x3; val_offset:83793*0 + 3*283*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83793*0 + 3*283*FLEN/8, x4, x1, x2)

inst_27932:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x47ff000; valaddr_reg:x3; val_offset:83796*0 + 3*284*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83796*0 + 3*284*FLEN/8, x4, x1, x2)

inst_27933:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x47ff800; valaddr_reg:x3; val_offset:83799*0 + 3*285*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83799*0 + 3*285*FLEN/8, x4, x1, x2)

inst_27934:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x47ffc00; valaddr_reg:x3; val_offset:83802*0 + 3*286*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83802*0 + 3*286*FLEN/8, x4, x1, x2)

inst_27935:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x47ffe00; valaddr_reg:x3; val_offset:83805*0 + 3*287*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83805*0 + 3*287*FLEN/8, x4, x1, x2)

inst_27936:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x47fff00; valaddr_reg:x3; val_offset:83808*0 + 3*288*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83808*0 + 3*288*FLEN/8, x4, x1, x2)

inst_27937:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x47fff80; valaddr_reg:x3; val_offset:83811*0 + 3*289*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83811*0 + 3*289*FLEN/8, x4, x1, x2)

inst_27938:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x47fffc0; valaddr_reg:x3; val_offset:83814*0 + 3*290*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83814*0 + 3*290*FLEN/8, x4, x1, x2)

inst_27939:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x47fffe0; valaddr_reg:x3; val_offset:83817*0 + 3*291*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83817*0 + 3*291*FLEN/8, x4, x1, x2)

inst_27940:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x47ffff0; valaddr_reg:x3; val_offset:83820*0 + 3*292*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83820*0 + 3*292*FLEN/8, x4, x1, x2)

inst_27941:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x47ffff8; valaddr_reg:x3; val_offset:83823*0 + 3*293*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83823*0 + 3*293*FLEN/8, x4, x1, x2)

inst_27942:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x47ffffc; valaddr_reg:x3; val_offset:83826*0 + 3*294*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83826*0 + 3*294*FLEN/8, x4, x1, x2)

inst_27943:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x47ffffe; valaddr_reg:x3; val_offset:83829*0 + 3*295*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83829*0 + 3*295*FLEN/8, x4, x1, x2)

inst_27944:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f447a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f447a; op2val:0x0;
op3val:0x47fffff; valaddr_reg:x3; val_offset:83832*0 + 3*296*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83832*0 + 3*296*FLEN/8, x4, x1, x2)

inst_27945:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f7994 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x646369 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f7994; op2val:0x3fe46369;
op3val:0x7f000001; valaddr_reg:x3; val_offset:83835*0 + 3*297*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83835*0 + 3*297*FLEN/8, x4, x1, x2)

inst_27946:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f7994 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x646369 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f7994; op2val:0x3fe46369;
op3val:0x7f000003; valaddr_reg:x3; val_offset:83838*0 + 3*298*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83838*0 + 3*298*FLEN/8, x4, x1, x2)

inst_27947:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f7994 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x646369 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f7994; op2val:0x3fe46369;
op3val:0x7f000007; valaddr_reg:x3; val_offset:83841*0 + 3*299*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83841*0 + 3*299*FLEN/8, x4, x1, x2)

inst_27948:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f7994 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x646369 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f7994; op2val:0x3fe46369;
op3val:0x7f199999; valaddr_reg:x3; val_offset:83844*0 + 3*300*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83844*0 + 3*300*FLEN/8, x4, x1, x2)

inst_27949:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f7994 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x646369 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f7994; op2val:0x3fe46369;
op3val:0x7f249249; valaddr_reg:x3; val_offset:83847*0 + 3*301*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83847*0 + 3*301*FLEN/8, x4, x1, x2)

inst_27950:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f7994 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x646369 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f7994; op2val:0x3fe46369;
op3val:0x7f333333; valaddr_reg:x3; val_offset:83850*0 + 3*302*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83850*0 + 3*302*FLEN/8, x4, x1, x2)

inst_27951:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f7994 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x646369 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f7994; op2val:0x3fe46369;
op3val:0x7f36db6d; valaddr_reg:x3; val_offset:83853*0 + 3*303*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83853*0 + 3*303*FLEN/8, x4, x1, x2)

inst_27952:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f7994 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x646369 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f7994; op2val:0x3fe46369;
op3val:0x7f3bbbbb; valaddr_reg:x3; val_offset:83856*0 + 3*304*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83856*0 + 3*304*FLEN/8, x4, x1, x2)

inst_27953:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f7994 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x646369 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f7994; op2val:0x3fe46369;
op3val:0x7f444444; valaddr_reg:x3; val_offset:83859*0 + 3*305*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83859*0 + 3*305*FLEN/8, x4, x1, x2)

inst_27954:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f7994 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x646369 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f7994; op2val:0x3fe46369;
op3val:0x7f4ccccc; valaddr_reg:x3; val_offset:83862*0 + 3*306*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83862*0 + 3*306*FLEN/8, x4, x1, x2)

inst_27955:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f7994 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x646369 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f7994; op2val:0x3fe46369;
op3val:0x7f5b6db6; valaddr_reg:x3; val_offset:83865*0 + 3*307*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83865*0 + 3*307*FLEN/8, x4, x1, x2)

inst_27956:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f7994 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x646369 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f7994; op2val:0x3fe46369;
op3val:0x7f666666; valaddr_reg:x3; val_offset:83868*0 + 3*308*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83868*0 + 3*308*FLEN/8, x4, x1, x2)

inst_27957:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f7994 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x646369 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f7994; op2val:0x3fe46369;
op3val:0x7f6db6db; valaddr_reg:x3; val_offset:83871*0 + 3*309*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83871*0 + 3*309*FLEN/8, x4, x1, x2)

inst_27958:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f7994 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x646369 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f7994; op2val:0x3fe46369;
op3val:0x7f7ffff8; valaddr_reg:x3; val_offset:83874*0 + 3*310*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83874*0 + 3*310*FLEN/8, x4, x1, x2)

inst_27959:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f7994 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x646369 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f7994; op2val:0x3fe46369;
op3val:0x7f7ffffc; valaddr_reg:x3; val_offset:83877*0 + 3*311*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83877*0 + 3*311*FLEN/8, x4, x1, x2)

inst_27960:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f7994 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x646369 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f7994; op2val:0x3fe46369;
op3val:0x7f7ffffe; valaddr_reg:x3; val_offset:83880*0 + 3*312*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83880*0 + 3*312*FLEN/8, x4, x1, x2)

inst_27961:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0f7994 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x646369 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0f7994; op2val:0x3fe46369;
op3val:0x7f7fffff; valaddr_reg:x3; val_offset:83883*0 + 3*313*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83883*0 + 3*313*FLEN/8, x4, x1, x2)

inst_27962:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xec and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x76000000; valaddr_reg:x3; val_offset:83886*0 + 3*314*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83886*0 + 3*314*FLEN/8, x4, x1, x2)

inst_27963:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xec and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x76000001; valaddr_reg:x3; val_offset:83889*0 + 3*315*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83889*0 + 3*315*FLEN/8, x4, x1, x2)

inst_27964:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xec and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x76000003; valaddr_reg:x3; val_offset:83892*0 + 3*316*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83892*0 + 3*316*FLEN/8, x4, x1, x2)

inst_27965:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xec and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x76000007; valaddr_reg:x3; val_offset:83895*0 + 3*317*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83895*0 + 3*317*FLEN/8, x4, x1, x2)

inst_27966:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xec and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x7600000f; valaddr_reg:x3; val_offset:83898*0 + 3*318*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83898*0 + 3*318*FLEN/8, x4, x1, x2)

inst_27967:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xec and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x7600001f; valaddr_reg:x3; val_offset:83901*0 + 3*319*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83901*0 + 3*319*FLEN/8, x4, x1, x2)

inst_27968:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xec and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x7600003f; valaddr_reg:x3; val_offset:83904*0 + 3*320*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83904*0 + 3*320*FLEN/8, x4, x1, x2)

inst_27969:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xec and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x7600007f; valaddr_reg:x3; val_offset:83907*0 + 3*321*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83907*0 + 3*321*FLEN/8, x4, x1, x2)

inst_27970:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xec and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x760000ff; valaddr_reg:x3; val_offset:83910*0 + 3*322*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83910*0 + 3*322*FLEN/8, x4, x1, x2)

inst_27971:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xec and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x760001ff; valaddr_reg:x3; val_offset:83913*0 + 3*323*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83913*0 + 3*323*FLEN/8, x4, x1, x2)

inst_27972:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xec and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x760003ff; valaddr_reg:x3; val_offset:83916*0 + 3*324*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83916*0 + 3*324*FLEN/8, x4, x1, x2)

inst_27973:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xec and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x760007ff; valaddr_reg:x3; val_offset:83919*0 + 3*325*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83919*0 + 3*325*FLEN/8, x4, x1, x2)

inst_27974:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xec and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x76000fff; valaddr_reg:x3; val_offset:83922*0 + 3*326*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83922*0 + 3*326*FLEN/8, x4, x1, x2)

inst_27975:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xec and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x76001fff; valaddr_reg:x3; val_offset:83925*0 + 3*327*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83925*0 + 3*327*FLEN/8, x4, x1, x2)

inst_27976:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xec and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x76003fff; valaddr_reg:x3; val_offset:83928*0 + 3*328*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83928*0 + 3*328*FLEN/8, x4, x1, x2)

inst_27977:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xec and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x76007fff; valaddr_reg:x3; val_offset:83931*0 + 3*329*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83931*0 + 3*329*FLEN/8, x4, x1, x2)

inst_27978:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xec and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x7600ffff; valaddr_reg:x3; val_offset:83934*0 + 3*330*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83934*0 + 3*330*FLEN/8, x4, x1, x2)

inst_27979:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xec and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x7601ffff; valaddr_reg:x3; val_offset:83937*0 + 3*331*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83937*0 + 3*331*FLEN/8, x4, x1, x2)

inst_27980:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xec and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x7603ffff; valaddr_reg:x3; val_offset:83940*0 + 3*332*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83940*0 + 3*332*FLEN/8, x4, x1, x2)

inst_27981:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xec and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x7607ffff; valaddr_reg:x3; val_offset:83943*0 + 3*333*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83943*0 + 3*333*FLEN/8, x4, x1, x2)

inst_27982:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xec and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x760fffff; valaddr_reg:x3; val_offset:83946*0 + 3*334*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83946*0 + 3*334*FLEN/8, x4, x1, x2)

inst_27983:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xec and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x761fffff; valaddr_reg:x3; val_offset:83949*0 + 3*335*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83949*0 + 3*335*FLEN/8, x4, x1, x2)

inst_27984:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xec and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x763fffff; valaddr_reg:x3; val_offset:83952*0 + 3*336*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83952*0 + 3*336*FLEN/8, x4, x1, x2)

inst_27985:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xec and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x76400000; valaddr_reg:x3; val_offset:83955*0 + 3*337*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83955*0 + 3*337*FLEN/8, x4, x1, x2)

inst_27986:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xec and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x76600000; valaddr_reg:x3; val_offset:83958*0 + 3*338*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83958*0 + 3*338*FLEN/8, x4, x1, x2)

inst_27987:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xec and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x76700000; valaddr_reg:x3; val_offset:83961*0 + 3*339*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83961*0 + 3*339*FLEN/8, x4, x1, x2)

inst_27988:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xec and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x76780000; valaddr_reg:x3; val_offset:83964*0 + 3*340*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83964*0 + 3*340*FLEN/8, x4, x1, x2)

inst_27989:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xec and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x767c0000; valaddr_reg:x3; val_offset:83967*0 + 3*341*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83967*0 + 3*341*FLEN/8, x4, x1, x2)

inst_27990:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xec and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x767e0000; valaddr_reg:x3; val_offset:83970*0 + 3*342*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83970*0 + 3*342*FLEN/8, x4, x1, x2)

inst_27991:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xec and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x767f0000; valaddr_reg:x3; val_offset:83973*0 + 3*343*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83973*0 + 3*343*FLEN/8, x4, x1, x2)

inst_27992:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xec and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x767f8000; valaddr_reg:x3; val_offset:83976*0 + 3*344*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83976*0 + 3*344*FLEN/8, x4, x1, x2)

inst_27993:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xec and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x767fc000; valaddr_reg:x3; val_offset:83979*0 + 3*345*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83979*0 + 3*345*FLEN/8, x4, x1, x2)

inst_27994:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xec and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x767fe000; valaddr_reg:x3; val_offset:83982*0 + 3*346*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83982*0 + 3*346*FLEN/8, x4, x1, x2)

inst_27995:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xec and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x767ff000; valaddr_reg:x3; val_offset:83985*0 + 3*347*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83985*0 + 3*347*FLEN/8, x4, x1, x2)

inst_27996:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xec and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x767ff800; valaddr_reg:x3; val_offset:83988*0 + 3*348*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83988*0 + 3*348*FLEN/8, x4, x1, x2)

inst_27997:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xec and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x767ffc00; valaddr_reg:x3; val_offset:83991*0 + 3*349*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83991*0 + 3*349*FLEN/8, x4, x1, x2)

inst_27998:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xec and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x767ffe00; valaddr_reg:x3; val_offset:83994*0 + 3*350*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83994*0 + 3*350*FLEN/8, x4, x1, x2)

inst_27999:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xec and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x767fff00; valaddr_reg:x3; val_offset:83997*0 + 3*351*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 83997*0 + 3*351*FLEN/8, x4, x1, x2)

inst_28000:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xec and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x767fff80; valaddr_reg:x3; val_offset:84000*0 + 3*352*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84000*0 + 3*352*FLEN/8, x4, x1, x2)

inst_28001:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xec and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x767fffc0; valaddr_reg:x3; val_offset:84003*0 + 3*353*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84003*0 + 3*353*FLEN/8, x4, x1, x2)

inst_28002:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xec and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x767fffe0; valaddr_reg:x3; val_offset:84006*0 + 3*354*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84006*0 + 3*354*FLEN/8, x4, x1, x2)

inst_28003:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xec and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x767ffff0; valaddr_reg:x3; val_offset:84009*0 + 3*355*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84009*0 + 3*355*FLEN/8, x4, x1, x2)

inst_28004:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xec and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x767ffff8; valaddr_reg:x3; val_offset:84012*0 + 3*356*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84012*0 + 3*356*FLEN/8, x4, x1, x2)

inst_28005:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xec and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x767ffffc; valaddr_reg:x3; val_offset:84015*0 + 3*357*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84015*0 + 3*357*FLEN/8, x4, x1, x2)

inst_28006:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xec and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x767ffffe; valaddr_reg:x3; val_offset:84018*0 + 3*358*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84018*0 + 3*358*FLEN/8, x4, x1, x2)

inst_28007:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xec and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x767fffff; valaddr_reg:x3; val_offset:84021*0 + 3*359*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84021*0 + 3*359*FLEN/8, x4, x1, x2)

inst_28008:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x7f000001; valaddr_reg:x3; val_offset:84024*0 + 3*360*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84024*0 + 3*360*FLEN/8, x4, x1, x2)

inst_28009:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x7f000003; valaddr_reg:x3; val_offset:84027*0 + 3*361*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84027*0 + 3*361*FLEN/8, x4, x1, x2)

inst_28010:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x7f000007; valaddr_reg:x3; val_offset:84030*0 + 3*362*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84030*0 + 3*362*FLEN/8, x4, x1, x2)

inst_28011:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x7f199999; valaddr_reg:x3; val_offset:84033*0 + 3*363*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84033*0 + 3*363*FLEN/8, x4, x1, x2)

inst_28012:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x7f249249; valaddr_reg:x3; val_offset:84036*0 + 3*364*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84036*0 + 3*364*FLEN/8, x4, x1, x2)

inst_28013:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x7f333333; valaddr_reg:x3; val_offset:84039*0 + 3*365*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84039*0 + 3*365*FLEN/8, x4, x1, x2)

inst_28014:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x7f36db6d; valaddr_reg:x3; val_offset:84042*0 + 3*366*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84042*0 + 3*366*FLEN/8, x4, x1, x2)

inst_28015:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x7f3bbbbb; valaddr_reg:x3; val_offset:84045*0 + 3*367*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84045*0 + 3*367*FLEN/8, x4, x1, x2)

inst_28016:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x7f444444; valaddr_reg:x3; val_offset:84048*0 + 3*368*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84048*0 + 3*368*FLEN/8, x4, x1, x2)

inst_28017:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x7f4ccccc; valaddr_reg:x3; val_offset:84051*0 + 3*369*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84051*0 + 3*369*FLEN/8, x4, x1, x2)

inst_28018:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x7f5b6db6; valaddr_reg:x3; val_offset:84054*0 + 3*370*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84054*0 + 3*370*FLEN/8, x4, x1, x2)

inst_28019:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x7f666666; valaddr_reg:x3; val_offset:84057*0 + 3*371*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84057*0 + 3*371*FLEN/8, x4, x1, x2)

inst_28020:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x7f6db6db; valaddr_reg:x3; val_offset:84060*0 + 3*372*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84060*0 + 3*372*FLEN/8, x4, x1, x2)

inst_28021:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x7f7ffff8; valaddr_reg:x3; val_offset:84063*0 + 3*373*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84063*0 + 3*373*FLEN/8, x4, x1, x2)

inst_28022:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x7f7ffffc; valaddr_reg:x3; val_offset:84066*0 + 3*374*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84066*0 + 3*374*FLEN/8, x4, x1, x2)

inst_28023:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0fc3b6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x63eda5 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f0fc3b6; op2val:0x3fe3eda5;
op3val:0x7f7ffffe; valaddr_reg:x3; val_offset:84069*0 + 3*375*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84069*0 + 3*375*FLEN/8, x4, x1, x2)

inst_28024:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x3; val_offset:84072*0 + 3*376*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84072*0 + 3*376*FLEN/8, x4, x1, x2)

inst_28025:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x80000003; valaddr_reg:x3; val_offset:84075*0 + 3*377*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84075*0 + 3*377*FLEN/8, x4, x1, x2)

inst_28026:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x80000007; valaddr_reg:x3; val_offset:84078*0 + 3*378*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84078*0 + 3*378*FLEN/8, x4, x1, x2)

inst_28027:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x80199999; valaddr_reg:x3; val_offset:84081*0 + 3*379*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84081*0 + 3*379*FLEN/8, x4, x1, x2)

inst_28028:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x80249249; valaddr_reg:x3; val_offset:84084*0 + 3*380*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84084*0 + 3*380*FLEN/8, x4, x1, x2)

inst_28029:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x80333333; valaddr_reg:x3; val_offset:84087*0 + 3*381*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84087*0 + 3*381*FLEN/8, x4, x1, x2)

inst_28030:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x8036db6d; valaddr_reg:x3; val_offset:84090*0 + 3*382*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84090*0 + 3*382*FLEN/8, x4, x1, x2)

inst_28031:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x803bbbbb; valaddr_reg:x3; val_offset:84093*0 + 3*383*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84093*0 + 3*383*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_4)

inst_28032:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x80444444; valaddr_reg:x3; val_offset:84096*0 + 3*384*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84096*0 + 3*384*FLEN/8, x4, x1, x2)

inst_28033:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x804ccccc; valaddr_reg:x3; val_offset:84099*0 + 3*385*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84099*0 + 3*385*FLEN/8, x4, x1, x2)

inst_28034:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x805b6db6; valaddr_reg:x3; val_offset:84102*0 + 3*386*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84102*0 + 3*386*FLEN/8, x4, x1, x2)

inst_28035:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x80666666; valaddr_reg:x3; val_offset:84105*0 + 3*387*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84105*0 + 3*387*FLEN/8, x4, x1, x2)

inst_28036:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x806db6db; valaddr_reg:x3; val_offset:84108*0 + 3*388*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84108*0 + 3*388*FLEN/8, x4, x1, x2)

inst_28037:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x807ffff8; valaddr_reg:x3; val_offset:84111*0 + 3*389*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84111*0 + 3*389*FLEN/8, x4, x1, x2)

inst_28038:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x807ffffc; valaddr_reg:x3; val_offset:84114*0 + 3*390*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84114*0 + 3*390*FLEN/8, x4, x1, x2)

inst_28039:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x3; val_offset:84117*0 + 3*391*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84117*0 + 3*391*FLEN/8, x4, x1, x2)

inst_28040:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x11 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x88800000; valaddr_reg:x3; val_offset:84120*0 + 3*392*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84120*0 + 3*392*FLEN/8, x4, x1, x2)

inst_28041:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x11 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x88800001; valaddr_reg:x3; val_offset:84123*0 + 3*393*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84123*0 + 3*393*FLEN/8, x4, x1, x2)

inst_28042:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x11 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x88800003; valaddr_reg:x3; val_offset:84126*0 + 3*394*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84126*0 + 3*394*FLEN/8, x4, x1, x2)

inst_28043:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x11 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x88800007; valaddr_reg:x3; val_offset:84129*0 + 3*395*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84129*0 + 3*395*FLEN/8, x4, x1, x2)

inst_28044:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x11 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x8880000f; valaddr_reg:x3; val_offset:84132*0 + 3*396*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84132*0 + 3*396*FLEN/8, x4, x1, x2)

inst_28045:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x11 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x8880001f; valaddr_reg:x3; val_offset:84135*0 + 3*397*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84135*0 + 3*397*FLEN/8, x4, x1, x2)

inst_28046:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x11 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x8880003f; valaddr_reg:x3; val_offset:84138*0 + 3*398*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84138*0 + 3*398*FLEN/8, x4, x1, x2)

inst_28047:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x11 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x8880007f; valaddr_reg:x3; val_offset:84141*0 + 3*399*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84141*0 + 3*399*FLEN/8, x4, x1, x2)

inst_28048:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x11 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x888000ff; valaddr_reg:x3; val_offset:84144*0 + 3*400*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84144*0 + 3*400*FLEN/8, x4, x1, x2)

inst_28049:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x11 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x888001ff; valaddr_reg:x3; val_offset:84147*0 + 3*401*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84147*0 + 3*401*FLEN/8, x4, x1, x2)

inst_28050:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x11 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x888003ff; valaddr_reg:x3; val_offset:84150*0 + 3*402*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84150*0 + 3*402*FLEN/8, x4, x1, x2)

inst_28051:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x11 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x888007ff; valaddr_reg:x3; val_offset:84153*0 + 3*403*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84153*0 + 3*403*FLEN/8, x4, x1, x2)

inst_28052:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x11 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x88800fff; valaddr_reg:x3; val_offset:84156*0 + 3*404*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84156*0 + 3*404*FLEN/8, x4, x1, x2)

inst_28053:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x11 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x88801fff; valaddr_reg:x3; val_offset:84159*0 + 3*405*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84159*0 + 3*405*FLEN/8, x4, x1, x2)

inst_28054:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x11 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x88803fff; valaddr_reg:x3; val_offset:84162*0 + 3*406*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84162*0 + 3*406*FLEN/8, x4, x1, x2)

inst_28055:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x11 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x88807fff; valaddr_reg:x3; val_offset:84165*0 + 3*407*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84165*0 + 3*407*FLEN/8, x4, x1, x2)

inst_28056:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x11 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x8880ffff; valaddr_reg:x3; val_offset:84168*0 + 3*408*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84168*0 + 3*408*FLEN/8, x4, x1, x2)

inst_28057:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x11 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x8881ffff; valaddr_reg:x3; val_offset:84171*0 + 3*409*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84171*0 + 3*409*FLEN/8, x4, x1, x2)

inst_28058:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x11 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x8883ffff; valaddr_reg:x3; val_offset:84174*0 + 3*410*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84174*0 + 3*410*FLEN/8, x4, x1, x2)

inst_28059:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x11 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x8887ffff; valaddr_reg:x3; val_offset:84177*0 + 3*411*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84177*0 + 3*411*FLEN/8, x4, x1, x2)

inst_28060:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x11 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x888fffff; valaddr_reg:x3; val_offset:84180*0 + 3*412*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84180*0 + 3*412*FLEN/8, x4, x1, x2)

inst_28061:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x11 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x889fffff; valaddr_reg:x3; val_offset:84183*0 + 3*413*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84183*0 + 3*413*FLEN/8, x4, x1, x2)

inst_28062:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x11 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x88bfffff; valaddr_reg:x3; val_offset:84186*0 + 3*414*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84186*0 + 3*414*FLEN/8, x4, x1, x2)

inst_28063:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x11 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x88c00000; valaddr_reg:x3; val_offset:84189*0 + 3*415*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84189*0 + 3*415*FLEN/8, x4, x1, x2)

inst_28064:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x11 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x88e00000; valaddr_reg:x3; val_offset:84192*0 + 3*416*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84192*0 + 3*416*FLEN/8, x4, x1, x2)

inst_28065:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x11 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x88f00000; valaddr_reg:x3; val_offset:84195*0 + 3*417*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84195*0 + 3*417*FLEN/8, x4, x1, x2)

inst_28066:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x11 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x88f80000; valaddr_reg:x3; val_offset:84198*0 + 3*418*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84198*0 + 3*418*FLEN/8, x4, x1, x2)

inst_28067:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x11 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x88fc0000; valaddr_reg:x3; val_offset:84201*0 + 3*419*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84201*0 + 3*419*FLEN/8, x4, x1, x2)

inst_28068:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x11 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x88fe0000; valaddr_reg:x3; val_offset:84204*0 + 3*420*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84204*0 + 3*420*FLEN/8, x4, x1, x2)

inst_28069:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x11 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x88ff0000; valaddr_reg:x3; val_offset:84207*0 + 3*421*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84207*0 + 3*421*FLEN/8, x4, x1, x2)

inst_28070:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x11 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x88ff8000; valaddr_reg:x3; val_offset:84210*0 + 3*422*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84210*0 + 3*422*FLEN/8, x4, x1, x2)

inst_28071:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x11 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x88ffc000; valaddr_reg:x3; val_offset:84213*0 + 3*423*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84213*0 + 3*423*FLEN/8, x4, x1, x2)

inst_28072:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x11 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x88ffe000; valaddr_reg:x3; val_offset:84216*0 + 3*424*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84216*0 + 3*424*FLEN/8, x4, x1, x2)

inst_28073:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x11 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x88fff000; valaddr_reg:x3; val_offset:84219*0 + 3*425*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84219*0 + 3*425*FLEN/8, x4, x1, x2)

inst_28074:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x11 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x88fff800; valaddr_reg:x3; val_offset:84222*0 + 3*426*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84222*0 + 3*426*FLEN/8, x4, x1, x2)

inst_28075:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x11 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x88fffc00; valaddr_reg:x3; val_offset:84225*0 + 3*427*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84225*0 + 3*427*FLEN/8, x4, x1, x2)

inst_28076:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x11 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x88fffe00; valaddr_reg:x3; val_offset:84228*0 + 3*428*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84228*0 + 3*428*FLEN/8, x4, x1, x2)

inst_28077:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x11 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x88ffff00; valaddr_reg:x3; val_offset:84231*0 + 3*429*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84231*0 + 3*429*FLEN/8, x4, x1, x2)

inst_28078:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x11 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x88ffff80; valaddr_reg:x3; val_offset:84234*0 + 3*430*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84234*0 + 3*430*FLEN/8, x4, x1, x2)

inst_28079:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x11 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x88ffffc0; valaddr_reg:x3; val_offset:84237*0 + 3*431*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84237*0 + 3*431*FLEN/8, x4, x1, x2)

inst_28080:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x11 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x88ffffe0; valaddr_reg:x3; val_offset:84240*0 + 3*432*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84240*0 + 3*432*FLEN/8, x4, x1, x2)

inst_28081:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x11 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x88fffff0; valaddr_reg:x3; val_offset:84243*0 + 3*433*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84243*0 + 3*433*FLEN/8, x4, x1, x2)

inst_28082:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x11 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x88fffff8; valaddr_reg:x3; val_offset:84246*0 + 3*434*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84246*0 + 3*434*FLEN/8, x4, x1, x2)

inst_28083:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x11 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x88fffffc; valaddr_reg:x3; val_offset:84249*0 + 3*435*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84249*0 + 3*435*FLEN/8, x4, x1, x2)

inst_28084:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x11 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x88fffffe; valaddr_reg:x3; val_offset:84252*0 + 3*436*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84252*0 + 3*436*FLEN/8, x4, x1, x2)

inst_28085:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1023d1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x11 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f1023d1; op2val:0x80000000;
op3val:0x88ffffff; valaddr_reg:x3; val_offset:84255*0 + 3*437*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84255*0 + 3*437*FLEN/8, x4, x1, x2)

inst_28086:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x71 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x38800000; valaddr_reg:x3; val_offset:84258*0 + 3*438*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84258*0 + 3*438*FLEN/8, x4, x1, x2)

inst_28087:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x71 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x38800001; valaddr_reg:x3; val_offset:84261*0 + 3*439*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84261*0 + 3*439*FLEN/8, x4, x1, x2)

inst_28088:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x71 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x38800003; valaddr_reg:x3; val_offset:84264*0 + 3*440*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84264*0 + 3*440*FLEN/8, x4, x1, x2)

inst_28089:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x71 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x38800007; valaddr_reg:x3; val_offset:84267*0 + 3*441*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84267*0 + 3*441*FLEN/8, x4, x1, x2)

inst_28090:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x71 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x3880000f; valaddr_reg:x3; val_offset:84270*0 + 3*442*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84270*0 + 3*442*FLEN/8, x4, x1, x2)

inst_28091:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x71 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x3880001f; valaddr_reg:x3; val_offset:84273*0 + 3*443*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84273*0 + 3*443*FLEN/8, x4, x1, x2)

inst_28092:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x71 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x3880003f; valaddr_reg:x3; val_offset:84276*0 + 3*444*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84276*0 + 3*444*FLEN/8, x4, x1, x2)

inst_28093:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x71 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x3880007f; valaddr_reg:x3; val_offset:84279*0 + 3*445*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84279*0 + 3*445*FLEN/8, x4, x1, x2)

inst_28094:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x71 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x388000ff; valaddr_reg:x3; val_offset:84282*0 + 3*446*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84282*0 + 3*446*FLEN/8, x4, x1, x2)

inst_28095:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x71 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x388001ff; valaddr_reg:x3; val_offset:84285*0 + 3*447*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84285*0 + 3*447*FLEN/8, x4, x1, x2)

inst_28096:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x71 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x388003ff; valaddr_reg:x3; val_offset:84288*0 + 3*448*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84288*0 + 3*448*FLEN/8, x4, x1, x2)

inst_28097:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x71 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x388007ff; valaddr_reg:x3; val_offset:84291*0 + 3*449*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84291*0 + 3*449*FLEN/8, x4, x1, x2)

inst_28098:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x71 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x38800fff; valaddr_reg:x3; val_offset:84294*0 + 3*450*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84294*0 + 3*450*FLEN/8, x4, x1, x2)

inst_28099:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x71 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x38801fff; valaddr_reg:x3; val_offset:84297*0 + 3*451*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84297*0 + 3*451*FLEN/8, x4, x1, x2)

inst_28100:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x71 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x38803fff; valaddr_reg:x3; val_offset:84300*0 + 3*452*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84300*0 + 3*452*FLEN/8, x4, x1, x2)

inst_28101:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x71 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x38807fff; valaddr_reg:x3; val_offset:84303*0 + 3*453*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84303*0 + 3*453*FLEN/8, x4, x1, x2)

inst_28102:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x71 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x3880ffff; valaddr_reg:x3; val_offset:84306*0 + 3*454*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84306*0 + 3*454*FLEN/8, x4, x1, x2)

inst_28103:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x71 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x3881ffff; valaddr_reg:x3; val_offset:84309*0 + 3*455*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84309*0 + 3*455*FLEN/8, x4, x1, x2)

inst_28104:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x71 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x3883ffff; valaddr_reg:x3; val_offset:84312*0 + 3*456*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84312*0 + 3*456*FLEN/8, x4, x1, x2)

inst_28105:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x71 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x3887ffff; valaddr_reg:x3; val_offset:84315*0 + 3*457*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84315*0 + 3*457*FLEN/8, x4, x1, x2)

inst_28106:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x71 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x388fffff; valaddr_reg:x3; val_offset:84318*0 + 3*458*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84318*0 + 3*458*FLEN/8, x4, x1, x2)

inst_28107:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x71 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x389fffff; valaddr_reg:x3; val_offset:84321*0 + 3*459*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84321*0 + 3*459*FLEN/8, x4, x1, x2)

inst_28108:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x71 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x38bfffff; valaddr_reg:x3; val_offset:84324*0 + 3*460*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84324*0 + 3*460*FLEN/8, x4, x1, x2)

inst_28109:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x71 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x38c00000; valaddr_reg:x3; val_offset:84327*0 + 3*461*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84327*0 + 3*461*FLEN/8, x4, x1, x2)

inst_28110:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x71 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x38e00000; valaddr_reg:x3; val_offset:84330*0 + 3*462*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84330*0 + 3*462*FLEN/8, x4, x1, x2)

inst_28111:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x71 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x38f00000; valaddr_reg:x3; val_offset:84333*0 + 3*463*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84333*0 + 3*463*FLEN/8, x4, x1, x2)

inst_28112:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x71 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x38f80000; valaddr_reg:x3; val_offset:84336*0 + 3*464*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84336*0 + 3*464*FLEN/8, x4, x1, x2)

inst_28113:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x71 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x38fc0000; valaddr_reg:x3; val_offset:84339*0 + 3*465*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84339*0 + 3*465*FLEN/8, x4, x1, x2)

inst_28114:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x71 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x38fe0000; valaddr_reg:x3; val_offset:84342*0 + 3*466*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84342*0 + 3*466*FLEN/8, x4, x1, x2)

inst_28115:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x71 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x38ff0000; valaddr_reg:x3; val_offset:84345*0 + 3*467*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84345*0 + 3*467*FLEN/8, x4, x1, x2)

inst_28116:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x71 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x38ff8000; valaddr_reg:x3; val_offset:84348*0 + 3*468*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84348*0 + 3*468*FLEN/8, x4, x1, x2)

inst_28117:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x71 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x38ffc000; valaddr_reg:x3; val_offset:84351*0 + 3*469*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84351*0 + 3*469*FLEN/8, x4, x1, x2)

inst_28118:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x71 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x38ffe000; valaddr_reg:x3; val_offset:84354*0 + 3*470*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84354*0 + 3*470*FLEN/8, x4, x1, x2)

inst_28119:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x71 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x38fff000; valaddr_reg:x3; val_offset:84357*0 + 3*471*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84357*0 + 3*471*FLEN/8, x4, x1, x2)

inst_28120:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x71 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x38fff800; valaddr_reg:x3; val_offset:84360*0 + 3*472*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84360*0 + 3*472*FLEN/8, x4, x1, x2)

inst_28121:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x71 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x38fffc00; valaddr_reg:x3; val_offset:84363*0 + 3*473*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84363*0 + 3*473*FLEN/8, x4, x1, x2)

inst_28122:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x71 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x38fffe00; valaddr_reg:x3; val_offset:84366*0 + 3*474*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84366*0 + 3*474*FLEN/8, x4, x1, x2)

inst_28123:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x71 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x38ffff00; valaddr_reg:x3; val_offset:84369*0 + 3*475*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84369*0 + 3*475*FLEN/8, x4, x1, x2)

inst_28124:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x71 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x38ffff80; valaddr_reg:x3; val_offset:84372*0 + 3*476*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84372*0 + 3*476*FLEN/8, x4, x1, x2)

inst_28125:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x71 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x38ffffc0; valaddr_reg:x3; val_offset:84375*0 + 3*477*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84375*0 + 3*477*FLEN/8, x4, x1, x2)

inst_28126:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x71 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x38ffffe0; valaddr_reg:x3; val_offset:84378*0 + 3*478*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84378*0 + 3*478*FLEN/8, x4, x1, x2)

inst_28127:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x71 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x38fffff0; valaddr_reg:x3; val_offset:84381*0 + 3*479*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84381*0 + 3*479*FLEN/8, x4, x1, x2)

inst_28128:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x71 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x38fffff8; valaddr_reg:x3; val_offset:84384*0 + 3*480*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84384*0 + 3*480*FLEN/8, x4, x1, x2)

inst_28129:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x71 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x38fffffc; valaddr_reg:x3; val_offset:84387*0 + 3*481*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84387*0 + 3*481*FLEN/8, x4, x1, x2)

inst_28130:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x71 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x38fffffe; valaddr_reg:x3; val_offset:84390*0 + 3*482*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84390*0 + 3*482*FLEN/8, x4, x1, x2)

inst_28131:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x71 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x38ffffff; valaddr_reg:x3; val_offset:84393*0 + 3*483*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84393*0 + 3*483*FLEN/8, x4, x1, x2)

inst_28132:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x3f800001; valaddr_reg:x3; val_offset:84396*0 + 3*484*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84396*0 + 3*484*FLEN/8, x4, x1, x2)

inst_28133:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x3f800003; valaddr_reg:x3; val_offset:84399*0 + 3*485*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84399*0 + 3*485*FLEN/8, x4, x1, x2)

inst_28134:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x3f800007; valaddr_reg:x3; val_offset:84402*0 + 3*486*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84402*0 + 3*486*FLEN/8, x4, x1, x2)

inst_28135:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x3f999999; valaddr_reg:x3; val_offset:84405*0 + 3*487*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84405*0 + 3*487*FLEN/8, x4, x1, x2)

inst_28136:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x3fa49249; valaddr_reg:x3; val_offset:84408*0 + 3*488*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84408*0 + 3*488*FLEN/8, x4, x1, x2)

inst_28137:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x3fb33333; valaddr_reg:x3; val_offset:84411*0 + 3*489*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84411*0 + 3*489*FLEN/8, x4, x1, x2)

inst_28138:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x3fb6db6d; valaddr_reg:x3; val_offset:84414*0 + 3*490*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84414*0 + 3*490*FLEN/8, x4, x1, x2)

inst_28139:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x3fbbbbbb; valaddr_reg:x3; val_offset:84417*0 + 3*491*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84417*0 + 3*491*FLEN/8, x4, x1, x2)

inst_28140:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x3fc44444; valaddr_reg:x3; val_offset:84420*0 + 3*492*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84420*0 + 3*492*FLEN/8, x4, x1, x2)

inst_28141:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x3fcccccc; valaddr_reg:x3; val_offset:84423*0 + 3*493*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84423*0 + 3*493*FLEN/8, x4, x1, x2)

inst_28142:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x3fdb6db6; valaddr_reg:x3; val_offset:84426*0 + 3*494*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84426*0 + 3*494*FLEN/8, x4, x1, x2)

inst_28143:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x3fe66666; valaddr_reg:x3; val_offset:84429*0 + 3*495*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84429*0 + 3*495*FLEN/8, x4, x1, x2)

inst_28144:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x3fedb6db; valaddr_reg:x3; val_offset:84432*0 + 3*496*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84432*0 + 3*496*FLEN/8, x4, x1, x2)

inst_28145:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x3ffffff8; valaddr_reg:x3; val_offset:84435*0 + 3*497*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84435*0 + 3*497*FLEN/8, x4, x1, x2)

inst_28146:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x3ffffffc; valaddr_reg:x3; val_offset:84438*0 + 3*498*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84438*0 + 3*498*FLEN/8, x4, x1, x2)

inst_28147:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x10cbbf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x389381 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f10cbbf; op2val:0x389381;
op3val:0x3ffffffe; valaddr_reg:x3; val_offset:84441*0 + 3*499*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84441*0 + 3*499*FLEN/8, x4, x1, x2)

inst_28148:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x80800001; valaddr_reg:x3; val_offset:84444*0 + 3*500*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84444*0 + 3*500*FLEN/8, x4, x1, x2)

inst_28149:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x80800003; valaddr_reg:x3; val_offset:84447*0 + 3*501*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84447*0 + 3*501*FLEN/8, x4, x1, x2)

inst_28150:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x80800007; valaddr_reg:x3; val_offset:84450*0 + 3*502*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84450*0 + 3*502*FLEN/8, x4, x1, x2)

inst_28151:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x80999999; valaddr_reg:x3; val_offset:84453*0 + 3*503*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84453*0 + 3*503*FLEN/8, x4, x1, x2)

inst_28152:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x80a49249; valaddr_reg:x3; val_offset:84456*0 + 3*504*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84456*0 + 3*504*FLEN/8, x4, x1, x2)

inst_28153:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x80b33333; valaddr_reg:x3; val_offset:84459*0 + 3*505*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84459*0 + 3*505*FLEN/8, x4, x1, x2)

inst_28154:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x80b6db6d; valaddr_reg:x3; val_offset:84462*0 + 3*506*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84462*0 + 3*506*FLEN/8, x4, x1, x2)

inst_28155:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x80bbbbbb; valaddr_reg:x3; val_offset:84465*0 + 3*507*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84465*0 + 3*507*FLEN/8, x4, x1, x2)

inst_28156:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x80c44444; valaddr_reg:x3; val_offset:84468*0 + 3*508*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84468*0 + 3*508*FLEN/8, x4, x1, x2)

inst_28157:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x80cccccc; valaddr_reg:x3; val_offset:84471*0 + 3*509*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84471*0 + 3*509*FLEN/8, x4, x1, x2)

inst_28158:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x80db6db6; valaddr_reg:x3; val_offset:84474*0 + 3*510*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84474*0 + 3*510*FLEN/8, x4, x1, x2)

inst_28159:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x80e66666; valaddr_reg:x3; val_offset:84477*0 + 3*511*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84477*0 + 3*511*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_5)

inst_28160:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x80edb6db; valaddr_reg:x3; val_offset:84480*0 + 3*512*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84480*0 + 3*512*FLEN/8, x4, x1, x2)

inst_28161:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x80fffff8; valaddr_reg:x3; val_offset:84483*0 + 3*513*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84483*0 + 3*513*FLEN/8, x4, x1, x2)

inst_28162:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x80fffffc; valaddr_reg:x3; val_offset:84486*0 + 3*514*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84486*0 + 3*514*FLEN/8, x4, x1, x2)

inst_28163:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x80fffffe; valaddr_reg:x3; val_offset:84489*0 + 3*515*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84489*0 + 3*515*FLEN/8, x4, x1, x2)

inst_28164:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x8a800000; valaddr_reg:x3; val_offset:84492*0 + 3*516*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84492*0 + 3*516*FLEN/8, x4, x1, x2)

inst_28165:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x8a800001; valaddr_reg:x3; val_offset:84495*0 + 3*517*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84495*0 + 3*517*FLEN/8, x4, x1, x2)

inst_28166:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x8a800003; valaddr_reg:x3; val_offset:84498*0 + 3*518*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84498*0 + 3*518*FLEN/8, x4, x1, x2)

inst_28167:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x8a800007; valaddr_reg:x3; val_offset:84501*0 + 3*519*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84501*0 + 3*519*FLEN/8, x4, x1, x2)

inst_28168:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x8a80000f; valaddr_reg:x3; val_offset:84504*0 + 3*520*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84504*0 + 3*520*FLEN/8, x4, x1, x2)

inst_28169:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x8a80001f; valaddr_reg:x3; val_offset:84507*0 + 3*521*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84507*0 + 3*521*FLEN/8, x4, x1, x2)

inst_28170:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x8a80003f; valaddr_reg:x3; val_offset:84510*0 + 3*522*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84510*0 + 3*522*FLEN/8, x4, x1, x2)

inst_28171:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x8a80007f; valaddr_reg:x3; val_offset:84513*0 + 3*523*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84513*0 + 3*523*FLEN/8, x4, x1, x2)

inst_28172:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x8a8000ff; valaddr_reg:x3; val_offset:84516*0 + 3*524*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84516*0 + 3*524*FLEN/8, x4, x1, x2)

inst_28173:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x8a8001ff; valaddr_reg:x3; val_offset:84519*0 + 3*525*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84519*0 + 3*525*FLEN/8, x4, x1, x2)

inst_28174:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x8a8003ff; valaddr_reg:x3; val_offset:84522*0 + 3*526*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84522*0 + 3*526*FLEN/8, x4, x1, x2)

inst_28175:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x8a8007ff; valaddr_reg:x3; val_offset:84525*0 + 3*527*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84525*0 + 3*527*FLEN/8, x4, x1, x2)

inst_28176:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x8a800fff; valaddr_reg:x3; val_offset:84528*0 + 3*528*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84528*0 + 3*528*FLEN/8, x4, x1, x2)

inst_28177:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x8a801fff; valaddr_reg:x3; val_offset:84531*0 + 3*529*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84531*0 + 3*529*FLEN/8, x4, x1, x2)

inst_28178:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x8a803fff; valaddr_reg:x3; val_offset:84534*0 + 3*530*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84534*0 + 3*530*FLEN/8, x4, x1, x2)

inst_28179:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x8a807fff; valaddr_reg:x3; val_offset:84537*0 + 3*531*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84537*0 + 3*531*FLEN/8, x4, x1, x2)

inst_28180:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x8a80ffff; valaddr_reg:x3; val_offset:84540*0 + 3*532*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84540*0 + 3*532*FLEN/8, x4, x1, x2)

inst_28181:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x8a81ffff; valaddr_reg:x3; val_offset:84543*0 + 3*533*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84543*0 + 3*533*FLEN/8, x4, x1, x2)

inst_28182:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x8a83ffff; valaddr_reg:x3; val_offset:84546*0 + 3*534*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84546*0 + 3*534*FLEN/8, x4, x1, x2)

inst_28183:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x8a87ffff; valaddr_reg:x3; val_offset:84549*0 + 3*535*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84549*0 + 3*535*FLEN/8, x4, x1, x2)

inst_28184:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x8a8fffff; valaddr_reg:x3; val_offset:84552*0 + 3*536*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84552*0 + 3*536*FLEN/8, x4, x1, x2)

inst_28185:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x8a9fffff; valaddr_reg:x3; val_offset:84555*0 + 3*537*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84555*0 + 3*537*FLEN/8, x4, x1, x2)

inst_28186:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x8abfffff; valaddr_reg:x3; val_offset:84558*0 + 3*538*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84558*0 + 3*538*FLEN/8, x4, x1, x2)

inst_28187:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x8ac00000; valaddr_reg:x3; val_offset:84561*0 + 3*539*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84561*0 + 3*539*FLEN/8, x4, x1, x2)

inst_28188:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x8ae00000; valaddr_reg:x3; val_offset:84564*0 + 3*540*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84564*0 + 3*540*FLEN/8, x4, x1, x2)

inst_28189:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x8af00000; valaddr_reg:x3; val_offset:84567*0 + 3*541*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84567*0 + 3*541*FLEN/8, x4, x1, x2)

inst_28190:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x8af80000; valaddr_reg:x3; val_offset:84570*0 + 3*542*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84570*0 + 3*542*FLEN/8, x4, x1, x2)

inst_28191:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x8afc0000; valaddr_reg:x3; val_offset:84573*0 + 3*543*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84573*0 + 3*543*FLEN/8, x4, x1, x2)

inst_28192:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x8afe0000; valaddr_reg:x3; val_offset:84576*0 + 3*544*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84576*0 + 3*544*FLEN/8, x4, x1, x2)

inst_28193:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x8aff0000; valaddr_reg:x3; val_offset:84579*0 + 3*545*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84579*0 + 3*545*FLEN/8, x4, x1, x2)

inst_28194:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x8aff8000; valaddr_reg:x3; val_offset:84582*0 + 3*546*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84582*0 + 3*546*FLEN/8, x4, x1, x2)

inst_28195:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x8affc000; valaddr_reg:x3; val_offset:84585*0 + 3*547*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84585*0 + 3*547*FLEN/8, x4, x1, x2)

inst_28196:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x8affe000; valaddr_reg:x3; val_offset:84588*0 + 3*548*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84588*0 + 3*548*FLEN/8, x4, x1, x2)

inst_28197:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x8afff000; valaddr_reg:x3; val_offset:84591*0 + 3*549*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84591*0 + 3*549*FLEN/8, x4, x1, x2)

inst_28198:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x8afff800; valaddr_reg:x3; val_offset:84594*0 + 3*550*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84594*0 + 3*550*FLEN/8, x4, x1, x2)

inst_28199:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x8afffc00; valaddr_reg:x3; val_offset:84597*0 + 3*551*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84597*0 + 3*551*FLEN/8, x4, x1, x2)

inst_28200:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x8afffe00; valaddr_reg:x3; val_offset:84600*0 + 3*552*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84600*0 + 3*552*FLEN/8, x4, x1, x2)

inst_28201:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x8affff00; valaddr_reg:x3; val_offset:84603*0 + 3*553*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84603*0 + 3*553*FLEN/8, x4, x1, x2)

inst_28202:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x8affff80; valaddr_reg:x3; val_offset:84606*0 + 3*554*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84606*0 + 3*554*FLEN/8, x4, x1, x2)

inst_28203:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x8affffc0; valaddr_reg:x3; val_offset:84609*0 + 3*555*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84609*0 + 3*555*FLEN/8, x4, x1, x2)

inst_28204:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x8affffe0; valaddr_reg:x3; val_offset:84612*0 + 3*556*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84612*0 + 3*556*FLEN/8, x4, x1, x2)

inst_28205:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x8afffff0; valaddr_reg:x3; val_offset:84615*0 + 3*557*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84615*0 + 3*557*FLEN/8, x4, x1, x2)

inst_28206:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x8afffff8; valaddr_reg:x3; val_offset:84618*0 + 3*558*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84618*0 + 3*558*FLEN/8, x4, x1, x2)

inst_28207:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x8afffffc; valaddr_reg:x3; val_offset:84621*0 + 3*559*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84621*0 + 3*559*FLEN/8, x4, x1, x2)

inst_28208:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x8afffffe; valaddr_reg:x3; val_offset:84624*0 + 3*560*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84624*0 + 3*560*FLEN/8, x4, x1, x2)

inst_28209:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x116cb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f116cb0; op2val:0x80000000;
op3val:0x8affffff; valaddr_reg:x3; val_offset:84627*0 + 3*561*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84627*0 + 3*561*FLEN/8, x4, x1, x2)

inst_28210:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0x800001; valaddr_reg:x3; val_offset:84630*0 + 3*562*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84630*0 + 3*562*FLEN/8, x4, x1, x2)

inst_28211:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0x800003; valaddr_reg:x3; val_offset:84633*0 + 3*563*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84633*0 + 3*563*FLEN/8, x4, x1, x2)

inst_28212:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0x800007; valaddr_reg:x3; val_offset:84636*0 + 3*564*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84636*0 + 3*564*FLEN/8, x4, x1, x2)

inst_28213:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0x999999; valaddr_reg:x3; val_offset:84639*0 + 3*565*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84639*0 + 3*565*FLEN/8, x4, x1, x2)

inst_28214:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0xa49249; valaddr_reg:x3; val_offset:84642*0 + 3*566*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84642*0 + 3*566*FLEN/8, x4, x1, x2)

inst_28215:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0xb33333; valaddr_reg:x3; val_offset:84645*0 + 3*567*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84645*0 + 3*567*FLEN/8, x4, x1, x2)

inst_28216:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0xb6db6d; valaddr_reg:x3; val_offset:84648*0 + 3*568*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84648*0 + 3*568*FLEN/8, x4, x1, x2)

inst_28217:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0xbbbbbb; valaddr_reg:x3; val_offset:84651*0 + 3*569*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84651*0 + 3*569*FLEN/8, x4, x1, x2)

inst_28218:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0xc44444; valaddr_reg:x3; val_offset:84654*0 + 3*570*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84654*0 + 3*570*FLEN/8, x4, x1, x2)

inst_28219:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0xcccccc; valaddr_reg:x3; val_offset:84657*0 + 3*571*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84657*0 + 3*571*FLEN/8, x4, x1, x2)

inst_28220:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0xdb6db6; valaddr_reg:x3; val_offset:84660*0 + 3*572*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84660*0 + 3*572*FLEN/8, x4, x1, x2)

inst_28221:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0xe66666; valaddr_reg:x3; val_offset:84663*0 + 3*573*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84663*0 + 3*573*FLEN/8, x4, x1, x2)

inst_28222:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0xedb6db; valaddr_reg:x3; val_offset:84666*0 + 3*574*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84666*0 + 3*574*FLEN/8, x4, x1, x2)

inst_28223:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0xfffff8; valaddr_reg:x3; val_offset:84669*0 + 3*575*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84669*0 + 3*575*FLEN/8, x4, x1, x2)

inst_28224:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0xfffffc; valaddr_reg:x3; val_offset:84672*0 + 3*576*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84672*0 + 3*576*FLEN/8, x4, x1, x2)

inst_28225:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0xfffffe; valaddr_reg:x3; val_offset:84675*0 + 3*577*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84675*0 + 3*577*FLEN/8, x4, x1, x2)

inst_28226:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0x4000000; valaddr_reg:x3; val_offset:84678*0 + 3*578*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84678*0 + 3*578*FLEN/8, x4, x1, x2)

inst_28227:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0x4000001; valaddr_reg:x3; val_offset:84681*0 + 3*579*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84681*0 + 3*579*FLEN/8, x4, x1, x2)

inst_28228:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0x4000003; valaddr_reg:x3; val_offset:84684*0 + 3*580*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84684*0 + 3*580*FLEN/8, x4, x1, x2)

inst_28229:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0x4000007; valaddr_reg:x3; val_offset:84687*0 + 3*581*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84687*0 + 3*581*FLEN/8, x4, x1, x2)

inst_28230:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0x400000f; valaddr_reg:x3; val_offset:84690*0 + 3*582*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84690*0 + 3*582*FLEN/8, x4, x1, x2)

inst_28231:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0x400001f; valaddr_reg:x3; val_offset:84693*0 + 3*583*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84693*0 + 3*583*FLEN/8, x4, x1, x2)

inst_28232:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0x400003f; valaddr_reg:x3; val_offset:84696*0 + 3*584*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84696*0 + 3*584*FLEN/8, x4, x1, x2)

inst_28233:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0x400007f; valaddr_reg:x3; val_offset:84699*0 + 3*585*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84699*0 + 3*585*FLEN/8, x4, x1, x2)

inst_28234:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0x40000ff; valaddr_reg:x3; val_offset:84702*0 + 3*586*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84702*0 + 3*586*FLEN/8, x4, x1, x2)

inst_28235:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0x40001ff; valaddr_reg:x3; val_offset:84705*0 + 3*587*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84705*0 + 3*587*FLEN/8, x4, x1, x2)

inst_28236:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0x40003ff; valaddr_reg:x3; val_offset:84708*0 + 3*588*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84708*0 + 3*588*FLEN/8, x4, x1, x2)

inst_28237:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0x40007ff; valaddr_reg:x3; val_offset:84711*0 + 3*589*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84711*0 + 3*589*FLEN/8, x4, x1, x2)

inst_28238:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0x4000fff; valaddr_reg:x3; val_offset:84714*0 + 3*590*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84714*0 + 3*590*FLEN/8, x4, x1, x2)

inst_28239:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0x4001fff; valaddr_reg:x3; val_offset:84717*0 + 3*591*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84717*0 + 3*591*FLEN/8, x4, x1, x2)

inst_28240:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0x4003fff; valaddr_reg:x3; val_offset:84720*0 + 3*592*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84720*0 + 3*592*FLEN/8, x4, x1, x2)

inst_28241:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0x4007fff; valaddr_reg:x3; val_offset:84723*0 + 3*593*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84723*0 + 3*593*FLEN/8, x4, x1, x2)

inst_28242:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0x400ffff; valaddr_reg:x3; val_offset:84726*0 + 3*594*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84726*0 + 3*594*FLEN/8, x4, x1, x2)

inst_28243:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0x401ffff; valaddr_reg:x3; val_offset:84729*0 + 3*595*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84729*0 + 3*595*FLEN/8, x4, x1, x2)

inst_28244:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0x403ffff; valaddr_reg:x3; val_offset:84732*0 + 3*596*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84732*0 + 3*596*FLEN/8, x4, x1, x2)

inst_28245:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0x407ffff; valaddr_reg:x3; val_offset:84735*0 + 3*597*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84735*0 + 3*597*FLEN/8, x4, x1, x2)

inst_28246:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0x40fffff; valaddr_reg:x3; val_offset:84738*0 + 3*598*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84738*0 + 3*598*FLEN/8, x4, x1, x2)

inst_28247:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0x41fffff; valaddr_reg:x3; val_offset:84741*0 + 3*599*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84741*0 + 3*599*FLEN/8, x4, x1, x2)

inst_28248:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0x43fffff; valaddr_reg:x3; val_offset:84744*0 + 3*600*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84744*0 + 3*600*FLEN/8, x4, x1, x2)

inst_28249:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0x4400000; valaddr_reg:x3; val_offset:84747*0 + 3*601*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84747*0 + 3*601*FLEN/8, x4, x1, x2)

inst_28250:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0x4600000; valaddr_reg:x3; val_offset:84750*0 + 3*602*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84750*0 + 3*602*FLEN/8, x4, x1, x2)

inst_28251:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0x4700000; valaddr_reg:x3; val_offset:84753*0 + 3*603*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84753*0 + 3*603*FLEN/8, x4, x1, x2)

inst_28252:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0x4780000; valaddr_reg:x3; val_offset:84756*0 + 3*604*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84756*0 + 3*604*FLEN/8, x4, x1, x2)

inst_28253:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0x47c0000; valaddr_reg:x3; val_offset:84759*0 + 3*605*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84759*0 + 3*605*FLEN/8, x4, x1, x2)

inst_28254:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0x47e0000; valaddr_reg:x3; val_offset:84762*0 + 3*606*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84762*0 + 3*606*FLEN/8, x4, x1, x2)

inst_28255:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0x47f0000; valaddr_reg:x3; val_offset:84765*0 + 3*607*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84765*0 + 3*607*FLEN/8, x4, x1, x2)

inst_28256:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0x47f8000; valaddr_reg:x3; val_offset:84768*0 + 3*608*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84768*0 + 3*608*FLEN/8, x4, x1, x2)

inst_28257:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0x47fc000; valaddr_reg:x3; val_offset:84771*0 + 3*609*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84771*0 + 3*609*FLEN/8, x4, x1, x2)

inst_28258:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0x47fe000; valaddr_reg:x3; val_offset:84774*0 + 3*610*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84774*0 + 3*610*FLEN/8, x4, x1, x2)

inst_28259:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0x47ff000; valaddr_reg:x3; val_offset:84777*0 + 3*611*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84777*0 + 3*611*FLEN/8, x4, x1, x2)

inst_28260:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0x47ff800; valaddr_reg:x3; val_offset:84780*0 + 3*612*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84780*0 + 3*612*FLEN/8, x4, x1, x2)

inst_28261:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0x47ffc00; valaddr_reg:x3; val_offset:84783*0 + 3*613*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84783*0 + 3*613*FLEN/8, x4, x1, x2)

inst_28262:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0x47ffe00; valaddr_reg:x3; val_offset:84786*0 + 3*614*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84786*0 + 3*614*FLEN/8, x4, x1, x2)

inst_28263:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0x47fff00; valaddr_reg:x3; val_offset:84789*0 + 3*615*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84789*0 + 3*615*FLEN/8, x4, x1, x2)

inst_28264:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0x47fff80; valaddr_reg:x3; val_offset:84792*0 + 3*616*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84792*0 + 3*616*FLEN/8, x4, x1, x2)

inst_28265:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0x47fffc0; valaddr_reg:x3; val_offset:84795*0 + 3*617*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84795*0 + 3*617*FLEN/8, x4, x1, x2)

inst_28266:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0x47fffe0; valaddr_reg:x3; val_offset:84798*0 + 3*618*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84798*0 + 3*618*FLEN/8, x4, x1, x2)

inst_28267:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0x47ffff0; valaddr_reg:x3; val_offset:84801*0 + 3*619*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84801*0 + 3*619*FLEN/8, x4, x1, x2)

inst_28268:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0x47ffff8; valaddr_reg:x3; val_offset:84804*0 + 3*620*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84804*0 + 3*620*FLEN/8, x4, x1, x2)

inst_28269:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0x47ffffc; valaddr_reg:x3; val_offset:84807*0 + 3*621*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84807*0 + 3*621*FLEN/8, x4, x1, x2)

inst_28270:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0x47ffffe; valaddr_reg:x3; val_offset:84810*0 + 3*622*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84810*0 + 3*622*FLEN/8, x4, x1, x2)

inst_28271:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x117cee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f117cee; op2val:0x0;
op3val:0x47fffff; valaddr_reg:x3; val_offset:84813*0 + 3*623*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84813*0 + 3*623*FLEN/8, x4, x1, x2)

inst_28272:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0x1; valaddr_reg:x3; val_offset:84816*0 + 3*624*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84816*0 + 3*624*FLEN/8, x4, x1, x2)

inst_28273:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0x3; valaddr_reg:x3; val_offset:84819*0 + 3*625*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84819*0 + 3*625*FLEN/8, x4, x1, x2)

inst_28274:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0x7; valaddr_reg:x3; val_offset:84822*0 + 3*626*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84822*0 + 3*626*FLEN/8, x4, x1, x2)

inst_28275:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0x199999; valaddr_reg:x3; val_offset:84825*0 + 3*627*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84825*0 + 3*627*FLEN/8, x4, x1, x2)

inst_28276:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0x249249; valaddr_reg:x3; val_offset:84828*0 + 3*628*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84828*0 + 3*628*FLEN/8, x4, x1, x2)

inst_28277:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0x333333; valaddr_reg:x3; val_offset:84831*0 + 3*629*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84831*0 + 3*629*FLEN/8, x4, x1, x2)

inst_28278:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0x36db6d; valaddr_reg:x3; val_offset:84834*0 + 3*630*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84834*0 + 3*630*FLEN/8, x4, x1, x2)

inst_28279:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0x3bbbbb; valaddr_reg:x3; val_offset:84837*0 + 3*631*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84837*0 + 3*631*FLEN/8, x4, x1, x2)

inst_28280:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0x444444; valaddr_reg:x3; val_offset:84840*0 + 3*632*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84840*0 + 3*632*FLEN/8, x4, x1, x2)

inst_28281:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0x4ccccc; valaddr_reg:x3; val_offset:84843*0 + 3*633*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84843*0 + 3*633*FLEN/8, x4, x1, x2)

inst_28282:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0x5b6db6; valaddr_reg:x3; val_offset:84846*0 + 3*634*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84846*0 + 3*634*FLEN/8, x4, x1, x2)

inst_28283:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0x666666; valaddr_reg:x3; val_offset:84849*0 + 3*635*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84849*0 + 3*635*FLEN/8, x4, x1, x2)

inst_28284:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0x6db6db; valaddr_reg:x3; val_offset:84852*0 + 3*636*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84852*0 + 3*636*FLEN/8, x4, x1, x2)

inst_28285:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0x7ffff8; valaddr_reg:x3; val_offset:84855*0 + 3*637*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84855*0 + 3*637*FLEN/8, x4, x1, x2)

inst_28286:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0x7ffffc; valaddr_reg:x3; val_offset:84858*0 + 3*638*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84858*0 + 3*638*FLEN/8, x4, x1, x2)

inst_28287:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0x7ffffe; valaddr_reg:x3; val_offset:84861*0 + 3*639*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84861*0 + 3*639*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_6)

inst_28288:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf000000; valaddr_reg:x3; val_offset:84864*0 + 3*640*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84864*0 + 3*640*FLEN/8, x4, x1, x2)

inst_28289:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf000001; valaddr_reg:x3; val_offset:84867*0 + 3*641*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84867*0 + 3*641*FLEN/8, x4, x1, x2)

inst_28290:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf000003; valaddr_reg:x3; val_offset:84870*0 + 3*642*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84870*0 + 3*642*FLEN/8, x4, x1, x2)

inst_28291:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf000007; valaddr_reg:x3; val_offset:84873*0 + 3*643*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84873*0 + 3*643*FLEN/8, x4, x1, x2)

inst_28292:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf00000f; valaddr_reg:x3; val_offset:84876*0 + 3*644*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84876*0 + 3*644*FLEN/8, x4, x1, x2)

inst_28293:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf00001f; valaddr_reg:x3; val_offset:84879*0 + 3*645*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84879*0 + 3*645*FLEN/8, x4, x1, x2)

inst_28294:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf00003f; valaddr_reg:x3; val_offset:84882*0 + 3*646*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84882*0 + 3*646*FLEN/8, x4, x1, x2)

inst_28295:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf00007f; valaddr_reg:x3; val_offset:84885*0 + 3*647*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84885*0 + 3*647*FLEN/8, x4, x1, x2)

inst_28296:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf0000ff; valaddr_reg:x3; val_offset:84888*0 + 3*648*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84888*0 + 3*648*FLEN/8, x4, x1, x2)

inst_28297:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf0001ff; valaddr_reg:x3; val_offset:84891*0 + 3*649*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84891*0 + 3*649*FLEN/8, x4, x1, x2)

inst_28298:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf0003ff; valaddr_reg:x3; val_offset:84894*0 + 3*650*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84894*0 + 3*650*FLEN/8, x4, x1, x2)

inst_28299:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf0007ff; valaddr_reg:x3; val_offset:84897*0 + 3*651*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84897*0 + 3*651*FLEN/8, x4, x1, x2)

inst_28300:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf000fff; valaddr_reg:x3; val_offset:84900*0 + 3*652*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84900*0 + 3*652*FLEN/8, x4, x1, x2)

inst_28301:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf001fff; valaddr_reg:x3; val_offset:84903*0 + 3*653*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84903*0 + 3*653*FLEN/8, x4, x1, x2)

inst_28302:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf003fff; valaddr_reg:x3; val_offset:84906*0 + 3*654*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84906*0 + 3*654*FLEN/8, x4, x1, x2)

inst_28303:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf007fff; valaddr_reg:x3; val_offset:84909*0 + 3*655*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84909*0 + 3*655*FLEN/8, x4, x1, x2)

inst_28304:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf00ffff; valaddr_reg:x3; val_offset:84912*0 + 3*656*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84912*0 + 3*656*FLEN/8, x4, x1, x2)

inst_28305:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf01ffff; valaddr_reg:x3; val_offset:84915*0 + 3*657*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84915*0 + 3*657*FLEN/8, x4, x1, x2)

inst_28306:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf03ffff; valaddr_reg:x3; val_offset:84918*0 + 3*658*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84918*0 + 3*658*FLEN/8, x4, x1, x2)

inst_28307:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf07ffff; valaddr_reg:x3; val_offset:84921*0 + 3*659*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84921*0 + 3*659*FLEN/8, x4, x1, x2)

inst_28308:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf0fffff; valaddr_reg:x3; val_offset:84924*0 + 3*660*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84924*0 + 3*660*FLEN/8, x4, x1, x2)

inst_28309:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf1fffff; valaddr_reg:x3; val_offset:84927*0 + 3*661*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84927*0 + 3*661*FLEN/8, x4, x1, x2)

inst_28310:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf3fffff; valaddr_reg:x3; val_offset:84930*0 + 3*662*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84930*0 + 3*662*FLEN/8, x4, x1, x2)

inst_28311:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf400000; valaddr_reg:x3; val_offset:84933*0 + 3*663*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84933*0 + 3*663*FLEN/8, x4, x1, x2)

inst_28312:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf600000; valaddr_reg:x3; val_offset:84936*0 + 3*664*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84936*0 + 3*664*FLEN/8, x4, x1, x2)

inst_28313:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf700000; valaddr_reg:x3; val_offset:84939*0 + 3*665*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84939*0 + 3*665*FLEN/8, x4, x1, x2)

inst_28314:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf780000; valaddr_reg:x3; val_offset:84942*0 + 3*666*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84942*0 + 3*666*FLEN/8, x4, x1, x2)

inst_28315:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf7c0000; valaddr_reg:x3; val_offset:84945*0 + 3*667*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84945*0 + 3*667*FLEN/8, x4, x1, x2)

inst_28316:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf7e0000; valaddr_reg:x3; val_offset:84948*0 + 3*668*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84948*0 + 3*668*FLEN/8, x4, x1, x2)

inst_28317:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf7f0000; valaddr_reg:x3; val_offset:84951*0 + 3*669*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84951*0 + 3*669*FLEN/8, x4, x1, x2)

inst_28318:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf7f8000; valaddr_reg:x3; val_offset:84954*0 + 3*670*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84954*0 + 3*670*FLEN/8, x4, x1, x2)

inst_28319:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf7fc000; valaddr_reg:x3; val_offset:84957*0 + 3*671*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84957*0 + 3*671*FLEN/8, x4, x1, x2)

inst_28320:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf7fe000; valaddr_reg:x3; val_offset:84960*0 + 3*672*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84960*0 + 3*672*FLEN/8, x4, x1, x2)

inst_28321:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf7ff000; valaddr_reg:x3; val_offset:84963*0 + 3*673*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84963*0 + 3*673*FLEN/8, x4, x1, x2)

inst_28322:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf7ff800; valaddr_reg:x3; val_offset:84966*0 + 3*674*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84966*0 + 3*674*FLEN/8, x4, x1, x2)

inst_28323:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf7ffc00; valaddr_reg:x3; val_offset:84969*0 + 3*675*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84969*0 + 3*675*FLEN/8, x4, x1, x2)

inst_28324:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf7ffe00; valaddr_reg:x3; val_offset:84972*0 + 3*676*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84972*0 + 3*676*FLEN/8, x4, x1, x2)

inst_28325:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf7fff00; valaddr_reg:x3; val_offset:84975*0 + 3*677*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84975*0 + 3*677*FLEN/8, x4, x1, x2)

inst_28326:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf7fff80; valaddr_reg:x3; val_offset:84978*0 + 3*678*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84978*0 + 3*678*FLEN/8, x4, x1, x2)

inst_28327:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf7fffc0; valaddr_reg:x3; val_offset:84981*0 + 3*679*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84981*0 + 3*679*FLEN/8, x4, x1, x2)

inst_28328:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf7fffe0; valaddr_reg:x3; val_offset:84984*0 + 3*680*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84984*0 + 3*680*FLEN/8, x4, x1, x2)

inst_28329:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf7ffff0; valaddr_reg:x3; val_offset:84987*0 + 3*681*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84987*0 + 3*681*FLEN/8, x4, x1, x2)

inst_28330:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf7ffff8; valaddr_reg:x3; val_offset:84990*0 + 3*682*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84990*0 + 3*682*FLEN/8, x4, x1, x2)

inst_28331:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf7ffffc; valaddr_reg:x3; val_offset:84993*0 + 3*683*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84993*0 + 3*683*FLEN/8, x4, x1, x2)

inst_28332:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf7ffffe; valaddr_reg:x3; val_offset:84996*0 + 3*684*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84996*0 + 3*684*FLEN/8, x4, x1, x2)

inst_28333:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121a1a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121a1a; op2val:0x0;
op3val:0xf7fffff; valaddr_reg:x3; val_offset:84999*0 + 3*685*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 84999*0 + 3*685*FLEN/8, x4, x1, x2)

inst_28334:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x1; valaddr_reg:x3; val_offset:85002*0 + 3*686*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85002*0 + 3*686*FLEN/8, x4, x1, x2)

inst_28335:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x3; valaddr_reg:x3; val_offset:85005*0 + 3*687*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85005*0 + 3*687*FLEN/8, x4, x1, x2)

inst_28336:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x7; valaddr_reg:x3; val_offset:85008*0 + 3*688*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85008*0 + 3*688*FLEN/8, x4, x1, x2)

inst_28337:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x199999; valaddr_reg:x3; val_offset:85011*0 + 3*689*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85011*0 + 3*689*FLEN/8, x4, x1, x2)

inst_28338:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x249249; valaddr_reg:x3; val_offset:85014*0 + 3*690*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85014*0 + 3*690*FLEN/8, x4, x1, x2)

inst_28339:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x333333; valaddr_reg:x3; val_offset:85017*0 + 3*691*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85017*0 + 3*691*FLEN/8, x4, x1, x2)

inst_28340:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x36db6d; valaddr_reg:x3; val_offset:85020*0 + 3*692*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85020*0 + 3*692*FLEN/8, x4, x1, x2)

inst_28341:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x3bbbbb; valaddr_reg:x3; val_offset:85023*0 + 3*693*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85023*0 + 3*693*FLEN/8, x4, x1, x2)

inst_28342:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x444444; valaddr_reg:x3; val_offset:85026*0 + 3*694*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85026*0 + 3*694*FLEN/8, x4, x1, x2)

inst_28343:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x4ccccc; valaddr_reg:x3; val_offset:85029*0 + 3*695*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85029*0 + 3*695*FLEN/8, x4, x1, x2)

inst_28344:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x5b6db6; valaddr_reg:x3; val_offset:85032*0 + 3*696*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85032*0 + 3*696*FLEN/8, x4, x1, x2)

inst_28345:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x666666; valaddr_reg:x3; val_offset:85035*0 + 3*697*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85035*0 + 3*697*FLEN/8, x4, x1, x2)

inst_28346:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x6db6db; valaddr_reg:x3; val_offset:85038*0 + 3*698*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85038*0 + 3*698*FLEN/8, x4, x1, x2)

inst_28347:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x7ffff8; valaddr_reg:x3; val_offset:85041*0 + 3*699*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85041*0 + 3*699*FLEN/8, x4, x1, x2)

inst_28348:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x7ffffc; valaddr_reg:x3; val_offset:85044*0 + 3*700*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85044*0 + 3*700*FLEN/8, x4, x1, x2)

inst_28349:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x7ffffe; valaddr_reg:x3; val_offset:85047*0 + 3*701*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85047*0 + 3*701*FLEN/8, x4, x1, x2)

inst_28350:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x02 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x1000000; valaddr_reg:x3; val_offset:85050*0 + 3*702*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85050*0 + 3*702*FLEN/8, x4, x1, x2)

inst_28351:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x02 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x1000001; valaddr_reg:x3; val_offset:85053*0 + 3*703*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85053*0 + 3*703*FLEN/8, x4, x1, x2)

inst_28352:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x02 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x1000003; valaddr_reg:x3; val_offset:85056*0 + 3*704*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85056*0 + 3*704*FLEN/8, x4, x1, x2)

inst_28353:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x02 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x1000007; valaddr_reg:x3; val_offset:85059*0 + 3*705*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85059*0 + 3*705*FLEN/8, x4, x1, x2)

inst_28354:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x02 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x100000f; valaddr_reg:x3; val_offset:85062*0 + 3*706*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85062*0 + 3*706*FLEN/8, x4, x1, x2)

inst_28355:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x02 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x100001f; valaddr_reg:x3; val_offset:85065*0 + 3*707*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85065*0 + 3*707*FLEN/8, x4, x1, x2)

inst_28356:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x02 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x100003f; valaddr_reg:x3; val_offset:85068*0 + 3*708*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85068*0 + 3*708*FLEN/8, x4, x1, x2)

inst_28357:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x02 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x100007f; valaddr_reg:x3; val_offset:85071*0 + 3*709*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85071*0 + 3*709*FLEN/8, x4, x1, x2)

inst_28358:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x02 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x10000ff; valaddr_reg:x3; val_offset:85074*0 + 3*710*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85074*0 + 3*710*FLEN/8, x4, x1, x2)

inst_28359:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x02 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x10001ff; valaddr_reg:x3; val_offset:85077*0 + 3*711*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85077*0 + 3*711*FLEN/8, x4, x1, x2)

inst_28360:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x02 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x10003ff; valaddr_reg:x3; val_offset:85080*0 + 3*712*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85080*0 + 3*712*FLEN/8, x4, x1, x2)

inst_28361:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x02 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x10007ff; valaddr_reg:x3; val_offset:85083*0 + 3*713*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85083*0 + 3*713*FLEN/8, x4, x1, x2)

inst_28362:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x02 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x1000fff; valaddr_reg:x3; val_offset:85086*0 + 3*714*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85086*0 + 3*714*FLEN/8, x4, x1, x2)

inst_28363:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x02 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x1001fff; valaddr_reg:x3; val_offset:85089*0 + 3*715*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85089*0 + 3*715*FLEN/8, x4, x1, x2)

inst_28364:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x02 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x1003fff; valaddr_reg:x3; val_offset:85092*0 + 3*716*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85092*0 + 3*716*FLEN/8, x4, x1, x2)

inst_28365:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x02 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x1007fff; valaddr_reg:x3; val_offset:85095*0 + 3*717*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85095*0 + 3*717*FLEN/8, x4, x1, x2)

inst_28366:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x02 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x100ffff; valaddr_reg:x3; val_offset:85098*0 + 3*718*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85098*0 + 3*718*FLEN/8, x4, x1, x2)

inst_28367:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x02 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x101ffff; valaddr_reg:x3; val_offset:85101*0 + 3*719*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85101*0 + 3*719*FLEN/8, x4, x1, x2)

inst_28368:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x02 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x103ffff; valaddr_reg:x3; val_offset:85104*0 + 3*720*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85104*0 + 3*720*FLEN/8, x4, x1, x2)

inst_28369:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x02 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x107ffff; valaddr_reg:x3; val_offset:85107*0 + 3*721*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85107*0 + 3*721*FLEN/8, x4, x1, x2)

inst_28370:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x02 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x10fffff; valaddr_reg:x3; val_offset:85110*0 + 3*722*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85110*0 + 3*722*FLEN/8, x4, x1, x2)

inst_28371:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x02 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x11fffff; valaddr_reg:x3; val_offset:85113*0 + 3*723*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85113*0 + 3*723*FLEN/8, x4, x1, x2)

inst_28372:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x02 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x13fffff; valaddr_reg:x3; val_offset:85116*0 + 3*724*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85116*0 + 3*724*FLEN/8, x4, x1, x2)

inst_28373:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x02 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x1400000; valaddr_reg:x3; val_offset:85119*0 + 3*725*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85119*0 + 3*725*FLEN/8, x4, x1, x2)

inst_28374:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x02 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x1600000; valaddr_reg:x3; val_offset:85122*0 + 3*726*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85122*0 + 3*726*FLEN/8, x4, x1, x2)

inst_28375:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x02 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x1700000; valaddr_reg:x3; val_offset:85125*0 + 3*727*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85125*0 + 3*727*FLEN/8, x4, x1, x2)

inst_28376:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x02 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x1780000; valaddr_reg:x3; val_offset:85128*0 + 3*728*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85128*0 + 3*728*FLEN/8, x4, x1, x2)

inst_28377:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x02 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x17c0000; valaddr_reg:x3; val_offset:85131*0 + 3*729*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85131*0 + 3*729*FLEN/8, x4, x1, x2)

inst_28378:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x02 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x17e0000; valaddr_reg:x3; val_offset:85134*0 + 3*730*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85134*0 + 3*730*FLEN/8, x4, x1, x2)

inst_28379:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x02 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x17f0000; valaddr_reg:x3; val_offset:85137*0 + 3*731*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85137*0 + 3*731*FLEN/8, x4, x1, x2)

inst_28380:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x02 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x17f8000; valaddr_reg:x3; val_offset:85140*0 + 3*732*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85140*0 + 3*732*FLEN/8, x4, x1, x2)

inst_28381:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x02 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x17fc000; valaddr_reg:x3; val_offset:85143*0 + 3*733*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85143*0 + 3*733*FLEN/8, x4, x1, x2)

inst_28382:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x02 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x17fe000; valaddr_reg:x3; val_offset:85146*0 + 3*734*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85146*0 + 3*734*FLEN/8, x4, x1, x2)

inst_28383:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x02 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x17ff000; valaddr_reg:x3; val_offset:85149*0 + 3*735*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85149*0 + 3*735*FLEN/8, x4, x1, x2)

inst_28384:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x02 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x17ff800; valaddr_reg:x3; val_offset:85152*0 + 3*736*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85152*0 + 3*736*FLEN/8, x4, x1, x2)

inst_28385:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x02 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x17ffc00; valaddr_reg:x3; val_offset:85155*0 + 3*737*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85155*0 + 3*737*FLEN/8, x4, x1, x2)

inst_28386:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x02 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x17ffe00; valaddr_reg:x3; val_offset:85158*0 + 3*738*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85158*0 + 3*738*FLEN/8, x4, x1, x2)

inst_28387:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x02 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x17fff00; valaddr_reg:x3; val_offset:85161*0 + 3*739*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85161*0 + 3*739*FLEN/8, x4, x1, x2)

inst_28388:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x02 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x17fff80; valaddr_reg:x3; val_offset:85164*0 + 3*740*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85164*0 + 3*740*FLEN/8, x4, x1, x2)

inst_28389:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x02 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x17fffc0; valaddr_reg:x3; val_offset:85167*0 + 3*741*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85167*0 + 3*741*FLEN/8, x4, x1, x2)

inst_28390:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x02 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x17fffe0; valaddr_reg:x3; val_offset:85170*0 + 3*742*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85170*0 + 3*742*FLEN/8, x4, x1, x2)

inst_28391:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x02 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x17ffff0; valaddr_reg:x3; val_offset:85173*0 + 3*743*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85173*0 + 3*743*FLEN/8, x4, x1, x2)

inst_28392:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x02 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x17ffff8; valaddr_reg:x3; val_offset:85176*0 + 3*744*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85176*0 + 3*744*FLEN/8, x4, x1, x2)

inst_28393:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x02 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x17ffffc; valaddr_reg:x3; val_offset:85179*0 + 3*745*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85179*0 + 3*745*FLEN/8, x4, x1, x2)

inst_28394:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x02 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x17ffffe; valaddr_reg:x3; val_offset:85182*0 + 3*746*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85182*0 + 3*746*FLEN/8, x4, x1, x2)

inst_28395:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121ad3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x02 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121ad3; op2val:0x0;
op3val:0x17fffff; valaddr_reg:x3; val_offset:85185*0 + 3*747*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85185*0 + 3*747*FLEN/8, x4, x1, x2)

inst_28396:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121fe5 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x603f39 and fs3 == 0 and fe3 == 0xbf and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121fe5; op2val:0x3fe03f39;
op3val:0x5f800000; valaddr_reg:x3; val_offset:85188*0 + 3*748*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85188*0 + 3*748*FLEN/8, x4, x1, x2)

inst_28397:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121fe5 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x603f39 and fs3 == 0 and fe3 == 0xbf and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121fe5; op2val:0x3fe03f39;
op3val:0x5f800001; valaddr_reg:x3; val_offset:85191*0 + 3*749*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85191*0 + 3*749*FLEN/8, x4, x1, x2)

inst_28398:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121fe5 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x603f39 and fs3 == 0 and fe3 == 0xbf and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121fe5; op2val:0x3fe03f39;
op3val:0x5f800003; valaddr_reg:x3; val_offset:85194*0 + 3*750*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85194*0 + 3*750*FLEN/8, x4, x1, x2)

inst_28399:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121fe5 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x603f39 and fs3 == 0 and fe3 == 0xbf and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121fe5; op2val:0x3fe03f39;
op3val:0x5f800007; valaddr_reg:x3; val_offset:85197*0 + 3*751*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85197*0 + 3*751*FLEN/8, x4, x1, x2)

inst_28400:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121fe5 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x603f39 and fs3 == 0 and fe3 == 0xbf and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121fe5; op2val:0x3fe03f39;
op3val:0x5f80000f; valaddr_reg:x3; val_offset:85200*0 + 3*752*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85200*0 + 3*752*FLEN/8, x4, x1, x2)

inst_28401:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121fe5 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x603f39 and fs3 == 0 and fe3 == 0xbf and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121fe5; op2val:0x3fe03f39;
op3val:0x5f80001f; valaddr_reg:x3; val_offset:85203*0 + 3*753*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85203*0 + 3*753*FLEN/8, x4, x1, x2)

inst_28402:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121fe5 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x603f39 and fs3 == 0 and fe3 == 0xbf and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121fe5; op2val:0x3fe03f39;
op3val:0x5f80003f; valaddr_reg:x3; val_offset:85206*0 + 3*754*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85206*0 + 3*754*FLEN/8, x4, x1, x2)

inst_28403:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121fe5 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x603f39 and fs3 == 0 and fe3 == 0xbf and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121fe5; op2val:0x3fe03f39;
op3val:0x5f80007f; valaddr_reg:x3; val_offset:85209*0 + 3*755*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85209*0 + 3*755*FLEN/8, x4, x1, x2)

inst_28404:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121fe5 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x603f39 and fs3 == 0 and fe3 == 0xbf and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121fe5; op2val:0x3fe03f39;
op3val:0x5f8000ff; valaddr_reg:x3; val_offset:85212*0 + 3*756*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85212*0 + 3*756*FLEN/8, x4, x1, x2)

inst_28405:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121fe5 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x603f39 and fs3 == 0 and fe3 == 0xbf and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121fe5; op2val:0x3fe03f39;
op3val:0x5f8001ff; valaddr_reg:x3; val_offset:85215*0 + 3*757*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85215*0 + 3*757*FLEN/8, x4, x1, x2)

inst_28406:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121fe5 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x603f39 and fs3 == 0 and fe3 == 0xbf and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121fe5; op2val:0x3fe03f39;
op3val:0x5f8003ff; valaddr_reg:x3; val_offset:85218*0 + 3*758*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85218*0 + 3*758*FLEN/8, x4, x1, x2)

inst_28407:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121fe5 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x603f39 and fs3 == 0 and fe3 == 0xbf and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121fe5; op2val:0x3fe03f39;
op3val:0x5f8007ff; valaddr_reg:x3; val_offset:85221*0 + 3*759*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85221*0 + 3*759*FLEN/8, x4, x1, x2)

inst_28408:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121fe5 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x603f39 and fs3 == 0 and fe3 == 0xbf and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121fe5; op2val:0x3fe03f39;
op3val:0x5f800fff; valaddr_reg:x3; val_offset:85224*0 + 3*760*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85224*0 + 3*760*FLEN/8, x4, x1, x2)

inst_28409:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121fe5 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x603f39 and fs3 == 0 and fe3 == 0xbf and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121fe5; op2val:0x3fe03f39;
op3val:0x5f801fff; valaddr_reg:x3; val_offset:85227*0 + 3*761*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85227*0 + 3*761*FLEN/8, x4, x1, x2)

inst_28410:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121fe5 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x603f39 and fs3 == 0 and fe3 == 0xbf and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121fe5; op2val:0x3fe03f39;
op3val:0x5f803fff; valaddr_reg:x3; val_offset:85230*0 + 3*762*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85230*0 + 3*762*FLEN/8, x4, x1, x2)

inst_28411:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121fe5 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x603f39 and fs3 == 0 and fe3 == 0xbf and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121fe5; op2val:0x3fe03f39;
op3val:0x5f807fff; valaddr_reg:x3; val_offset:85233*0 + 3*763*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85233*0 + 3*763*FLEN/8, x4, x1, x2)

inst_28412:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121fe5 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x603f39 and fs3 == 0 and fe3 == 0xbf and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121fe5; op2val:0x3fe03f39;
op3val:0x5f80ffff; valaddr_reg:x3; val_offset:85236*0 + 3*764*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85236*0 + 3*764*FLEN/8, x4, x1, x2)

inst_28413:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121fe5 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x603f39 and fs3 == 0 and fe3 == 0xbf and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121fe5; op2val:0x3fe03f39;
op3val:0x5f81ffff; valaddr_reg:x3; val_offset:85239*0 + 3*765*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85239*0 + 3*765*FLEN/8, x4, x1, x2)

inst_28414:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121fe5 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x603f39 and fs3 == 0 and fe3 == 0xbf and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121fe5; op2val:0x3fe03f39;
op3val:0x5f83ffff; valaddr_reg:x3; val_offset:85242*0 + 3*766*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85242*0 + 3*766*FLEN/8, x4, x1, x2)

inst_28415:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x121fe5 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x603f39 and fs3 == 0 and fe3 == 0xbf and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7f121fe5; op2val:0x3fe03f39;
op3val:0x5f87ffff; valaddr_reg:x3; val_offset:85245*0 + 3*767*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 85245*0 + 3*767*FLEN/8, x4, x1, x2)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0x7f0eaf24,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffff8,32,FLEN)
NAN_BOXED(0x7f0eaf24,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffc,32,FLEN)
NAN_BOXED(0x7f0eaf24,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffe,32,FLEN)
NAN_BOXED(0x7f0eaf24,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x82000000,32,FLEN)
NAN_BOXED(0x7f0eaf24,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x82000001,32,FLEN)
NAN_BOXED(0x7f0eaf24,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x82000003,32,FLEN)
NAN_BOXED(0x7f0eaf24,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x82000007,32,FLEN)
NAN_BOXED(0x7f0eaf24,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8200000f,32,FLEN)
NAN_BOXED(0x7f0eaf24,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8200001f,32,FLEN)
NAN_BOXED(0x7f0eaf24,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8200003f,32,FLEN)
NAN_BOXED(0x7f0eaf24,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8200007f,32,FLEN)
NAN_BOXED(0x7f0eaf24,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x820000ff,32,FLEN)
NAN_BOXED(0x7f0eaf24,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x820001ff,32,FLEN)
NAN_BOXED(0x7f0eaf24,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x820003ff,32,FLEN)
NAN_BOXED(0x7f0eaf24,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x820007ff,32,FLEN)
NAN_BOXED(0x7f0eaf24,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x82000fff,32,FLEN)
NAN_BOXED(0x7f0eaf24,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x82001fff,32,FLEN)
NAN_BOXED(0x7f0eaf24,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x82003fff,32,FLEN)
NAN_BOXED(0x7f0eaf24,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x82007fff,32,FLEN)
NAN_BOXED(0x7f0eaf24,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8200ffff,32,FLEN)
NAN_BOXED(0x7f0eaf24,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8201ffff,32,FLEN)
NAN_BOXED(0x7f0eaf24,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8203ffff,32,FLEN)
NAN_BOXED(0x7f0eaf24,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8207ffff,32,FLEN)
NAN_BOXED(0x7f0eaf24,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x820fffff,32,FLEN)
NAN_BOXED(0x7f0eaf24,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x821fffff,32,FLEN)
NAN_BOXED(0x7f0eaf24,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x823fffff,32,FLEN)
NAN_BOXED(0x7f0eaf24,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x82400000,32,FLEN)
NAN_BOXED(0x7f0eaf24,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x82600000,32,FLEN)
NAN_BOXED(0x7f0eaf24,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x82700000,32,FLEN)
NAN_BOXED(0x7f0eaf24,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x82780000,32,FLEN)
NAN_BOXED(0x7f0eaf24,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x827c0000,32,FLEN)
NAN_BOXED(0x7f0eaf24,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x827e0000,32,FLEN)
NAN_BOXED(0x7f0eaf24,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x827f0000,32,FLEN)
NAN_BOXED(0x7f0eaf24,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x827f8000,32,FLEN)
NAN_BOXED(0x7f0eaf24,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x827fc000,32,FLEN)
NAN_BOXED(0x7f0eaf24,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x827fe000,32,FLEN)
NAN_BOXED(0x7f0eaf24,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x827ff000,32,FLEN)
NAN_BOXED(0x7f0eaf24,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x827ff800,32,FLEN)
NAN_BOXED(0x7f0eaf24,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x827ffc00,32,FLEN)
NAN_BOXED(0x7f0eaf24,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x827ffe00,32,FLEN)
NAN_BOXED(0x7f0eaf24,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x827fff00,32,FLEN)
NAN_BOXED(0x7f0eaf24,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x827fff80,32,FLEN)
NAN_BOXED(0x7f0eaf24,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x827fffc0,32,FLEN)
NAN_BOXED(0x7f0eaf24,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x827fffe0,32,FLEN)
NAN_BOXED(0x7f0eaf24,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x827ffff0,32,FLEN)
NAN_BOXED(0x7f0eaf24,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x827ffff8,32,FLEN)
NAN_BOXED(0x7f0eaf24,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x827ffffc,32,FLEN)
NAN_BOXED(0x7f0eaf24,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x827ffffe,32,FLEN)
NAN_BOXED(0x7f0eaf24,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x827fffff,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000001,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000003,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000007,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80199999,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80249249,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80333333,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8036db6d,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x803bbbbb,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80444444,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x804ccccc,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x805b6db6,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80666666,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x806db6db,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffff8,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffc,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffe,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89800000,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89800001,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89800003,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89800007,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8980000f,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8980001f,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8980003f,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8980007f,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x898000ff,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x898001ff,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x898003ff,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x898007ff,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89800fff,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89801fff,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89803fff,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89807fff,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8980ffff,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8981ffff,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8983ffff,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8987ffff,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x898fffff,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x899fffff,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89bfffff,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89c00000,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89e00000,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89f00000,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89f80000,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89fc0000,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89fe0000,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89ff0000,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89ff8000,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89ffc000,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89ffe000,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89fff000,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89fff800,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89fffc00,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89fffe00,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89ffff00,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89ffff80,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89ffffc0,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89ffffe0,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89fffff0,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89fffff8,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89fffffc,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89fffffe,32,FLEN)
NAN_BOXED(0x7f0ecbd9,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89ffffff,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x6e800000,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x6e800001,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x6e800003,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x6e800007,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x6e80000f,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x6e80001f,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x6e80003f,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x6e80007f,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x6e8000ff,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x6e8001ff,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x6e8003ff,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x6e8007ff,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x6e800fff,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x6e801fff,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x6e803fff,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x6e807fff,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x6e80ffff,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x6e81ffff,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x6e83ffff,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x6e87ffff,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x6e8fffff,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x6e9fffff,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x6ebfffff,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x6ec00000,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x6ee00000,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x6ef00000,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x6ef80000,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x6efc0000,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x6efe0000,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x6eff0000,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x6eff8000,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x6effc000,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x6effe000,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x6efff000,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x6efff800,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x6efffc00,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x6efffe00,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x6effff00,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x6effff80,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x6effffc0,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x6effffe0,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x6efffff0,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x6efffff8,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x6efffffc,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x6efffffe,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x6effffff,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x7f000001,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x7f000003,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x7f000007,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x7f199999,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x7f249249,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x7f333333,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x7f36db6d,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x7f3bbbbb,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x7f444444,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x7f4ccccc,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x7f5b6db6,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x7f666666,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x7f6db6db,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x7f7ffff8,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x7f7ffffc,32,FLEN)
NAN_BOXED(0x7f0ef815,32,FLEN)
NAN_BOXED(0x3fe53247,32,FLEN)
NAN_BOXED(0x7f7ffffe,32,FLEN)
NAN_BOXED(0x7f0f3001,32,FLEN)
NAN_BOXED(0x3fe4d8c4,32,FLEN)
NAN_BOXED(0x77000000,32,FLEN)
NAN_BOXED(0x7f0f3001,32,FLEN)
NAN_BOXED(0x3fe4d8c4,32,FLEN)
NAN_BOXED(0x77000001,32,FLEN)
NAN_BOXED(0x7f0f3001,32,FLEN)
NAN_BOXED(0x3fe4d8c4,32,FLEN)
NAN_BOXED(0x77000003,32,FLEN)
NAN_BOXED(0x7f0f3001,32,FLEN)
NAN_BOXED(0x3fe4d8c4,32,FLEN)
NAN_BOXED(0x77000007,32,FLEN)
NAN_BOXED(0x7f0f3001,32,FLEN)
NAN_BOXED(0x3fe4d8c4,32,FLEN)
NAN_BOXED(0x7700000f,32,FLEN)
NAN_BOXED(0x7f0f3001,32,FLEN)
NAN_BOXED(0x3fe4d8c4,32,FLEN)
NAN_BOXED(0x7700001f,32,FLEN)
NAN_BOXED(0x7f0f3001,32,FLEN)
NAN_BOXED(0x3fe4d8c4,32,FLEN)
NAN_BOXED(0x7700003f,32,FLEN)
NAN_BOXED(0x7f0f3001,32,FLEN)
NAN_BOXED(0x3fe4d8c4,32,FLEN)
NAN_BOXED(0x7700007f,32,FLEN)
NAN_BOXED(0x7f0f3001,32,FLEN)
NAN_BOXED(0x3fe4d8c4,32,FLEN)
NAN_BOXED(0x770000ff,32,FLEN)
NAN_BOXED(0x7f0f3001,32,FLEN)
NAN_BOXED(0x3fe4d8c4,32,FLEN)
NAN_BOXED(0x770001ff,32,FLEN)
NAN_BOXED(0x7f0f3001,32,FLEN)
NAN_BOXED(0x3fe4d8c4,32,FLEN)
NAN_BOXED(0x770003ff,32,FLEN)
NAN_BOXED(0x7f0f3001,32,FLEN)
NAN_BOXED(0x3fe4d8c4,32,FLEN)
NAN_BOXED(0x770007ff,32,FLEN)
NAN_BOXED(0x7f0f3001,32,FLEN)
NAN_BOXED(0x3fe4d8c4,32,FLEN)
NAN_BOXED(0x77000fff,32,FLEN)
NAN_BOXED(0x7f0f3001,32,FLEN)
NAN_BOXED(0x3fe4d8c4,32,FLEN)
NAN_BOXED(0x77001fff,32,FLEN)
NAN_BOXED(0x7f0f3001,32,FLEN)
NAN_BOXED(0x3fe4d8c4,32,FLEN)
NAN_BOXED(0x77003fff,32,FLEN)
NAN_BOXED(0x7f0f3001,32,FLEN)
NAN_BOXED(0x3fe4d8c4,32,FLEN)
NAN_BOXED(0x77007fff,32,FLEN)
NAN_BOXED(0x7f0f3001,32,FLEN)
NAN_BOXED(0x3fe4d8c4,32,FLEN)
NAN_BOXED(0x7700ffff,32,FLEN)
NAN_BOXED(0x7f0f3001,32,FLEN)
NAN_BOXED(0x3fe4d8c4,32,FLEN)
NAN_BOXED(0x7701ffff,32,FLEN)
NAN_BOXED(0x7f0f3001,32,FLEN)
NAN_BOXED(0x3fe4d8c4,32,FLEN)
NAN_BOXED(0x7703ffff,32,FLEN)
NAN_BOXED(0x7f0f3001,32,FLEN)
NAN_BOXED(0x3fe4d8c4,32,FLEN)
NAN_BOXED(0x7707ffff,32,FLEN)
NAN_BOXED(0x7f0f3001,32,FLEN)
NAN_BOXED(0x3fe4d8c4,32,FLEN)
NAN_BOXED(0x770fffff,32,FLEN)
NAN_BOXED(0x7f0f3001,32,FLEN)
NAN_BOXED(0x3fe4d8c4,32,FLEN)
NAN_BOXED(0x771fffff,32,FLEN)
NAN_BOXED(0x7f0f3001,32,FLEN)
NAN_BOXED(0x3fe4d8c4,32,FLEN)
NAN_BOXED(0x773fffff,32,FLEN)
NAN_BOXED(0x7f0f3001,32,FLEN)
NAN_BOXED(0x3fe4d8c4,32,FLEN)
NAN_BOXED(0x77400000,32,FLEN)
NAN_BOXED(0x7f0f3001,32,FLEN)
NAN_BOXED(0x3fe4d8c4,32,FLEN)
NAN_BOXED(0x77600000,32,FLEN)
NAN_BOXED(0x7f0f3001,32,FLEN)
NAN_BOXED(0x3fe4d8c4,32,FLEN)
NAN_BOXED(0x77700000,32,FLEN)
NAN_BOXED(0x7f0f3001,32,FLEN)
NAN_BOXED(0x3fe4d8c4,32,FLEN)
NAN_BOXED(0x77780000,32,FLEN)
NAN_BOXED(0x7f0f3001,32,FLEN)
NAN_BOXED(0x3fe4d8c4,32,FLEN)
NAN_BOXED(0x777c0000,32,FLEN)
NAN_BOXED(0x7f0f3001,32,FLEN)
NAN_BOXED(0x3fe4d8c4,32,FLEN)
NAN_BOXED(0x777e0000,32,FLEN)
NAN_BOXED(0x7f0f3001,32,FLEN)
NAN_BOXED(0x3fe4d8c4,32,FLEN)
NAN_BOXED(0x777f0000,32,FLEN)
NAN_BOXED(0x7f0f3001,32,FLEN)
NAN_BOXED(0x3fe4d8c4,32,FLEN)
NAN_BOXED(0x777f8000,32,FLEN)
NAN_BOXED(0x7f0f3001,32,FLEN)
NAN_BOXED(0x3fe4d8c4,32,FLEN)
NAN_BOXED(0x777fc000,32,FLEN)
NAN_BOXED(0x7f0f3001,32,FLEN)
NAN_BOXED(0x3fe4d8c4,32,FLEN)
NAN_BOXED(0x777fe000,32,FLEN)
NAN_BOXED(0x7f0f3001,32,FLEN)
NAN_BOXED(0x3fe4d8c4,32,FLEN)
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NAN_BOXED(0x7f0f3001,32,FLEN)
NAN_BOXED(0x3fe4d8c4,32,FLEN)
NAN_BOXED(0x777ff800,32,FLEN)
NAN_BOXED(0x7f0f3001,32,FLEN)
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NAN_BOXED(0x3fe4d8c4,32,FLEN)
NAN_BOXED(0x777ffe00,32,FLEN)
NAN_BOXED(0x7f0f3001,32,FLEN)
NAN_BOXED(0x3fe4d8c4,32,FLEN)
NAN_BOXED(0x777fff00,32,FLEN)
NAN_BOXED(0x7f0f3001,32,FLEN)
NAN_BOXED(0x3fe4d8c4,32,FLEN)
NAN_BOXED(0x777fff80,32,FLEN)
NAN_BOXED(0x7f0f3001,32,FLEN)
NAN_BOXED(0x3fe4d8c4,32,FLEN)
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NAN_BOXED(0x3fe4d8c4,32,FLEN)
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NAN_BOXED(0x7f0f3001,32,FLEN)
NAN_BOXED(0x3fe4d8c4,32,FLEN)
NAN_BOXED(0x777ffff0,32,FLEN)
NAN_BOXED(0x7f0f3001,32,FLEN)
NAN_BOXED(0x3fe4d8c4,32,FLEN)
NAN_BOXED(0x777ffff8,32,FLEN)
NAN_BOXED(0x7f0f3001,32,FLEN)
NAN_BOXED(0x3fe4d8c4,32,FLEN)
NAN_BOXED(0x777ffffc,32,FLEN)
NAN_BOXED(0x7f0f3001,32,FLEN)
NAN_BOXED(0x3fe4d8c4,32,FLEN)
NAN_BOXED(0x777ffffe,32,FLEN)
NAN_BOXED(0x7f0f3001,32,FLEN)
NAN_BOXED(0x3fe4d8c4,32,FLEN)
NAN_BOXED(0x777fffff,32,FLEN)
NAN_BOXED(0x7f0f3001,32,FLEN)
NAN_BOXED(0x3fe4d8c4,32,FLEN)
NAN_BOXED(0x7f000001,32,FLEN)
NAN_BOXED(0x7f0f3001,32,FLEN)
NAN_BOXED(0x3fe4d8c4,32,FLEN)
NAN_BOXED(0x7f000003,32,FLEN)
NAN_BOXED(0x7f0f3001,32,FLEN)
NAN_BOXED(0x3fe4d8c4,32,FLEN)
NAN_BOXED(0x7f000007,32,FLEN)
NAN_BOXED(0x7f0f3001,32,FLEN)
NAN_BOXED(0x3fe4d8c4,32,FLEN)
NAN_BOXED(0x7f199999,32,FLEN)
NAN_BOXED(0x7f0f3001,32,FLEN)
NAN_BOXED(0x3fe4d8c4,32,FLEN)
NAN_BOXED(0x7f249249,32,FLEN)
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NAN_BOXED(0x3fe4d8c4,32,FLEN)
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NAN_BOXED(0x7f0f3001,32,FLEN)
NAN_BOXED(0x3fe4d8c4,32,FLEN)
NAN_BOXED(0x7f36db6d,32,FLEN)
NAN_BOXED(0x7f0f3001,32,FLEN)
NAN_BOXED(0x3fe4d8c4,32,FLEN)
NAN_BOXED(0x7f3bbbbb,32,FLEN)
NAN_BOXED(0x7f0f3001,32,FLEN)
NAN_BOXED(0x3fe4d8c4,32,FLEN)
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NAN_BOXED(0x7f0fc3b6,32,FLEN)
NAN_BOXED(0x3fe3eda5,32,FLEN)
NAN_BOXED(0x7f000007,32,FLEN)
NAN_BOXED(0x7f0fc3b6,32,FLEN)
NAN_BOXED(0x3fe3eda5,32,FLEN)
NAN_BOXED(0x7f199999,32,FLEN)
NAN_BOXED(0x7f0fc3b6,32,FLEN)
NAN_BOXED(0x3fe3eda5,32,FLEN)
NAN_BOXED(0x7f249249,32,FLEN)
NAN_BOXED(0x7f0fc3b6,32,FLEN)
NAN_BOXED(0x3fe3eda5,32,FLEN)
NAN_BOXED(0x7f333333,32,FLEN)
NAN_BOXED(0x7f0fc3b6,32,FLEN)
NAN_BOXED(0x3fe3eda5,32,FLEN)
NAN_BOXED(0x7f36db6d,32,FLEN)
NAN_BOXED(0x7f0fc3b6,32,FLEN)
NAN_BOXED(0x3fe3eda5,32,FLEN)
NAN_BOXED(0x7f3bbbbb,32,FLEN)
NAN_BOXED(0x7f0fc3b6,32,FLEN)
NAN_BOXED(0x3fe3eda5,32,FLEN)
NAN_BOXED(0x7f444444,32,FLEN)
NAN_BOXED(0x7f0fc3b6,32,FLEN)
NAN_BOXED(0x3fe3eda5,32,FLEN)
NAN_BOXED(0x7f4ccccc,32,FLEN)
NAN_BOXED(0x7f0fc3b6,32,FLEN)
NAN_BOXED(0x3fe3eda5,32,FLEN)
NAN_BOXED(0x7f5b6db6,32,FLEN)
NAN_BOXED(0x7f0fc3b6,32,FLEN)
NAN_BOXED(0x3fe3eda5,32,FLEN)
NAN_BOXED(0x7f666666,32,FLEN)
NAN_BOXED(0x7f0fc3b6,32,FLEN)
NAN_BOXED(0x3fe3eda5,32,FLEN)
NAN_BOXED(0x7f6db6db,32,FLEN)
NAN_BOXED(0x7f0fc3b6,32,FLEN)
NAN_BOXED(0x3fe3eda5,32,FLEN)
NAN_BOXED(0x7f7ffff8,32,FLEN)
NAN_BOXED(0x7f0fc3b6,32,FLEN)
NAN_BOXED(0x3fe3eda5,32,FLEN)
NAN_BOXED(0x7f7ffffc,32,FLEN)
NAN_BOXED(0x7f0fc3b6,32,FLEN)
NAN_BOXED(0x3fe3eda5,32,FLEN)
NAN_BOXED(0x7f7ffffe,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000001,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000003,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000007,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80199999,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80249249,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80333333,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8036db6d,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x803bbbbb,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80444444,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x804ccccc,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x805b6db6,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80666666,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x806db6db,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffff8,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffc,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffe,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x88800000,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x88800001,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x88800003,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x88800007,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8880000f,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8880001f,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8880003f,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8880007f,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x888000ff,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x888001ff,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x888003ff,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x888007ff,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x88800fff,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x88801fff,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x88803fff,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x88807fff,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8880ffff,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8881ffff,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8883ffff,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8887ffff,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x888fffff,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x889fffff,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x88bfffff,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x88c00000,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x88e00000,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x88f00000,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x88f80000,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x88fc0000,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x88fe0000,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x88ff0000,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x88ff8000,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x88ffc000,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x88ffe000,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x88fff000,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x88fff800,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x88fffc00,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x88fffe00,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x88ffff00,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x88ffff80,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x88ffffc0,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x88ffffe0,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x88fffff0,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x88fffff8,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x88fffffc,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x88fffffe,32,FLEN)
NAN_BOXED(0x7f1023d1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x88ffffff,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x38800000,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x38800001,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x38800003,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x38800007,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x3880000f,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x3880001f,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x3880003f,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x3880007f,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x388000ff,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x388001ff,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x388003ff,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x388007ff,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x38800fff,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x38801fff,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x38803fff,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x38807fff,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x3880ffff,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x3881ffff,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x3883ffff,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x3887ffff,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x388fffff,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x389fffff,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x38bfffff,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x38c00000,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x38e00000,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x38f00000,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x38f80000,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x38fc0000,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x38fe0000,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x38ff0000,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x38ff8000,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x38ffc000,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x38ffe000,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x38fff000,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x38fff800,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x38fffc00,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x38fffe00,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x38ffff00,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x38ffff80,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x38ffffc0,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x38ffffe0,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x38fffff0,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x38fffff8,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x38fffffc,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x38fffffe,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x38ffffff,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x3f800001,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x3f800003,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x3f800007,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x3f999999,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x3fa49249,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x3fb33333,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x3fb6db6d,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x3fbbbbbb,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x3fc44444,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x3fcccccc,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x3fdb6db6,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x3fe66666,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x3fedb6db,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x3ffffff8,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x3ffffffc,32,FLEN)
NAN_BOXED(0x7f10cbbf,32,FLEN)
NAN_BOXED(0x389381,32,FLEN)
NAN_BOXED(0x3ffffffe,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80800001,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80800003,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80800007,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80999999,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80a49249,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80b33333,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80b6db6d,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80bbbbbb,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80c44444,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80cccccc,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80db6db6,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80e66666,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80edb6db,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80fffff8,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80fffffc,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80fffffe,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a800000,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a800001,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a800003,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a800007,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a80000f,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a80001f,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a80003f,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a80007f,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a8000ff,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a8001ff,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a8003ff,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a8007ff,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a800fff,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a801fff,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a803fff,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a807fff,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a80ffff,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a81ffff,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a83ffff,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a87ffff,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a8fffff,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8a9fffff,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8abfffff,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8ac00000,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8ae00000,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8af00000,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8af80000,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8afc0000,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8afe0000,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8aff0000,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8aff8000,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8affc000,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8affe000,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8afff000,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8afff800,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8afffc00,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8afffe00,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8affff00,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8affff80,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8affffc0,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8affffe0,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8afffff0,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8afffff8,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8afffffc,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8afffffe,32,FLEN)
NAN_BOXED(0x7f116cb0,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8affffff,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800001,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800003,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800007,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x999999,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa49249,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb33333,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb6db6d,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbbbbbb,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xc44444,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xcccccc,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xdb6db6,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe66666,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xedb6db,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffff8,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffffc,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffffe,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4000000,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4000001,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4000003,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4000007,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x400000f,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x400001f,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x400003f,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x400007f,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x40000ff,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x40001ff,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x40003ff,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x40007ff,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4000fff,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4001fff,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4003fff,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4007fff,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x400ffff,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x401ffff,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x403ffff,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x407ffff,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x40fffff,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x41fffff,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x43fffff,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4400000,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4600000,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4700000,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4780000,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x47c0000,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x47e0000,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x47f0000,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x47f8000,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x47fc000,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x47fe000,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x47ff000,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x47ff800,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x47ffc00,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x47ffe00,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x47fff00,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x47fff80,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x47fffc0,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x47fffe0,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x47ffff0,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x47ffff8,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x47ffffc,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x47ffffe,32,FLEN)
NAN_BOXED(0x7f117cee,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x47fffff,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x199999,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x249249,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x333333,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x36db6d,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3bbbbb,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x444444,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4ccccc,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5b6db6,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x666666,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6db6db,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffff8,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffc,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffe,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf000000,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf000001,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf000003,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf000007,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf00000f,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf00001f,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf00003f,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf00007f,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf0000ff,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf0001ff,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf0003ff,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf0007ff,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf000fff,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf001fff,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf003fff,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf007fff,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf00ffff,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf01ffff,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf03ffff,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf07ffff,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf0fffff,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf1fffff,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf3fffff,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf400000,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf600000,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf700000,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf780000,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7c0000,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7e0000,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7f0000,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7f8000,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7fc000,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7fe000,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7ff000,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7ff800,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7ffc00,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7ffe00,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7fff00,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7fff80,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7fffc0,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7fffe0,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7ffff0,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7ffff8,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7ffffc,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7ffffe,32,FLEN)
NAN_BOXED(0x7f121a1a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf7fffff,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x199999,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x249249,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x333333,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x36db6d,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3bbbbb,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x444444,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4ccccc,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5b6db6,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x666666,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6db6db,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffff8,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffc,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffe,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1000000,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1000001,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1000003,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1000007,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x100000f,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x100001f,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x100003f,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x100007f,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x10000ff,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x10001ff,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x10003ff,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x10007ff,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1000fff,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1001fff,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1003fff,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1007fff,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x100ffff,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x101ffff,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x103ffff,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x107ffff,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x10fffff,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x11fffff,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x13fffff,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1400000,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1600000,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1700000,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1780000,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x17c0000,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x17e0000,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x17f0000,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x17f8000,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x17fc000,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x17fe000,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x17ff000,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x17ff800,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x17ffc00,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x17ffe00,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x17fff00,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x17fff80,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x17fffc0,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x17fffe0,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x17ffff0,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x17ffff8,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x17ffffc,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x17ffffe,32,FLEN)
NAN_BOXED(0x7f121ad3,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x17fffff,32,FLEN)
NAN_BOXED(0x7f121fe5,32,FLEN)
NAN_BOXED(0x3fe03f39,32,FLEN)
NAN_BOXED(0x5f800000,32,FLEN)
NAN_BOXED(0x7f121fe5,32,FLEN)
NAN_BOXED(0x3fe03f39,32,FLEN)
NAN_BOXED(0x5f800001,32,FLEN)
NAN_BOXED(0x7f121fe5,32,FLEN)
NAN_BOXED(0x3fe03f39,32,FLEN)
NAN_BOXED(0x5f800003,32,FLEN)
NAN_BOXED(0x7f121fe5,32,FLEN)
NAN_BOXED(0x3fe03f39,32,FLEN)
NAN_BOXED(0x5f800007,32,FLEN)
NAN_BOXED(0x7f121fe5,32,FLEN)
NAN_BOXED(0x3fe03f39,32,FLEN)
NAN_BOXED(0x5f80000f,32,FLEN)
NAN_BOXED(0x7f121fe5,32,FLEN)
NAN_BOXED(0x3fe03f39,32,FLEN)
NAN_BOXED(0x5f80001f,32,FLEN)
NAN_BOXED(0x7f121fe5,32,FLEN)
NAN_BOXED(0x3fe03f39,32,FLEN)
NAN_BOXED(0x5f80003f,32,FLEN)
NAN_BOXED(0x7f121fe5,32,FLEN)
NAN_BOXED(0x3fe03f39,32,FLEN)
NAN_BOXED(0x5f80007f,32,FLEN)
NAN_BOXED(0x7f121fe5,32,FLEN)
NAN_BOXED(0x3fe03f39,32,FLEN)
NAN_BOXED(0x5f8000ff,32,FLEN)
NAN_BOXED(0x7f121fe5,32,FLEN)
NAN_BOXED(0x3fe03f39,32,FLEN)
NAN_BOXED(0x5f8001ff,32,FLEN)
NAN_BOXED(0x7f121fe5,32,FLEN)
NAN_BOXED(0x3fe03f39,32,FLEN)
NAN_BOXED(0x5f8003ff,32,FLEN)
NAN_BOXED(0x7f121fe5,32,FLEN)
NAN_BOXED(0x3fe03f39,32,FLEN)
NAN_BOXED(0x5f8007ff,32,FLEN)
NAN_BOXED(0x7f121fe5,32,FLEN)
NAN_BOXED(0x3fe03f39,32,FLEN)
NAN_BOXED(0x5f800fff,32,FLEN)
NAN_BOXED(0x7f121fe5,32,FLEN)
NAN_BOXED(0x3fe03f39,32,FLEN)
NAN_BOXED(0x5f801fff,32,FLEN)
NAN_BOXED(0x7f121fe5,32,FLEN)
NAN_BOXED(0x3fe03f39,32,FLEN)
NAN_BOXED(0x5f803fff,32,FLEN)
NAN_BOXED(0x7f121fe5,32,FLEN)
NAN_BOXED(0x3fe03f39,32,FLEN)
NAN_BOXED(0x5f807fff,32,FLEN)
NAN_BOXED(0x7f121fe5,32,FLEN)
NAN_BOXED(0x3fe03f39,32,FLEN)
NAN_BOXED(0x5f80ffff,32,FLEN)
NAN_BOXED(0x7f121fe5,32,FLEN)
NAN_BOXED(0x3fe03f39,32,FLEN)
NAN_BOXED(0x5f81ffff,32,FLEN)
NAN_BOXED(0x7f121fe5,32,FLEN)
NAN_BOXED(0x3fe03f39,32,FLEN)
NAN_BOXED(0x5f83ffff,32,FLEN)
NAN_BOXED(0x7f121fe5,32,FLEN)
NAN_BOXED(0x3fe03f39,32,FLEN)
NAN_BOXED(0x5f87ffff,32,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;


signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_2:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_3:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_4:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_5:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_6:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine

tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
    .fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;

#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif

sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
