
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.7.1
// timestamp : Fri Jun 17 14:17:59 2022 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /scratch/pawan/work/normalised/RV32F/fmadd.s.cgf \
 \
//                  -- xlen 32  \
//                  --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fmadd.s instruction of the RISC-V RV32F_Zicsr,RV32FD_Zicsr,RV64F_Zicsr,RV64FD_Zicsr extension for the fmadd_b15 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*);def TEST_CASE_1=True;",fmadd_b15)
RVTEST_CASE(1,"//check ISA:=regex(.*E.*F.*);def TEST_CASE_1=True;",fmadd_b15)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_17664:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x300757 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb00757; op2val:0x80000000;
op3val:0x8d0001ff; valaddr_reg:x3; val_offset:52992*0 + 3*-1*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 52992*0 + 3*0*FLEN/8, x4, x1, x2)

inst_17665:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x300757 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb00757; op2val:0x80000000;
op3val:0x8d0003ff; valaddr_reg:x3; val_offset:52995*0 + 3*0*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 52995*0 + 3*1*FLEN/8, x4, x1, x2)

inst_17666:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x300757 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb00757; op2val:0x80000000;
op3val:0x8d0007ff; valaddr_reg:x3; val_offset:52998*0 + 3*1*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 52998*0 + 3*2*FLEN/8, x4, x1, x2)

inst_17667:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x300757 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb00757; op2val:0x80000000;
op3val:0x8d000fff; valaddr_reg:x3; val_offset:53001*0 + 3*2*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53001*0 + 3*3*FLEN/8, x4, x1, x2)

inst_17668:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x300757 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb00757; op2val:0x80000000;
op3val:0x8d001fff; valaddr_reg:x3; val_offset:53004*0 + 3*3*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53004*0 + 3*4*FLEN/8, x4, x1, x2)

inst_17669:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x300757 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb00757; op2val:0x80000000;
op3val:0x8d003fff; valaddr_reg:x3; val_offset:53007*0 + 3*4*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53007*0 + 3*5*FLEN/8, x4, x1, x2)

inst_17670:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x300757 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb00757; op2val:0x80000000;
op3val:0x8d007fff; valaddr_reg:x3; val_offset:53010*0 + 3*5*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53010*0 + 3*6*FLEN/8, x4, x1, x2)

inst_17671:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x300757 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb00757; op2val:0x80000000;
op3val:0x8d00ffff; valaddr_reg:x3; val_offset:53013*0 + 3*6*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53013*0 + 3*7*FLEN/8, x4, x1, x2)

inst_17672:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x300757 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb00757; op2val:0x80000000;
op3val:0x8d01ffff; valaddr_reg:x3; val_offset:53016*0 + 3*7*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53016*0 + 3*8*FLEN/8, x4, x1, x2)

inst_17673:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x300757 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb00757; op2val:0x80000000;
op3val:0x8d03ffff; valaddr_reg:x3; val_offset:53019*0 + 3*8*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53019*0 + 3*9*FLEN/8, x4, x1, x2)

inst_17674:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x300757 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb00757; op2val:0x80000000;
op3val:0x8d07ffff; valaddr_reg:x3; val_offset:53022*0 + 3*9*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53022*0 + 3*10*FLEN/8, x4, x1, x2)

inst_17675:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x300757 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb00757; op2val:0x80000000;
op3val:0x8d0fffff; valaddr_reg:x3; val_offset:53025*0 + 3*10*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53025*0 + 3*11*FLEN/8, x4, x1, x2)

inst_17676:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x300757 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb00757; op2val:0x80000000;
op3val:0x8d1fffff; valaddr_reg:x3; val_offset:53028*0 + 3*11*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53028*0 + 3*12*FLEN/8, x4, x1, x2)

inst_17677:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x300757 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb00757; op2val:0x80000000;
op3val:0x8d3fffff; valaddr_reg:x3; val_offset:53031*0 + 3*12*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53031*0 + 3*13*FLEN/8, x4, x1, x2)

inst_17678:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x300757 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb00757; op2val:0x80000000;
op3val:0x8d400000; valaddr_reg:x3; val_offset:53034*0 + 3*13*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53034*0 + 3*14*FLEN/8, x4, x1, x2)

inst_17679:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x300757 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb00757; op2val:0x80000000;
op3val:0x8d600000; valaddr_reg:x3; val_offset:53037*0 + 3*14*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53037*0 + 3*15*FLEN/8, x4, x1, x2)

inst_17680:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x300757 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb00757; op2val:0x80000000;
op3val:0x8d700000; valaddr_reg:x3; val_offset:53040*0 + 3*15*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53040*0 + 3*16*FLEN/8, x4, x1, x2)

inst_17681:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x300757 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb00757; op2val:0x80000000;
op3val:0x8d780000; valaddr_reg:x3; val_offset:53043*0 + 3*16*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53043*0 + 3*17*FLEN/8, x4, x1, x2)

inst_17682:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x300757 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb00757; op2val:0x80000000;
op3val:0x8d7c0000; valaddr_reg:x3; val_offset:53046*0 + 3*17*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53046*0 + 3*18*FLEN/8, x4, x1, x2)

inst_17683:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x300757 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb00757; op2val:0x80000000;
op3val:0x8d7e0000; valaddr_reg:x3; val_offset:53049*0 + 3*18*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53049*0 + 3*19*FLEN/8, x4, x1, x2)

inst_17684:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x300757 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb00757; op2val:0x80000000;
op3val:0x8d7f0000; valaddr_reg:x3; val_offset:53052*0 + 3*19*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53052*0 + 3*20*FLEN/8, x4, x1, x2)

inst_17685:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x300757 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb00757; op2val:0x80000000;
op3val:0x8d7f8000; valaddr_reg:x3; val_offset:53055*0 + 3*20*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53055*0 + 3*21*FLEN/8, x4, x1, x2)

inst_17686:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x300757 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb00757; op2val:0x80000000;
op3val:0x8d7fc000; valaddr_reg:x3; val_offset:53058*0 + 3*21*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53058*0 + 3*22*FLEN/8, x4, x1, x2)

inst_17687:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x300757 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb00757; op2val:0x80000000;
op3val:0x8d7fe000; valaddr_reg:x3; val_offset:53061*0 + 3*22*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53061*0 + 3*23*FLEN/8, x4, x1, x2)

inst_17688:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x300757 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb00757; op2val:0x80000000;
op3val:0x8d7ff000; valaddr_reg:x3; val_offset:53064*0 + 3*23*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53064*0 + 3*24*FLEN/8, x4, x1, x2)

inst_17689:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x300757 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb00757; op2val:0x80000000;
op3val:0x8d7ff800; valaddr_reg:x3; val_offset:53067*0 + 3*24*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53067*0 + 3*25*FLEN/8, x4, x1, x2)

inst_17690:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x300757 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb00757; op2val:0x80000000;
op3val:0x8d7ffc00; valaddr_reg:x3; val_offset:53070*0 + 3*25*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53070*0 + 3*26*FLEN/8, x4, x1, x2)

inst_17691:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x300757 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb00757; op2val:0x80000000;
op3val:0x8d7ffe00; valaddr_reg:x3; val_offset:53073*0 + 3*26*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53073*0 + 3*27*FLEN/8, x4, x1, x2)

inst_17692:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x300757 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb00757; op2val:0x80000000;
op3val:0x8d7fff00; valaddr_reg:x3; val_offset:53076*0 + 3*27*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53076*0 + 3*28*FLEN/8, x4, x1, x2)

inst_17693:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x300757 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb00757; op2val:0x80000000;
op3val:0x8d7fff80; valaddr_reg:x3; val_offset:53079*0 + 3*28*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53079*0 + 3*29*FLEN/8, x4, x1, x2)

inst_17694:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x300757 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb00757; op2val:0x80000000;
op3val:0x8d7fffc0; valaddr_reg:x3; val_offset:53082*0 + 3*29*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53082*0 + 3*30*FLEN/8, x4, x1, x2)

inst_17695:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x300757 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb00757; op2val:0x80000000;
op3val:0x8d7fffe0; valaddr_reg:x3; val_offset:53085*0 + 3*30*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53085*0 + 3*31*FLEN/8, x4, x1, x2)

inst_17696:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x300757 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb00757; op2val:0x80000000;
op3val:0x8d7ffff0; valaddr_reg:x3; val_offset:53088*0 + 3*31*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53088*0 + 3*32*FLEN/8, x4, x1, x2)

inst_17697:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x300757 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb00757; op2val:0x80000000;
op3val:0x8d7ffff8; valaddr_reg:x3; val_offset:53091*0 + 3*32*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53091*0 + 3*33*FLEN/8, x4, x1, x2)

inst_17698:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x300757 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb00757; op2val:0x80000000;
op3val:0x8d7ffffc; valaddr_reg:x3; val_offset:53094*0 + 3*33*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53094*0 + 3*34*FLEN/8, x4, x1, x2)

inst_17699:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x300757 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb00757; op2val:0x80000000;
op3val:0x8d7ffffe; valaddr_reg:x3; val_offset:53097*0 + 3*34*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53097*0 + 3*35*FLEN/8, x4, x1, x2)

inst_17700:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x300757 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb00757; op2val:0x80000000;
op3val:0x8d7fffff; valaddr_reg:x3; val_offset:53100*0 + 3*35*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53100*0 + 3*36*FLEN/8, x4, x1, x2)

inst_17701:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xbf800001; valaddr_reg:x3; val_offset:53103*0 + 3*36*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53103*0 + 3*37*FLEN/8, x4, x1, x2)

inst_17702:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xbf800003; valaddr_reg:x3; val_offset:53106*0 + 3*37*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53106*0 + 3*38*FLEN/8, x4, x1, x2)

inst_17703:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xbf800007; valaddr_reg:x3; val_offset:53109*0 + 3*38*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53109*0 + 3*39*FLEN/8, x4, x1, x2)

inst_17704:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xbf999999; valaddr_reg:x3; val_offset:53112*0 + 3*39*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53112*0 + 3*40*FLEN/8, x4, x1, x2)

inst_17705:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xbfa49249; valaddr_reg:x3; val_offset:53115*0 + 3*40*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53115*0 + 3*41*FLEN/8, x4, x1, x2)

inst_17706:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xbfb33333; valaddr_reg:x3; val_offset:53118*0 + 3*41*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53118*0 + 3*42*FLEN/8, x4, x1, x2)

inst_17707:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xbfb6db6d; valaddr_reg:x3; val_offset:53121*0 + 3*42*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53121*0 + 3*43*FLEN/8, x4, x1, x2)

inst_17708:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xbfbbbbbb; valaddr_reg:x3; val_offset:53124*0 + 3*43*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53124*0 + 3*44*FLEN/8, x4, x1, x2)

inst_17709:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xbfc44444; valaddr_reg:x3; val_offset:53127*0 + 3*44*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53127*0 + 3*45*FLEN/8, x4, x1, x2)

inst_17710:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xbfcccccc; valaddr_reg:x3; val_offset:53130*0 + 3*45*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53130*0 + 3*46*FLEN/8, x4, x1, x2)

inst_17711:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xbfdb6db6; valaddr_reg:x3; val_offset:53133*0 + 3*46*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53133*0 + 3*47*FLEN/8, x4, x1, x2)

inst_17712:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xbfe66666; valaddr_reg:x3; val_offset:53136*0 + 3*47*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53136*0 + 3*48*FLEN/8, x4, x1, x2)

inst_17713:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xbfedb6db; valaddr_reg:x3; val_offset:53139*0 + 3*48*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53139*0 + 3*49*FLEN/8, x4, x1, x2)

inst_17714:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xbffffff8; valaddr_reg:x3; val_offset:53142*0 + 3*49*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53142*0 + 3*50*FLEN/8, x4, x1, x2)

inst_17715:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xbffffffc; valaddr_reg:x3; val_offset:53145*0 + 3*50*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53145*0 + 3*51*FLEN/8, x4, x1, x2)

inst_17716:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xbffffffe; valaddr_reg:x3; val_offset:53148*0 + 3*51*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53148*0 + 3*52*FLEN/8, x4, x1, x2)

inst_17717:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x93 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xc9800000; valaddr_reg:x3; val_offset:53151*0 + 3*52*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53151*0 + 3*53*FLEN/8, x4, x1, x2)

inst_17718:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x93 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xc9800001; valaddr_reg:x3; val_offset:53154*0 + 3*53*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53154*0 + 3*54*FLEN/8, x4, x1, x2)

inst_17719:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x93 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xc9800003; valaddr_reg:x3; val_offset:53157*0 + 3*54*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53157*0 + 3*55*FLEN/8, x4, x1, x2)

inst_17720:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x93 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xc9800007; valaddr_reg:x3; val_offset:53160*0 + 3*55*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53160*0 + 3*56*FLEN/8, x4, x1, x2)

inst_17721:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x93 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xc980000f; valaddr_reg:x3; val_offset:53163*0 + 3*56*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53163*0 + 3*57*FLEN/8, x4, x1, x2)

inst_17722:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x93 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xc980001f; valaddr_reg:x3; val_offset:53166*0 + 3*57*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53166*0 + 3*58*FLEN/8, x4, x1, x2)

inst_17723:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x93 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xc980003f; valaddr_reg:x3; val_offset:53169*0 + 3*58*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53169*0 + 3*59*FLEN/8, x4, x1, x2)

inst_17724:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x93 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xc980007f; valaddr_reg:x3; val_offset:53172*0 + 3*59*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53172*0 + 3*60*FLEN/8, x4, x1, x2)

inst_17725:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x93 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xc98000ff; valaddr_reg:x3; val_offset:53175*0 + 3*60*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53175*0 + 3*61*FLEN/8, x4, x1, x2)

inst_17726:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x93 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xc98001ff; valaddr_reg:x3; val_offset:53178*0 + 3*61*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53178*0 + 3*62*FLEN/8, x4, x1, x2)

inst_17727:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x93 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xc98003ff; valaddr_reg:x3; val_offset:53181*0 + 3*62*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53181*0 + 3*63*FLEN/8, x4, x1, x2)

inst_17728:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x93 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xc98007ff; valaddr_reg:x3; val_offset:53184*0 + 3*63*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53184*0 + 3*64*FLEN/8, x4, x1, x2)

inst_17729:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x93 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xc9800fff; valaddr_reg:x3; val_offset:53187*0 + 3*64*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53187*0 + 3*65*FLEN/8, x4, x1, x2)

inst_17730:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x93 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xc9801fff; valaddr_reg:x3; val_offset:53190*0 + 3*65*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53190*0 + 3*66*FLEN/8, x4, x1, x2)

inst_17731:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x93 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xc9803fff; valaddr_reg:x3; val_offset:53193*0 + 3*66*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53193*0 + 3*67*FLEN/8, x4, x1, x2)

inst_17732:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x93 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xc9807fff; valaddr_reg:x3; val_offset:53196*0 + 3*67*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53196*0 + 3*68*FLEN/8, x4, x1, x2)

inst_17733:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x93 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xc980ffff; valaddr_reg:x3; val_offset:53199*0 + 3*68*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53199*0 + 3*69*FLEN/8, x4, x1, x2)

inst_17734:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x93 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xc981ffff; valaddr_reg:x3; val_offset:53202*0 + 3*69*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53202*0 + 3*70*FLEN/8, x4, x1, x2)

inst_17735:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x93 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xc983ffff; valaddr_reg:x3; val_offset:53205*0 + 3*70*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53205*0 + 3*71*FLEN/8, x4, x1, x2)

inst_17736:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x93 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xc987ffff; valaddr_reg:x3; val_offset:53208*0 + 3*71*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53208*0 + 3*72*FLEN/8, x4, x1, x2)

inst_17737:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x93 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xc98fffff; valaddr_reg:x3; val_offset:53211*0 + 3*72*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53211*0 + 3*73*FLEN/8, x4, x1, x2)

inst_17738:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x93 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xc99fffff; valaddr_reg:x3; val_offset:53214*0 + 3*73*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53214*0 + 3*74*FLEN/8, x4, x1, x2)

inst_17739:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x93 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xc9bfffff; valaddr_reg:x3; val_offset:53217*0 + 3*74*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53217*0 + 3*75*FLEN/8, x4, x1, x2)

inst_17740:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x93 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xc9c00000; valaddr_reg:x3; val_offset:53220*0 + 3*75*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53220*0 + 3*76*FLEN/8, x4, x1, x2)

inst_17741:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x93 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xc9e00000; valaddr_reg:x3; val_offset:53223*0 + 3*76*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53223*0 + 3*77*FLEN/8, x4, x1, x2)

inst_17742:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x93 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xc9f00000; valaddr_reg:x3; val_offset:53226*0 + 3*77*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53226*0 + 3*78*FLEN/8, x4, x1, x2)

inst_17743:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x93 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xc9f80000; valaddr_reg:x3; val_offset:53229*0 + 3*78*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53229*0 + 3*79*FLEN/8, x4, x1, x2)

inst_17744:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x93 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xc9fc0000; valaddr_reg:x3; val_offset:53232*0 + 3*79*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53232*0 + 3*80*FLEN/8, x4, x1, x2)

inst_17745:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x93 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xc9fe0000; valaddr_reg:x3; val_offset:53235*0 + 3*80*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53235*0 + 3*81*FLEN/8, x4, x1, x2)

inst_17746:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x93 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xc9ff0000; valaddr_reg:x3; val_offset:53238*0 + 3*81*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53238*0 + 3*82*FLEN/8, x4, x1, x2)

inst_17747:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x93 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xc9ff8000; valaddr_reg:x3; val_offset:53241*0 + 3*82*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53241*0 + 3*83*FLEN/8, x4, x1, x2)

inst_17748:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x93 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xc9ffc000; valaddr_reg:x3; val_offset:53244*0 + 3*83*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53244*0 + 3*84*FLEN/8, x4, x1, x2)

inst_17749:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x93 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xc9ffe000; valaddr_reg:x3; val_offset:53247*0 + 3*84*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53247*0 + 3*85*FLEN/8, x4, x1, x2)

inst_17750:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x93 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xc9fff000; valaddr_reg:x3; val_offset:53250*0 + 3*85*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53250*0 + 3*86*FLEN/8, x4, x1, x2)

inst_17751:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x93 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xc9fff800; valaddr_reg:x3; val_offset:53253*0 + 3*86*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53253*0 + 3*87*FLEN/8, x4, x1, x2)

inst_17752:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x93 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xc9fffc00; valaddr_reg:x3; val_offset:53256*0 + 3*87*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53256*0 + 3*88*FLEN/8, x4, x1, x2)

inst_17753:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x93 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xc9fffe00; valaddr_reg:x3; val_offset:53259*0 + 3*88*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53259*0 + 3*89*FLEN/8, x4, x1, x2)

inst_17754:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x93 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xc9ffff00; valaddr_reg:x3; val_offset:53262*0 + 3*89*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53262*0 + 3*90*FLEN/8, x4, x1, x2)

inst_17755:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x93 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xc9ffff80; valaddr_reg:x3; val_offset:53265*0 + 3*90*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53265*0 + 3*91*FLEN/8, x4, x1, x2)

inst_17756:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x93 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xc9ffffc0; valaddr_reg:x3; val_offset:53268*0 + 3*91*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53268*0 + 3*92*FLEN/8, x4, x1, x2)

inst_17757:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x93 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xc9ffffe0; valaddr_reg:x3; val_offset:53271*0 + 3*92*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53271*0 + 3*93*FLEN/8, x4, x1, x2)

inst_17758:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x93 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xc9fffff0; valaddr_reg:x3; val_offset:53274*0 + 3*93*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53274*0 + 3*94*FLEN/8, x4, x1, x2)

inst_17759:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x93 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xc9fffff8; valaddr_reg:x3; val_offset:53277*0 + 3*94*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53277*0 + 3*95*FLEN/8, x4, x1, x2)

inst_17760:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x93 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xc9fffffc; valaddr_reg:x3; val_offset:53280*0 + 3*95*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53280*0 + 3*96*FLEN/8, x4, x1, x2)

inst_17761:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x93 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xc9fffffe; valaddr_reg:x3; val_offset:53283*0 + 3*96*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53283*0 + 3*97*FLEN/8, x4, x1, x2)

inst_17762:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x30208a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x5d0612 and fs3 == 1 and fe3 == 0x93 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb0208a; op2val:0x805d0612;
op3val:0xc9ffffff; valaddr_reg:x3; val_offset:53286*0 + 3*97*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53286*0 + 3*98*FLEN/8, x4, x1, x2)

inst_17763:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xd0 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xe8000000; valaddr_reg:x3; val_offset:53289*0 + 3*98*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53289*0 + 3*99*FLEN/8, x4, x1, x2)

inst_17764:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xd0 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xe8000001; valaddr_reg:x3; val_offset:53292*0 + 3*99*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53292*0 + 3*100*FLEN/8, x4, x1, x2)

inst_17765:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xd0 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xe8000003; valaddr_reg:x3; val_offset:53295*0 + 3*100*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53295*0 + 3*101*FLEN/8, x4, x1, x2)

inst_17766:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xd0 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xe8000007; valaddr_reg:x3; val_offset:53298*0 + 3*101*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53298*0 + 3*102*FLEN/8, x4, x1, x2)

inst_17767:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xd0 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xe800000f; valaddr_reg:x3; val_offset:53301*0 + 3*102*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53301*0 + 3*103*FLEN/8, x4, x1, x2)

inst_17768:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xd0 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xe800001f; valaddr_reg:x3; val_offset:53304*0 + 3*103*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53304*0 + 3*104*FLEN/8, x4, x1, x2)

inst_17769:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xd0 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xe800003f; valaddr_reg:x3; val_offset:53307*0 + 3*104*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53307*0 + 3*105*FLEN/8, x4, x1, x2)

inst_17770:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xd0 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xe800007f; valaddr_reg:x3; val_offset:53310*0 + 3*105*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53310*0 + 3*106*FLEN/8, x4, x1, x2)

inst_17771:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xd0 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xe80000ff; valaddr_reg:x3; val_offset:53313*0 + 3*106*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53313*0 + 3*107*FLEN/8, x4, x1, x2)

inst_17772:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xd0 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xe80001ff; valaddr_reg:x3; val_offset:53316*0 + 3*107*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53316*0 + 3*108*FLEN/8, x4, x1, x2)

inst_17773:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xd0 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xe80003ff; valaddr_reg:x3; val_offset:53319*0 + 3*108*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53319*0 + 3*109*FLEN/8, x4, x1, x2)

inst_17774:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xd0 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xe80007ff; valaddr_reg:x3; val_offset:53322*0 + 3*109*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53322*0 + 3*110*FLEN/8, x4, x1, x2)

inst_17775:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xd0 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xe8000fff; valaddr_reg:x3; val_offset:53325*0 + 3*110*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53325*0 + 3*111*FLEN/8, x4, x1, x2)

inst_17776:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xd0 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xe8001fff; valaddr_reg:x3; val_offset:53328*0 + 3*111*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53328*0 + 3*112*FLEN/8, x4, x1, x2)

inst_17777:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xd0 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xe8003fff; valaddr_reg:x3; val_offset:53331*0 + 3*112*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53331*0 + 3*113*FLEN/8, x4, x1, x2)

inst_17778:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xd0 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xe8007fff; valaddr_reg:x3; val_offset:53334*0 + 3*113*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53334*0 + 3*114*FLEN/8, x4, x1, x2)

inst_17779:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xd0 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xe800ffff; valaddr_reg:x3; val_offset:53337*0 + 3*114*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53337*0 + 3*115*FLEN/8, x4, x1, x2)

inst_17780:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xd0 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xe801ffff; valaddr_reg:x3; val_offset:53340*0 + 3*115*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53340*0 + 3*116*FLEN/8, x4, x1, x2)

inst_17781:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xd0 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xe803ffff; valaddr_reg:x3; val_offset:53343*0 + 3*116*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53343*0 + 3*117*FLEN/8, x4, x1, x2)

inst_17782:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xd0 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xe807ffff; valaddr_reg:x3; val_offset:53346*0 + 3*117*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53346*0 + 3*118*FLEN/8, x4, x1, x2)

inst_17783:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xd0 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xe80fffff; valaddr_reg:x3; val_offset:53349*0 + 3*118*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53349*0 + 3*119*FLEN/8, x4, x1, x2)

inst_17784:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xd0 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xe81fffff; valaddr_reg:x3; val_offset:53352*0 + 3*119*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53352*0 + 3*120*FLEN/8, x4, x1, x2)

inst_17785:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xd0 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xe83fffff; valaddr_reg:x3; val_offset:53355*0 + 3*120*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53355*0 + 3*121*FLEN/8, x4, x1, x2)

inst_17786:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xd0 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xe8400000; valaddr_reg:x3; val_offset:53358*0 + 3*121*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53358*0 + 3*122*FLEN/8, x4, x1, x2)

inst_17787:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xd0 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xe8600000; valaddr_reg:x3; val_offset:53361*0 + 3*122*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53361*0 + 3*123*FLEN/8, x4, x1, x2)

inst_17788:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xd0 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xe8700000; valaddr_reg:x3; val_offset:53364*0 + 3*123*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53364*0 + 3*124*FLEN/8, x4, x1, x2)

inst_17789:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xd0 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xe8780000; valaddr_reg:x3; val_offset:53367*0 + 3*124*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53367*0 + 3*125*FLEN/8, x4, x1, x2)

inst_17790:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xd0 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xe87c0000; valaddr_reg:x3; val_offset:53370*0 + 3*125*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53370*0 + 3*126*FLEN/8, x4, x1, x2)

inst_17791:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xd0 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xe87e0000; valaddr_reg:x3; val_offset:53373*0 + 3*126*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53373*0 + 3*127*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_2)

inst_17792:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xd0 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xe87f0000; valaddr_reg:x3; val_offset:53376*0 + 3*127*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53376*0 + 3*128*FLEN/8, x4, x1, x2)

inst_17793:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xd0 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xe87f8000; valaddr_reg:x3; val_offset:53379*0 + 3*128*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53379*0 + 3*129*FLEN/8, x4, x1, x2)

inst_17794:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xd0 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xe87fc000; valaddr_reg:x3; val_offset:53382*0 + 3*129*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53382*0 + 3*130*FLEN/8, x4, x1, x2)

inst_17795:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xd0 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xe87fe000; valaddr_reg:x3; val_offset:53385*0 + 3*130*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53385*0 + 3*131*FLEN/8, x4, x1, x2)

inst_17796:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xd0 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xe87ff000; valaddr_reg:x3; val_offset:53388*0 + 3*131*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53388*0 + 3*132*FLEN/8, x4, x1, x2)

inst_17797:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xd0 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xe87ff800; valaddr_reg:x3; val_offset:53391*0 + 3*132*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53391*0 + 3*133*FLEN/8, x4, x1, x2)

inst_17798:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xd0 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xe87ffc00; valaddr_reg:x3; val_offset:53394*0 + 3*133*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53394*0 + 3*134*FLEN/8, x4, x1, x2)

inst_17799:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xd0 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xe87ffe00; valaddr_reg:x3; val_offset:53397*0 + 3*134*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53397*0 + 3*135*FLEN/8, x4, x1, x2)

inst_17800:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xd0 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xe87fff00; valaddr_reg:x3; val_offset:53400*0 + 3*135*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53400*0 + 3*136*FLEN/8, x4, x1, x2)

inst_17801:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xd0 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xe87fff80; valaddr_reg:x3; val_offset:53403*0 + 3*136*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53403*0 + 3*137*FLEN/8, x4, x1, x2)

inst_17802:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xd0 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xe87fffc0; valaddr_reg:x3; val_offset:53406*0 + 3*137*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53406*0 + 3*138*FLEN/8, x4, x1, x2)

inst_17803:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xd0 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xe87fffe0; valaddr_reg:x3; val_offset:53409*0 + 3*138*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53409*0 + 3*139*FLEN/8, x4, x1, x2)

inst_17804:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xd0 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xe87ffff0; valaddr_reg:x3; val_offset:53412*0 + 3*139*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53412*0 + 3*140*FLEN/8, x4, x1, x2)

inst_17805:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xd0 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xe87ffff8; valaddr_reg:x3; val_offset:53415*0 + 3*140*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53415*0 + 3*141*FLEN/8, x4, x1, x2)

inst_17806:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xd0 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xe87ffffc; valaddr_reg:x3; val_offset:53418*0 + 3*141*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53418*0 + 3*142*FLEN/8, x4, x1, x2)

inst_17807:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xd0 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xe87ffffe; valaddr_reg:x3; val_offset:53421*0 + 3*142*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53421*0 + 3*143*FLEN/8, x4, x1, x2)

inst_17808:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xd0 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xe87fffff; valaddr_reg:x3; val_offset:53424*0 + 3*143*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53424*0 + 3*144*FLEN/8, x4, x1, x2)

inst_17809:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xff000001; valaddr_reg:x3; val_offset:53427*0 + 3*144*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53427*0 + 3*145*FLEN/8, x4, x1, x2)

inst_17810:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xff000003; valaddr_reg:x3; val_offset:53430*0 + 3*145*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53430*0 + 3*146*FLEN/8, x4, x1, x2)

inst_17811:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xff000007; valaddr_reg:x3; val_offset:53433*0 + 3*146*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53433*0 + 3*147*FLEN/8, x4, x1, x2)

inst_17812:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xff199999; valaddr_reg:x3; val_offset:53436*0 + 3*147*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53436*0 + 3*148*FLEN/8, x4, x1, x2)

inst_17813:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xff249249; valaddr_reg:x3; val_offset:53439*0 + 3*148*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53439*0 + 3*149*FLEN/8, x4, x1, x2)

inst_17814:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xff333333; valaddr_reg:x3; val_offset:53442*0 + 3*149*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53442*0 + 3*150*FLEN/8, x4, x1, x2)

inst_17815:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xff36db6d; valaddr_reg:x3; val_offset:53445*0 + 3*150*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53445*0 + 3*151*FLEN/8, x4, x1, x2)

inst_17816:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xff3bbbbb; valaddr_reg:x3; val_offset:53448*0 + 3*151*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53448*0 + 3*152*FLEN/8, x4, x1, x2)

inst_17817:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xff444444; valaddr_reg:x3; val_offset:53451*0 + 3*152*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53451*0 + 3*153*FLEN/8, x4, x1, x2)

inst_17818:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xff4ccccc; valaddr_reg:x3; val_offset:53454*0 + 3*153*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53454*0 + 3*154*FLEN/8, x4, x1, x2)

inst_17819:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xff5b6db6; valaddr_reg:x3; val_offset:53457*0 + 3*154*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53457*0 + 3*155*FLEN/8, x4, x1, x2)

inst_17820:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xff666666; valaddr_reg:x3; val_offset:53460*0 + 3*155*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53460*0 + 3*156*FLEN/8, x4, x1, x2)

inst_17821:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xff6db6db; valaddr_reg:x3; val_offset:53463*0 + 3*156*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53463*0 + 3*157*FLEN/8, x4, x1, x2)

inst_17822:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xff7ffff8; valaddr_reg:x3; val_offset:53466*0 + 3*157*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53466*0 + 3*158*FLEN/8, x4, x1, x2)

inst_17823:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xff7ffffc; valaddr_reg:x3; val_offset:53469*0 + 3*158*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53469*0 + 3*159*FLEN/8, x4, x1, x2)

inst_17824:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x31933e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3887c1 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb1933e; op2val:0xc03887c1;
op3val:0xff7ffffe; valaddr_reg:x3; val_offset:53472*0 + 3*159*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53472*0 + 3*160*FLEN/8, x4, x1, x2)

inst_17825:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x3f800001; valaddr_reg:x3; val_offset:53475*0 + 3*160*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53475*0 + 3*161*FLEN/8, x4, x1, x2)

inst_17826:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x3f800003; valaddr_reg:x3; val_offset:53478*0 + 3*161*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53478*0 + 3*162*FLEN/8, x4, x1, x2)

inst_17827:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x3f800007; valaddr_reg:x3; val_offset:53481*0 + 3*162*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53481*0 + 3*163*FLEN/8, x4, x1, x2)

inst_17828:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x3f999999; valaddr_reg:x3; val_offset:53484*0 + 3*163*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53484*0 + 3*164*FLEN/8, x4, x1, x2)

inst_17829:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x3fa49249; valaddr_reg:x3; val_offset:53487*0 + 3*164*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53487*0 + 3*165*FLEN/8, x4, x1, x2)

inst_17830:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x3fb33333; valaddr_reg:x3; val_offset:53490*0 + 3*165*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53490*0 + 3*166*FLEN/8, x4, x1, x2)

inst_17831:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x3fb6db6d; valaddr_reg:x3; val_offset:53493*0 + 3*166*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53493*0 + 3*167*FLEN/8, x4, x1, x2)

inst_17832:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x3fbbbbbb; valaddr_reg:x3; val_offset:53496*0 + 3*167*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53496*0 + 3*168*FLEN/8, x4, x1, x2)

inst_17833:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x3fc44444; valaddr_reg:x3; val_offset:53499*0 + 3*168*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53499*0 + 3*169*FLEN/8, x4, x1, x2)

inst_17834:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x3fcccccc; valaddr_reg:x3; val_offset:53502*0 + 3*169*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53502*0 + 3*170*FLEN/8, x4, x1, x2)

inst_17835:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x3fdb6db6; valaddr_reg:x3; val_offset:53505*0 + 3*170*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53505*0 + 3*171*FLEN/8, x4, x1, x2)

inst_17836:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x3fe66666; valaddr_reg:x3; val_offset:53508*0 + 3*171*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53508*0 + 3*172*FLEN/8, x4, x1, x2)

inst_17837:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x3fedb6db; valaddr_reg:x3; val_offset:53511*0 + 3*172*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53511*0 + 3*173*FLEN/8, x4, x1, x2)

inst_17838:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x3ffffff8; valaddr_reg:x3; val_offset:53514*0 + 3*173*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53514*0 + 3*174*FLEN/8, x4, x1, x2)

inst_17839:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x3ffffffc; valaddr_reg:x3; val_offset:53517*0 + 3*174*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53517*0 + 3*175*FLEN/8, x4, x1, x2)

inst_17840:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x3ffffffe; valaddr_reg:x3; val_offset:53520*0 + 3*175*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53520*0 + 3*176*FLEN/8, x4, x1, x2)

inst_17841:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x80 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x40000000; valaddr_reg:x3; val_offset:53523*0 + 3*176*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53523*0 + 3*177*FLEN/8, x4, x1, x2)

inst_17842:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x80 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x40000001; valaddr_reg:x3; val_offset:53526*0 + 3*177*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53526*0 + 3*178*FLEN/8, x4, x1, x2)

inst_17843:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x80 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x40000003; valaddr_reg:x3; val_offset:53529*0 + 3*178*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53529*0 + 3*179*FLEN/8, x4, x1, x2)

inst_17844:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x80 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x40000007; valaddr_reg:x3; val_offset:53532*0 + 3*179*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53532*0 + 3*180*FLEN/8, x4, x1, x2)

inst_17845:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x80 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x4000000f; valaddr_reg:x3; val_offset:53535*0 + 3*180*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53535*0 + 3*181*FLEN/8, x4, x1, x2)

inst_17846:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x80 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x4000001f; valaddr_reg:x3; val_offset:53538*0 + 3*181*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53538*0 + 3*182*FLEN/8, x4, x1, x2)

inst_17847:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x80 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x4000003f; valaddr_reg:x3; val_offset:53541*0 + 3*182*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53541*0 + 3*183*FLEN/8, x4, x1, x2)

inst_17848:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x80 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x4000007f; valaddr_reg:x3; val_offset:53544*0 + 3*183*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53544*0 + 3*184*FLEN/8, x4, x1, x2)

inst_17849:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x80 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x400000ff; valaddr_reg:x3; val_offset:53547*0 + 3*184*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53547*0 + 3*185*FLEN/8, x4, x1, x2)

inst_17850:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x80 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x400001ff; valaddr_reg:x3; val_offset:53550*0 + 3*185*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53550*0 + 3*186*FLEN/8, x4, x1, x2)

inst_17851:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x80 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x400003ff; valaddr_reg:x3; val_offset:53553*0 + 3*186*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53553*0 + 3*187*FLEN/8, x4, x1, x2)

inst_17852:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x80 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x400007ff; valaddr_reg:x3; val_offset:53556*0 + 3*187*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53556*0 + 3*188*FLEN/8, x4, x1, x2)

inst_17853:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x80 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x40000fff; valaddr_reg:x3; val_offset:53559*0 + 3*188*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53559*0 + 3*189*FLEN/8, x4, x1, x2)

inst_17854:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x80 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x40001fff; valaddr_reg:x3; val_offset:53562*0 + 3*189*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53562*0 + 3*190*FLEN/8, x4, x1, x2)

inst_17855:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x80 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x40003fff; valaddr_reg:x3; val_offset:53565*0 + 3*190*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53565*0 + 3*191*FLEN/8, x4, x1, x2)

inst_17856:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x80 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x40007fff; valaddr_reg:x3; val_offset:53568*0 + 3*191*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53568*0 + 3*192*FLEN/8, x4, x1, x2)

inst_17857:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x80 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x4000ffff; valaddr_reg:x3; val_offset:53571*0 + 3*192*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53571*0 + 3*193*FLEN/8, x4, x1, x2)

inst_17858:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x80 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x4001ffff; valaddr_reg:x3; val_offset:53574*0 + 3*193*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53574*0 + 3*194*FLEN/8, x4, x1, x2)

inst_17859:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x80 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x4003ffff; valaddr_reg:x3; val_offset:53577*0 + 3*194*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53577*0 + 3*195*FLEN/8, x4, x1, x2)

inst_17860:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x80 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x4007ffff; valaddr_reg:x3; val_offset:53580*0 + 3*195*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53580*0 + 3*196*FLEN/8, x4, x1, x2)

inst_17861:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x80 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x400fffff; valaddr_reg:x3; val_offset:53583*0 + 3*196*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53583*0 + 3*197*FLEN/8, x4, x1, x2)

inst_17862:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x80 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x401fffff; valaddr_reg:x3; val_offset:53586*0 + 3*197*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53586*0 + 3*198*FLEN/8, x4, x1, x2)

inst_17863:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x80 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x403fffff; valaddr_reg:x3; val_offset:53589*0 + 3*198*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53589*0 + 3*199*FLEN/8, x4, x1, x2)

inst_17864:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x80 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x40400000; valaddr_reg:x3; val_offset:53592*0 + 3*199*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53592*0 + 3*200*FLEN/8, x4, x1, x2)

inst_17865:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x80 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x40600000; valaddr_reg:x3; val_offset:53595*0 + 3*200*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53595*0 + 3*201*FLEN/8, x4, x1, x2)

inst_17866:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x80 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x40700000; valaddr_reg:x3; val_offset:53598*0 + 3*201*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53598*0 + 3*202*FLEN/8, x4, x1, x2)

inst_17867:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x80 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x40780000; valaddr_reg:x3; val_offset:53601*0 + 3*202*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53601*0 + 3*203*FLEN/8, x4, x1, x2)

inst_17868:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x80 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x407c0000; valaddr_reg:x3; val_offset:53604*0 + 3*203*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53604*0 + 3*204*FLEN/8, x4, x1, x2)

inst_17869:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x80 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x407e0000; valaddr_reg:x3; val_offset:53607*0 + 3*204*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53607*0 + 3*205*FLEN/8, x4, x1, x2)

inst_17870:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x80 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x407f0000; valaddr_reg:x3; val_offset:53610*0 + 3*205*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53610*0 + 3*206*FLEN/8, x4, x1, x2)

inst_17871:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x80 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x407f8000; valaddr_reg:x3; val_offset:53613*0 + 3*206*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53613*0 + 3*207*FLEN/8, x4, x1, x2)

inst_17872:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x80 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x407fc000; valaddr_reg:x3; val_offset:53616*0 + 3*207*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53616*0 + 3*208*FLEN/8, x4, x1, x2)

inst_17873:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x80 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x407fe000; valaddr_reg:x3; val_offset:53619*0 + 3*208*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53619*0 + 3*209*FLEN/8, x4, x1, x2)

inst_17874:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x80 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x407ff000; valaddr_reg:x3; val_offset:53622*0 + 3*209*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53622*0 + 3*210*FLEN/8, x4, x1, x2)

inst_17875:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x80 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x407ff800; valaddr_reg:x3; val_offset:53625*0 + 3*210*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53625*0 + 3*211*FLEN/8, x4, x1, x2)

inst_17876:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x80 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x407ffc00; valaddr_reg:x3; val_offset:53628*0 + 3*211*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53628*0 + 3*212*FLEN/8, x4, x1, x2)

inst_17877:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x80 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x407ffe00; valaddr_reg:x3; val_offset:53631*0 + 3*212*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53631*0 + 3*213*FLEN/8, x4, x1, x2)

inst_17878:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x80 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x407fff00; valaddr_reg:x3; val_offset:53634*0 + 3*213*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53634*0 + 3*214*FLEN/8, x4, x1, x2)

inst_17879:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x80 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x407fff80; valaddr_reg:x3; val_offset:53637*0 + 3*214*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53637*0 + 3*215*FLEN/8, x4, x1, x2)

inst_17880:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x80 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x407fffc0; valaddr_reg:x3; val_offset:53640*0 + 3*215*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53640*0 + 3*216*FLEN/8, x4, x1, x2)

inst_17881:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x80 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x407fffe0; valaddr_reg:x3; val_offset:53643*0 + 3*216*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53643*0 + 3*217*FLEN/8, x4, x1, x2)

inst_17882:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x80 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x407ffff0; valaddr_reg:x3; val_offset:53646*0 + 3*217*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53646*0 + 3*218*FLEN/8, x4, x1, x2)

inst_17883:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x80 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x407ffff8; valaddr_reg:x3; val_offset:53649*0 + 3*218*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53649*0 + 3*219*FLEN/8, x4, x1, x2)

inst_17884:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x80 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x407ffffc; valaddr_reg:x3; val_offset:53652*0 + 3*219*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53652*0 + 3*220*FLEN/8, x4, x1, x2)

inst_17885:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x80 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x407ffffe; valaddr_reg:x3; val_offset:53655*0 + 3*220*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53655*0 + 3*221*FLEN/8, x4, x1, x2)

inst_17886:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3360dd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5b5670 and fs3 == 0 and fe3 == 0x80 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb360dd; op2val:0x5b5670;
op3val:0x407fffff; valaddr_reg:x3; val_offset:53658*0 + 3*221*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53658*0 + 3*222*FLEN/8, x4, x1, x2)

inst_17887:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0x800001; valaddr_reg:x3; val_offset:53661*0 + 3*222*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53661*0 + 3*223*FLEN/8, x4, x1, x2)

inst_17888:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0x800003; valaddr_reg:x3; val_offset:53664*0 + 3*223*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53664*0 + 3*224*FLEN/8, x4, x1, x2)

inst_17889:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0x800007; valaddr_reg:x3; val_offset:53667*0 + 3*224*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53667*0 + 3*225*FLEN/8, x4, x1, x2)

inst_17890:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0x999999; valaddr_reg:x3; val_offset:53670*0 + 3*225*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53670*0 + 3*226*FLEN/8, x4, x1, x2)

inst_17891:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xa49249; valaddr_reg:x3; val_offset:53673*0 + 3*226*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53673*0 + 3*227*FLEN/8, x4, x1, x2)

inst_17892:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xb33333; valaddr_reg:x3; val_offset:53676*0 + 3*227*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53676*0 + 3*228*FLEN/8, x4, x1, x2)

inst_17893:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xb6db6d; valaddr_reg:x3; val_offset:53679*0 + 3*228*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53679*0 + 3*229*FLEN/8, x4, x1, x2)

inst_17894:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xbbbbbb; valaddr_reg:x3; val_offset:53682*0 + 3*229*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53682*0 + 3*230*FLEN/8, x4, x1, x2)

inst_17895:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xc44444; valaddr_reg:x3; val_offset:53685*0 + 3*230*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53685*0 + 3*231*FLEN/8, x4, x1, x2)

inst_17896:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xcccccc; valaddr_reg:x3; val_offset:53688*0 + 3*231*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53688*0 + 3*232*FLEN/8, x4, x1, x2)

inst_17897:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xdb6db6; valaddr_reg:x3; val_offset:53691*0 + 3*232*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53691*0 + 3*233*FLEN/8, x4, x1, x2)

inst_17898:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xe66666; valaddr_reg:x3; val_offset:53694*0 + 3*233*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53694*0 + 3*234*FLEN/8, x4, x1, x2)

inst_17899:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xedb6db; valaddr_reg:x3; val_offset:53697*0 + 3*234*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53697*0 + 3*235*FLEN/8, x4, x1, x2)

inst_17900:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xfffff8; valaddr_reg:x3; val_offset:53700*0 + 3*235*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53700*0 + 3*236*FLEN/8, x4, x1, x2)

inst_17901:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xfffffc; valaddr_reg:x3; val_offset:53703*0 + 3*236*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53703*0 + 3*237*FLEN/8, x4, x1, x2)

inst_17902:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xfffffe; valaddr_reg:x3; val_offset:53706*0 + 3*237*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53706*0 + 3*238*FLEN/8, x4, x1, x2)

inst_17903:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xc800000; valaddr_reg:x3; val_offset:53709*0 + 3*238*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53709*0 + 3*239*FLEN/8, x4, x1, x2)

inst_17904:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xc800001; valaddr_reg:x3; val_offset:53712*0 + 3*239*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53712*0 + 3*240*FLEN/8, x4, x1, x2)

inst_17905:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xc800003; valaddr_reg:x3; val_offset:53715*0 + 3*240*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53715*0 + 3*241*FLEN/8, x4, x1, x2)

inst_17906:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xc800007; valaddr_reg:x3; val_offset:53718*0 + 3*241*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53718*0 + 3*242*FLEN/8, x4, x1, x2)

inst_17907:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xc80000f; valaddr_reg:x3; val_offset:53721*0 + 3*242*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53721*0 + 3*243*FLEN/8, x4, x1, x2)

inst_17908:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xc80001f; valaddr_reg:x3; val_offset:53724*0 + 3*243*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53724*0 + 3*244*FLEN/8, x4, x1, x2)

inst_17909:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xc80003f; valaddr_reg:x3; val_offset:53727*0 + 3*244*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53727*0 + 3*245*FLEN/8, x4, x1, x2)

inst_17910:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xc80007f; valaddr_reg:x3; val_offset:53730*0 + 3*245*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53730*0 + 3*246*FLEN/8, x4, x1, x2)

inst_17911:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xc8000ff; valaddr_reg:x3; val_offset:53733*0 + 3*246*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53733*0 + 3*247*FLEN/8, x4, x1, x2)

inst_17912:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xc8001ff; valaddr_reg:x3; val_offset:53736*0 + 3*247*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53736*0 + 3*248*FLEN/8, x4, x1, x2)

inst_17913:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xc8003ff; valaddr_reg:x3; val_offset:53739*0 + 3*248*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53739*0 + 3*249*FLEN/8, x4, x1, x2)

inst_17914:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xc8007ff; valaddr_reg:x3; val_offset:53742*0 + 3*249*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53742*0 + 3*250*FLEN/8, x4, x1, x2)

inst_17915:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xc800fff; valaddr_reg:x3; val_offset:53745*0 + 3*250*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53745*0 + 3*251*FLEN/8, x4, x1, x2)

inst_17916:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xc801fff; valaddr_reg:x3; val_offset:53748*0 + 3*251*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53748*0 + 3*252*FLEN/8, x4, x1, x2)

inst_17917:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xc803fff; valaddr_reg:x3; val_offset:53751*0 + 3*252*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53751*0 + 3*253*FLEN/8, x4, x1, x2)

inst_17918:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xc807fff; valaddr_reg:x3; val_offset:53754*0 + 3*253*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53754*0 + 3*254*FLEN/8, x4, x1, x2)

inst_17919:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xc80ffff; valaddr_reg:x3; val_offset:53757*0 + 3*254*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53757*0 + 3*255*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_3)

inst_17920:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xc81ffff; valaddr_reg:x3; val_offset:53760*0 + 3*256*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53760*0 + 3*256*FLEN/8, x4, x1, x2)

inst_17921:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xc83ffff; valaddr_reg:x3; val_offset:53763*0 + 3*257*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53763*0 + 3*257*FLEN/8, x4, x1, x2)

inst_17922:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xc87ffff; valaddr_reg:x3; val_offset:53766*0 + 3*258*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53766*0 + 3*258*FLEN/8, x4, x1, x2)

inst_17923:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xc8fffff; valaddr_reg:x3; val_offset:53769*0 + 3*259*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53769*0 + 3*259*FLEN/8, x4, x1, x2)

inst_17924:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xc9fffff; valaddr_reg:x3; val_offset:53772*0 + 3*260*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53772*0 + 3*260*FLEN/8, x4, x1, x2)

inst_17925:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xcbfffff; valaddr_reg:x3; val_offset:53775*0 + 3*261*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53775*0 + 3*261*FLEN/8, x4, x1, x2)

inst_17926:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xcc00000; valaddr_reg:x3; val_offset:53778*0 + 3*262*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53778*0 + 3*262*FLEN/8, x4, x1, x2)

inst_17927:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xce00000; valaddr_reg:x3; val_offset:53781*0 + 3*263*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53781*0 + 3*263*FLEN/8, x4, x1, x2)

inst_17928:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xcf00000; valaddr_reg:x3; val_offset:53784*0 + 3*264*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53784*0 + 3*264*FLEN/8, x4, x1, x2)

inst_17929:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xcf80000; valaddr_reg:x3; val_offset:53787*0 + 3*265*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53787*0 + 3*265*FLEN/8, x4, x1, x2)

inst_17930:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xcfc0000; valaddr_reg:x3; val_offset:53790*0 + 3*266*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53790*0 + 3*266*FLEN/8, x4, x1, x2)

inst_17931:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xcfe0000; valaddr_reg:x3; val_offset:53793*0 + 3*267*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53793*0 + 3*267*FLEN/8, x4, x1, x2)

inst_17932:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xcff0000; valaddr_reg:x3; val_offset:53796*0 + 3*268*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53796*0 + 3*268*FLEN/8, x4, x1, x2)

inst_17933:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xcff8000; valaddr_reg:x3; val_offset:53799*0 + 3*269*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53799*0 + 3*269*FLEN/8, x4, x1, x2)

inst_17934:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xcffc000; valaddr_reg:x3; val_offset:53802*0 + 3*270*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53802*0 + 3*270*FLEN/8, x4, x1, x2)

inst_17935:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xcffe000; valaddr_reg:x3; val_offset:53805*0 + 3*271*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53805*0 + 3*271*FLEN/8, x4, x1, x2)

inst_17936:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xcfff000; valaddr_reg:x3; val_offset:53808*0 + 3*272*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53808*0 + 3*272*FLEN/8, x4, x1, x2)

inst_17937:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xcfff800; valaddr_reg:x3; val_offset:53811*0 + 3*273*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53811*0 + 3*273*FLEN/8, x4, x1, x2)

inst_17938:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xcfffc00; valaddr_reg:x3; val_offset:53814*0 + 3*274*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53814*0 + 3*274*FLEN/8, x4, x1, x2)

inst_17939:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xcfffe00; valaddr_reg:x3; val_offset:53817*0 + 3*275*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53817*0 + 3*275*FLEN/8, x4, x1, x2)

inst_17940:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xcffff00; valaddr_reg:x3; val_offset:53820*0 + 3*276*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53820*0 + 3*276*FLEN/8, x4, x1, x2)

inst_17941:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xcffff80; valaddr_reg:x3; val_offset:53823*0 + 3*277*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53823*0 + 3*277*FLEN/8, x4, x1, x2)

inst_17942:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xcffffc0; valaddr_reg:x3; val_offset:53826*0 + 3*278*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53826*0 + 3*278*FLEN/8, x4, x1, x2)

inst_17943:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xcffffe0; valaddr_reg:x3; val_offset:53829*0 + 3*279*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53829*0 + 3*279*FLEN/8, x4, x1, x2)

inst_17944:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xcfffff0; valaddr_reg:x3; val_offset:53832*0 + 3*280*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53832*0 + 3*280*FLEN/8, x4, x1, x2)

inst_17945:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xcfffff8; valaddr_reg:x3; val_offset:53835*0 + 3*281*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53835*0 + 3*281*FLEN/8, x4, x1, x2)

inst_17946:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xcfffffc; valaddr_reg:x3; val_offset:53838*0 + 3*282*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53838*0 + 3*282*FLEN/8, x4, x1, x2)

inst_17947:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xcfffffe; valaddr_reg:x3; val_offset:53841*0 + 3*283*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53841*0 + 3*283*FLEN/8, x4, x1, x2)

inst_17948:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x33667c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb3667c; op2val:0x0;
op3val:0xcffffff; valaddr_reg:x3; val_offset:53844*0 + 3*284*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53844*0 + 3*284*FLEN/8, x4, x1, x2)

inst_17949:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x3f800001; valaddr_reg:x3; val_offset:53847*0 + 3*285*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53847*0 + 3*285*FLEN/8, x4, x1, x2)

inst_17950:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x3f800003; valaddr_reg:x3; val_offset:53850*0 + 3*286*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53850*0 + 3*286*FLEN/8, x4, x1, x2)

inst_17951:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x3f800007; valaddr_reg:x3; val_offset:53853*0 + 3*287*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53853*0 + 3*287*FLEN/8, x4, x1, x2)

inst_17952:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x3f999999; valaddr_reg:x3; val_offset:53856*0 + 3*288*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53856*0 + 3*288*FLEN/8, x4, x1, x2)

inst_17953:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x3fa49249; valaddr_reg:x3; val_offset:53859*0 + 3*289*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53859*0 + 3*289*FLEN/8, x4, x1, x2)

inst_17954:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x3fb33333; valaddr_reg:x3; val_offset:53862*0 + 3*290*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53862*0 + 3*290*FLEN/8, x4, x1, x2)

inst_17955:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x3fb6db6d; valaddr_reg:x3; val_offset:53865*0 + 3*291*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53865*0 + 3*291*FLEN/8, x4, x1, x2)

inst_17956:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x3fbbbbbb; valaddr_reg:x3; val_offset:53868*0 + 3*292*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53868*0 + 3*292*FLEN/8, x4, x1, x2)

inst_17957:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x3fc44444; valaddr_reg:x3; val_offset:53871*0 + 3*293*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53871*0 + 3*293*FLEN/8, x4, x1, x2)

inst_17958:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x3fcccccc; valaddr_reg:x3; val_offset:53874*0 + 3*294*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53874*0 + 3*294*FLEN/8, x4, x1, x2)

inst_17959:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x3fdb6db6; valaddr_reg:x3; val_offset:53877*0 + 3*295*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53877*0 + 3*295*FLEN/8, x4, x1, x2)

inst_17960:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x3fe66666; valaddr_reg:x3; val_offset:53880*0 + 3*296*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53880*0 + 3*296*FLEN/8, x4, x1, x2)

inst_17961:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x3fedb6db; valaddr_reg:x3; val_offset:53883*0 + 3*297*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53883*0 + 3*297*FLEN/8, x4, x1, x2)

inst_17962:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x3ffffff8; valaddr_reg:x3; val_offset:53886*0 + 3*298*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53886*0 + 3*298*FLEN/8, x4, x1, x2)

inst_17963:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x3ffffffc; valaddr_reg:x3; val_offset:53889*0 + 3*299*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53889*0 + 3*299*FLEN/8, x4, x1, x2)

inst_17964:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x3ffffffe; valaddr_reg:x3; val_offset:53892*0 + 3*300*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53892*0 + 3*300*FLEN/8, x4, x1, x2)

inst_17965:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x86 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x43000000; valaddr_reg:x3; val_offset:53895*0 + 3*301*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53895*0 + 3*301*FLEN/8, x4, x1, x2)

inst_17966:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x86 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x43000001; valaddr_reg:x3; val_offset:53898*0 + 3*302*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53898*0 + 3*302*FLEN/8, x4, x1, x2)

inst_17967:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x86 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x43000003; valaddr_reg:x3; val_offset:53901*0 + 3*303*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53901*0 + 3*303*FLEN/8, x4, x1, x2)

inst_17968:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x86 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x43000007; valaddr_reg:x3; val_offset:53904*0 + 3*304*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53904*0 + 3*304*FLEN/8, x4, x1, x2)

inst_17969:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x86 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x4300000f; valaddr_reg:x3; val_offset:53907*0 + 3*305*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53907*0 + 3*305*FLEN/8, x4, x1, x2)

inst_17970:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x86 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x4300001f; valaddr_reg:x3; val_offset:53910*0 + 3*306*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53910*0 + 3*306*FLEN/8, x4, x1, x2)

inst_17971:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x86 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x4300003f; valaddr_reg:x3; val_offset:53913*0 + 3*307*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53913*0 + 3*307*FLEN/8, x4, x1, x2)

inst_17972:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x86 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x4300007f; valaddr_reg:x3; val_offset:53916*0 + 3*308*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53916*0 + 3*308*FLEN/8, x4, x1, x2)

inst_17973:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x86 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x430000ff; valaddr_reg:x3; val_offset:53919*0 + 3*309*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53919*0 + 3*309*FLEN/8, x4, x1, x2)

inst_17974:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x86 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x430001ff; valaddr_reg:x3; val_offset:53922*0 + 3*310*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53922*0 + 3*310*FLEN/8, x4, x1, x2)

inst_17975:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x86 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x430003ff; valaddr_reg:x3; val_offset:53925*0 + 3*311*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53925*0 + 3*311*FLEN/8, x4, x1, x2)

inst_17976:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x86 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x430007ff; valaddr_reg:x3; val_offset:53928*0 + 3*312*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53928*0 + 3*312*FLEN/8, x4, x1, x2)

inst_17977:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x86 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x43000fff; valaddr_reg:x3; val_offset:53931*0 + 3*313*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53931*0 + 3*313*FLEN/8, x4, x1, x2)

inst_17978:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x86 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x43001fff; valaddr_reg:x3; val_offset:53934*0 + 3*314*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53934*0 + 3*314*FLEN/8, x4, x1, x2)

inst_17979:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x86 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x43003fff; valaddr_reg:x3; val_offset:53937*0 + 3*315*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53937*0 + 3*315*FLEN/8, x4, x1, x2)

inst_17980:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x86 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x43007fff; valaddr_reg:x3; val_offset:53940*0 + 3*316*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53940*0 + 3*316*FLEN/8, x4, x1, x2)

inst_17981:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x86 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x4300ffff; valaddr_reg:x3; val_offset:53943*0 + 3*317*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53943*0 + 3*317*FLEN/8, x4, x1, x2)

inst_17982:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x86 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x4301ffff; valaddr_reg:x3; val_offset:53946*0 + 3*318*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53946*0 + 3*318*FLEN/8, x4, x1, x2)

inst_17983:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x86 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x4303ffff; valaddr_reg:x3; val_offset:53949*0 + 3*319*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53949*0 + 3*319*FLEN/8, x4, x1, x2)

inst_17984:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x86 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x4307ffff; valaddr_reg:x3; val_offset:53952*0 + 3*320*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53952*0 + 3*320*FLEN/8, x4, x1, x2)

inst_17985:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x86 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x430fffff; valaddr_reg:x3; val_offset:53955*0 + 3*321*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53955*0 + 3*321*FLEN/8, x4, x1, x2)

inst_17986:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x86 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x431fffff; valaddr_reg:x3; val_offset:53958*0 + 3*322*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53958*0 + 3*322*FLEN/8, x4, x1, x2)

inst_17987:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x86 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x433fffff; valaddr_reg:x3; val_offset:53961*0 + 3*323*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53961*0 + 3*323*FLEN/8, x4, x1, x2)

inst_17988:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x86 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x43400000; valaddr_reg:x3; val_offset:53964*0 + 3*324*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53964*0 + 3*324*FLEN/8, x4, x1, x2)

inst_17989:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x86 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x43600000; valaddr_reg:x3; val_offset:53967*0 + 3*325*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53967*0 + 3*325*FLEN/8, x4, x1, x2)

inst_17990:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x86 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x43700000; valaddr_reg:x3; val_offset:53970*0 + 3*326*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53970*0 + 3*326*FLEN/8, x4, x1, x2)

inst_17991:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x86 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x43780000; valaddr_reg:x3; val_offset:53973*0 + 3*327*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53973*0 + 3*327*FLEN/8, x4, x1, x2)

inst_17992:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x86 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x437c0000; valaddr_reg:x3; val_offset:53976*0 + 3*328*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53976*0 + 3*328*FLEN/8, x4, x1, x2)

inst_17993:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x86 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x437e0000; valaddr_reg:x3; val_offset:53979*0 + 3*329*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53979*0 + 3*329*FLEN/8, x4, x1, x2)

inst_17994:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x86 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x437f0000; valaddr_reg:x3; val_offset:53982*0 + 3*330*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53982*0 + 3*330*FLEN/8, x4, x1, x2)

inst_17995:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x86 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x437f8000; valaddr_reg:x3; val_offset:53985*0 + 3*331*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53985*0 + 3*331*FLEN/8, x4, x1, x2)

inst_17996:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x86 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x437fc000; valaddr_reg:x3; val_offset:53988*0 + 3*332*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53988*0 + 3*332*FLEN/8, x4, x1, x2)

inst_17997:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x86 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x437fe000; valaddr_reg:x3; val_offset:53991*0 + 3*333*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53991*0 + 3*333*FLEN/8, x4, x1, x2)

inst_17998:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x86 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x437ff000; valaddr_reg:x3; val_offset:53994*0 + 3*334*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53994*0 + 3*334*FLEN/8, x4, x1, x2)

inst_17999:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x86 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x437ff800; valaddr_reg:x3; val_offset:53997*0 + 3*335*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 53997*0 + 3*335*FLEN/8, x4, x1, x2)

inst_18000:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x86 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x437ffc00; valaddr_reg:x3; val_offset:54000*0 + 3*336*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54000*0 + 3*336*FLEN/8, x4, x1, x2)

inst_18001:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x86 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x437ffe00; valaddr_reg:x3; val_offset:54003*0 + 3*337*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54003*0 + 3*337*FLEN/8, x4, x1, x2)

inst_18002:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x86 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x437fff00; valaddr_reg:x3; val_offset:54006*0 + 3*338*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54006*0 + 3*338*FLEN/8, x4, x1, x2)

inst_18003:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x86 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x437fff80; valaddr_reg:x3; val_offset:54009*0 + 3*339*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54009*0 + 3*339*FLEN/8, x4, x1, x2)

inst_18004:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x86 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x437fffc0; valaddr_reg:x3; val_offset:54012*0 + 3*340*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54012*0 + 3*340*FLEN/8, x4, x1, x2)

inst_18005:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x86 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x437fffe0; valaddr_reg:x3; val_offset:54015*0 + 3*341*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54015*0 + 3*341*FLEN/8, x4, x1, x2)

inst_18006:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x86 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x437ffff0; valaddr_reg:x3; val_offset:54018*0 + 3*342*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54018*0 + 3*342*FLEN/8, x4, x1, x2)

inst_18007:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x86 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x437ffff8; valaddr_reg:x3; val_offset:54021*0 + 3*343*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54021*0 + 3*343*FLEN/8, x4, x1, x2)

inst_18008:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x86 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x437ffffc; valaddr_reg:x3; val_offset:54024*0 + 3*344*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54024*0 + 3*344*FLEN/8, x4, x1, x2)

inst_18009:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x86 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x437ffffe; valaddr_reg:x3; val_offset:54027*0 + 3*345*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54027*0 + 3*345*FLEN/8, x4, x1, x2)

inst_18010:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x349020 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5abd08 and fs3 == 0 and fe3 == 0x86 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb49020; op2val:0x5abd08;
op3val:0x437fffff; valaddr_reg:x3; val_offset:54030*0 + 3*346*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54030*0 + 3*346*FLEN/8, x4, x1, x2)

inst_18011:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xc1 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xe0800000; valaddr_reg:x3; val_offset:54033*0 + 3*347*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54033*0 + 3*347*FLEN/8, x4, x1, x2)

inst_18012:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xc1 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xe0800001; valaddr_reg:x3; val_offset:54036*0 + 3*348*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54036*0 + 3*348*FLEN/8, x4, x1, x2)

inst_18013:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xc1 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xe0800003; valaddr_reg:x3; val_offset:54039*0 + 3*349*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54039*0 + 3*349*FLEN/8, x4, x1, x2)

inst_18014:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xc1 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xe0800007; valaddr_reg:x3; val_offset:54042*0 + 3*350*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54042*0 + 3*350*FLEN/8, x4, x1, x2)

inst_18015:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xc1 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xe080000f; valaddr_reg:x3; val_offset:54045*0 + 3*351*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54045*0 + 3*351*FLEN/8, x4, x1, x2)

inst_18016:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xc1 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xe080001f; valaddr_reg:x3; val_offset:54048*0 + 3*352*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54048*0 + 3*352*FLEN/8, x4, x1, x2)

inst_18017:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xc1 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xe080003f; valaddr_reg:x3; val_offset:54051*0 + 3*353*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54051*0 + 3*353*FLEN/8, x4, x1, x2)

inst_18018:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xc1 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xe080007f; valaddr_reg:x3; val_offset:54054*0 + 3*354*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54054*0 + 3*354*FLEN/8, x4, x1, x2)

inst_18019:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xc1 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xe08000ff; valaddr_reg:x3; val_offset:54057*0 + 3*355*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54057*0 + 3*355*FLEN/8, x4, x1, x2)

inst_18020:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xc1 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xe08001ff; valaddr_reg:x3; val_offset:54060*0 + 3*356*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54060*0 + 3*356*FLEN/8, x4, x1, x2)

inst_18021:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xc1 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xe08003ff; valaddr_reg:x3; val_offset:54063*0 + 3*357*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54063*0 + 3*357*FLEN/8, x4, x1, x2)

inst_18022:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xc1 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xe08007ff; valaddr_reg:x3; val_offset:54066*0 + 3*358*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54066*0 + 3*358*FLEN/8, x4, x1, x2)

inst_18023:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xc1 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xe0800fff; valaddr_reg:x3; val_offset:54069*0 + 3*359*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54069*0 + 3*359*FLEN/8, x4, x1, x2)

inst_18024:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xc1 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xe0801fff; valaddr_reg:x3; val_offset:54072*0 + 3*360*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54072*0 + 3*360*FLEN/8, x4, x1, x2)

inst_18025:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xc1 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xe0803fff; valaddr_reg:x3; val_offset:54075*0 + 3*361*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54075*0 + 3*361*FLEN/8, x4, x1, x2)

inst_18026:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xc1 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xe0807fff; valaddr_reg:x3; val_offset:54078*0 + 3*362*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54078*0 + 3*362*FLEN/8, x4, x1, x2)

inst_18027:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xc1 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xe080ffff; valaddr_reg:x3; val_offset:54081*0 + 3*363*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54081*0 + 3*363*FLEN/8, x4, x1, x2)

inst_18028:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xc1 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xe081ffff; valaddr_reg:x3; val_offset:54084*0 + 3*364*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54084*0 + 3*364*FLEN/8, x4, x1, x2)

inst_18029:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xc1 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xe083ffff; valaddr_reg:x3; val_offset:54087*0 + 3*365*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54087*0 + 3*365*FLEN/8, x4, x1, x2)

inst_18030:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xc1 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xe087ffff; valaddr_reg:x3; val_offset:54090*0 + 3*366*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54090*0 + 3*366*FLEN/8, x4, x1, x2)

inst_18031:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xc1 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xe08fffff; valaddr_reg:x3; val_offset:54093*0 + 3*367*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54093*0 + 3*367*FLEN/8, x4, x1, x2)

inst_18032:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xc1 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xe09fffff; valaddr_reg:x3; val_offset:54096*0 + 3*368*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54096*0 + 3*368*FLEN/8, x4, x1, x2)

inst_18033:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xc1 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xe0bfffff; valaddr_reg:x3; val_offset:54099*0 + 3*369*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54099*0 + 3*369*FLEN/8, x4, x1, x2)

inst_18034:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xc1 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xe0c00000; valaddr_reg:x3; val_offset:54102*0 + 3*370*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54102*0 + 3*370*FLEN/8, x4, x1, x2)

inst_18035:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xc1 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xe0e00000; valaddr_reg:x3; val_offset:54105*0 + 3*371*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54105*0 + 3*371*FLEN/8, x4, x1, x2)

inst_18036:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xc1 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xe0f00000; valaddr_reg:x3; val_offset:54108*0 + 3*372*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54108*0 + 3*372*FLEN/8, x4, x1, x2)

inst_18037:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xc1 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xe0f80000; valaddr_reg:x3; val_offset:54111*0 + 3*373*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54111*0 + 3*373*FLEN/8, x4, x1, x2)

inst_18038:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xc1 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xe0fc0000; valaddr_reg:x3; val_offset:54114*0 + 3*374*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54114*0 + 3*374*FLEN/8, x4, x1, x2)

inst_18039:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xc1 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xe0fe0000; valaddr_reg:x3; val_offset:54117*0 + 3*375*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54117*0 + 3*375*FLEN/8, x4, x1, x2)

inst_18040:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xc1 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xe0ff0000; valaddr_reg:x3; val_offset:54120*0 + 3*376*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54120*0 + 3*376*FLEN/8, x4, x1, x2)

inst_18041:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xc1 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xe0ff8000; valaddr_reg:x3; val_offset:54123*0 + 3*377*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54123*0 + 3*377*FLEN/8, x4, x1, x2)

inst_18042:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xc1 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xe0ffc000; valaddr_reg:x3; val_offset:54126*0 + 3*378*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54126*0 + 3*378*FLEN/8, x4, x1, x2)

inst_18043:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xc1 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xe0ffe000; valaddr_reg:x3; val_offset:54129*0 + 3*379*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54129*0 + 3*379*FLEN/8, x4, x1, x2)

inst_18044:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xc1 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xe0fff000; valaddr_reg:x3; val_offset:54132*0 + 3*380*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54132*0 + 3*380*FLEN/8, x4, x1, x2)

inst_18045:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xc1 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xe0fff800; valaddr_reg:x3; val_offset:54135*0 + 3*381*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54135*0 + 3*381*FLEN/8, x4, x1, x2)

inst_18046:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xc1 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xe0fffc00; valaddr_reg:x3; val_offset:54138*0 + 3*382*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54138*0 + 3*382*FLEN/8, x4, x1, x2)

inst_18047:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xc1 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xe0fffe00; valaddr_reg:x3; val_offset:54141*0 + 3*383*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54141*0 + 3*383*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_4)

inst_18048:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xc1 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xe0ffff00; valaddr_reg:x3; val_offset:54144*0 + 3*384*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54144*0 + 3*384*FLEN/8, x4, x1, x2)

inst_18049:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xc1 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xe0ffff80; valaddr_reg:x3; val_offset:54147*0 + 3*385*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54147*0 + 3*385*FLEN/8, x4, x1, x2)

inst_18050:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xc1 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xe0ffffc0; valaddr_reg:x3; val_offset:54150*0 + 3*386*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54150*0 + 3*386*FLEN/8, x4, x1, x2)

inst_18051:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xc1 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xe0ffffe0; valaddr_reg:x3; val_offset:54153*0 + 3*387*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54153*0 + 3*387*FLEN/8, x4, x1, x2)

inst_18052:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xc1 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xe0fffff0; valaddr_reg:x3; val_offset:54156*0 + 3*388*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54156*0 + 3*388*FLEN/8, x4, x1, x2)

inst_18053:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xc1 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xe0fffff8; valaddr_reg:x3; val_offset:54159*0 + 3*389*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54159*0 + 3*389*FLEN/8, x4, x1, x2)

inst_18054:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xc1 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xe0fffffc; valaddr_reg:x3; val_offset:54162*0 + 3*390*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54162*0 + 3*390*FLEN/8, x4, x1, x2)

inst_18055:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xc1 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xe0fffffe; valaddr_reg:x3; val_offset:54165*0 + 3*391*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54165*0 + 3*391*FLEN/8, x4, x1, x2)

inst_18056:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xc1 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xe0ffffff; valaddr_reg:x3; val_offset:54168*0 + 3*392*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54168*0 + 3*392*FLEN/8, x4, x1, x2)

inst_18057:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xff000001; valaddr_reg:x3; val_offset:54171*0 + 3*393*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54171*0 + 3*393*FLEN/8, x4, x1, x2)

inst_18058:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xff000003; valaddr_reg:x3; val_offset:54174*0 + 3*394*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54174*0 + 3*394*FLEN/8, x4, x1, x2)

inst_18059:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xff000007; valaddr_reg:x3; val_offset:54177*0 + 3*395*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54177*0 + 3*395*FLEN/8, x4, x1, x2)

inst_18060:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xff199999; valaddr_reg:x3; val_offset:54180*0 + 3*396*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54180*0 + 3*396*FLEN/8, x4, x1, x2)

inst_18061:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xff249249; valaddr_reg:x3; val_offset:54183*0 + 3*397*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54183*0 + 3*397*FLEN/8, x4, x1, x2)

inst_18062:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xff333333; valaddr_reg:x3; val_offset:54186*0 + 3*398*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54186*0 + 3*398*FLEN/8, x4, x1, x2)

inst_18063:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xff36db6d; valaddr_reg:x3; val_offset:54189*0 + 3*399*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54189*0 + 3*399*FLEN/8, x4, x1, x2)

inst_18064:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xff3bbbbb; valaddr_reg:x3; val_offset:54192*0 + 3*400*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54192*0 + 3*400*FLEN/8, x4, x1, x2)

inst_18065:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xff444444; valaddr_reg:x3; val_offset:54195*0 + 3*401*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54195*0 + 3*401*FLEN/8, x4, x1, x2)

inst_18066:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xff4ccccc; valaddr_reg:x3; val_offset:54198*0 + 3*402*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54198*0 + 3*402*FLEN/8, x4, x1, x2)

inst_18067:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xff5b6db6; valaddr_reg:x3; val_offset:54201*0 + 3*403*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54201*0 + 3*403*FLEN/8, x4, x1, x2)

inst_18068:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xff666666; valaddr_reg:x3; val_offset:54204*0 + 3*404*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54204*0 + 3*404*FLEN/8, x4, x1, x2)

inst_18069:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xff6db6db; valaddr_reg:x3; val_offset:54207*0 + 3*405*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54207*0 + 3*405*FLEN/8, x4, x1, x2)

inst_18070:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xff7ffff8; valaddr_reg:x3; val_offset:54210*0 + 3*406*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54210*0 + 3*406*FLEN/8, x4, x1, x2)

inst_18071:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xff7ffffc; valaddr_reg:x3; val_offset:54213*0 + 3*407*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54213*0 + 3*407*FLEN/8, x4, x1, x2)

inst_18072:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d220 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3537d3 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d220; op2val:0xc03537d3;
op3val:0xff7ffffe; valaddr_reg:x3; val_offset:54216*0 + 3*408*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54216*0 + 3*408*FLEN/8, x4, x1, x2)

inst_18073:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0x800001; valaddr_reg:x3; val_offset:54219*0 + 3*409*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54219*0 + 3*409*FLEN/8, x4, x1, x2)

inst_18074:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0x800003; valaddr_reg:x3; val_offset:54222*0 + 3*410*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54222*0 + 3*410*FLEN/8, x4, x1, x2)

inst_18075:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0x800007; valaddr_reg:x3; val_offset:54225*0 + 3*411*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54225*0 + 3*411*FLEN/8, x4, x1, x2)

inst_18076:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0x999999; valaddr_reg:x3; val_offset:54228*0 + 3*412*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54228*0 + 3*412*FLEN/8, x4, x1, x2)

inst_18077:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0xa49249; valaddr_reg:x3; val_offset:54231*0 + 3*413*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54231*0 + 3*413*FLEN/8, x4, x1, x2)

inst_18078:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0xb33333; valaddr_reg:x3; val_offset:54234*0 + 3*414*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54234*0 + 3*414*FLEN/8, x4, x1, x2)

inst_18079:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0xb6db6d; valaddr_reg:x3; val_offset:54237*0 + 3*415*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54237*0 + 3*415*FLEN/8, x4, x1, x2)

inst_18080:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0xbbbbbb; valaddr_reg:x3; val_offset:54240*0 + 3*416*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54240*0 + 3*416*FLEN/8, x4, x1, x2)

inst_18081:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0xc44444; valaddr_reg:x3; val_offset:54243*0 + 3*417*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54243*0 + 3*417*FLEN/8, x4, x1, x2)

inst_18082:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0xcccccc; valaddr_reg:x3; val_offset:54246*0 + 3*418*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54246*0 + 3*418*FLEN/8, x4, x1, x2)

inst_18083:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0xdb6db6; valaddr_reg:x3; val_offset:54249*0 + 3*419*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54249*0 + 3*419*FLEN/8, x4, x1, x2)

inst_18084:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0xe66666; valaddr_reg:x3; val_offset:54252*0 + 3*420*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54252*0 + 3*420*FLEN/8, x4, x1, x2)

inst_18085:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0xedb6db; valaddr_reg:x3; val_offset:54255*0 + 3*421*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54255*0 + 3*421*FLEN/8, x4, x1, x2)

inst_18086:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0xfffff8; valaddr_reg:x3; val_offset:54258*0 + 3*422*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54258*0 + 3*422*FLEN/8, x4, x1, x2)

inst_18087:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0xfffffc; valaddr_reg:x3; val_offset:54261*0 + 3*423*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54261*0 + 3*423*FLEN/8, x4, x1, x2)

inst_18088:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0xfffffe; valaddr_reg:x3; val_offset:54264*0 + 3*424*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54264*0 + 3*424*FLEN/8, x4, x1, x2)

inst_18089:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0x6000000; valaddr_reg:x3; val_offset:54267*0 + 3*425*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54267*0 + 3*425*FLEN/8, x4, x1, x2)

inst_18090:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0x6000001; valaddr_reg:x3; val_offset:54270*0 + 3*426*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54270*0 + 3*426*FLEN/8, x4, x1, x2)

inst_18091:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0x6000003; valaddr_reg:x3; val_offset:54273*0 + 3*427*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54273*0 + 3*427*FLEN/8, x4, x1, x2)

inst_18092:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0x6000007; valaddr_reg:x3; val_offset:54276*0 + 3*428*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54276*0 + 3*428*FLEN/8, x4, x1, x2)

inst_18093:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0x600000f; valaddr_reg:x3; val_offset:54279*0 + 3*429*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54279*0 + 3*429*FLEN/8, x4, x1, x2)

inst_18094:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0x600001f; valaddr_reg:x3; val_offset:54282*0 + 3*430*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54282*0 + 3*430*FLEN/8, x4, x1, x2)

inst_18095:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0x600003f; valaddr_reg:x3; val_offset:54285*0 + 3*431*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54285*0 + 3*431*FLEN/8, x4, x1, x2)

inst_18096:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0x600007f; valaddr_reg:x3; val_offset:54288*0 + 3*432*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54288*0 + 3*432*FLEN/8, x4, x1, x2)

inst_18097:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0x60000ff; valaddr_reg:x3; val_offset:54291*0 + 3*433*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54291*0 + 3*433*FLEN/8, x4, x1, x2)

inst_18098:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0x60001ff; valaddr_reg:x3; val_offset:54294*0 + 3*434*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54294*0 + 3*434*FLEN/8, x4, x1, x2)

inst_18099:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0x60003ff; valaddr_reg:x3; val_offset:54297*0 + 3*435*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54297*0 + 3*435*FLEN/8, x4, x1, x2)

inst_18100:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0x60007ff; valaddr_reg:x3; val_offset:54300*0 + 3*436*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54300*0 + 3*436*FLEN/8, x4, x1, x2)

inst_18101:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0x6000fff; valaddr_reg:x3; val_offset:54303*0 + 3*437*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54303*0 + 3*437*FLEN/8, x4, x1, x2)

inst_18102:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0x6001fff; valaddr_reg:x3; val_offset:54306*0 + 3*438*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54306*0 + 3*438*FLEN/8, x4, x1, x2)

inst_18103:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0x6003fff; valaddr_reg:x3; val_offset:54309*0 + 3*439*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54309*0 + 3*439*FLEN/8, x4, x1, x2)

inst_18104:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0x6007fff; valaddr_reg:x3; val_offset:54312*0 + 3*440*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54312*0 + 3*440*FLEN/8, x4, x1, x2)

inst_18105:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0x600ffff; valaddr_reg:x3; val_offset:54315*0 + 3*441*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54315*0 + 3*441*FLEN/8, x4, x1, x2)

inst_18106:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0x601ffff; valaddr_reg:x3; val_offset:54318*0 + 3*442*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54318*0 + 3*442*FLEN/8, x4, x1, x2)

inst_18107:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0x603ffff; valaddr_reg:x3; val_offset:54321*0 + 3*443*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54321*0 + 3*443*FLEN/8, x4, x1, x2)

inst_18108:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0x607ffff; valaddr_reg:x3; val_offset:54324*0 + 3*444*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54324*0 + 3*444*FLEN/8, x4, x1, x2)

inst_18109:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0x60fffff; valaddr_reg:x3; val_offset:54327*0 + 3*445*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54327*0 + 3*445*FLEN/8, x4, x1, x2)

inst_18110:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0x61fffff; valaddr_reg:x3; val_offset:54330*0 + 3*446*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54330*0 + 3*446*FLEN/8, x4, x1, x2)

inst_18111:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0x63fffff; valaddr_reg:x3; val_offset:54333*0 + 3*447*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54333*0 + 3*447*FLEN/8, x4, x1, x2)

inst_18112:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0x6400000; valaddr_reg:x3; val_offset:54336*0 + 3*448*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54336*0 + 3*448*FLEN/8, x4, x1, x2)

inst_18113:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0x6600000; valaddr_reg:x3; val_offset:54339*0 + 3*449*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54339*0 + 3*449*FLEN/8, x4, x1, x2)

inst_18114:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0x6700000; valaddr_reg:x3; val_offset:54342*0 + 3*450*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54342*0 + 3*450*FLEN/8, x4, x1, x2)

inst_18115:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0x6780000; valaddr_reg:x3; val_offset:54345*0 + 3*451*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54345*0 + 3*451*FLEN/8, x4, x1, x2)

inst_18116:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0x67c0000; valaddr_reg:x3; val_offset:54348*0 + 3*452*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54348*0 + 3*452*FLEN/8, x4, x1, x2)

inst_18117:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0x67e0000; valaddr_reg:x3; val_offset:54351*0 + 3*453*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54351*0 + 3*453*FLEN/8, x4, x1, x2)

inst_18118:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0x67f0000; valaddr_reg:x3; val_offset:54354*0 + 3*454*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54354*0 + 3*454*FLEN/8, x4, x1, x2)

inst_18119:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0x67f8000; valaddr_reg:x3; val_offset:54357*0 + 3*455*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54357*0 + 3*455*FLEN/8, x4, x1, x2)

inst_18120:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0x67fc000; valaddr_reg:x3; val_offset:54360*0 + 3*456*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54360*0 + 3*456*FLEN/8, x4, x1, x2)

inst_18121:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0x67fe000; valaddr_reg:x3; val_offset:54363*0 + 3*457*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54363*0 + 3*457*FLEN/8, x4, x1, x2)

inst_18122:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0x67ff000; valaddr_reg:x3; val_offset:54366*0 + 3*458*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54366*0 + 3*458*FLEN/8, x4, x1, x2)

inst_18123:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0x67ff800; valaddr_reg:x3; val_offset:54369*0 + 3*459*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54369*0 + 3*459*FLEN/8, x4, x1, x2)

inst_18124:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0x67ffc00; valaddr_reg:x3; val_offset:54372*0 + 3*460*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54372*0 + 3*460*FLEN/8, x4, x1, x2)

inst_18125:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0x67ffe00; valaddr_reg:x3; val_offset:54375*0 + 3*461*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54375*0 + 3*461*FLEN/8, x4, x1, x2)

inst_18126:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0x67fff00; valaddr_reg:x3; val_offset:54378*0 + 3*462*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54378*0 + 3*462*FLEN/8, x4, x1, x2)

inst_18127:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0x67fff80; valaddr_reg:x3; val_offset:54381*0 + 3*463*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54381*0 + 3*463*FLEN/8, x4, x1, x2)

inst_18128:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0x67fffc0; valaddr_reg:x3; val_offset:54384*0 + 3*464*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54384*0 + 3*464*FLEN/8, x4, x1, x2)

inst_18129:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0x67fffe0; valaddr_reg:x3; val_offset:54387*0 + 3*465*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54387*0 + 3*465*FLEN/8, x4, x1, x2)

inst_18130:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0x67ffff0; valaddr_reg:x3; val_offset:54390*0 + 3*466*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54390*0 + 3*466*FLEN/8, x4, x1, x2)

inst_18131:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0x67ffff8; valaddr_reg:x3; val_offset:54393*0 + 3*467*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54393*0 + 3*467*FLEN/8, x4, x1, x2)

inst_18132:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0x67ffffc; valaddr_reg:x3; val_offset:54396*0 + 3*468*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54396*0 + 3*468*FLEN/8, x4, x1, x2)

inst_18133:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0x67ffffe; valaddr_reg:x3; val_offset:54399*0 + 3*469*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54399*0 + 3*469*FLEN/8, x4, x1, x2)

inst_18134:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x34d24a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb4d24a; op2val:0x0;
op3val:0x67fffff; valaddr_reg:x3; val_offset:54402*0 + 3*470*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54402*0 + 3*470*FLEN/8, x4, x1, x2)

inst_18135:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xde and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xef000000; valaddr_reg:x3; val_offset:54405*0 + 3*471*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54405*0 + 3*471*FLEN/8, x4, x1, x2)

inst_18136:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xde and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xef000001; valaddr_reg:x3; val_offset:54408*0 + 3*472*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54408*0 + 3*472*FLEN/8, x4, x1, x2)

inst_18137:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xde and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xef000003; valaddr_reg:x3; val_offset:54411*0 + 3*473*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54411*0 + 3*473*FLEN/8, x4, x1, x2)

inst_18138:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xde and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xef000007; valaddr_reg:x3; val_offset:54414*0 + 3*474*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54414*0 + 3*474*FLEN/8, x4, x1, x2)

inst_18139:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xde and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xef00000f; valaddr_reg:x3; val_offset:54417*0 + 3*475*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54417*0 + 3*475*FLEN/8, x4, x1, x2)

inst_18140:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xde and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xef00001f; valaddr_reg:x3; val_offset:54420*0 + 3*476*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54420*0 + 3*476*FLEN/8, x4, x1, x2)

inst_18141:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xde and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xef00003f; valaddr_reg:x3; val_offset:54423*0 + 3*477*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54423*0 + 3*477*FLEN/8, x4, x1, x2)

inst_18142:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xde and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xef00007f; valaddr_reg:x3; val_offset:54426*0 + 3*478*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54426*0 + 3*478*FLEN/8, x4, x1, x2)

inst_18143:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xde and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xef0000ff; valaddr_reg:x3; val_offset:54429*0 + 3*479*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54429*0 + 3*479*FLEN/8, x4, x1, x2)

inst_18144:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xde and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xef0001ff; valaddr_reg:x3; val_offset:54432*0 + 3*480*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54432*0 + 3*480*FLEN/8, x4, x1, x2)

inst_18145:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xde and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xef0003ff; valaddr_reg:x3; val_offset:54435*0 + 3*481*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54435*0 + 3*481*FLEN/8, x4, x1, x2)

inst_18146:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xde and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xef0007ff; valaddr_reg:x3; val_offset:54438*0 + 3*482*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54438*0 + 3*482*FLEN/8, x4, x1, x2)

inst_18147:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xde and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xef000fff; valaddr_reg:x3; val_offset:54441*0 + 3*483*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54441*0 + 3*483*FLEN/8, x4, x1, x2)

inst_18148:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xde and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xef001fff; valaddr_reg:x3; val_offset:54444*0 + 3*484*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54444*0 + 3*484*FLEN/8, x4, x1, x2)

inst_18149:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xde and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xef003fff; valaddr_reg:x3; val_offset:54447*0 + 3*485*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54447*0 + 3*485*FLEN/8, x4, x1, x2)

inst_18150:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xde and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xef007fff; valaddr_reg:x3; val_offset:54450*0 + 3*486*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54450*0 + 3*486*FLEN/8, x4, x1, x2)

inst_18151:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xde and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xef00ffff; valaddr_reg:x3; val_offset:54453*0 + 3*487*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54453*0 + 3*487*FLEN/8, x4, x1, x2)

inst_18152:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xde and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xef01ffff; valaddr_reg:x3; val_offset:54456*0 + 3*488*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54456*0 + 3*488*FLEN/8, x4, x1, x2)

inst_18153:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xde and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xef03ffff; valaddr_reg:x3; val_offset:54459*0 + 3*489*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54459*0 + 3*489*FLEN/8, x4, x1, x2)

inst_18154:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xde and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xef07ffff; valaddr_reg:x3; val_offset:54462*0 + 3*490*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54462*0 + 3*490*FLEN/8, x4, x1, x2)

inst_18155:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xde and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xef0fffff; valaddr_reg:x3; val_offset:54465*0 + 3*491*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54465*0 + 3*491*FLEN/8, x4, x1, x2)

inst_18156:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xde and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xef1fffff; valaddr_reg:x3; val_offset:54468*0 + 3*492*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54468*0 + 3*492*FLEN/8, x4, x1, x2)

inst_18157:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xde and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xef3fffff; valaddr_reg:x3; val_offset:54471*0 + 3*493*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54471*0 + 3*493*FLEN/8, x4, x1, x2)

inst_18158:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xde and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xef400000; valaddr_reg:x3; val_offset:54474*0 + 3*494*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54474*0 + 3*494*FLEN/8, x4, x1, x2)

inst_18159:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xde and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xef600000; valaddr_reg:x3; val_offset:54477*0 + 3*495*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54477*0 + 3*495*FLEN/8, x4, x1, x2)

inst_18160:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xde and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xef700000; valaddr_reg:x3; val_offset:54480*0 + 3*496*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54480*0 + 3*496*FLEN/8, x4, x1, x2)

inst_18161:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xde and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xef780000; valaddr_reg:x3; val_offset:54483*0 + 3*497*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54483*0 + 3*497*FLEN/8, x4, x1, x2)

inst_18162:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xde and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xef7c0000; valaddr_reg:x3; val_offset:54486*0 + 3*498*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54486*0 + 3*498*FLEN/8, x4, x1, x2)

inst_18163:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xde and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xef7e0000; valaddr_reg:x3; val_offset:54489*0 + 3*499*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54489*0 + 3*499*FLEN/8, x4, x1, x2)

inst_18164:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xde and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xef7f0000; valaddr_reg:x3; val_offset:54492*0 + 3*500*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54492*0 + 3*500*FLEN/8, x4, x1, x2)

inst_18165:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xde and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xef7f8000; valaddr_reg:x3; val_offset:54495*0 + 3*501*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54495*0 + 3*501*FLEN/8, x4, x1, x2)

inst_18166:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xde and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xef7fc000; valaddr_reg:x3; val_offset:54498*0 + 3*502*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54498*0 + 3*502*FLEN/8, x4, x1, x2)

inst_18167:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xde and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xef7fe000; valaddr_reg:x3; val_offset:54501*0 + 3*503*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54501*0 + 3*503*FLEN/8, x4, x1, x2)

inst_18168:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xde and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xef7ff000; valaddr_reg:x3; val_offset:54504*0 + 3*504*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54504*0 + 3*504*FLEN/8, x4, x1, x2)

inst_18169:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xde and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xef7ff800; valaddr_reg:x3; val_offset:54507*0 + 3*505*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54507*0 + 3*505*FLEN/8, x4, x1, x2)

inst_18170:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xde and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xef7ffc00; valaddr_reg:x3; val_offset:54510*0 + 3*506*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54510*0 + 3*506*FLEN/8, x4, x1, x2)

inst_18171:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xde and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xef7ffe00; valaddr_reg:x3; val_offset:54513*0 + 3*507*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54513*0 + 3*507*FLEN/8, x4, x1, x2)

inst_18172:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xde and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xef7fff00; valaddr_reg:x3; val_offset:54516*0 + 3*508*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54516*0 + 3*508*FLEN/8, x4, x1, x2)

inst_18173:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xde and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xef7fff80; valaddr_reg:x3; val_offset:54519*0 + 3*509*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54519*0 + 3*509*FLEN/8, x4, x1, x2)

inst_18174:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xde and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xef7fffc0; valaddr_reg:x3; val_offset:54522*0 + 3*510*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54522*0 + 3*510*FLEN/8, x4, x1, x2)

inst_18175:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xde and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xef7fffe0; valaddr_reg:x3; val_offset:54525*0 + 3*511*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54525*0 + 3*511*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_5)

inst_18176:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xde and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xef7ffff0; valaddr_reg:x3; val_offset:54528*0 + 3*512*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54528*0 + 3*512*FLEN/8, x4, x1, x2)

inst_18177:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xde and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xef7ffff8; valaddr_reg:x3; val_offset:54531*0 + 3*513*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54531*0 + 3*513*FLEN/8, x4, x1, x2)

inst_18178:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xde and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xef7ffffc; valaddr_reg:x3; val_offset:54534*0 + 3*514*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54534*0 + 3*514*FLEN/8, x4, x1, x2)

inst_18179:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xde and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xef7ffffe; valaddr_reg:x3; val_offset:54537*0 + 3*515*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54537*0 + 3*515*FLEN/8, x4, x1, x2)

inst_18180:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xde and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xef7fffff; valaddr_reg:x3; val_offset:54540*0 + 3*516*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54540*0 + 3*516*FLEN/8, x4, x1, x2)

inst_18181:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xff000001; valaddr_reg:x3; val_offset:54543*0 + 3*517*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54543*0 + 3*517*FLEN/8, x4, x1, x2)

inst_18182:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xff000003; valaddr_reg:x3; val_offset:54546*0 + 3*518*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54546*0 + 3*518*FLEN/8, x4, x1, x2)

inst_18183:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xff000007; valaddr_reg:x3; val_offset:54549*0 + 3*519*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54549*0 + 3*519*FLEN/8, x4, x1, x2)

inst_18184:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xff199999; valaddr_reg:x3; val_offset:54552*0 + 3*520*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54552*0 + 3*520*FLEN/8, x4, x1, x2)

inst_18185:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xff249249; valaddr_reg:x3; val_offset:54555*0 + 3*521*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54555*0 + 3*521*FLEN/8, x4, x1, x2)

inst_18186:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xff333333; valaddr_reg:x3; val_offset:54558*0 + 3*522*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54558*0 + 3*522*FLEN/8, x4, x1, x2)

inst_18187:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xff36db6d; valaddr_reg:x3; val_offset:54561*0 + 3*523*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54561*0 + 3*523*FLEN/8, x4, x1, x2)

inst_18188:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xff3bbbbb; valaddr_reg:x3; val_offset:54564*0 + 3*524*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54564*0 + 3*524*FLEN/8, x4, x1, x2)

inst_18189:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xff444444; valaddr_reg:x3; val_offset:54567*0 + 3*525*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54567*0 + 3*525*FLEN/8, x4, x1, x2)

inst_18190:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xff4ccccc; valaddr_reg:x3; val_offset:54570*0 + 3*526*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54570*0 + 3*526*FLEN/8, x4, x1, x2)

inst_18191:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xff5b6db6; valaddr_reg:x3; val_offset:54573*0 + 3*527*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54573*0 + 3*527*FLEN/8, x4, x1, x2)

inst_18192:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xff666666; valaddr_reg:x3; val_offset:54576*0 + 3*528*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54576*0 + 3*528*FLEN/8, x4, x1, x2)

inst_18193:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xff6db6db; valaddr_reg:x3; val_offset:54579*0 + 3*529*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54579*0 + 3*529*FLEN/8, x4, x1, x2)

inst_18194:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xff7ffff8; valaddr_reg:x3; val_offset:54582*0 + 3*530*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54582*0 + 3*530*FLEN/8, x4, x1, x2)

inst_18195:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xff7ffffc; valaddr_reg:x3; val_offset:54585*0 + 3*531*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54585*0 + 3*531*FLEN/8, x4, x1, x2)

inst_18196:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3507ef and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3501f5 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb507ef; op2val:0xc03501f5;
op3val:0xff7ffffe; valaddr_reg:x3; val_offset:54588*0 + 3*532*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54588*0 + 3*532*FLEN/8, x4, x1, x2)

inst_18197:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x1; valaddr_reg:x3; val_offset:54591*0 + 3*533*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54591*0 + 3*533*FLEN/8, x4, x1, x2)

inst_18198:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x3; valaddr_reg:x3; val_offset:54594*0 + 3*534*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54594*0 + 3*534*FLEN/8, x4, x1, x2)

inst_18199:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x7; valaddr_reg:x3; val_offset:54597*0 + 3*535*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54597*0 + 3*535*FLEN/8, x4, x1, x2)

inst_18200:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x199999; valaddr_reg:x3; val_offset:54600*0 + 3*536*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54600*0 + 3*536*FLEN/8, x4, x1, x2)

inst_18201:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x249249; valaddr_reg:x3; val_offset:54603*0 + 3*537*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54603*0 + 3*537*FLEN/8, x4, x1, x2)

inst_18202:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x333333; valaddr_reg:x3; val_offset:54606*0 + 3*538*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54606*0 + 3*538*FLEN/8, x4, x1, x2)

inst_18203:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x36db6d; valaddr_reg:x3; val_offset:54609*0 + 3*539*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54609*0 + 3*539*FLEN/8, x4, x1, x2)

inst_18204:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x3bbbbb; valaddr_reg:x3; val_offset:54612*0 + 3*540*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54612*0 + 3*540*FLEN/8, x4, x1, x2)

inst_18205:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x444444; valaddr_reg:x3; val_offset:54615*0 + 3*541*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54615*0 + 3*541*FLEN/8, x4, x1, x2)

inst_18206:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x4ccccc; valaddr_reg:x3; val_offset:54618*0 + 3*542*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54618*0 + 3*542*FLEN/8, x4, x1, x2)

inst_18207:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x5b6db6; valaddr_reg:x3; val_offset:54621*0 + 3*543*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54621*0 + 3*543*FLEN/8, x4, x1, x2)

inst_18208:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x666666; valaddr_reg:x3; val_offset:54624*0 + 3*544*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54624*0 + 3*544*FLEN/8, x4, x1, x2)

inst_18209:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x6db6db; valaddr_reg:x3; val_offset:54627*0 + 3*545*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54627*0 + 3*545*FLEN/8, x4, x1, x2)

inst_18210:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x7ffff8; valaddr_reg:x3; val_offset:54630*0 + 3*546*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54630*0 + 3*546*FLEN/8, x4, x1, x2)

inst_18211:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x7ffffc; valaddr_reg:x3; val_offset:54633*0 + 3*547*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54633*0 + 3*547*FLEN/8, x4, x1, x2)

inst_18212:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x7ffffe; valaddr_reg:x3; val_offset:54636*0 + 3*548*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54636*0 + 3*548*FLEN/8, x4, x1, x2)

inst_18213:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x7800000; valaddr_reg:x3; val_offset:54639*0 + 3*549*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54639*0 + 3*549*FLEN/8, x4, x1, x2)

inst_18214:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x7800001; valaddr_reg:x3; val_offset:54642*0 + 3*550*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54642*0 + 3*550*FLEN/8, x4, x1, x2)

inst_18215:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x7800003; valaddr_reg:x3; val_offset:54645*0 + 3*551*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54645*0 + 3*551*FLEN/8, x4, x1, x2)

inst_18216:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x7800007; valaddr_reg:x3; val_offset:54648*0 + 3*552*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54648*0 + 3*552*FLEN/8, x4, x1, x2)

inst_18217:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x780000f; valaddr_reg:x3; val_offset:54651*0 + 3*553*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54651*0 + 3*553*FLEN/8, x4, x1, x2)

inst_18218:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x780001f; valaddr_reg:x3; val_offset:54654*0 + 3*554*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54654*0 + 3*554*FLEN/8, x4, x1, x2)

inst_18219:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x780003f; valaddr_reg:x3; val_offset:54657*0 + 3*555*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54657*0 + 3*555*FLEN/8, x4, x1, x2)

inst_18220:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x780007f; valaddr_reg:x3; val_offset:54660*0 + 3*556*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54660*0 + 3*556*FLEN/8, x4, x1, x2)

inst_18221:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x78000ff; valaddr_reg:x3; val_offset:54663*0 + 3*557*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54663*0 + 3*557*FLEN/8, x4, x1, x2)

inst_18222:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x78001ff; valaddr_reg:x3; val_offset:54666*0 + 3*558*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54666*0 + 3*558*FLEN/8, x4, x1, x2)

inst_18223:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x78003ff; valaddr_reg:x3; val_offset:54669*0 + 3*559*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54669*0 + 3*559*FLEN/8, x4, x1, x2)

inst_18224:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x78007ff; valaddr_reg:x3; val_offset:54672*0 + 3*560*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54672*0 + 3*560*FLEN/8, x4, x1, x2)

inst_18225:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x7800fff; valaddr_reg:x3; val_offset:54675*0 + 3*561*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54675*0 + 3*561*FLEN/8, x4, x1, x2)

inst_18226:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x7801fff; valaddr_reg:x3; val_offset:54678*0 + 3*562*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54678*0 + 3*562*FLEN/8, x4, x1, x2)

inst_18227:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x7803fff; valaddr_reg:x3; val_offset:54681*0 + 3*563*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54681*0 + 3*563*FLEN/8, x4, x1, x2)

inst_18228:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x7807fff; valaddr_reg:x3; val_offset:54684*0 + 3*564*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54684*0 + 3*564*FLEN/8, x4, x1, x2)

inst_18229:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x780ffff; valaddr_reg:x3; val_offset:54687*0 + 3*565*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54687*0 + 3*565*FLEN/8, x4, x1, x2)

inst_18230:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x781ffff; valaddr_reg:x3; val_offset:54690*0 + 3*566*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54690*0 + 3*566*FLEN/8, x4, x1, x2)

inst_18231:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x783ffff; valaddr_reg:x3; val_offset:54693*0 + 3*567*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54693*0 + 3*567*FLEN/8, x4, x1, x2)

inst_18232:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x787ffff; valaddr_reg:x3; val_offset:54696*0 + 3*568*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54696*0 + 3*568*FLEN/8, x4, x1, x2)

inst_18233:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x78fffff; valaddr_reg:x3; val_offset:54699*0 + 3*569*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54699*0 + 3*569*FLEN/8, x4, x1, x2)

inst_18234:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x79fffff; valaddr_reg:x3; val_offset:54702*0 + 3*570*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54702*0 + 3*570*FLEN/8, x4, x1, x2)

inst_18235:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x7bfffff; valaddr_reg:x3; val_offset:54705*0 + 3*571*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54705*0 + 3*571*FLEN/8, x4, x1, x2)

inst_18236:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x7c00000; valaddr_reg:x3; val_offset:54708*0 + 3*572*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54708*0 + 3*572*FLEN/8, x4, x1, x2)

inst_18237:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x7e00000; valaddr_reg:x3; val_offset:54711*0 + 3*573*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54711*0 + 3*573*FLEN/8, x4, x1, x2)

inst_18238:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x7f00000; valaddr_reg:x3; val_offset:54714*0 + 3*574*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54714*0 + 3*574*FLEN/8, x4, x1, x2)

inst_18239:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x7f80000; valaddr_reg:x3; val_offset:54717*0 + 3*575*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54717*0 + 3*575*FLEN/8, x4, x1, x2)

inst_18240:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x7fc0000; valaddr_reg:x3; val_offset:54720*0 + 3*576*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54720*0 + 3*576*FLEN/8, x4, x1, x2)

inst_18241:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x7fe0000; valaddr_reg:x3; val_offset:54723*0 + 3*577*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54723*0 + 3*577*FLEN/8, x4, x1, x2)

inst_18242:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x7ff0000; valaddr_reg:x3; val_offset:54726*0 + 3*578*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54726*0 + 3*578*FLEN/8, x4, x1, x2)

inst_18243:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x7ff8000; valaddr_reg:x3; val_offset:54729*0 + 3*579*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54729*0 + 3*579*FLEN/8, x4, x1, x2)

inst_18244:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x7ffc000; valaddr_reg:x3; val_offset:54732*0 + 3*580*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54732*0 + 3*580*FLEN/8, x4, x1, x2)

inst_18245:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x7ffe000; valaddr_reg:x3; val_offset:54735*0 + 3*581*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54735*0 + 3*581*FLEN/8, x4, x1, x2)

inst_18246:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x7fff000; valaddr_reg:x3; val_offset:54738*0 + 3*582*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54738*0 + 3*582*FLEN/8, x4, x1, x2)

inst_18247:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x7fff800; valaddr_reg:x3; val_offset:54741*0 + 3*583*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54741*0 + 3*583*FLEN/8, x4, x1, x2)

inst_18248:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x7fffc00; valaddr_reg:x3; val_offset:54744*0 + 3*584*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54744*0 + 3*584*FLEN/8, x4, x1, x2)

inst_18249:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x7fffe00; valaddr_reg:x3; val_offset:54747*0 + 3*585*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54747*0 + 3*585*FLEN/8, x4, x1, x2)

inst_18250:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x7ffff00; valaddr_reg:x3; val_offset:54750*0 + 3*586*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54750*0 + 3*586*FLEN/8, x4, x1, x2)

inst_18251:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x7ffff80; valaddr_reg:x3; val_offset:54753*0 + 3*587*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54753*0 + 3*587*FLEN/8, x4, x1, x2)

inst_18252:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x7ffffc0; valaddr_reg:x3; val_offset:54756*0 + 3*588*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54756*0 + 3*588*FLEN/8, x4, x1, x2)

inst_18253:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x7ffffe0; valaddr_reg:x3; val_offset:54759*0 + 3*589*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54759*0 + 3*589*FLEN/8, x4, x1, x2)

inst_18254:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x7fffff0; valaddr_reg:x3; val_offset:54762*0 + 3*590*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54762*0 + 3*590*FLEN/8, x4, x1, x2)

inst_18255:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x7fffff8; valaddr_reg:x3; val_offset:54765*0 + 3*591*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54765*0 + 3*591*FLEN/8, x4, x1, x2)

inst_18256:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x7fffffc; valaddr_reg:x3; val_offset:54768*0 + 3*592*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54768*0 + 3*592*FLEN/8, x4, x1, x2)

inst_18257:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x7fffffe; valaddr_reg:x3; val_offset:54771*0 + 3*593*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54771*0 + 3*593*FLEN/8, x4, x1, x2)

inst_18258:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36048d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6048d; op2val:0x0;
op3val:0x7ffffff; valaddr_reg:x3; val_offset:54774*0 + 3*594*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54774*0 + 3*594*FLEN/8, x4, x1, x2)

inst_18259:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x79 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbc800000; valaddr_reg:x3; val_offset:54777*0 + 3*595*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54777*0 + 3*595*FLEN/8, x4, x1, x2)

inst_18260:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x79 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbc800001; valaddr_reg:x3; val_offset:54780*0 + 3*596*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54780*0 + 3*596*FLEN/8, x4, x1, x2)

inst_18261:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x79 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbc800003; valaddr_reg:x3; val_offset:54783*0 + 3*597*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54783*0 + 3*597*FLEN/8, x4, x1, x2)

inst_18262:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x79 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbc800007; valaddr_reg:x3; val_offset:54786*0 + 3*598*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54786*0 + 3*598*FLEN/8, x4, x1, x2)

inst_18263:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x79 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbc80000f; valaddr_reg:x3; val_offset:54789*0 + 3*599*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54789*0 + 3*599*FLEN/8, x4, x1, x2)

inst_18264:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x79 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbc80001f; valaddr_reg:x3; val_offset:54792*0 + 3*600*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54792*0 + 3*600*FLEN/8, x4, x1, x2)

inst_18265:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x79 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbc80003f; valaddr_reg:x3; val_offset:54795*0 + 3*601*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54795*0 + 3*601*FLEN/8, x4, x1, x2)

inst_18266:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x79 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbc80007f; valaddr_reg:x3; val_offset:54798*0 + 3*602*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54798*0 + 3*602*FLEN/8, x4, x1, x2)

inst_18267:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x79 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbc8000ff; valaddr_reg:x3; val_offset:54801*0 + 3*603*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54801*0 + 3*603*FLEN/8, x4, x1, x2)

inst_18268:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x79 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbc8001ff; valaddr_reg:x3; val_offset:54804*0 + 3*604*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54804*0 + 3*604*FLEN/8, x4, x1, x2)

inst_18269:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x79 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbc8003ff; valaddr_reg:x3; val_offset:54807*0 + 3*605*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54807*0 + 3*605*FLEN/8, x4, x1, x2)

inst_18270:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x79 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbc8007ff; valaddr_reg:x3; val_offset:54810*0 + 3*606*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54810*0 + 3*606*FLEN/8, x4, x1, x2)

inst_18271:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x79 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbc800fff; valaddr_reg:x3; val_offset:54813*0 + 3*607*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54813*0 + 3*607*FLEN/8, x4, x1, x2)

inst_18272:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x79 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbc801fff; valaddr_reg:x3; val_offset:54816*0 + 3*608*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54816*0 + 3*608*FLEN/8, x4, x1, x2)

inst_18273:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x79 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbc803fff; valaddr_reg:x3; val_offset:54819*0 + 3*609*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54819*0 + 3*609*FLEN/8, x4, x1, x2)

inst_18274:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x79 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbc807fff; valaddr_reg:x3; val_offset:54822*0 + 3*610*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54822*0 + 3*610*FLEN/8, x4, x1, x2)

inst_18275:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x79 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbc80ffff; valaddr_reg:x3; val_offset:54825*0 + 3*611*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54825*0 + 3*611*FLEN/8, x4, x1, x2)

inst_18276:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x79 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbc81ffff; valaddr_reg:x3; val_offset:54828*0 + 3*612*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54828*0 + 3*612*FLEN/8, x4, x1, x2)

inst_18277:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x79 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbc83ffff; valaddr_reg:x3; val_offset:54831*0 + 3*613*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54831*0 + 3*613*FLEN/8, x4, x1, x2)

inst_18278:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x79 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbc87ffff; valaddr_reg:x3; val_offset:54834*0 + 3*614*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54834*0 + 3*614*FLEN/8, x4, x1, x2)

inst_18279:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x79 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbc8fffff; valaddr_reg:x3; val_offset:54837*0 + 3*615*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54837*0 + 3*615*FLEN/8, x4, x1, x2)

inst_18280:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x79 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbc9fffff; valaddr_reg:x3; val_offset:54840*0 + 3*616*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54840*0 + 3*616*FLEN/8, x4, x1, x2)

inst_18281:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x79 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbcbfffff; valaddr_reg:x3; val_offset:54843*0 + 3*617*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54843*0 + 3*617*FLEN/8, x4, x1, x2)

inst_18282:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x79 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbcc00000; valaddr_reg:x3; val_offset:54846*0 + 3*618*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54846*0 + 3*618*FLEN/8, x4, x1, x2)

inst_18283:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x79 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbce00000; valaddr_reg:x3; val_offset:54849*0 + 3*619*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54849*0 + 3*619*FLEN/8, x4, x1, x2)

inst_18284:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x79 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbcf00000; valaddr_reg:x3; val_offset:54852*0 + 3*620*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54852*0 + 3*620*FLEN/8, x4, x1, x2)

inst_18285:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x79 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbcf80000; valaddr_reg:x3; val_offset:54855*0 + 3*621*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54855*0 + 3*621*FLEN/8, x4, x1, x2)

inst_18286:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x79 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbcfc0000; valaddr_reg:x3; val_offset:54858*0 + 3*622*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54858*0 + 3*622*FLEN/8, x4, x1, x2)

inst_18287:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x79 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbcfe0000; valaddr_reg:x3; val_offset:54861*0 + 3*623*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54861*0 + 3*623*FLEN/8, x4, x1, x2)

inst_18288:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x79 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbcff0000; valaddr_reg:x3; val_offset:54864*0 + 3*624*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54864*0 + 3*624*FLEN/8, x4, x1, x2)

inst_18289:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x79 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbcff8000; valaddr_reg:x3; val_offset:54867*0 + 3*625*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54867*0 + 3*625*FLEN/8, x4, x1, x2)

inst_18290:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x79 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbcffc000; valaddr_reg:x3; val_offset:54870*0 + 3*626*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54870*0 + 3*626*FLEN/8, x4, x1, x2)

inst_18291:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x79 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbcffe000; valaddr_reg:x3; val_offset:54873*0 + 3*627*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54873*0 + 3*627*FLEN/8, x4, x1, x2)

inst_18292:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x79 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbcfff000; valaddr_reg:x3; val_offset:54876*0 + 3*628*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54876*0 + 3*628*FLEN/8, x4, x1, x2)

inst_18293:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x79 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbcfff800; valaddr_reg:x3; val_offset:54879*0 + 3*629*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54879*0 + 3*629*FLEN/8, x4, x1, x2)

inst_18294:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x79 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbcfffc00; valaddr_reg:x3; val_offset:54882*0 + 3*630*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54882*0 + 3*630*FLEN/8, x4, x1, x2)

inst_18295:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x79 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbcfffe00; valaddr_reg:x3; val_offset:54885*0 + 3*631*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54885*0 + 3*631*FLEN/8, x4, x1, x2)

inst_18296:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x79 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbcffff00; valaddr_reg:x3; val_offset:54888*0 + 3*632*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54888*0 + 3*632*FLEN/8, x4, x1, x2)

inst_18297:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x79 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbcffff80; valaddr_reg:x3; val_offset:54891*0 + 3*633*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54891*0 + 3*633*FLEN/8, x4, x1, x2)

inst_18298:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x79 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbcffffc0; valaddr_reg:x3; val_offset:54894*0 + 3*634*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54894*0 + 3*634*FLEN/8, x4, x1, x2)

inst_18299:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x79 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbcffffe0; valaddr_reg:x3; val_offset:54897*0 + 3*635*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54897*0 + 3*635*FLEN/8, x4, x1, x2)

inst_18300:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x79 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbcfffff0; valaddr_reg:x3; val_offset:54900*0 + 3*636*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54900*0 + 3*636*FLEN/8, x4, x1, x2)

inst_18301:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x79 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbcfffff8; valaddr_reg:x3; val_offset:54903*0 + 3*637*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54903*0 + 3*637*FLEN/8, x4, x1, x2)

inst_18302:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x79 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbcfffffc; valaddr_reg:x3; val_offset:54906*0 + 3*638*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54906*0 + 3*638*FLEN/8, x4, x1, x2)

inst_18303:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x79 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbcfffffe; valaddr_reg:x3; val_offset:54909*0 + 3*639*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54909*0 + 3*639*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_6)

inst_18304:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x79 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbcffffff; valaddr_reg:x3; val_offset:54912*0 + 3*640*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54912*0 + 3*640*FLEN/8, x4, x1, x2)

inst_18305:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbf800001; valaddr_reg:x3; val_offset:54915*0 + 3*641*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54915*0 + 3*641*FLEN/8, x4, x1, x2)

inst_18306:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbf800003; valaddr_reg:x3; val_offset:54918*0 + 3*642*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54918*0 + 3*642*FLEN/8, x4, x1, x2)

inst_18307:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbf800007; valaddr_reg:x3; val_offset:54921*0 + 3*643*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54921*0 + 3*643*FLEN/8, x4, x1, x2)

inst_18308:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbf999999; valaddr_reg:x3; val_offset:54924*0 + 3*644*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54924*0 + 3*644*FLEN/8, x4, x1, x2)

inst_18309:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbfa49249; valaddr_reg:x3; val_offset:54927*0 + 3*645*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54927*0 + 3*645*FLEN/8, x4, x1, x2)

inst_18310:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbfb33333; valaddr_reg:x3; val_offset:54930*0 + 3*646*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54930*0 + 3*646*FLEN/8, x4, x1, x2)

inst_18311:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbfb6db6d; valaddr_reg:x3; val_offset:54933*0 + 3*647*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54933*0 + 3*647*FLEN/8, x4, x1, x2)

inst_18312:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbfbbbbbb; valaddr_reg:x3; val_offset:54936*0 + 3*648*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54936*0 + 3*648*FLEN/8, x4, x1, x2)

inst_18313:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbfc44444; valaddr_reg:x3; val_offset:54939*0 + 3*649*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54939*0 + 3*649*FLEN/8, x4, x1, x2)

inst_18314:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbfcccccc; valaddr_reg:x3; val_offset:54942*0 + 3*650*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54942*0 + 3*650*FLEN/8, x4, x1, x2)

inst_18315:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbfdb6db6; valaddr_reg:x3; val_offset:54945*0 + 3*651*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54945*0 + 3*651*FLEN/8, x4, x1, x2)

inst_18316:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbfe66666; valaddr_reg:x3; val_offset:54948*0 + 3*652*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54948*0 + 3*652*FLEN/8, x4, x1, x2)

inst_18317:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbfedb6db; valaddr_reg:x3; val_offset:54951*0 + 3*653*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54951*0 + 3*653*FLEN/8, x4, x1, x2)

inst_18318:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbffffff8; valaddr_reg:x3; val_offset:54954*0 + 3*654*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54954*0 + 3*654*FLEN/8, x4, x1, x2)

inst_18319:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbffffffc; valaddr_reg:x3; val_offset:54957*0 + 3*655*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54957*0 + 3*655*FLEN/8, x4, x1, x2)

inst_18320:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x36a1eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x59b5d0 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb6a1eb; op2val:0x8059b5d0;
op3val:0xbffffffe; valaddr_reg:x3; val_offset:54960*0 + 3*656*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54960*0 + 3*656*FLEN/8, x4, x1, x2)

inst_18321:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x6c000000; valaddr_reg:x3; val_offset:54963*0 + 3*657*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54963*0 + 3*657*FLEN/8, x4, x1, x2)

inst_18322:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x6c000001; valaddr_reg:x3; val_offset:54966*0 + 3*658*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54966*0 + 3*658*FLEN/8, x4, x1, x2)

inst_18323:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x6c000003; valaddr_reg:x3; val_offset:54969*0 + 3*659*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54969*0 + 3*659*FLEN/8, x4, x1, x2)

inst_18324:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x6c000007; valaddr_reg:x3; val_offset:54972*0 + 3*660*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54972*0 + 3*660*FLEN/8, x4, x1, x2)

inst_18325:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x6c00000f; valaddr_reg:x3; val_offset:54975*0 + 3*661*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54975*0 + 3*661*FLEN/8, x4, x1, x2)

inst_18326:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x6c00001f; valaddr_reg:x3; val_offset:54978*0 + 3*662*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54978*0 + 3*662*FLEN/8, x4, x1, x2)

inst_18327:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x6c00003f; valaddr_reg:x3; val_offset:54981*0 + 3*663*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54981*0 + 3*663*FLEN/8, x4, x1, x2)

inst_18328:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x6c00007f; valaddr_reg:x3; val_offset:54984*0 + 3*664*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54984*0 + 3*664*FLEN/8, x4, x1, x2)

inst_18329:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x6c0000ff; valaddr_reg:x3; val_offset:54987*0 + 3*665*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54987*0 + 3*665*FLEN/8, x4, x1, x2)

inst_18330:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x6c0001ff; valaddr_reg:x3; val_offset:54990*0 + 3*666*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54990*0 + 3*666*FLEN/8, x4, x1, x2)

inst_18331:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x6c0003ff; valaddr_reg:x3; val_offset:54993*0 + 3*667*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54993*0 + 3*667*FLEN/8, x4, x1, x2)

inst_18332:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x6c0007ff; valaddr_reg:x3; val_offset:54996*0 + 3*668*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54996*0 + 3*668*FLEN/8, x4, x1, x2)

inst_18333:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x6c000fff; valaddr_reg:x3; val_offset:54999*0 + 3*669*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 54999*0 + 3*669*FLEN/8, x4, x1, x2)

inst_18334:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x6c001fff; valaddr_reg:x3; val_offset:55002*0 + 3*670*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55002*0 + 3*670*FLEN/8, x4, x1, x2)

inst_18335:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x6c003fff; valaddr_reg:x3; val_offset:55005*0 + 3*671*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55005*0 + 3*671*FLEN/8, x4, x1, x2)

inst_18336:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x6c007fff; valaddr_reg:x3; val_offset:55008*0 + 3*672*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55008*0 + 3*672*FLEN/8, x4, x1, x2)

inst_18337:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x6c00ffff; valaddr_reg:x3; val_offset:55011*0 + 3*673*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55011*0 + 3*673*FLEN/8, x4, x1, x2)

inst_18338:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x6c01ffff; valaddr_reg:x3; val_offset:55014*0 + 3*674*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55014*0 + 3*674*FLEN/8, x4, x1, x2)

inst_18339:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x6c03ffff; valaddr_reg:x3; val_offset:55017*0 + 3*675*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55017*0 + 3*675*FLEN/8, x4, x1, x2)

inst_18340:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x6c07ffff; valaddr_reg:x3; val_offset:55020*0 + 3*676*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55020*0 + 3*676*FLEN/8, x4, x1, x2)

inst_18341:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x6c0fffff; valaddr_reg:x3; val_offset:55023*0 + 3*677*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55023*0 + 3*677*FLEN/8, x4, x1, x2)

inst_18342:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x6c1fffff; valaddr_reg:x3; val_offset:55026*0 + 3*678*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55026*0 + 3*678*FLEN/8, x4, x1, x2)

inst_18343:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x6c3fffff; valaddr_reg:x3; val_offset:55029*0 + 3*679*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55029*0 + 3*679*FLEN/8, x4, x1, x2)

inst_18344:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x6c400000; valaddr_reg:x3; val_offset:55032*0 + 3*680*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55032*0 + 3*680*FLEN/8, x4, x1, x2)

inst_18345:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x6c600000; valaddr_reg:x3; val_offset:55035*0 + 3*681*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55035*0 + 3*681*FLEN/8, x4, x1, x2)

inst_18346:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x6c700000; valaddr_reg:x3; val_offset:55038*0 + 3*682*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55038*0 + 3*682*FLEN/8, x4, x1, x2)

inst_18347:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x6c780000; valaddr_reg:x3; val_offset:55041*0 + 3*683*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55041*0 + 3*683*FLEN/8, x4, x1, x2)

inst_18348:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x6c7c0000; valaddr_reg:x3; val_offset:55044*0 + 3*684*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55044*0 + 3*684*FLEN/8, x4, x1, x2)

inst_18349:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x6c7e0000; valaddr_reg:x3; val_offset:55047*0 + 3*685*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55047*0 + 3*685*FLEN/8, x4, x1, x2)

inst_18350:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x6c7f0000; valaddr_reg:x3; val_offset:55050*0 + 3*686*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55050*0 + 3*686*FLEN/8, x4, x1, x2)

inst_18351:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x6c7f8000; valaddr_reg:x3; val_offset:55053*0 + 3*687*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55053*0 + 3*687*FLEN/8, x4, x1, x2)

inst_18352:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x6c7fc000; valaddr_reg:x3; val_offset:55056*0 + 3*688*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55056*0 + 3*688*FLEN/8, x4, x1, x2)

inst_18353:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x6c7fe000; valaddr_reg:x3; val_offset:55059*0 + 3*689*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55059*0 + 3*689*FLEN/8, x4, x1, x2)

inst_18354:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x6c7ff000; valaddr_reg:x3; val_offset:55062*0 + 3*690*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55062*0 + 3*690*FLEN/8, x4, x1, x2)

inst_18355:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x6c7ff800; valaddr_reg:x3; val_offset:55065*0 + 3*691*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55065*0 + 3*691*FLEN/8, x4, x1, x2)

inst_18356:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x6c7ffc00; valaddr_reg:x3; val_offset:55068*0 + 3*692*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55068*0 + 3*692*FLEN/8, x4, x1, x2)

inst_18357:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x6c7ffe00; valaddr_reg:x3; val_offset:55071*0 + 3*693*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55071*0 + 3*693*FLEN/8, x4, x1, x2)

inst_18358:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x6c7fff00; valaddr_reg:x3; val_offset:55074*0 + 3*694*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55074*0 + 3*694*FLEN/8, x4, x1, x2)

inst_18359:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x6c7fff80; valaddr_reg:x3; val_offset:55077*0 + 3*695*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55077*0 + 3*695*FLEN/8, x4, x1, x2)

inst_18360:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x6c7fffc0; valaddr_reg:x3; val_offset:55080*0 + 3*696*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55080*0 + 3*696*FLEN/8, x4, x1, x2)

inst_18361:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x6c7fffe0; valaddr_reg:x3; val_offset:55083*0 + 3*697*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55083*0 + 3*697*FLEN/8, x4, x1, x2)

inst_18362:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x6c7ffff0; valaddr_reg:x3; val_offset:55086*0 + 3*698*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55086*0 + 3*698*FLEN/8, x4, x1, x2)

inst_18363:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x6c7ffff8; valaddr_reg:x3; val_offset:55089*0 + 3*699*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55089*0 + 3*699*FLEN/8, x4, x1, x2)

inst_18364:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x6c7ffffc; valaddr_reg:x3; val_offset:55092*0 + 3*700*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55092*0 + 3*700*FLEN/8, x4, x1, x2)

inst_18365:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x6c7ffffe; valaddr_reg:x3; val_offset:55095*0 + 3*701*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55095*0 + 3*701*FLEN/8, x4, x1, x2)

inst_18366:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x6c7fffff; valaddr_reg:x3; val_offset:55098*0 + 3*702*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55098*0 + 3*702*FLEN/8, x4, x1, x2)

inst_18367:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x7f000001; valaddr_reg:x3; val_offset:55101*0 + 3*703*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55101*0 + 3*703*FLEN/8, x4, x1, x2)

inst_18368:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x7f000003; valaddr_reg:x3; val_offset:55104*0 + 3*704*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55104*0 + 3*704*FLEN/8, x4, x1, x2)

inst_18369:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x7f000007; valaddr_reg:x3; val_offset:55107*0 + 3*705*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55107*0 + 3*705*FLEN/8, x4, x1, x2)

inst_18370:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x7f199999; valaddr_reg:x3; val_offset:55110*0 + 3*706*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55110*0 + 3*706*FLEN/8, x4, x1, x2)

inst_18371:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x7f249249; valaddr_reg:x3; val_offset:55113*0 + 3*707*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55113*0 + 3*707*FLEN/8, x4, x1, x2)

inst_18372:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x7f333333; valaddr_reg:x3; val_offset:55116*0 + 3*708*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55116*0 + 3*708*FLEN/8, x4, x1, x2)

inst_18373:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x7f36db6d; valaddr_reg:x3; val_offset:55119*0 + 3*709*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55119*0 + 3*709*FLEN/8, x4, x1, x2)

inst_18374:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x7f3bbbbb; valaddr_reg:x3; val_offset:55122*0 + 3*710*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55122*0 + 3*710*FLEN/8, x4, x1, x2)

inst_18375:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x7f444444; valaddr_reg:x3; val_offset:55125*0 + 3*711*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55125*0 + 3*711*FLEN/8, x4, x1, x2)

inst_18376:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x7f4ccccc; valaddr_reg:x3; val_offset:55128*0 + 3*712*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55128*0 + 3*712*FLEN/8, x4, x1, x2)

inst_18377:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x7f5b6db6; valaddr_reg:x3; val_offset:55131*0 + 3*713*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55131*0 + 3*713*FLEN/8, x4, x1, x2)

inst_18378:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x7f666666; valaddr_reg:x3; val_offset:55134*0 + 3*714*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55134*0 + 3*714*FLEN/8, x4, x1, x2)

inst_18379:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x7f6db6db; valaddr_reg:x3; val_offset:55137*0 + 3*715*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55137*0 + 3*715*FLEN/8, x4, x1, x2)

inst_18380:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x7f7ffff8; valaddr_reg:x3; val_offset:55140*0 + 3*716*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55140*0 + 3*716*FLEN/8, x4, x1, x2)

inst_18381:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x7f7ffffc; valaddr_reg:x3; val_offset:55143*0 + 3*717*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55143*0 + 3*717*FLEN/8, x4, x1, x2)

inst_18382:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370cea and fs2 == 0 and fe2 == 0x80 and fm2 == 0x3302c0 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb70cea; op2val:0x403302c0;
op3val:0x7f7ffffe; valaddr_reg:x3; val_offset:55146*0 + 3*718*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55146*0 + 3*718*FLEN/8, x4, x1, x2)

inst_18383:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3793aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb793aa; op2val:0x0;
op3val:0x1; valaddr_reg:x3; val_offset:55149*0 + 3*719*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55149*0 + 3*719*FLEN/8, x4, x1, x2)

inst_18384:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3793aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb793aa; op2val:0x0;
op3val:0x3; valaddr_reg:x3; val_offset:55152*0 + 3*720*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55152*0 + 3*720*FLEN/8, x4, x1, x2)

inst_18385:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3793aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb793aa; op2val:0x0;
op3val:0x7; valaddr_reg:x3; val_offset:55155*0 + 3*721*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55155*0 + 3*721*FLEN/8, x4, x1, x2)

inst_18386:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3793aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb793aa; op2val:0x0;
op3val:0x199999; valaddr_reg:x3; val_offset:55158*0 + 3*722*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55158*0 + 3*722*FLEN/8, x4, x1, x2)

inst_18387:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3793aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb793aa; op2val:0x0;
op3val:0x249249; valaddr_reg:x3; val_offset:55161*0 + 3*723*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55161*0 + 3*723*FLEN/8, x4, x1, x2)

inst_18388:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3793aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb793aa; op2val:0x0;
op3val:0x333333; valaddr_reg:x3; val_offset:55164*0 + 3*724*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55164*0 + 3*724*FLEN/8, x4, x1, x2)

inst_18389:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3793aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb793aa; op2val:0x0;
op3val:0x36db6d; valaddr_reg:x3; val_offset:55167*0 + 3*725*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55167*0 + 3*725*FLEN/8, x4, x1, x2)

inst_18390:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3793aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb793aa; op2val:0x0;
op3val:0x3bbbbb; valaddr_reg:x3; val_offset:55170*0 + 3*726*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55170*0 + 3*726*FLEN/8, x4, x1, x2)

inst_18391:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3793aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb793aa; op2val:0x0;
op3val:0x444444; valaddr_reg:x3; val_offset:55173*0 + 3*727*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55173*0 + 3*727*FLEN/8, x4, x1, x2)

inst_18392:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3793aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb793aa; op2val:0x0;
op3val:0x4ccccc; valaddr_reg:x3; val_offset:55176*0 + 3*728*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55176*0 + 3*728*FLEN/8, x4, x1, x2)

inst_18393:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3793aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb793aa; op2val:0x0;
op3val:0x5b6db6; valaddr_reg:x3; val_offset:55179*0 + 3*729*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55179*0 + 3*729*FLEN/8, x4, x1, x2)

inst_18394:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3793aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb793aa; op2val:0x0;
op3val:0x666666; valaddr_reg:x3; val_offset:55182*0 + 3*730*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55182*0 + 3*730*FLEN/8, x4, x1, x2)

inst_18395:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3793aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb793aa; op2val:0x0;
op3val:0x6db6db; valaddr_reg:x3; val_offset:55185*0 + 3*731*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55185*0 + 3*731*FLEN/8, x4, x1, x2)

inst_18396:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3793aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb793aa; op2val:0x0;
op3val:0x7ffff8; valaddr_reg:x3; val_offset:55188*0 + 3*732*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55188*0 + 3*732*FLEN/8, x4, x1, x2)

inst_18397:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3793aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb793aa; op2val:0x0;
op3val:0x7ffffc; valaddr_reg:x3; val_offset:55191*0 + 3*733*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55191*0 + 3*733*FLEN/8, x4, x1, x2)

inst_18398:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3793aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb793aa; op2val:0x0;
op3val:0x7ffffe; valaddr_reg:x3; val_offset:55194*0 + 3*734*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55194*0 + 3*734*FLEN/8, x4, x1, x2)

inst_18399:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3793aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb793aa; op2val:0x0;
op3val:0x2000000; valaddr_reg:x3; val_offset:55197*0 + 3*735*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55197*0 + 3*735*FLEN/8, x4, x1, x2)

inst_18400:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3793aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb793aa; op2val:0x0;
op3val:0x2000001; valaddr_reg:x3; val_offset:55200*0 + 3*736*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55200*0 + 3*736*FLEN/8, x4, x1, x2)

inst_18401:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3793aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb793aa; op2val:0x0;
op3val:0x2000003; valaddr_reg:x3; val_offset:55203*0 + 3*737*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55203*0 + 3*737*FLEN/8, x4, x1, x2)

inst_18402:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3793aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb793aa; op2val:0x0;
op3val:0x2000007; valaddr_reg:x3; val_offset:55206*0 + 3*738*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55206*0 + 3*738*FLEN/8, x4, x1, x2)

inst_18403:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3793aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb793aa; op2val:0x0;
op3val:0x200000f; valaddr_reg:x3; val_offset:55209*0 + 3*739*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55209*0 + 3*739*FLEN/8, x4, x1, x2)

inst_18404:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3793aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb793aa; op2val:0x0;
op3val:0x200001f; valaddr_reg:x3; val_offset:55212*0 + 3*740*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55212*0 + 3*740*FLEN/8, x4, x1, x2)

inst_18405:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3793aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb793aa; op2val:0x0;
op3val:0x200003f; valaddr_reg:x3; val_offset:55215*0 + 3*741*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55215*0 + 3*741*FLEN/8, x4, x1, x2)

inst_18406:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3793aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb793aa; op2val:0x0;
op3val:0x200007f; valaddr_reg:x3; val_offset:55218*0 + 3*742*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55218*0 + 3*742*FLEN/8, x4, x1, x2)

inst_18407:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3793aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb793aa; op2val:0x0;
op3val:0x20000ff; valaddr_reg:x3; val_offset:55221*0 + 3*743*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55221*0 + 3*743*FLEN/8, x4, x1, x2)

inst_18408:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3793aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb793aa; op2val:0x0;
op3val:0x20001ff; valaddr_reg:x3; val_offset:55224*0 + 3*744*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55224*0 + 3*744*FLEN/8, x4, x1, x2)

inst_18409:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3793aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb793aa; op2val:0x0;
op3val:0x20003ff; valaddr_reg:x3; val_offset:55227*0 + 3*745*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55227*0 + 3*745*FLEN/8, x4, x1, x2)

inst_18410:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3793aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb793aa; op2val:0x0;
op3val:0x20007ff; valaddr_reg:x3; val_offset:55230*0 + 3*746*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55230*0 + 3*746*FLEN/8, x4, x1, x2)

inst_18411:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3793aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb793aa; op2val:0x0;
op3val:0x2000fff; valaddr_reg:x3; val_offset:55233*0 + 3*747*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55233*0 + 3*747*FLEN/8, x4, x1, x2)

inst_18412:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3793aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb793aa; op2val:0x0;
op3val:0x2001fff; valaddr_reg:x3; val_offset:55236*0 + 3*748*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55236*0 + 3*748*FLEN/8, x4, x1, x2)

inst_18413:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3793aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb793aa; op2val:0x0;
op3val:0x2003fff; valaddr_reg:x3; val_offset:55239*0 + 3*749*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55239*0 + 3*749*FLEN/8, x4, x1, x2)

inst_18414:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3793aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb793aa; op2val:0x0;
op3val:0x2007fff; valaddr_reg:x3; val_offset:55242*0 + 3*750*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55242*0 + 3*750*FLEN/8, x4, x1, x2)

inst_18415:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3793aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb793aa; op2val:0x0;
op3val:0x200ffff; valaddr_reg:x3; val_offset:55245*0 + 3*751*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55245*0 + 3*751*FLEN/8, x4, x1, x2)

inst_18416:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3793aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb793aa; op2val:0x0;
op3val:0x201ffff; valaddr_reg:x3; val_offset:55248*0 + 3*752*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55248*0 + 3*752*FLEN/8, x4, x1, x2)

inst_18417:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3793aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb793aa; op2val:0x0;
op3val:0x203ffff; valaddr_reg:x3; val_offset:55251*0 + 3*753*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55251*0 + 3*753*FLEN/8, x4, x1, x2)

inst_18418:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3793aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb793aa; op2val:0x0;
op3val:0x207ffff; valaddr_reg:x3; val_offset:55254*0 + 3*754*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55254*0 + 3*754*FLEN/8, x4, x1, x2)

inst_18419:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3793aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb793aa; op2val:0x0;
op3val:0x20fffff; valaddr_reg:x3; val_offset:55257*0 + 3*755*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55257*0 + 3*755*FLEN/8, x4, x1, x2)

inst_18420:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3793aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb793aa; op2val:0x0;
op3val:0x21fffff; valaddr_reg:x3; val_offset:55260*0 + 3*756*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55260*0 + 3*756*FLEN/8, x4, x1, x2)

inst_18421:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3793aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb793aa; op2val:0x0;
op3val:0x23fffff; valaddr_reg:x3; val_offset:55263*0 + 3*757*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55263*0 + 3*757*FLEN/8, x4, x1, x2)

inst_18422:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3793aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb793aa; op2val:0x0;
op3val:0x2400000; valaddr_reg:x3; val_offset:55266*0 + 3*758*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55266*0 + 3*758*FLEN/8, x4, x1, x2)

inst_18423:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3793aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb793aa; op2val:0x0;
op3val:0x2600000; valaddr_reg:x3; val_offset:55269*0 + 3*759*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55269*0 + 3*759*FLEN/8, x4, x1, x2)

inst_18424:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3793aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb793aa; op2val:0x0;
op3val:0x2700000; valaddr_reg:x3; val_offset:55272*0 + 3*760*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55272*0 + 3*760*FLEN/8, x4, x1, x2)

inst_18425:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3793aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb793aa; op2val:0x0;
op3val:0x2780000; valaddr_reg:x3; val_offset:55275*0 + 3*761*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55275*0 + 3*761*FLEN/8, x4, x1, x2)

inst_18426:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3793aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb793aa; op2val:0x0;
op3val:0x27c0000; valaddr_reg:x3; val_offset:55278*0 + 3*762*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55278*0 + 3*762*FLEN/8, x4, x1, x2)

inst_18427:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3793aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb793aa; op2val:0x0;
op3val:0x27e0000; valaddr_reg:x3; val_offset:55281*0 + 3*763*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55281*0 + 3*763*FLEN/8, x4, x1, x2)

inst_18428:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3793aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb793aa; op2val:0x0;
op3val:0x27f0000; valaddr_reg:x3; val_offset:55284*0 + 3*764*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55284*0 + 3*764*FLEN/8, x4, x1, x2)

inst_18429:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3793aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb793aa; op2val:0x0;
op3val:0x27f8000; valaddr_reg:x3; val_offset:55287*0 + 3*765*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55287*0 + 3*765*FLEN/8, x4, x1, x2)

inst_18430:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3793aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb793aa; op2val:0x0;
op3val:0x27fc000; valaddr_reg:x3; val_offset:55290*0 + 3*766*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55290*0 + 3*766*FLEN/8, x4, x1, x2)

inst_18431:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3793aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7eb793aa; op2val:0x0;
op3val:0x27fe000; valaddr_reg:x3; val_offset:55293*0 + 3*767*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 55293*0 + 3*767*FLEN/8, x4, x1, x2)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0x7eb00757,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d0001ff,32,FLEN)
NAN_BOXED(0x7eb00757,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d0003ff,32,FLEN)
NAN_BOXED(0x7eb00757,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d0007ff,32,FLEN)
NAN_BOXED(0x7eb00757,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d000fff,32,FLEN)
NAN_BOXED(0x7eb00757,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d001fff,32,FLEN)
NAN_BOXED(0x7eb00757,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d003fff,32,FLEN)
NAN_BOXED(0x7eb00757,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d007fff,32,FLEN)
NAN_BOXED(0x7eb00757,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d00ffff,32,FLEN)
NAN_BOXED(0x7eb00757,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d01ffff,32,FLEN)
NAN_BOXED(0x7eb00757,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d03ffff,32,FLEN)
NAN_BOXED(0x7eb00757,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d07ffff,32,FLEN)
NAN_BOXED(0x7eb00757,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d0fffff,32,FLEN)
NAN_BOXED(0x7eb00757,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d1fffff,32,FLEN)
NAN_BOXED(0x7eb00757,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d3fffff,32,FLEN)
NAN_BOXED(0x7eb00757,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d400000,32,FLEN)
NAN_BOXED(0x7eb00757,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d600000,32,FLEN)
NAN_BOXED(0x7eb00757,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d700000,32,FLEN)
NAN_BOXED(0x7eb00757,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d780000,32,FLEN)
NAN_BOXED(0x7eb00757,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d7c0000,32,FLEN)
NAN_BOXED(0x7eb00757,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d7e0000,32,FLEN)
NAN_BOXED(0x7eb00757,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d7f0000,32,FLEN)
NAN_BOXED(0x7eb00757,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d7f8000,32,FLEN)
NAN_BOXED(0x7eb00757,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d7fc000,32,FLEN)
NAN_BOXED(0x7eb00757,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d7fe000,32,FLEN)
NAN_BOXED(0x7eb00757,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d7ff000,32,FLEN)
NAN_BOXED(0x7eb00757,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d7ff800,32,FLEN)
NAN_BOXED(0x7eb00757,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d7ffc00,32,FLEN)
NAN_BOXED(0x7eb00757,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d7ffe00,32,FLEN)
NAN_BOXED(0x7eb00757,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d7fff00,32,FLEN)
NAN_BOXED(0x7eb00757,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d7fff80,32,FLEN)
NAN_BOXED(0x7eb00757,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d7fffc0,32,FLEN)
NAN_BOXED(0x7eb00757,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d7fffe0,32,FLEN)
NAN_BOXED(0x7eb00757,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d7ffff0,32,FLEN)
NAN_BOXED(0x7eb00757,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d7ffff8,32,FLEN)
NAN_BOXED(0x7eb00757,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d7ffffc,32,FLEN)
NAN_BOXED(0x7eb00757,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d7ffffe,32,FLEN)
NAN_BOXED(0x7eb00757,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d7fffff,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xbf800001,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xbf800003,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xbf800007,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xbf999999,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xbfa49249,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xbfb33333,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xbfb6db6d,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xbfbbbbbb,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xbfc44444,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xbfcccccc,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xbfdb6db6,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xbfe66666,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xbfedb6db,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xbffffff8,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xbffffffc,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xbffffffe,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xc9800000,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xc9800001,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xc9800003,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xc9800007,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xc980000f,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xc980001f,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xc980003f,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xc980007f,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xc98000ff,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xc98001ff,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xc98003ff,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xc98007ff,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xc9800fff,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xc9801fff,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xc9803fff,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xc9807fff,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xc980ffff,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xc981ffff,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xc983ffff,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xc987ffff,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xc98fffff,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xc99fffff,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xc9bfffff,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xc9c00000,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xc9e00000,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xc9f00000,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xc9f80000,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xc9fc0000,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xc9fe0000,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xc9ff0000,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xc9ff8000,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xc9ffc000,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xc9ffe000,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xc9fff000,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xc9fff800,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xc9fffc00,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xc9fffe00,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xc9ffff00,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xc9ffff80,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xc9ffffc0,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xc9ffffe0,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xc9fffff0,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xc9fffff8,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xc9fffffc,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xc9fffffe,32,FLEN)
NAN_BOXED(0x7eb0208a,32,FLEN)
NAN_BOXED(0x805d0612,32,FLEN)
NAN_BOXED(0xc9ffffff,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xe8000000,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xe8000001,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xe8000003,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xe8000007,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xe800000f,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xe800001f,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xe800003f,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xe800007f,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xe80000ff,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xe80001ff,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xe80003ff,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xe80007ff,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xe8000fff,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xe8001fff,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xe8003fff,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xe8007fff,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xe800ffff,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xe801ffff,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xe803ffff,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xe807ffff,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xe80fffff,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xe81fffff,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xe83fffff,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xe8400000,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xe8600000,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xe8700000,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xe8780000,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xe87c0000,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xe87e0000,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xe87f0000,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xe87f8000,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xe87fc000,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xe87fe000,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xe87ff000,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xe87ff800,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xe87ffc00,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xe87ffe00,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xe87fff00,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xe87fff80,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xe87fffc0,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xe87fffe0,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xe87ffff0,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xe87ffff8,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xe87ffffc,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xe87ffffe,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xe87fffff,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xff000001,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xff000003,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xff000007,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xff199999,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xff249249,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xff333333,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xff36db6d,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xff3bbbbb,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xff444444,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xff4ccccc,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xff5b6db6,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xff666666,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xff6db6db,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xff7ffff8,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xff7ffffc,32,FLEN)
NAN_BOXED(0x7eb1933e,32,FLEN)
NAN_BOXED(0xc03887c1,32,FLEN)
NAN_BOXED(0xff7ffffe,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x3f800001,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x3f800003,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x3f800007,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x3f999999,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x3fa49249,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x3fb33333,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x3fb6db6d,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x3fbbbbbb,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x3fc44444,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x3fcccccc,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x3fdb6db6,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x3fe66666,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x3fedb6db,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x3ffffff8,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x3ffffffc,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x3ffffffe,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x40000000,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x40000001,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x40000003,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x40000007,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x4000000f,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x4000001f,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x4000003f,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x4000007f,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x400000ff,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x400001ff,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x400003ff,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x400007ff,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x40000fff,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x40001fff,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x40003fff,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x40007fff,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x4000ffff,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x4001ffff,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x4003ffff,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x4007ffff,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x400fffff,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x401fffff,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x403fffff,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x40400000,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x40600000,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x40700000,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x40780000,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x407c0000,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x407e0000,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x407f0000,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x407f8000,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x407fc000,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x407fe000,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x407ff000,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x407ff800,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x407ffc00,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x407ffe00,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x407fff00,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x407fff80,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x407fffc0,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x407fffe0,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x407ffff0,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x407ffff8,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x407ffffc,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x407ffffe,32,FLEN)
NAN_BOXED(0x7eb360dd,32,FLEN)
NAN_BOXED(0x5b5670,32,FLEN)
NAN_BOXED(0x407fffff,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800001,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800003,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800007,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x999999,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa49249,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb33333,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb6db6d,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbbbbbb,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xc44444,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xcccccc,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xdb6db6,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe66666,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xedb6db,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffff8,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffffc,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffffe,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xc800000,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xc800001,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xc800003,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xc800007,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xc80000f,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xc80001f,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xc80003f,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xc80007f,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xc8000ff,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xc8001ff,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xc8003ff,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xc8007ff,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xc800fff,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xc801fff,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xc803fff,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xc807fff,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xc80ffff,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xc81ffff,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xc83ffff,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xc87ffff,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xc8fffff,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xc9fffff,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xcbfffff,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xcc00000,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xce00000,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xcf00000,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xcf80000,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xcfc0000,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xcfe0000,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xcff0000,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xcff8000,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xcffc000,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xcffe000,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xcfff000,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xcfff800,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xcfffc00,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xcfffe00,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xcffff00,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xcffff80,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xcffffc0,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xcffffe0,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xcfffff0,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xcfffff8,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xcfffffc,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xcfffffe,32,FLEN)
NAN_BOXED(0x7eb3667c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xcffffff,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x3f800001,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x3f800003,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x3f800007,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x3f999999,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x3fa49249,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x3fb33333,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x3fb6db6d,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x3fbbbbbb,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x3fc44444,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x3fcccccc,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x3fdb6db6,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x3fe66666,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x3fedb6db,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x3ffffff8,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x3ffffffc,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x3ffffffe,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x43000000,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x43000001,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x43000003,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x43000007,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x4300000f,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x4300001f,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x4300003f,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x4300007f,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x430000ff,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x430001ff,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x430003ff,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x430007ff,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x43000fff,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x43001fff,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x43003fff,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x43007fff,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x4300ffff,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x4301ffff,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x4303ffff,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x4307ffff,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x430fffff,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x431fffff,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x433fffff,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x43400000,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x43600000,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x43700000,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x43780000,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x437c0000,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x437e0000,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x437f0000,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x437f8000,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x437fc000,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x437fe000,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x437ff000,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x437ff800,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x437ffc00,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x437ffe00,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x437fff00,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x437fff80,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x437fffc0,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x437fffe0,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x437ffff0,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x437ffff8,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x437ffffc,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x437ffffe,32,FLEN)
NAN_BOXED(0x7eb49020,32,FLEN)
NAN_BOXED(0x5abd08,32,FLEN)
NAN_BOXED(0x437fffff,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xe0800000,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xe0800001,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xe0800003,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xe0800007,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xe080000f,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xe080001f,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xe080003f,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xe080007f,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xe08000ff,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xe08001ff,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xe08003ff,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xe08007ff,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xe0800fff,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xe0801fff,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xe0803fff,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xe0807fff,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xe080ffff,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xe081ffff,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xe083ffff,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xe087ffff,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xe08fffff,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xe09fffff,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xe0bfffff,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xe0c00000,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xe0e00000,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xe0f00000,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xe0f80000,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xe0fc0000,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xe0fe0000,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xe0ff0000,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xe0ff8000,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xe0ffc000,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xe0ffe000,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xe0fff000,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xe0fff800,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xe0fffc00,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xe0fffe00,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xe0ffff00,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xe0ffff80,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xe0ffffc0,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xe0ffffe0,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xe0fffff0,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xe0fffff8,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xe0fffffc,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xe0fffffe,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xe0ffffff,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xff000001,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xff000003,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xff000007,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xff199999,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xff249249,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xff333333,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xff36db6d,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xff3bbbbb,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xff444444,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xff4ccccc,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xff5b6db6,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xff666666,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xff6db6db,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xff7ffff8,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xff7ffffc,32,FLEN)
NAN_BOXED(0x7eb4d220,32,FLEN)
NAN_BOXED(0xc03537d3,32,FLEN)
NAN_BOXED(0xff7ffffe,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800001,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800003,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800007,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x999999,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa49249,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb33333,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb6db6d,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbbbbbb,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xc44444,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xcccccc,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xdb6db6,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe66666,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xedb6db,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffff8,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffffc,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffffe,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6000000,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6000001,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6000003,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6000007,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x600000f,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x600001f,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x600003f,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x600007f,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x60000ff,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x60001ff,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x60003ff,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x60007ff,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6000fff,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6001fff,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6003fff,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6007fff,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x600ffff,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x601ffff,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x603ffff,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x607ffff,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x60fffff,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x61fffff,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x63fffff,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6400000,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6600000,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6700000,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6780000,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x67c0000,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x67e0000,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x67f0000,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x67f8000,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x67fc000,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x67fe000,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x67ff000,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x67ff800,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x67ffc00,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x67ffe00,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x67fff00,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x67fff80,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x67fffc0,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x67fffe0,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x67ffff0,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x67ffff8,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x67ffffc,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x67ffffe,32,FLEN)
NAN_BOXED(0x7eb4d24a,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x67fffff,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xef000000,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xef000001,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xef000003,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xef000007,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xef00000f,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xef00001f,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xef00003f,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xef00007f,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xef0000ff,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xef0001ff,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xef0003ff,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xef0007ff,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xef000fff,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xef001fff,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xef003fff,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xef007fff,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xef00ffff,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xef01ffff,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xef03ffff,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xef07ffff,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xef0fffff,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xef1fffff,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xef3fffff,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xef400000,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xef600000,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xef700000,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xef780000,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xef7c0000,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xef7e0000,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xef7f0000,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xef7f8000,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xef7fc000,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xef7fe000,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xef7ff000,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xef7ff800,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xef7ffc00,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xef7ffe00,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xef7fff00,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xef7fff80,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xef7fffc0,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xef7fffe0,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xef7ffff0,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xef7ffff8,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xef7ffffc,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xef7ffffe,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xef7fffff,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xff000001,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xff000003,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xff000007,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xff199999,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xff249249,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xff333333,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xff36db6d,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xff3bbbbb,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xff444444,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xff4ccccc,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xff5b6db6,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xff666666,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xff6db6db,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xff7ffff8,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xff7ffffc,32,FLEN)
NAN_BOXED(0x7eb507ef,32,FLEN)
NAN_BOXED(0xc03501f5,32,FLEN)
NAN_BOXED(0xff7ffffe,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x199999,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x249249,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x333333,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x36db6d,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3bbbbb,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x444444,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4ccccc,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5b6db6,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x666666,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6db6db,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffff8,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffc,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffe,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7800000,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7800001,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7800003,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7800007,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x780000f,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x780001f,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x780003f,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x780007f,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x78000ff,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x78001ff,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x78003ff,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x78007ff,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7800fff,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7801fff,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7803fff,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7807fff,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x780ffff,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x781ffff,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x783ffff,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x787ffff,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x78fffff,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x79fffff,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7bfffff,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7c00000,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7e00000,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7f00000,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7f80000,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fc0000,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fe0000,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ff0000,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ff8000,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffc000,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffe000,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fff000,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fff800,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fffc00,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fffe00,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffff00,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffff80,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffc0,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffe0,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fffff0,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fffff8,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fffffc,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fffffe,32,FLEN)
NAN_BOXED(0x7eb6048d,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffff,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbc800000,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbc800001,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbc800003,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbc800007,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbc80000f,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbc80001f,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbc80003f,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbc80007f,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbc8000ff,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbc8001ff,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbc8003ff,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbc8007ff,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbc800fff,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbc801fff,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbc803fff,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbc807fff,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbc80ffff,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbc81ffff,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbc83ffff,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbc87ffff,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbc8fffff,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbc9fffff,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbcbfffff,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbcc00000,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbce00000,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbcf00000,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbcf80000,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbcfc0000,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbcfe0000,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbcff0000,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbcff8000,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbcffc000,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbcffe000,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbcfff000,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbcfff800,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbcfffc00,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbcfffe00,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbcffff00,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbcffff80,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbcffffc0,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbcffffe0,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbcfffff0,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbcfffff8,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbcfffffc,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbcfffffe,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbcffffff,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbf800001,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbf800003,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbf800007,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbf999999,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbfa49249,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbfb33333,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbfb6db6d,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbfbbbbbb,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbfc44444,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbfcccccc,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbfdb6db6,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbfe66666,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbfedb6db,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbffffff8,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbffffffc,32,FLEN)
NAN_BOXED(0x7eb6a1eb,32,FLEN)
NAN_BOXED(0x8059b5d0,32,FLEN)
NAN_BOXED(0xbffffffe,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x6c000000,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x6c000001,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x6c000003,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x6c000007,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x6c00000f,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x6c00001f,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x6c00003f,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x6c00007f,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x6c0000ff,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x6c0001ff,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x6c0003ff,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x6c0007ff,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x6c000fff,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x6c001fff,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x6c003fff,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x6c007fff,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x6c00ffff,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x6c01ffff,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x6c03ffff,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x6c07ffff,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x6c0fffff,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x6c1fffff,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x6c3fffff,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x6c400000,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x6c600000,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x6c700000,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x6c780000,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x6c7c0000,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x6c7e0000,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x6c7f0000,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x6c7f8000,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x6c7fc000,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x6c7fe000,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x6c7ff000,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x6c7ff800,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x6c7ffc00,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x6c7ffe00,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x6c7fff00,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x6c7fff80,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x6c7fffc0,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x6c7fffe0,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x6c7ffff0,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x6c7ffff8,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x6c7ffffc,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x6c7ffffe,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x6c7fffff,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x7f000001,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x7f000003,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x7f000007,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x7f199999,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x7f249249,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x7f333333,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x7f36db6d,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x7f3bbbbb,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x7f444444,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x7f4ccccc,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x7f5b6db6,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x7f666666,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x7f6db6db,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x7f7ffff8,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x7f7ffffc,32,FLEN)
NAN_BOXED(0x7eb70cea,32,FLEN)
NAN_BOXED(0x403302c0,32,FLEN)
NAN_BOXED(0x7f7ffffe,32,FLEN)
NAN_BOXED(0x7eb793aa,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1,32,FLEN)
NAN_BOXED(0x7eb793aa,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3,32,FLEN)
NAN_BOXED(0x7eb793aa,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7,32,FLEN)
NAN_BOXED(0x7eb793aa,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x199999,32,FLEN)
NAN_BOXED(0x7eb793aa,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x249249,32,FLEN)
NAN_BOXED(0x7eb793aa,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x333333,32,FLEN)
NAN_BOXED(0x7eb793aa,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x36db6d,32,FLEN)
NAN_BOXED(0x7eb793aa,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3bbbbb,32,FLEN)
NAN_BOXED(0x7eb793aa,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x444444,32,FLEN)
NAN_BOXED(0x7eb793aa,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4ccccc,32,FLEN)
NAN_BOXED(0x7eb793aa,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5b6db6,32,FLEN)
NAN_BOXED(0x7eb793aa,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x666666,32,FLEN)
NAN_BOXED(0x7eb793aa,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6db6db,32,FLEN)
NAN_BOXED(0x7eb793aa,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffff8,32,FLEN)
NAN_BOXED(0x7eb793aa,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffc,32,FLEN)
NAN_BOXED(0x7eb793aa,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffe,32,FLEN)
NAN_BOXED(0x7eb793aa,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2000000,32,FLEN)
NAN_BOXED(0x7eb793aa,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2000001,32,FLEN)
NAN_BOXED(0x7eb793aa,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2000003,32,FLEN)
NAN_BOXED(0x7eb793aa,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2000007,32,FLEN)
NAN_BOXED(0x7eb793aa,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x200000f,32,FLEN)
NAN_BOXED(0x7eb793aa,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x200001f,32,FLEN)
NAN_BOXED(0x7eb793aa,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x200003f,32,FLEN)
NAN_BOXED(0x7eb793aa,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x200007f,32,FLEN)
NAN_BOXED(0x7eb793aa,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x20000ff,32,FLEN)
NAN_BOXED(0x7eb793aa,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x20001ff,32,FLEN)
NAN_BOXED(0x7eb793aa,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x20003ff,32,FLEN)
NAN_BOXED(0x7eb793aa,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x20007ff,32,FLEN)
NAN_BOXED(0x7eb793aa,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2000fff,32,FLEN)
NAN_BOXED(0x7eb793aa,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2001fff,32,FLEN)
NAN_BOXED(0x7eb793aa,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2003fff,32,FLEN)
NAN_BOXED(0x7eb793aa,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2007fff,32,FLEN)
NAN_BOXED(0x7eb793aa,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x200ffff,32,FLEN)
NAN_BOXED(0x7eb793aa,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x201ffff,32,FLEN)
NAN_BOXED(0x7eb793aa,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x203ffff,32,FLEN)
NAN_BOXED(0x7eb793aa,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x207ffff,32,FLEN)
NAN_BOXED(0x7eb793aa,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x20fffff,32,FLEN)
NAN_BOXED(0x7eb793aa,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x21fffff,32,FLEN)
NAN_BOXED(0x7eb793aa,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x23fffff,32,FLEN)
NAN_BOXED(0x7eb793aa,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2400000,32,FLEN)
NAN_BOXED(0x7eb793aa,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2600000,32,FLEN)
NAN_BOXED(0x7eb793aa,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2700000,32,FLEN)
NAN_BOXED(0x7eb793aa,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2780000,32,FLEN)
NAN_BOXED(0x7eb793aa,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x27c0000,32,FLEN)
NAN_BOXED(0x7eb793aa,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x27e0000,32,FLEN)
NAN_BOXED(0x7eb793aa,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x27f0000,32,FLEN)
NAN_BOXED(0x7eb793aa,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x27f8000,32,FLEN)
NAN_BOXED(0x7eb793aa,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x27fc000,32,FLEN)
NAN_BOXED(0x7eb793aa,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x27fe000,32,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;


signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_2:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_3:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_4:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_5:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_6:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine

tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
    .fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;

#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif

sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
