
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.11.0
// timestamp : Mon Feb  5 07:30:48 2024 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fnmadd.s.cgf \
 \
//                  -- xlen 64  \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fnmadd.s instruction of the RISC-V RV64_Zfinx,RV64_Zdinx extension for the fnmadd_b15 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV64I_Zfinx,RV64I_Zdinx")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*);def TEST_CASE_1=True;",fnmadd_b15)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_31447:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x29477e and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4192d7 and fs3 == 0 and fe3 == 0xd6 and fm3 == 0x0000ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f29477e; op2val:0x3fc192d7;
op3val:0x6b0000ff; valaddr_reg:x12; val_offset:94278*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94278*FLEN/8, x13, x9, x10)

inst_31448:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x29477e and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4192d7 and fs3 == 0 and fe3 == 0xd6 and fm3 == 0x7fff00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f29477e; op2val:0x3fc192d7;
op3val:0x6b7fff00; valaddr_reg:x12; val_offset:94281*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94281*FLEN/8, x13, x9, x10)

inst_31449:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x29477e and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4192d7 and fs3 == 0 and fe3 == 0xd6 and fm3 == 0x00007f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f29477e; op2val:0x3fc192d7;
op3val:0x6b00007f; valaddr_reg:x12; val_offset:94284*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94284*FLEN/8, x13, x9, x10)

inst_31450:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x29477e and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4192d7 and fs3 == 0 and fe3 == 0xd6 and fm3 == 0x7fff80 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f29477e; op2val:0x3fc192d7;
op3val:0x6b7fff80; valaddr_reg:x12; val_offset:94287*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94287*FLEN/8, x13, x9, x10)

inst_31451:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x29477e and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4192d7 and fs3 == 0 and fe3 == 0xd6 and fm3 == 0x00003f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f29477e; op2val:0x3fc192d7;
op3val:0x6b00003f; valaddr_reg:x12; val_offset:94290*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94290*FLEN/8, x13, x9, x10)

inst_31452:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x29477e and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4192d7 and fs3 == 0 and fe3 == 0xd6 and fm3 == 0x7fffc0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f29477e; op2val:0x3fc192d7;
op3val:0x6b7fffc0; valaddr_reg:x12; val_offset:94293*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94293*FLEN/8, x13, x9, x10)

inst_31453:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x29477e and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4192d7 and fs3 == 0 and fe3 == 0xd6 and fm3 == 0x00001f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f29477e; op2val:0x3fc192d7;
op3val:0x6b00001f; valaddr_reg:x12; val_offset:94296*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94296*FLEN/8, x13, x9, x10)

inst_31454:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x29477e and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4192d7 and fs3 == 0 and fe3 == 0xd6 and fm3 == 0x7fffe0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f29477e; op2val:0x3fc192d7;
op3val:0x6b7fffe0; valaddr_reg:x12; val_offset:94299*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94299*FLEN/8, x13, x9, x10)

inst_31455:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x29477e and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4192d7 and fs3 == 0 and fe3 == 0xd6 and fm3 == 0x00000f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f29477e; op2val:0x3fc192d7;
op3val:0x6b00000f; valaddr_reg:x12; val_offset:94302*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94302*FLEN/8, x13, x9, x10)

inst_31456:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x29477e and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4192d7 and fs3 == 0 and fe3 == 0xd6 and fm3 == 0x7ffff0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f29477e; op2val:0x3fc192d7;
op3val:0x6b7ffff0; valaddr_reg:x12; val_offset:94305*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94305*FLEN/8, x13, x9, x10)

inst_31457:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x29477e and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4192d7 and fs3 == 0 and fe3 == 0xd6 and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f29477e; op2val:0x3fc192d7;
op3val:0x6b000007; valaddr_reg:x12; val_offset:94308*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94308*FLEN/8, x13, x9, x10)

inst_31458:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x29477e and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4192d7 and fs3 == 0 and fe3 == 0xd6 and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f29477e; op2val:0x3fc192d7;
op3val:0x6b7ffff8; valaddr_reg:x12; val_offset:94311*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94311*FLEN/8, x13, x9, x10)

inst_31459:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x29477e and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4192d7 and fs3 == 0 and fe3 == 0xd6 and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f29477e; op2val:0x3fc192d7;
op3val:0x6b000003; valaddr_reg:x12; val_offset:94314*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94314*FLEN/8, x13, x9, x10)

inst_31460:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x29477e and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4192d7 and fs3 == 0 and fe3 == 0xd6 and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f29477e; op2val:0x3fc192d7;
op3val:0x6b7ffffc; valaddr_reg:x12; val_offset:94317*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94317*FLEN/8, x13, x9, x10)

inst_31461:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x29477e and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4192d7 and fs3 == 0 and fe3 == 0xd6 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f29477e; op2val:0x3fc192d7;
op3val:0x6b000001; valaddr_reg:x12; val_offset:94320*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94320*FLEN/8, x13, x9, x10)

inst_31462:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x29477e and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4192d7 and fs3 == 0 and fe3 == 0xd6 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f29477e; op2val:0x3fc192d7;
op3val:0x6b7ffffe; valaddr_reg:x12; val_offset:94323*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94323*FLEN/8, x13, x9, x10)

inst_31463:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x29477e and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4192d7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f29477e; op2val:0x3fc192d7;
op3val:0x7f7ffff8; valaddr_reg:x12; val_offset:94326*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94326*FLEN/8, x13, x9, x10)

inst_31464:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x29477e and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4192d7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f29477e; op2val:0x3fc192d7;
op3val:0x7f000007; valaddr_reg:x12; val_offset:94329*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94329*FLEN/8, x13, x9, x10)

inst_31465:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x29477e and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4192d7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f29477e; op2val:0x3fc192d7;
op3val:0x7f7ffffc; valaddr_reg:x12; val_offset:94332*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94332*FLEN/8, x13, x9, x10)

inst_31466:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x29477e and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4192d7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f29477e; op2val:0x3fc192d7;
op3val:0x7f000003; valaddr_reg:x12; val_offset:94335*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94335*FLEN/8, x13, x9, x10)

inst_31467:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x29477e and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4192d7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f29477e; op2val:0x3fc192d7;
op3val:0x7f7ffffe; valaddr_reg:x12; val_offset:94338*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94338*FLEN/8, x13, x9, x10)

inst_31468:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x29477e and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4192d7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f29477e; op2val:0x3fc192d7;
op3val:0x7f000001; valaddr_reg:x12; val_offset:94341*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94341*FLEN/8, x13, x9, x10)

inst_31469:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x29477e and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4192d7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x36db6d and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f29477e; op2val:0x3fc192d7;
op3val:0x7f36db6d; valaddr_reg:x12; val_offset:94344*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94344*FLEN/8, x13, x9, x10)

inst_31470:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x29477e and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4192d7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x6db6db and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f29477e; op2val:0x3fc192d7;
op3val:0x7f6db6db; valaddr_reg:x12; val_offset:94347*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94347*FLEN/8, x13, x9, x10)

inst_31471:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x29477e and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4192d7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x199999 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f29477e; op2val:0x3fc192d7;
op3val:0x7f199999; valaddr_reg:x12; val_offset:94350*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94350*FLEN/8, x13, x9, x10)

inst_31472:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x29477e and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4192d7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x666666 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f29477e; op2val:0x3fc192d7;
op3val:0x7f666666; valaddr_reg:x12; val_offset:94353*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94353*FLEN/8, x13, x9, x10)

inst_31473:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x29477e and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4192d7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3bbbbb and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f29477e; op2val:0x3fc192d7;
op3val:0x7f3bbbbb; valaddr_reg:x12; val_offset:94356*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94356*FLEN/8, x13, x9, x10)

inst_31474:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x29477e and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4192d7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x444444 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f29477e; op2val:0x3fc192d7;
op3val:0x7f444444; valaddr_reg:x12; val_offset:94359*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94359*FLEN/8, x13, x9, x10)

inst_31475:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x29477e and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4192d7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x249249 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f29477e; op2val:0x3fc192d7;
op3val:0x7f249249; valaddr_reg:x12; val_offset:94362*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94362*FLEN/8, x13, x9, x10)

inst_31476:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x29477e and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4192d7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x5b6db6 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f29477e; op2val:0x3fc192d7;
op3val:0x7f5b6db6; valaddr_reg:x12; val_offset:94365*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94365*FLEN/8, x13, x9, x10)

inst_31477:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x29477e and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4192d7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x333333 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f29477e; op2val:0x3fc192d7;
op3val:0x7f333333; valaddr_reg:x12; val_offset:94368*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94368*FLEN/8, x13, x9, x10)

inst_31478:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x29477e and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4192d7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x4ccccc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f29477e; op2val:0x3fc192d7;
op3val:0x7f4ccccc; valaddr_reg:x12; val_offset:94371*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94371*FLEN/8, x13, x9, x10)

inst_31479:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xd7 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x6bffffff; valaddr_reg:x12; val_offset:94374*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94374*FLEN/8, x13, x9, x10)

inst_31480:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xd7 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x6b800000; valaddr_reg:x12; val_offset:94377*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94377*FLEN/8, x13, x9, x10)

inst_31481:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xd7 and fm3 == 0x3fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x6bbfffff; valaddr_reg:x12; val_offset:94380*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94380*FLEN/8, x13, x9, x10)

inst_31482:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xd7 and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x6bc00000; valaddr_reg:x12; val_offset:94383*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94383*FLEN/8, x13, x9, x10)

inst_31483:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xd7 and fm3 == 0x1fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x6b9fffff; valaddr_reg:x12; val_offset:94386*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94386*FLEN/8, x13, x9, x10)

inst_31484:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xd7 and fm3 == 0x600000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x6be00000; valaddr_reg:x12; val_offset:94389*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94389*FLEN/8, x13, x9, x10)

inst_31485:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xd7 and fm3 == 0x0fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x6b8fffff; valaddr_reg:x12; val_offset:94392*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94392*FLEN/8, x13, x9, x10)

inst_31486:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xd7 and fm3 == 0x700000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x6bf00000; valaddr_reg:x12; val_offset:94395*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94395*FLEN/8, x13, x9, x10)

inst_31487:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xd7 and fm3 == 0x07ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x6b87ffff; valaddr_reg:x12; val_offset:94398*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94398*FLEN/8, x13, x9, x10)

inst_31488:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xd7 and fm3 == 0x780000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x6bf80000; valaddr_reg:x12; val_offset:94401*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94401*FLEN/8, x13, x9, x10)

inst_31489:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xd7 and fm3 == 0x03ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x6b83ffff; valaddr_reg:x12; val_offset:94404*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94404*FLEN/8, x13, x9, x10)

inst_31490:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xd7 and fm3 == 0x7c0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x6bfc0000; valaddr_reg:x12; val_offset:94407*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94407*FLEN/8, x13, x9, x10)

inst_31491:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xd7 and fm3 == 0x01ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x6b81ffff; valaddr_reg:x12; val_offset:94410*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94410*FLEN/8, x13, x9, x10)

inst_31492:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xd7 and fm3 == 0x7e0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x6bfe0000; valaddr_reg:x12; val_offset:94413*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94413*FLEN/8, x13, x9, x10)

inst_31493:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xd7 and fm3 == 0x00ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x6b80ffff; valaddr_reg:x12; val_offset:94416*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94416*FLEN/8, x13, x9, x10)

inst_31494:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xd7 and fm3 == 0x7f0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x6bff0000; valaddr_reg:x12; val_offset:94419*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94419*FLEN/8, x13, x9, x10)

inst_31495:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xd7 and fm3 == 0x007fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x6b807fff; valaddr_reg:x12; val_offset:94422*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94422*FLEN/8, x13, x9, x10)

inst_31496:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xd7 and fm3 == 0x7f8000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x6bff8000; valaddr_reg:x12; val_offset:94425*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94425*FLEN/8, x13, x9, x10)

inst_31497:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xd7 and fm3 == 0x003fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x6b803fff; valaddr_reg:x12; val_offset:94428*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94428*FLEN/8, x13, x9, x10)

inst_31498:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xd7 and fm3 == 0x7fc000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x6bffc000; valaddr_reg:x12; val_offset:94431*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94431*FLEN/8, x13, x9, x10)

inst_31499:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xd7 and fm3 == 0x001fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x6b801fff; valaddr_reg:x12; val_offset:94434*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94434*FLEN/8, x13, x9, x10)

inst_31500:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xd7 and fm3 == 0x7fe000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x6bffe000; valaddr_reg:x12; val_offset:94437*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94437*FLEN/8, x13, x9, x10)

inst_31501:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xd7 and fm3 == 0x000fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x6b800fff; valaddr_reg:x12; val_offset:94440*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94440*FLEN/8, x13, x9, x10)

inst_31502:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xd7 and fm3 == 0x7ff000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x6bfff000; valaddr_reg:x12; val_offset:94443*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94443*FLEN/8, x13, x9, x10)

inst_31503:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xd7 and fm3 == 0x0007ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x6b8007ff; valaddr_reg:x12; val_offset:94446*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94446*FLEN/8, x13, x9, x10)

inst_31504:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xd7 and fm3 == 0x7ff800 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x6bfff800; valaddr_reg:x12; val_offset:94449*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94449*FLEN/8, x13, x9, x10)

inst_31505:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xd7 and fm3 == 0x0003ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x6b8003ff; valaddr_reg:x12; val_offset:94452*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94452*FLEN/8, x13, x9, x10)

inst_31506:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xd7 and fm3 == 0x7ffc00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x6bfffc00; valaddr_reg:x12; val_offset:94455*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94455*FLEN/8, x13, x9, x10)

inst_31507:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xd7 and fm3 == 0x0001ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x6b8001ff; valaddr_reg:x12; val_offset:94458*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94458*FLEN/8, x13, x9, x10)

inst_31508:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xd7 and fm3 == 0x7ffe00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x6bfffe00; valaddr_reg:x12; val_offset:94461*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94461*FLEN/8, x13, x9, x10)

inst_31509:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xd7 and fm3 == 0x0000ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x6b8000ff; valaddr_reg:x12; val_offset:94464*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94464*FLEN/8, x13, x9, x10)

inst_31510:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xd7 and fm3 == 0x7fff00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x6bffff00; valaddr_reg:x12; val_offset:94467*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94467*FLEN/8, x13, x9, x10)

inst_31511:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xd7 and fm3 == 0x00007f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x6b80007f; valaddr_reg:x12; val_offset:94470*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94470*FLEN/8, x13, x9, x10)

RVTEST_SIGBASE(x9,signature_x9_246)
inst_31512:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xd7 and fm3 == 0x7fff80 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x6bffff80; valaddr_reg:x12; val_offset:94473*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94473*FLEN/8, x13, x9, x10)

inst_31513:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xd7 and fm3 == 0x00003f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x6b80003f; valaddr_reg:x12; val_offset:94476*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94476*FLEN/8, x13, x9, x10)

inst_31514:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xd7 and fm3 == 0x7fffc0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x6bffffc0; valaddr_reg:x12; val_offset:94479*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94479*FLEN/8, x13, x9, x10)

inst_31515:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xd7 and fm3 == 0x00001f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x6b80001f; valaddr_reg:x12; val_offset:94482*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94482*FLEN/8, x13, x9, x10)

inst_31516:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xd7 and fm3 == 0x7fffe0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x6bffffe0; valaddr_reg:x12; val_offset:94485*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94485*FLEN/8, x13, x9, x10)

inst_31517:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xd7 and fm3 == 0x00000f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x6b80000f; valaddr_reg:x12; val_offset:94488*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94488*FLEN/8, x13, x9, x10)

inst_31518:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xd7 and fm3 == 0x7ffff0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x6bfffff0; valaddr_reg:x12; val_offset:94491*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94491*FLEN/8, x13, x9, x10)

inst_31519:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xd7 and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x6b800007; valaddr_reg:x12; val_offset:94494*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94494*FLEN/8, x13, x9, x10)

inst_31520:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xd7 and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x6bfffff8; valaddr_reg:x12; val_offset:94497*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94497*FLEN/8, x13, x9, x10)

inst_31521:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xd7 and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x6b800003; valaddr_reg:x12; val_offset:94500*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94500*FLEN/8, x13, x9, x10)

inst_31522:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xd7 and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x6bfffffc; valaddr_reg:x12; val_offset:94503*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94503*FLEN/8, x13, x9, x10)

inst_31523:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xd7 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x6b800001; valaddr_reg:x12; val_offset:94506*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94506*FLEN/8, x13, x9, x10)

inst_31524:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xd7 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x6bfffffe; valaddr_reg:x12; val_offset:94509*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94509*FLEN/8, x13, x9, x10)

inst_31525:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x7f7ffff8; valaddr_reg:x12; val_offset:94512*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94512*FLEN/8, x13, x9, x10)

inst_31526:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x7f000007; valaddr_reg:x12; val_offset:94515*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94515*FLEN/8, x13, x9, x10)

inst_31527:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x7f7ffffc; valaddr_reg:x12; val_offset:94518*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94518*FLEN/8, x13, x9, x10)

inst_31528:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x7f000003; valaddr_reg:x12; val_offset:94521*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94521*FLEN/8, x13, x9, x10)

inst_31529:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x7f7ffffe; valaddr_reg:x12; val_offset:94524*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94524*FLEN/8, x13, x9, x10)

inst_31530:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x7f000001; valaddr_reg:x12; val_offset:94527*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94527*FLEN/8, x13, x9, x10)

inst_31531:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x36db6d and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x7f36db6d; valaddr_reg:x12; val_offset:94530*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94530*FLEN/8, x13, x9, x10)

inst_31532:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x6db6db and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x7f6db6db; valaddr_reg:x12; val_offset:94533*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94533*FLEN/8, x13, x9, x10)

inst_31533:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x199999 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x7f199999; valaddr_reg:x12; val_offset:94536*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94536*FLEN/8, x13, x9, x10)

inst_31534:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x666666 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x7f666666; valaddr_reg:x12; val_offset:94539*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94539*FLEN/8, x13, x9, x10)

inst_31535:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3bbbbb and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x7f3bbbbb; valaddr_reg:x12; val_offset:94542*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94542*FLEN/8, x13, x9, x10)

inst_31536:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x444444 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x7f444444; valaddr_reg:x12; val_offset:94545*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94545*FLEN/8, x13, x9, x10)

inst_31537:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x249249 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x7f249249; valaddr_reg:x12; val_offset:94548*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94548*FLEN/8, x13, x9, x10)

inst_31538:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x5b6db6 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x7f5b6db6; valaddr_reg:x12; val_offset:94551*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94551*FLEN/8, x13, x9, x10)

inst_31539:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x333333 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x7f333333; valaddr_reg:x12; val_offset:94554*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94554*FLEN/8, x13, x9, x10)

inst_31540:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x1f3fb6 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4dc416 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x4ccccc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f1f3fb6; op2val:0x3fcdc416;
op3val:0x7f4ccccc; valaddr_reg:x12; val_offset:94557*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94557*FLEN/8, x13, x9, x10)

inst_31541:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x6c7fffff; valaddr_reg:x12; val_offset:94560*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94560*FLEN/8, x13, x9, x10)

inst_31542:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x6c000000; valaddr_reg:x12; val_offset:94563*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94563*FLEN/8, x13, x9, x10)

inst_31543:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x3fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x6c3fffff; valaddr_reg:x12; val_offset:94566*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94566*FLEN/8, x13, x9, x10)

inst_31544:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x6c400000; valaddr_reg:x12; val_offset:94569*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94569*FLEN/8, x13, x9, x10)

inst_31545:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x1fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x6c1fffff; valaddr_reg:x12; val_offset:94572*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94572*FLEN/8, x13, x9, x10)

inst_31546:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x600000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x6c600000; valaddr_reg:x12; val_offset:94575*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94575*FLEN/8, x13, x9, x10)

inst_31547:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x0fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x6c0fffff; valaddr_reg:x12; val_offset:94578*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94578*FLEN/8, x13, x9, x10)

inst_31548:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x700000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x6c700000; valaddr_reg:x12; val_offset:94581*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94581*FLEN/8, x13, x9, x10)

inst_31549:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x07ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x6c07ffff; valaddr_reg:x12; val_offset:94584*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94584*FLEN/8, x13, x9, x10)

inst_31550:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x780000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x6c780000; valaddr_reg:x12; val_offset:94587*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94587*FLEN/8, x13, x9, x10)

inst_31551:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x03ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x6c03ffff; valaddr_reg:x12; val_offset:94590*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94590*FLEN/8, x13, x9, x10)

inst_31552:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x7c0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x6c7c0000; valaddr_reg:x12; val_offset:94593*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94593*FLEN/8, x13, x9, x10)

inst_31553:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x01ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x6c01ffff; valaddr_reg:x12; val_offset:94596*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94596*FLEN/8, x13, x9, x10)

inst_31554:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x7e0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x6c7e0000; valaddr_reg:x12; val_offset:94599*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94599*FLEN/8, x13, x9, x10)

inst_31555:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x00ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x6c00ffff; valaddr_reg:x12; val_offset:94602*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94602*FLEN/8, x13, x9, x10)

inst_31556:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x7f0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x6c7f0000; valaddr_reg:x12; val_offset:94605*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94605*FLEN/8, x13, x9, x10)

inst_31557:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x007fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x6c007fff; valaddr_reg:x12; val_offset:94608*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94608*FLEN/8, x13, x9, x10)

inst_31558:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x7f8000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x6c7f8000; valaddr_reg:x12; val_offset:94611*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94611*FLEN/8, x13, x9, x10)

inst_31559:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x003fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x6c003fff; valaddr_reg:x12; val_offset:94614*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94614*FLEN/8, x13, x9, x10)

inst_31560:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x7fc000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x6c7fc000; valaddr_reg:x12; val_offset:94617*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94617*FLEN/8, x13, x9, x10)

inst_31561:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x001fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x6c001fff; valaddr_reg:x12; val_offset:94620*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94620*FLEN/8, x13, x9, x10)

inst_31562:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x7fe000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x6c7fe000; valaddr_reg:x12; val_offset:94623*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94623*FLEN/8, x13, x9, x10)

inst_31563:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x000fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x6c000fff; valaddr_reg:x12; val_offset:94626*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94626*FLEN/8, x13, x9, x10)

inst_31564:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x7ff000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x6c7ff000; valaddr_reg:x12; val_offset:94629*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94629*FLEN/8, x13, x9, x10)

inst_31565:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x0007ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x6c0007ff; valaddr_reg:x12; val_offset:94632*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94632*FLEN/8, x13, x9, x10)

inst_31566:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x7ff800 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x6c7ff800; valaddr_reg:x12; val_offset:94635*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94635*FLEN/8, x13, x9, x10)

inst_31567:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x0003ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x6c0003ff; valaddr_reg:x12; val_offset:94638*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94638*FLEN/8, x13, x9, x10)

inst_31568:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x7ffc00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x6c7ffc00; valaddr_reg:x12; val_offset:94641*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94641*FLEN/8, x13, x9, x10)

inst_31569:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x0001ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x6c0001ff; valaddr_reg:x12; val_offset:94644*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94644*FLEN/8, x13, x9, x10)

inst_31570:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x7ffe00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x6c7ffe00; valaddr_reg:x12; val_offset:94647*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94647*FLEN/8, x13, x9, x10)

inst_31571:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x0000ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x6c0000ff; valaddr_reg:x12; val_offset:94650*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94650*FLEN/8, x13, x9, x10)

inst_31572:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x7fff00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x6c7fff00; valaddr_reg:x12; val_offset:94653*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94653*FLEN/8, x13, x9, x10)

inst_31573:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x00007f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x6c00007f; valaddr_reg:x12; val_offset:94656*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94656*FLEN/8, x13, x9, x10)

inst_31574:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x7fff80 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x6c7fff80; valaddr_reg:x12; val_offset:94659*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94659*FLEN/8, x13, x9, x10)

inst_31575:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x00003f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x6c00003f; valaddr_reg:x12; val_offset:94662*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94662*FLEN/8, x13, x9, x10)

inst_31576:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x7fffc0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x6c7fffc0; valaddr_reg:x12; val_offset:94665*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94665*FLEN/8, x13, x9, x10)

inst_31577:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x00001f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x6c00001f; valaddr_reg:x12; val_offset:94668*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94668*FLEN/8, x13, x9, x10)

inst_31578:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x7fffe0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x6c7fffe0; valaddr_reg:x12; val_offset:94671*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94671*FLEN/8, x13, x9, x10)

inst_31579:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x00000f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x6c00000f; valaddr_reg:x12; val_offset:94674*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94674*FLEN/8, x13, x9, x10)

inst_31580:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x7ffff0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x6c7ffff0; valaddr_reg:x12; val_offset:94677*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94677*FLEN/8, x13, x9, x10)

inst_31581:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x6c000007; valaddr_reg:x12; val_offset:94680*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94680*FLEN/8, x13, x9, x10)

inst_31582:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x6c7ffff8; valaddr_reg:x12; val_offset:94683*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94683*FLEN/8, x13, x9, x10)

inst_31583:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x6c000003; valaddr_reg:x12; val_offset:94686*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94686*FLEN/8, x13, x9, x10)

inst_31584:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x6c7ffffc; valaddr_reg:x12; val_offset:94689*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94689*FLEN/8, x13, x9, x10)

inst_31585:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x6c000001; valaddr_reg:x12; val_offset:94692*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94692*FLEN/8, x13, x9, x10)

inst_31586:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xd8 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x6c7ffffe; valaddr_reg:x12; val_offset:94695*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94695*FLEN/8, x13, x9, x10)

inst_31587:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x7f7ffff8; valaddr_reg:x12; val_offset:94698*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94698*FLEN/8, x13, x9, x10)

inst_31588:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x7f000007; valaddr_reg:x12; val_offset:94701*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94701*FLEN/8, x13, x9, x10)

inst_31589:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x7f7ffffc; valaddr_reg:x12; val_offset:94704*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94704*FLEN/8, x13, x9, x10)

inst_31590:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x7f000003; valaddr_reg:x12; val_offset:94707*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94707*FLEN/8, x13, x9, x10)

inst_31591:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x7f7ffffe; valaddr_reg:x12; val_offset:94710*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94710*FLEN/8, x13, x9, x10)

inst_31592:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x7f000001; valaddr_reg:x12; val_offset:94713*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94713*FLEN/8, x13, x9, x10)

inst_31593:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xfe and fm3 == 0x36db6d and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x7f36db6d; valaddr_reg:x12; val_offset:94716*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94716*FLEN/8, x13, x9, x10)

inst_31594:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xfe and fm3 == 0x6db6db and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x7f6db6db; valaddr_reg:x12; val_offset:94719*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94719*FLEN/8, x13, x9, x10)

inst_31595:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xfe and fm3 == 0x199999 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x7f199999; valaddr_reg:x12; val_offset:94722*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94722*FLEN/8, x13, x9, x10)

inst_31596:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xfe and fm3 == 0x666666 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x7f666666; valaddr_reg:x12; val_offset:94725*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94725*FLEN/8, x13, x9, x10)

inst_31597:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3bbbbb and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x7f3bbbbb; valaddr_reg:x12; val_offset:94728*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94728*FLEN/8, x13, x9, x10)

inst_31598:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xfe and fm3 == 0x444444 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x7f444444; valaddr_reg:x12; val_offset:94731*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94731*FLEN/8, x13, x9, x10)

inst_31599:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xfe and fm3 == 0x249249 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x7f249249; valaddr_reg:x12; val_offset:94734*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94734*FLEN/8, x13, x9, x10)

inst_31600:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xfe and fm3 == 0x5b6db6 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x7f5b6db6; valaddr_reg:x12; val_offset:94737*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94737*FLEN/8, x13, x9, x10)

inst_31601:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xfe and fm3 == 0x333333 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x7f333333; valaddr_reg:x12; val_offset:94740*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94740*FLEN/8, x13, x9, x10)

inst_31602:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x44356e and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27017d and fs3 == 0 and fe3 == 0xfe and fm3 == 0x4ccccc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ec4356e; op2val:0x4027017d;
op3val:0x7f4ccccc; valaddr_reg:x12; val_offset:94743*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94743*FLEN/8, x13, x9, x10)

inst_31603:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xd9 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x6cffffff; valaddr_reg:x12; val_offset:94746*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94746*FLEN/8, x13, x9, x10)

inst_31604:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xd9 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x6c800000; valaddr_reg:x12; val_offset:94749*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94749*FLEN/8, x13, x9, x10)

inst_31605:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xd9 and fm3 == 0x3fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x6cbfffff; valaddr_reg:x12; val_offset:94752*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94752*FLEN/8, x13, x9, x10)

inst_31606:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xd9 and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x6cc00000; valaddr_reg:x12; val_offset:94755*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94755*FLEN/8, x13, x9, x10)

inst_31607:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xd9 and fm3 == 0x1fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x6c9fffff; valaddr_reg:x12; val_offset:94758*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94758*FLEN/8, x13, x9, x10)

inst_31608:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xd9 and fm3 == 0x600000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x6ce00000; valaddr_reg:x12; val_offset:94761*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94761*FLEN/8, x13, x9, x10)

inst_31609:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xd9 and fm3 == 0x0fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x6c8fffff; valaddr_reg:x12; val_offset:94764*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94764*FLEN/8, x13, x9, x10)

inst_31610:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xd9 and fm3 == 0x700000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x6cf00000; valaddr_reg:x12; val_offset:94767*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94767*FLEN/8, x13, x9, x10)

inst_31611:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xd9 and fm3 == 0x07ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x6c87ffff; valaddr_reg:x12; val_offset:94770*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94770*FLEN/8, x13, x9, x10)

inst_31612:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xd9 and fm3 == 0x780000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x6cf80000; valaddr_reg:x12; val_offset:94773*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94773*FLEN/8, x13, x9, x10)

inst_31613:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xd9 and fm3 == 0x03ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x6c83ffff; valaddr_reg:x12; val_offset:94776*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94776*FLEN/8, x13, x9, x10)

inst_31614:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xd9 and fm3 == 0x7c0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x6cfc0000; valaddr_reg:x12; val_offset:94779*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94779*FLEN/8, x13, x9, x10)

inst_31615:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xd9 and fm3 == 0x01ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x6c81ffff; valaddr_reg:x12; val_offset:94782*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94782*FLEN/8, x13, x9, x10)

inst_31616:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xd9 and fm3 == 0x7e0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x6cfe0000; valaddr_reg:x12; val_offset:94785*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94785*FLEN/8, x13, x9, x10)

inst_31617:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xd9 and fm3 == 0x00ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x6c80ffff; valaddr_reg:x12; val_offset:94788*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94788*FLEN/8, x13, x9, x10)

inst_31618:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xd9 and fm3 == 0x7f0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x6cff0000; valaddr_reg:x12; val_offset:94791*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94791*FLEN/8, x13, x9, x10)

inst_31619:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xd9 and fm3 == 0x007fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x6c807fff; valaddr_reg:x12; val_offset:94794*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94794*FLEN/8, x13, x9, x10)

inst_31620:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xd9 and fm3 == 0x7f8000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x6cff8000; valaddr_reg:x12; val_offset:94797*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94797*FLEN/8, x13, x9, x10)

inst_31621:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xd9 and fm3 == 0x003fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x6c803fff; valaddr_reg:x12; val_offset:94800*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94800*FLEN/8, x13, x9, x10)

inst_31622:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xd9 and fm3 == 0x7fc000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x6cffc000; valaddr_reg:x12; val_offset:94803*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94803*FLEN/8, x13, x9, x10)

inst_31623:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xd9 and fm3 == 0x001fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x6c801fff; valaddr_reg:x12; val_offset:94806*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94806*FLEN/8, x13, x9, x10)

inst_31624:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xd9 and fm3 == 0x7fe000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x6cffe000; valaddr_reg:x12; val_offset:94809*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94809*FLEN/8, x13, x9, x10)

inst_31625:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xd9 and fm3 == 0x000fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x6c800fff; valaddr_reg:x12; val_offset:94812*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94812*FLEN/8, x13, x9, x10)

inst_31626:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xd9 and fm3 == 0x7ff000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x6cfff000; valaddr_reg:x12; val_offset:94815*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94815*FLEN/8, x13, x9, x10)

inst_31627:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xd9 and fm3 == 0x0007ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x6c8007ff; valaddr_reg:x12; val_offset:94818*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94818*FLEN/8, x13, x9, x10)

inst_31628:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xd9 and fm3 == 0x7ff800 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x6cfff800; valaddr_reg:x12; val_offset:94821*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94821*FLEN/8, x13, x9, x10)

inst_31629:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xd9 and fm3 == 0x0003ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x6c8003ff; valaddr_reg:x12; val_offset:94824*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94824*FLEN/8, x13, x9, x10)

inst_31630:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xd9 and fm3 == 0x7ffc00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x6cfffc00; valaddr_reg:x12; val_offset:94827*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94827*FLEN/8, x13, x9, x10)

inst_31631:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xd9 and fm3 == 0x0001ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x6c8001ff; valaddr_reg:x12; val_offset:94830*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94830*FLEN/8, x13, x9, x10)

inst_31632:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xd9 and fm3 == 0x7ffe00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x6cfffe00; valaddr_reg:x12; val_offset:94833*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94833*FLEN/8, x13, x9, x10)

inst_31633:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xd9 and fm3 == 0x0000ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x6c8000ff; valaddr_reg:x12; val_offset:94836*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94836*FLEN/8, x13, x9, x10)

inst_31634:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xd9 and fm3 == 0x7fff00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x6cffff00; valaddr_reg:x12; val_offset:94839*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94839*FLEN/8, x13, x9, x10)

inst_31635:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xd9 and fm3 == 0x00007f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x6c80007f; valaddr_reg:x12; val_offset:94842*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94842*FLEN/8, x13, x9, x10)

inst_31636:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xd9 and fm3 == 0x7fff80 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x6cffff80; valaddr_reg:x12; val_offset:94845*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94845*FLEN/8, x13, x9, x10)

inst_31637:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xd9 and fm3 == 0x00003f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x6c80003f; valaddr_reg:x12; val_offset:94848*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94848*FLEN/8, x13, x9, x10)

inst_31638:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xd9 and fm3 == 0x7fffc0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x6cffffc0; valaddr_reg:x12; val_offset:94851*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94851*FLEN/8, x13, x9, x10)

inst_31639:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xd9 and fm3 == 0x00001f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x6c80001f; valaddr_reg:x12; val_offset:94854*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94854*FLEN/8, x13, x9, x10)

RVTEST_SIGBASE(x9,signature_x9_247)
inst_31640:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xd9 and fm3 == 0x7fffe0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x6cffffe0; valaddr_reg:x12; val_offset:94857*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94857*FLEN/8, x13, x9, x10)

inst_31641:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xd9 and fm3 == 0x00000f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x6c80000f; valaddr_reg:x12; val_offset:94860*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94860*FLEN/8, x13, x9, x10)

inst_31642:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xd9 and fm3 == 0x7ffff0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x6cfffff0; valaddr_reg:x12; val_offset:94863*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94863*FLEN/8, x13, x9, x10)

inst_31643:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xd9 and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x6c800007; valaddr_reg:x12; val_offset:94866*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94866*FLEN/8, x13, x9, x10)

inst_31644:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xd9 and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x6cfffff8; valaddr_reg:x12; val_offset:94869*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94869*FLEN/8, x13, x9, x10)

inst_31645:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xd9 and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x6c800003; valaddr_reg:x12; val_offset:94872*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94872*FLEN/8, x13, x9, x10)

inst_31646:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xd9 and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x6cfffffc; valaddr_reg:x12; val_offset:94875*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94875*FLEN/8, x13, x9, x10)

inst_31647:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xd9 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x6c800001; valaddr_reg:x12; val_offset:94878*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94878*FLEN/8, x13, x9, x10)

inst_31648:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xd9 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x6cfffffe; valaddr_reg:x12; val_offset:94881*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94881*FLEN/8, x13, x9, x10)

inst_31649:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x7f7ffff8; valaddr_reg:x12; val_offset:94884*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94884*FLEN/8, x13, x9, x10)

inst_31650:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x7f000007; valaddr_reg:x12; val_offset:94887*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94887*FLEN/8, x13, x9, x10)

inst_31651:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x7f7ffffc; valaddr_reg:x12; val_offset:94890*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94890*FLEN/8, x13, x9, x10)

inst_31652:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x7f000003; valaddr_reg:x12; val_offset:94893*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94893*FLEN/8, x13, x9, x10)

inst_31653:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x7f7ffffe; valaddr_reg:x12; val_offset:94896*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94896*FLEN/8, x13, x9, x10)

inst_31654:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x7f000001; valaddr_reg:x12; val_offset:94899*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94899*FLEN/8, x13, x9, x10)

inst_31655:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xfe and fm3 == 0x36db6d and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x7f36db6d; valaddr_reg:x12; val_offset:94902*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94902*FLEN/8, x13, x9, x10)

inst_31656:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xfe and fm3 == 0x6db6db and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x7f6db6db; valaddr_reg:x12; val_offset:94905*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94905*FLEN/8, x13, x9, x10)

inst_31657:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xfe and fm3 == 0x199999 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x7f199999; valaddr_reg:x12; val_offset:94908*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94908*FLEN/8, x13, x9, x10)

inst_31658:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xfe and fm3 == 0x666666 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x7f666666; valaddr_reg:x12; val_offset:94911*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94911*FLEN/8, x13, x9, x10)

inst_31659:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3bbbbb and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x7f3bbbbb; valaddr_reg:x12; val_offset:94914*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94914*FLEN/8, x13, x9, x10)

inst_31660:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xfe and fm3 == 0x444444 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x7f444444; valaddr_reg:x12; val_offset:94917*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94917*FLEN/8, x13, x9, x10)

inst_31661:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xfe and fm3 == 0x249249 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x7f249249; valaddr_reg:x12; val_offset:94920*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94920*FLEN/8, x13, x9, x10)

inst_31662:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xfe and fm3 == 0x5b6db6 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x7f5b6db6; valaddr_reg:x12; val_offset:94923*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94923*FLEN/8, x13, x9, x10)

inst_31663:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xfe and fm3 == 0x333333 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x7f333333; valaddr_reg:x12; val_offset:94926*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94926*FLEN/8, x13, x9, x10)

inst_31664:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d81e9 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ce94f and fs3 == 0 and fe3 == 0xfe and fm3 == 0x4ccccc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d81e9; op2val:0x3face94f;
op3val:0x7f4ccccc; valaddr_reg:x12; val_offset:94929*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94929*FLEN/8, x13, x9, x10)

inst_31665:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xda and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x6d7fffff; valaddr_reg:x12; val_offset:94932*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94932*FLEN/8, x13, x9, x10)

inst_31666:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xda and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x6d000000; valaddr_reg:x12; val_offset:94935*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94935*FLEN/8, x13, x9, x10)

inst_31667:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xda and fm3 == 0x3fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x6d3fffff; valaddr_reg:x12; val_offset:94938*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94938*FLEN/8, x13, x9, x10)

inst_31668:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xda and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x6d400000; valaddr_reg:x12; val_offset:94941*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94941*FLEN/8, x13, x9, x10)

inst_31669:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xda and fm3 == 0x1fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x6d1fffff; valaddr_reg:x12; val_offset:94944*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94944*FLEN/8, x13, x9, x10)

inst_31670:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xda and fm3 == 0x600000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x6d600000; valaddr_reg:x12; val_offset:94947*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94947*FLEN/8, x13, x9, x10)

inst_31671:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xda and fm3 == 0x0fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x6d0fffff; valaddr_reg:x12; val_offset:94950*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94950*FLEN/8, x13, x9, x10)

inst_31672:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xda and fm3 == 0x700000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x6d700000; valaddr_reg:x12; val_offset:94953*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94953*FLEN/8, x13, x9, x10)

inst_31673:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xda and fm3 == 0x07ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x6d07ffff; valaddr_reg:x12; val_offset:94956*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94956*FLEN/8, x13, x9, x10)

inst_31674:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xda and fm3 == 0x780000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x6d780000; valaddr_reg:x12; val_offset:94959*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94959*FLEN/8, x13, x9, x10)

inst_31675:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xda and fm3 == 0x03ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x6d03ffff; valaddr_reg:x12; val_offset:94962*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94962*FLEN/8, x13, x9, x10)

inst_31676:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xda and fm3 == 0x7c0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x6d7c0000; valaddr_reg:x12; val_offset:94965*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94965*FLEN/8, x13, x9, x10)

inst_31677:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xda and fm3 == 0x01ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x6d01ffff; valaddr_reg:x12; val_offset:94968*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94968*FLEN/8, x13, x9, x10)

inst_31678:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xda and fm3 == 0x7e0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x6d7e0000; valaddr_reg:x12; val_offset:94971*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94971*FLEN/8, x13, x9, x10)

inst_31679:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xda and fm3 == 0x00ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x6d00ffff; valaddr_reg:x12; val_offset:94974*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94974*FLEN/8, x13, x9, x10)

inst_31680:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xda and fm3 == 0x7f0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x6d7f0000; valaddr_reg:x12; val_offset:94977*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94977*FLEN/8, x13, x9, x10)

inst_31681:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xda and fm3 == 0x007fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x6d007fff; valaddr_reg:x12; val_offset:94980*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94980*FLEN/8, x13, x9, x10)

inst_31682:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xda and fm3 == 0x7f8000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x6d7f8000; valaddr_reg:x12; val_offset:94983*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94983*FLEN/8, x13, x9, x10)

inst_31683:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xda and fm3 == 0x003fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x6d003fff; valaddr_reg:x12; val_offset:94986*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94986*FLEN/8, x13, x9, x10)

inst_31684:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xda and fm3 == 0x7fc000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x6d7fc000; valaddr_reg:x12; val_offset:94989*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94989*FLEN/8, x13, x9, x10)

inst_31685:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xda and fm3 == 0x001fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x6d001fff; valaddr_reg:x12; val_offset:94992*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94992*FLEN/8, x13, x9, x10)

inst_31686:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xda and fm3 == 0x7fe000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x6d7fe000; valaddr_reg:x12; val_offset:94995*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94995*FLEN/8, x13, x9, x10)

inst_31687:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xda and fm3 == 0x000fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x6d000fff; valaddr_reg:x12; val_offset:94998*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 94998*FLEN/8, x13, x9, x10)

inst_31688:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xda and fm3 == 0x7ff000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x6d7ff000; valaddr_reg:x12; val_offset:95001*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95001*FLEN/8, x13, x9, x10)

inst_31689:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xda and fm3 == 0x0007ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x6d0007ff; valaddr_reg:x12; val_offset:95004*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95004*FLEN/8, x13, x9, x10)

inst_31690:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xda and fm3 == 0x7ff800 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x6d7ff800; valaddr_reg:x12; val_offset:95007*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95007*FLEN/8, x13, x9, x10)

inst_31691:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xda and fm3 == 0x0003ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x6d0003ff; valaddr_reg:x12; val_offset:95010*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95010*FLEN/8, x13, x9, x10)

inst_31692:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xda and fm3 == 0x7ffc00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x6d7ffc00; valaddr_reg:x12; val_offset:95013*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95013*FLEN/8, x13, x9, x10)

inst_31693:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xda and fm3 == 0x0001ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x6d0001ff; valaddr_reg:x12; val_offset:95016*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95016*FLEN/8, x13, x9, x10)

inst_31694:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xda and fm3 == 0x7ffe00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x6d7ffe00; valaddr_reg:x12; val_offset:95019*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95019*FLEN/8, x13, x9, x10)

inst_31695:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xda and fm3 == 0x0000ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x6d0000ff; valaddr_reg:x12; val_offset:95022*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95022*FLEN/8, x13, x9, x10)

inst_31696:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xda and fm3 == 0x7fff00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x6d7fff00; valaddr_reg:x12; val_offset:95025*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95025*FLEN/8, x13, x9, x10)

inst_31697:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xda and fm3 == 0x00007f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x6d00007f; valaddr_reg:x12; val_offset:95028*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95028*FLEN/8, x13, x9, x10)

inst_31698:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xda and fm3 == 0x7fff80 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x6d7fff80; valaddr_reg:x12; val_offset:95031*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95031*FLEN/8, x13, x9, x10)

inst_31699:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xda and fm3 == 0x00003f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x6d00003f; valaddr_reg:x12; val_offset:95034*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95034*FLEN/8, x13, x9, x10)

inst_31700:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xda and fm3 == 0x7fffc0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x6d7fffc0; valaddr_reg:x12; val_offset:95037*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95037*FLEN/8, x13, x9, x10)

inst_31701:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xda and fm3 == 0x00001f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x6d00001f; valaddr_reg:x12; val_offset:95040*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95040*FLEN/8, x13, x9, x10)

inst_31702:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xda and fm3 == 0x7fffe0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x6d7fffe0; valaddr_reg:x12; val_offset:95043*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95043*FLEN/8, x13, x9, x10)

inst_31703:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xda and fm3 == 0x00000f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x6d00000f; valaddr_reg:x12; val_offset:95046*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95046*FLEN/8, x13, x9, x10)

inst_31704:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xda and fm3 == 0x7ffff0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x6d7ffff0; valaddr_reg:x12; val_offset:95049*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95049*FLEN/8, x13, x9, x10)

inst_31705:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xda and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x6d000007; valaddr_reg:x12; val_offset:95052*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95052*FLEN/8, x13, x9, x10)

inst_31706:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xda and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x6d7ffff8; valaddr_reg:x12; val_offset:95055*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95055*FLEN/8, x13, x9, x10)

inst_31707:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xda and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x6d000003; valaddr_reg:x12; val_offset:95058*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95058*FLEN/8, x13, x9, x10)

inst_31708:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xda and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x6d7ffffc; valaddr_reg:x12; val_offset:95061*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95061*FLEN/8, x13, x9, x10)

inst_31709:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xda and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x6d000001; valaddr_reg:x12; val_offset:95064*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95064*FLEN/8, x13, x9, x10)

inst_31710:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xda and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x6d7ffffe; valaddr_reg:x12; val_offset:95067*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95067*FLEN/8, x13, x9, x10)

inst_31711:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x7f7ffff8; valaddr_reg:x12; val_offset:95070*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95070*FLEN/8, x13, x9, x10)

inst_31712:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x7f000007; valaddr_reg:x12; val_offset:95073*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95073*FLEN/8, x13, x9, x10)

inst_31713:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x7f7ffffc; valaddr_reg:x12; val_offset:95076*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95076*FLEN/8, x13, x9, x10)

inst_31714:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x7f000003; valaddr_reg:x12; val_offset:95079*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95079*FLEN/8, x13, x9, x10)

inst_31715:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x7f7ffffe; valaddr_reg:x12; val_offset:95082*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95082*FLEN/8, x13, x9, x10)

inst_31716:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x7f000001; valaddr_reg:x12; val_offset:95085*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95085*FLEN/8, x13, x9, x10)

inst_31717:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x36db6d and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x7f36db6d; valaddr_reg:x12; val_offset:95088*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95088*FLEN/8, x13, x9, x10)

inst_31718:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x6db6db and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x7f6db6db; valaddr_reg:x12; val_offset:95091*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95091*FLEN/8, x13, x9, x10)

inst_31719:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x199999 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x7f199999; valaddr_reg:x12; val_offset:95094*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95094*FLEN/8, x13, x9, x10)

inst_31720:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x666666 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x7f666666; valaddr_reg:x12; val_offset:95097*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95097*FLEN/8, x13, x9, x10)

inst_31721:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3bbbbb and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x7f3bbbbb; valaddr_reg:x12; val_offset:95100*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95100*FLEN/8, x13, x9, x10)

inst_31722:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x444444 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x7f444444; valaddr_reg:x12; val_offset:95103*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95103*FLEN/8, x13, x9, x10)

inst_31723:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x249249 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x7f249249; valaddr_reg:x12; val_offset:95106*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95106*FLEN/8, x13, x9, x10)

inst_31724:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x5b6db6 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x7f5b6db6; valaddr_reg:x12; val_offset:95109*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95109*FLEN/8, x13, x9, x10)

inst_31725:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x333333 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x7f333333; valaddr_reg:x12; val_offset:95112*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95112*FLEN/8, x13, x9, x10)

inst_31726:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x313f41 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x38df31 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x4ccccc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eb13f41; op2val:0x4038df31;
op3val:0x7f4ccccc; valaddr_reg:x12; val_offset:95115*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95115*FLEN/8, x13, x9, x10)

inst_31727:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xdb and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x6dffffff; valaddr_reg:x12; val_offset:95118*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95118*FLEN/8, x13, x9, x10)

inst_31728:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xdb and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x6d800000; valaddr_reg:x12; val_offset:95121*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95121*FLEN/8, x13, x9, x10)

inst_31729:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xdb and fm3 == 0x3fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x6dbfffff; valaddr_reg:x12; val_offset:95124*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95124*FLEN/8, x13, x9, x10)

inst_31730:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xdb and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x6dc00000; valaddr_reg:x12; val_offset:95127*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95127*FLEN/8, x13, x9, x10)

inst_31731:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xdb and fm3 == 0x1fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x6d9fffff; valaddr_reg:x12; val_offset:95130*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95130*FLEN/8, x13, x9, x10)

inst_31732:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xdb and fm3 == 0x600000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x6de00000; valaddr_reg:x12; val_offset:95133*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95133*FLEN/8, x13, x9, x10)

inst_31733:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xdb and fm3 == 0x0fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x6d8fffff; valaddr_reg:x12; val_offset:95136*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95136*FLEN/8, x13, x9, x10)

inst_31734:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xdb and fm3 == 0x700000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x6df00000; valaddr_reg:x12; val_offset:95139*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95139*FLEN/8, x13, x9, x10)

inst_31735:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xdb and fm3 == 0x07ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x6d87ffff; valaddr_reg:x12; val_offset:95142*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95142*FLEN/8, x13, x9, x10)

inst_31736:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xdb and fm3 == 0x780000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x6df80000; valaddr_reg:x12; val_offset:95145*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95145*FLEN/8, x13, x9, x10)

inst_31737:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xdb and fm3 == 0x03ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x6d83ffff; valaddr_reg:x12; val_offset:95148*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95148*FLEN/8, x13, x9, x10)

inst_31738:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xdb and fm3 == 0x7c0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x6dfc0000; valaddr_reg:x12; val_offset:95151*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95151*FLEN/8, x13, x9, x10)

inst_31739:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xdb and fm3 == 0x01ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x6d81ffff; valaddr_reg:x12; val_offset:95154*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95154*FLEN/8, x13, x9, x10)

inst_31740:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xdb and fm3 == 0x7e0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x6dfe0000; valaddr_reg:x12; val_offset:95157*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95157*FLEN/8, x13, x9, x10)

inst_31741:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xdb and fm3 == 0x00ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x6d80ffff; valaddr_reg:x12; val_offset:95160*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95160*FLEN/8, x13, x9, x10)

inst_31742:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xdb and fm3 == 0x7f0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x6dff0000; valaddr_reg:x12; val_offset:95163*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95163*FLEN/8, x13, x9, x10)

inst_31743:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xdb and fm3 == 0x007fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x6d807fff; valaddr_reg:x12; val_offset:95166*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95166*FLEN/8, x13, x9, x10)

inst_31744:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xdb and fm3 == 0x7f8000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x6dff8000; valaddr_reg:x12; val_offset:95169*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95169*FLEN/8, x13, x9, x10)

inst_31745:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xdb and fm3 == 0x003fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x6d803fff; valaddr_reg:x12; val_offset:95172*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95172*FLEN/8, x13, x9, x10)

inst_31746:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xdb and fm3 == 0x7fc000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x6dffc000; valaddr_reg:x12; val_offset:95175*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95175*FLEN/8, x13, x9, x10)

inst_31747:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xdb and fm3 == 0x001fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x6d801fff; valaddr_reg:x12; val_offset:95178*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95178*FLEN/8, x13, x9, x10)

inst_31748:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xdb and fm3 == 0x7fe000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x6dffe000; valaddr_reg:x12; val_offset:95181*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95181*FLEN/8, x13, x9, x10)

inst_31749:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xdb and fm3 == 0x000fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x6d800fff; valaddr_reg:x12; val_offset:95184*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95184*FLEN/8, x13, x9, x10)

inst_31750:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xdb and fm3 == 0x7ff000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x6dfff000; valaddr_reg:x12; val_offset:95187*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95187*FLEN/8, x13, x9, x10)

inst_31751:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xdb and fm3 == 0x0007ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x6d8007ff; valaddr_reg:x12; val_offset:95190*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95190*FLEN/8, x13, x9, x10)

inst_31752:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xdb and fm3 == 0x7ff800 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x6dfff800; valaddr_reg:x12; val_offset:95193*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95193*FLEN/8, x13, x9, x10)

inst_31753:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xdb and fm3 == 0x0003ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x6d8003ff; valaddr_reg:x12; val_offset:95196*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95196*FLEN/8, x13, x9, x10)

inst_31754:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xdb and fm3 == 0x7ffc00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x6dfffc00; valaddr_reg:x12; val_offset:95199*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95199*FLEN/8, x13, x9, x10)

inst_31755:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xdb and fm3 == 0x0001ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x6d8001ff; valaddr_reg:x12; val_offset:95202*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95202*FLEN/8, x13, x9, x10)

inst_31756:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xdb and fm3 == 0x7ffe00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x6dfffe00; valaddr_reg:x12; val_offset:95205*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95205*FLEN/8, x13, x9, x10)

inst_31757:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xdb and fm3 == 0x0000ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x6d8000ff; valaddr_reg:x12; val_offset:95208*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95208*FLEN/8, x13, x9, x10)

inst_31758:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xdb and fm3 == 0x7fff00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x6dffff00; valaddr_reg:x12; val_offset:95211*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95211*FLEN/8, x13, x9, x10)

inst_31759:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xdb and fm3 == 0x00007f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x6d80007f; valaddr_reg:x12; val_offset:95214*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95214*FLEN/8, x13, x9, x10)

inst_31760:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xdb and fm3 == 0x7fff80 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x6dffff80; valaddr_reg:x12; val_offset:95217*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95217*FLEN/8, x13, x9, x10)

inst_31761:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xdb and fm3 == 0x00003f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x6d80003f; valaddr_reg:x12; val_offset:95220*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95220*FLEN/8, x13, x9, x10)

inst_31762:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xdb and fm3 == 0x7fffc0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x6dffffc0; valaddr_reg:x12; val_offset:95223*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95223*FLEN/8, x13, x9, x10)

inst_31763:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xdb and fm3 == 0x00001f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x6d80001f; valaddr_reg:x12; val_offset:95226*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95226*FLEN/8, x13, x9, x10)

inst_31764:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xdb and fm3 == 0x7fffe0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x6dffffe0; valaddr_reg:x12; val_offset:95229*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95229*FLEN/8, x13, x9, x10)

inst_31765:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xdb and fm3 == 0x00000f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x6d80000f; valaddr_reg:x12; val_offset:95232*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95232*FLEN/8, x13, x9, x10)

inst_31766:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xdb and fm3 == 0x7ffff0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x6dfffff0; valaddr_reg:x12; val_offset:95235*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95235*FLEN/8, x13, x9, x10)

inst_31767:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xdb and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x6d800007; valaddr_reg:x12; val_offset:95238*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95238*FLEN/8, x13, x9, x10)

RVTEST_SIGBASE(x9,signature_x9_248)
inst_31768:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xdb and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x6dfffff8; valaddr_reg:x12; val_offset:95241*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95241*FLEN/8, x13, x9, x10)

inst_31769:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xdb and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x6d800003; valaddr_reg:x12; val_offset:95244*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95244*FLEN/8, x13, x9, x10)

inst_31770:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xdb and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x6dfffffc; valaddr_reg:x12; val_offset:95247*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95247*FLEN/8, x13, x9, x10)

inst_31771:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xdb and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x6d800001; valaddr_reg:x12; val_offset:95250*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95250*FLEN/8, x13, x9, x10)

inst_31772:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xdb and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x6dfffffe; valaddr_reg:x12; val_offset:95253*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95253*FLEN/8, x13, x9, x10)

inst_31773:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x7f7ffff8; valaddr_reg:x12; val_offset:95256*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95256*FLEN/8, x13, x9, x10)

inst_31774:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x7f000007; valaddr_reg:x12; val_offset:95259*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95259*FLEN/8, x13, x9, x10)

inst_31775:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x7f7ffffc; valaddr_reg:x12; val_offset:95262*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95262*FLEN/8, x13, x9, x10)

inst_31776:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x7f000003; valaddr_reg:x12; val_offset:95265*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95265*FLEN/8, x13, x9, x10)

inst_31777:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x7f7ffffe; valaddr_reg:x12; val_offset:95268*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95268*FLEN/8, x13, x9, x10)

inst_31778:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x7f000001; valaddr_reg:x12; val_offset:95271*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95271*FLEN/8, x13, x9, x10)

inst_31779:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x36db6d and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x7f36db6d; valaddr_reg:x12; val_offset:95274*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95274*FLEN/8, x13, x9, x10)

inst_31780:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x6db6db and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x7f6db6db; valaddr_reg:x12; val_offset:95277*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95277*FLEN/8, x13, x9, x10)

inst_31781:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x199999 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x7f199999; valaddr_reg:x12; val_offset:95280*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95280*FLEN/8, x13, x9, x10)

inst_31782:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x666666 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x7f666666; valaddr_reg:x12; val_offset:95283*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95283*FLEN/8, x13, x9, x10)

inst_31783:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3bbbbb and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x7f3bbbbb; valaddr_reg:x12; val_offset:95286*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95286*FLEN/8, x13, x9, x10)

inst_31784:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x444444 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x7f444444; valaddr_reg:x12; val_offset:95289*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95289*FLEN/8, x13, x9, x10)

inst_31785:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x249249 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x7f249249; valaddr_reg:x12; val_offset:95292*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95292*FLEN/8, x13, x9, x10)

inst_31786:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x5b6db6 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x7f5b6db6; valaddr_reg:x12; val_offset:95295*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95295*FLEN/8, x13, x9, x10)

inst_31787:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x333333 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x7f333333; valaddr_reg:x12; val_offset:95298*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95298*FLEN/8, x13, x9, x10)

inst_31788:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x203def and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c7da2 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x4ccccc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f203def; op2val:0x3fcc7da2;
op3val:0x7f4ccccc; valaddr_reg:x12; val_offset:95301*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95301*FLEN/8, x13, x9, x10)

inst_31789:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xdc and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x6e7fffff; valaddr_reg:x12; val_offset:95304*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95304*FLEN/8, x13, x9, x10)

inst_31790:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xdc and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x6e000000; valaddr_reg:x12; val_offset:95307*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95307*FLEN/8, x13, x9, x10)

inst_31791:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xdc and fm3 == 0x3fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x6e3fffff; valaddr_reg:x12; val_offset:95310*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95310*FLEN/8, x13, x9, x10)

inst_31792:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xdc and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x6e400000; valaddr_reg:x12; val_offset:95313*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95313*FLEN/8, x13, x9, x10)

inst_31793:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xdc and fm3 == 0x1fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x6e1fffff; valaddr_reg:x12; val_offset:95316*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95316*FLEN/8, x13, x9, x10)

inst_31794:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xdc and fm3 == 0x600000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x6e600000; valaddr_reg:x12; val_offset:95319*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95319*FLEN/8, x13, x9, x10)

inst_31795:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xdc and fm3 == 0x0fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x6e0fffff; valaddr_reg:x12; val_offset:95322*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95322*FLEN/8, x13, x9, x10)

inst_31796:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xdc and fm3 == 0x700000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x6e700000; valaddr_reg:x12; val_offset:95325*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95325*FLEN/8, x13, x9, x10)

inst_31797:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xdc and fm3 == 0x07ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x6e07ffff; valaddr_reg:x12; val_offset:95328*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95328*FLEN/8, x13, x9, x10)

inst_31798:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xdc and fm3 == 0x780000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x6e780000; valaddr_reg:x12; val_offset:95331*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95331*FLEN/8, x13, x9, x10)

inst_31799:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xdc and fm3 == 0x03ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x6e03ffff; valaddr_reg:x12; val_offset:95334*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95334*FLEN/8, x13, x9, x10)

inst_31800:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xdc and fm3 == 0x7c0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x6e7c0000; valaddr_reg:x12; val_offset:95337*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95337*FLEN/8, x13, x9, x10)

inst_31801:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xdc and fm3 == 0x01ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x6e01ffff; valaddr_reg:x12; val_offset:95340*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95340*FLEN/8, x13, x9, x10)

inst_31802:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xdc and fm3 == 0x7e0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x6e7e0000; valaddr_reg:x12; val_offset:95343*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95343*FLEN/8, x13, x9, x10)

inst_31803:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xdc and fm3 == 0x00ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x6e00ffff; valaddr_reg:x12; val_offset:95346*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95346*FLEN/8, x13, x9, x10)

inst_31804:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xdc and fm3 == 0x7f0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x6e7f0000; valaddr_reg:x12; val_offset:95349*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95349*FLEN/8, x13, x9, x10)

inst_31805:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xdc and fm3 == 0x007fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x6e007fff; valaddr_reg:x12; val_offset:95352*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95352*FLEN/8, x13, x9, x10)

inst_31806:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xdc and fm3 == 0x7f8000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x6e7f8000; valaddr_reg:x12; val_offset:95355*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95355*FLEN/8, x13, x9, x10)

inst_31807:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xdc and fm3 == 0x003fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x6e003fff; valaddr_reg:x12; val_offset:95358*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95358*FLEN/8, x13, x9, x10)

inst_31808:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xdc and fm3 == 0x7fc000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x6e7fc000; valaddr_reg:x12; val_offset:95361*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95361*FLEN/8, x13, x9, x10)

inst_31809:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xdc and fm3 == 0x001fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x6e001fff; valaddr_reg:x12; val_offset:95364*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95364*FLEN/8, x13, x9, x10)

inst_31810:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xdc and fm3 == 0x7fe000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x6e7fe000; valaddr_reg:x12; val_offset:95367*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95367*FLEN/8, x13, x9, x10)

inst_31811:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xdc and fm3 == 0x000fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x6e000fff; valaddr_reg:x12; val_offset:95370*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95370*FLEN/8, x13, x9, x10)

inst_31812:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xdc and fm3 == 0x7ff000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x6e7ff000; valaddr_reg:x12; val_offset:95373*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95373*FLEN/8, x13, x9, x10)

inst_31813:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xdc and fm3 == 0x0007ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x6e0007ff; valaddr_reg:x12; val_offset:95376*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95376*FLEN/8, x13, x9, x10)

inst_31814:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xdc and fm3 == 0x7ff800 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x6e7ff800; valaddr_reg:x12; val_offset:95379*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95379*FLEN/8, x13, x9, x10)

inst_31815:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xdc and fm3 == 0x0003ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x6e0003ff; valaddr_reg:x12; val_offset:95382*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95382*FLEN/8, x13, x9, x10)

inst_31816:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xdc and fm3 == 0x7ffc00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x6e7ffc00; valaddr_reg:x12; val_offset:95385*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95385*FLEN/8, x13, x9, x10)

inst_31817:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xdc and fm3 == 0x0001ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x6e0001ff; valaddr_reg:x12; val_offset:95388*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95388*FLEN/8, x13, x9, x10)

inst_31818:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xdc and fm3 == 0x7ffe00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x6e7ffe00; valaddr_reg:x12; val_offset:95391*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95391*FLEN/8, x13, x9, x10)

inst_31819:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xdc and fm3 == 0x0000ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x6e0000ff; valaddr_reg:x12; val_offset:95394*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95394*FLEN/8, x13, x9, x10)

inst_31820:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xdc and fm3 == 0x7fff00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x6e7fff00; valaddr_reg:x12; val_offset:95397*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95397*FLEN/8, x13, x9, x10)

inst_31821:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xdc and fm3 == 0x00007f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x6e00007f; valaddr_reg:x12; val_offset:95400*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95400*FLEN/8, x13, x9, x10)

inst_31822:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xdc and fm3 == 0x7fff80 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x6e7fff80; valaddr_reg:x12; val_offset:95403*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95403*FLEN/8, x13, x9, x10)

inst_31823:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xdc and fm3 == 0x00003f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x6e00003f; valaddr_reg:x12; val_offset:95406*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95406*FLEN/8, x13, x9, x10)

inst_31824:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xdc and fm3 == 0x7fffc0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x6e7fffc0; valaddr_reg:x12; val_offset:95409*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95409*FLEN/8, x13, x9, x10)

inst_31825:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xdc and fm3 == 0x00001f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x6e00001f; valaddr_reg:x12; val_offset:95412*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95412*FLEN/8, x13, x9, x10)

inst_31826:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xdc and fm3 == 0x7fffe0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x6e7fffe0; valaddr_reg:x12; val_offset:95415*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95415*FLEN/8, x13, x9, x10)

inst_31827:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xdc and fm3 == 0x00000f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x6e00000f; valaddr_reg:x12; val_offset:95418*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95418*FLEN/8, x13, x9, x10)

inst_31828:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xdc and fm3 == 0x7ffff0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x6e7ffff0; valaddr_reg:x12; val_offset:95421*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95421*FLEN/8, x13, x9, x10)

inst_31829:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xdc and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x6e000007; valaddr_reg:x12; val_offset:95424*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95424*FLEN/8, x13, x9, x10)

inst_31830:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xdc and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x6e7ffff8; valaddr_reg:x12; val_offset:95427*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95427*FLEN/8, x13, x9, x10)

inst_31831:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xdc and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x6e000003; valaddr_reg:x12; val_offset:95430*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95430*FLEN/8, x13, x9, x10)

inst_31832:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xdc and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x6e7ffffc; valaddr_reg:x12; val_offset:95433*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95433*FLEN/8, x13, x9, x10)

inst_31833:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xdc and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x6e000001; valaddr_reg:x12; val_offset:95436*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95436*FLEN/8, x13, x9, x10)

inst_31834:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xdc and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x6e7ffffe; valaddr_reg:x12; val_offset:95439*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95439*FLEN/8, x13, x9, x10)

inst_31835:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x7f7ffff8; valaddr_reg:x12; val_offset:95442*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95442*FLEN/8, x13, x9, x10)

inst_31836:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x7f000007; valaddr_reg:x12; val_offset:95445*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95445*FLEN/8, x13, x9, x10)

inst_31837:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x7f7ffffc; valaddr_reg:x12; val_offset:95448*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95448*FLEN/8, x13, x9, x10)

inst_31838:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x7f000003; valaddr_reg:x12; val_offset:95451*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95451*FLEN/8, x13, x9, x10)

inst_31839:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x7f7ffffe; valaddr_reg:x12; val_offset:95454*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95454*FLEN/8, x13, x9, x10)

inst_31840:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x7f000001; valaddr_reg:x12; val_offset:95457*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95457*FLEN/8, x13, x9, x10)

inst_31841:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x36db6d and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x7f36db6d; valaddr_reg:x12; val_offset:95460*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95460*FLEN/8, x13, x9, x10)

inst_31842:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x6db6db and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x7f6db6db; valaddr_reg:x12; val_offset:95463*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95463*FLEN/8, x13, x9, x10)

inst_31843:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x199999 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x7f199999; valaddr_reg:x12; val_offset:95466*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95466*FLEN/8, x13, x9, x10)

inst_31844:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x666666 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x7f666666; valaddr_reg:x12; val_offset:95469*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95469*FLEN/8, x13, x9, x10)

inst_31845:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3bbbbb and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x7f3bbbbb; valaddr_reg:x12; val_offset:95472*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95472*FLEN/8, x13, x9, x10)

inst_31846:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x444444 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x7f444444; valaddr_reg:x12; val_offset:95475*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95475*FLEN/8, x13, x9, x10)

inst_31847:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x249249 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x7f249249; valaddr_reg:x12; val_offset:95478*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95478*FLEN/8, x13, x9, x10)

inst_31848:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x5b6db6 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x7f5b6db6; valaddr_reg:x12; val_offset:95481*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95481*FLEN/8, x13, x9, x10)

inst_31849:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x333333 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x7f333333; valaddr_reg:x12; val_offset:95484*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95484*FLEN/8, x13, x9, x10)

inst_31850:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1d0aed and fs2 == 0 and fe2 == 0x80 and fm2 == 0x50a819 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x4ccccc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9d0aed; op2val:0x4050a819;
op3val:0x7f4ccccc; valaddr_reg:x12; val_offset:95487*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95487*FLEN/8, x13, x9, x10)

inst_31851:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6effffff; valaddr_reg:x12; val_offset:95490*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95490*FLEN/8, x13, x9, x10)

inst_31852:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6e800000; valaddr_reg:x12; val_offset:95493*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95493*FLEN/8, x13, x9, x10)

inst_31853:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x3fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6ebfffff; valaddr_reg:x12; val_offset:95496*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95496*FLEN/8, x13, x9, x10)

inst_31854:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6ec00000; valaddr_reg:x12; val_offset:95499*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95499*FLEN/8, x13, x9, x10)

inst_31855:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x1fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6e9fffff; valaddr_reg:x12; val_offset:95502*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95502*FLEN/8, x13, x9, x10)

inst_31856:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x600000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6ee00000; valaddr_reg:x12; val_offset:95505*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95505*FLEN/8, x13, x9, x10)

inst_31857:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x0fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6e8fffff; valaddr_reg:x12; val_offset:95508*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95508*FLEN/8, x13, x9, x10)

inst_31858:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x700000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6ef00000; valaddr_reg:x12; val_offset:95511*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95511*FLEN/8, x13, x9, x10)

inst_31859:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x07ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6e87ffff; valaddr_reg:x12; val_offset:95514*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95514*FLEN/8, x13, x9, x10)

inst_31860:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x780000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6ef80000; valaddr_reg:x12; val_offset:95517*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95517*FLEN/8, x13, x9, x10)

inst_31861:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x03ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6e83ffff; valaddr_reg:x12; val_offset:95520*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95520*FLEN/8, x13, x9, x10)

inst_31862:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x7c0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6efc0000; valaddr_reg:x12; val_offset:95523*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95523*FLEN/8, x13, x9, x10)

inst_31863:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x01ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6e81ffff; valaddr_reg:x12; val_offset:95526*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95526*FLEN/8, x13, x9, x10)

inst_31864:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x7e0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6efe0000; valaddr_reg:x12; val_offset:95529*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95529*FLEN/8, x13, x9, x10)

inst_31865:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x00ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6e80ffff; valaddr_reg:x12; val_offset:95532*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95532*FLEN/8, x13, x9, x10)

inst_31866:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x7f0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6eff0000; valaddr_reg:x12; val_offset:95535*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95535*FLEN/8, x13, x9, x10)

inst_31867:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x007fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6e807fff; valaddr_reg:x12; val_offset:95538*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95538*FLEN/8, x13, x9, x10)

inst_31868:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x7f8000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6eff8000; valaddr_reg:x12; val_offset:95541*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95541*FLEN/8, x13, x9, x10)

inst_31869:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x003fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6e803fff; valaddr_reg:x12; val_offset:95544*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95544*FLEN/8, x13, x9, x10)

inst_31870:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x7fc000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6effc000; valaddr_reg:x12; val_offset:95547*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95547*FLEN/8, x13, x9, x10)

inst_31871:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x001fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6e801fff; valaddr_reg:x12; val_offset:95550*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95550*FLEN/8, x13, x9, x10)

inst_31872:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x7fe000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6effe000; valaddr_reg:x12; val_offset:95553*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95553*FLEN/8, x13, x9, x10)

inst_31873:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x000fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6e800fff; valaddr_reg:x12; val_offset:95556*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95556*FLEN/8, x13, x9, x10)

inst_31874:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x7ff000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6efff000; valaddr_reg:x12; val_offset:95559*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95559*FLEN/8, x13, x9, x10)

inst_31875:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x0007ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6e8007ff; valaddr_reg:x12; val_offset:95562*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95562*FLEN/8, x13, x9, x10)

inst_31876:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x7ff800 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6efff800; valaddr_reg:x12; val_offset:95565*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95565*FLEN/8, x13, x9, x10)

inst_31877:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x0003ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6e8003ff; valaddr_reg:x12; val_offset:95568*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95568*FLEN/8, x13, x9, x10)

inst_31878:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x7ffc00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6efffc00; valaddr_reg:x12; val_offset:95571*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95571*FLEN/8, x13, x9, x10)

inst_31879:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x0001ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6e8001ff; valaddr_reg:x12; val_offset:95574*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95574*FLEN/8, x13, x9, x10)

inst_31880:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x7ffe00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6efffe00; valaddr_reg:x12; val_offset:95577*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95577*FLEN/8, x13, x9, x10)

inst_31881:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x0000ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6e8000ff; valaddr_reg:x12; val_offset:95580*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95580*FLEN/8, x13, x9, x10)

inst_31882:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x7fff00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6effff00; valaddr_reg:x12; val_offset:95583*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95583*FLEN/8, x13, x9, x10)

inst_31883:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x00007f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6e80007f; valaddr_reg:x12; val_offset:95586*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95586*FLEN/8, x13, x9, x10)

inst_31884:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x7fff80 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6effff80; valaddr_reg:x12; val_offset:95589*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95589*FLEN/8, x13, x9, x10)

inst_31885:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x00003f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6e80003f; valaddr_reg:x12; val_offset:95592*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95592*FLEN/8, x13, x9, x10)

inst_31886:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x7fffc0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6effffc0; valaddr_reg:x12; val_offset:95595*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95595*FLEN/8, x13, x9, x10)

inst_31887:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x00001f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6e80001f; valaddr_reg:x12; val_offset:95598*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95598*FLEN/8, x13, x9, x10)

inst_31888:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x7fffe0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6effffe0; valaddr_reg:x12; val_offset:95601*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95601*FLEN/8, x13, x9, x10)

inst_31889:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x00000f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6e80000f; valaddr_reg:x12; val_offset:95604*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95604*FLEN/8, x13, x9, x10)

inst_31890:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x7ffff0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6efffff0; valaddr_reg:x12; val_offset:95607*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95607*FLEN/8, x13, x9, x10)

inst_31891:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6e800007; valaddr_reg:x12; val_offset:95610*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95610*FLEN/8, x13, x9, x10)

inst_31892:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6efffff8; valaddr_reg:x12; val_offset:95613*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95613*FLEN/8, x13, x9, x10)

inst_31893:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6e800003; valaddr_reg:x12; val_offset:95616*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95616*FLEN/8, x13, x9, x10)

inst_31894:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6efffffc; valaddr_reg:x12; val_offset:95619*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95619*FLEN/8, x13, x9, x10)

inst_31895:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6e800001; valaddr_reg:x12; val_offset:95622*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95622*FLEN/8, x13, x9, x10)

RVTEST_SIGBASE(x9,signature_x9_249)
inst_31896:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xdd and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x6efffffe; valaddr_reg:x12; val_offset:95625*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95625*FLEN/8, x13, x9, x10)

inst_31897:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x7f7ffff8; valaddr_reg:x12; val_offset:95628*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95628*FLEN/8, x13, x9, x10)

inst_31898:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x7f000007; valaddr_reg:x12; val_offset:95631*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95631*FLEN/8, x13, x9, x10)

inst_31899:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x7f7ffffc; valaddr_reg:x12; val_offset:95634*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95634*FLEN/8, x13, x9, x10)

inst_31900:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x7f000003; valaddr_reg:x12; val_offset:95637*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95637*FLEN/8, x13, x9, x10)

inst_31901:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x7f7ffffe; valaddr_reg:x12; val_offset:95640*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95640*FLEN/8, x13, x9, x10)

inst_31902:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x7f000001; valaddr_reg:x12; val_offset:95643*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95643*FLEN/8, x13, x9, x10)

inst_31903:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x36db6d and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x7f36db6d; valaddr_reg:x12; val_offset:95646*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95646*FLEN/8, x13, x9, x10)

inst_31904:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x6db6db and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x7f6db6db; valaddr_reg:x12; val_offset:95649*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95649*FLEN/8, x13, x9, x10)

inst_31905:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x199999 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x7f199999; valaddr_reg:x12; val_offset:95652*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95652*FLEN/8, x13, x9, x10)

inst_31906:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x666666 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x7f666666; valaddr_reg:x12; val_offset:95655*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95655*FLEN/8, x13, x9, x10)

inst_31907:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3bbbbb and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x7f3bbbbb; valaddr_reg:x12; val_offset:95658*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95658*FLEN/8, x13, x9, x10)

inst_31908:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x444444 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x7f444444; valaddr_reg:x12; val_offset:95661*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95661*FLEN/8, x13, x9, x10)

inst_31909:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x249249 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x7f249249; valaddr_reg:x12; val_offset:95664*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95664*FLEN/8, x13, x9, x10)

inst_31910:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x5b6db6 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x7f5b6db6; valaddr_reg:x12; val_offset:95667*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95667*FLEN/8, x13, x9, x10)

inst_31911:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x333333 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x7f333333; valaddr_reg:x12; val_offset:95670*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95670*FLEN/8, x13, x9, x10)

inst_31912:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x0ef815 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x653247 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x4ccccc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f0ef815; op2val:0x3fe53247;
op3val:0x7f4ccccc; valaddr_reg:x12; val_offset:95673*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95673*FLEN/8, x13, x9, x10)

inst_31913:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xde and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x6f7fffff; valaddr_reg:x12; val_offset:95676*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95676*FLEN/8, x13, x9, x10)

inst_31914:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xde and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x6f000000; valaddr_reg:x12; val_offset:95679*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95679*FLEN/8, x13, x9, x10)

inst_31915:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xde and fm3 == 0x3fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x6f3fffff; valaddr_reg:x12; val_offset:95682*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95682*FLEN/8, x13, x9, x10)

inst_31916:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xde and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x6f400000; valaddr_reg:x12; val_offset:95685*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95685*FLEN/8, x13, x9, x10)

inst_31917:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xde and fm3 == 0x1fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x6f1fffff; valaddr_reg:x12; val_offset:95688*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95688*FLEN/8, x13, x9, x10)

inst_31918:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xde and fm3 == 0x600000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x6f600000; valaddr_reg:x12; val_offset:95691*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95691*FLEN/8, x13, x9, x10)

inst_31919:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xde and fm3 == 0x0fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x6f0fffff; valaddr_reg:x12; val_offset:95694*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95694*FLEN/8, x13, x9, x10)

inst_31920:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xde and fm3 == 0x700000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x6f700000; valaddr_reg:x12; val_offset:95697*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95697*FLEN/8, x13, x9, x10)

inst_31921:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xde and fm3 == 0x07ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x6f07ffff; valaddr_reg:x12; val_offset:95700*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95700*FLEN/8, x13, x9, x10)

inst_31922:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xde and fm3 == 0x780000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x6f780000; valaddr_reg:x12; val_offset:95703*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95703*FLEN/8, x13, x9, x10)

inst_31923:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xde and fm3 == 0x03ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x6f03ffff; valaddr_reg:x12; val_offset:95706*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95706*FLEN/8, x13, x9, x10)

inst_31924:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xde and fm3 == 0x7c0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x6f7c0000; valaddr_reg:x12; val_offset:95709*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95709*FLEN/8, x13, x9, x10)

inst_31925:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xde and fm3 == 0x01ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x6f01ffff; valaddr_reg:x12; val_offset:95712*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95712*FLEN/8, x13, x9, x10)

inst_31926:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xde and fm3 == 0x7e0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x6f7e0000; valaddr_reg:x12; val_offset:95715*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95715*FLEN/8, x13, x9, x10)

inst_31927:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xde and fm3 == 0x00ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x6f00ffff; valaddr_reg:x12; val_offset:95718*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95718*FLEN/8, x13, x9, x10)

inst_31928:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xde and fm3 == 0x7f0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x6f7f0000; valaddr_reg:x12; val_offset:95721*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95721*FLEN/8, x13, x9, x10)

inst_31929:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xde and fm3 == 0x007fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x6f007fff; valaddr_reg:x12; val_offset:95724*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95724*FLEN/8, x13, x9, x10)

inst_31930:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xde and fm3 == 0x7f8000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x6f7f8000; valaddr_reg:x12; val_offset:95727*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95727*FLEN/8, x13, x9, x10)

inst_31931:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xde and fm3 == 0x003fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x6f003fff; valaddr_reg:x12; val_offset:95730*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95730*FLEN/8, x13, x9, x10)

inst_31932:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xde and fm3 == 0x7fc000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x6f7fc000; valaddr_reg:x12; val_offset:95733*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95733*FLEN/8, x13, x9, x10)

inst_31933:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xde and fm3 == 0x001fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x6f001fff; valaddr_reg:x12; val_offset:95736*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95736*FLEN/8, x13, x9, x10)

inst_31934:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xde and fm3 == 0x7fe000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x6f7fe000; valaddr_reg:x12; val_offset:95739*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95739*FLEN/8, x13, x9, x10)

inst_31935:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xde and fm3 == 0x000fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x6f000fff; valaddr_reg:x12; val_offset:95742*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95742*FLEN/8, x13, x9, x10)

inst_31936:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xde and fm3 == 0x7ff000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x6f7ff000; valaddr_reg:x12; val_offset:95745*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95745*FLEN/8, x13, x9, x10)

inst_31937:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xde and fm3 == 0x0007ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x6f0007ff; valaddr_reg:x12; val_offset:95748*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95748*FLEN/8, x13, x9, x10)

inst_31938:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xde and fm3 == 0x7ff800 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x6f7ff800; valaddr_reg:x12; val_offset:95751*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95751*FLEN/8, x13, x9, x10)

inst_31939:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xde and fm3 == 0x0003ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x6f0003ff; valaddr_reg:x12; val_offset:95754*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95754*FLEN/8, x13, x9, x10)

inst_31940:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xde and fm3 == 0x7ffc00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x6f7ffc00; valaddr_reg:x12; val_offset:95757*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95757*FLEN/8, x13, x9, x10)

inst_31941:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xde and fm3 == 0x0001ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x6f0001ff; valaddr_reg:x12; val_offset:95760*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95760*FLEN/8, x13, x9, x10)

inst_31942:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xde and fm3 == 0x7ffe00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x6f7ffe00; valaddr_reg:x12; val_offset:95763*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95763*FLEN/8, x13, x9, x10)

inst_31943:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xde and fm3 == 0x0000ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x6f0000ff; valaddr_reg:x12; val_offset:95766*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95766*FLEN/8, x13, x9, x10)

inst_31944:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xde and fm3 == 0x7fff00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x6f7fff00; valaddr_reg:x12; val_offset:95769*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95769*FLEN/8, x13, x9, x10)

inst_31945:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xde and fm3 == 0x00007f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x6f00007f; valaddr_reg:x12; val_offset:95772*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95772*FLEN/8, x13, x9, x10)

inst_31946:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xde and fm3 == 0x7fff80 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x6f7fff80; valaddr_reg:x12; val_offset:95775*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95775*FLEN/8, x13, x9, x10)

inst_31947:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xde and fm3 == 0x00003f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x6f00003f; valaddr_reg:x12; val_offset:95778*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95778*FLEN/8, x13, x9, x10)

inst_31948:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xde and fm3 == 0x7fffc0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x6f7fffc0; valaddr_reg:x12; val_offset:95781*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95781*FLEN/8, x13, x9, x10)

inst_31949:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xde and fm3 == 0x00001f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x6f00001f; valaddr_reg:x12; val_offset:95784*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95784*FLEN/8, x13, x9, x10)

inst_31950:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xde and fm3 == 0x7fffe0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x6f7fffe0; valaddr_reg:x12; val_offset:95787*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95787*FLEN/8, x13, x9, x10)

inst_31951:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xde and fm3 == 0x00000f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x6f00000f; valaddr_reg:x12; val_offset:95790*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95790*FLEN/8, x13, x9, x10)

inst_31952:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xde and fm3 == 0x7ffff0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x6f7ffff0; valaddr_reg:x12; val_offset:95793*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95793*FLEN/8, x13, x9, x10)

inst_31953:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xde and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x6f000007; valaddr_reg:x12; val_offset:95796*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95796*FLEN/8, x13, x9, x10)

inst_31954:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xde and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x6f7ffff8; valaddr_reg:x12; val_offset:95799*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95799*FLEN/8, x13, x9, x10)

inst_31955:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xde and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x6f000003; valaddr_reg:x12; val_offset:95802*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95802*FLEN/8, x13, x9, x10)

inst_31956:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xde and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x6f7ffffc; valaddr_reg:x12; val_offset:95805*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95805*FLEN/8, x13, x9, x10)

inst_31957:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xde and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x6f000001; valaddr_reg:x12; val_offset:95808*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95808*FLEN/8, x13, x9, x10)

inst_31958:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xde and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x6f7ffffe; valaddr_reg:x12; val_offset:95811*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95811*FLEN/8, x13, x9, x10)

inst_31959:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x7f7ffff8; valaddr_reg:x12; val_offset:95814*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95814*FLEN/8, x13, x9, x10)

inst_31960:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x7f000007; valaddr_reg:x12; val_offset:95817*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95817*FLEN/8, x13, x9, x10)

inst_31961:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x7f7ffffc; valaddr_reg:x12; val_offset:95820*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95820*FLEN/8, x13, x9, x10)

inst_31962:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x7f000003; valaddr_reg:x12; val_offset:95823*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95823*FLEN/8, x13, x9, x10)

inst_31963:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x7f7ffffe; valaddr_reg:x12; val_offset:95826*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95826*FLEN/8, x13, x9, x10)

inst_31964:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x7f000001; valaddr_reg:x12; val_offset:95829*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95829*FLEN/8, x13, x9, x10)

inst_31965:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xfe and fm3 == 0x36db6d and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x7f36db6d; valaddr_reg:x12; val_offset:95832*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95832*FLEN/8, x13, x9, x10)

inst_31966:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xfe and fm3 == 0x6db6db and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x7f6db6db; valaddr_reg:x12; val_offset:95835*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95835*FLEN/8, x13, x9, x10)

inst_31967:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xfe and fm3 == 0x199999 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x7f199999; valaddr_reg:x12; val_offset:95838*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95838*FLEN/8, x13, x9, x10)

inst_31968:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xfe and fm3 == 0x666666 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x7f666666; valaddr_reg:x12; val_offset:95841*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95841*FLEN/8, x13, x9, x10)

inst_31969:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3bbbbb and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x7f3bbbbb; valaddr_reg:x12; val_offset:95844*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95844*FLEN/8, x13, x9, x10)

inst_31970:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xfe and fm3 == 0x444444 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x7f444444; valaddr_reg:x12; val_offset:95847*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95847*FLEN/8, x13, x9, x10)

inst_31971:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xfe and fm3 == 0x249249 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x7f249249; valaddr_reg:x12; val_offset:95850*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95850*FLEN/8, x13, x9, x10)

inst_31972:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xfe and fm3 == 0x5b6db6 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x7f5b6db6; valaddr_reg:x12; val_offset:95853*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95853*FLEN/8, x13, x9, x10)

inst_31973:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xfe and fm3 == 0x333333 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x7f333333; valaddr_reg:x12; val_offset:95856*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95856*FLEN/8, x13, x9, x10)

inst_31974:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3d9e1a and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2ccf9a and fs3 == 0 and fe3 == 0xfe and fm3 == 0x4ccccc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f3d9e1a; op2val:0x3faccf9a;
op3val:0x7f4ccccc; valaddr_reg:x12; val_offset:95859*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95859*FLEN/8, x13, x9, x10)

inst_31975:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xdf and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x6fffffff; valaddr_reg:x12; val_offset:95862*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95862*FLEN/8, x13, x9, x10)

inst_31976:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xdf and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x6f800000; valaddr_reg:x12; val_offset:95865*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95865*FLEN/8, x13, x9, x10)

inst_31977:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xdf and fm3 == 0x3fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x6fbfffff; valaddr_reg:x12; val_offset:95868*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95868*FLEN/8, x13, x9, x10)

inst_31978:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xdf and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x6fc00000; valaddr_reg:x12; val_offset:95871*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95871*FLEN/8, x13, x9, x10)

inst_31979:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xdf and fm3 == 0x1fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x6f9fffff; valaddr_reg:x12; val_offset:95874*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95874*FLEN/8, x13, x9, x10)

inst_31980:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xdf and fm3 == 0x600000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x6fe00000; valaddr_reg:x12; val_offset:95877*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95877*FLEN/8, x13, x9, x10)

inst_31981:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xdf and fm3 == 0x0fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x6f8fffff; valaddr_reg:x12; val_offset:95880*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95880*FLEN/8, x13, x9, x10)

inst_31982:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xdf and fm3 == 0x700000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x6ff00000; valaddr_reg:x12; val_offset:95883*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95883*FLEN/8, x13, x9, x10)

inst_31983:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xdf and fm3 == 0x07ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x6f87ffff; valaddr_reg:x12; val_offset:95886*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95886*FLEN/8, x13, x9, x10)

inst_31984:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xdf and fm3 == 0x780000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x6ff80000; valaddr_reg:x12; val_offset:95889*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95889*FLEN/8, x13, x9, x10)

inst_31985:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xdf and fm3 == 0x03ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x6f83ffff; valaddr_reg:x12; val_offset:95892*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95892*FLEN/8, x13, x9, x10)

inst_31986:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xdf and fm3 == 0x7c0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x6ffc0000; valaddr_reg:x12; val_offset:95895*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95895*FLEN/8, x13, x9, x10)

inst_31987:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xdf and fm3 == 0x01ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x6f81ffff; valaddr_reg:x12; val_offset:95898*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95898*FLEN/8, x13, x9, x10)

inst_31988:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xdf and fm3 == 0x7e0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x6ffe0000; valaddr_reg:x12; val_offset:95901*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95901*FLEN/8, x13, x9, x10)

inst_31989:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xdf and fm3 == 0x00ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x6f80ffff; valaddr_reg:x12; val_offset:95904*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95904*FLEN/8, x13, x9, x10)

inst_31990:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xdf and fm3 == 0x7f0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x6fff0000; valaddr_reg:x12; val_offset:95907*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95907*FLEN/8, x13, x9, x10)

inst_31991:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xdf and fm3 == 0x007fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x6f807fff; valaddr_reg:x12; val_offset:95910*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95910*FLEN/8, x13, x9, x10)

inst_31992:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xdf and fm3 == 0x7f8000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x6fff8000; valaddr_reg:x12; val_offset:95913*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95913*FLEN/8, x13, x9, x10)

inst_31993:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xdf and fm3 == 0x003fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x6f803fff; valaddr_reg:x12; val_offset:95916*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95916*FLEN/8, x13, x9, x10)

inst_31994:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xdf and fm3 == 0x7fc000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x6fffc000; valaddr_reg:x12; val_offset:95919*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95919*FLEN/8, x13, x9, x10)

inst_31995:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xdf and fm3 == 0x001fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x6f801fff; valaddr_reg:x12; val_offset:95922*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95922*FLEN/8, x13, x9, x10)

inst_31996:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xdf and fm3 == 0x7fe000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x6fffe000; valaddr_reg:x12; val_offset:95925*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95925*FLEN/8, x13, x9, x10)

inst_31997:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xdf and fm3 == 0x000fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x6f800fff; valaddr_reg:x12; val_offset:95928*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95928*FLEN/8, x13, x9, x10)

inst_31998:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xdf and fm3 == 0x7ff000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x6ffff000; valaddr_reg:x12; val_offset:95931*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95931*FLEN/8, x13, x9, x10)

inst_31999:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xdf and fm3 == 0x0007ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x6f8007ff; valaddr_reg:x12; val_offset:95934*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95934*FLEN/8, x13, x9, x10)

inst_32000:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xdf and fm3 == 0x7ff800 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x6ffff800; valaddr_reg:x12; val_offset:95937*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95937*FLEN/8, x13, x9, x10)

inst_32001:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xdf and fm3 == 0x0003ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x6f8003ff; valaddr_reg:x12; val_offset:95940*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95940*FLEN/8, x13, x9, x10)

inst_32002:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xdf and fm3 == 0x7ffc00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x6ffffc00; valaddr_reg:x12; val_offset:95943*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95943*FLEN/8, x13, x9, x10)

inst_32003:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xdf and fm3 == 0x0001ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x6f8001ff; valaddr_reg:x12; val_offset:95946*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95946*FLEN/8, x13, x9, x10)

inst_32004:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xdf and fm3 == 0x7ffe00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x6ffffe00; valaddr_reg:x12; val_offset:95949*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95949*FLEN/8, x13, x9, x10)

inst_32005:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xdf and fm3 == 0x0000ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x6f8000ff; valaddr_reg:x12; val_offset:95952*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95952*FLEN/8, x13, x9, x10)

inst_32006:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xdf and fm3 == 0x7fff00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x6fffff00; valaddr_reg:x12; val_offset:95955*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95955*FLEN/8, x13, x9, x10)

inst_32007:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xdf and fm3 == 0x00007f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x6f80007f; valaddr_reg:x12; val_offset:95958*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95958*FLEN/8, x13, x9, x10)

inst_32008:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xdf and fm3 == 0x7fff80 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x6fffff80; valaddr_reg:x12; val_offset:95961*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95961*FLEN/8, x13, x9, x10)

inst_32009:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xdf and fm3 == 0x00003f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x6f80003f; valaddr_reg:x12; val_offset:95964*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95964*FLEN/8, x13, x9, x10)

inst_32010:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xdf and fm3 == 0x7fffc0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x6fffffc0; valaddr_reg:x12; val_offset:95967*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95967*FLEN/8, x13, x9, x10)

inst_32011:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xdf and fm3 == 0x00001f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x6f80001f; valaddr_reg:x12; val_offset:95970*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95970*FLEN/8, x13, x9, x10)

inst_32012:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xdf and fm3 == 0x7fffe0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x6fffffe0; valaddr_reg:x12; val_offset:95973*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95973*FLEN/8, x13, x9, x10)

inst_32013:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xdf and fm3 == 0x00000f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x6f80000f; valaddr_reg:x12; val_offset:95976*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95976*FLEN/8, x13, x9, x10)

inst_32014:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xdf and fm3 == 0x7ffff0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x6ffffff0; valaddr_reg:x12; val_offset:95979*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95979*FLEN/8, x13, x9, x10)

inst_32015:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xdf and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x6f800007; valaddr_reg:x12; val_offset:95982*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95982*FLEN/8, x13, x9, x10)

inst_32016:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xdf and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x6ffffff8; valaddr_reg:x12; val_offset:95985*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95985*FLEN/8, x13, x9, x10)

inst_32017:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xdf and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x6f800003; valaddr_reg:x12; val_offset:95988*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95988*FLEN/8, x13, x9, x10)

inst_32018:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xdf and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x6ffffffc; valaddr_reg:x12; val_offset:95991*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95991*FLEN/8, x13, x9, x10)

inst_32019:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xdf and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x6f800001; valaddr_reg:x12; val_offset:95994*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95994*FLEN/8, x13, x9, x10)

inst_32020:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xdf and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x6ffffffe; valaddr_reg:x12; val_offset:95997*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 95997*FLEN/8, x13, x9, x10)

inst_32021:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x7f7ffff8; valaddr_reg:x12; val_offset:96000*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96000*FLEN/8, x13, x9, x10)

inst_32022:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x7f000007; valaddr_reg:x12; val_offset:96003*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96003*FLEN/8, x13, x9, x10)

inst_32023:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x7f7ffffc; valaddr_reg:x12; val_offset:96006*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96006*FLEN/8, x13, x9, x10)

RVTEST_SIGBASE(x9,signature_x9_250)
inst_32024:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x7f000003; valaddr_reg:x12; val_offset:96009*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96009*FLEN/8, x13, x9, x10)

inst_32025:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x7f7ffffe; valaddr_reg:x12; val_offset:96012*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96012*FLEN/8, x13, x9, x10)

inst_32026:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x7f000001; valaddr_reg:x12; val_offset:96015*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96015*FLEN/8, x13, x9, x10)

inst_32027:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xfe and fm3 == 0x36db6d and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x7f36db6d; valaddr_reg:x12; val_offset:96018*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96018*FLEN/8, x13, x9, x10)

inst_32028:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xfe and fm3 == 0x6db6db and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x7f6db6db; valaddr_reg:x12; val_offset:96021*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96021*FLEN/8, x13, x9, x10)

inst_32029:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xfe and fm3 == 0x199999 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x7f199999; valaddr_reg:x12; val_offset:96024*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96024*FLEN/8, x13, x9, x10)

inst_32030:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xfe and fm3 == 0x666666 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x7f666666; valaddr_reg:x12; val_offset:96027*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96027*FLEN/8, x13, x9, x10)

inst_32031:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3bbbbb and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x7f3bbbbb; valaddr_reg:x12; val_offset:96030*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96030*FLEN/8, x13, x9, x10)

inst_32032:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xfe and fm3 == 0x444444 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x7f444444; valaddr_reg:x12; val_offset:96033*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96033*FLEN/8, x13, x9, x10)

inst_32033:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xfe and fm3 == 0x249249 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x7f249249; valaddr_reg:x12; val_offset:96036*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96036*FLEN/8, x13, x9, x10)

inst_32034:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xfe and fm3 == 0x5b6db6 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x7f5b6db6; valaddr_reg:x12; val_offset:96039*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96039*FLEN/8, x13, x9, x10)

inst_32035:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xfe and fm3 == 0x333333 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x7f333333; valaddr_reg:x12; val_offset:96042*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96042*FLEN/8, x13, x9, x10)

inst_32036:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x6a7f9d and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0bbc8b and fs3 == 0 and fe3 == 0xfe and fm3 == 0x4ccccc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e6a7f9d; op2val:0x408bbc8b;
op3val:0x7f4ccccc; valaddr_reg:x12; val_offset:96045*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96045*FLEN/8, x13, x9, x10)

inst_32037:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xe0 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x707fffff; valaddr_reg:x12; val_offset:96048*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96048*FLEN/8, x13, x9, x10)

inst_32038:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xe0 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x70000000; valaddr_reg:x12; val_offset:96051*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96051*FLEN/8, x13, x9, x10)

inst_32039:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xe0 and fm3 == 0x3fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x703fffff; valaddr_reg:x12; val_offset:96054*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96054*FLEN/8, x13, x9, x10)

inst_32040:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xe0 and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x70400000; valaddr_reg:x12; val_offset:96057*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96057*FLEN/8, x13, x9, x10)

inst_32041:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xe0 and fm3 == 0x1fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x701fffff; valaddr_reg:x12; val_offset:96060*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96060*FLEN/8, x13, x9, x10)

inst_32042:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xe0 and fm3 == 0x600000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x70600000; valaddr_reg:x12; val_offset:96063*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96063*FLEN/8, x13, x9, x10)

inst_32043:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xe0 and fm3 == 0x0fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x700fffff; valaddr_reg:x12; val_offset:96066*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96066*FLEN/8, x13, x9, x10)

inst_32044:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xe0 and fm3 == 0x700000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x70700000; valaddr_reg:x12; val_offset:96069*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96069*FLEN/8, x13, x9, x10)

inst_32045:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xe0 and fm3 == 0x07ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x7007ffff; valaddr_reg:x12; val_offset:96072*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96072*FLEN/8, x13, x9, x10)

inst_32046:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xe0 and fm3 == 0x780000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x70780000; valaddr_reg:x12; val_offset:96075*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96075*FLEN/8, x13, x9, x10)

inst_32047:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xe0 and fm3 == 0x03ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x7003ffff; valaddr_reg:x12; val_offset:96078*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96078*FLEN/8, x13, x9, x10)

inst_32048:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xe0 and fm3 == 0x7c0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x707c0000; valaddr_reg:x12; val_offset:96081*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96081*FLEN/8, x13, x9, x10)

inst_32049:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xe0 and fm3 == 0x01ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x7001ffff; valaddr_reg:x12; val_offset:96084*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96084*FLEN/8, x13, x9, x10)

inst_32050:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xe0 and fm3 == 0x7e0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x707e0000; valaddr_reg:x12; val_offset:96087*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96087*FLEN/8, x13, x9, x10)

inst_32051:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xe0 and fm3 == 0x00ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x7000ffff; valaddr_reg:x12; val_offset:96090*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96090*FLEN/8, x13, x9, x10)

inst_32052:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xe0 and fm3 == 0x7f0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x707f0000; valaddr_reg:x12; val_offset:96093*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96093*FLEN/8, x13, x9, x10)

inst_32053:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xe0 and fm3 == 0x007fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x70007fff; valaddr_reg:x12; val_offset:96096*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96096*FLEN/8, x13, x9, x10)

inst_32054:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xe0 and fm3 == 0x7f8000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x707f8000; valaddr_reg:x12; val_offset:96099*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96099*FLEN/8, x13, x9, x10)

inst_32055:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xe0 and fm3 == 0x003fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x70003fff; valaddr_reg:x12; val_offset:96102*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96102*FLEN/8, x13, x9, x10)

inst_32056:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xe0 and fm3 == 0x7fc000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x707fc000; valaddr_reg:x12; val_offset:96105*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96105*FLEN/8, x13, x9, x10)

inst_32057:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xe0 and fm3 == 0x001fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x70001fff; valaddr_reg:x12; val_offset:96108*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96108*FLEN/8, x13, x9, x10)

inst_32058:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xe0 and fm3 == 0x7fe000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x707fe000; valaddr_reg:x12; val_offset:96111*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96111*FLEN/8, x13, x9, x10)

inst_32059:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xe0 and fm3 == 0x000fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x70000fff; valaddr_reg:x12; val_offset:96114*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96114*FLEN/8, x13, x9, x10)

inst_32060:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xe0 and fm3 == 0x7ff000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x707ff000; valaddr_reg:x12; val_offset:96117*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96117*FLEN/8, x13, x9, x10)

inst_32061:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xe0 and fm3 == 0x0007ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x700007ff; valaddr_reg:x12; val_offset:96120*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96120*FLEN/8, x13, x9, x10)

inst_32062:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xe0 and fm3 == 0x7ff800 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x707ff800; valaddr_reg:x12; val_offset:96123*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96123*FLEN/8, x13, x9, x10)

inst_32063:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xe0 and fm3 == 0x0003ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x700003ff; valaddr_reg:x12; val_offset:96126*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96126*FLEN/8, x13, x9, x10)

inst_32064:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xe0 and fm3 == 0x7ffc00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x707ffc00; valaddr_reg:x12; val_offset:96129*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96129*FLEN/8, x13, x9, x10)

inst_32065:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xe0 and fm3 == 0x0001ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x700001ff; valaddr_reg:x12; val_offset:96132*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96132*FLEN/8, x13, x9, x10)

inst_32066:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xe0 and fm3 == 0x7ffe00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x707ffe00; valaddr_reg:x12; val_offset:96135*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96135*FLEN/8, x13, x9, x10)

inst_32067:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xe0 and fm3 == 0x0000ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x700000ff; valaddr_reg:x12; val_offset:96138*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96138*FLEN/8, x13, x9, x10)

inst_32068:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xe0 and fm3 == 0x7fff00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x707fff00; valaddr_reg:x12; val_offset:96141*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96141*FLEN/8, x13, x9, x10)

inst_32069:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xe0 and fm3 == 0x00007f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x7000007f; valaddr_reg:x12; val_offset:96144*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96144*FLEN/8, x13, x9, x10)

inst_32070:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xe0 and fm3 == 0x7fff80 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x707fff80; valaddr_reg:x12; val_offset:96147*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96147*FLEN/8, x13, x9, x10)

inst_32071:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xe0 and fm3 == 0x00003f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x7000003f; valaddr_reg:x12; val_offset:96150*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96150*FLEN/8, x13, x9, x10)

inst_32072:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xe0 and fm3 == 0x7fffc0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x707fffc0; valaddr_reg:x12; val_offset:96153*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96153*FLEN/8, x13, x9, x10)

inst_32073:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xe0 and fm3 == 0x00001f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x7000001f; valaddr_reg:x12; val_offset:96156*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96156*FLEN/8, x13, x9, x10)

inst_32074:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xe0 and fm3 == 0x7fffe0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x707fffe0; valaddr_reg:x12; val_offset:96159*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96159*FLEN/8, x13, x9, x10)

inst_32075:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xe0 and fm3 == 0x00000f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x7000000f; valaddr_reg:x12; val_offset:96162*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96162*FLEN/8, x13, x9, x10)

inst_32076:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xe0 and fm3 == 0x7ffff0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x707ffff0; valaddr_reg:x12; val_offset:96165*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96165*FLEN/8, x13, x9, x10)

inst_32077:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xe0 and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x70000007; valaddr_reg:x12; val_offset:96168*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96168*FLEN/8, x13, x9, x10)

inst_32078:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xe0 and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x707ffff8; valaddr_reg:x12; val_offset:96171*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96171*FLEN/8, x13, x9, x10)

inst_32079:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xe0 and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x70000003; valaddr_reg:x12; val_offset:96174*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96174*FLEN/8, x13, x9, x10)

inst_32080:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xe0 and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x707ffffc; valaddr_reg:x12; val_offset:96177*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96177*FLEN/8, x13, x9, x10)

inst_32081:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xe0 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x70000001; valaddr_reg:x12; val_offset:96180*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96180*FLEN/8, x13, x9, x10)

inst_32082:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xe0 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x707ffffe; valaddr_reg:x12; val_offset:96183*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96183*FLEN/8, x13, x9, x10)

inst_32083:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x7f7ffff8; valaddr_reg:x12; val_offset:96186*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96186*FLEN/8, x13, x9, x10)

inst_32084:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x7f000007; valaddr_reg:x12; val_offset:96189*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96189*FLEN/8, x13, x9, x10)

inst_32085:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x7f7ffffc; valaddr_reg:x12; val_offset:96192*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96192*FLEN/8, x13, x9, x10)

inst_32086:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x7f000003; valaddr_reg:x12; val_offset:96195*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96195*FLEN/8, x13, x9, x10)

inst_32087:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x7f7ffffe; valaddr_reg:x12; val_offset:96198*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96198*FLEN/8, x13, x9, x10)

inst_32088:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x7f000001; valaddr_reg:x12; val_offset:96201*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96201*FLEN/8, x13, x9, x10)

inst_32089:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x36db6d and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x7f36db6d; valaddr_reg:x12; val_offset:96204*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96204*FLEN/8, x13, x9, x10)

inst_32090:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x6db6db and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x7f6db6db; valaddr_reg:x12; val_offset:96207*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96207*FLEN/8, x13, x9, x10)

inst_32091:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x199999 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x7f199999; valaddr_reg:x12; val_offset:96210*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96210*FLEN/8, x13, x9, x10)

inst_32092:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x666666 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x7f666666; valaddr_reg:x12; val_offset:96213*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96213*FLEN/8, x13, x9, x10)

inst_32093:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3bbbbb and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x7f3bbbbb; valaddr_reg:x12; val_offset:96216*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96216*FLEN/8, x13, x9, x10)

inst_32094:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x444444 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x7f444444; valaddr_reg:x12; val_offset:96219*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96219*FLEN/8, x13, x9, x10)

inst_32095:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x249249 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x7f249249; valaddr_reg:x12; val_offset:96222*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96222*FLEN/8, x13, x9, x10)

inst_32096:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x5b6db6 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x7f5b6db6; valaddr_reg:x12; val_offset:96225*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96225*FLEN/8, x13, x9, x10)

inst_32097:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x333333 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x7f333333; valaddr_reg:x12; val_offset:96228*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96228*FLEN/8, x13, x9, x10)

inst_32098:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x02ccdc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x7a84f7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x4ccccc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e02ccdc; op2val:0x40fa84f7;
op3val:0x7f4ccccc; valaddr_reg:x12; val_offset:96231*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96231*FLEN/8, x13, x9, x10)

inst_32099:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xe1 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x70ffffff; valaddr_reg:x12; val_offset:96234*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96234*FLEN/8, x13, x9, x10)

inst_32100:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xe1 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x70800000; valaddr_reg:x12; val_offset:96237*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96237*FLEN/8, x13, x9, x10)

inst_32101:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xe1 and fm3 == 0x3fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x70bfffff; valaddr_reg:x12; val_offset:96240*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96240*FLEN/8, x13, x9, x10)

inst_32102:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xe1 and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x70c00000; valaddr_reg:x12; val_offset:96243*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96243*FLEN/8, x13, x9, x10)

inst_32103:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xe1 and fm3 == 0x1fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x709fffff; valaddr_reg:x12; val_offset:96246*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96246*FLEN/8, x13, x9, x10)

inst_32104:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xe1 and fm3 == 0x600000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x70e00000; valaddr_reg:x12; val_offset:96249*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96249*FLEN/8, x13, x9, x10)

inst_32105:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xe1 and fm3 == 0x0fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x708fffff; valaddr_reg:x12; val_offset:96252*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96252*FLEN/8, x13, x9, x10)

inst_32106:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xe1 and fm3 == 0x700000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x70f00000; valaddr_reg:x12; val_offset:96255*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96255*FLEN/8, x13, x9, x10)

inst_32107:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xe1 and fm3 == 0x07ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x7087ffff; valaddr_reg:x12; val_offset:96258*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96258*FLEN/8, x13, x9, x10)

inst_32108:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xe1 and fm3 == 0x780000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x70f80000; valaddr_reg:x12; val_offset:96261*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96261*FLEN/8, x13, x9, x10)

inst_32109:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xe1 and fm3 == 0x03ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x7083ffff; valaddr_reg:x12; val_offset:96264*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96264*FLEN/8, x13, x9, x10)

inst_32110:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xe1 and fm3 == 0x7c0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x70fc0000; valaddr_reg:x12; val_offset:96267*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96267*FLEN/8, x13, x9, x10)

inst_32111:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xe1 and fm3 == 0x01ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x7081ffff; valaddr_reg:x12; val_offset:96270*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96270*FLEN/8, x13, x9, x10)

inst_32112:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xe1 and fm3 == 0x7e0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x70fe0000; valaddr_reg:x12; val_offset:96273*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96273*FLEN/8, x13, x9, x10)

inst_32113:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xe1 and fm3 == 0x00ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x7080ffff; valaddr_reg:x12; val_offset:96276*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96276*FLEN/8, x13, x9, x10)

inst_32114:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xe1 and fm3 == 0x7f0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x70ff0000; valaddr_reg:x12; val_offset:96279*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96279*FLEN/8, x13, x9, x10)

inst_32115:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xe1 and fm3 == 0x007fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x70807fff; valaddr_reg:x12; val_offset:96282*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96282*FLEN/8, x13, x9, x10)

inst_32116:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xe1 and fm3 == 0x7f8000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x70ff8000; valaddr_reg:x12; val_offset:96285*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96285*FLEN/8, x13, x9, x10)

inst_32117:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xe1 and fm3 == 0x003fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x70803fff; valaddr_reg:x12; val_offset:96288*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96288*FLEN/8, x13, x9, x10)

inst_32118:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xe1 and fm3 == 0x7fc000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x70ffc000; valaddr_reg:x12; val_offset:96291*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96291*FLEN/8, x13, x9, x10)

inst_32119:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xe1 and fm3 == 0x001fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x70801fff; valaddr_reg:x12; val_offset:96294*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96294*FLEN/8, x13, x9, x10)

inst_32120:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xe1 and fm3 == 0x7fe000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x70ffe000; valaddr_reg:x12; val_offset:96297*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96297*FLEN/8, x13, x9, x10)

inst_32121:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xe1 and fm3 == 0x000fff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x70800fff; valaddr_reg:x12; val_offset:96300*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96300*FLEN/8, x13, x9, x10)

inst_32122:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xe1 and fm3 == 0x7ff000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x70fff000; valaddr_reg:x12; val_offset:96303*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96303*FLEN/8, x13, x9, x10)

inst_32123:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xe1 and fm3 == 0x0007ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x708007ff; valaddr_reg:x12; val_offset:96306*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96306*FLEN/8, x13, x9, x10)

inst_32124:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xe1 and fm3 == 0x7ff800 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x70fff800; valaddr_reg:x12; val_offset:96309*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96309*FLEN/8, x13, x9, x10)

inst_32125:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xe1 and fm3 == 0x0003ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x708003ff; valaddr_reg:x12; val_offset:96312*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96312*FLEN/8, x13, x9, x10)

inst_32126:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xe1 and fm3 == 0x7ffc00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x70fffc00; valaddr_reg:x12; val_offset:96315*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96315*FLEN/8, x13, x9, x10)

inst_32127:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xe1 and fm3 == 0x0001ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x708001ff; valaddr_reg:x12; val_offset:96318*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96318*FLEN/8, x13, x9, x10)

inst_32128:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xe1 and fm3 == 0x7ffe00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x70fffe00; valaddr_reg:x12; val_offset:96321*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96321*FLEN/8, x13, x9, x10)

inst_32129:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xe1 and fm3 == 0x0000ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x708000ff; valaddr_reg:x12; val_offset:96324*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96324*FLEN/8, x13, x9, x10)

inst_32130:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xe1 and fm3 == 0x7fff00 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x70ffff00; valaddr_reg:x12; val_offset:96327*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96327*FLEN/8, x13, x9, x10)

inst_32131:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xe1 and fm3 == 0x00007f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x7080007f; valaddr_reg:x12; val_offset:96330*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96330*FLEN/8, x13, x9, x10)

inst_32132:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xe1 and fm3 == 0x7fff80 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x70ffff80; valaddr_reg:x12; val_offset:96333*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96333*FLEN/8, x13, x9, x10)

inst_32133:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xe1 and fm3 == 0x00003f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x7080003f; valaddr_reg:x12; val_offset:96336*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96336*FLEN/8, x13, x9, x10)

inst_32134:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xe1 and fm3 == 0x7fffc0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x70ffffc0; valaddr_reg:x12; val_offset:96339*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96339*FLEN/8, x13, x9, x10)

inst_32135:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xe1 and fm3 == 0x00001f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x7080001f; valaddr_reg:x12; val_offset:96342*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96342*FLEN/8, x13, x9, x10)

inst_32136:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xe1 and fm3 == 0x7fffe0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x70ffffe0; valaddr_reg:x12; val_offset:96345*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96345*FLEN/8, x13, x9, x10)

inst_32137:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xe1 and fm3 == 0x00000f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x7080000f; valaddr_reg:x12; val_offset:96348*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96348*FLEN/8, x13, x9, x10)

inst_32138:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xe1 and fm3 == 0x7ffff0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x70fffff0; valaddr_reg:x12; val_offset:96351*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96351*FLEN/8, x13, x9, x10)

inst_32139:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xe1 and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x70800007; valaddr_reg:x12; val_offset:96354*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96354*FLEN/8, x13, x9, x10)

inst_32140:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xe1 and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x70fffff8; valaddr_reg:x12; val_offset:96357*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96357*FLEN/8, x13, x9, x10)

inst_32141:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xe1 and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x70800003; valaddr_reg:x12; val_offset:96360*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96360*FLEN/8, x13, x9, x10)

inst_32142:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xe1 and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x70fffffc; valaddr_reg:x12; val_offset:96363*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96363*FLEN/8, x13, x9, x10)

inst_32143:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xe1 and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x70800001; valaddr_reg:x12; val_offset:96366*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96366*FLEN/8, x13, x9, x10)

inst_32144:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xe1 and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x70fffffe; valaddr_reg:x12; val_offset:96369*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96369*FLEN/8, x13, x9, x10)

inst_32145:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffff8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x7f7ffff8; valaddr_reg:x12; val_offset:96372*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96372*FLEN/8, x13, x9, x10)

inst_32146:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000007 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x7f000007; valaddr_reg:x12; val_offset:96375*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96375*FLEN/8, x13, x9, x10)

inst_32147:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x7f7ffffc; valaddr_reg:x12; val_offset:96378*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96378*FLEN/8, x13, x9, x10)

inst_32148:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000003 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x7f000003; valaddr_reg:x12; val_offset:96381*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96381*FLEN/8, x13, x9, x10)

inst_32149:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffe and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x7f7ffffe; valaddr_reg:x12; val_offset:96384*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96384*FLEN/8, x13, x9, x10)

inst_32150:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000001 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x7f000001; valaddr_reg:x12; val_offset:96387*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96387*FLEN/8, x13, x9, x10)

inst_32151:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xfe and fm3 == 0x36db6d and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x7f36db6d; valaddr_reg:x12; val_offset:96390*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96390*FLEN/8, x13, x9, x10)

RVTEST_SIGBASE(x9,signature_x9_251)
inst_32152:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xfe and fm3 == 0x6db6db and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x7f6db6db; valaddr_reg:x12; val_offset:96393*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96393*FLEN/8, x13, x9, x10)

inst_32153:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xfe and fm3 == 0x199999 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x7f199999; valaddr_reg:x12; val_offset:96396*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96396*FLEN/8, x13, x9, x10)

inst_32154:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xfe and fm3 == 0x666666 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x7f666666; valaddr_reg:x12; val_offset:96399*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96399*FLEN/8, x13, x9, x10)

inst_32155:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3bbbbb and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x7f3bbbbb; valaddr_reg:x12; val_offset:96402*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96402*FLEN/8, x13, x9, x10)

inst_32156:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xfe and fm3 == 0x444444 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x7f444444; valaddr_reg:x12; val_offset:96405*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96405*FLEN/8, x13, x9, x10)

inst_32157:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xfe and fm3 == 0x249249 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x7f249249; valaddr_reg:x12; val_offset:96408*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96408*FLEN/8, x13, x9, x10)

inst_32158:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xfe and fm3 == 0x5b6db6 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x7f5b6db6; valaddr_reg:x12; val_offset:96411*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96411*FLEN/8, x13, x9, x10)

inst_32159:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xfe and fm3 == 0x333333 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x7f333333; valaddr_reg:x12; val_offset:96414*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96414*FLEN/8, x13, x9, x10)

inst_32160:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x6e17ca and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09a07e and fs3 == 0 and fe3 == 0xfe and fm3 == 0x4ccccc and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7eee17ca; op2val:0x4009a07e;
op3val:0x7f4ccccc; valaddr_reg:x12; val_offset:96417*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96417*FLEN/8, x13, x9, x10)

inst_32161:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4be31d and fs2 == 0 and fe2 == 0x80 and fm2 == 0x20b761 and fs3 == 0 and fe3 == 0xe2 and fm3 == 0x7fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ecbe31d; op2val:0x4020b761;
op3val:0x717fffff; valaddr_reg:x12; val_offset:96420*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96420*FLEN/8, x13, x9, x10)

inst_32162:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4be31d and fs2 == 0 and fe2 == 0x80 and fm2 == 0x20b761 and fs3 == 0 and fe3 == 0xe2 and fm3 == 0x000000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ecbe31d; op2val:0x4020b761;
op3val:0x71000000; valaddr_reg:x12; val_offset:96423*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96423*FLEN/8, x13, x9, x10)

inst_32163:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4be31d and fs2 == 0 and fe2 == 0x80 and fm2 == 0x20b761 and fs3 == 0 and fe3 == 0xe2 and fm3 == 0x3fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ecbe31d; op2val:0x4020b761;
op3val:0x713fffff; valaddr_reg:x12; val_offset:96426*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96426*FLEN/8, x13, x9, x10)

inst_32164:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4be31d and fs2 == 0 and fe2 == 0x80 and fm2 == 0x20b761 and fs3 == 0 and fe3 == 0xe2 and fm3 == 0x400000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ecbe31d; op2val:0x4020b761;
op3val:0x71400000; valaddr_reg:x12; val_offset:96429*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96429*FLEN/8, x13, x9, x10)

inst_32165:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4be31d and fs2 == 0 and fe2 == 0x80 and fm2 == 0x20b761 and fs3 == 0 and fe3 == 0xe2 and fm3 == 0x1fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ecbe31d; op2val:0x4020b761;
op3val:0x711fffff; valaddr_reg:x12; val_offset:96432*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96432*FLEN/8, x13, x9, x10)

inst_32166:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4be31d and fs2 == 0 and fe2 == 0x80 and fm2 == 0x20b761 and fs3 == 0 and fe3 == 0xe2 and fm3 == 0x600000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ecbe31d; op2val:0x4020b761;
op3val:0x71600000; valaddr_reg:x12; val_offset:96435*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96435*FLEN/8, x13, x9, x10)

inst_32167:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4be31d and fs2 == 0 and fe2 == 0x80 and fm2 == 0x20b761 and fs3 == 0 and fe3 == 0xe2 and fm3 == 0x0fffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ecbe31d; op2val:0x4020b761;
op3val:0x710fffff; valaddr_reg:x12; val_offset:96438*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96438*FLEN/8, x13, x9, x10)

inst_32168:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4be31d and fs2 == 0 and fe2 == 0x80 and fm2 == 0x20b761 and fs3 == 0 and fe3 == 0xe2 and fm3 == 0x700000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ecbe31d; op2val:0x4020b761;
op3val:0x71700000; valaddr_reg:x12; val_offset:96441*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96441*FLEN/8, x13, x9, x10)

inst_32169:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4be31d and fs2 == 0 and fe2 == 0x80 and fm2 == 0x20b761 and fs3 == 0 and fe3 == 0xe2 and fm3 == 0x07ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ecbe31d; op2val:0x4020b761;
op3val:0x7107ffff; valaddr_reg:x12; val_offset:96444*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96444*FLEN/8, x13, x9, x10)

inst_32170:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4be31d and fs2 == 0 and fe2 == 0x80 and fm2 == 0x20b761 and fs3 == 0 and fe3 == 0xe2 and fm3 == 0x780000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ecbe31d; op2val:0x4020b761;
op3val:0x71780000; valaddr_reg:x12; val_offset:96447*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96447*FLEN/8, x13, x9, x10)

inst_32171:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4be31d and fs2 == 0 and fe2 == 0x80 and fm2 == 0x20b761 and fs3 == 0 and fe3 == 0xe2 and fm3 == 0x03ffff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ecbe31d; op2val:0x4020b761;
op3val:0x7103ffff; valaddr_reg:x12; val_offset:96450*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96450*FLEN/8, x13, x9, x10)

inst_32172:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x4be31d and fs2 == 0 and fe2 == 0x80 and fm2 == 0x20b761 and fs3 == 0 and fe3 == 0xe2 and fm3 == 0x7c0000 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmadd.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ecbe31d; op2val:0x4020b761;
op3val:0x717c0000; valaddr_reg:x12; val_offset:96453*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, x31, x30, x29, x28, dyn, 0, 0, x12, 96453*FLEN/8, x13, x9, x10)

#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(1069650647,32,FLEN)
NAN_BOXED(2135180356,32,FLEN)
NAN_BOXED(2133411710,32,FLEN)
NAN_BOXED(1069650647,32,FLEN)
NAN_BOXED(2133103177,32,FLEN)
NAN_BOXED(2133411710,32,FLEN)
NAN_BOXED(1069650647,32,FLEN)
NAN_BOXED(2136698294,32,FLEN)
NAN_BOXED(2133411710,32,FLEN)
NAN_BOXED(1069650647,32,FLEN)
NAN_BOXED(2134061875,32,FLEN)
NAN_BOXED(2133411710,32,FLEN)
NAN_BOXED(1069650647,32,FLEN)
NAN_BOXED(2135739596,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(1811939327,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(1803550720,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(1807745023,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(1807745024,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(1805647871,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(1809842176,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(1804599295,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(1810890752,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(1804075007,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(1811415040,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(1803812863,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(1811677184,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(1803681791,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(1811808256,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(1803616255,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(1811873792,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(1803583487,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(1811906560,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(1803567103,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(1811922944,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(1803558911,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(1811931136,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(1803554815,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(1811935232,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(1803552767,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(1811937280,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(1803551743,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(1811938304,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(1803551231,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(1811938816,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(1803550975,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(1811939072,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(1803550847,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(1811939200,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(1803550783,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(1811939264,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(1803550751,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(1811939296,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(1803550735,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(1811939312,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(1803550727,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(1811939320,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(1803550723,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(1811939324,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(1803550721,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(1811939326,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(2139095032,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(2130706439,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(2139095036,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(2130706435,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(2139095038,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(2130706433,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(2134301549,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(2137896667,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(2132384153,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(2137417318,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(2134621115,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(2135180356,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(2133103177,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(2136698294,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(2134061875,32,FLEN)
NAN_BOXED(2132754358,32,FLEN)
NAN_BOXED(1070449686,32,FLEN)
NAN_BOXED(2135739596,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(1820327935,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(1811939328,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(1816133631,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(1816133632,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(1814036479,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(1818230784,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(1812987903,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(1819279360,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(1812463615,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(1819803648,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(1812201471,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(1820065792,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(1812070399,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(1820196864,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(1812004863,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(1820262400,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(1811972095,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(1820295168,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(1811955711,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(1820311552,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(1811947519,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(1820319744,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(1811943423,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(1820323840,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(1811941375,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(1820325888,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(1811940351,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(1820326912,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(1811939839,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(1820327424,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(1811939583,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(1820327680,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(1811939455,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(1820327808,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(1811939391,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(1820327872,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(1811939359,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(1820327904,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(1811939343,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(1820327920,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(1811939335,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(1820327928,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(1811939331,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(1820327932,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(1811939329,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(1820327934,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(2139095032,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(2130706439,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(2139095036,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(2130706435,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(2139095038,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(2130706433,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(2134301549,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(2137896667,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(2132384153,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(2137417318,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(2134621115,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(2135180356,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(2133103177,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(2136698294,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(2134061875,32,FLEN)
NAN_BOXED(2126787950,32,FLEN)
NAN_BOXED(1076298109,32,FLEN)
NAN_BOXED(2135739596,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(1828716543,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(1820327936,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(1824522239,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(1824522240,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(1822425087,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(1826619392,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(1821376511,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(1827667968,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(1820852223,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(1828192256,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(1820590079,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(1828454400,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(1820459007,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(1828585472,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(1820393471,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(1828651008,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(1820360703,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(1828683776,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(1820344319,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(1828700160,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(1820336127,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(1828708352,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(1820332031,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(1828712448,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(1820329983,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(1828714496,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(1820328959,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(1828715520,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(1820328447,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(1828716032,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(1820328191,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(1828716288,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(1820328063,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(1828716416,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(1820327999,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(1828716480,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(1820327967,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(1828716512,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(1820327951,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(1828716528,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(1820327943,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(1828716536,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(1820327939,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(1828716540,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(1820327937,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(1828716542,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(2139095032,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(2130706439,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(2139095036,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(2130706435,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(2139095038,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(2130706433,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(2134301549,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(2137896667,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(2132384153,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(2137417318,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(2134621115,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(2135180356,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(2133103177,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(2136698294,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(2134061875,32,FLEN)
NAN_BOXED(2134737385,32,FLEN)
NAN_BOXED(1068296527,32,FLEN)
NAN_BOXED(2135739596,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(1837105151,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(1828716544,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(1832910847,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(1832910848,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(1830813695,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(1835008000,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(1829765119,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(1836056576,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(1829240831,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(1836580864,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(1828978687,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(1836843008,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(1828847615,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(1836974080,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(1828782079,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(1837039616,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(1828749311,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(1837072384,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(1828732927,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(1837088768,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(1828724735,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(1837096960,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(1828720639,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(1837101056,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(1828718591,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(1837103104,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(1828717567,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(1837104128,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(1828717055,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(1837104640,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(1828716799,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(1837104896,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(1828716671,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(1837105024,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(1828716607,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(1837105088,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(1828716575,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(1837105120,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(1828716559,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(1837105136,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(1828716551,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(1837105144,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(1828716547,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(1837105148,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(1828716545,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(1837105150,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(2139095032,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(2130706439,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(2139095036,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(2130706435,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(2139095038,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(2130706433,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(2134301549,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(2137896667,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(2132384153,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(2137417318,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(2134621115,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(2135180356,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(2133103177,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(2136698294,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(2134061875,32,FLEN)
NAN_BOXED(2125545281,32,FLEN)
NAN_BOXED(1077468977,32,FLEN)
NAN_BOXED(2135739596,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(1845493759,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(1837105152,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(1841299455,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(1841299456,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(1839202303,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(1843396608,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(1838153727,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(1844445184,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(1837629439,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(1844969472,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(1837367295,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(1845231616,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(1837236223,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(1845362688,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(1837170687,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(1845428224,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(1837137919,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(1845460992,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(1837121535,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(1845477376,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(1837113343,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(1845485568,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(1837109247,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(1845489664,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(1837107199,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(1845491712,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(1837106175,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(1845492736,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(1837105663,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(1845493248,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(1837105407,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(1845493504,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(1837105279,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(1845493632,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(1837105215,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(1845493696,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(1837105183,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(1845493728,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(1837105167,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(1845493744,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(1837105159,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(1845493752,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(1837105155,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(1845493756,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(1837105153,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(1845493758,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(2139095032,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(2130706439,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(2139095036,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(2130706435,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(2139095038,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(2130706433,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(2134301549,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(2137896667,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(2132384153,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(2137417318,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(2134621115,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(2135180356,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(2133103177,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(2136698294,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(2134061875,32,FLEN)
NAN_BOXED(2132819439,32,FLEN)
NAN_BOXED(1070366114,32,FLEN)
NAN_BOXED(2135739596,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(1853882367,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(1845493760,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(1849688063,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(1849688064,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(1847590911,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(1851785216,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(1846542335,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(1852833792,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(1846018047,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(1853358080,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(1845755903,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(1853620224,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(1845624831,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(1853751296,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(1845559295,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(1853816832,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(1845526527,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(1853849600,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(1845510143,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(1853865984,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(1845501951,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(1853874176,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(1845497855,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(1853878272,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(1845495807,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(1853880320,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(1845494783,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(1853881344,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(1845494271,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(1853881856,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(1845494015,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(1853882112,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(1845493887,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(1853882240,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(1845493823,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(1853882304,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(1845493791,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(1853882336,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(1845493775,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(1853882352,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(1845493767,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(1853882360,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(1845493763,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(1853882364,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(1845493761,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(1853882366,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(2139095032,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(2130706439,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(2139095036,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(2130706435,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(2139095038,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(2130706433,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(2134301549,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(2137896667,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(2132384153,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(2137417318,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(2134621115,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(2135180356,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(2133103177,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(2136698294,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(2134061875,32,FLEN)
NAN_BOXED(2124221165,32,FLEN)
NAN_BOXED(1079027737,32,FLEN)
NAN_BOXED(2135739596,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(1862270975,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(1853882368,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(1858076671,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(1858076672,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(1855979519,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(1860173824,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(1854930943,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(1861222400,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(1854406655,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(1861746688,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(1854144511,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(1862008832,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(1854013439,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(1862139904,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(1853947903,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(1862205440,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(1853915135,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(1862238208,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(1853898751,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(1862254592,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(1853890559,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(1862262784,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(1853886463,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(1862266880,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(1853884415,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(1862268928,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(1853883391,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(1862269952,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(1853882879,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(1862270464,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(1853882623,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(1862270720,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(1853882495,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(1862270848,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(1853882431,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(1862270912,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(1853882399,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(1862270944,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(1853882383,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(1862270960,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(1853882375,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(1862270968,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(1853882371,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(1862270972,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(1853882369,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(1862270974,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(2139095032,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(2130706439,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(2139095036,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(2130706435,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(2139095038,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(2130706433,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(2134301549,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(2137896667,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(2132384153,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(2137417318,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(2134621115,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(2135180356,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(2133103177,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(2136698294,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(2134061875,32,FLEN)
NAN_BOXED(2131687445,32,FLEN)
NAN_BOXED(1071985223,32,FLEN)
NAN_BOXED(2135739596,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(1870659583,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(1862270976,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(1866465279,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(1866465280,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(1864368127,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(1868562432,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(1863319551,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(1869611008,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(1862795263,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(1870135296,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(1862533119,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(1870397440,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(1862402047,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(1870528512,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(1862336511,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(1870594048,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(1862303743,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(1870626816,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(1862287359,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(1870643200,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(1862279167,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(1870651392,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(1862275071,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(1870655488,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(1862273023,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(1870657536,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(1862271999,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(1870658560,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(1862271487,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(1870659072,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(1862271231,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(1870659328,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(1862271103,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(1870659456,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(1862271039,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(1870659520,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(1862271007,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(1870659552,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(1862270991,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(1870659568,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(1862270983,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(1870659576,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(1862270979,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(1870659580,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(1862270977,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(1870659582,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(2139095032,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(2130706439,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(2139095036,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(2130706435,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(2139095038,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(2130706433,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(2134301549,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(2137896667,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(2132384153,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(2137417318,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(2134621115,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(2135180356,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(2133103177,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(2136698294,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(2134061875,32,FLEN)
NAN_BOXED(2134744602,32,FLEN)
NAN_BOXED(1068289946,32,FLEN)
NAN_BOXED(2135739596,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(1879048191,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(1870659584,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(1874853887,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(1874853888,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(1872756735,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(1876951040,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(1871708159,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(1877999616,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(1871183871,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(1878523904,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(1870921727,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(1878786048,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(1870790655,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(1878917120,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(1870725119,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(1878982656,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(1870692351,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(1879015424,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(1870675967,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(1879031808,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(1870667775,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(1879040000,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(1870663679,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(1879044096,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(1870661631,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(1879046144,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(1870660607,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(1879047168,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(1870660095,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(1879047680,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(1870659839,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(1879047936,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(1870659711,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(1879048064,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(1870659647,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(1879048128,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(1870659615,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(1879048160,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(1870659599,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(1879048176,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(1870659591,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(1879048184,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(1870659587,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(1879048188,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(1870659585,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(1879048190,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(2139095032,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(2130706439,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(2139095036,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(2130706435,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(2139095038,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(2130706433,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(2134301549,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(2137896667,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(2132384153,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(2137417318,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(2134621115,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(2135180356,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(2133103177,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(2136698294,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(2134061875,32,FLEN)
NAN_BOXED(2120908701,32,FLEN)
NAN_BOXED(1082899595,32,FLEN)
NAN_BOXED(2135739596,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(1887436799,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(1879048192,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(1883242495,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(1883242496,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(1881145343,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(1885339648,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(1880096767,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(1886388224,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(1879572479,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(1886912512,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(1879310335,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(1887174656,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(1879179263,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(1887305728,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(1879113727,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(1887371264,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(1879080959,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(1887404032,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(1879064575,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(1887420416,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(1879056383,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(1887428608,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(1879052287,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(1887432704,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(1879050239,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(1887434752,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(1879049215,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(1887435776,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(1879048703,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(1887436288,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(1879048447,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(1887436544,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(1879048319,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(1887436672,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(1879048255,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(1887436736,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(1879048223,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(1887436768,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(1879048207,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(1887436784,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(1879048199,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(1887436792,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(1879048195,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(1887436796,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(1879048193,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(1887436798,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(2139095032,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(2130706439,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(2139095036,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(2130706435,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(2139095038,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(2130706433,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(2134301549,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(2137896667,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(2132384153,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(2137417318,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(2134621115,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(2135180356,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(2133103177,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(2136698294,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(2134061875,32,FLEN)
NAN_BOXED(2114112732,32,FLEN)
NAN_BOXED(1090159863,32,FLEN)
NAN_BOXED(2135739596,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(1895825407,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(1887436800,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(1891631103,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(1891631104,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(1889533951,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(1893728256,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(1888485375,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(1894776832,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(1887961087,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(1895301120,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(1887698943,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(1895563264,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(1887567871,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(1895694336,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(1887502335,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(1895759872,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(1887469567,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(1895792640,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(1887453183,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(1895809024,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(1887444991,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(1895817216,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(1887440895,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(1895821312,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(1887438847,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(1895823360,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(1887437823,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(1895824384,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(1887437311,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(1895824896,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(1887437055,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(1895825152,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(1887436927,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(1895825280,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(1887436863,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(1895825344,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(1887436831,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(1895825376,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(1887436815,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(1895825392,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(1887436807,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(1895825400,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(1887436803,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(1895825404,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(1887436801,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(1895825406,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(2139095032,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(2130706439,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(2139095036,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(2130706435,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(2139095038,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(2130706433,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(2134301549,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(2137896667,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(2132384153,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(2137417318,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(2134621115,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(2135180356,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(2133103177,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(2136698294,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(2134061875,32,FLEN)
NAN_BOXED(2129532874,32,FLEN)
NAN_BOXED(1074372734,32,FLEN)
NAN_BOXED(2135739596,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(1904214015,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(1895825408,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(1900019711,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(1900019712,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(1897922559,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(1902116864,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(1896873983,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(1903165440,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(1896349695,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(1903689728,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(1896087551,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(1903951872,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(1895956479,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(1904082944,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(1895890943,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(1904148480,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(1895858175,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(1904181248,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(1895841791,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(1904197632,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(1895833599,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(1904205824,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(1895829503,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(1904209920,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(1895827455,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(1904211968,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(1895826431,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(1904212992,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(1895825919,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(1904213504,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(1895825663,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(1904213760,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(1895825535,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(1904213888,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(1895825471,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(1904213952,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(1895825439,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(1904213984,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(1895825423,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(1904214000,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(1895825415,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(1904214008,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(1895825411,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(1904214012,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(1895825409,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(1904214014,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(2139095032,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(2130706439,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(2139095036,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(2130706435,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(2139095038,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(2130706433,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(2134301549,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(2137896667,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(2132384153,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(2137417318,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(2134621115,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(2135180356,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(2133103177,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(2136698294,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(2134061875,32,FLEN)
NAN_BOXED(2127291165,32,FLEN)
NAN_BOXED(1075885921,32,FLEN)
NAN_BOXED(2135739596,32,FLEN)
NAN_BOXED(2122974367,32,FLEN)
NAN_BOXED(1080912655,32,FLEN)
NAN_BOXED(1912602623,32,FLEN)
NAN_BOXED(2122974367,32,FLEN)
NAN_BOXED(1080912655,32,FLEN)
NAN_BOXED(1904214016,32,FLEN)
NAN_BOXED(2122974367,32,FLEN)
NAN_BOXED(1080912655,32,FLEN)
NAN_BOXED(1908408319,32,FLEN)
NAN_BOXED(2122974367,32,FLEN)
NAN_BOXED(1080912655,32,FLEN)
NAN_BOXED(1908408320,32,FLEN)
NAN_BOXED(2122974367,32,FLEN)
NAN_BOXED(1080912655,32,FLEN)
NAN_BOXED(1906311167,32,FLEN)
NAN_BOXED(2122974367,32,FLEN)
NAN_BOXED(1080912655,32,FLEN)
NAN_BOXED(1910505472,32,FLEN)
NAN_BOXED(2122974367,32,FLEN)
NAN_BOXED(1080912655,32,FLEN)
NAN_BOXED(1905262591,32,FLEN)
NAN_BOXED(2122974367,32,FLEN)
NAN_BOXED(1080912655,32,FLEN)
NAN_BOXED(1911554048,32,FLEN)
NAN_BOXED(2122974367,32,FLEN)
NAN_BOXED(1080912655,32,FLEN)
NAN_BOXED(1904738303,32,FLEN)
NAN_BOXED(2122974367,32,FLEN)
NAN_BOXED(1080912655,32,FLEN)
NAN_BOXED(1912078336,32,FLEN)
NAN_BOXED(2122974367,32,FLEN)
NAN_BOXED(1080912655,32,FLEN)
NAN_BOXED(1904476159,32,FLEN)
NAN_BOXED(2122974367,32,FLEN)
NAN_BOXED(1080912655,32,FLEN)
NAN_BOXED(1912340480,32,FLEN)
NAN_BOXED(2122974367,32,FLEN)
NAN_BOXED(1080912655,32,FLEN)
NAN_BOXED(1904345087,32,FLEN)
NAN_BOXED(2122974367,32,FLEN)
NAN_BOXED(1080912655,32,FLEN)
NAN_BOXED(1912471552,32,FLEN)
NAN_BOXED(2122974367,32,FLEN)
NAN_BOXED(1080912655,32,FLEN)
NAN_BOXED(1904279551,32,FLEN)
NAN_BOXED(2122974367,32,FLEN)
NAN_BOXED(1080912655,32,FLEN)
NAN_BOXED(1912537088,32,FLEN)
NAN_BOXED(2122974367,32,FLEN)
NAN_BOXED(1080912655,32,FLEN)
NAN_BOXED(1904246783,32,FLEN)
NAN_BOXED(2122974367,32,FLEN)
NAN_BOXED(1080912655,32,FLEN)
NAN_BOXED(1912569856,32,FLEN)
NAN_BOXED(2122974367,32,FLEN)
NAN_BOXED(1080912655,32,FLEN)
NAN_BOXED(1904230399,32,FLEN)
NAN_BOXED(2122974367,32,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;



signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 48*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_0:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_1:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_2:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_3:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_4:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_5:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_6:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_7:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_8:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_9:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_10:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_11:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_12:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_13:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_14:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_15:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_16:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_17:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_18:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_19:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_20:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_21:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_22:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_23:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_24:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_25:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_26:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_27:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_28:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_29:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_30:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_31:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_32:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_33:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_34:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_35:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_36:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_37:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_38:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_39:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_40:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_41:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_42:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_43:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_44:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_45:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_46:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_47:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_48:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_49:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_50:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_51:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_52:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_53:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_54:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_55:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_56:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_57:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_58:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_59:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_60:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_61:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_62:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_63:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_64:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_65:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_66:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_67:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_68:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_69:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_70:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_71:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_72:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_73:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_74:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_75:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_76:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_77:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_78:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_79:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_80:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_81:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_82:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_83:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_84:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_85:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_86:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_87:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_88:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_89:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_90:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_91:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_92:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_93:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_94:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_95:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_96:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_97:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_98:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_99:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_100:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_101:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_102:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_103:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_104:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_105:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_106:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_107:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_108:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_109:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_110:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_111:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_112:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_113:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_114:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_115:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_116:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_117:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_118:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_119:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_120:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_121:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_122:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_123:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_124:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_125:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_126:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_127:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_128:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_129:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_130:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_131:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_132:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_133:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_134:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_135:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_136:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_137:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_138:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_139:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_140:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_141:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_142:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_143:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_144:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_145:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_146:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_147:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_148:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_149:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_150:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_151:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_152:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_153:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_154:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_155:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_156:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_157:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_158:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_159:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_160:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_161:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_162:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_163:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_164:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_165:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_166:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_167:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_168:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_169:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_170:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_171:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_172:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_173:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_174:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_175:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_176:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_177:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_178:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_179:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_180:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_181:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_182:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_183:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_184:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_185:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_186:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_187:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_188:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_189:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_190:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_191:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_192:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_193:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_194:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_195:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_196:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_197:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_198:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_199:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_200:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_201:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_202:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_203:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_204:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_205:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_206:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_207:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_208:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_209:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_210:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_211:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_212:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_213:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_214:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_215:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_216:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_217:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_218:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_219:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_220:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_221:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_222:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_223:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_224:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_225:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_226:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_227:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_228:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_229:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_230:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_231:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_232:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_233:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_234:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_235:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_236:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_237:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_238:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_239:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_240:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_241:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_242:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_243:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_244:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_245:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_246:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_247:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_248:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_249:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_250:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_251:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_252:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_253:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_254:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_255:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_256:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_257:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_258:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_259:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_260:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_261:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_262:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_263:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_264:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_265:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_266:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_267:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_268:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_269:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_270:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_271:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_272:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_273:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_274:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_275:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_276:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_277:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_278:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_279:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_280:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_281:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_282:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_283:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_284:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_285:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_286:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_287:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_288:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_289:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_290:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_291:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_292:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_293:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_294:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_295:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_296:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_297:
    .fill 180*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;

mtrap_sigptr:
    .fill 64*XLEN/32,4,0xdeadbeef

tsig_end_canary:
CANARY;
#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif


sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
