
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.12.2
// timestamp : Wed Sep 25 06:07:02 2024 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fnmsub.cgf \
 \
//                  -- xlen 32  \
//                  --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fnmsub.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fnmsub_b8 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fnmsub_b8)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x7,test_dataset_0)
RVTEST_SIGBASE(x4,signature_x4_1)

inst_0:
// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x8, rs2==x8, rs3==x13, rd==x22,fs1 == 0 and fe1 == 0x0e and fm1 == 0x22f and fs2 == 1 and fe2 == 0x0a and fm2 == 0x23d and fs3 == 0 and fe3 == 0x0a and fm3 == 0x0d3 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x8; op2:x8; op3:x13; dest:x22; op1val:0x3a2f; op2val:0x3a2f;
op3val:0x28d3; valaddr_reg:x7; val_offset:0*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x22, x8, x8, x13, dyn, 0, 0, x7, 0*FLEN/8, x9, x4, x2)

inst_1:
// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x0, rs2==x10, rs3==x23, rd==x0,fs1 == 0 and fe1 == 0x0e and fm1 == 0x22f and fs2 == 1 and fe2 == 0x0a and fm2 == 0x23d and fs3 == 0 and fe3 == 0x0a and fm3 == 0x0d3 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x0; op2:x10; op3:x23; dest:x0; op1val:0x0; op2val:0xaa3d;
op3val:0x28d3; valaddr_reg:x7; val_offset:3*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x0, x0, x10, x23, dyn, 32, 0, x7, 3*FLEN/8, x9, x4, x2)

inst_2:
// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x23, rs2==x25, rs3==x27, rd==x28,fs1 == 0 and fe1 == 0x0e and fm1 == 0x22f and fs2 == 1 and fe2 == 0x0a and fm2 == 0x23d and fs3 == 0 and fe3 == 0x0a and fm3 == 0x0d3 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x23; op2:x25; op3:x27; dest:x28; op1val:0x3a2f; op2val:0xaa3d;
op3val:0x28d3; valaddr_reg:x7; val_offset:6*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x28, x23, x25, x27, dyn, 64, 0, x7, 6*FLEN/8, x9, x4, x2)

inst_3:
// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x24, rs2==x12, rs3==x24, rd==x27,fs1 == 0 and fe1 == 0x0e and fm1 == 0x22f and fs2 == 1 and fe2 == 0x0a and fm2 == 0x23d and fs3 == 0 and fe3 == 0x0a and fm3 == 0x0d3 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x24; op2:x12; op3:x24; dest:x27; op1val:0x3a2f; op2val:0xaa3d;
op3val:0x3a2f; valaddr_reg:x7; val_offset:9*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x27, x24, x12, x24, dyn, 96, 0, x7, 9*FLEN/8, x9, x4, x2)

inst_4:
// rs1 == rs2 == rs3 != rd, rs1==x1, rs2==x1, rs3==x1, rd==x10,fs1 == 0 and fe1 == 0x0e and fm1 == 0x22f and fs2 == 1 and fe2 == 0x0a and fm2 == 0x23d and fs3 == 0 and fe3 == 0x0a and fm3 == 0x0d3 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x1; op2:x1; op3:x1; dest:x10; op1val:0x3a2f; op2val:0x3a2f;
op3val:0x3a2f; valaddr_reg:x7; val_offset:12*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x10, x1, x1, x1, dyn, 128, 0, x7, 12*FLEN/8, x9, x4, x2)

inst_5:
// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x22, rs2==x0, rs3==x18, rd==x18,fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fd and fs2 == 1 and fe2 == 0x0d and fm2 == 0x167 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0b9 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x22; op2:x0; op3:x18; dest:x18; op1val:0x3afd; op2val:0x0;
op3val:0x34b9; valaddr_reg:x7; val_offset:15*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x18, x22, x0, x18, dyn, 0, 0, x7, 15*FLEN/8, x9, x4, x2)

inst_6:
// rd == rs2 == rs3 != rs1, rs1==x3, rs2==x17, rs3==x17, rd==x17,fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fd and fs2 == 1 and fe2 == 0x0d and fm2 == 0x167 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0b9 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x3; op2:x17; op3:x17; dest:x17; op1val:0x3afd; op2val:0xb567;
op3val:0xb567; valaddr_reg:x7; val_offset:18*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x17, x3, x17, x17, dyn, 32, 0, x7, 18*FLEN/8, x9, x4, x2)

inst_7:
// rs1 == rd == rs3 != rs2, rs1==x14, rs2==x31, rs3==x14, rd==x14,fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fd and fs2 == 1 and fe2 == 0x0d and fm2 == 0x167 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0b9 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x14; op2:x31; op3:x14; dest:x14; op1val:0x3afd; op2val:0xb567;
op3val:0x3afd; valaddr_reg:x7; val_offset:21*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x14, x14, x31, x14, dyn, 64, 0, x7, 21*FLEN/8, x9, x4, x2)

inst_8:
// rs1 == rs2 == rs3 == rd, rs1==x6, rs2==x6, rs3==x6, rd==x6,fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fd and fs2 == 1 and fe2 == 0x0d and fm2 == 0x167 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0b9 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x6; op2:x6; op3:x6; dest:x6; op1val:0x3afd; op2val:0x3afd;
op3val:0x3afd; valaddr_reg:x7; val_offset:24*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x6, x6, x6, x6, dyn, 96, 0, x7, 24*FLEN/8, x9, x4, x2)

inst_9:
// rs1 == rs2 == rd != rs3, rs1==x26, rs2==x26, rs3==x25, rd==x26,fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fd and fs2 == 1 and fe2 == 0x0d and fm2 == 0x167 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0b9 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x26; op2:x26; op3:x25; dest:x26; op1val:0x3afd; op2val:0x3afd;
op3val:0x34b9; valaddr_reg:x7; val_offset:27*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x26, x26, x26, x25, dyn, 128, 0, x7, 27*FLEN/8, x9, x4, x2)

inst_10:
// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x29, rs2==x19, rs3==x0, rd==x19,fs1 == 0 and fe1 == 0x0e and fm1 == 0x351 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x294 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x205 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x29; op2:x19; op3:x0; dest:x19; op1val:0x3b51; op2val:0xba94;
op3val:0x0; valaddr_reg:x7; val_offset:30*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x19, x29, x19, x0, dyn, 0, 0, x7, 30*FLEN/8, x9, x4, x2)

inst_11:
// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x5, rs2==x30, rs3==x30, rd==x21,fs1 == 0 and fe1 == 0x0e and fm1 == 0x351 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x294 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x205 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x5; op2:x30; op3:x30; dest:x21; op1val:0x3b51; op2val:0xba94;
op3val:0xba94; valaddr_reg:x7; val_offset:33*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x21, x5, x30, x30, dyn, 32, 0, x7, 33*FLEN/8, x9, x4, x2)
RVTEST_VALBASEUPD(x13,test_dataset_1)

inst_12:
// rs1==x9, rs2==x5, rs3==x26, rd==x11,fs1 == 0 and fe1 == 0x0e and fm1 == 0x351 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x294 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x205 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x9; op2:x5; op3:x26; dest:x11; op1val:0x3b51; op2val:0xba94;
op3val:0x3a05; valaddr_reg:x13; val_offset:0*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x11, x9, x5, x26, dyn, 64, 0, x13, 0*FLEN/8, x15, x4, x2)

inst_13:
// rs1==x2, rs2==x24, rs3==x21, rd==x25,fs1 == 0 and fe1 == 0x0e and fm1 == 0x351 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x294 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x205 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x2; op2:x24; op3:x21; dest:x25; op1val:0x3b51; op2val:0xba94;
op3val:0x3a05; valaddr_reg:x13; val_offset:3*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x25, x2, x24, x21, dyn, 96, 0, x13, 3*FLEN/8, x15, x4, x6)
RVTEST_SIGBASE(x1,signature_x1_0)

inst_14:
// rs1==x19, rs2==x29, rs3==x4, rd==x24,fs1 == 0 and fe1 == 0x0e and fm1 == 0x351 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x294 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x205 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x19; op2:x29; op3:x4; dest:x24; op1val:0x3b51; op2val:0xba94;
op3val:0x3a05; valaddr_reg:x13; val_offset:6*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x24, x19, x29, x4, dyn, 128, 0, x13, 6*FLEN/8, x15, x1, x6)

inst_15:
// rs1==x17, rs2==x4, rs3==x9, rd==x2,fs1 == 0 and fe1 == 0x04 and fm1 == 0x323 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x316 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x253 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x17; op2:x4; op3:x9; dest:x2; op1val:0x1323; op2val:0xe316;
op3val:0x3a53; valaddr_reg:x13; val_offset:9*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x2, x17, x4, x9, dyn, 0, 0, x13, 9*FLEN/8, x15, x1, x6)

inst_16:
// rs1==x10, rs2==x18, rs3==x2, rd==x5,fs1 == 0 and fe1 == 0x04 and fm1 == 0x323 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x316 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x253 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x10; op2:x18; op3:x2; dest:x5; op1val:0x1323; op2val:0xe316;
op3val:0x3a53; valaddr_reg:x13; val_offset:12*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x5, x10, x18, x2, dyn, 32, 0, x13, 12*FLEN/8, x15, x1, x6)

inst_17:
// rs1==x31, rs2==x14, rs3==x15, rd==x8,fs1 == 0 and fe1 == 0x04 and fm1 == 0x323 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x316 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x253 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x31; op2:x14; op3:x15; dest:x8; op1val:0x1323; op2val:0xe316;
op3val:0x3a53; valaddr_reg:x13; val_offset:15*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x8, x31, x14, x15, dyn, 64, 0, x13, 15*FLEN/8, x15, x1, x6)

inst_18:
// rs1==x7, rs2==x20, rs3==x22, rd==x3,fs1 == 0 and fe1 == 0x04 and fm1 == 0x323 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x316 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x253 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x7; op2:x20; op3:x22; dest:x3; op1val:0x1323; op2val:0xe316;
op3val:0x3a53; valaddr_reg:x13; val_offset:18*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x3, x7, x20, x22, dyn, 96, 0, x13, 18*FLEN/8, x15, x1, x6)

inst_19:
// rs1==x27, rs2==x23, rs3==x28, rd==x20,fs1 == 0 and fe1 == 0x04 and fm1 == 0x323 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x316 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x253 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x27; op2:x23; op3:x28; dest:x20; op1val:0x1323; op2val:0xe316;
op3val:0x3a53; valaddr_reg:x13; val_offset:21*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x20, x27, x23, x28, dyn, 128, 0, x13, 21*FLEN/8, x15, x1, x6)

inst_20:
// rs1==x16, rs2==x9, rs3==x5, rd==x4,fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ba and fs2 == 1 and fe2 == 0x0f and fm2 == 0x20a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x053 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x16; op2:x9; op3:x5; dest:x4; op1val:0x35ba; op2val:0xbe0a;
op3val:0x3853; valaddr_reg:x13; val_offset:24*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x4, x16, x9, x5, dyn, 0, 0, x13, 24*FLEN/8, x15, x1, x6)

inst_21:
// rs1==x20, rs2==x3, rs3==x10, rd==x12,fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ba and fs2 == 1 and fe2 == 0x0f and fm2 == 0x20a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x053 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x20; op2:x3; op3:x10; dest:x12; op1val:0x35ba; op2val:0xbe0a;
op3val:0x3853; valaddr_reg:x13; val_offset:27*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x12, x20, x3, x10, dyn, 32, 0, x13, 27*FLEN/8, x15, x1, x6)
RVTEST_VALBASEUPD(x8,test_dataset_2)

inst_22:
// rs1==x15, rs2==x22, rs3==x3, rd==x7,fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ba and fs2 == 1 and fe2 == 0x0f and fm2 == 0x20a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x053 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x15; op2:x22; op3:x3; dest:x7; op1val:0x35ba; op2val:0xbe0a;
op3val:0x3853; valaddr_reg:x8; val_offset:0*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x7, x15, x22, x3, dyn, 64, 0, x8, 0*FLEN/8, x10, x1, x6)

inst_23:
// rs1==x28, rs2==x11, rs3==x8, rd==x30,fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ba and fs2 == 1 and fe2 == 0x0f and fm2 == 0x20a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x053 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x28; op2:x11; op3:x8; dest:x30; op1val:0x35ba; op2val:0xbe0a;
op3val:0x3853; valaddr_reg:x8; val_offset:3*FLEN/8; rmval:dyn;
testreg:x6; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x30, x28, x11, x8, dyn, 96, 0, x8, 3*FLEN/8, x10, x1, x6)
RVTEST_SIGBASE(x3,signature_x3_0)

inst_24:
// rs1==x13, rs2==x7, rs3==x12, rd==x31,fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ba and fs2 == 1 and fe2 == 0x0f and fm2 == 0x20a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x053 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x13; op2:x7; op3:x12; dest:x31; op1val:0x35ba; op2val:0xbe0a;
op3val:0x3853; valaddr_reg:x8; val_offset:6*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x13, x7, x12, dyn, 128, 0, x8, 6*FLEN/8, x10, x3, x5)

inst_25:
// rs1==x21, rs2==x27, rs3==x7, rd==x15,fs1 == 0 and fe1 == 0x0e and fm1 == 0x05f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x363 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x00a and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x21; op2:x27; op3:x7; dest:x15; op1val:0x385f; op2val:0xbb63;
op3val:0x380a; valaddr_reg:x8; val_offset:9*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x15, x21, x27, x7, dyn, 0, 0, x8, 9*FLEN/8, x10, x3, x5)

inst_26:
// rs1==x11, rs2==x16, rs3==x29, rd==x13,fs1 == 0 and fe1 == 0x0e and fm1 == 0x05f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x363 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x00a and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x11; op2:x16; op3:x29; dest:x13; op1val:0x385f; op2val:0xbb63;
op3val:0x380a; valaddr_reg:x8; val_offset:12*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x13, x11, x16, x29, dyn, 32, 0, x8, 12*FLEN/8, x10, x3, x5)

inst_27:
// rs1==x4, rs2==x15, rs3==x31, rd==x16,fs1 == 0 and fe1 == 0x0e and fm1 == 0x05f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x363 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x00a and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x4; op2:x15; op3:x31; dest:x16; op1val:0x385f; op2val:0xbb63;
op3val:0x380a; valaddr_reg:x8; val_offset:15*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x16, x4, x15, x31, dyn, 64, 0, x8, 15*FLEN/8, x10, x3, x5)

inst_28:
// rs1==x18, rs2==x13, rs3==x19, rd==x23,fs1 == 0 and fe1 == 0x0e and fm1 == 0x05f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x363 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x00a and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x18; op2:x13; op3:x19; dest:x23; op1val:0x385f; op2val:0xbb63;
op3val:0x380a; valaddr_reg:x8; val_offset:18*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x23, x18, x13, x19, dyn, 96, 0, x8, 18*FLEN/8, x10, x3, x5)

inst_29:
// rs1==x30, rs2==x28, rs3==x20, rd==x9,fs1 == 0 and fe1 == 0x0e and fm1 == 0x05f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x363 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x00a and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x28; op3:x20; dest:x9; op1val:0x385f; op2val:0xbb63;
op3val:0x380a; valaddr_reg:x8; val_offset:21*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x9, x30, x28, x20, dyn, 128, 0, x8, 21*FLEN/8, x10, x3, x5)

inst_30:
// rs1==x12, rs2==x2, rs3==x16, rd==x1,fs1 == 0 and fe1 == 0x0e and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2b6 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x16c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x12; op2:x2; op3:x16; dest:x1; op1val:0x3a76; op2val:0xb2b6;
op3val:0x316c; valaddr_reg:x8; val_offset:24*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x1, x12, x2, x16, dyn, 0, 0, x8, 24*FLEN/8, x10, x3, x5)

inst_31:
// rs1==x25, rs2==x21, rs3==x11, rd==x29,fs1 == 0 and fe1 == 0x0e and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2b6 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x16c and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x25; op2:x21; op3:x11; dest:x29; op1val:0x3a76; op2val:0xb2b6;
op3val:0x316c; valaddr_reg:x8; val_offset:27*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x29, x25, x21, x11, dyn, 32, 0, x8, 27*FLEN/8, x10, x3, x5)

inst_32:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2b6 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x16c and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a76; op2val:0xb2b6;
op3val:0x316c; valaddr_reg:x8; val_offset:30*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 30*FLEN/8, x10, x3, x5)

inst_33:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2b6 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x16c and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a76; op2val:0xb2b6;
op3val:0x316c; valaddr_reg:x8; val_offset:33*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 33*FLEN/8, x10, x3, x5)

inst_34:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2b6 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x16c and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a76; op2val:0xb2b6;
op3val:0x316c; valaddr_reg:x8; val_offset:36*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 36*FLEN/8, x10, x3, x5)

inst_35:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x348 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2ba and fs3 == 0 and fe3 == 0x0e and fm3 == 0x220 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b48; op2val:0xbaba;
op3val:0x3a20; valaddr_reg:x8; val_offset:39*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 39*FLEN/8, x10, x3, x5)

inst_36:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x348 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2ba and fs3 == 0 and fe3 == 0x0e and fm3 == 0x220 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b48; op2val:0xbaba;
op3val:0x3a20; valaddr_reg:x8; val_offset:42*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 42*FLEN/8, x10, x3, x5)

inst_37:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x348 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2ba and fs3 == 0 and fe3 == 0x0e and fm3 == 0x220 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b48; op2val:0xbaba;
op3val:0x3a20; valaddr_reg:x8; val_offset:45*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 45*FLEN/8, x10, x3, x5)

inst_38:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x348 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2ba and fs3 == 0 and fe3 == 0x0e and fm3 == 0x220 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b48; op2val:0xbaba;
op3val:0x3a20; valaddr_reg:x8; val_offset:48*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 48*FLEN/8, x10, x3, x5)

inst_39:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x348 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2ba and fs3 == 0 and fe3 == 0x0e and fm3 == 0x220 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b48; op2val:0xbaba;
op3val:0x3a20; valaddr_reg:x8; val_offset:51*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 51*FLEN/8, x10, x3, x5)

inst_40:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1fc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1dd and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bd7; op2val:0xb9fc;
op3val:0x39dd; valaddr_reg:x8; val_offset:54*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 54*FLEN/8, x10, x3, x5)

inst_41:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1fc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1dd and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bd7; op2val:0xb9fc;
op3val:0x39dd; valaddr_reg:x8; val_offset:57*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 57*FLEN/8, x10, x3, x5)

inst_42:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1fc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1dd and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bd7; op2val:0xb9fc;
op3val:0x39dd; valaddr_reg:x8; val_offset:60*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 60*FLEN/8, x10, x3, x5)

inst_43:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1fc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1dd and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bd7; op2val:0xb9fc;
op3val:0x39dd; valaddr_reg:x8; val_offset:63*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 63*FLEN/8, x10, x3, x5)

inst_44:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3d7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1fc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1dd and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bd7; op2val:0xb9fc;
op3val:0x39dd; valaddr_reg:x8; val_offset:66*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 66*FLEN/8, x10, x3, x5)

inst_45:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x0c and fm2 == 0x14a and fs3 == 0 and fe3 == 0x0b and fm3 == 0x244 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38bd; op2val:0xb14a;
op3val:0x2e44; valaddr_reg:x8; val_offset:69*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 69*FLEN/8, x10, x3, x5)

inst_46:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x0c and fm2 == 0x14a and fs3 == 0 and fe3 == 0x0b and fm3 == 0x244 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38bd; op2val:0xb14a;
op3val:0x2e44; valaddr_reg:x8; val_offset:72*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 72*FLEN/8, x10, x3, x5)

inst_47:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x0c and fm2 == 0x14a and fs3 == 0 and fe3 == 0x0b and fm3 == 0x244 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38bd; op2val:0xb14a;
op3val:0x2e44; valaddr_reg:x8; val_offset:75*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 75*FLEN/8, x10, x3, x5)

inst_48:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x0c and fm2 == 0x14a and fs3 == 0 and fe3 == 0x0b and fm3 == 0x244 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38bd; op2val:0xb14a;
op3val:0x2e44; valaddr_reg:x8; val_offset:78*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 78*FLEN/8, x10, x3, x5)

inst_49:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x0c and fm2 == 0x14a and fs3 == 0 and fe3 == 0x0b and fm3 == 0x244 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38bd; op2val:0xb14a;
op3val:0x2e44; valaddr_reg:x8; val_offset:81*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 81*FLEN/8, x10, x3, x5)

inst_50:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1b5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x317 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38f7; op2val:0xbdb5;
op3val:0x3b17; valaddr_reg:x8; val_offset:84*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 84*FLEN/8, x10, x3, x5)

inst_51:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1b5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x317 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38f7; op2val:0xbdb5;
op3val:0x3b17; valaddr_reg:x8; val_offset:87*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 87*FLEN/8, x10, x3, x5)

inst_52:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1b5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x317 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38f7; op2val:0xbdb5;
op3val:0x3b17; valaddr_reg:x8; val_offset:90*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 90*FLEN/8, x10, x3, x5)

inst_53:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1b5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x317 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38f7; op2val:0xbdb5;
op3val:0x3b17; valaddr_reg:x8; val_offset:93*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 93*FLEN/8, x10, x3, x5)

inst_54:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0f7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1b5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x317 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38f7; op2val:0xbdb5;
op3val:0x3b17; valaddr_reg:x8; val_offset:96*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 96*FLEN/8, x10, x3, x5)

inst_55:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ee and fs2 == 1 and fe2 == 0x08 and fm2 == 0x1cc and fs3 == 0 and fe3 == 0x08 and fm3 == 0x04c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ee; op2val:0xa1cc;
op3val:0x204c; valaddr_reg:x8; val_offset:99*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 99*FLEN/8, x10, x3, x5)

inst_56:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ee and fs2 == 1 and fe2 == 0x08 and fm2 == 0x1cc and fs3 == 0 and fe3 == 0x08 and fm3 == 0x04c and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ee; op2val:0xa1cc;
op3val:0x204c; valaddr_reg:x8; val_offset:102*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 102*FLEN/8, x10, x3, x5)

inst_57:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ee and fs2 == 1 and fe2 == 0x08 and fm2 == 0x1cc and fs3 == 0 and fe3 == 0x08 and fm3 == 0x04c and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ee; op2val:0xa1cc;
op3val:0x204c; valaddr_reg:x8; val_offset:105*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 105*FLEN/8, x10, x3, x5)

inst_58:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ee and fs2 == 1 and fe2 == 0x08 and fm2 == 0x1cc and fs3 == 0 and fe3 == 0x08 and fm3 == 0x04c and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ee; op2val:0xa1cc;
op3val:0x204c; valaddr_reg:x8; val_offset:108*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 108*FLEN/8, x10, x3, x5)

inst_59:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ee and fs2 == 1 and fe2 == 0x08 and fm2 == 0x1cc and fs3 == 0 and fe3 == 0x08 and fm3 == 0x04c and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ee; op2val:0xa1cc;
op3val:0x204c; valaddr_reg:x8; val_offset:111*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 111*FLEN/8, x10, x3, x5)

inst_60:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x37e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x27c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x213 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b7e; op2val:0xb67c;
op3val:0x3613; valaddr_reg:x8; val_offset:114*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 114*FLEN/8, x10, x3, x5)

inst_61:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x37e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x27c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x213 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b7e; op2val:0xb67c;
op3val:0x3613; valaddr_reg:x8; val_offset:117*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 117*FLEN/8, x10, x3, x5)

inst_62:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x37e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x27c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x213 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b7e; op2val:0xb67c;
op3val:0x3613; valaddr_reg:x8; val_offset:120*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 120*FLEN/8, x10, x3, x5)

inst_63:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x37e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x27c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x213 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b7e; op2val:0xb67c;
op3val:0x3613; valaddr_reg:x8; val_offset:123*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 123*FLEN/8, x10, x3, x5)

inst_64:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x37e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x27c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x213 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b7e; op2val:0xb67c;
op3val:0x3613; valaddr_reg:x8; val_offset:126*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 126*FLEN/8, x10, x3, x5)

inst_65:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x05b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x16d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38fb; op2val:0xb85b;
op3val:0x356d; valaddr_reg:x8; val_offset:129*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 129*FLEN/8, x10, x3, x5)

inst_66:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x05b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x16d and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38fb; op2val:0xb85b;
op3val:0x356d; valaddr_reg:x8; val_offset:132*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 132*FLEN/8, x10, x3, x5)

inst_67:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x05b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x16d and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38fb; op2val:0xb85b;
op3val:0x356d; valaddr_reg:x8; val_offset:135*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 135*FLEN/8, x10, x3, x5)

inst_68:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x05b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x16d and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38fb; op2val:0xb85b;
op3val:0x356d; valaddr_reg:x8; val_offset:138*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 138*FLEN/8, x10, x3, x5)

inst_69:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x05b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x16d and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38fb; op2val:0xb85b;
op3val:0x356d; valaddr_reg:x8; val_offset:141*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 141*FLEN/8, x10, x3, x5)

inst_70:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x14a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x377 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0f0 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x394a; op2val:0xb777;
op3val:0x34f0; valaddr_reg:x8; val_offset:144*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 144*FLEN/8, x10, x3, x5)

inst_71:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x14a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x377 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0f0 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x394a; op2val:0xb777;
op3val:0x34f0; valaddr_reg:x8; val_offset:147*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 147*FLEN/8, x10, x3, x5)

inst_72:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x14a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x377 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0f0 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x394a; op2val:0xb777;
op3val:0x34f0; valaddr_reg:x8; val_offset:150*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 150*FLEN/8, x10, x3, x5)

inst_73:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x14a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x377 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0f0 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x394a; op2val:0xb777;
op3val:0x34f0; valaddr_reg:x8; val_offset:153*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 153*FLEN/8, x10, x3, x5)

inst_74:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x14a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x377 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0f0 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x394a; op2val:0xb777;
op3val:0x34f0; valaddr_reg:x8; val_offset:156*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 156*FLEN/8, x10, x3, x5)

inst_75:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x004 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x193 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x19a and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3804; op2val:0xb993;
op3val:0x359a; valaddr_reg:x8; val_offset:159*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 159*FLEN/8, x10, x3, x5)

inst_76:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x004 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x193 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x19a and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3804; op2val:0xb993;
op3val:0x359a; valaddr_reg:x8; val_offset:162*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 162*FLEN/8, x10, x3, x5)

inst_77:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x004 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x193 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x19a and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3804; op2val:0xb993;
op3val:0x359a; valaddr_reg:x8; val_offset:165*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 165*FLEN/8, x10, x3, x5)

inst_78:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x004 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x193 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x19a and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3804; op2val:0xb993;
op3val:0x359a; valaddr_reg:x8; val_offset:168*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 168*FLEN/8, x10, x3, x5)

inst_79:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x004 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x193 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x19a and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3804; op2val:0xb993;
op3val:0x359a; valaddr_reg:x8; val_offset:171*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 171*FLEN/8, x10, x3, x5)

inst_80:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x24f and fs2 == 1 and fe2 == 0x11 and fm2 == 0x03e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b2 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e4f; op2val:0xc43e;
op3val:0x36b2; valaddr_reg:x8; val_offset:174*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 174*FLEN/8, x10, x3, x5)

inst_81:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x24f and fs2 == 1 and fe2 == 0x11 and fm2 == 0x03e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b2 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e4f; op2val:0xc43e;
op3val:0x36b2; valaddr_reg:x8; val_offset:177*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 177*FLEN/8, x10, x3, x5)

inst_82:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x24f and fs2 == 1 and fe2 == 0x11 and fm2 == 0x03e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b2 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e4f; op2val:0xc43e;
op3val:0x36b2; valaddr_reg:x8; val_offset:180*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 180*FLEN/8, x10, x3, x5)

inst_83:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x24f and fs2 == 1 and fe2 == 0x11 and fm2 == 0x03e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b2 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e4f; op2val:0xc43e;
op3val:0x36b2; valaddr_reg:x8; val_offset:183*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 183*FLEN/8, x10, x3, x5)

inst_84:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x24f and fs2 == 1 and fe2 == 0x11 and fm2 == 0x03e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b2 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e4f; op2val:0xc43e;
op3val:0x36b2; valaddr_reg:x8; val_offset:186*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 186*FLEN/8, x10, x3, x5)

inst_85:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2dc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x05c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x37c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3adc; op2val:0xbc5c;
op3val:0x3b7c; valaddr_reg:x8; val_offset:189*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 189*FLEN/8, x10, x3, x5)

inst_86:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2dc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x05c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x37c and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3adc; op2val:0xbc5c;
op3val:0x3b7c; valaddr_reg:x8; val_offset:192*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 192*FLEN/8, x10, x3, x5)

inst_87:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2dc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x05c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x37c and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3adc; op2val:0xbc5c;
op3val:0x3b7c; valaddr_reg:x8; val_offset:195*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 195*FLEN/8, x10, x3, x5)

inst_88:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2dc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x05c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x37c and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3adc; op2val:0xbc5c;
op3val:0x3b7c; valaddr_reg:x8; val_offset:198*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 198*FLEN/8, x10, x3, x5)

inst_89:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2dc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x05c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x37c and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3adc; op2val:0xbc5c;
op3val:0x3b7c; valaddr_reg:x8; val_offset:201*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 201*FLEN/8, x10, x3, x5)

inst_90:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2e7 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0bd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x017 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ae7; op2val:0xc8bd;
op3val:0x3817; valaddr_reg:x8; val_offset:204*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 204*FLEN/8, x10, x3, x5)

inst_91:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2e7 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0bd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x017 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ae7; op2val:0xc8bd;
op3val:0x3817; valaddr_reg:x8; val_offset:207*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 207*FLEN/8, x10, x3, x5)

inst_92:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2e7 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0bd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x017 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ae7; op2val:0xc8bd;
op3val:0x3817; valaddr_reg:x8; val_offset:210*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 210*FLEN/8, x10, x3, x5)

inst_93:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2e7 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0bd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x017 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ae7; op2val:0xc8bd;
op3val:0x3817; valaddr_reg:x8; val_offset:213*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 213*FLEN/8, x10, x3, x5)

inst_94:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2e7 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0bd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x017 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ae7; op2val:0xc8bd;
op3val:0x3817; valaddr_reg:x8; val_offset:216*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 216*FLEN/8, x10, x3, x5)

inst_95:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x272 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x048 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2e8 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a72; op2val:0xac48;
op3val:0x2ae8; valaddr_reg:x8; val_offset:219*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 219*FLEN/8, x10, x3, x5)

inst_96:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x272 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x048 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2e8 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a72; op2val:0xac48;
op3val:0x2ae8; valaddr_reg:x8; val_offset:222*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 222*FLEN/8, x10, x3, x5)

inst_97:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x272 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x048 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2e8 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a72; op2val:0xac48;
op3val:0x2ae8; valaddr_reg:x8; val_offset:225*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 225*FLEN/8, x10, x3, x5)

inst_98:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x272 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x048 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2e8 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a72; op2val:0xac48;
op3val:0x2ae8; valaddr_reg:x8; val_offset:228*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 228*FLEN/8, x10, x3, x5)

inst_99:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x272 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x048 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x2e8 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a72; op2val:0xac48;
op3val:0x2ae8; valaddr_reg:x8; val_offset:231*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 231*FLEN/8, x10, x3, x5)

inst_100:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2bc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x126 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x056 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36bc; op2val:0xb926;
op3val:0x3456; valaddr_reg:x8; val_offset:234*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 234*FLEN/8, x10, x3, x5)

inst_101:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2bc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x126 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x056 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36bc; op2val:0xb926;
op3val:0x3456; valaddr_reg:x8; val_offset:237*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 237*FLEN/8, x10, x3, x5)

inst_102:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2bc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x126 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x056 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36bc; op2val:0xb926;
op3val:0x3456; valaddr_reg:x8; val_offset:240*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 240*FLEN/8, x10, x3, x5)

inst_103:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2bc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x126 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x056 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36bc; op2val:0xb926;
op3val:0x3456; valaddr_reg:x8; val_offset:243*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 243*FLEN/8, x10, x3, x5)

inst_104:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2bc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x126 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x056 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36bc; op2val:0xb926;
op3val:0x3456; valaddr_reg:x8; val_offset:246*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 246*FLEN/8, x10, x3, x5)

inst_105:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x39e and fs2 == 1 and fe2 == 0x11 and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b6 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f9e; op2val:0xc600;
op3val:0x39b6; valaddr_reg:x8; val_offset:249*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 249*FLEN/8, x10, x3, x5)

inst_106:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x39e and fs2 == 1 and fe2 == 0x11 and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b6 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f9e; op2val:0xc600;
op3val:0x39b6; valaddr_reg:x8; val_offset:252*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 252*FLEN/8, x10, x3, x5)

inst_107:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x39e and fs2 == 1 and fe2 == 0x11 and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b6 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f9e; op2val:0xc600;
op3val:0x39b6; valaddr_reg:x8; val_offset:255*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 255*FLEN/8, x10, x3, x5)

inst_108:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x39e and fs2 == 1 and fe2 == 0x11 and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b6 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f9e; op2val:0xc600;
op3val:0x39b6; valaddr_reg:x8; val_offset:258*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 258*FLEN/8, x10, x3, x5)

inst_109:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x39e and fs2 == 1 and fe2 == 0x11 and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b6 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f9e; op2val:0xc600;
op3val:0x39b6; valaddr_reg:x8; val_offset:261*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 261*FLEN/8, x10, x3, x5)

inst_110:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x125 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x210 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3cd and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3925; op2val:0xb210;
op3val:0x2fcd; valaddr_reg:x8; val_offset:264*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 264*FLEN/8, x10, x3, x5)

inst_111:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x125 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x210 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3cd and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3925; op2val:0xb210;
op3val:0x2fcd; valaddr_reg:x8; val_offset:267*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 267*FLEN/8, x10, x3, x5)

inst_112:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x125 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x210 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3cd and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3925; op2val:0xb210;
op3val:0x2fcd; valaddr_reg:x8; val_offset:270*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 270*FLEN/8, x10, x3, x5)

inst_113:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x125 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x210 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3cd and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3925; op2val:0xb210;
op3val:0x2fcd; valaddr_reg:x8; val_offset:273*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 273*FLEN/8, x10, x3, x5)

inst_114:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x125 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x210 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3cd and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3925; op2val:0xb210;
op3val:0x2fcd; valaddr_reg:x8; val_offset:276*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 276*FLEN/8, x10, x3, x5)

inst_115:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2eb and fs2 == 1 and fe2 == 0x0d and fm2 == 0x05c and fs3 == 0 and fe3 == 0x0c and fm3 == 0x38a and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aeb; op2val:0xb45c;
op3val:0x338a; valaddr_reg:x8; val_offset:279*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 279*FLEN/8, x10, x3, x5)

inst_116:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2eb and fs2 == 1 and fe2 == 0x0d and fm2 == 0x05c and fs3 == 0 and fe3 == 0x0c and fm3 == 0x38a and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aeb; op2val:0xb45c;
op3val:0x338a; valaddr_reg:x8; val_offset:282*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 282*FLEN/8, x10, x3, x5)

inst_117:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2eb and fs2 == 1 and fe2 == 0x0d and fm2 == 0x05c and fs3 == 0 and fe3 == 0x0c and fm3 == 0x38a and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aeb; op2val:0xb45c;
op3val:0x338a; valaddr_reg:x8; val_offset:285*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 285*FLEN/8, x10, x3, x5)

inst_118:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2eb and fs2 == 1 and fe2 == 0x0d and fm2 == 0x05c and fs3 == 0 and fe3 == 0x0c and fm3 == 0x38a and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aeb; op2val:0xb45c;
op3val:0x338a; valaddr_reg:x8; val_offset:288*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 288*FLEN/8, x10, x3, x5)

inst_119:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2eb and fs2 == 1 and fe2 == 0x0d and fm2 == 0x05c and fs3 == 0 and fe3 == 0x0c and fm3 == 0x38a and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aeb; op2val:0xb45c;
op3val:0x338a; valaddr_reg:x8; val_offset:291*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 291*FLEN/8, x10, x3, x5)

inst_120:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x338 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x17e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0f5 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b38; op2val:0xb57e;
op3val:0x34f5; valaddr_reg:x8; val_offset:294*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 294*FLEN/8, x10, x3, x5)

inst_121:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x338 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x17e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0f5 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b38; op2val:0xb57e;
op3val:0x34f5; valaddr_reg:x8; val_offset:297*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 297*FLEN/8, x10, x3, x5)

inst_122:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x338 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x17e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0f5 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b38; op2val:0xb57e;
op3val:0x34f5; valaddr_reg:x8; val_offset:300*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 300*FLEN/8, x10, x3, x5)

inst_123:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x338 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x17e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0f5 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b38; op2val:0xb57e;
op3val:0x34f5; valaddr_reg:x8; val_offset:303*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 303*FLEN/8, x10, x3, x5)

inst_124:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x338 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x17e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0f5 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b38; op2val:0xb57e;
op3val:0x34f5; valaddr_reg:x8; val_offset:306*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 306*FLEN/8, x10, x3, x5)

inst_125:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c4 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x15f and fs3 == 0 and fe3 == 0x0a and fm3 == 0x266 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34c4; op2val:0xb15f;
op3val:0x2a66; valaddr_reg:x8; val_offset:309*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 309*FLEN/8, x10, x3, x5)

inst_126:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c4 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x15f and fs3 == 0 and fe3 == 0x0a and fm3 == 0x266 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34c4; op2val:0xb15f;
op3val:0x2a66; valaddr_reg:x8; val_offset:312*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 312*FLEN/8, x10, x3, x5)

inst_127:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c4 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x15f and fs3 == 0 and fe3 == 0x0a and fm3 == 0x266 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34c4; op2val:0xb15f;
op3val:0x2a66; valaddr_reg:x8; val_offset:315*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 315*FLEN/8, x10, x3, x5)

inst_128:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c4 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x15f and fs3 == 0 and fe3 == 0x0a and fm3 == 0x266 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34c4; op2val:0xb15f;
op3val:0x2a66; valaddr_reg:x8; val_offset:318*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 318*FLEN/8, x10, x3, x5)

inst_129:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c4 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x15f and fs3 == 0 and fe3 == 0x0a and fm3 == 0x266 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34c4; op2val:0xb15f;
op3val:0x2a66; valaddr_reg:x8; val_offset:321*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 321*FLEN/8, x10, x3, x5)

inst_130:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x102 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x257 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3f1 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3102; op2val:0xc257;
op3val:0x37f1; valaddr_reg:x8; val_offset:324*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 324*FLEN/8, x10, x3, x5)

inst_131:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x102 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x257 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3f1 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3102; op2val:0xc257;
op3val:0x37f1; valaddr_reg:x8; val_offset:327*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 327*FLEN/8, x10, x3, x5)

inst_132:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x102 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x257 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3f1 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3102; op2val:0xc257;
op3val:0x37f1; valaddr_reg:x8; val_offset:330*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 330*FLEN/8, x10, x3, x5)

inst_133:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x102 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x257 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3f1 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3102; op2val:0xc257;
op3val:0x37f1; valaddr_reg:x8; val_offset:333*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 333*FLEN/8, x10, x3, x5)

inst_134:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x102 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x257 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3f1 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3102; op2val:0xc257;
op3val:0x37f1; valaddr_reg:x8; val_offset:336*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 336*FLEN/8, x10, x3, x5)

inst_135:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x26b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cc and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a6b; op2val:0xbc3c;
op3val:0x3acc; valaddr_reg:x8; val_offset:339*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 339*FLEN/8, x10, x3, x5)

inst_136:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x26b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cc and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a6b; op2val:0xbc3c;
op3val:0x3acc; valaddr_reg:x8; val_offset:342*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 342*FLEN/8, x10, x3, x5)

inst_137:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x26b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cc and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a6b; op2val:0xbc3c;
op3val:0x3acc; valaddr_reg:x8; val_offset:345*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 345*FLEN/8, x10, x3, x5)

inst_138:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x26b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cc and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a6b; op2val:0xbc3c;
op3val:0x3acc; valaddr_reg:x8; val_offset:348*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 348*FLEN/8, x10, x3, x5)

inst_139:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x26b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2cc and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a6b; op2val:0xbc3c;
op3val:0x3acc; valaddr_reg:x8; val_offset:351*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 351*FLEN/8, x10, x3, x5)

inst_140:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x029 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3d7 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x378a; op2val:0xbc29;
op3val:0x37d7; valaddr_reg:x8; val_offset:354*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 354*FLEN/8, x10, x3, x5)

inst_141:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x029 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3d7 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x378a; op2val:0xbc29;
op3val:0x37d7; valaddr_reg:x8; val_offset:357*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 357*FLEN/8, x10, x3, x5)

inst_142:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x029 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3d7 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x378a; op2val:0xbc29;
op3val:0x37d7; valaddr_reg:x8; val_offset:360*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 360*FLEN/8, x10, x3, x5)

inst_143:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x029 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3d7 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x378a; op2val:0xbc29;
op3val:0x37d7; valaddr_reg:x8; val_offset:363*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 363*FLEN/8, x10, x3, x5)

inst_144:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x029 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3d7 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x378a; op2val:0xbc29;
op3val:0x37d7; valaddr_reg:x8; val_offset:366*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 366*FLEN/8, x10, x3, x5)

inst_145:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36d and fs2 == 1 and fe2 == 0x0b and fm2 == 0x2ab and fs3 == 0 and fe3 == 0x0b and fm3 == 0x231 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6d; op2val:0xaeab;
op3val:0x2e31; valaddr_reg:x8; val_offset:369*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 369*FLEN/8, x10, x3, x5)

inst_146:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36d and fs2 == 1 and fe2 == 0x0b and fm2 == 0x2ab and fs3 == 0 and fe3 == 0x0b and fm3 == 0x231 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6d; op2val:0xaeab;
op3val:0x2e31; valaddr_reg:x8; val_offset:372*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 372*FLEN/8, x10, x3, x5)

inst_147:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36d and fs2 == 1 and fe2 == 0x0b and fm2 == 0x2ab and fs3 == 0 and fe3 == 0x0b and fm3 == 0x231 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6d; op2val:0xaeab;
op3val:0x2e31; valaddr_reg:x8; val_offset:375*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 375*FLEN/8, x10, x3, x5)

inst_148:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36d and fs2 == 1 and fe2 == 0x0b and fm2 == 0x2ab and fs3 == 0 and fe3 == 0x0b and fm3 == 0x231 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6d; op2val:0xaeab;
op3val:0x2e31; valaddr_reg:x8; val_offset:378*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 378*FLEN/8, x10, x3, x5)

inst_149:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36d and fs2 == 1 and fe2 == 0x0b and fm2 == 0x2ab and fs3 == 0 and fe3 == 0x0b and fm3 == 0x231 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6d; op2val:0xaeab;
op3val:0x2e31; valaddr_reg:x8; val_offset:381*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 381*FLEN/8, x10, x3, x5)

inst_150:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e1 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0d9 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0c7 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37e1; op2val:0xb8d9;
op3val:0x34c7; valaddr_reg:x8; val_offset:384*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 384*FLEN/8, x10, x3, x5)

inst_151:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e1 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0d9 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0c7 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37e1; op2val:0xb8d9;
op3val:0x34c7; valaddr_reg:x8; val_offset:387*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 387*FLEN/8, x10, x3, x5)
RVTEST_SIGBASE(x3,signature_x3_1)

inst_152:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e1 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0d9 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0c7 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37e1; op2val:0xb8d9;
op3val:0x34c7; valaddr_reg:x8; val_offset:390*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 390*FLEN/8, x10, x3, x5)

inst_153:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e1 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0d9 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0c7 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37e1; op2val:0xb8d9;
op3val:0x34c7; valaddr_reg:x8; val_offset:393*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 393*FLEN/8, x10, x3, x5)

inst_154:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e1 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0d9 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0c7 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37e1; op2val:0xb8d9;
op3val:0x34c7; valaddr_reg:x8; val_offset:396*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 396*FLEN/8, x10, x3, x5)

inst_155:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3c1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x20c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a3d; op2val:0xbbc1;
op3val:0x3a0c; valaddr_reg:x8; val_offset:399*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 399*FLEN/8, x10, x3, x5)

inst_156:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3c1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x20c and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a3d; op2val:0xbbc1;
op3val:0x3a0c; valaddr_reg:x8; val_offset:402*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 402*FLEN/8, x10, x3, x5)

inst_157:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3c1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x20c and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a3d; op2val:0xbbc1;
op3val:0x3a0c; valaddr_reg:x8; val_offset:405*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 405*FLEN/8, x10, x3, x5)

inst_158:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3c1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x20c and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a3d; op2val:0xbbc1;
op3val:0x3a0c; valaddr_reg:x8; val_offset:408*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 408*FLEN/8, x10, x3, x5)

inst_159:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3c1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x20c and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a3d; op2val:0xbbc1;
op3val:0x3a0c; valaddr_reg:x8; val_offset:411*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 411*FLEN/8, x10, x3, x5)

inst_160:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x151 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x141 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3be7; op2val:0xb951;
op3val:0x3941; valaddr_reg:x8; val_offset:414*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 414*FLEN/8, x10, x3, x5)

inst_161:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x151 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x141 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3be7; op2val:0xb951;
op3val:0x3941; valaddr_reg:x8; val_offset:417*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 417*FLEN/8, x10, x3, x5)

inst_162:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x151 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x141 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3be7; op2val:0xb951;
op3val:0x3941; valaddr_reg:x8; val_offset:420*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 420*FLEN/8, x10, x3, x5)

inst_163:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x151 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x141 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3be7; op2val:0xb951;
op3val:0x3941; valaddr_reg:x8; val_offset:423*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 423*FLEN/8, x10, x3, x5)

inst_164:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e7 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x151 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x141 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3be7; op2val:0xb951;
op3val:0x3941; valaddr_reg:x8; val_offset:426*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 426*FLEN/8, x10, x3, x5)

inst_165:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1dd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x24a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x09c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39dd; op2val:0xba4a;
op3val:0x389c; valaddr_reg:x8; val_offset:429*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 429*FLEN/8, x10, x3, x5)

inst_166:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1dd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x24a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x09c and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39dd; op2val:0xba4a;
op3val:0x389c; valaddr_reg:x8; val_offset:432*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 432*FLEN/8, x10, x3, x5)

inst_167:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1dd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x24a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x09c and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39dd; op2val:0xba4a;
op3val:0x389c; valaddr_reg:x8; val_offset:435*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 435*FLEN/8, x10, x3, x5)

inst_168:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1dd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x24a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x09c and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39dd; op2val:0xba4a;
op3val:0x389c; valaddr_reg:x8; val_offset:438*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 438*FLEN/8, x10, x3, x5)

inst_169:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1dd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x24a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x09c and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39dd; op2val:0xba4a;
op3val:0x389c; valaddr_reg:x8; val_offset:441*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 441*FLEN/8, x10, x3, x5)

inst_170:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x0d and fm2 == 0x041 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x14d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38fc; op2val:0xb441;
op3val:0x314d; valaddr_reg:x8; val_offset:444*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 444*FLEN/8, x10, x3, x5)

inst_171:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x0d and fm2 == 0x041 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x14d and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38fc; op2val:0xb441;
op3val:0x314d; valaddr_reg:x8; val_offset:447*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 447*FLEN/8, x10, x3, x5)

inst_172:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x0d and fm2 == 0x041 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x14d and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38fc; op2val:0xb441;
op3val:0x314d; valaddr_reg:x8; val_offset:450*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 450*FLEN/8, x10, x3, x5)

inst_173:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x0d and fm2 == 0x041 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x14d and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38fc; op2val:0xb441;
op3val:0x314d; valaddr_reg:x8; val_offset:453*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 453*FLEN/8, x10, x3, x5)

inst_174:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x0d and fm2 == 0x041 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x14d and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38fc; op2val:0xb441;
op3val:0x314d; valaddr_reg:x8; val_offset:456*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 456*FLEN/8, x10, x3, x5)

inst_175:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2f2 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x399 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x299 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ef2; op2val:0xc799;
op3val:0x3a99; valaddr_reg:x8; val_offset:459*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 459*FLEN/8, x10, x3, x5)

inst_176:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2f2 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x399 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x299 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ef2; op2val:0xc799;
op3val:0x3a99; valaddr_reg:x8; val_offset:462*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 462*FLEN/8, x10, x3, x5)

inst_177:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2f2 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x399 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x299 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ef2; op2val:0xc799;
op3val:0x3a99; valaddr_reg:x8; val_offset:465*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 465*FLEN/8, x10, x3, x5)

inst_178:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2f2 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x399 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x299 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ef2; op2val:0xc799;
op3val:0x3a99; valaddr_reg:x8; val_offset:468*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 468*FLEN/8, x10, x3, x5)

inst_179:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x2f2 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x399 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x299 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ef2; op2val:0xc799;
op3val:0x3a99; valaddr_reg:x8; val_offset:471*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 471*FLEN/8, x10, x3, x5)

inst_180:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x186 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ab and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d4; op2val:0xbd86;
op3val:0x3aab; valaddr_reg:x8; val_offset:474*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 474*FLEN/8, x10, x3, x5)

inst_181:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x186 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ab and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d4; op2val:0xbd86;
op3val:0x3aab; valaddr_reg:x8; val_offset:477*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 477*FLEN/8, x10, x3, x5)

inst_182:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x186 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ab and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d4; op2val:0xbd86;
op3val:0x3aab; valaddr_reg:x8; val_offset:480*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 480*FLEN/8, x10, x3, x5)

inst_183:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x186 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ab and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d4; op2val:0xbd86;
op3val:0x3aab; valaddr_reg:x8; val_offset:483*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 483*FLEN/8, x10, x3, x5)

inst_184:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x186 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2ab and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d4; op2val:0xbd86;
op3val:0x3aab; valaddr_reg:x8; val_offset:486*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 486*FLEN/8, x10, x3, x5)

inst_185:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x163 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0c7 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x270 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3563; op2val:0xacc7;
op3val:0x2670; valaddr_reg:x8; val_offset:489*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 489*FLEN/8, x10, x3, x5)

inst_186:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x163 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0c7 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x270 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3563; op2val:0xacc7;
op3val:0x2670; valaddr_reg:x8; val_offset:492*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 492*FLEN/8, x10, x3, x5)

inst_187:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x163 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0c7 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x270 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3563; op2val:0xacc7;
op3val:0x2670; valaddr_reg:x8; val_offset:495*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 495*FLEN/8, x10, x3, x5)

inst_188:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x163 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0c7 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x270 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3563; op2val:0xacc7;
op3val:0x2670; valaddr_reg:x8; val_offset:498*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 498*FLEN/8, x10, x3, x5)

inst_189:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x163 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x0c7 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x270 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3563; op2val:0xacc7;
op3val:0x2670; valaddr_reg:x8; val_offset:501*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 501*FLEN/8, x10, x3, x5)

inst_190:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x262 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0ae and fs3 == 0 and fe3 == 0x0c and fm3 == 0x379 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a62; op2val:0xb4ae;
op3val:0x3379; valaddr_reg:x8; val_offset:504*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 504*FLEN/8, x10, x3, x5)

inst_191:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x262 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0ae and fs3 == 0 and fe3 == 0x0c and fm3 == 0x379 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a62; op2val:0xb4ae;
op3val:0x3379; valaddr_reg:x8; val_offset:507*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 507*FLEN/8, x10, x3, x5)

inst_192:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x262 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0ae and fs3 == 0 and fe3 == 0x0c and fm3 == 0x379 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a62; op2val:0xb4ae;
op3val:0x3379; valaddr_reg:x8; val_offset:510*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 510*FLEN/8, x10, x3, x5)

inst_193:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x262 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0ae and fs3 == 0 and fe3 == 0x0c and fm3 == 0x379 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a62; op2val:0xb4ae;
op3val:0x3379; valaddr_reg:x8; val_offset:513*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 513*FLEN/8, x10, x3, x5)

inst_194:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x262 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0ae and fs3 == 0 and fe3 == 0x0c and fm3 == 0x379 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a62; op2val:0xb4ae;
op3val:0x3379; valaddr_reg:x8; val_offset:516*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 516*FLEN/8, x10, x3, x5)

inst_195:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x199 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1a3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e4 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3999; op2val:0xbda3;
op3val:0x3be4; valaddr_reg:x8; val_offset:519*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 519*FLEN/8, x10, x3, x5)

inst_196:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x199 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1a3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e4 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3999; op2val:0xbda3;
op3val:0x3be4; valaddr_reg:x8; val_offset:522*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 522*FLEN/8, x10, x3, x5)

inst_197:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x199 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1a3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e4 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3999; op2val:0xbda3;
op3val:0x3be4; valaddr_reg:x8; val_offset:525*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 525*FLEN/8, x10, x3, x5)

inst_198:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x199 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1a3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e4 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3999; op2val:0xbda3;
op3val:0x3be4; valaddr_reg:x8; val_offset:528*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 528*FLEN/8, x10, x3, x5)

inst_199:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x199 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1a3 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3e4 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3999; op2val:0xbda3;
op3val:0x3be4; valaddr_reg:x8; val_offset:531*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 531*FLEN/8, x10, x3, x5)

inst_200:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x38a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x195 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x143 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x338a; op2val:0xc195;
op3val:0x3943; valaddr_reg:x8; val_offset:534*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 534*FLEN/8, x10, x3, x5)

inst_201:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x38a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x195 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x143 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x338a; op2val:0xc195;
op3val:0x3943; valaddr_reg:x8; val_offset:537*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 537*FLEN/8, x10, x3, x5)

inst_202:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x38a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x195 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x143 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x338a; op2val:0xc195;
op3val:0x3943; valaddr_reg:x8; val_offset:540*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 540*FLEN/8, x10, x3, x5)

inst_203:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x38a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x195 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x143 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x338a; op2val:0xc195;
op3val:0x3943; valaddr_reg:x8; val_offset:543*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 543*FLEN/8, x10, x3, x5)

inst_204:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x38a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x195 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x143 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x338a; op2val:0xc195;
op3val:0x3943; valaddr_reg:x8; val_offset:546*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 546*FLEN/8, x10, x3, x5)

inst_205:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x170 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x083 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aa3; op2val:0xb970;
op3val:0x3883; valaddr_reg:x8; val_offset:549*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 549*FLEN/8, x10, x3, x5)

inst_206:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x170 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x083 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aa3; op2val:0xb970;
op3val:0x3883; valaddr_reg:x8; val_offset:552*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 552*FLEN/8, x10, x3, x5)

inst_207:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x170 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x083 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aa3; op2val:0xb970;
op3val:0x3883; valaddr_reg:x8; val_offset:555*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 555*FLEN/8, x10, x3, x5)

inst_208:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x170 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x083 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aa3; op2val:0xb970;
op3val:0x3883; valaddr_reg:x8; val_offset:558*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 558*FLEN/8, x10, x3, x5)

inst_209:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2a3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x170 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x083 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aa3; op2val:0xb970;
op3val:0x3883; valaddr_reg:x8; val_offset:561*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 561*FLEN/8, x10, x3, x5)

inst_210:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x225 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x224 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0b8 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a25; op2val:0xba24;
op3val:0x38b8; valaddr_reg:x8; val_offset:564*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 564*FLEN/8, x10, x3, x5)

inst_211:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x225 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x224 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0b8 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a25; op2val:0xba24;
op3val:0x38b8; valaddr_reg:x8; val_offset:567*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 567*FLEN/8, x10, x3, x5)

inst_212:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x225 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x224 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0b8 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a25; op2val:0xba24;
op3val:0x38b8; valaddr_reg:x8; val_offset:570*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 570*FLEN/8, x10, x3, x5)

inst_213:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x225 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x224 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0b8 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a25; op2val:0xba24;
op3val:0x38b8; valaddr_reg:x8; val_offset:573*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 573*FLEN/8, x10, x3, x5)

inst_214:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x225 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x224 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0b8 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a25; op2val:0xba24;
op3val:0x38b8; valaddr_reg:x8; val_offset:576*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 576*FLEN/8, x10, x3, x5)

inst_215:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x034 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a8 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x386e; op2val:0xbc34;
op3val:0x38a8; valaddr_reg:x8; val_offset:579*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 579*FLEN/8, x10, x3, x5)

inst_216:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x034 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a8 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x386e; op2val:0xbc34;
op3val:0x38a8; valaddr_reg:x8; val_offset:582*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 582*FLEN/8, x10, x3, x5)

inst_217:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x034 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a8 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x386e; op2val:0xbc34;
op3val:0x38a8; valaddr_reg:x8; val_offset:585*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 585*FLEN/8, x10, x3, x5)

inst_218:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x034 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a8 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x386e; op2val:0xbc34;
op3val:0x38a8; valaddr_reg:x8; val_offset:588*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 588*FLEN/8, x10, x3, x5)

inst_219:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x034 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a8 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x386e; op2val:0xbc34;
op3val:0x38a8; valaddr_reg:x8; val_offset:591*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 591*FLEN/8, x10, x3, x5)

inst_220:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x295 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b0 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3695; op2val:0xbeea;
op3val:0x39b0; valaddr_reg:x8; val_offset:594*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 594*FLEN/8, x10, x3, x5)

inst_221:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x295 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b0 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3695; op2val:0xbeea;
op3val:0x39b0; valaddr_reg:x8; val_offset:597*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 597*FLEN/8, x10, x3, x5)

inst_222:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x295 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b0 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3695; op2val:0xbeea;
op3val:0x39b0; valaddr_reg:x8; val_offset:600*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 600*FLEN/8, x10, x3, x5)

inst_223:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x295 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b0 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3695; op2val:0xbeea;
op3val:0x39b0; valaddr_reg:x8; val_offset:603*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 603*FLEN/8, x10, x3, x5)

inst_224:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x295 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2ea and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1b0 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3695; op2val:0xbeea;
op3val:0x39b0; valaddr_reg:x8; val_offset:606*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 606*FLEN/8, x10, x3, x5)

inst_225:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x33d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x351 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b3d; op2val:0xbc0b;
op3val:0x3b51; valaddr_reg:x8; val_offset:609*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 609*FLEN/8, x10, x3, x5)

inst_226:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x33d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x351 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b3d; op2val:0xbc0b;
op3val:0x3b51; valaddr_reg:x8; val_offset:612*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 612*FLEN/8, x10, x3, x5)

inst_227:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x33d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x351 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b3d; op2val:0xbc0b;
op3val:0x3b51; valaddr_reg:x8; val_offset:615*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 615*FLEN/8, x10, x3, x5)

inst_228:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x33d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x351 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b3d; op2val:0xbc0b;
op3val:0x3b51; valaddr_reg:x8; val_offset:618*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 618*FLEN/8, x10, x3, x5)

inst_229:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x33d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x351 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b3d; op2val:0xbc0b;
op3val:0x3b51; valaddr_reg:x8; val_offset:621*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 621*FLEN/8, x10, x3, x5)

inst_230:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x325 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x04a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3aa and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b25; op2val:0xb84a;
op3val:0x37aa; valaddr_reg:x8; val_offset:624*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 624*FLEN/8, x10, x3, x5)

inst_231:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x325 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x04a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3aa and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b25; op2val:0xb84a;
op3val:0x37aa; valaddr_reg:x8; val_offset:627*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 627*FLEN/8, x10, x3, x5)

inst_232:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x325 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x04a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3aa and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b25; op2val:0xb84a;
op3val:0x37aa; valaddr_reg:x8; val_offset:630*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 630*FLEN/8, x10, x3, x5)

inst_233:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x325 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x04a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3aa and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b25; op2val:0xb84a;
op3val:0x37aa; valaddr_reg:x8; val_offset:633*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 633*FLEN/8, x10, x3, x5)

inst_234:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x325 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x04a and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3aa and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b25; op2val:0xb84a;
op3val:0x37aa; valaddr_reg:x8; val_offset:636*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 636*FLEN/8, x10, x3, x5)

inst_235:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0cf and fs3 == 0 and fe3 == 0x0c and fm3 == 0x227 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391e; op2val:0xb4cf;
op3val:0x3227; valaddr_reg:x8; val_offset:639*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 639*FLEN/8, x10, x3, x5)

inst_236:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0cf and fs3 == 0 and fe3 == 0x0c and fm3 == 0x227 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391e; op2val:0xb4cf;
op3val:0x3227; valaddr_reg:x8; val_offset:642*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 642*FLEN/8, x10, x3, x5)

inst_237:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0cf and fs3 == 0 and fe3 == 0x0c and fm3 == 0x227 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391e; op2val:0xb4cf;
op3val:0x3227; valaddr_reg:x8; val_offset:645*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 645*FLEN/8, x10, x3, x5)

inst_238:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0cf and fs3 == 0 and fe3 == 0x0c and fm3 == 0x227 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391e; op2val:0xb4cf;
op3val:0x3227; valaddr_reg:x8; val_offset:648*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 648*FLEN/8, x10, x3, x5)

inst_239:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11e and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0cf and fs3 == 0 and fe3 == 0x0c and fm3 == 0x227 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391e; op2val:0xb4cf;
op3val:0x3227; valaddr_reg:x8; val_offset:651*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 651*FLEN/8, x10, x3, x5)

inst_240:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3eb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0b7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0ab and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37eb; op2val:0xb8b7;
op3val:0x34ab; valaddr_reg:x8; val_offset:654*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 654*FLEN/8, x10, x3, x5)

inst_241:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3eb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0b7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0ab and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37eb; op2val:0xb8b7;
op3val:0x34ab; valaddr_reg:x8; val_offset:657*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 657*FLEN/8, x10, x3, x5)

inst_242:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3eb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0b7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0ab and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37eb; op2val:0xb8b7;
op3val:0x34ab; valaddr_reg:x8; val_offset:660*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 660*FLEN/8, x10, x3, x5)

inst_243:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3eb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0b7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0ab and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37eb; op2val:0xb8b7;
op3val:0x34ab; valaddr_reg:x8; val_offset:663*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 663*FLEN/8, x10, x3, x5)

inst_244:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3eb and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0b7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0ab and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37eb; op2val:0xb8b7;
op3val:0x34ab; valaddr_reg:x8; val_offset:666*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 666*FLEN/8, x10, x3, x5)

inst_245:
// fs1 == 0 and fe1 == 0x09 and fm1 == 0x11d and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1dc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x37f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x251d; op2val:0xd1dc;
op3val:0x3b7f; valaddr_reg:x8; val_offset:669*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 669*FLEN/8, x10, x3, x5)

inst_246:
// fs1 == 0 and fe1 == 0x09 and fm1 == 0x11d and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1dc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x37f and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x251d; op2val:0xd1dc;
op3val:0x3b7f; valaddr_reg:x8; val_offset:672*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 672*FLEN/8, x10, x3, x5)

inst_247:
// fs1 == 0 and fe1 == 0x09 and fm1 == 0x11d and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1dc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x37f and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x251d; op2val:0xd1dc;
op3val:0x3b7f; valaddr_reg:x8; val_offset:675*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 675*FLEN/8, x10, x3, x5)

inst_248:
// fs1 == 0 and fe1 == 0x09 and fm1 == 0x11d and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1dc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x37f and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x251d; op2val:0xd1dc;
op3val:0x3b7f; valaddr_reg:x8; val_offset:678*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 678*FLEN/8, x10, x3, x5)

inst_249:
// fs1 == 0 and fe1 == 0x09 and fm1 == 0x11d and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1dc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x37f and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x251d; op2val:0xd1dc;
op3val:0x3b7f; valaddr_reg:x8; val_offset:681*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 681*FLEN/8, x10, x3, x5)

inst_250:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3dd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2fe and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2e0 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bdd; op2val:0xbafe;
op3val:0x3ae0; valaddr_reg:x8; val_offset:684*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 684*FLEN/8, x10, x3, x5)

inst_251:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3dd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2fe and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2e0 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bdd; op2val:0xbafe;
op3val:0x3ae0; valaddr_reg:x8; val_offset:687*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 687*FLEN/8, x10, x3, x5)

inst_252:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3dd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2fe and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2e0 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bdd; op2val:0xbafe;
op3val:0x3ae0; valaddr_reg:x8; val_offset:690*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 690*FLEN/8, x10, x3, x5)

inst_253:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3dd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2fe and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2e0 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bdd; op2val:0xbafe;
op3val:0x3ae0; valaddr_reg:x8; val_offset:693*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 693*FLEN/8, x10, x3, x5)

inst_254:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3dd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2fe and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2e0 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bdd; op2val:0xbafe;
op3val:0x3ae0; valaddr_reg:x8; val_offset:696*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 696*FLEN/8, x10, x3, x5)

inst_255:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x18f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2d2 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e8; op2val:0xb98f;
op3val:0x36d2; valaddr_reg:x8; val_offset:699*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 699*FLEN/8, x10, x3, x5)

inst_256:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x18f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2d2 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e8; op2val:0xb98f;
op3val:0x36d2; valaddr_reg:x8; val_offset:702*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 702*FLEN/8, x10, x3, x5)

inst_257:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x18f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2d2 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e8; op2val:0xb98f;
op3val:0x36d2; valaddr_reg:x8; val_offset:705*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 705*FLEN/8, x10, x3, x5)

inst_258:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x18f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2d2 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e8; op2val:0xb98f;
op3val:0x36d2; valaddr_reg:x8; val_offset:708*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 708*FLEN/8, x10, x3, x5)

inst_259:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x18f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2d2 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e8; op2val:0xb98f;
op3val:0x36d2; valaddr_reg:x8; val_offset:711*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 711*FLEN/8, x10, x3, x5)

inst_260:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x019 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x10f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x130 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3419; op2val:0xc10f;
op3val:0x3930; valaddr_reg:x8; val_offset:714*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 714*FLEN/8, x10, x3, x5)

inst_261:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x019 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x10f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x130 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3419; op2val:0xc10f;
op3val:0x3930; valaddr_reg:x8; val_offset:717*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 717*FLEN/8, x10, x3, x5)

inst_262:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x019 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x10f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x130 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3419; op2val:0xc10f;
op3val:0x3930; valaddr_reg:x8; val_offset:720*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 720*FLEN/8, x10, x3, x5)

inst_263:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x019 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x10f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x130 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3419; op2val:0xc10f;
op3val:0x3930; valaddr_reg:x8; val_offset:723*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 723*FLEN/8, x10, x3, x5)

inst_264:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x019 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x10f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x130 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3419; op2val:0xc10f;
op3val:0x3930; valaddr_reg:x8; val_offset:726*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 726*FLEN/8, x10, x3, x5)

inst_265:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x07e and fs2 == 1 and fe2 == 0x13 and fm2 == 0x31a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3f9 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x287e; op2val:0xcf1a;
op3val:0x3bf9; valaddr_reg:x8; val_offset:729*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 729*FLEN/8, x10, x3, x5)

inst_266:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x07e and fs2 == 1 and fe2 == 0x13 and fm2 == 0x31a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3f9 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x287e; op2val:0xcf1a;
op3val:0x3bf9; valaddr_reg:x8; val_offset:732*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 732*FLEN/8, x10, x3, x5)

inst_267:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x07e and fs2 == 1 and fe2 == 0x13 and fm2 == 0x31a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3f9 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x287e; op2val:0xcf1a;
op3val:0x3bf9; valaddr_reg:x8; val_offset:735*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 735*FLEN/8, x10, x3, x5)

inst_268:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x07e and fs2 == 1 and fe2 == 0x13 and fm2 == 0x31a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3f9 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x287e; op2val:0xcf1a;
op3val:0x3bf9; valaddr_reg:x8; val_offset:738*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 738*FLEN/8, x10, x3, x5)

inst_269:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x07e and fs2 == 1 and fe2 == 0x13 and fm2 == 0x31a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3f9 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x287e; op2val:0xcf1a;
op3val:0x3bf9; valaddr_reg:x8; val_offset:741*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 741*FLEN/8, x10, x3, x5)

inst_270:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x142 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0ce and fs3 == 0 and fe3 == 0x0e and fm3 == 0x251 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3142; op2val:0xc4ce;
op3val:0x3a51; valaddr_reg:x8; val_offset:744*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 744*FLEN/8, x10, x3, x5)

inst_271:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x142 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0ce and fs3 == 0 and fe3 == 0x0e and fm3 == 0x251 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3142; op2val:0xc4ce;
op3val:0x3a51; valaddr_reg:x8; val_offset:747*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 747*FLEN/8, x10, x3, x5)

inst_272:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x142 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0ce and fs3 == 0 and fe3 == 0x0e and fm3 == 0x251 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3142; op2val:0xc4ce;
op3val:0x3a51; valaddr_reg:x8; val_offset:750*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 750*FLEN/8, x10, x3, x5)

inst_273:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x142 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0ce and fs3 == 0 and fe3 == 0x0e and fm3 == 0x251 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3142; op2val:0xc4ce;
op3val:0x3a51; valaddr_reg:x8; val_offset:753*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 753*FLEN/8, x10, x3, x5)

inst_274:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x142 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0ce and fs3 == 0 and fe3 == 0x0e and fm3 == 0x251 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3142; op2val:0xc4ce;
op3val:0x3a51; valaddr_reg:x8; val_offset:756*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 756*FLEN/8, x10, x3, x5)

inst_275:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x11 and fm2 == 0x3be and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3bc and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ffd; op2val:0xc7be;
op3val:0x3bbc; valaddr_reg:x8; val_offset:759*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 759*FLEN/8, x10, x3, x5)

inst_276:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x11 and fm2 == 0x3be and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3bc and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ffd; op2val:0xc7be;
op3val:0x3bbc; valaddr_reg:x8; val_offset:762*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 762*FLEN/8, x10, x3, x5)

inst_277:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x11 and fm2 == 0x3be and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3bc and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ffd; op2val:0xc7be;
op3val:0x3bbc; valaddr_reg:x8; val_offset:765*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 765*FLEN/8, x10, x3, x5)

inst_278:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x11 and fm2 == 0x3be and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3bc and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ffd; op2val:0xc7be;
op3val:0x3bbc; valaddr_reg:x8; val_offset:768*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 768*FLEN/8, x10, x3, x5)

inst_279:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x11 and fm2 == 0x3be and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3bc and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ffd; op2val:0xc7be;
op3val:0x3bbc; valaddr_reg:x8; val_offset:771*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 771*FLEN/8, x10, x3, x5)
RVTEST_SIGBASE(x3,signature_x3_2)

inst_280:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x077 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2e6 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3b3 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2877; op2val:0xc6e6;
op3val:0x33b3; valaddr_reg:x8; val_offset:774*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 774*FLEN/8, x10, x3, x5)

inst_281:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x077 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2e6 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3b3 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2877; op2val:0xc6e6;
op3val:0x33b3; valaddr_reg:x8; val_offset:777*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 777*FLEN/8, x10, x3, x5)

inst_282:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x077 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2e6 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3b3 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2877; op2val:0xc6e6;
op3val:0x33b3; valaddr_reg:x8; val_offset:780*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 780*FLEN/8, x10, x3, x5)

inst_283:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x077 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2e6 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3b3 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2877; op2val:0xc6e6;
op3val:0x33b3; valaddr_reg:x8; val_offset:783*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 783*FLEN/8, x10, x3, x5)

inst_284:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x077 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2e6 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3b3 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2877; op2val:0xc6e6;
op3val:0x33b3; valaddr_reg:x8; val_offset:786*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 786*FLEN/8, x10, x3, x5)

inst_285:
// fs1 == 0 and fe1 == 0x08 and fm1 == 0x0ea and fs2 == 1 and fe2 == 0x14 and fm2 == 0x178 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b8 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x20ea; op2val:0xd178;
op3val:0x36b8; valaddr_reg:x8; val_offset:789*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 789*FLEN/8, x10, x3, x5)

inst_286:
// fs1 == 0 and fe1 == 0x08 and fm1 == 0x0ea and fs2 == 1 and fe2 == 0x14 and fm2 == 0x178 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b8 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x20ea; op2val:0xd178;
op3val:0x36b8; valaddr_reg:x8; val_offset:792*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 792*FLEN/8, x10, x3, x5)

inst_287:
// fs1 == 0 and fe1 == 0x08 and fm1 == 0x0ea and fs2 == 1 and fe2 == 0x14 and fm2 == 0x178 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b8 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x20ea; op2val:0xd178;
op3val:0x36b8; valaddr_reg:x8; val_offset:795*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 795*FLEN/8, x10, x3, x5)

inst_288:
// fs1 == 0 and fe1 == 0x08 and fm1 == 0x0ea and fs2 == 1 and fe2 == 0x14 and fm2 == 0x178 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b8 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x20ea; op2val:0xd178;
op3val:0x36b8; valaddr_reg:x8; val_offset:798*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 798*FLEN/8, x10, x3, x5)

inst_289:
// fs1 == 0 and fe1 == 0x08 and fm1 == 0x0ea and fs2 == 1 and fe2 == 0x14 and fm2 == 0x178 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b8 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x20ea; op2val:0xd178;
op3val:0x36b8; valaddr_reg:x8; val_offset:801*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 801*FLEN/8, x10, x3, x5)

inst_290:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x293 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x0b5 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x3ba and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a93; op2val:0xa8b5;
op3val:0x27ba; valaddr_reg:x8; val_offset:804*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 804*FLEN/8, x10, x3, x5)

inst_291:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x293 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x0b5 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x3ba and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a93; op2val:0xa8b5;
op3val:0x27ba; valaddr_reg:x8; val_offset:807*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 807*FLEN/8, x10, x3, x5)

inst_292:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x293 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x0b5 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x3ba and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a93; op2val:0xa8b5;
op3val:0x27ba; valaddr_reg:x8; val_offset:810*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 810*FLEN/8, x10, x3, x5)

inst_293:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x293 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x0b5 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x3ba and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a93; op2val:0xa8b5;
op3val:0x27ba; valaddr_reg:x8; val_offset:813*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 813*FLEN/8, x10, x3, x5)

inst_294:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x293 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x0b5 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x3ba and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a93; op2val:0xa8b5;
op3val:0x27ba; valaddr_reg:x8; val_offset:816*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 816*FLEN/8, x10, x3, x5)

inst_295:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x077 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x290 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x355 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3877; op2val:0xbe90;
op3val:0x3b55; valaddr_reg:x8; val_offset:819*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 819*FLEN/8, x10, x3, x5)

inst_296:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x077 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x290 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x355 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3877; op2val:0xbe90;
op3val:0x3b55; valaddr_reg:x8; val_offset:822*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 822*FLEN/8, x10, x3, x5)

inst_297:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x077 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x290 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x355 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3877; op2val:0xbe90;
op3val:0x3b55; valaddr_reg:x8; val_offset:825*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 825*FLEN/8, x10, x3, x5)

inst_298:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x077 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x290 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x355 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3877; op2val:0xbe90;
op3val:0x3b55; valaddr_reg:x8; val_offset:828*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 828*FLEN/8, x10, x3, x5)

inst_299:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x077 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x290 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x355 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3877; op2val:0xbe90;
op3val:0x3b55; valaddr_reg:x8; val_offset:831*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 831*FLEN/8, x10, x3, x5)

inst_300:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x250 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x118 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x005 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3650; op2val:0xbd18;
op3val:0x3805; valaddr_reg:x8; val_offset:834*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 834*FLEN/8, x10, x3, x5)

inst_301:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x250 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x118 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x005 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3650; op2val:0xbd18;
op3val:0x3805; valaddr_reg:x8; val_offset:837*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 837*FLEN/8, x10, x3, x5)

inst_302:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x250 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x118 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x005 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3650; op2val:0xbd18;
op3val:0x3805; valaddr_reg:x8; val_offset:840*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 840*FLEN/8, x10, x3, x5)

inst_303:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x250 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x118 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x005 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3650; op2val:0xbd18;
op3val:0x3805; valaddr_reg:x8; val_offset:843*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 843*FLEN/8, x10, x3, x5)

inst_304:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x250 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x118 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x005 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3650; op2val:0xbd18;
op3val:0x3805; valaddr_reg:x8; val_offset:846*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 846*FLEN/8, x10, x3, x5)

inst_305:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x036 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x26b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2c3 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3836; op2val:0xbe6b;
op3val:0x3ac3; valaddr_reg:x8; val_offset:849*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 849*FLEN/8, x10, x3, x5)

inst_306:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x036 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x26b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2c3 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3836; op2val:0xbe6b;
op3val:0x3ac3; valaddr_reg:x8; val_offset:852*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 852*FLEN/8, x10, x3, x5)

inst_307:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x036 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x26b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2c3 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3836; op2val:0xbe6b;
op3val:0x3ac3; valaddr_reg:x8; val_offset:855*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 855*FLEN/8, x10, x3, x5)

inst_308:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x036 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x26b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2c3 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3836; op2val:0xbe6b;
op3val:0x3ac3; valaddr_reg:x8; val_offset:858*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 858*FLEN/8, x10, x3, x5)

inst_309:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x036 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x26b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2c3 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3836; op2val:0xbe6b;
op3val:0x3ac3; valaddr_reg:x8; val_offset:861*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 861*FLEN/8, x10, x3, x5)

inst_310:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x306 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3a4 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b5 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b06; op2val:0xb7a4;
op3val:0x36b5; valaddr_reg:x8; val_offset:864*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 864*FLEN/8, x10, x3, x5)

inst_311:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x306 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3a4 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b5 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b06; op2val:0xb7a4;
op3val:0x36b5; valaddr_reg:x8; val_offset:867*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 867*FLEN/8, x10, x3, x5)

inst_312:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x306 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3a4 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b5 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b06; op2val:0xb7a4;
op3val:0x36b5; valaddr_reg:x8; val_offset:870*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 870*FLEN/8, x10, x3, x5)

inst_313:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x306 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3a4 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b5 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b06; op2val:0xb7a4;
op3val:0x36b5; valaddr_reg:x8; val_offset:873*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 873*FLEN/8, x10, x3, x5)

inst_314:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x306 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3a4 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b5 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b06; op2val:0xb7a4;
op3val:0x36b5; valaddr_reg:x8; val_offset:876*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 876*FLEN/8, x10, x3, x5)

inst_315:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x060 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x262 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2fd and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3860; op2val:0xbe62;
op3val:0x3afd; valaddr_reg:x8; val_offset:879*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 879*FLEN/8, x10, x3, x5)

inst_316:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x060 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x262 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2fd and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3860; op2val:0xbe62;
op3val:0x3afd; valaddr_reg:x8; val_offset:882*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 882*FLEN/8, x10, x3, x5)

inst_317:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x060 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x262 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2fd and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3860; op2val:0xbe62;
op3val:0x3afd; valaddr_reg:x8; val_offset:885*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 885*FLEN/8, x10, x3, x5)

inst_318:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x060 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x262 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2fd and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3860; op2val:0xbe62;
op3val:0x3afd; valaddr_reg:x8; val_offset:888*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 888*FLEN/8, x10, x3, x5)

inst_319:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x060 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x262 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2fd and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3860; op2val:0xbe62;
op3val:0x3afd; valaddr_reg:x8; val_offset:891*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 891*FLEN/8, x10, x3, x5)

inst_320:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3d6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x064 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x387b; op2val:0xb7d6;
op3val:0x3464; valaddr_reg:x8; val_offset:894*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 894*FLEN/8, x10, x3, x5)

inst_321:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3d6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x064 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x387b; op2val:0xb7d6;
op3val:0x3464; valaddr_reg:x8; val_offset:897*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 897*FLEN/8, x10, x3, x5)

inst_322:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3d6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x064 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x387b; op2val:0xb7d6;
op3val:0x3464; valaddr_reg:x8; val_offset:900*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 900*FLEN/8, x10, x3, x5)

inst_323:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3d6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x064 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x387b; op2val:0xb7d6;
op3val:0x3464; valaddr_reg:x8; val_offset:903*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 903*FLEN/8, x10, x3, x5)

inst_324:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x07b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3d6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x064 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x387b; op2val:0xb7d6;
op3val:0x3464; valaddr_reg:x8; val_offset:906*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 906*FLEN/8, x10, x3, x5)

inst_325:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x08d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x36e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x03a and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x348d; op2val:0xbf6e;
op3val:0x383a; valaddr_reg:x8; val_offset:909*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 909*FLEN/8, x10, x3, x5)

inst_326:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x08d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x36e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x03a and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x348d; op2val:0xbf6e;
op3val:0x383a; valaddr_reg:x8; val_offset:912*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 912*FLEN/8, x10, x3, x5)

inst_327:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x08d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x36e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x03a and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x348d; op2val:0xbf6e;
op3val:0x383a; valaddr_reg:x8; val_offset:915*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 915*FLEN/8, x10, x3, x5)

inst_328:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x08d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x36e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x03a and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x348d; op2val:0xbf6e;
op3val:0x383a; valaddr_reg:x8; val_offset:918*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 918*FLEN/8, x10, x3, x5)

inst_329:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x08d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x36e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x03a and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x348d; op2val:0xbf6e;
op3val:0x383a; valaddr_reg:x8; val_offset:921*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 921*FLEN/8, x10, x3, x5)

inst_330:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d9 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x037 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x11d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d9; op2val:0xbc37;
op3val:0x391d; valaddr_reg:x8; val_offset:924*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 924*FLEN/8, x10, x3, x5)

inst_331:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d9 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x037 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x11d and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d9; op2val:0xbc37;
op3val:0x391d; valaddr_reg:x8; val_offset:927*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 927*FLEN/8, x10, x3, x5)

inst_332:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d9 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x037 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x11d and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d9; op2val:0xbc37;
op3val:0x391d; valaddr_reg:x8; val_offset:930*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 930*FLEN/8, x10, x3, x5)

inst_333:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d9 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x037 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x11d and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d9; op2val:0xbc37;
op3val:0x391d; valaddr_reg:x8; val_offset:933*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 933*FLEN/8, x10, x3, x5)

inst_334:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d9 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x037 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x11d and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d9; op2val:0xbc37;
op3val:0x391d; valaddr_reg:x8; val_offset:936*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 936*FLEN/8, x10, x3, x5)

inst_335:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x232 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x025 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x26b and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a32; op2val:0xbc25;
op3val:0x3a6b; valaddr_reg:x8; val_offset:939*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 939*FLEN/8, x10, x3, x5)

inst_336:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x232 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x025 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x26b and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a32; op2val:0xbc25;
op3val:0x3a6b; valaddr_reg:x8; val_offset:942*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 942*FLEN/8, x10, x3, x5)

inst_337:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x232 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x025 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x26b and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a32; op2val:0xbc25;
op3val:0x3a6b; valaddr_reg:x8; val_offset:945*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 945*FLEN/8, x10, x3, x5)

inst_338:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x232 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x025 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x26b and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a32; op2val:0xbc25;
op3val:0x3a6b; valaddr_reg:x8; val_offset:948*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 948*FLEN/8, x10, x3, x5)

inst_339:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x232 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x025 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x26b and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a32; op2val:0xbc25;
op3val:0x3a6b; valaddr_reg:x8; val_offset:951*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 951*FLEN/8, x10, x3, x5)

inst_340:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x271 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x322 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x386e; op2val:0xbe71;
op3val:0x3b22; valaddr_reg:x8; val_offset:954*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 954*FLEN/8, x10, x3, x5)

inst_341:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x271 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x322 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x386e; op2val:0xbe71;
op3val:0x3b22; valaddr_reg:x8; val_offset:957*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 957*FLEN/8, x10, x3, x5)

inst_342:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x271 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x322 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x386e; op2val:0xbe71;
op3val:0x3b22; valaddr_reg:x8; val_offset:960*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 960*FLEN/8, x10, x3, x5)

inst_343:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x271 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x322 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x386e; op2val:0xbe71;
op3val:0x3b22; valaddr_reg:x8; val_offset:963*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 963*FLEN/8, x10, x3, x5)

inst_344:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x271 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x322 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x386e; op2val:0xbe71;
op3val:0x3b22; valaddr_reg:x8; val_offset:966*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 966*FLEN/8, x10, x3, x5)

inst_345:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x066 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0aa and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3466; op2val:0xbc3e;
op3val:0x34aa; valaddr_reg:x8; val_offset:969*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 969*FLEN/8, x10, x3, x5)

inst_346:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x066 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0aa and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3466; op2val:0xbc3e;
op3val:0x34aa; valaddr_reg:x8; val_offset:972*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 972*FLEN/8, x10, x3, x5)

inst_347:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x066 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0aa and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3466; op2val:0xbc3e;
op3val:0x34aa; valaddr_reg:x8; val_offset:975*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 975*FLEN/8, x10, x3, x5)

inst_348:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x066 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0aa and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3466; op2val:0xbc3e;
op3val:0x34aa; valaddr_reg:x8; val_offset:978*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 978*FLEN/8, x10, x3, x5)

inst_349:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x066 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x03e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0aa and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3466; op2val:0xbc3e;
op3val:0x34aa; valaddr_reg:x8; val_offset:981*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 981*FLEN/8, x10, x3, x5)

inst_350:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x237 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x108 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d1 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3637; op2val:0xc108;
op3val:0x3bd1; valaddr_reg:x8; val_offset:984*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 984*FLEN/8, x10, x3, x5)

inst_351:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x237 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x108 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d1 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3637; op2val:0xc108;
op3val:0x3bd1; valaddr_reg:x8; val_offset:987*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 987*FLEN/8, x10, x3, x5)

inst_352:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x237 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x108 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d1 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3637; op2val:0xc108;
op3val:0x3bd1; valaddr_reg:x8; val_offset:990*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 990*FLEN/8, x10, x3, x5)

inst_353:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x237 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x108 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d1 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3637; op2val:0xc108;
op3val:0x3bd1; valaddr_reg:x8; val_offset:993*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 993*FLEN/8, x10, x3, x5)

inst_354:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x237 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x108 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3d1 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3637; op2val:0xc108;
op3val:0x3bd1; valaddr_reg:x8; val_offset:996*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 996*FLEN/8, x10, x3, x5)

inst_355:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x116 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x324 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08a and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3916; op2val:0xbb24;
op3val:0x388a; valaddr_reg:x8; val_offset:999*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 999*FLEN/8, x10, x3, x5)

inst_356:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x116 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x324 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08a and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3916; op2val:0xbb24;
op3val:0x388a; valaddr_reg:x8; val_offset:1002*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1002*FLEN/8, x10, x3, x5)

inst_357:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x116 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x324 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08a and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3916; op2val:0xbb24;
op3val:0x388a; valaddr_reg:x8; val_offset:1005*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1005*FLEN/8, x10, x3, x5)

inst_358:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x116 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x324 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08a and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3916; op2val:0xbb24;
op3val:0x388a; valaddr_reg:x8; val_offset:1008*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1008*FLEN/8, x10, x3, x5)

inst_359:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x116 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x324 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08a and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3916; op2val:0xbb24;
op3val:0x388a; valaddr_reg:x8; val_offset:1011*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1011*FLEN/8, x10, x3, x5)

inst_360:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x340 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x090 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x021 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b40; op2val:0xa890;
op3val:0x2821; valaddr_reg:x8; val_offset:1014*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1014*FLEN/8, x10, x3, x5)

inst_361:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x340 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x090 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x021 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b40; op2val:0xa890;
op3val:0x2821; valaddr_reg:x8; val_offset:1017*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1017*FLEN/8, x10, x3, x5)

inst_362:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x340 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x090 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x021 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b40; op2val:0xa890;
op3val:0x2821; valaddr_reg:x8; val_offset:1020*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1020*FLEN/8, x10, x3, x5)

inst_363:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x340 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x090 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x021 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b40; op2val:0xa890;
op3val:0x2821; valaddr_reg:x8; val_offset:1023*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1023*FLEN/8, x10, x3, x5)

inst_364:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x340 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x090 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x021 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b40; op2val:0xa890;
op3val:0x2821; valaddr_reg:x8; val_offset:1026*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1026*FLEN/8, x10, x3, x5)

inst_365:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3d2 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x012 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3f5 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x33d2; op2val:0xc012;
op3val:0x37f5; valaddr_reg:x8; val_offset:1029*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1029*FLEN/8, x10, x3, x5)

inst_366:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3d2 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x012 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3f5 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x33d2; op2val:0xc012;
op3val:0x37f5; valaddr_reg:x8; val_offset:1032*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1032*FLEN/8, x10, x3, x5)

inst_367:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3d2 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x012 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3f5 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x33d2; op2val:0xc012;
op3val:0x37f5; valaddr_reg:x8; val_offset:1035*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1035*FLEN/8, x10, x3, x5)

inst_368:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3d2 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x012 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3f5 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x33d2; op2val:0xc012;
op3val:0x37f5; valaddr_reg:x8; val_offset:1038*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1038*FLEN/8, x10, x3, x5)

inst_369:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3d2 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x012 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3f5 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x33d2; op2val:0xc012;
op3val:0x37f5; valaddr_reg:x8; val_offset:1041*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1041*FLEN/8, x10, x3, x5)

inst_370:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b7 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x16c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x265 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34b7; op2val:0xc16c;
op3val:0x3a65; valaddr_reg:x8; val_offset:1044*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1044*FLEN/8, x10, x3, x5)

inst_371:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b7 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x16c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x265 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34b7; op2val:0xc16c;
op3val:0x3a65; valaddr_reg:x8; val_offset:1047*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1047*FLEN/8, x10, x3, x5)

inst_372:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b7 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x16c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x265 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34b7; op2val:0xc16c;
op3val:0x3a65; valaddr_reg:x8; val_offset:1050*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1050*FLEN/8, x10, x3, x5)

inst_373:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b7 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x16c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x265 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34b7; op2val:0xc16c;
op3val:0x3a65; valaddr_reg:x8; val_offset:1053*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1053*FLEN/8, x10, x3, x5)

inst_374:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0b7 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x16c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x265 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34b7; op2val:0xc16c;
op3val:0x3a65; valaddr_reg:x8; val_offset:1056*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1056*FLEN/8, x10, x3, x5)

inst_375:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x22a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ec and fs3 == 0 and fe3 == 0x0d and fm3 == 0x396 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a2a; op2val:0xb8ec;
op3val:0x3796; valaddr_reg:x8; val_offset:1059*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1059*FLEN/8, x10, x3, x5)

inst_376:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x22a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ec and fs3 == 0 and fe3 == 0x0d and fm3 == 0x396 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a2a; op2val:0xb8ec;
op3val:0x3796; valaddr_reg:x8; val_offset:1062*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1062*FLEN/8, x10, x3, x5)

inst_377:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x22a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ec and fs3 == 0 and fe3 == 0x0d and fm3 == 0x396 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a2a; op2val:0xb8ec;
op3val:0x3796; valaddr_reg:x8; val_offset:1065*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1065*FLEN/8, x10, x3, x5)

inst_378:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x22a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ec and fs3 == 0 and fe3 == 0x0d and fm3 == 0x396 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a2a; op2val:0xb8ec;
op3val:0x3796; valaddr_reg:x8; val_offset:1068*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1068*FLEN/8, x10, x3, x5)

inst_379:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x22a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ec and fs3 == 0 and fe3 == 0x0d and fm3 == 0x396 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a2a; op2val:0xb8ec;
op3val:0x3796; valaddr_reg:x8; val_offset:1071*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1071*FLEN/8, x10, x3, x5)

inst_380:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x018 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x182 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1a4 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3418; op2val:0xbd82;
op3val:0x35a4; valaddr_reg:x8; val_offset:1074*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1074*FLEN/8, x10, x3, x5)

inst_381:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x018 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x182 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1a4 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3418; op2val:0xbd82;
op3val:0x35a4; valaddr_reg:x8; val_offset:1077*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1077*FLEN/8, x10, x3, x5)

inst_382:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x018 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x182 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1a4 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3418; op2val:0xbd82;
op3val:0x35a4; valaddr_reg:x8; val_offset:1080*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1080*FLEN/8, x10, x3, x5)

inst_383:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x018 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x182 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1a4 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3418; op2val:0xbd82;
op3val:0x35a4; valaddr_reg:x8; val_offset:1083*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1083*FLEN/8, x10, x3, x5)

inst_384:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x018 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x182 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1a4 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3418; op2val:0xbd82;
op3val:0x35a4; valaddr_reg:x8; val_offset:1086*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1086*FLEN/8, x10, x3, x5)

inst_385:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f2 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x23b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x230 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bf2; op2val:0xb63b;
op3val:0x3630; valaddr_reg:x8; val_offset:1089*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1089*FLEN/8, x10, x3, x5)

inst_386:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f2 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x23b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x230 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bf2; op2val:0xb63b;
op3val:0x3630; valaddr_reg:x8; val_offset:1092*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1092*FLEN/8, x10, x3, x5)

inst_387:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f2 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x23b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x230 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bf2; op2val:0xb63b;
op3val:0x3630; valaddr_reg:x8; val_offset:1095*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1095*FLEN/8, x10, x3, x5)

inst_388:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f2 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x23b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x230 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bf2; op2val:0xb63b;
op3val:0x3630; valaddr_reg:x8; val_offset:1098*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1098*FLEN/8, x10, x3, x5)

inst_389:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3f2 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x23b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x230 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bf2; op2val:0xb63b;
op3val:0x3630; valaddr_reg:x8; val_offset:1101*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1101*FLEN/8, x10, x3, x5)

inst_390:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1d6 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1a1 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x01b and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2dd6; op2val:0xc1a1;
op3val:0x341b; valaddr_reg:x8; val_offset:1104*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1104*FLEN/8, x10, x3, x5)

inst_391:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1d6 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1a1 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x01b and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2dd6; op2val:0xc1a1;
op3val:0x341b; valaddr_reg:x8; val_offset:1107*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1107*FLEN/8, x10, x3, x5)

inst_392:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1d6 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1a1 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x01b and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2dd6; op2val:0xc1a1;
op3val:0x341b; valaddr_reg:x8; val_offset:1110*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1110*FLEN/8, x10, x3, x5)

inst_393:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1d6 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1a1 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x01b and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2dd6; op2val:0xc1a1;
op3val:0x341b; valaddr_reg:x8; val_offset:1113*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1113*FLEN/8, x10, x3, x5)

inst_394:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x1d6 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1a1 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x01b and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2dd6; op2val:0xc1a1;
op3val:0x341b; valaddr_reg:x8; val_offset:1116*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1116*FLEN/8, x10, x3, x5)

inst_395:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0a3 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x00f and fs3 == 0 and fe3 == 0x09 and fm3 == 0x0b1 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ca3; op2val:0xb40f;
op3val:0x24b1; valaddr_reg:x8; val_offset:1119*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1119*FLEN/8, x10, x3, x5)

inst_396:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0a3 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x00f and fs3 == 0 and fe3 == 0x09 and fm3 == 0x0b1 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ca3; op2val:0xb40f;
op3val:0x24b1; valaddr_reg:x8; val_offset:1122*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1122*FLEN/8, x10, x3, x5)

inst_397:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0a3 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x00f and fs3 == 0 and fe3 == 0x09 and fm3 == 0x0b1 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ca3; op2val:0xb40f;
op3val:0x24b1; valaddr_reg:x8; val_offset:1125*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1125*FLEN/8, x10, x3, x5)

inst_398:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0a3 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x00f and fs3 == 0 and fe3 == 0x09 and fm3 == 0x0b1 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ca3; op2val:0xb40f;
op3val:0x24b1; valaddr_reg:x8; val_offset:1128*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1128*FLEN/8, x10, x3, x5)

inst_399:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0a3 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x00f and fs3 == 0 and fe3 == 0x09 and fm3 == 0x0b1 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ca3; op2val:0xb40f;
op3val:0x24b1; valaddr_reg:x8; val_offset:1131*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1131*FLEN/8, x10, x3, x5)

inst_400:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x235 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x340 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a0 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a35; op2val:0xbb40;
op3val:0x39a0; valaddr_reg:x8; val_offset:1134*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1134*FLEN/8, x10, x3, x5)

inst_401:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x235 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x340 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a0 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a35; op2val:0xbb40;
op3val:0x39a0; valaddr_reg:x8; val_offset:1137*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1137*FLEN/8, x10, x3, x5)

inst_402:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x235 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x340 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a0 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a35; op2val:0xbb40;
op3val:0x39a0; valaddr_reg:x8; val_offset:1140*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1140*FLEN/8, x10, x3, x5)

inst_403:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x235 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x340 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a0 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a35; op2val:0xbb40;
op3val:0x39a0; valaddr_reg:x8; val_offset:1143*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1143*FLEN/8, x10, x3, x5)

inst_404:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x235 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x340 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a0 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a35; op2val:0xbb40;
op3val:0x39a0; valaddr_reg:x8; val_offset:1146*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1146*FLEN/8, x10, x3, x5)

inst_405:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x33e and fs2 == 1 and fe2 == 0x0a and fm2 == 0x297 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x1f4 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x373e; op2val:0xaa97;
op3val:0x25f4; valaddr_reg:x8; val_offset:1149*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1149*FLEN/8, x10, x3, x5)

inst_406:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x33e and fs2 == 1 and fe2 == 0x0a and fm2 == 0x297 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x1f4 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x373e; op2val:0xaa97;
op3val:0x25f4; valaddr_reg:x8; val_offset:1152*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1152*FLEN/8, x10, x3, x5)

inst_407:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x33e and fs2 == 1 and fe2 == 0x0a and fm2 == 0x297 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x1f4 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x373e; op2val:0xaa97;
op3val:0x25f4; valaddr_reg:x8; val_offset:1155*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1155*FLEN/8, x10, x3, x5)
RVTEST_SIGBASE(x3,signature_x3_3)

inst_408:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x33e and fs2 == 1 and fe2 == 0x0a and fm2 == 0x297 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x1f4 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x373e; op2val:0xaa97;
op3val:0x25f4; valaddr_reg:x8; val_offset:1158*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1158*FLEN/8, x10, x3, x5)

inst_409:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x33e and fs2 == 1 and fe2 == 0x0a and fm2 == 0x297 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x1f4 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x373e; op2val:0xaa97;
op3val:0x25f4; valaddr_reg:x8; val_offset:1161*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1161*FLEN/8, x10, x3, x5)

inst_410:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10b and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1f4 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x381 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x390b; op2val:0xadf4;
op3val:0x2b81; valaddr_reg:x8; val_offset:1164*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1164*FLEN/8, x10, x3, x5)

inst_411:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10b and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1f4 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x381 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x390b; op2val:0xadf4;
op3val:0x2b81; valaddr_reg:x8; val_offset:1167*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1167*FLEN/8, x10, x3, x5)

inst_412:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10b and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1f4 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x381 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x390b; op2val:0xadf4;
op3val:0x2b81; valaddr_reg:x8; val_offset:1170*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1170*FLEN/8, x10, x3, x5)

inst_413:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10b and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1f4 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x381 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x390b; op2val:0xadf4;
op3val:0x2b81; valaddr_reg:x8; val_offset:1173*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1173*FLEN/8, x10, x3, x5)

inst_414:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10b and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1f4 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x381 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x390b; op2val:0xadf4;
op3val:0x2b81; valaddr_reg:x8; val_offset:1176*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1176*FLEN/8, x10, x3, x5)

inst_415:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0c9 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x278 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3bd and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30c9; op2val:0xc278;
op3val:0x37bd; valaddr_reg:x8; val_offset:1179*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1179*FLEN/8, x10, x3, x5)

inst_416:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0c9 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x278 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3bd and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30c9; op2val:0xc278;
op3val:0x37bd; valaddr_reg:x8; val_offset:1182*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1182*FLEN/8, x10, x3, x5)

inst_417:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0c9 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x278 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3bd and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30c9; op2val:0xc278;
op3val:0x37bd; valaddr_reg:x8; val_offset:1185*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1185*FLEN/8, x10, x3, x5)

inst_418:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0c9 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x278 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3bd and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30c9; op2val:0xc278;
op3val:0x37bd; valaddr_reg:x8; val_offset:1188*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1188*FLEN/8, x10, x3, x5)

inst_419:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0c9 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x278 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3bd and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30c9; op2val:0xc278;
op3val:0x37bd; valaddr_reg:x8; val_offset:1191*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1191*FLEN/8, x10, x3, x5)

inst_420:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x0b and fm2 == 0x358 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x180 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ff; op2val:0xaf58;
op3val:0x2980; valaddr_reg:x8; val_offset:1194*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1194*FLEN/8, x10, x3, x5)

inst_421:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x0b and fm2 == 0x358 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x180 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ff; op2val:0xaf58;
op3val:0x2980; valaddr_reg:x8; val_offset:1197*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1197*FLEN/8, x10, x3, x5)

inst_422:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x0b and fm2 == 0x358 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x180 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ff; op2val:0xaf58;
op3val:0x2980; valaddr_reg:x8; val_offset:1200*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1200*FLEN/8, x10, x3, x5)

inst_423:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x0b and fm2 == 0x358 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x180 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ff; op2val:0xaf58;
op3val:0x2980; valaddr_reg:x8; val_offset:1203*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1203*FLEN/8, x10, x3, x5)

inst_424:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ff and fs2 == 1 and fe2 == 0x0b and fm2 == 0x358 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x180 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ff; op2val:0xaf58;
op3val:0x2980; valaddr_reg:x8; val_offset:1206*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1206*FLEN/8, x10, x3, x5)

inst_425:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x10 and fm2 == 0x27f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a2 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32ef; op2val:0xc27f;
op3val:0x39a2; valaddr_reg:x8; val_offset:1209*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1209*FLEN/8, x10, x3, x5)

inst_426:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x10 and fm2 == 0x27f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a2 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32ef; op2val:0xc27f;
op3val:0x39a2; valaddr_reg:x8; val_offset:1212*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1212*FLEN/8, x10, x3, x5)

inst_427:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x10 and fm2 == 0x27f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a2 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32ef; op2val:0xc27f;
op3val:0x39a2; valaddr_reg:x8; val_offset:1215*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1215*FLEN/8, x10, x3, x5)

inst_428:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x10 and fm2 == 0x27f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a2 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32ef; op2val:0xc27f;
op3val:0x39a2; valaddr_reg:x8; val_offset:1218*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1218*FLEN/8, x10, x3, x5)

inst_429:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x10 and fm2 == 0x27f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a2 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32ef; op2val:0xc27f;
op3val:0x39a2; valaddr_reg:x8; val_offset:1221*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1221*FLEN/8, x10, x3, x5)

inst_430:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x136 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x26f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30f0; op2val:0xc536;
op3val:0x3a6f; valaddr_reg:x8; val_offset:1224*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1224*FLEN/8, x10, x3, x5)

inst_431:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x136 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x26f and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30f0; op2val:0xc536;
op3val:0x3a6f; valaddr_reg:x8; val_offset:1227*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1227*FLEN/8, x10, x3, x5)

inst_432:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x136 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x26f and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30f0; op2val:0xc536;
op3val:0x3a6f; valaddr_reg:x8; val_offset:1230*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1230*FLEN/8, x10, x3, x5)

inst_433:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x136 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x26f and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30f0; op2val:0xc536;
op3val:0x3a6f; valaddr_reg:x8; val_offset:1233*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1233*FLEN/8, x10, x3, x5)

inst_434:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0f0 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x136 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x26f and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30f0; op2val:0xc536;
op3val:0x3a6f; valaddr_reg:x8; val_offset:1236*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1236*FLEN/8, x10, x3, x5)

inst_435:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10a and fs2 == 1 and fe2 == 0x0b and fm2 == 0x037 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x14e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x390a; op2val:0xac37;
op3val:0x294e; valaddr_reg:x8; val_offset:1239*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1239*FLEN/8, x10, x3, x5)

inst_436:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10a and fs2 == 1 and fe2 == 0x0b and fm2 == 0x037 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x14e and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x390a; op2val:0xac37;
op3val:0x294e; valaddr_reg:x8; val_offset:1242*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1242*FLEN/8, x10, x3, x5)

inst_437:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10a and fs2 == 1 and fe2 == 0x0b and fm2 == 0x037 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x14e and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x390a; op2val:0xac37;
op3val:0x294e; valaddr_reg:x8; val_offset:1245*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1245*FLEN/8, x10, x3, x5)

inst_438:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10a and fs2 == 1 and fe2 == 0x0b and fm2 == 0x037 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x14e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x390a; op2val:0xac37;
op3val:0x294e; valaddr_reg:x8; val_offset:1248*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1248*FLEN/8, x10, x3, x5)

inst_439:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x10a and fs2 == 1 and fe2 == 0x0b and fm2 == 0x037 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x14e and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x390a; op2val:0xac37;
op3val:0x294e; valaddr_reg:x8; val_offset:1251*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1251*FLEN/8, x10, x3, x5)

inst_440:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0e5 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x07f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x181 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30e5; op2val:0xc47f;
op3val:0x3981; valaddr_reg:x8; val_offset:1254*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1254*FLEN/8, x10, x3, x5)

inst_441:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0e5 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x07f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x181 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30e5; op2val:0xc47f;
op3val:0x3981; valaddr_reg:x8; val_offset:1257*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1257*FLEN/8, x10, x3, x5)

inst_442:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0e5 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x07f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x181 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30e5; op2val:0xc47f;
op3val:0x3981; valaddr_reg:x8; val_offset:1260*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1260*FLEN/8, x10, x3, x5)

inst_443:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0e5 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x07f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x181 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30e5; op2val:0xc47f;
op3val:0x3981; valaddr_reg:x8; val_offset:1263*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1263*FLEN/8, x10, x3, x5)

inst_444:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0e5 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x07f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x181 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30e5; op2val:0xc47f;
op3val:0x3981; valaddr_reg:x8; val_offset:1266*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1266*FLEN/8, x10, x3, x5)

inst_445:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ad and fs2 == 1 and fe2 == 0x0e and fm2 == 0x05d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x231 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ad; op2val:0xb85d;
op3val:0x3631; valaddr_reg:x8; val_offset:1269*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1269*FLEN/8, x10, x3, x5)

inst_446:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ad and fs2 == 1 and fe2 == 0x0e and fm2 == 0x05d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x231 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ad; op2val:0xb85d;
op3val:0x3631; valaddr_reg:x8; val_offset:1272*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1272*FLEN/8, x10, x3, x5)

inst_447:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ad and fs2 == 1 and fe2 == 0x0e and fm2 == 0x05d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x231 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ad; op2val:0xb85d;
op3val:0x3631; valaddr_reg:x8; val_offset:1275*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1275*FLEN/8, x10, x3, x5)

inst_448:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ad and fs2 == 1 and fe2 == 0x0e and fm2 == 0x05d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x231 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ad; op2val:0xb85d;
op3val:0x3631; valaddr_reg:x8; val_offset:1278*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1278*FLEN/8, x10, x3, x5)

inst_449:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ad and fs2 == 1 and fe2 == 0x0e and fm2 == 0x05d and fs3 == 0 and fe3 == 0x0d and fm3 == 0x231 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ad; op2val:0xb85d;
op3val:0x3631; valaddr_reg:x8; val_offset:1281*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1281*FLEN/8, x10, x3, x5)

inst_450:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x109 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x003 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x10d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3109; op2val:0xc003;
op3val:0x350d; valaddr_reg:x8; val_offset:1284*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1284*FLEN/8, x10, x3, x5)

inst_451:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x109 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x003 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x10d and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3109; op2val:0xc003;
op3val:0x350d; valaddr_reg:x8; val_offset:1287*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1287*FLEN/8, x10, x3, x5)

inst_452:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x109 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x003 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x10d and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3109; op2val:0xc003;
op3val:0x350d; valaddr_reg:x8; val_offset:1290*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1290*FLEN/8, x10, x3, x5)

inst_453:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x109 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x003 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x10d and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3109; op2val:0xc003;
op3val:0x350d; valaddr_reg:x8; val_offset:1293*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1293*FLEN/8, x10, x3, x5)

inst_454:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x109 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x003 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x10d and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3109; op2val:0xc003;
op3val:0x350d; valaddr_reg:x8; val_offset:1296*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1296*FLEN/8, x10, x3, x5)

inst_455:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x018 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x040 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x05a and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c18; op2val:0xc440;
op3val:0x345a; valaddr_reg:x8; val_offset:1299*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1299*FLEN/8, x10, x3, x5)

inst_456:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x018 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x040 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x05a and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c18; op2val:0xc440;
op3val:0x345a; valaddr_reg:x8; val_offset:1302*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1302*FLEN/8, x10, x3, x5)

inst_457:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x018 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x040 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x05a and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c18; op2val:0xc440;
op3val:0x345a; valaddr_reg:x8; val_offset:1305*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1305*FLEN/8, x10, x3, x5)

inst_458:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x018 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x040 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x05a and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c18; op2val:0xc440;
op3val:0x345a; valaddr_reg:x8; val_offset:1308*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1308*FLEN/8, x10, x3, x5)

inst_459:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x018 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x040 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x05a and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c18; op2val:0xc440;
op3val:0x345a; valaddr_reg:x8; val_offset:1311*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1311*FLEN/8, x10, x3, x5)

inst_460:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1bb and fs2 == 1 and fe2 == 0x10 and fm2 == 0x069 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x252 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31bb; op2val:0xc069;
op3val:0x3652; valaddr_reg:x8; val_offset:1314*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1314*FLEN/8, x10, x3, x5)

inst_461:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1bb and fs2 == 1 and fe2 == 0x10 and fm2 == 0x069 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x252 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31bb; op2val:0xc069;
op3val:0x3652; valaddr_reg:x8; val_offset:1317*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1317*FLEN/8, x10, x3, x5)

inst_462:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1bb and fs2 == 1 and fe2 == 0x10 and fm2 == 0x069 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x252 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31bb; op2val:0xc069;
op3val:0x3652; valaddr_reg:x8; val_offset:1320*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1320*FLEN/8, x10, x3, x5)

inst_463:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1bb and fs2 == 1 and fe2 == 0x10 and fm2 == 0x069 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x252 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31bb; op2val:0xc069;
op3val:0x3652; valaddr_reg:x8; val_offset:1323*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1323*FLEN/8, x10, x3, x5)

inst_464:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1bb and fs2 == 1 and fe2 == 0x10 and fm2 == 0x069 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x252 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31bb; op2val:0xc069;
op3val:0x3652; valaddr_reg:x8; val_offset:1326*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1326*FLEN/8, x10, x3, x5)

inst_465:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x32e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x094 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391a; op2val:0xbb2e;
op3val:0x3894; valaddr_reg:x8; val_offset:1329*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1329*FLEN/8, x10, x3, x5)

inst_466:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x32e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x094 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391a; op2val:0xbb2e;
op3val:0x3894; valaddr_reg:x8; val_offset:1332*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1332*FLEN/8, x10, x3, x5)

inst_467:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x32e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x094 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391a; op2val:0xbb2e;
op3val:0x3894; valaddr_reg:x8; val_offset:1335*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1335*FLEN/8, x10, x3, x5)

inst_468:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x32e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x094 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391a; op2val:0xbb2e;
op3val:0x3894; valaddr_reg:x8; val_offset:1338*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1338*FLEN/8, x10, x3, x5)

inst_469:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x32e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x094 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391a; op2val:0xbb2e;
op3val:0x3894; valaddr_reg:x8; val_offset:1341*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1341*FLEN/8, x10, x3, x5)

inst_470:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x014 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x363 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x389 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3814; op2val:0xbb63;
op3val:0x3789; valaddr_reg:x8; val_offset:1344*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1344*FLEN/8, x10, x3, x5)

inst_471:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x014 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x363 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x389 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3814; op2val:0xbb63;
op3val:0x3789; valaddr_reg:x8; val_offset:1347*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1347*FLEN/8, x10, x3, x5)

inst_472:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x014 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x363 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x389 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3814; op2val:0xbb63;
op3val:0x3789; valaddr_reg:x8; val_offset:1350*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1350*FLEN/8, x10, x3, x5)

inst_473:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x014 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x363 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x389 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3814; op2val:0xbb63;
op3val:0x3789; valaddr_reg:x8; val_offset:1353*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1353*FLEN/8, x10, x3, x5)

inst_474:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x014 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x363 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x389 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3814; op2val:0xbb63;
op3val:0x3789; valaddr_reg:x8; val_offset:1356*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1356*FLEN/8, x10, x3, x5)

inst_475:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x12d and fs2 == 1 and fe2 == 0x11 and fm2 == 0x084 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1d9 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x312d; op2val:0xc484;
op3val:0x39d9; valaddr_reg:x8; val_offset:1359*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1359*FLEN/8, x10, x3, x5)

inst_476:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x12d and fs2 == 1 and fe2 == 0x11 and fm2 == 0x084 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1d9 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x312d; op2val:0xc484;
op3val:0x39d9; valaddr_reg:x8; val_offset:1362*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1362*FLEN/8, x10, x3, x5)

inst_477:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x12d and fs2 == 1 and fe2 == 0x11 and fm2 == 0x084 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1d9 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x312d; op2val:0xc484;
op3val:0x39d9; valaddr_reg:x8; val_offset:1365*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1365*FLEN/8, x10, x3, x5)

inst_478:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x12d and fs2 == 1 and fe2 == 0x11 and fm2 == 0x084 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1d9 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x312d; op2val:0xc484;
op3val:0x39d9; valaddr_reg:x8; val_offset:1368*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1368*FLEN/8, x10, x3, x5)

inst_479:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x12d and fs2 == 1 and fe2 == 0x11 and fm2 == 0x084 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1d9 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x312d; op2val:0xc484;
op3val:0x39d9; valaddr_reg:x8; val_offset:1371*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1371*FLEN/8, x10, x3, x5)

inst_480:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x373 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x095 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x045 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b73; op2val:0xb495;
op3val:0x3445; valaddr_reg:x8; val_offset:1374*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1374*FLEN/8, x10, x3, x5)

inst_481:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x373 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x095 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x045 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b73; op2val:0xb495;
op3val:0x3445; valaddr_reg:x8; val_offset:1377*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1377*FLEN/8, x10, x3, x5)

inst_482:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x373 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x095 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x045 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b73; op2val:0xb495;
op3val:0x3445; valaddr_reg:x8; val_offset:1380*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1380*FLEN/8, x10, x3, x5)

inst_483:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x373 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x095 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x045 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b73; op2val:0xb495;
op3val:0x3445; valaddr_reg:x8; val_offset:1383*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1383*FLEN/8, x10, x3, x5)

inst_484:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x373 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x095 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x045 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b73; op2val:0xb495;
op3val:0x3445; valaddr_reg:x8; val_offset:1386*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1386*FLEN/8, x10, x3, x5)

inst_485:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x25e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a4 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39d5; op2val:0xba5e;
op3val:0x38a4; valaddr_reg:x8; val_offset:1389*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1389*FLEN/8, x10, x3, x5)

inst_486:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x25e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a4 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39d5; op2val:0xba5e;
op3val:0x38a4; valaddr_reg:x8; val_offset:1392*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1392*FLEN/8, x10, x3, x5)

inst_487:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x25e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a4 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39d5; op2val:0xba5e;
op3val:0x38a4; valaddr_reg:x8; val_offset:1395*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1395*FLEN/8, x10, x3, x5)

inst_488:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x25e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a4 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39d5; op2val:0xba5e;
op3val:0x38a4; valaddr_reg:x8; val_offset:1398*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1398*FLEN/8, x10, x3, x5)

inst_489:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x25e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0a4 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39d5; op2val:0xba5e;
op3val:0x38a4; valaddr_reg:x8; val_offset:1401*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1401*FLEN/8, x10, x3, x5)

inst_490:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x310 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x230 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x176 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b10; op2val:0xb230;
op3val:0x3176; valaddr_reg:x8; val_offset:1404*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1404*FLEN/8, x10, x3, x5)

inst_491:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x310 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x230 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x176 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b10; op2val:0xb230;
op3val:0x3176; valaddr_reg:x8; val_offset:1407*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1407*FLEN/8, x10, x3, x5)

inst_492:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x310 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x230 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x176 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b10; op2val:0xb230;
op3val:0x3176; valaddr_reg:x8; val_offset:1410*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1410*FLEN/8, x10, x3, x5)

inst_493:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x310 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x230 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x176 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b10; op2val:0xb230;
op3val:0x3176; valaddr_reg:x8; val_offset:1413*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1413*FLEN/8, x10, x3, x5)

inst_494:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x310 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x230 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x176 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b10; op2val:0xb230;
op3val:0x3176; valaddr_reg:x8; val_offset:1416*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1416*FLEN/8, x10, x3, x5)

inst_495:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ce and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ce and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1aa and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ce; op2val:0xbbce;
op3val:0x39aa; valaddr_reg:x8; val_offset:1419*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1419*FLEN/8, x10, x3, x5)

inst_496:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ce and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ce and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1aa and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ce; op2val:0xbbce;
op3val:0x39aa; valaddr_reg:x8; val_offset:1422*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1422*FLEN/8, x10, x3, x5)

inst_497:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ce and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ce and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1aa and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ce; op2val:0xbbce;
op3val:0x39aa; valaddr_reg:x8; val_offset:1425*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1425*FLEN/8, x10, x3, x5)

inst_498:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ce and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ce and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1aa and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ce; op2val:0xbbce;
op3val:0x39aa; valaddr_reg:x8; val_offset:1428*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1428*FLEN/8, x10, x3, x5)

inst_499:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ce and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ce and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1aa and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ce; op2val:0xbbce;
op3val:0x39aa; valaddr_reg:x8; val_offset:1431*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1431*FLEN/8, x10, x3, x5)

inst_500:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x244 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x110 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3ee and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3244; op2val:0xc110;
op3val:0x37ee; valaddr_reg:x8; val_offset:1434*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1434*FLEN/8, x10, x3, x5)

inst_501:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x244 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x110 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3ee and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3244; op2val:0xc110;
op3val:0x37ee; valaddr_reg:x8; val_offset:1437*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1437*FLEN/8, x10, x3, x5)

inst_502:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x244 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x110 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3ee and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3244; op2val:0xc110;
op3val:0x37ee; valaddr_reg:x8; val_offset:1440*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1440*FLEN/8, x10, x3, x5)

inst_503:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x244 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x110 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3ee and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3244; op2val:0xc110;
op3val:0x37ee; valaddr_reg:x8; val_offset:1443*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1443*FLEN/8, x10, x3, x5)

inst_504:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x244 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x110 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3ee and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3244; op2val:0xc110;
op3val:0x37ee; valaddr_reg:x8; val_offset:1446*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1446*FLEN/8, x10, x3, x5)

inst_505:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c8 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0f1 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x325 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39c8; op2val:0xb0f1;
op3val:0x2f25; valaddr_reg:x8; val_offset:1449*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1449*FLEN/8, x10, x3, x5)

inst_506:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c8 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0f1 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x325 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39c8; op2val:0xb0f1;
op3val:0x2f25; valaddr_reg:x8; val_offset:1452*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1452*FLEN/8, x10, x3, x5)

inst_507:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c8 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0f1 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x325 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39c8; op2val:0xb0f1;
op3val:0x2f25; valaddr_reg:x8; val_offset:1455*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1455*FLEN/8, x10, x3, x5)

inst_508:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c8 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0f1 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x325 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39c8; op2val:0xb0f1;
op3val:0x2f25; valaddr_reg:x8; val_offset:1458*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1458*FLEN/8, x10, x3, x5)

inst_509:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1c8 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0f1 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x325 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39c8; op2val:0xb0f1;
op3val:0x2f25; valaddr_reg:x8; val_offset:1461*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1461*FLEN/8, x10, x3, x5)

inst_510:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0b4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x057 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x11b and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38b4; op2val:0xbc57;
op3val:0x391b; valaddr_reg:x8; val_offset:1464*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1464*FLEN/8, x10, x3, x5)

inst_511:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0b4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x057 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x11b and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38b4; op2val:0xbc57;
op3val:0x391b; valaddr_reg:x8; val_offset:1467*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1467*FLEN/8, x10, x3, x5)

inst_512:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0b4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x057 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x11b and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38b4; op2val:0xbc57;
op3val:0x391b; valaddr_reg:x8; val_offset:1470*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1470*FLEN/8, x10, x3, x5)

inst_513:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0b4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x057 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x11b and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38b4; op2val:0xbc57;
op3val:0x391b; valaddr_reg:x8; val_offset:1473*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1473*FLEN/8, x10, x3, x5)

inst_514:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0b4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x057 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x11b and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38b4; op2val:0xbc57;
op3val:0x391b; valaddr_reg:x8; val_offset:1476*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1476*FLEN/8, x10, x3, x5)

inst_515:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x06d and fs2 == 1 and fe2 == 0x11 and fm2 == 0x211 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2b7 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x286d; op2val:0xc611;
op3val:0x32b7; valaddr_reg:x8; val_offset:1479*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1479*FLEN/8, x10, x3, x5)

inst_516:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x06d and fs2 == 1 and fe2 == 0x11 and fm2 == 0x211 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2b7 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x286d; op2val:0xc611;
op3val:0x32b7; valaddr_reg:x8; val_offset:1482*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1482*FLEN/8, x10, x3, x5)

inst_517:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x06d and fs2 == 1 and fe2 == 0x11 and fm2 == 0x211 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2b7 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x286d; op2val:0xc611;
op3val:0x32b7; valaddr_reg:x8; val_offset:1485*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1485*FLEN/8, x10, x3, x5)

inst_518:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x06d and fs2 == 1 and fe2 == 0x11 and fm2 == 0x211 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2b7 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x286d; op2val:0xc611;
op3val:0x32b7; valaddr_reg:x8; val_offset:1488*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1488*FLEN/8, x10, x3, x5)

inst_519:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x06d and fs2 == 1 and fe2 == 0x11 and fm2 == 0x211 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2b7 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x286d; op2val:0xc611;
op3val:0x32b7; valaddr_reg:x8; val_offset:1491*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1491*FLEN/8, x10, x3, x5)

inst_520:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x00a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1f0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x200 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x340a; op2val:0xc1f0;
op3val:0x3a00; valaddr_reg:x8; val_offset:1494*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1494*FLEN/8, x10, x3, x5)

inst_521:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x00a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1f0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x200 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x340a; op2val:0xc1f0;
op3val:0x3a00; valaddr_reg:x8; val_offset:1497*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1497*FLEN/8, x10, x3, x5)

inst_522:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x00a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1f0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x200 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x340a; op2val:0xc1f0;
op3val:0x3a00; valaddr_reg:x8; val_offset:1500*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1500*FLEN/8, x10, x3, x5)

inst_523:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x00a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1f0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x200 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x340a; op2val:0xc1f0;
op3val:0x3a00; valaddr_reg:x8; val_offset:1503*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1503*FLEN/8, x10, x3, x5)

inst_524:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x00a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1f0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x200 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x340a; op2val:0xc1f0;
op3val:0x3a00; valaddr_reg:x8; val_offset:1506*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1506*FLEN/8, x10, x3, x5)

inst_525:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x052 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x274 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31f9; op2val:0xc052;
op3val:0x3674; valaddr_reg:x8; val_offset:1509*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1509*FLEN/8, x10, x3, x5)

inst_526:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x052 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x274 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31f9; op2val:0xc052;
op3val:0x3674; valaddr_reg:x8; val_offset:1512*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1512*FLEN/8, x10, x3, x5)

inst_527:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x052 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x274 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31f9; op2val:0xc052;
op3val:0x3674; valaddr_reg:x8; val_offset:1515*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1515*FLEN/8, x10, x3, x5)

inst_528:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x052 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x274 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31f9; op2val:0xc052;
op3val:0x3674; valaddr_reg:x8; val_offset:1518*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1518*FLEN/8, x10, x3, x5)

inst_529:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x052 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x274 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31f9; op2val:0xc052;
op3val:0x3674; valaddr_reg:x8; val_offset:1521*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1521*FLEN/8, x10, x3, x5)

inst_530:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x173 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x36c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x10e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3173; op2val:0xc36c;
op3val:0x390e; valaddr_reg:x8; val_offset:1524*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1524*FLEN/8, x10, x3, x5)

inst_531:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x173 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x36c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x10e and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3173; op2val:0xc36c;
op3val:0x390e; valaddr_reg:x8; val_offset:1527*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1527*FLEN/8, x10, x3, x5)

inst_532:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x173 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x36c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x10e and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3173; op2val:0xc36c;
op3val:0x390e; valaddr_reg:x8; val_offset:1530*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1530*FLEN/8, x10, x3, x5)

inst_533:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x173 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x36c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x10e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3173; op2val:0xc36c;
op3val:0x390e; valaddr_reg:x8; val_offset:1533*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1533*FLEN/8, x10, x3, x5)

inst_534:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x173 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x36c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x10e and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3173; op2val:0xc36c;
op3val:0x390e; valaddr_reg:x8; val_offset:1536*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1536*FLEN/8, x10, x3, x5)

inst_535:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x304 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x38a and fs3 == 0 and fe3 == 0x0c and fm3 == 0x29c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3304; op2val:0xbb8a;
op3val:0x329c; valaddr_reg:x8; val_offset:1539*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1539*FLEN/8, x10, x3, x5)
RVTEST_SIGBASE(x3,signature_x3_4)

inst_536:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x304 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x38a and fs3 == 0 and fe3 == 0x0c and fm3 == 0x29c and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3304; op2val:0xbb8a;
op3val:0x329c; valaddr_reg:x8; val_offset:1542*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1542*FLEN/8, x10, x3, x5)

inst_537:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x304 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x38a and fs3 == 0 and fe3 == 0x0c and fm3 == 0x29c and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3304; op2val:0xbb8a;
op3val:0x329c; valaddr_reg:x8; val_offset:1545*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1545*FLEN/8, x10, x3, x5)

inst_538:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x304 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x38a and fs3 == 0 and fe3 == 0x0c and fm3 == 0x29c and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3304; op2val:0xbb8a;
op3val:0x329c; valaddr_reg:x8; val_offset:1548*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1548*FLEN/8, x10, x3, x5)

inst_539:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x304 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x38a and fs3 == 0 and fe3 == 0x0c and fm3 == 0x29c and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3304; op2val:0xbb8a;
op3val:0x329c; valaddr_reg:x8; val_offset:1551*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1551*FLEN/8, x10, x3, x5)

inst_540:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x083 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x186 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e5; op2val:0xb883;
op3val:0x3586; valaddr_reg:x8; val_offset:1554*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1554*FLEN/8, x10, x3, x5)

inst_541:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x083 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x186 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e5; op2val:0xb883;
op3val:0x3586; valaddr_reg:x8; val_offset:1557*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1557*FLEN/8, x10, x3, x5)

inst_542:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x083 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x186 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e5; op2val:0xb883;
op3val:0x3586; valaddr_reg:x8; val_offset:1560*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1560*FLEN/8, x10, x3, x5)

inst_543:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x083 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x186 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e5; op2val:0xb883;
op3val:0x3586; valaddr_reg:x8; val_offset:1563*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1563*FLEN/8, x10, x3, x5)

inst_544:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x083 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x186 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e5; op2val:0xb883;
op3val:0x3586; valaddr_reg:x8; val_offset:1566*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1566*FLEN/8, x10, x3, x5)

inst_545:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x308 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x013 and fs3 == 0 and fe3 == 0x07 and fm3 == 0x31f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3308; op2val:0xa813;
op3val:0x1f1f; valaddr_reg:x8; val_offset:1569*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1569*FLEN/8, x10, x3, x5)

inst_546:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x308 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x013 and fs3 == 0 and fe3 == 0x07 and fm3 == 0x31f and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3308; op2val:0xa813;
op3val:0x1f1f; valaddr_reg:x8; val_offset:1572*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1572*FLEN/8, x10, x3, x5)

inst_547:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x308 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x013 and fs3 == 0 and fe3 == 0x07 and fm3 == 0x31f and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3308; op2val:0xa813;
op3val:0x1f1f; valaddr_reg:x8; val_offset:1575*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1575*FLEN/8, x10, x3, x5)

inst_548:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x308 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x013 and fs3 == 0 and fe3 == 0x07 and fm3 == 0x31f and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3308; op2val:0xa813;
op3val:0x1f1f; valaddr_reg:x8; val_offset:1578*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1578*FLEN/8, x10, x3, x5)

inst_549:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x308 and fs2 == 1 and fe2 == 0x0a and fm2 == 0x013 and fs3 == 0 and fe3 == 0x07 and fm3 == 0x31f and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3308; op2val:0xa813;
op3val:0x1f1f; valaddr_reg:x8; val_offset:1581*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1581*FLEN/8, x10, x3, x5)

inst_550:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x117 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x15f and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2d7 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2d17; op2val:0xc15f;
op3val:0x32d7; valaddr_reg:x8; val_offset:1584*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1584*FLEN/8, x10, x3, x5)

inst_551:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x117 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x15f and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2d7 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2d17; op2val:0xc15f;
op3val:0x32d7; valaddr_reg:x8; val_offset:1587*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1587*FLEN/8, x10, x3, x5)

inst_552:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x117 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x15f and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2d7 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2d17; op2val:0xc15f;
op3val:0x32d7; valaddr_reg:x8; val_offset:1590*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1590*FLEN/8, x10, x3, x5)

inst_553:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x117 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x15f and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2d7 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2d17; op2val:0xc15f;
op3val:0x32d7; valaddr_reg:x8; val_offset:1593*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1593*FLEN/8, x10, x3, x5)

inst_554:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x117 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x15f and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2d7 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2d17; op2val:0xc15f;
op3val:0x32d7; valaddr_reg:x8; val_offset:1596*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1596*FLEN/8, x10, x3, x5)

inst_555:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e7 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x339 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x23c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ae7; op2val:0xb739;
op3val:0x363c; valaddr_reg:x8; val_offset:1599*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1599*FLEN/8, x10, x3, x5)

inst_556:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e7 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x339 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x23c and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ae7; op2val:0xb739;
op3val:0x363c; valaddr_reg:x8; val_offset:1602*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1602*FLEN/8, x10, x3, x5)

inst_557:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e7 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x339 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x23c and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ae7; op2val:0xb739;
op3val:0x363c; valaddr_reg:x8; val_offset:1605*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1605*FLEN/8, x10, x3, x5)

inst_558:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e7 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x339 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x23c and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ae7; op2val:0xb739;
op3val:0x363c; valaddr_reg:x8; val_offset:1608*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1608*FLEN/8, x10, x3, x5)

inst_559:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2e7 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x339 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x23c and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ae7; op2val:0xb739;
op3val:0x363c; valaddr_reg:x8; val_offset:1611*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1611*FLEN/8, x10, x3, x5)

inst_560:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x10a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1cc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x34d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x350a; op2val:0xc1cc;
op3val:0x3b4d; valaddr_reg:x8; val_offset:1614*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1614*FLEN/8, x10, x3, x5)

inst_561:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x10a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1cc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x34d and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x350a; op2val:0xc1cc;
op3val:0x3b4d; valaddr_reg:x8; val_offset:1617*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1617*FLEN/8, x10, x3, x5)

inst_562:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x10a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1cc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x34d and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x350a; op2val:0xc1cc;
op3val:0x3b4d; valaddr_reg:x8; val_offset:1620*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1620*FLEN/8, x10, x3, x5)

inst_563:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x10a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1cc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x34d and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x350a; op2val:0xc1cc;
op3val:0x3b4d; valaddr_reg:x8; val_offset:1623*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1623*FLEN/8, x10, x3, x5)

inst_564:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x10a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1cc and fs3 == 0 and fe3 == 0x0e and fm3 == 0x34d and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x350a; op2val:0xc1cc;
op3val:0x3b4d; valaddr_reg:x8; val_offset:1626*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1626*FLEN/8, x10, x3, x5)

inst_565:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x04c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3d2 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x033 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x384c; op2val:0xb3d2;
op3val:0x3033; valaddr_reg:x8; val_offset:1629*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1629*FLEN/8, x10, x3, x5)

inst_566:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x04c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3d2 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x033 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x384c; op2val:0xb3d2;
op3val:0x3033; valaddr_reg:x8; val_offset:1632*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1632*FLEN/8, x10, x3, x5)

inst_567:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x04c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3d2 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x033 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x384c; op2val:0xb3d2;
op3val:0x3033; valaddr_reg:x8; val_offset:1635*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1635*FLEN/8, x10, x3, x5)

inst_568:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x04c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3d2 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x033 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x384c; op2val:0xb3d2;
op3val:0x3033; valaddr_reg:x8; val_offset:1638*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1638*FLEN/8, x10, x3, x5)

inst_569:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x04c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x3d2 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x033 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x384c; op2val:0xb3d2;
op3val:0x3033; valaddr_reg:x8; val_offset:1641*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1641*FLEN/8, x10, x3, x5)

inst_570:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x20e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x252 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0c8 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e0e; op2val:0xba52;
op3val:0x2cc8; valaddr_reg:x8; val_offset:1644*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1644*FLEN/8, x10, x3, x5)

inst_571:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x20e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x252 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0c8 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e0e; op2val:0xba52;
op3val:0x2cc8; valaddr_reg:x8; val_offset:1647*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1647*FLEN/8, x10, x3, x5)

inst_572:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x20e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x252 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0c8 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e0e; op2val:0xba52;
op3val:0x2cc8; valaddr_reg:x8; val_offset:1650*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1650*FLEN/8, x10, x3, x5)

inst_573:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x20e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x252 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0c8 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e0e; op2val:0xba52;
op3val:0x2cc8; valaddr_reg:x8; val_offset:1653*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1653*FLEN/8, x10, x3, x5)

inst_574:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x20e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x252 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0c8 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e0e; op2val:0xba52;
op3val:0x2cc8; valaddr_reg:x8; val_offset:1656*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1656*FLEN/8, x10, x3, x5)

inst_575:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x342 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2ee and fs3 == 0 and fe3 == 0x0d and fm3 == 0x249 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b42; op2val:0xb6ee;
op3val:0x3649; valaddr_reg:x8; val_offset:1659*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1659*FLEN/8, x10, x3, x5)

inst_576:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x342 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2ee and fs3 == 0 and fe3 == 0x0d and fm3 == 0x249 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b42; op2val:0xb6ee;
op3val:0x3649; valaddr_reg:x8; val_offset:1662*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1662*FLEN/8, x10, x3, x5)

inst_577:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x342 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2ee and fs3 == 0 and fe3 == 0x0d and fm3 == 0x249 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b42; op2val:0xb6ee;
op3val:0x3649; valaddr_reg:x8; val_offset:1665*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1665*FLEN/8, x10, x3, x5)

inst_578:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x342 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2ee and fs3 == 0 and fe3 == 0x0d and fm3 == 0x249 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b42; op2val:0xb6ee;
op3val:0x3649; valaddr_reg:x8; val_offset:1668*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1668*FLEN/8, x10, x3, x5)

inst_579:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x342 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x2ee and fs3 == 0 and fe3 == 0x0d and fm3 == 0x249 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b42; op2val:0xb6ee;
op3val:0x3649; valaddr_reg:x8; val_offset:1671*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1671*FLEN/8, x10, x3, x5)

inst_580:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x052 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x125 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x18e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3052; op2val:0xc125;
op3val:0x358e; valaddr_reg:x8; val_offset:1674*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1674*FLEN/8, x10, x3, x5)

inst_581:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x052 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x125 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x18e and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3052; op2val:0xc125;
op3val:0x358e; valaddr_reg:x8; val_offset:1677*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1677*FLEN/8, x10, x3, x5)

inst_582:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x052 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x125 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x18e and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3052; op2val:0xc125;
op3val:0x358e; valaddr_reg:x8; val_offset:1680*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1680*FLEN/8, x10, x3, x5)

inst_583:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x052 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x125 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x18e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3052; op2val:0xc125;
op3val:0x358e; valaddr_reg:x8; val_offset:1683*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1683*FLEN/8, x10, x3, x5)

inst_584:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x052 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x125 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x18e and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3052; op2val:0xc125;
op3val:0x358e; valaddr_reg:x8; val_offset:1686*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1686*FLEN/8, x10, x3, x5)

inst_585:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x170 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1a7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3b0 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3970; op2val:0xbda7;
op3val:0x3bb0; valaddr_reg:x8; val_offset:1689*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1689*FLEN/8, x10, x3, x5)

inst_586:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x170 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1a7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3b0 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3970; op2val:0xbda7;
op3val:0x3bb0; valaddr_reg:x8; val_offset:1692*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1692*FLEN/8, x10, x3, x5)

inst_587:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x170 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1a7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3b0 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3970; op2val:0xbda7;
op3val:0x3bb0; valaddr_reg:x8; val_offset:1695*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1695*FLEN/8, x10, x3, x5)

inst_588:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x170 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1a7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3b0 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3970; op2val:0xbda7;
op3val:0x3bb0; valaddr_reg:x8; val_offset:1698*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1698*FLEN/8, x10, x3, x5)

inst_589:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x170 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1a7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3b0 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3970; op2val:0xbda7;
op3val:0x3bb0; valaddr_reg:x8; val_offset:1701*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1701*FLEN/8, x10, x3, x5)

inst_590:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x122 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x307 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x082 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2d22; op2val:0xbf07;
op3val:0x3082; valaddr_reg:x8; val_offset:1704*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1704*FLEN/8, x10, x3, x5)

inst_591:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x122 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x307 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x082 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2d22; op2val:0xbf07;
op3val:0x3082; valaddr_reg:x8; val_offset:1707*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1707*FLEN/8, x10, x3, x5)

inst_592:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x122 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x307 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x082 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2d22; op2val:0xbf07;
op3val:0x3082; valaddr_reg:x8; val_offset:1710*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1710*FLEN/8, x10, x3, x5)

inst_593:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x122 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x307 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x082 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2d22; op2val:0xbf07;
op3val:0x3082; valaddr_reg:x8; val_offset:1713*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1713*FLEN/8, x10, x3, x5)

inst_594:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x122 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x307 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x082 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2d22; op2val:0xbf07;
op3val:0x3082; valaddr_reg:x8; val_offset:1716*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1716*FLEN/8, x10, x3, x5)

inst_595:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x18a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x351 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x111 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x358a; op2val:0xbf51;
op3val:0x3911; valaddr_reg:x8; val_offset:1719*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1719*FLEN/8, x10, x3, x5)

inst_596:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x18a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x351 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x111 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x358a; op2val:0xbf51;
op3val:0x3911; valaddr_reg:x8; val_offset:1722*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1722*FLEN/8, x10, x3, x5)

inst_597:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x18a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x351 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x111 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x358a; op2val:0xbf51;
op3val:0x3911; valaddr_reg:x8; val_offset:1725*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1725*FLEN/8, x10, x3, x5)

inst_598:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x18a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x351 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x111 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x358a; op2val:0xbf51;
op3val:0x3911; valaddr_reg:x8; val_offset:1728*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1728*FLEN/8, x10, x3, x5)

inst_599:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x18a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x351 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x111 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x358a; op2val:0xbf51;
op3val:0x3911; valaddr_reg:x8; val_offset:1731*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1731*FLEN/8, x10, x3, x5)

inst_600:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x17d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x051 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1ed and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x317d; op2val:0xbc51;
op3val:0x31ed; valaddr_reg:x8; val_offset:1734*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1734*FLEN/8, x10, x3, x5)

inst_601:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x17d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x051 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1ed and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x317d; op2val:0xbc51;
op3val:0x31ed; valaddr_reg:x8; val_offset:1737*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1737*FLEN/8, x10, x3, x5)

inst_602:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x17d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x051 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1ed and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x317d; op2val:0xbc51;
op3val:0x31ed; valaddr_reg:x8; val_offset:1740*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1740*FLEN/8, x10, x3, x5)

inst_603:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x17d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x051 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1ed and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x317d; op2val:0xbc51;
op3val:0x31ed; valaddr_reg:x8; val_offset:1743*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1743*FLEN/8, x10, x3, x5)

inst_604:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x17d and fs2 == 1 and fe2 == 0x0f and fm2 == 0x051 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1ed and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x317d; op2val:0xbc51;
op3val:0x31ed; valaddr_reg:x8; val_offset:1746*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1746*FLEN/8, x10, x3, x5)

inst_605:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x067 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1d0 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x267 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3467; op2val:0xbdd0;
op3val:0x3667; valaddr_reg:x8; val_offset:1749*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1749*FLEN/8, x10, x3, x5)

inst_606:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x067 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1d0 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x267 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3467; op2val:0xbdd0;
op3val:0x3667; valaddr_reg:x8; val_offset:1752*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1752*FLEN/8, x10, x3, x5)

inst_607:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x067 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1d0 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x267 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3467; op2val:0xbdd0;
op3val:0x3667; valaddr_reg:x8; val_offset:1755*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1755*FLEN/8, x10, x3, x5)

inst_608:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x067 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1d0 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x267 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3467; op2val:0xbdd0;
op3val:0x3667; valaddr_reg:x8; val_offset:1758*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1758*FLEN/8, x10, x3, x5)

inst_609:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x067 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1d0 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x267 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3467; op2val:0xbdd0;
op3val:0x3667; valaddr_reg:x8; val_offset:1761*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1761*FLEN/8, x10, x3, x5)

inst_610:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x172 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x022 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a0 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3972; op2val:0xbc22;
op3val:0x39a0; valaddr_reg:x8; val_offset:1764*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1764*FLEN/8, x10, x3, x5)

inst_611:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x172 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x022 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a0 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3972; op2val:0xbc22;
op3val:0x39a0; valaddr_reg:x8; val_offset:1767*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1767*FLEN/8, x10, x3, x5)

inst_612:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x172 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x022 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a0 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3972; op2val:0xbc22;
op3val:0x39a0; valaddr_reg:x8; val_offset:1770*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1770*FLEN/8, x10, x3, x5)

inst_613:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x172 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x022 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a0 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3972; op2val:0xbc22;
op3val:0x39a0; valaddr_reg:x8; val_offset:1773*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1773*FLEN/8, x10, x3, x5)

inst_614:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x172 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x022 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a0 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3972; op2val:0xbc22;
op3val:0x39a0; valaddr_reg:x8; val_offset:1776*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1776*FLEN/8, x10, x3, x5)

inst_615:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x123 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x030 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x162 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3923; op2val:0xbc30;
op3val:0x3962; valaddr_reg:x8; val_offset:1779*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1779*FLEN/8, x10, x3, x5)

inst_616:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x123 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x030 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x162 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3923; op2val:0xbc30;
op3val:0x3962; valaddr_reg:x8; val_offset:1782*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1782*FLEN/8, x10, x3, x5)

inst_617:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x123 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x030 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x162 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3923; op2val:0xbc30;
op3val:0x3962; valaddr_reg:x8; val_offset:1785*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1785*FLEN/8, x10, x3, x5)

inst_618:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x123 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x030 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x162 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3923; op2val:0xbc30;
op3val:0x3962; valaddr_reg:x8; val_offset:1788*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1788*FLEN/8, x10, x3, x5)

inst_619:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x123 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x030 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x162 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3923; op2val:0xbc30;
op3val:0x3962; valaddr_reg:x8; val_offset:1791*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1791*FLEN/8, x10, x3, x5)

inst_620:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ad and fs2 == 1 and fe2 == 0x0f and fm2 == 0x362 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x316 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37ad; op2val:0xbf62;
op3val:0x3b16; valaddr_reg:x8; val_offset:1794*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1794*FLEN/8, x10, x3, x5)

inst_621:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ad and fs2 == 1 and fe2 == 0x0f and fm2 == 0x362 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x316 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37ad; op2val:0xbf62;
op3val:0x3b16; valaddr_reg:x8; val_offset:1797*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1797*FLEN/8, x10, x3, x5)

inst_622:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ad and fs2 == 1 and fe2 == 0x0f and fm2 == 0x362 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x316 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37ad; op2val:0xbf62;
op3val:0x3b16; valaddr_reg:x8; val_offset:1800*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1800*FLEN/8, x10, x3, x5)

inst_623:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ad and fs2 == 1 and fe2 == 0x0f and fm2 == 0x362 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x316 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37ad; op2val:0xbf62;
op3val:0x3b16; valaddr_reg:x8; val_offset:1803*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1803*FLEN/8, x10, x3, x5)

inst_624:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3ad and fs2 == 1 and fe2 == 0x0f and fm2 == 0x362 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x316 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37ad; op2val:0xbf62;
op3val:0x3b16; valaddr_reg:x8; val_offset:1806*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1806*FLEN/8, x10, x3, x5)

inst_625:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x075 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ae and fs3 == 0 and fe3 == 0x0e and fm3 == 0x137 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3475; op2val:0xc0ae;
op3val:0x3937; valaddr_reg:x8; val_offset:1809*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1809*FLEN/8, x10, x3, x5)

inst_626:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x075 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ae and fs3 == 0 and fe3 == 0x0e and fm3 == 0x137 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3475; op2val:0xc0ae;
op3val:0x3937; valaddr_reg:x8; val_offset:1812*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1812*FLEN/8, x10, x3, x5)

inst_627:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x075 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ae and fs3 == 0 and fe3 == 0x0e and fm3 == 0x137 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3475; op2val:0xc0ae;
op3val:0x3937; valaddr_reg:x8; val_offset:1815*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1815*FLEN/8, x10, x3, x5)

inst_628:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x075 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ae and fs3 == 0 and fe3 == 0x0e and fm3 == 0x137 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3475; op2val:0xc0ae;
op3val:0x3937; valaddr_reg:x8; val_offset:1818*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1818*FLEN/8, x10, x3, x5)

inst_629:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x075 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ae and fs3 == 0 and fe3 == 0x0e and fm3 == 0x137 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3475; op2val:0xc0ae;
op3val:0x3937; valaddr_reg:x8; val_offset:1821*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1821*FLEN/8, x10, x3, x5)

inst_630:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x318 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1f5 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ab8; op2val:0xbb18;
op3val:0x39f5; valaddr_reg:x8; val_offset:1824*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1824*FLEN/8, x10, x3, x5)

inst_631:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x318 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1f5 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ab8; op2val:0xbb18;
op3val:0x39f5; valaddr_reg:x8; val_offset:1827*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1827*FLEN/8, x10, x3, x5)

inst_632:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x318 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1f5 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ab8; op2val:0xbb18;
op3val:0x39f5; valaddr_reg:x8; val_offset:1830*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1830*FLEN/8, x10, x3, x5)

inst_633:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x318 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1f5 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ab8; op2val:0xbb18;
op3val:0x39f5; valaddr_reg:x8; val_offset:1833*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1833*FLEN/8, x10, x3, x5)

inst_634:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x318 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1f5 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ab8; op2val:0xbb18;
op3val:0x39f5; valaddr_reg:x8; val_offset:1836*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1836*FLEN/8, x10, x3, x5)

inst_635:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x373 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e2; op2val:0xbb73;
op3val:0x388c; valaddr_reg:x8; val_offset:1839*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1839*FLEN/8, x10, x3, x5)

inst_636:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x373 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08c and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e2; op2val:0xbb73;
op3val:0x388c; valaddr_reg:x8; val_offset:1842*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1842*FLEN/8, x10, x3, x5)

inst_637:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x373 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08c and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e2; op2val:0xbb73;
op3val:0x388c; valaddr_reg:x8; val_offset:1845*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1845*FLEN/8, x10, x3, x5)

inst_638:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x373 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08c and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e2; op2val:0xbb73;
op3val:0x388c; valaddr_reg:x8; val_offset:1848*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1848*FLEN/8, x10, x3, x5)

inst_639:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0e2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x373 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x08c and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38e2; op2val:0xbb73;
op3val:0x388c; valaddr_reg:x8; val_offset:1851*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1851*FLEN/8, x10, x3, x5)

inst_640:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2f8 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x021 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x333 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32f8; op2val:0xc421;
op3val:0x3b33; valaddr_reg:x8; val_offset:1854*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1854*FLEN/8, x10, x3, x5)

inst_641:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2f8 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x021 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x333 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32f8; op2val:0xc421;
op3val:0x3b33; valaddr_reg:x8; val_offset:1857*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1857*FLEN/8, x10, x3, x5)

inst_642:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2f8 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x021 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x333 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32f8; op2val:0xc421;
op3val:0x3b33; valaddr_reg:x8; val_offset:1860*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1860*FLEN/8, x10, x3, x5)

inst_643:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2f8 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x021 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x333 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32f8; op2val:0xc421;
op3val:0x3b33; valaddr_reg:x8; val_offset:1863*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1863*FLEN/8, x10, x3, x5)

inst_644:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2f8 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x021 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x333 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32f8; op2val:0xc421;
op3val:0x3b33; valaddr_reg:x8; val_offset:1866*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1866*FLEN/8, x10, x3, x5)

inst_645:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x238 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x346 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a7 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a38; op2val:0xbb46;
op3val:0x39a7; valaddr_reg:x8; val_offset:1869*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1869*FLEN/8, x10, x3, x5)

inst_646:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x238 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x346 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a7 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a38; op2val:0xbb46;
op3val:0x39a7; valaddr_reg:x8; val_offset:1872*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1872*FLEN/8, x10, x3, x5)

inst_647:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x238 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x346 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a7 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a38; op2val:0xbb46;
op3val:0x39a7; valaddr_reg:x8; val_offset:1875*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1875*FLEN/8, x10, x3, x5)

inst_648:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x238 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x346 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a7 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a38; op2val:0xbb46;
op3val:0x39a7; valaddr_reg:x8; val_offset:1878*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1878*FLEN/8, x10, x3, x5)

inst_649:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x238 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x346 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1a7 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a38; op2val:0xbb46;
op3val:0x39a7; valaddr_reg:x8; val_offset:1881*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1881*FLEN/8, x10, x3, x5)

inst_650:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x296 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0df and fs3 == 0 and fe3 == 0x0d and fm3 == 0x002 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a96; op2val:0xb4df;
op3val:0x3402; valaddr_reg:x8; val_offset:1884*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1884*FLEN/8, x10, x3, x5)

inst_651:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x296 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0df and fs3 == 0 and fe3 == 0x0d and fm3 == 0x002 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a96; op2val:0xb4df;
op3val:0x3402; valaddr_reg:x8; val_offset:1887*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1887*FLEN/8, x10, x3, x5)

inst_652:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x296 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0df and fs3 == 0 and fe3 == 0x0d and fm3 == 0x002 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a96; op2val:0xb4df;
op3val:0x3402; valaddr_reg:x8; val_offset:1890*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1890*FLEN/8, x10, x3, x5)

inst_653:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x296 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0df and fs3 == 0 and fe3 == 0x0d and fm3 == 0x002 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a96; op2val:0xb4df;
op3val:0x3402; valaddr_reg:x8; val_offset:1893*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1893*FLEN/8, x10, x3, x5)

inst_654:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x296 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0df and fs3 == 0 and fe3 == 0x0d and fm3 == 0x002 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a96; op2val:0xb4df;
op3val:0x3402; valaddr_reg:x8; val_offset:1896*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1896*FLEN/8, x10, x3, x5)

inst_655:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x320 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x042 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x397 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b20; op2val:0xbc42;
op3val:0x3b97; valaddr_reg:x8; val_offset:1899*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1899*FLEN/8, x10, x3, x5)

inst_656:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x320 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x042 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x397 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b20; op2val:0xbc42;
op3val:0x3b97; valaddr_reg:x8; val_offset:1902*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1902*FLEN/8, x10, x3, x5)

inst_657:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x320 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x042 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x397 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b20; op2val:0xbc42;
op3val:0x3b97; valaddr_reg:x8; val_offset:1905*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1905*FLEN/8, x10, x3, x5)

inst_658:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x320 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x042 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x397 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b20; op2val:0xbc42;
op3val:0x3b97; valaddr_reg:x8; val_offset:1908*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1908*FLEN/8, x10, x3, x5)

inst_659:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x320 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x042 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x397 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b20; op2val:0xbc42;
op3val:0x3b97; valaddr_reg:x8; val_offset:1911*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1911*FLEN/8, x10, x3, x5)

inst_660:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x31b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c0 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x038 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x371b; op2val:0xb8c0;
op3val:0x3438; valaddr_reg:x8; val_offset:1914*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1914*FLEN/8, x10, x3, x5)

inst_661:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x31b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c0 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x038 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x371b; op2val:0xb8c0;
op3val:0x3438; valaddr_reg:x8; val_offset:1917*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1917*FLEN/8, x10, x3, x5)

inst_662:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x31b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c0 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x038 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x371b; op2val:0xb8c0;
op3val:0x3438; valaddr_reg:x8; val_offset:1920*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1920*FLEN/8, x10, x3, x5)

inst_663:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x31b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c0 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x038 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x371b; op2val:0xb8c0;
op3val:0x3438; valaddr_reg:x8; val_offset:1923*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1923*FLEN/8, x10, x3, x5)
RVTEST_SIGBASE(x3,signature_x3_5)

inst_664:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x31b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0c0 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x038 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x371b; op2val:0xb8c0;
op3val:0x3438; valaddr_reg:x8; val_offset:1926*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1926*FLEN/8, x10, x3, x5)

inst_665:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x199 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x109 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x30c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3199; op2val:0xc109;
op3val:0x370c; valaddr_reg:x8; val_offset:1929*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1929*FLEN/8, x10, x3, x5)

inst_666:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x199 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x109 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x30c and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3199; op2val:0xc109;
op3val:0x370c; valaddr_reg:x8; val_offset:1932*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1932*FLEN/8, x10, x3, x5)

inst_667:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x199 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x109 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x30c and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3199; op2val:0xc109;
op3val:0x370c; valaddr_reg:x8; val_offset:1935*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1935*FLEN/8, x10, x3, x5)

inst_668:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x199 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x109 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x30c and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3199; op2val:0xc109;
op3val:0x370c; valaddr_reg:x8; val_offset:1938*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1938*FLEN/8, x10, x3, x5)

inst_669:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x199 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x109 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x30c and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3199; op2val:0xc109;
op3val:0x370c; valaddr_reg:x8; val_offset:1941*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1941*FLEN/8, x10, x3, x5)

inst_670:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x162 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x19e and fs3 == 0 and fe3 == 0x0b and fm3 == 0x38f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3962; op2val:0xb19e;
op3val:0x2f8f; valaddr_reg:x8; val_offset:1944*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1944*FLEN/8, x10, x3, x5)

inst_671:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x162 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x19e and fs3 == 0 and fe3 == 0x0b and fm3 == 0x38f and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3962; op2val:0xb19e;
op3val:0x2f8f; valaddr_reg:x8; val_offset:1947*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1947*FLEN/8, x10, x3, x5)

inst_672:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x162 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x19e and fs3 == 0 and fe3 == 0x0b and fm3 == 0x38f and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3962; op2val:0xb19e;
op3val:0x2f8f; valaddr_reg:x8; val_offset:1950*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1950*FLEN/8, x10, x3, x5)

inst_673:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x162 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x19e and fs3 == 0 and fe3 == 0x0b and fm3 == 0x38f and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3962; op2val:0xb19e;
op3val:0x2f8f; valaddr_reg:x8; val_offset:1953*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1953*FLEN/8, x10, x3, x5)

inst_674:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x162 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x19e and fs3 == 0 and fe3 == 0x0b and fm3 == 0x38f and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3962; op2val:0xb19e;
op3val:0x2f8f; valaddr_reg:x8; val_offset:1956*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1956*FLEN/8, x10, x3, x5)

inst_675:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x038 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3e6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x02b and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3438; op2val:0xbfe6;
op3val:0x382b; valaddr_reg:x8; val_offset:1959*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1959*FLEN/8, x10, x3, x5)

inst_676:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x038 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3e6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x02b and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3438; op2val:0xbfe6;
op3val:0x382b; valaddr_reg:x8; val_offset:1962*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1962*FLEN/8, x10, x3, x5)

inst_677:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x038 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3e6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x02b and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3438; op2val:0xbfe6;
op3val:0x382b; valaddr_reg:x8; val_offset:1965*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1965*FLEN/8, x10, x3, x5)

inst_678:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x038 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3e6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x02b and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3438; op2val:0xbfe6;
op3val:0x382b; valaddr_reg:x8; val_offset:1968*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1968*FLEN/8, x10, x3, x5)

inst_679:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x038 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3e6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x02b and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3438; op2val:0xbfe6;
op3val:0x382b; valaddr_reg:x8; val_offset:1971*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1971*FLEN/8, x10, x3, x5)

inst_680:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2fe and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0b0 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x018 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36fe; op2val:0xb0b0;
op3val:0x2c18; valaddr_reg:x8; val_offset:1974*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1974*FLEN/8, x10, x3, x5)

inst_681:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2fe and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0b0 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x018 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36fe; op2val:0xb0b0;
op3val:0x2c18; valaddr_reg:x8; val_offset:1977*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1977*FLEN/8, x10, x3, x5)

inst_682:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2fe and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0b0 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x018 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36fe; op2val:0xb0b0;
op3val:0x2c18; valaddr_reg:x8; val_offset:1980*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1980*FLEN/8, x10, x3, x5)

inst_683:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2fe and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0b0 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x018 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36fe; op2val:0xb0b0;
op3val:0x2c18; valaddr_reg:x8; val_offset:1983*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1983*FLEN/8, x10, x3, x5)

inst_684:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2fe and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0b0 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x018 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36fe; op2val:0xb0b0;
op3val:0x2c18; valaddr_reg:x8; val_offset:1986*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 1986*FLEN/8, x10, x3, x5)

inst_685:
// fs1 == 0 and fe1 == 0x06 and fm1 == 0x189 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x25e and fs3 == 0 and fe3 == 0x0b and fm3 == 0x067 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1989; op2val:0xce5e;
op3val:0x2c67; valaddr_reg:x8; val_offset:1989*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 1989*FLEN/8, x10, x3, x5)

inst_686:
// fs1 == 0 and fe1 == 0x06 and fm1 == 0x189 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x25e and fs3 == 0 and fe3 == 0x0b and fm3 == 0x067 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1989; op2val:0xce5e;
op3val:0x2c67; valaddr_reg:x8; val_offset:1992*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 1992*FLEN/8, x10, x3, x5)

inst_687:
// fs1 == 0 and fe1 == 0x06 and fm1 == 0x189 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x25e and fs3 == 0 and fe3 == 0x0b and fm3 == 0x067 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1989; op2val:0xce5e;
op3val:0x2c67; valaddr_reg:x8; val_offset:1995*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 1995*FLEN/8, x10, x3, x5)

inst_688:
// fs1 == 0 and fe1 == 0x06 and fm1 == 0x189 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x25e and fs3 == 0 and fe3 == 0x0b and fm3 == 0x067 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1989; op2val:0xce5e;
op3val:0x2c67; valaddr_reg:x8; val_offset:1998*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 1998*FLEN/8, x10, x3, x5)

inst_689:
// fs1 == 0 and fe1 == 0x06 and fm1 == 0x189 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x25e and fs3 == 0 and fe3 == 0x0b and fm3 == 0x067 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1989; op2val:0xce5e;
op3val:0x2c67; valaddr_reg:x8; val_offset:2001*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2001*FLEN/8, x10, x3, x5)

inst_690:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2f0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x235 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x162 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3af0; op2val:0xba35;
op3val:0x3962; valaddr_reg:x8; val_offset:2004*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2004*FLEN/8, x10, x3, x5)

inst_691:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2f0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x235 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x162 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3af0; op2val:0xba35;
op3val:0x3962; valaddr_reg:x8; val_offset:2007*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2007*FLEN/8, x10, x3, x5)

inst_692:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2f0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x235 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x162 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3af0; op2val:0xba35;
op3val:0x3962; valaddr_reg:x8; val_offset:2010*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2010*FLEN/8, x10, x3, x5)

inst_693:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2f0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x235 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x162 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3af0; op2val:0xba35;
op3val:0x3962; valaddr_reg:x8; val_offset:2013*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2013*FLEN/8, x10, x3, x5)

inst_694:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2f0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x235 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x162 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3af0; op2val:0xba35;
op3val:0x3962; valaddr_reg:x8; val_offset:2016*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2016*FLEN/8, x10, x3, x5)

inst_695:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0bc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x19d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2a5 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38bc; op2val:0xbd9d;
op3val:0x3aa5; valaddr_reg:x8; val_offset:2019*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2019*FLEN/8, x10, x3, x5)

inst_696:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0bc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x19d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2a5 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38bc; op2val:0xbd9d;
op3val:0x3aa5; valaddr_reg:x8; val_offset:2022*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2022*FLEN/8, x10, x3, x5)

inst_697:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0bc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x19d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2a5 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38bc; op2val:0xbd9d;
op3val:0x3aa5; valaddr_reg:x8; val_offset:2025*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2025*FLEN/8, x10, x3, x5)

inst_698:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0bc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x19d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2a5 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38bc; op2val:0xbd9d;
op3val:0x3aa5; valaddr_reg:x8; val_offset:2028*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2028*FLEN/8, x10, x3, x5)

inst_699:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0bc and fs2 == 1 and fe2 == 0x0f and fm2 == 0x19d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2a5 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38bc; op2val:0xbd9d;
op3val:0x3aa5; valaddr_reg:x8; val_offset:2031*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2031*FLEN/8, x10, x3, x5)

inst_700:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x39d and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3e4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x383 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x339d; op2val:0xc3e4;
op3val:0x3b83; valaddr_reg:x8; val_offset:2034*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2034*FLEN/8, x10, x3, x5)

inst_701:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x39d and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3e4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x383 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x339d; op2val:0xc3e4;
op3val:0x3b83; valaddr_reg:x8; val_offset:2037*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2037*FLEN/8, x10, x3, x5)

inst_702:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x39d and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3e4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x383 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x339d; op2val:0xc3e4;
op3val:0x3b83; valaddr_reg:x8; val_offset:2040*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2040*FLEN/8, x10, x3, x5)

inst_703:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x39d and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3e4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x383 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x339d; op2val:0xc3e4;
op3val:0x3b83; valaddr_reg:x8; val_offset:2043*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2043*FLEN/8, x10, x3, x5)

inst_704:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x39d and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3e4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x383 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x339d; op2val:0xc3e4;
op3val:0x3b83; valaddr_reg:x8; val_offset:2046*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2046*FLEN/8, x10, x3, x5)

inst_705:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x334 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x35c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2a1 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f34; op2val:0xc35c;
op3val:0x36a1; valaddr_reg:x8; val_offset:2049*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2049*FLEN/8, x10, x3, x5)

inst_706:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x334 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x35c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2a1 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f34; op2val:0xc35c;
op3val:0x36a1; valaddr_reg:x8; val_offset:2052*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2052*FLEN/8, x10, x3, x5)

inst_707:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x334 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x35c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2a1 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f34; op2val:0xc35c;
op3val:0x36a1; valaddr_reg:x8; val_offset:2055*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2055*FLEN/8, x10, x3, x5)

inst_708:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x334 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x35c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2a1 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f34; op2val:0xc35c;
op3val:0x36a1; valaddr_reg:x8; val_offset:2058*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2058*FLEN/8, x10, x3, x5)

inst_709:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x334 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x35c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2a1 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f34; op2val:0xc35c;
op3val:0x36a1; valaddr_reg:x8; val_offset:2061*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2061*FLEN/8, x10, x3, x5)

inst_710:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x22e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x20f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0ae and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x362e; op2val:0xbe0f;
op3val:0x38ae; valaddr_reg:x8; val_offset:2064*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2064*FLEN/8, x10, x3, x5)

inst_711:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x22e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x20f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0ae and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x362e; op2val:0xbe0f;
op3val:0x38ae; valaddr_reg:x8; val_offset:2067*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2067*FLEN/8, x10, x3, x5)

inst_712:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x22e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x20f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0ae and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x362e; op2val:0xbe0f;
op3val:0x38ae; valaddr_reg:x8; val_offset:2070*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2070*FLEN/8, x10, x3, x5)

inst_713:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x22e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x20f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0ae and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x362e; op2val:0xbe0f;
op3val:0x38ae; valaddr_reg:x8; val_offset:2073*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2073*FLEN/8, x10, x3, x5)

inst_714:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x22e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x20f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0ae and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x362e; op2val:0xbe0f;
op3val:0x38ae; valaddr_reg:x8; val_offset:2076*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2076*FLEN/8, x10, x3, x5)

inst_715:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x011 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2a3 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2bf and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c11; op2val:0xc6a3;
op3val:0x36bf; valaddr_reg:x8; val_offset:2079*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2079*FLEN/8, x10, x3, x5)

inst_716:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x011 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2a3 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2bf and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c11; op2val:0xc6a3;
op3val:0x36bf; valaddr_reg:x8; val_offset:2082*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2082*FLEN/8, x10, x3, x5)

inst_717:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x011 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2a3 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2bf and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c11; op2val:0xc6a3;
op3val:0x36bf; valaddr_reg:x8; val_offset:2085*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2085*FLEN/8, x10, x3, x5)

inst_718:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x011 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2a3 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2bf and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c11; op2val:0xc6a3;
op3val:0x36bf; valaddr_reg:x8; val_offset:2088*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2088*FLEN/8, x10, x3, x5)

inst_719:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x011 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2a3 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2bf and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c11; op2val:0xc6a3;
op3val:0x36bf; valaddr_reg:x8; val_offset:2091*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2091*FLEN/8, x10, x3, x5)

inst_720:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x29f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1fc and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0f3 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e9f; op2val:0xb9fc;
op3val:0x2cf3; valaddr_reg:x8; val_offset:2094*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2094*FLEN/8, x10, x3, x5)

inst_721:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x29f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1fc and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0f3 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e9f; op2val:0xb9fc;
op3val:0x2cf3; valaddr_reg:x8; val_offset:2097*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2097*FLEN/8, x10, x3, x5)

inst_722:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x29f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1fc and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0f3 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e9f; op2val:0xb9fc;
op3val:0x2cf3; valaddr_reg:x8; val_offset:2100*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2100*FLEN/8, x10, x3, x5)

inst_723:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x29f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1fc and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0f3 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e9f; op2val:0xb9fc;
op3val:0x2cf3; valaddr_reg:x8; val_offset:2103*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2103*FLEN/8, x10, x3, x5)

inst_724:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x29f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1fc and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0f3 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e9f; op2val:0xb9fc;
op3val:0x2cf3; valaddr_reg:x8; val_offset:2106*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2106*FLEN/8, x10, x3, x5)

inst_725:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ed and fs2 == 1 and fe2 == 0x0a and fm2 == 0x2f7 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x046 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ed; op2val:0xaaf7;
op3val:0x2446; valaddr_reg:x8; val_offset:2109*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2109*FLEN/8, x10, x3, x5)

inst_726:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ed and fs2 == 1 and fe2 == 0x0a and fm2 == 0x2f7 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x046 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ed; op2val:0xaaf7;
op3val:0x2446; valaddr_reg:x8; val_offset:2112*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2112*FLEN/8, x10, x3, x5)

inst_727:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ed and fs2 == 1 and fe2 == 0x0a and fm2 == 0x2f7 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x046 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ed; op2val:0xaaf7;
op3val:0x2446; valaddr_reg:x8; val_offset:2115*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2115*FLEN/8, x10, x3, x5)

inst_728:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ed and fs2 == 1 and fe2 == 0x0a and fm2 == 0x2f7 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x046 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ed; op2val:0xaaf7;
op3val:0x2446; valaddr_reg:x8; val_offset:2118*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2118*FLEN/8, x10, x3, x5)

inst_729:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ed and fs2 == 1 and fe2 == 0x0a and fm2 == 0x2f7 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x046 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ed; op2val:0xaaf7;
op3val:0x2446; valaddr_reg:x8; val_offset:2121*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2121*FLEN/8, x10, x3, x5)

inst_730:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x015 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x111 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3815; op2val:0xbcf7;
op3val:0x3911; valaddr_reg:x8; val_offset:2124*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2124*FLEN/8, x10, x3, x5)

inst_731:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x015 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x111 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3815; op2val:0xbcf7;
op3val:0x3911; valaddr_reg:x8; val_offset:2127*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2127*FLEN/8, x10, x3, x5)

inst_732:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x015 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x111 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3815; op2val:0xbcf7;
op3val:0x3911; valaddr_reg:x8; val_offset:2130*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2130*FLEN/8, x10, x3, x5)

inst_733:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x015 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x111 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3815; op2val:0xbcf7;
op3val:0x3911; valaddr_reg:x8; val_offset:2133*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2133*FLEN/8, x10, x3, x5)

inst_734:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x015 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x111 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3815; op2val:0xbcf7;
op3val:0x3911; valaddr_reg:x8; val_offset:2136*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2136*FLEN/8, x10, x3, x5)

inst_735:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0fe and fs2 == 1 and fe2 == 0x10 and fm2 == 0x20c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x38d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30fe; op2val:0xc20c;
op3val:0x378d; valaddr_reg:x8; val_offset:2139*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2139*FLEN/8, x10, x3, x5)

inst_736:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0fe and fs2 == 1 and fe2 == 0x10 and fm2 == 0x20c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x38d and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30fe; op2val:0xc20c;
op3val:0x378d; valaddr_reg:x8; val_offset:2142*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2142*FLEN/8, x10, x3, x5)

inst_737:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0fe and fs2 == 1 and fe2 == 0x10 and fm2 == 0x20c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x38d and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30fe; op2val:0xc20c;
op3val:0x378d; valaddr_reg:x8; val_offset:2145*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2145*FLEN/8, x10, x3, x5)

inst_738:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0fe and fs2 == 1 and fe2 == 0x10 and fm2 == 0x20c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x38d and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30fe; op2val:0xc20c;
op3val:0x378d; valaddr_reg:x8; val_offset:2148*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2148*FLEN/8, x10, x3, x5)

inst_739:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x0fe and fs2 == 1 and fe2 == 0x10 and fm2 == 0x20c and fs3 == 0 and fe3 == 0x0d and fm3 == 0x38d and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x30fe; op2val:0xc20c;
op3val:0x378d; valaddr_reg:x8; val_offset:2151*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2151*FLEN/8, x10, x3, x5)

inst_740:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x187 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x368 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x11e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3987; op2val:0xb768;
op3val:0x351e; valaddr_reg:x8; val_offset:2154*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2154*FLEN/8, x10, x3, x5)

inst_741:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x187 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x368 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x11e and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3987; op2val:0xb768;
op3val:0x351e; valaddr_reg:x8; val_offset:2157*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2157*FLEN/8, x10, x3, x5)

inst_742:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x187 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x368 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x11e and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3987; op2val:0xb768;
op3val:0x351e; valaddr_reg:x8; val_offset:2160*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2160*FLEN/8, x10, x3, x5)

inst_743:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x187 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x368 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x11e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3987; op2val:0xb768;
op3val:0x351e; valaddr_reg:x8; val_offset:2163*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2163*FLEN/8, x10, x3, x5)

inst_744:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x187 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x368 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x11e and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3987; op2val:0xb768;
op3val:0x351e; valaddr_reg:x8; val_offset:2166*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2166*FLEN/8, x10, x3, x5)

inst_745:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x031 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2a7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2fa and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3831; op2val:0xbea7;
op3val:0x3afa; valaddr_reg:x8; val_offset:2169*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2169*FLEN/8, x10, x3, x5)

inst_746:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x031 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2a7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2fa and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3831; op2val:0xbea7;
op3val:0x3afa; valaddr_reg:x8; val_offset:2172*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2172*FLEN/8, x10, x3, x5)

inst_747:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x031 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2a7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2fa and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3831; op2val:0xbea7;
op3val:0x3afa; valaddr_reg:x8; val_offset:2175*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2175*FLEN/8, x10, x3, x5)

inst_748:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x031 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2a7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2fa and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3831; op2val:0xbea7;
op3val:0x3afa; valaddr_reg:x8; val_offset:2178*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2178*FLEN/8, x10, x3, x5)

inst_749:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x031 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2a7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2fa and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3831; op2val:0xbea7;
op3val:0x3afa; valaddr_reg:x8; val_offset:2181*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2181*FLEN/8, x10, x3, x5)

inst_750:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x130 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x22a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x000 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3130; op2val:0xc22a;
op3val:0x3800; valaddr_reg:x8; val_offset:2184*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2184*FLEN/8, x10, x3, x5)

inst_751:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x130 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x22a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x000 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3130; op2val:0xc22a;
op3val:0x3800; valaddr_reg:x8; val_offset:2187*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2187*FLEN/8, x10, x3, x5)

inst_752:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x130 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x22a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x000 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3130; op2val:0xc22a;
op3val:0x3800; valaddr_reg:x8; val_offset:2190*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2190*FLEN/8, x10, x3, x5)

inst_753:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x130 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x22a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x000 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3130; op2val:0xc22a;
op3val:0x3800; valaddr_reg:x8; val_offset:2193*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2193*FLEN/8, x10, x3, x5)

inst_754:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x130 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x22a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x000 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3130; op2val:0xc22a;
op3val:0x3800; valaddr_reg:x8; val_offset:2196*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2196*FLEN/8, x10, x3, x5)

inst_755:
// fs1 == 0 and fe1 == 0x09 and fm1 == 0x34b and fs2 == 1 and fe2 == 0x13 and fm2 == 0x017 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x376 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x274b; op2val:0xcc17;
op3val:0x3776; valaddr_reg:x8; val_offset:2199*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2199*FLEN/8, x10, x3, x5)

inst_756:
// fs1 == 0 and fe1 == 0x09 and fm1 == 0x34b and fs2 == 1 and fe2 == 0x13 and fm2 == 0x017 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x376 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x274b; op2val:0xcc17;
op3val:0x3776; valaddr_reg:x8; val_offset:2202*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2202*FLEN/8, x10, x3, x5)

inst_757:
// fs1 == 0 and fe1 == 0x09 and fm1 == 0x34b and fs2 == 1 and fe2 == 0x13 and fm2 == 0x017 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x376 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x274b; op2val:0xcc17;
op3val:0x3776; valaddr_reg:x8; val_offset:2205*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2205*FLEN/8, x10, x3, x5)

inst_758:
// fs1 == 0 and fe1 == 0x09 and fm1 == 0x34b and fs2 == 1 and fe2 == 0x13 and fm2 == 0x017 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x376 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x274b; op2val:0xcc17;
op3val:0x3776; valaddr_reg:x8; val_offset:2208*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2208*FLEN/8, x10, x3, x5)

inst_759:
// fs1 == 0 and fe1 == 0x09 and fm1 == 0x34b and fs2 == 1 and fe2 == 0x13 and fm2 == 0x017 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x376 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x274b; op2val:0xcc17;
op3val:0x3776; valaddr_reg:x8; val_offset:2211*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2211*FLEN/8, x10, x3, x5)

inst_760:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x00b and fs2 == 1 and fe2 == 0x12 and fm2 == 0x19f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1af and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c0b; op2val:0xc99f;
op3val:0x39af; valaddr_reg:x8; val_offset:2214*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2214*FLEN/8, x10, x3, x5)

inst_761:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x00b and fs2 == 1 and fe2 == 0x12 and fm2 == 0x19f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1af and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c0b; op2val:0xc99f;
op3val:0x39af; valaddr_reg:x8; val_offset:2217*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2217*FLEN/8, x10, x3, x5)

inst_762:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x00b and fs2 == 1 and fe2 == 0x12 and fm2 == 0x19f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1af and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c0b; op2val:0xc99f;
op3val:0x39af; valaddr_reg:x8; val_offset:2220*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2220*FLEN/8, x10, x3, x5)

inst_763:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x00b and fs2 == 1 and fe2 == 0x12 and fm2 == 0x19f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1af and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c0b; op2val:0xc99f;
op3val:0x39af; valaddr_reg:x8; val_offset:2223*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2223*FLEN/8, x10, x3, x5)

inst_764:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x00b and fs2 == 1 and fe2 == 0x12 and fm2 == 0x19f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1af and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2c0b; op2val:0xc99f;
op3val:0x39af; valaddr_reg:x8; val_offset:2226*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2226*FLEN/8, x10, x3, x5)

inst_765:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x242 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0d7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x393 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a42; op2val:0xb8d7;
op3val:0x3793; valaddr_reg:x8; val_offset:2229*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2229*FLEN/8, x10, x3, x5)

inst_766:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x242 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0d7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x393 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a42; op2val:0xb8d7;
op3val:0x3793; valaddr_reg:x8; val_offset:2232*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2232*FLEN/8, x10, x3, x5)

inst_767:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x242 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0d7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x393 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a42; op2val:0xb8d7;
op3val:0x3793; valaddr_reg:x8; val_offset:2235*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2235*FLEN/8, x10, x3, x5)

inst_768:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x242 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0d7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x393 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a42; op2val:0xb8d7;
op3val:0x3793; valaddr_reg:x8; val_offset:2238*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2238*FLEN/8, x10, x3, x5)

inst_769:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x242 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0d7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x393 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a42; op2val:0xb8d7;
op3val:0x3793; valaddr_reg:x8; val_offset:2241*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2241*FLEN/8, x10, x3, x5)

inst_770:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x377 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x202 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x19b and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3377; op2val:0xba02;
op3val:0x319b; valaddr_reg:x8; val_offset:2244*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2244*FLEN/8, x10, x3, x5)

inst_771:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x377 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x202 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x19b and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3377; op2val:0xba02;
op3val:0x319b; valaddr_reg:x8; val_offset:2247*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2247*FLEN/8, x10, x3, x5)

inst_772:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x377 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x202 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x19b and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3377; op2val:0xba02;
op3val:0x319b; valaddr_reg:x8; val_offset:2250*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2250*FLEN/8, x10, x3, x5)

inst_773:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x377 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x202 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x19b and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3377; op2val:0xba02;
op3val:0x319b; valaddr_reg:x8; val_offset:2253*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2253*FLEN/8, x10, x3, x5)

inst_774:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x377 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x202 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x19b and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3377; op2val:0xba02;
op3val:0x319b; valaddr_reg:x8; val_offset:2256*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2256*FLEN/8, x10, x3, x5)

inst_775:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a4 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0f7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x301 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35a4; op2val:0xc0f7;
op3val:0x3b01; valaddr_reg:x8; val_offset:2259*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2259*FLEN/8, x10, x3, x5)

inst_776:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a4 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0f7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x301 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35a4; op2val:0xc0f7;
op3val:0x3b01; valaddr_reg:x8; val_offset:2262*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2262*FLEN/8, x10, x3, x5)

inst_777:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a4 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0f7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x301 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35a4; op2val:0xc0f7;
op3val:0x3b01; valaddr_reg:x8; val_offset:2265*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2265*FLEN/8, x10, x3, x5)

inst_778:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a4 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0f7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x301 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35a4; op2val:0xc0f7;
op3val:0x3b01; valaddr_reg:x8; val_offset:2268*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2268*FLEN/8, x10, x3, x5)

inst_779:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a4 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0f7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x301 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35a4; op2val:0xc0f7;
op3val:0x3b01; valaddr_reg:x8; val_offset:2271*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2271*FLEN/8, x10, x3, x5)

inst_780:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x25e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3b8 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d8; op2val:0xbe5e;
op3val:0x3bb8; valaddr_reg:x8; val_offset:2274*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2274*FLEN/8, x10, x3, x5)

inst_781:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x25e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3b8 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d8; op2val:0xbe5e;
op3val:0x3bb8; valaddr_reg:x8; val_offset:2277*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2277*FLEN/8, x10, x3, x5)

inst_782:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x25e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3b8 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d8; op2val:0xbe5e;
op3val:0x3bb8; valaddr_reg:x8; val_offset:2280*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2280*FLEN/8, x10, x3, x5)

inst_783:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x25e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3b8 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d8; op2val:0xbe5e;
op3val:0x3bb8; valaddr_reg:x8; val_offset:2283*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2283*FLEN/8, x10, x3, x5)

inst_784:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d8 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x25e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3b8 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d8; op2val:0xbe5e;
op3val:0x3bb8; valaddr_reg:x8; val_offset:2286*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2286*FLEN/8, x10, x3, x5)

inst_785:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x107 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1a3 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x314 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3907; op2val:0xada3;
op3val:0x2b14; valaddr_reg:x8; val_offset:2289*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2289*FLEN/8, x10, x3, x5)

inst_786:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x107 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1a3 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x314 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3907; op2val:0xada3;
op3val:0x2b14; valaddr_reg:x8; val_offset:2292*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2292*FLEN/8, x10, x3, x5)

inst_787:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x107 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1a3 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x314 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3907; op2val:0xada3;
op3val:0x2b14; valaddr_reg:x8; val_offset:2295*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2295*FLEN/8, x10, x3, x5)

inst_788:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x107 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1a3 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x314 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3907; op2val:0xada3;
op3val:0x2b14; valaddr_reg:x8; val_offset:2298*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2298*FLEN/8, x10, x3, x5)

inst_789:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x107 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x1a3 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x314 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3907; op2val:0xada3;
op3val:0x2b14; valaddr_reg:x8; val_offset:2301*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2301*FLEN/8, x10, x3, x5)

inst_790:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x139 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x361 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0d1 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3939; op2val:0xb761;
op3val:0x34d1; valaddr_reg:x8; val_offset:2304*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2304*FLEN/8, x10, x3, x5)

inst_791:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x139 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x361 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0d1 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3939; op2val:0xb761;
op3val:0x34d1; valaddr_reg:x8; val_offset:2307*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2307*FLEN/8, x10, x3, x5)
RVTEST_SIGBASE(x3,signature_x3_6)

inst_792:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x139 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x361 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0d1 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3939; op2val:0xb761;
op3val:0x34d1; valaddr_reg:x8; val_offset:2310*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2310*FLEN/8, x10, x3, x5)

inst_793:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x139 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x361 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0d1 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3939; op2val:0xb761;
op3val:0x34d1; valaddr_reg:x8; val_offset:2313*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2313*FLEN/8, x10, x3, x5)

inst_794:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x139 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x361 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0d1 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3939; op2val:0xb761;
op3val:0x34d1; valaddr_reg:x8; val_offset:2316*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2316*FLEN/8, x10, x3, x5)

inst_795:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x20e and fs2 == 1 and fe2 == 0x10 and fm2 == 0x086 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2da and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x360e; op2val:0xc086;
op3val:0x3ada; valaddr_reg:x8; val_offset:2319*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2319*FLEN/8, x10, x3, x5)

inst_796:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x20e and fs2 == 1 and fe2 == 0x10 and fm2 == 0x086 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2da and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x360e; op2val:0xc086;
op3val:0x3ada; valaddr_reg:x8; val_offset:2322*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2322*FLEN/8, x10, x3, x5)

inst_797:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x20e and fs2 == 1 and fe2 == 0x10 and fm2 == 0x086 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2da and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x360e; op2val:0xc086;
op3val:0x3ada; valaddr_reg:x8; val_offset:2325*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2325*FLEN/8, x10, x3, x5)

inst_798:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x20e and fs2 == 1 and fe2 == 0x10 and fm2 == 0x086 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2da and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x360e; op2val:0xc086;
op3val:0x3ada; valaddr_reg:x8; val_offset:2328*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2328*FLEN/8, x10, x3, x5)

inst_799:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x20e and fs2 == 1 and fe2 == 0x10 and fm2 == 0x086 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2da and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x360e; op2val:0xc086;
op3val:0x3ada; valaddr_reg:x8; val_offset:2331*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2331*FLEN/8, x10, x3, x5)

inst_800:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x35c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34fc; op2val:0xc1e8;
op3val:0x3b5c; valaddr_reg:x8; val_offset:2334*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2334*FLEN/8, x10, x3, x5)

inst_801:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x35c and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34fc; op2val:0xc1e8;
op3val:0x3b5c; valaddr_reg:x8; val_offset:2337*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2337*FLEN/8, x10, x3, x5)

inst_802:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x35c and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34fc; op2val:0xc1e8;
op3val:0x3b5c; valaddr_reg:x8; val_offset:2340*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2340*FLEN/8, x10, x3, x5)

inst_803:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x35c and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34fc; op2val:0xc1e8;
op3val:0x3b5c; valaddr_reg:x8; val_offset:2343*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2343*FLEN/8, x10, x3, x5)

inst_804:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0fc and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e8 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x35c and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34fc; op2val:0xc1e8;
op3val:0x3b5c; valaddr_reg:x8; val_offset:2346*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2346*FLEN/8, x10, x3, x5)

inst_805:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x285 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x01f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b8 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a85; op2val:0xb81f;
op3val:0x36b8; valaddr_reg:x8; val_offset:2349*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2349*FLEN/8, x10, x3, x5)

inst_806:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x285 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x01f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b8 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a85; op2val:0xb81f;
op3val:0x36b8; valaddr_reg:x8; val_offset:2352*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2352*FLEN/8, x10, x3, x5)

inst_807:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x285 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x01f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b8 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a85; op2val:0xb81f;
op3val:0x36b8; valaddr_reg:x8; val_offset:2355*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2355*FLEN/8, x10, x3, x5)

inst_808:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x285 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x01f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b8 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a85; op2val:0xb81f;
op3val:0x36b8; valaddr_reg:x8; val_offset:2358*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2358*FLEN/8, x10, x3, x5)

inst_809:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x285 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x01f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b8 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a85; op2val:0xb81f;
op3val:0x36b8; valaddr_reg:x8; val_offset:2361*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2361*FLEN/8, x10, x3, x5)

inst_810:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fb and fs2 == 1 and fe2 == 0x0a and fm2 == 0x13a and fs3 == 0 and fe3 == 0x0a and fm3 == 0x08e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3afb; op2val:0xa93a;
op3val:0x288e; valaddr_reg:x8; val_offset:2364*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2364*FLEN/8, x10, x3, x5)

inst_811:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fb and fs2 == 1 and fe2 == 0x0a and fm2 == 0x13a and fs3 == 0 and fe3 == 0x0a and fm3 == 0x08e and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3afb; op2val:0xa93a;
op3val:0x288e; valaddr_reg:x8; val_offset:2367*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2367*FLEN/8, x10, x3, x5)

inst_812:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fb and fs2 == 1 and fe2 == 0x0a and fm2 == 0x13a and fs3 == 0 and fe3 == 0x0a and fm3 == 0x08e and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3afb; op2val:0xa93a;
op3val:0x288e; valaddr_reg:x8; val_offset:2370*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2370*FLEN/8, x10, x3, x5)

inst_813:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fb and fs2 == 1 and fe2 == 0x0a and fm2 == 0x13a and fs3 == 0 and fe3 == 0x0a and fm3 == 0x08e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3afb; op2val:0xa93a;
op3val:0x288e; valaddr_reg:x8; val_offset:2373*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2373*FLEN/8, x10, x3, x5)

inst_814:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fb and fs2 == 1 and fe2 == 0x0a and fm2 == 0x13a and fs3 == 0 and fe3 == 0x0a and fm3 == 0x08e and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3afb; op2val:0xa93a;
op3val:0x288e; valaddr_reg:x8; val_offset:2376*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2376*FLEN/8, x10, x3, x5)

inst_815:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x098 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x126 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1ea and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3898; op2val:0xb926;
op3val:0x35ea; valaddr_reg:x8; val_offset:2379*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2379*FLEN/8, x10, x3, x5)

inst_816:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x098 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x126 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1ea and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3898; op2val:0xb926;
op3val:0x35ea; valaddr_reg:x8; val_offset:2382*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2382*FLEN/8, x10, x3, x5)

inst_817:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x098 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x126 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1ea and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3898; op2val:0xb926;
op3val:0x35ea; valaddr_reg:x8; val_offset:2385*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2385*FLEN/8, x10, x3, x5)

inst_818:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x098 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x126 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1ea and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3898; op2val:0xb926;
op3val:0x35ea; valaddr_reg:x8; val_offset:2388*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2388*FLEN/8, x10, x3, x5)

inst_819:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x098 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x126 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1ea and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3898; op2val:0xb926;
op3val:0x35ea; valaddr_reg:x8; val_offset:2391*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2391*FLEN/8, x10, x3, x5)

inst_820:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x078 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x262 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x322 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2878; op2val:0xce62;
op3val:0x3b22; valaddr_reg:x8; val_offset:2394*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2394*FLEN/8, x10, x3, x5)

inst_821:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x078 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x262 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x322 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2878; op2val:0xce62;
op3val:0x3b22; valaddr_reg:x8; val_offset:2397*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2397*FLEN/8, x10, x3, x5)

inst_822:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x078 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x262 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x322 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2878; op2val:0xce62;
op3val:0x3b22; valaddr_reg:x8; val_offset:2400*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2400*FLEN/8, x10, x3, x5)

inst_823:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x078 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x262 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x322 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2878; op2val:0xce62;
op3val:0x3b22; valaddr_reg:x8; val_offset:2403*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2403*FLEN/8, x10, x3, x5)

inst_824:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x078 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x262 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x322 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2878; op2val:0xce62;
op3val:0x3b22; valaddr_reg:x8; val_offset:2406*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2406*FLEN/8, x10, x3, x5)

inst_825:
// fs1 == 0 and fe1 == 0x05 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x3a1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3ae and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1407; op2val:0xe3a1;
op3val:0x3bae; valaddr_reg:x8; val_offset:2409*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2409*FLEN/8, x10, x3, x5)

inst_826:
// fs1 == 0 and fe1 == 0x05 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x3a1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3ae and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1407; op2val:0xe3a1;
op3val:0x3bae; valaddr_reg:x8; val_offset:2412*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2412*FLEN/8, x10, x3, x5)

inst_827:
// fs1 == 0 and fe1 == 0x05 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x3a1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3ae and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1407; op2val:0xe3a1;
op3val:0x3bae; valaddr_reg:x8; val_offset:2415*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2415*FLEN/8, x10, x3, x5)

inst_828:
// fs1 == 0 and fe1 == 0x05 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x3a1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3ae and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1407; op2val:0xe3a1;
op3val:0x3bae; valaddr_reg:x8; val_offset:2418*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2418*FLEN/8, x10, x3, x5)

inst_829:
// fs1 == 0 and fe1 == 0x05 and fm1 == 0x007 and fs2 == 1 and fe2 == 0x18 and fm2 == 0x3a1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3ae and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1407; op2val:0xe3a1;
op3val:0x3bae; valaddr_reg:x8; val_offset:2421*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2421*FLEN/8, x10, x3, x5)

inst_830:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x261 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2e7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x181 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3661; op2val:0xbae7;
op3val:0x3581; valaddr_reg:x8; val_offset:2424*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2424*FLEN/8, x10, x3, x5)

inst_831:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x261 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2e7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x181 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3661; op2val:0xbae7;
op3val:0x3581; valaddr_reg:x8; val_offset:2427*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2427*FLEN/8, x10, x3, x5)

inst_832:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x261 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2e7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x181 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3661; op2val:0xbae7;
op3val:0x3581; valaddr_reg:x8; val_offset:2430*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2430*FLEN/8, x10, x3, x5)

inst_833:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x261 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2e7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x181 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3661; op2val:0xbae7;
op3val:0x3581; valaddr_reg:x8; val_offset:2433*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2433*FLEN/8, x10, x3, x5)

inst_834:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x261 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2e7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x181 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3661; op2val:0xbae7;
op3val:0x3581; valaddr_reg:x8; val_offset:2436*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2436*FLEN/8, x10, x3, x5)

inst_835:
// fs1 == 0 and fe1 == 0x08 and fm1 == 0x346 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x122 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2346; op2val:0xd1a5;
op3val:0x3922; valaddr_reg:x8; val_offset:2439*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2439*FLEN/8, x10, x3, x5)

inst_836:
// fs1 == 0 and fe1 == 0x08 and fm1 == 0x346 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x122 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2346; op2val:0xd1a5;
op3val:0x3922; valaddr_reg:x8; val_offset:2442*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2442*FLEN/8, x10, x3, x5)

inst_837:
// fs1 == 0 and fe1 == 0x08 and fm1 == 0x346 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x122 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2346; op2val:0xd1a5;
op3val:0x3922; valaddr_reg:x8; val_offset:2445*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2445*FLEN/8, x10, x3, x5)

inst_838:
// fs1 == 0 and fe1 == 0x08 and fm1 == 0x346 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x122 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2346; op2val:0xd1a5;
op3val:0x3922; valaddr_reg:x8; val_offset:2448*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2448*FLEN/8, x10, x3, x5)

inst_839:
// fs1 == 0 and fe1 == 0x08 and fm1 == 0x346 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1a5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x122 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2346; op2val:0xd1a5;
op3val:0x3922; valaddr_reg:x8; val_offset:2451*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2451*FLEN/8, x10, x3, x5)

inst_840:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2d2 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x290 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x198 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ad2; op2val:0xc690;
op3val:0x3598; valaddr_reg:x8; val_offset:2454*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2454*FLEN/8, x10, x3, x5)

inst_841:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2d2 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x290 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x198 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ad2; op2val:0xc690;
op3val:0x3598; valaddr_reg:x8; val_offset:2457*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2457*FLEN/8, x10, x3, x5)

inst_842:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2d2 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x290 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x198 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ad2; op2val:0xc690;
op3val:0x3598; valaddr_reg:x8; val_offset:2460*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2460*FLEN/8, x10, x3, x5)

inst_843:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2d2 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x290 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x198 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ad2; op2val:0xc690;
op3val:0x3598; valaddr_reg:x8; val_offset:2463*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2463*FLEN/8, x10, x3, x5)

inst_844:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2d2 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x290 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x198 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ad2; op2val:0xc690;
op3val:0x3598; valaddr_reg:x8; val_offset:2466*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2466*FLEN/8, x10, x3, x5)

inst_845:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x258 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2a4 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x382f; op2val:0xbe58;
op3val:0x3aa4; valaddr_reg:x8; val_offset:2469*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2469*FLEN/8, x10, x3, x5)

inst_846:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x258 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2a4 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x382f; op2val:0xbe58;
op3val:0x3aa4; valaddr_reg:x8; val_offset:2472*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2472*FLEN/8, x10, x3, x5)

inst_847:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x258 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2a4 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x382f; op2val:0xbe58;
op3val:0x3aa4; valaddr_reg:x8; val_offset:2475*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2475*FLEN/8, x10, x3, x5)

inst_848:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x258 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2a4 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x382f; op2val:0xbe58;
op3val:0x3aa4; valaddr_reg:x8; val_offset:2478*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2478*FLEN/8, x10, x3, x5)

inst_849:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x02f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x258 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2a4 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x382f; op2val:0xbe58;
op3val:0x3aa4; valaddr_reg:x8; val_offset:2481*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2481*FLEN/8, x10, x3, x5)

inst_850:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x21d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2a5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x114 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a1d; op2val:0xbaa5;
op3val:0x3914; valaddr_reg:x8; val_offset:2484*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2484*FLEN/8, x10, x3, x5)

inst_851:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x21d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2a5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x114 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a1d; op2val:0xbaa5;
op3val:0x3914; valaddr_reg:x8; val_offset:2487*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2487*FLEN/8, x10, x3, x5)

inst_852:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x21d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2a5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x114 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a1d; op2val:0xbaa5;
op3val:0x3914; valaddr_reg:x8; val_offset:2490*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2490*FLEN/8, x10, x3, x5)

inst_853:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x21d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2a5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x114 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a1d; op2val:0xbaa5;
op3val:0x3914; valaddr_reg:x8; val_offset:2493*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2493*FLEN/8, x10, x3, x5)

inst_854:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x21d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2a5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x114 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a1d; op2val:0xbaa5;
op3val:0x3914; valaddr_reg:x8; val_offset:2496*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2496*FLEN/8, x10, x3, x5)

inst_855:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x13a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x106 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x393a; op2val:0xbbb0;
op3val:0x3906; valaddr_reg:x8; val_offset:2499*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2499*FLEN/8, x10, x3, x5)

inst_856:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x13a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x106 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x393a; op2val:0xbbb0;
op3val:0x3906; valaddr_reg:x8; val_offset:2502*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2502*FLEN/8, x10, x3, x5)

inst_857:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x13a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x106 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x393a; op2val:0xbbb0;
op3val:0x3906; valaddr_reg:x8; val_offset:2505*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2505*FLEN/8, x10, x3, x5)

inst_858:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x13a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x106 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x393a; op2val:0xbbb0;
op3val:0x3906; valaddr_reg:x8; val_offset:2508*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2508*FLEN/8, x10, x3, x5)

inst_859:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x13a and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3b0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x106 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x393a; op2val:0xbbb0;
op3val:0x3906; valaddr_reg:x8; val_offset:2511*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2511*FLEN/8, x10, x3, x5)

inst_860:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x224 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x283 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x100 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3224; op2val:0xc283;
op3val:0x3900; valaddr_reg:x8; val_offset:2514*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2514*FLEN/8, x10, x3, x5)

inst_861:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x224 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x283 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x100 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3224; op2val:0xc283;
op3val:0x3900; valaddr_reg:x8; val_offset:2517*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2517*FLEN/8, x10, x3, x5)

inst_862:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x224 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x283 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x100 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3224; op2val:0xc283;
op3val:0x3900; valaddr_reg:x8; val_offset:2520*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2520*FLEN/8, x10, x3, x5)

inst_863:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x224 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x283 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x100 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3224; op2val:0xc283;
op3val:0x3900; valaddr_reg:x8; val_offset:2523*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2523*FLEN/8, x10, x3, x5)

inst_864:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x224 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x283 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x100 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3224; op2val:0xc283;
op3val:0x3900; valaddr_reg:x8; val_offset:2526*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2526*FLEN/8, x10, x3, x5)

inst_865:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f1 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x12d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3b0 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35f1; op2val:0xc12d;
op3val:0x3bb0; valaddr_reg:x8; val_offset:2529*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2529*FLEN/8, x10, x3, x5)

inst_866:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f1 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x12d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3b0 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35f1; op2val:0xc12d;
op3val:0x3bb0; valaddr_reg:x8; val_offset:2532*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2532*FLEN/8, x10, x3, x5)

inst_867:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f1 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x12d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3b0 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35f1; op2val:0xc12d;
op3val:0x3bb0; valaddr_reg:x8; val_offset:2535*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2535*FLEN/8, x10, x3, x5)

inst_868:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f1 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x12d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3b0 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35f1; op2val:0xc12d;
op3val:0x3bb0; valaddr_reg:x8; val_offset:2538*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2538*FLEN/8, x10, x3, x5)

inst_869:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1f1 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x12d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3b0 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35f1; op2val:0xc12d;
op3val:0x3bb0; valaddr_reg:x8; val_offset:2541*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2541*FLEN/8, x10, x3, x5)

inst_870:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2df and fs2 == 1 and fe2 == 0x0d and fm2 == 0x167 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0a4 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3adf; op2val:0xb567;
op3val:0x34a4; valaddr_reg:x8; val_offset:2544*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2544*FLEN/8, x10, x3, x5)

inst_871:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2df and fs2 == 1 and fe2 == 0x0d and fm2 == 0x167 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0a4 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3adf; op2val:0xb567;
op3val:0x34a4; valaddr_reg:x8; val_offset:2547*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2547*FLEN/8, x10, x3, x5)

inst_872:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2df and fs2 == 1 and fe2 == 0x0d and fm2 == 0x167 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0a4 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3adf; op2val:0xb567;
op3val:0x34a4; valaddr_reg:x8; val_offset:2550*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2550*FLEN/8, x10, x3, x5)

inst_873:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2df and fs2 == 1 and fe2 == 0x0d and fm2 == 0x167 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0a4 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3adf; op2val:0xb567;
op3val:0x34a4; valaddr_reg:x8; val_offset:2553*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2553*FLEN/8, x10, x3, x5)

inst_874:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2df and fs2 == 1 and fe2 == 0x0d and fm2 == 0x167 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0a4 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3adf; op2val:0xb567;
op3val:0x34a4; valaddr_reg:x8; val_offset:2556*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2556*FLEN/8, x10, x3, x5)

inst_875:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x301 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x246 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x17e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f01; op2val:0xc646;
op3val:0x397e; valaddr_reg:x8; val_offset:2559*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2559*FLEN/8, x10, x3, x5)

inst_876:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x301 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x246 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x17e and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f01; op2val:0xc646;
op3val:0x397e; valaddr_reg:x8; val_offset:2562*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2562*FLEN/8, x10, x3, x5)

inst_877:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x301 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x246 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x17e and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f01; op2val:0xc646;
op3val:0x397e; valaddr_reg:x8; val_offset:2565*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2565*FLEN/8, x10, x3, x5)

inst_878:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x301 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x246 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x17e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f01; op2val:0xc646;
op3val:0x397e; valaddr_reg:x8; val_offset:2568*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2568*FLEN/8, x10, x3, x5)

inst_879:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x301 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x246 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x17e and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f01; op2val:0xc646;
op3val:0x397e; valaddr_reg:x8; val_offset:2571*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2571*FLEN/8, x10, x3, x5)

inst_880:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3bd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x258 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x223 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bbd; op2val:0xba58;
op3val:0x3a23; valaddr_reg:x8; val_offset:2574*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2574*FLEN/8, x10, x3, x5)

inst_881:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3bd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x258 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x223 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bbd; op2val:0xba58;
op3val:0x3a23; valaddr_reg:x8; val_offset:2577*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2577*FLEN/8, x10, x3, x5)

inst_882:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3bd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x258 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x223 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bbd; op2val:0xba58;
op3val:0x3a23; valaddr_reg:x8; val_offset:2580*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2580*FLEN/8, x10, x3, x5)

inst_883:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3bd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x258 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x223 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bbd; op2val:0xba58;
op3val:0x3a23; valaddr_reg:x8; val_offset:2583*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2583*FLEN/8, x10, x3, x5)

inst_884:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3bd and fs2 == 1 and fe2 == 0x0e and fm2 == 0x258 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x223 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bbd; op2val:0xba58;
op3val:0x3a23; valaddr_reg:x8; val_offset:2586*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2586*FLEN/8, x10, x3, x5)

inst_885:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ed and fs3 == 0 and fe3 == 0x0e and fm3 == 0x111 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391d; op2val:0xbbed;
op3val:0x3911; valaddr_reg:x8; val_offset:2589*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2589*FLEN/8, x10, x3, x5)

inst_886:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ed and fs3 == 0 and fe3 == 0x0e and fm3 == 0x111 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391d; op2val:0xbbed;
op3val:0x3911; valaddr_reg:x8; val_offset:2592*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2592*FLEN/8, x10, x3, x5)

inst_887:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ed and fs3 == 0 and fe3 == 0x0e and fm3 == 0x111 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391d; op2val:0xbbed;
op3val:0x3911; valaddr_reg:x8; val_offset:2595*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2595*FLEN/8, x10, x3, x5)

inst_888:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ed and fs3 == 0 and fe3 == 0x0e and fm3 == 0x111 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391d; op2val:0xbbed;
op3val:0x3911; valaddr_reg:x8; val_offset:2598*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2598*FLEN/8, x10, x3, x5)

inst_889:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3ed and fs3 == 0 and fe3 == 0x0e and fm3 == 0x111 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391d; op2val:0xbbed;
op3val:0x3911; valaddr_reg:x8; val_offset:2601*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2601*FLEN/8, x10, x3, x5)

inst_890:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x304 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x25e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x196 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3704; op2val:0xbe5e;
op3val:0x3996; valaddr_reg:x8; val_offset:2604*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2604*FLEN/8, x10, x3, x5)

inst_891:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x304 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x25e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x196 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3704; op2val:0xbe5e;
op3val:0x3996; valaddr_reg:x8; val_offset:2607*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2607*FLEN/8, x10, x3, x5)

inst_892:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x304 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x25e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x196 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3704; op2val:0xbe5e;
op3val:0x3996; valaddr_reg:x8; val_offset:2610*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2610*FLEN/8, x10, x3, x5)

inst_893:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x304 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x25e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x196 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3704; op2val:0xbe5e;
op3val:0x3996; valaddr_reg:x8; val_offset:2613*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2613*FLEN/8, x10, x3, x5)

inst_894:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x304 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x25e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x196 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3704; op2val:0xbe5e;
op3val:0x3996; valaddr_reg:x8; val_offset:2616*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2616*FLEN/8, x10, x3, x5)

inst_895:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0da and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2da and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35a5; op2val:0xb8da;
op3val:0x32da; valaddr_reg:x8; val_offset:2619*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2619*FLEN/8, x10, x3, x5)

inst_896:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0da and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2da and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35a5; op2val:0xb8da;
op3val:0x32da; valaddr_reg:x8; val_offset:2622*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2622*FLEN/8, x10, x3, x5)

inst_897:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0da and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2da and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35a5; op2val:0xb8da;
op3val:0x32da; valaddr_reg:x8; val_offset:2625*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2625*FLEN/8, x10, x3, x5)

inst_898:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0da and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2da and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35a5; op2val:0xb8da;
op3val:0x32da; valaddr_reg:x8; val_offset:2628*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2628*FLEN/8, x10, x3, x5)

inst_899:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1a5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0da and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2da and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35a5; op2val:0xb8da;
op3val:0x32da; valaddr_reg:x8; val_offset:2631*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2631*FLEN/8, x10, x3, x5)

inst_900:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2f0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x023 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32f0; op2val:0xbcc5;
op3val:0x3423; valaddr_reg:x8; val_offset:2634*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2634*FLEN/8, x10, x3, x5)

inst_901:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2f0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x023 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32f0; op2val:0xbcc5;
op3val:0x3423; valaddr_reg:x8; val_offset:2637*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2637*FLEN/8, x10, x3, x5)

inst_902:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2f0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x023 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32f0; op2val:0xbcc5;
op3val:0x3423; valaddr_reg:x8; val_offset:2640*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2640*FLEN/8, x10, x3, x5)

inst_903:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2f0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x023 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32f0; op2val:0xbcc5;
op3val:0x3423; valaddr_reg:x8; val_offset:2643*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2643*FLEN/8, x10, x3, x5)

inst_904:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x2f0 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x023 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x32f0; op2val:0xbcc5;
op3val:0x3423; valaddr_reg:x8; val_offset:2646*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2646*FLEN/8, x10, x3, x5)

inst_905:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2a7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x31b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e9 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36a7; op2val:0xbf1b;
op3val:0x39e9; valaddr_reg:x8; val_offset:2649*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2649*FLEN/8, x10, x3, x5)

inst_906:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2a7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x31b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e9 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36a7; op2val:0xbf1b;
op3val:0x39e9; valaddr_reg:x8; val_offset:2652*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2652*FLEN/8, x10, x3, x5)

inst_907:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2a7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x31b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e9 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36a7; op2val:0xbf1b;
op3val:0x39e9; valaddr_reg:x8; val_offset:2655*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2655*FLEN/8, x10, x3, x5)

inst_908:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2a7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x31b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e9 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36a7; op2val:0xbf1b;
op3val:0x39e9; valaddr_reg:x8; val_offset:2658*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2658*FLEN/8, x10, x3, x5)

inst_909:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2a7 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x31b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1e9 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36a7; op2val:0xbf1b;
op3val:0x39e9; valaddr_reg:x8; val_offset:2661*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2661*FLEN/8, x10, x3, x5)

inst_910:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x113 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x07a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ae and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3113; op2val:0xc47a;
op3val:0x39ae; valaddr_reg:x8; val_offset:2664*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2664*FLEN/8, x10, x3, x5)

inst_911:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x113 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x07a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ae and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3113; op2val:0xc47a;
op3val:0x39ae; valaddr_reg:x8; val_offset:2667*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2667*FLEN/8, x10, x3, x5)

inst_912:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x113 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x07a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ae and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3113; op2val:0xc47a;
op3val:0x39ae; valaddr_reg:x8; val_offset:2670*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2670*FLEN/8, x10, x3, x5)

inst_913:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x113 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x07a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ae and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3113; op2val:0xc47a;
op3val:0x39ae; valaddr_reg:x8; val_offset:2673*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2673*FLEN/8, x10, x3, x5)

inst_914:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x113 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x07a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1ae and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3113; op2val:0xc47a;
op3val:0x39ae; valaddr_reg:x8; val_offset:2676*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2676*FLEN/8, x10, x3, x5)

inst_915:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x07a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3e6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x06c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x307a; op2val:0xc3e6;
op3val:0x386c; valaddr_reg:x8; val_offset:2679*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2679*FLEN/8, x10, x3, x5)

inst_916:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x07a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3e6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x06c and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x307a; op2val:0xc3e6;
op3val:0x386c; valaddr_reg:x8; val_offset:2682*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2682*FLEN/8, x10, x3, x5)

inst_917:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x07a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3e6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x06c and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x307a; op2val:0xc3e6;
op3val:0x386c; valaddr_reg:x8; val_offset:2685*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2685*FLEN/8, x10, x3, x5)

inst_918:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x07a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3e6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x06c and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x307a; op2val:0xc3e6;
op3val:0x386c; valaddr_reg:x8; val_offset:2688*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2688*FLEN/8, x10, x3, x5)

inst_919:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x07a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3e6 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x06c and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x307a; op2val:0xc3e6;
op3val:0x386c; valaddr_reg:x8; val_offset:2691*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2691*FLEN/8, x10, x3, x5)
RVTEST_SIGBASE(x3,signature_x3_7)

inst_920:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ee and fs2 == 1 and fe2 == 0x0f and fm2 == 0x167 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x001 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ee; op2val:0xbd67;
op3val:0x3801; valaddr_reg:x8; val_offset:2694*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2694*FLEN/8, x10, x3, x5)

inst_921:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ee and fs2 == 1 and fe2 == 0x0f and fm2 == 0x167 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x001 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ee; op2val:0xbd67;
op3val:0x3801; valaddr_reg:x8; val_offset:2697*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2697*FLEN/8, x10, x3, x5)

inst_922:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ee and fs2 == 1 and fe2 == 0x0f and fm2 == 0x167 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x001 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ee; op2val:0xbd67;
op3val:0x3801; valaddr_reg:x8; val_offset:2700*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2700*FLEN/8, x10, x3, x5)

inst_923:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ee and fs2 == 1 and fe2 == 0x0f and fm2 == 0x167 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x001 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ee; op2val:0xbd67;
op3val:0x3801; valaddr_reg:x8; val_offset:2703*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2703*FLEN/8, x10, x3, x5)

inst_924:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ee and fs2 == 1 and fe2 == 0x0f and fm2 == 0x167 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x001 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ee; op2val:0xbd67;
op3val:0x3801; valaddr_reg:x8; val_offset:2706*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2706*FLEN/8, x10, x3, x5)

inst_925:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x189 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x39d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x145 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3589; op2val:0xbf9d;
op3val:0x3945; valaddr_reg:x8; val_offset:2709*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2709*FLEN/8, x10, x3, x5)

inst_926:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x189 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x39d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x145 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3589; op2val:0xbf9d;
op3val:0x3945; valaddr_reg:x8; val_offset:2712*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2712*FLEN/8, x10, x3, x5)

inst_927:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x189 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x39d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x145 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3589; op2val:0xbf9d;
op3val:0x3945; valaddr_reg:x8; val_offset:2715*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2715*FLEN/8, x10, x3, x5)

inst_928:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x189 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x39d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x145 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3589; op2val:0xbf9d;
op3val:0x3945; valaddr_reg:x8; val_offset:2718*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2718*FLEN/8, x10, x3, x5)

inst_929:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x189 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x39d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x145 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3589; op2val:0xbf9d;
op3val:0x3945; valaddr_reg:x8; val_offset:2721*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2721*FLEN/8, x10, x3, x5)

inst_930:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2bf and fs2 == 1 and fe2 == 0x0e and fm2 == 0x100 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x037 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36bf; op2val:0xb900;
op3val:0x3437; valaddr_reg:x8; val_offset:2724*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2724*FLEN/8, x10, x3, x5)

inst_931:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2bf and fs2 == 1 and fe2 == 0x0e and fm2 == 0x100 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x037 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36bf; op2val:0xb900;
op3val:0x3437; valaddr_reg:x8; val_offset:2727*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2727*FLEN/8, x10, x3, x5)

inst_932:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2bf and fs2 == 1 and fe2 == 0x0e and fm2 == 0x100 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x037 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36bf; op2val:0xb900;
op3val:0x3437; valaddr_reg:x8; val_offset:2730*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2730*FLEN/8, x10, x3, x5)

inst_933:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2bf and fs2 == 1 and fe2 == 0x0e and fm2 == 0x100 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x037 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36bf; op2val:0xb900;
op3val:0x3437; valaddr_reg:x8; val_offset:2733*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2733*FLEN/8, x10, x3, x5)

inst_934:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2bf and fs2 == 1 and fe2 == 0x0e and fm2 == 0x100 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x037 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36bf; op2val:0xb900;
op3val:0x3437; valaddr_reg:x8; val_offset:2736*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2736*FLEN/8, x10, x3, x5)

inst_935:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x101 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x264 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391b; op2val:0xb901;
op3val:0x3664; valaddr_reg:x8; val_offset:2739*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2739*FLEN/8, x10, x3, x5)

inst_936:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x101 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x264 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391b; op2val:0xb901;
op3val:0x3664; valaddr_reg:x8; val_offset:2742*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2742*FLEN/8, x10, x3, x5)

inst_937:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x101 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x264 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391b; op2val:0xb901;
op3val:0x3664; valaddr_reg:x8; val_offset:2745*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2745*FLEN/8, x10, x3, x5)

inst_938:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x101 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x264 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391b; op2val:0xb901;
op3val:0x3664; valaddr_reg:x8; val_offset:2748*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2748*FLEN/8, x10, x3, x5)

inst_939:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x11b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x101 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x264 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x391b; op2val:0xb901;
op3val:0x3664; valaddr_reg:x8; val_offset:2751*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2751*FLEN/8, x10, x3, x5)

inst_940:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x059 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3cd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x03d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3859; op2val:0xbbcd;
op3val:0x383d; valaddr_reg:x8; val_offset:2754*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2754*FLEN/8, x10, x3, x5)

inst_941:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x059 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3cd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x03d and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3859; op2val:0xbbcd;
op3val:0x383d; valaddr_reg:x8; val_offset:2757*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2757*FLEN/8, x10, x3, x5)

inst_942:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x059 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3cd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x03d and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3859; op2val:0xbbcd;
op3val:0x383d; valaddr_reg:x8; val_offset:2760*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2760*FLEN/8, x10, x3, x5)

inst_943:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x059 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3cd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x03d and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3859; op2val:0xbbcd;
op3val:0x383d; valaddr_reg:x8; val_offset:2763*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2763*FLEN/8, x10, x3, x5)

inst_944:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x059 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3cd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x03d and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3859; op2val:0xbbcd;
op3val:0x383d; valaddr_reg:x8; val_offset:2766*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2766*FLEN/8, x10, x3, x5)

inst_945:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ee and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1e2 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x341 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ee; op2val:0xb9e2;
op3val:0x3741; valaddr_reg:x8; val_offset:2769*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2769*FLEN/8, x10, x3, x5)

inst_946:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ee and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1e2 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x341 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ee; op2val:0xb9e2;
op3val:0x3741; valaddr_reg:x8; val_offset:2772*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2772*FLEN/8, x10, x3, x5)

inst_947:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ee and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1e2 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x341 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ee; op2val:0xb9e2;
op3val:0x3741; valaddr_reg:x8; val_offset:2775*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2775*FLEN/8, x10, x3, x5)

inst_948:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ee and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1e2 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x341 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ee; op2val:0xb9e2;
op3val:0x3741; valaddr_reg:x8; val_offset:2778*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2778*FLEN/8, x10, x3, x5)

inst_949:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ee and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1e2 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x341 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ee; op2val:0xb9e2;
op3val:0x3741; valaddr_reg:x8; val_offset:2781*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2781*FLEN/8, x10, x3, x5)

inst_950:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0a6 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1af and fs3 == 0 and fe3 == 0x0e and fm3 == 0x29c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34a6; op2val:0xc1af;
op3val:0x3a9c; valaddr_reg:x8; val_offset:2784*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2784*FLEN/8, x10, x3, x5)

inst_951:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0a6 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1af and fs3 == 0 and fe3 == 0x0e and fm3 == 0x29c and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34a6; op2val:0xc1af;
op3val:0x3a9c; valaddr_reg:x8; val_offset:2787*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2787*FLEN/8, x10, x3, x5)

inst_952:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0a6 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1af and fs3 == 0 and fe3 == 0x0e and fm3 == 0x29c and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34a6; op2val:0xc1af;
op3val:0x3a9c; valaddr_reg:x8; val_offset:2790*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2790*FLEN/8, x10, x3, x5)

inst_953:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0a6 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1af and fs3 == 0 and fe3 == 0x0e and fm3 == 0x29c and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34a6; op2val:0xc1af;
op3val:0x3a9c; valaddr_reg:x8; val_offset:2793*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2793*FLEN/8, x10, x3, x5)

inst_954:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0a6 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1af and fs3 == 0 and fe3 == 0x0e and fm3 == 0x29c and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34a6; op2val:0xc1af;
op3val:0x3a9c; valaddr_reg:x8; val_offset:2796*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2796*FLEN/8, x10, x3, x5)

inst_955:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d4 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2a0 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1a8 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ad4; op2val:0xb2a0;
op3val:0x31a8; valaddr_reg:x8; val_offset:2799*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2799*FLEN/8, x10, x3, x5)

inst_956:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d4 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2a0 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1a8 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ad4; op2val:0xb2a0;
op3val:0x31a8; valaddr_reg:x8; val_offset:2802*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2802*FLEN/8, x10, x3, x5)

inst_957:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d4 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2a0 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1a8 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ad4; op2val:0xb2a0;
op3val:0x31a8; valaddr_reg:x8; val_offset:2805*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2805*FLEN/8, x10, x3, x5)

inst_958:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d4 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2a0 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1a8 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ad4; op2val:0xb2a0;
op3val:0x31a8; valaddr_reg:x8; val_offset:2808*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2808*FLEN/8, x10, x3, x5)

inst_959:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d4 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2a0 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1a8 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ad4; op2val:0xb2a0;
op3val:0x31a8; valaddr_reg:x8; val_offset:2811*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2811*FLEN/8, x10, x3, x5)

inst_960:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x34a and fs2 == 1 and fe2 == 0x0c and fm2 == 0x344 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x29f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b4a; op2val:0xb344;
op3val:0x329f; valaddr_reg:x8; val_offset:2814*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2814*FLEN/8, x10, x3, x5)

inst_961:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x34a and fs2 == 1 and fe2 == 0x0c and fm2 == 0x344 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x29f and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b4a; op2val:0xb344;
op3val:0x329f; valaddr_reg:x8; val_offset:2817*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2817*FLEN/8, x10, x3, x5)

inst_962:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x34a and fs2 == 1 and fe2 == 0x0c and fm2 == 0x344 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x29f and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b4a; op2val:0xb344;
op3val:0x329f; valaddr_reg:x8; val_offset:2820*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2820*FLEN/8, x10, x3, x5)

inst_963:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x34a and fs2 == 1 and fe2 == 0x0c and fm2 == 0x344 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x29f and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b4a; op2val:0xb344;
op3val:0x329f; valaddr_reg:x8; val_offset:2823*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2823*FLEN/8, x10, x3, x5)

inst_964:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x34a and fs2 == 1 and fe2 == 0x0c and fm2 == 0x344 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x29f and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b4a; op2val:0xb344;
op3val:0x329f; valaddr_reg:x8; val_offset:2826*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2826*FLEN/8, x10, x3, x5)

inst_965:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3b5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x27e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x242 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x33b5; op2val:0xc27e;
op3val:0x3a42; valaddr_reg:x8; val_offset:2829*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2829*FLEN/8, x10, x3, x5)

inst_966:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3b5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x27e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x242 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x33b5; op2val:0xc27e;
op3val:0x3a42; valaddr_reg:x8; val_offset:2832*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2832*FLEN/8, x10, x3, x5)

inst_967:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3b5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x27e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x242 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x33b5; op2val:0xc27e;
op3val:0x3a42; valaddr_reg:x8; val_offset:2835*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2835*FLEN/8, x10, x3, x5)

inst_968:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3b5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x27e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x242 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x33b5; op2val:0xc27e;
op3val:0x3a42; valaddr_reg:x8; val_offset:2838*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2838*FLEN/8, x10, x3, x5)

inst_969:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x3b5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x27e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x242 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x33b5; op2val:0xc27e;
op3val:0x3a42; valaddr_reg:x8; val_offset:2841*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2841*FLEN/8, x10, x3, x5)

inst_970:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1d2 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x01a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1f9 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35d2; op2val:0xc01a;
op3val:0x39f9; valaddr_reg:x8; val_offset:2844*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2844*FLEN/8, x10, x3, x5)

inst_971:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1d2 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x01a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1f9 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35d2; op2val:0xc01a;
op3val:0x39f9; valaddr_reg:x8; val_offset:2847*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2847*FLEN/8, x10, x3, x5)

inst_972:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1d2 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x01a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1f9 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35d2; op2val:0xc01a;
op3val:0x39f9; valaddr_reg:x8; val_offset:2850*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2850*FLEN/8, x10, x3, x5)

inst_973:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1d2 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x01a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1f9 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35d2; op2val:0xc01a;
op3val:0x39f9; valaddr_reg:x8; val_offset:2853*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2853*FLEN/8, x10, x3, x5)

inst_974:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1d2 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x01a and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1f9 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35d2; op2val:0xc01a;
op3val:0x39f9; valaddr_reg:x8; val_offset:2856*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2856*FLEN/8, x10, x3, x5)

inst_975:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x393 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2c7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x26b and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f93; op2val:0xc6c7;
op3val:0x3a6b; valaddr_reg:x8; val_offset:2859*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2859*FLEN/8, x10, x3, x5)

inst_976:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x393 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2c7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x26b and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f93; op2val:0xc6c7;
op3val:0x3a6b; valaddr_reg:x8; val_offset:2862*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2862*FLEN/8, x10, x3, x5)

inst_977:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x393 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2c7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x26b and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f93; op2val:0xc6c7;
op3val:0x3a6b; valaddr_reg:x8; val_offset:2865*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2865*FLEN/8, x10, x3, x5)

inst_978:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x393 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2c7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x26b and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f93; op2val:0xc6c7;
op3val:0x3a6b; valaddr_reg:x8; val_offset:2868*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2868*FLEN/8, x10, x3, x5)

inst_979:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x393 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2c7 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x26b and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f93; op2val:0xc6c7;
op3val:0x3a6b; valaddr_reg:x8; val_offset:2871*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2871*FLEN/8, x10, x3, x5)

inst_980:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x313 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x05b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3b5 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b13; op2val:0xbc5b;
op3val:0x3bb5; valaddr_reg:x8; val_offset:2874*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2874*FLEN/8, x10, x3, x5)

inst_981:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x313 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x05b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3b5 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b13; op2val:0xbc5b;
op3val:0x3bb5; valaddr_reg:x8; val_offset:2877*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2877*FLEN/8, x10, x3, x5)

inst_982:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x313 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x05b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3b5 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b13; op2val:0xbc5b;
op3val:0x3bb5; valaddr_reg:x8; val_offset:2880*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2880*FLEN/8, x10, x3, x5)

inst_983:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x313 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x05b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3b5 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b13; op2val:0xbc5b;
op3val:0x3bb5; valaddr_reg:x8; val_offset:2883*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2883*FLEN/8, x10, x3, x5)

inst_984:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x313 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x05b and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3b5 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b13; op2val:0xbc5b;
op3val:0x3bb5; valaddr_reg:x8; val_offset:2886*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2886*FLEN/8, x10, x3, x5)

inst_985:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x081 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x199 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x24e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3481; op2val:0xc199;
op3val:0x3a4e; valaddr_reg:x8; val_offset:2889*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2889*FLEN/8, x10, x3, x5)

inst_986:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x081 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x199 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x24e and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3481; op2val:0xc199;
op3val:0x3a4e; valaddr_reg:x8; val_offset:2892*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2892*FLEN/8, x10, x3, x5)

inst_987:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x081 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x199 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x24e and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3481; op2val:0xc199;
op3val:0x3a4e; valaddr_reg:x8; val_offset:2895*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2895*FLEN/8, x10, x3, x5)

inst_988:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x081 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x199 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x24e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3481; op2val:0xc199;
op3val:0x3a4e; valaddr_reg:x8; val_offset:2898*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2898*FLEN/8, x10, x3, x5)

inst_989:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x081 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x199 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x24e and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3481; op2val:0xc199;
op3val:0x3a4e; valaddr_reg:x8; val_offset:2901*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2901*FLEN/8, x10, x3, x5)

inst_990:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x17c and fs2 == 1 and fe2 == 0x0a and fm2 == 0x052 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x1e9 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x397c; op2val:0xa852;
op3val:0x25e9; valaddr_reg:x8; val_offset:2904*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2904*FLEN/8, x10, x3, x5)

inst_991:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x17c and fs2 == 1 and fe2 == 0x0a and fm2 == 0x052 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x1e9 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x397c; op2val:0xa852;
op3val:0x25e9; valaddr_reg:x8; val_offset:2907*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2907*FLEN/8, x10, x3, x5)

inst_992:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x17c and fs2 == 1 and fe2 == 0x0a and fm2 == 0x052 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x1e9 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x397c; op2val:0xa852;
op3val:0x25e9; valaddr_reg:x8; val_offset:2910*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2910*FLEN/8, x10, x3, x5)

inst_993:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x17c and fs2 == 1 and fe2 == 0x0a and fm2 == 0x052 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x1e9 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x397c; op2val:0xa852;
op3val:0x25e9; valaddr_reg:x8; val_offset:2913*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2913*FLEN/8, x10, x3, x5)

inst_994:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x17c and fs2 == 1 and fe2 == 0x0a and fm2 == 0x052 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x1e9 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x397c; op2val:0xa852;
op3val:0x25e9; valaddr_reg:x8; val_offset:2916*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2916*FLEN/8, x10, x3, x5)

inst_995:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x039 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3f4 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x032 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3439; op2val:0xbbf4;
op3val:0x3432; valaddr_reg:x8; val_offset:2919*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2919*FLEN/8, x10, x3, x5)

inst_996:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x039 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3f4 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x032 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3439; op2val:0xbbf4;
op3val:0x3432; valaddr_reg:x8; val_offset:2922*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2922*FLEN/8, x10, x3, x5)

inst_997:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x039 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3f4 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x032 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3439; op2val:0xbbf4;
op3val:0x3432; valaddr_reg:x8; val_offset:2925*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2925*FLEN/8, x10, x3, x5)

inst_998:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x039 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3f4 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x032 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3439; op2val:0xbbf4;
op3val:0x3432; valaddr_reg:x8; val_offset:2928*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2928*FLEN/8, x10, x3, x5)

inst_999:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x039 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3f4 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x032 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3439; op2val:0xbbf4;
op3val:0x3432; valaddr_reg:x8; val_offset:2931*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2931*FLEN/8, x10, x3, x5)

inst_1000:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2c7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1c0 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36c9; op2val:0xbac7;
op3val:0x35c0; valaddr_reg:x8; val_offset:2934*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2934*FLEN/8, x10, x3, x5)

inst_1001:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2c7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1c0 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36c9; op2val:0xbac7;
op3val:0x35c0; valaddr_reg:x8; val_offset:2937*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2937*FLEN/8, x10, x3, x5)

inst_1002:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2c7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1c0 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36c9; op2val:0xbac7;
op3val:0x35c0; valaddr_reg:x8; val_offset:2940*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2940*FLEN/8, x10, x3, x5)

inst_1003:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2c7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1c0 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36c9; op2val:0xbac7;
op3val:0x35c0; valaddr_reg:x8; val_offset:2943*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2943*FLEN/8, x10, x3, x5)

inst_1004:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c9 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2c7 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1c0 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36c9; op2val:0xbac7;
op3val:0x35c0; valaddr_reg:x8; val_offset:2946*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2946*FLEN/8, x10, x3, x5)

inst_1005:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e9 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x211 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3be9; op2val:0xb211;
op3val:0x31ff; valaddr_reg:x8; val_offset:2949*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2949*FLEN/8, x10, x3, x5)

inst_1006:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e9 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x211 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1ff and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3be9; op2val:0xb211;
op3val:0x31ff; valaddr_reg:x8; val_offset:2952*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2952*FLEN/8, x10, x3, x5)

inst_1007:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e9 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x211 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1ff and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3be9; op2val:0xb211;
op3val:0x31ff; valaddr_reg:x8; val_offset:2955*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2955*FLEN/8, x10, x3, x5)

inst_1008:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e9 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x211 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1ff and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3be9; op2val:0xb211;
op3val:0x31ff; valaddr_reg:x8; val_offset:2958*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2958*FLEN/8, x10, x3, x5)

inst_1009:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3e9 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x211 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1ff and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3be9; op2val:0xb211;
op3val:0x31ff; valaddr_reg:x8; val_offset:2961*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2961*FLEN/8, x10, x3, x5)

inst_1010:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x15e and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2f0 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x0a7 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x395e; op2val:0xb2f0;
op3val:0x30a7; valaddr_reg:x8; val_offset:2964*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2964*FLEN/8, x10, x3, x5)

inst_1011:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x15e and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2f0 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x0a7 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x395e; op2val:0xb2f0;
op3val:0x30a7; valaddr_reg:x8; val_offset:2967*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2967*FLEN/8, x10, x3, x5)

inst_1012:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x15e and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2f0 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x0a7 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x395e; op2val:0xb2f0;
op3val:0x30a7; valaddr_reg:x8; val_offset:2970*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2970*FLEN/8, x10, x3, x5)

inst_1013:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x15e and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2f0 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x0a7 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x395e; op2val:0xb2f0;
op3val:0x30a7; valaddr_reg:x8; val_offset:2973*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2973*FLEN/8, x10, x3, x5)

inst_1014:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x15e and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2f0 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x0a7 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x395e; op2val:0xb2f0;
op3val:0x30a7; valaddr_reg:x8; val_offset:2976*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2976*FLEN/8, x10, x3, x5)

inst_1015:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0af and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0db and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1ae and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38af; op2val:0xb0db;
op3val:0x2dae; valaddr_reg:x8; val_offset:2979*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2979*FLEN/8, x10, x3, x5)

inst_1016:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0af and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0db and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1ae and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38af; op2val:0xb0db;
op3val:0x2dae; valaddr_reg:x8; val_offset:2982*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2982*FLEN/8, x10, x3, x5)

inst_1017:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0af and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0db and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1ae and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38af; op2val:0xb0db;
op3val:0x2dae; valaddr_reg:x8; val_offset:2985*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 2985*FLEN/8, x10, x3, x5)

inst_1018:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0af and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0db and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1ae and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38af; op2val:0xb0db;
op3val:0x2dae; valaddr_reg:x8; val_offset:2988*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 2988*FLEN/8, x10, x3, x5)

inst_1019:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0af and fs2 == 1 and fe2 == 0x0c and fm2 == 0x0db and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1ae and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38af; op2val:0xb0db;
op3val:0x2dae; valaddr_reg:x8; val_offset:2991*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 2991*FLEN/8, x10, x3, x5)

inst_1020:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x09 and fm2 == 0x10d and fs3 == 0 and fe3 == 0x09 and fm3 == 0x108 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bff; op2val:0xa50d;
op3val:0x2508; valaddr_reg:x8; val_offset:2994*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 2994*FLEN/8, x10, x3, x5)

inst_1021:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x09 and fm2 == 0x10d and fs3 == 0 and fe3 == 0x09 and fm3 == 0x108 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bff; op2val:0xa50d;
op3val:0x2508; valaddr_reg:x8; val_offset:2997*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 2997*FLEN/8, x10, x3, x5)

inst_1022:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x09 and fm2 == 0x10d and fs3 == 0 and fe3 == 0x09 and fm3 == 0x108 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bff; op2val:0xa50d;
op3val:0x2508; valaddr_reg:x8; val_offset:3000*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3000*FLEN/8, x10, x3, x5)

inst_1023:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x09 and fm2 == 0x10d and fs3 == 0 and fe3 == 0x09 and fm3 == 0x108 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bff; op2val:0xa50d;
op3val:0x2508; valaddr_reg:x8; val_offset:3003*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3003*FLEN/8, x10, x3, x5)

inst_1024:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x09 and fm2 == 0x10d and fs3 == 0 and fe3 == 0x09 and fm3 == 0x108 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bff; op2val:0xa50d;
op3val:0x2508; valaddr_reg:x8; val_offset:3006*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3006*FLEN/8, x10, x3, x5)

inst_1025:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x33b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x053 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3d3 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b3b; op2val:0xb853;
op3val:0x37d3; valaddr_reg:x8; val_offset:3009*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3009*FLEN/8, x10, x3, x5)

inst_1026:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x33b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x053 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3d3 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b3b; op2val:0xb853;
op3val:0x37d3; valaddr_reg:x8; val_offset:3012*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3012*FLEN/8, x10, x3, x5)

inst_1027:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x33b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x053 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3d3 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b3b; op2val:0xb853;
op3val:0x37d3; valaddr_reg:x8; val_offset:3015*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3015*FLEN/8, x10, x3, x5)

inst_1028:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x33b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x053 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3d3 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b3b; op2val:0xb853;
op3val:0x37d3; valaddr_reg:x8; val_offset:3018*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3018*FLEN/8, x10, x3, x5)

inst_1029:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x33b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x053 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3d3 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b3b; op2val:0xb853;
op3val:0x37d3; valaddr_reg:x8; val_offset:3021*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3021*FLEN/8, x10, x3, x5)

inst_1030:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x025 and fs2 == 1 and fe2 == 0x09 and fm2 == 0x2d2 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x30a and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3825; op2val:0xa6d2;
op3val:0x230a; valaddr_reg:x8; val_offset:3024*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3024*FLEN/8, x10, x3, x5)

inst_1031:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x025 and fs2 == 1 and fe2 == 0x09 and fm2 == 0x2d2 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x30a and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3825; op2val:0xa6d2;
op3val:0x230a; valaddr_reg:x8; val_offset:3027*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3027*FLEN/8, x10, x3, x5)

inst_1032:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x025 and fs2 == 1 and fe2 == 0x09 and fm2 == 0x2d2 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x30a and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3825; op2val:0xa6d2;
op3val:0x230a; valaddr_reg:x8; val_offset:3030*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3030*FLEN/8, x10, x3, x5)

inst_1033:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x025 and fs2 == 1 and fe2 == 0x09 and fm2 == 0x2d2 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x30a and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3825; op2val:0xa6d2;
op3val:0x230a; valaddr_reg:x8; val_offset:3033*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3033*FLEN/8, x10, x3, x5)

inst_1034:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x025 and fs2 == 1 and fe2 == 0x09 and fm2 == 0x2d2 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x30a and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3825; op2val:0xa6d2;
op3val:0x230a; valaddr_reg:x8; val_offset:3036*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3036*FLEN/8, x10, x3, x5)

inst_1035:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x088 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x01e and fs3 == 0 and fe3 == 0x09 and fm3 == 0x0a6 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3488; op2val:0xac1e;
op3val:0x24a6; valaddr_reg:x8; val_offset:3039*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3039*FLEN/8, x10, x3, x5)

inst_1036:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x088 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x01e and fs3 == 0 and fe3 == 0x09 and fm3 == 0x0a6 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3488; op2val:0xac1e;
op3val:0x24a6; valaddr_reg:x8; val_offset:3042*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3042*FLEN/8, x10, x3, x5)

inst_1037:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x088 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x01e and fs3 == 0 and fe3 == 0x09 and fm3 == 0x0a6 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3488; op2val:0xac1e;
op3val:0x24a6; valaddr_reg:x8; val_offset:3045*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3045*FLEN/8, x10, x3, x5)

inst_1038:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x088 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x01e and fs3 == 0 and fe3 == 0x09 and fm3 == 0x0a6 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3488; op2val:0xac1e;
op3val:0x24a6; valaddr_reg:x8; val_offset:3048*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3048*FLEN/8, x10, x3, x5)

inst_1039:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x088 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x01e and fs3 == 0 and fe3 == 0x09 and fm3 == 0x0a6 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3488; op2val:0xac1e;
op3val:0x24a6; valaddr_reg:x8; val_offset:3051*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3051*FLEN/8, x10, x3, x5)

inst_1040:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x209 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x218 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x099 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e09; op2val:0xc618;
op3val:0x3899; valaddr_reg:x8; val_offset:3054*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3054*FLEN/8, x10, x3, x5)

inst_1041:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x209 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x218 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x099 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e09; op2val:0xc618;
op3val:0x3899; valaddr_reg:x8; val_offset:3057*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3057*FLEN/8, x10, x3, x5)

inst_1042:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x209 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x218 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x099 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e09; op2val:0xc618;
op3val:0x3899; valaddr_reg:x8; val_offset:3060*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3060*FLEN/8, x10, x3, x5)

inst_1043:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x209 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x218 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x099 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e09; op2val:0xc618;
op3val:0x3899; valaddr_reg:x8; val_offset:3063*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3063*FLEN/8, x10, x3, x5)

inst_1044:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x209 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x218 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x099 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e09; op2val:0xc618;
op3val:0x3899; valaddr_reg:x8; val_offset:3066*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3066*FLEN/8, x10, x3, x5)

inst_1045:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x002 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2d5 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ad1; op2val:0xbc02;
op3val:0x3ad5; valaddr_reg:x8; val_offset:3069*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3069*FLEN/8, x10, x3, x5)

inst_1046:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x002 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2d5 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ad1; op2val:0xbc02;
op3val:0x3ad5; valaddr_reg:x8; val_offset:3072*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3072*FLEN/8, x10, x3, x5)

inst_1047:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x002 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2d5 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ad1; op2val:0xbc02;
op3val:0x3ad5; valaddr_reg:x8; val_offset:3075*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3075*FLEN/8, x10, x3, x5)
RVTEST_SIGBASE(x3,signature_x3_8)

inst_1048:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x002 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2d5 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ad1; op2val:0xbc02;
op3val:0x3ad5; valaddr_reg:x8; val_offset:3078*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3078*FLEN/8, x10, x3, x5)

inst_1049:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2d1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x002 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2d5 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ad1; op2val:0xbc02;
op3val:0x3ad5; valaddr_reg:x8; val_offset:3081*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3081*FLEN/8, x10, x3, x5)

inst_1050:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0a6 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x162 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x23f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34a6; op2val:0xb162;
op3val:0x2a3f; valaddr_reg:x8; val_offset:3084*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3084*FLEN/8, x10, x3, x5)

inst_1051:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0a6 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x162 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x23f and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34a6; op2val:0xb162;
op3val:0x2a3f; valaddr_reg:x8; val_offset:3087*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3087*FLEN/8, x10, x3, x5)

inst_1052:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0a6 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x162 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x23f and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34a6; op2val:0xb162;
op3val:0x2a3f; valaddr_reg:x8; val_offset:3090*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3090*FLEN/8, x10, x3, x5)

inst_1053:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0a6 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x162 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x23f and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34a6; op2val:0xb162;
op3val:0x2a3f; valaddr_reg:x8; val_offset:3093*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3093*FLEN/8, x10, x3, x5)

inst_1054:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0a6 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x162 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x23f and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34a6; op2val:0xb162;
op3val:0x2a3f; valaddr_reg:x8; val_offset:3096*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3096*FLEN/8, x10, x3, x5)

inst_1055:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x15c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3ce and fs3 == 0 and fe3 == 0x0e and fm3 == 0x13a and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x355c; op2val:0xbfce;
op3val:0x393a; valaddr_reg:x8; val_offset:3099*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3099*FLEN/8, x10, x3, x5)

inst_1056:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x15c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3ce and fs3 == 0 and fe3 == 0x0e and fm3 == 0x13a and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x355c; op2val:0xbfce;
op3val:0x393a; valaddr_reg:x8; val_offset:3102*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3102*FLEN/8, x10, x3, x5)

inst_1057:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x15c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3ce and fs3 == 0 and fe3 == 0x0e and fm3 == 0x13a and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x355c; op2val:0xbfce;
op3val:0x393a; valaddr_reg:x8; val_offset:3105*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3105*FLEN/8, x10, x3, x5)

inst_1058:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x15c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3ce and fs3 == 0 and fe3 == 0x0e and fm3 == 0x13a and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x355c; op2val:0xbfce;
op3val:0x393a; valaddr_reg:x8; val_offset:3108*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3108*FLEN/8, x10, x3, x5)

inst_1059:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x15c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3ce and fs3 == 0 and fe3 == 0x0e and fm3 == 0x13a and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x355c; op2val:0xbfce;
op3val:0x393a; valaddr_reg:x8; val_offset:3111*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3111*FLEN/8, x10, x3, x5)

inst_1060:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x271 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2d1 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x17d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3671; op2val:0xbad1;
op3val:0x357d; valaddr_reg:x8; val_offset:3114*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3114*FLEN/8, x10, x3, x5)

inst_1061:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x271 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2d1 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x17d and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3671; op2val:0xbad1;
op3val:0x357d; valaddr_reg:x8; val_offset:3117*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3117*FLEN/8, x10, x3, x5)

inst_1062:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x271 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2d1 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x17d and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3671; op2val:0xbad1;
op3val:0x357d; valaddr_reg:x8; val_offset:3120*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3120*FLEN/8, x10, x3, x5)

inst_1063:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x271 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2d1 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x17d and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3671; op2val:0xbad1;
op3val:0x357d; valaddr_reg:x8; val_offset:3123*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3123*FLEN/8, x10, x3, x5)

inst_1064:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x271 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2d1 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x17d and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3671; op2val:0xbad1;
op3val:0x357d; valaddr_reg:x8; val_offset:3126*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3126*FLEN/8, x10, x3, x5)

inst_1065:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x28e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0e5 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39f9; op2val:0xb68e;
op3val:0x34e5; valaddr_reg:x8; val_offset:3129*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3129*FLEN/8, x10, x3, x5)

inst_1066:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x28e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0e5 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39f9; op2val:0xb68e;
op3val:0x34e5; valaddr_reg:x8; val_offset:3132*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3132*FLEN/8, x10, x3, x5)

inst_1067:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x28e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0e5 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39f9; op2val:0xb68e;
op3val:0x34e5; valaddr_reg:x8; val_offset:3135*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3135*FLEN/8, x10, x3, x5)

inst_1068:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x28e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0e5 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39f9; op2val:0xb68e;
op3val:0x34e5; valaddr_reg:x8; val_offset:3138*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3138*FLEN/8, x10, x3, x5)

inst_1069:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x28e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0e5 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39f9; op2val:0xb68e;
op3val:0x34e5; valaddr_reg:x8; val_offset:3141*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3141*FLEN/8, x10, x3, x5)

inst_1070:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x268 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3c7 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a68; op2val:0xbcdb;
op3val:0x3bc7; valaddr_reg:x8; val_offset:3144*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3144*FLEN/8, x10, x3, x5)

inst_1071:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x268 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3c7 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a68; op2val:0xbcdb;
op3val:0x3bc7; valaddr_reg:x8; val_offset:3147*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3147*FLEN/8, x10, x3, x5)

inst_1072:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x268 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3c7 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a68; op2val:0xbcdb;
op3val:0x3bc7; valaddr_reg:x8; val_offset:3150*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3150*FLEN/8, x10, x3, x5)

inst_1073:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x268 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3c7 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a68; op2val:0xbcdb;
op3val:0x3bc7; valaddr_reg:x8; val_offset:3153*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3153*FLEN/8, x10, x3, x5)

inst_1074:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x268 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0db and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3c7 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a68; op2val:0xbcdb;
op3val:0x3bc7; valaddr_reg:x8; val_offset:3156*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3156*FLEN/8, x10, x3, x5)

inst_1075:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x37c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x060 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x018 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b7c; op2val:0xb860;
op3val:0x3818; valaddr_reg:x8; val_offset:3159*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3159*FLEN/8, x10, x3, x5)

inst_1076:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x37c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x060 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x018 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b7c; op2val:0xb860;
op3val:0x3818; valaddr_reg:x8; val_offset:3162*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3162*FLEN/8, x10, x3, x5)

inst_1077:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x37c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x060 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x018 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b7c; op2val:0xb860;
op3val:0x3818; valaddr_reg:x8; val_offset:3165*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3165*FLEN/8, x10, x3, x5)

inst_1078:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x37c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x060 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x018 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b7c; op2val:0xb860;
op3val:0x3818; valaddr_reg:x8; val_offset:3168*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3168*FLEN/8, x10, x3, x5)

inst_1079:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x37c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x060 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x018 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b7c; op2val:0xb860;
op3val:0x3818; valaddr_reg:x8; val_offset:3171*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3171*FLEN/8, x10, x3, x5)

inst_1080:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0dd and fs2 == 1 and fe2 == 0x10 and fm2 == 0x118 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x232 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34dd; op2val:0xc118;
op3val:0x3a32; valaddr_reg:x8; val_offset:3174*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3174*FLEN/8, x10, x3, x5)

inst_1081:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0dd and fs2 == 1 and fe2 == 0x10 and fm2 == 0x118 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x232 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34dd; op2val:0xc118;
op3val:0x3a32; valaddr_reg:x8; val_offset:3177*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3177*FLEN/8, x10, x3, x5)

inst_1082:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0dd and fs2 == 1 and fe2 == 0x10 and fm2 == 0x118 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x232 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34dd; op2val:0xc118;
op3val:0x3a32; valaddr_reg:x8; val_offset:3180*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3180*FLEN/8, x10, x3, x5)

inst_1083:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0dd and fs2 == 1 and fe2 == 0x10 and fm2 == 0x118 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x232 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34dd; op2val:0xc118;
op3val:0x3a32; valaddr_reg:x8; val_offset:3183*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3183*FLEN/8, x10, x3, x5)

inst_1084:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0dd and fs2 == 1 and fe2 == 0x10 and fm2 == 0x118 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x232 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34dd; op2val:0xc118;
op3val:0x3a32; valaddr_reg:x8; val_offset:3186*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3186*FLEN/8, x10, x3, x5)

inst_1085:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x012 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0e9 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d3; op2val:0xb812;
op3val:0x34e9; valaddr_reg:x8; val_offset:3189*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3189*FLEN/8, x10, x3, x5)

inst_1086:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x012 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0e9 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d3; op2val:0xb812;
op3val:0x34e9; valaddr_reg:x8; val_offset:3192*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3192*FLEN/8, x10, x3, x5)

inst_1087:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x012 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0e9 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d3; op2val:0xb812;
op3val:0x34e9; valaddr_reg:x8; val_offset:3195*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3195*FLEN/8, x10, x3, x5)

inst_1088:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x012 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0e9 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d3; op2val:0xb812;
op3val:0x34e9; valaddr_reg:x8; val_offset:3198*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3198*FLEN/8, x10, x3, x5)

inst_1089:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0d3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x012 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0e9 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38d3; op2val:0xb812;
op3val:0x34e9; valaddr_reg:x8; val_offset:3201*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3201*FLEN/8, x10, x3, x5)

inst_1090:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x12f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3a4 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39e5; op2val:0xb92f;
op3val:0x37a4; valaddr_reg:x8; val_offset:3204*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3204*FLEN/8, x10, x3, x5)

inst_1091:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x12f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3a4 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39e5; op2val:0xb92f;
op3val:0x37a4; valaddr_reg:x8; val_offset:3207*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3207*FLEN/8, x10, x3, x5)

inst_1092:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x12f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3a4 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39e5; op2val:0xb92f;
op3val:0x37a4; valaddr_reg:x8; val_offset:3210*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3210*FLEN/8, x10, x3, x5)

inst_1093:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x12f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3a4 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39e5; op2val:0xb92f;
op3val:0x37a4; valaddr_reg:x8; val_offset:3213*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3213*FLEN/8, x10, x3, x5)

inst_1094:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1e5 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x12f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3a4 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39e5; op2val:0xb92f;
op3val:0x37a4; valaddr_reg:x8; val_offset:3216*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3216*FLEN/8, x10, x3, x5)

inst_1095:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x25a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1fb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0c0 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x365a; op2val:0xbdfb;
op3val:0x38c0; valaddr_reg:x8; val_offset:3219*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3219*FLEN/8, x10, x3, x5)

inst_1096:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x25a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1fb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0c0 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x365a; op2val:0xbdfb;
op3val:0x38c0; valaddr_reg:x8; val_offset:3222*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3222*FLEN/8, x10, x3, x5)

inst_1097:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x25a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1fb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0c0 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x365a; op2val:0xbdfb;
op3val:0x38c0; valaddr_reg:x8; val_offset:3225*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3225*FLEN/8, x10, x3, x5)

inst_1098:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x25a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1fb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0c0 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x365a; op2val:0xbdfb;
op3val:0x38c0; valaddr_reg:x8; val_offset:3228*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3228*FLEN/8, x10, x3, x5)

inst_1099:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x25a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1fb and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0c0 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x365a; op2val:0xbdfb;
op3val:0x38c0; valaddr_reg:x8; val_offset:3231*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3231*FLEN/8, x10, x3, x5)

inst_1100:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x236 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0ea and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a55; op2val:0xb636;
op3val:0x34ea; valaddr_reg:x8; val_offset:3234*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3234*FLEN/8, x10, x3, x5)

inst_1101:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x236 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0ea and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a55; op2val:0xb636;
op3val:0x34ea; valaddr_reg:x8; val_offset:3237*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3237*FLEN/8, x10, x3, x5)

inst_1102:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x236 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0ea and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a55; op2val:0xb636;
op3val:0x34ea; valaddr_reg:x8; val_offset:3240*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3240*FLEN/8, x10, x3, x5)

inst_1103:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x236 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0ea and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a55; op2val:0xb636;
op3val:0x34ea; valaddr_reg:x8; val_offset:3243*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3243*FLEN/8, x10, x3, x5)

inst_1104:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x255 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x236 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0ea and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a55; op2val:0xb636;
op3val:0x34ea; valaddr_reg:x8; val_offset:3246*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3246*FLEN/8, x10, x3, x5)

inst_1105:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c8 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x16c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x27d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34c8; op2val:0xc16c;
op3val:0x3a7d; valaddr_reg:x8; val_offset:3249*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3249*FLEN/8, x10, x3, x5)

inst_1106:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c8 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x16c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x27d and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34c8; op2val:0xc16c;
op3val:0x3a7d; valaddr_reg:x8; val_offset:3252*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3252*FLEN/8, x10, x3, x5)

inst_1107:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c8 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x16c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x27d and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34c8; op2val:0xc16c;
op3val:0x3a7d; valaddr_reg:x8; val_offset:3255*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3255*FLEN/8, x10, x3, x5)

inst_1108:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c8 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x16c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x27d and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34c8; op2val:0xc16c;
op3val:0x3a7d; valaddr_reg:x8; val_offset:3258*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3258*FLEN/8, x10, x3, x5)

inst_1109:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c8 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x16c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x27d and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34c8; op2val:0xc16c;
op3val:0x3a7d; valaddr_reg:x8; val_offset:3261*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3261*FLEN/8, x10, x3, x5)

inst_1110:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x22a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x328 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x184 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x322a; op2val:0xbf28;
op3val:0x3584; valaddr_reg:x8; val_offset:3264*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3264*FLEN/8, x10, x3, x5)

inst_1111:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x22a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x328 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x184 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x322a; op2val:0xbf28;
op3val:0x3584; valaddr_reg:x8; val_offset:3267*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3267*FLEN/8, x10, x3, x5)

inst_1112:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x22a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x328 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x184 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x322a; op2val:0xbf28;
op3val:0x3584; valaddr_reg:x8; val_offset:3270*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3270*FLEN/8, x10, x3, x5)

inst_1113:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x22a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x328 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x184 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x322a; op2val:0xbf28;
op3val:0x3584; valaddr_reg:x8; val_offset:3273*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3273*FLEN/8, x10, x3, x5)

inst_1114:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x22a and fs2 == 1 and fe2 == 0x0f and fm2 == 0x328 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x184 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x322a; op2val:0xbf28;
op3val:0x3584; valaddr_reg:x8; val_offset:3276*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3276*FLEN/8, x10, x3, x5)

inst_1115:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x046 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x295 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x309 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3046; op2val:0xbe95;
op3val:0x3309; valaddr_reg:x8; val_offset:3279*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3279*FLEN/8, x10, x3, x5)

inst_1116:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x046 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x295 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x309 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3046; op2val:0xbe95;
op3val:0x3309; valaddr_reg:x8; val_offset:3282*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3282*FLEN/8, x10, x3, x5)

inst_1117:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x046 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x295 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x309 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3046; op2val:0xbe95;
op3val:0x3309; valaddr_reg:x8; val_offset:3285*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3285*FLEN/8, x10, x3, x5)

inst_1118:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x046 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x295 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x309 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3046; op2val:0xbe95;
op3val:0x3309; valaddr_reg:x8; val_offset:3288*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3288*FLEN/8, x10, x3, x5)

inst_1119:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x046 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x295 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x309 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3046; op2val:0xbe95;
op3val:0x3309; valaddr_reg:x8; val_offset:3291*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3291*FLEN/8, x10, x3, x5)

inst_1120:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x07f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x08c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x380b; op2val:0xb87f;
op3val:0x348c; valaddr_reg:x8; val_offset:3294*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3294*FLEN/8, x10, x3, x5)

inst_1121:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x07f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x08c and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x380b; op2val:0xb87f;
op3val:0x348c; valaddr_reg:x8; val_offset:3297*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3297*FLEN/8, x10, x3, x5)

inst_1122:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x07f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x08c and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x380b; op2val:0xb87f;
op3val:0x348c; valaddr_reg:x8; val_offset:3300*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3300*FLEN/8, x10, x3, x5)

inst_1123:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x07f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x08c and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x380b; op2val:0xb87f;
op3val:0x348c; valaddr_reg:x8; val_offset:3303*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3303*FLEN/8, x10, x3, x5)

inst_1124:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x00b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x07f and fs3 == 0 and fe3 == 0x0d and fm3 == 0x08c and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x380b; op2val:0xb87f;
op3val:0x348c; valaddr_reg:x8; val_offset:3306*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3306*FLEN/8, x10, x3, x5)

inst_1125:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x17b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x00b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x18b and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x397b; op2val:0xb80b;
op3val:0x358b; valaddr_reg:x8; val_offset:3309*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3309*FLEN/8, x10, x3, x5)

inst_1126:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x17b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x00b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x18b and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x397b; op2val:0xb80b;
op3val:0x358b; valaddr_reg:x8; val_offset:3312*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3312*FLEN/8, x10, x3, x5)

inst_1127:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x17b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x00b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x18b and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x397b; op2val:0xb80b;
op3val:0x358b; valaddr_reg:x8; val_offset:3315*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3315*FLEN/8, x10, x3, x5)

inst_1128:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x17b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x00b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x18b and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x397b; op2val:0xb80b;
op3val:0x358b; valaddr_reg:x8; val_offset:3318*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3318*FLEN/8, x10, x3, x5)

inst_1129:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x17b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x00b and fs3 == 0 and fe3 == 0x0d and fm3 == 0x18b and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x397b; op2val:0xb80b;
op3val:0x358b; valaddr_reg:x8; val_offset:3321*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3321*FLEN/8, x10, x3, x5)

inst_1130:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x357 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x13b and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b57; op2val:0xb9b4;
op3val:0x393b; valaddr_reg:x8; val_offset:3324*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3324*FLEN/8, x10, x3, x5)

inst_1131:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x357 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x13b and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b57; op2val:0xb9b4;
op3val:0x393b; valaddr_reg:x8; val_offset:3327*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3327*FLEN/8, x10, x3, x5)

inst_1132:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x357 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x13b and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b57; op2val:0xb9b4;
op3val:0x393b; valaddr_reg:x8; val_offset:3330*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3330*FLEN/8, x10, x3, x5)

inst_1133:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x357 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x13b and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b57; op2val:0xb9b4;
op3val:0x393b; valaddr_reg:x8; val_offset:3333*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3333*FLEN/8, x10, x3, x5)

inst_1134:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x357 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1b4 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x13b and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b57; op2val:0xb9b4;
op3val:0x393b; valaddr_reg:x8; val_offset:3336*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3336*FLEN/8, x10, x3, x5)

inst_1135:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e7 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x36b and fs3 == 0 and fe3 == 0x0b and fm3 == 0x353 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37e7; op2val:0xb36b;
op3val:0x2f53; valaddr_reg:x8; val_offset:3339*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3339*FLEN/8, x10, x3, x5)

inst_1136:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e7 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x36b and fs3 == 0 and fe3 == 0x0b and fm3 == 0x353 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37e7; op2val:0xb36b;
op3val:0x2f53; valaddr_reg:x8; val_offset:3342*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3342*FLEN/8, x10, x3, x5)

inst_1137:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e7 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x36b and fs3 == 0 and fe3 == 0x0b and fm3 == 0x353 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37e7; op2val:0xb36b;
op3val:0x2f53; valaddr_reg:x8; val_offset:3345*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3345*FLEN/8, x10, x3, x5)

inst_1138:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e7 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x36b and fs3 == 0 and fe3 == 0x0b and fm3 == 0x353 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37e7; op2val:0xb36b;
op3val:0x2f53; valaddr_reg:x8; val_offset:3348*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3348*FLEN/8, x10, x3, x5)

inst_1139:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3e7 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x36b and fs3 == 0 and fe3 == 0x0b and fm3 == 0x353 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37e7; op2val:0xb36b;
op3val:0x2f53; valaddr_reg:x8; val_offset:3351*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3351*FLEN/8, x10, x3, x5)

inst_1140:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x10f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x09c and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1d3 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x350f; op2val:0xb49c;
op3val:0x2dd3; valaddr_reg:x8; val_offset:3354*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3354*FLEN/8, x10, x3, x5)

inst_1141:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x10f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x09c and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1d3 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x350f; op2val:0xb49c;
op3val:0x2dd3; valaddr_reg:x8; val_offset:3357*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3357*FLEN/8, x10, x3, x5)

inst_1142:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x10f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x09c and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1d3 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x350f; op2val:0xb49c;
op3val:0x2dd3; valaddr_reg:x8; val_offset:3360*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3360*FLEN/8, x10, x3, x5)

inst_1143:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x10f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x09c and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1d3 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x350f; op2val:0xb49c;
op3val:0x2dd3; valaddr_reg:x8; val_offset:3363*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3363*FLEN/8, x10, x3, x5)

inst_1144:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x10f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x09c and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1d3 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x350f; op2val:0xb49c;
op3val:0x2dd3; valaddr_reg:x8; val_offset:3366*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3366*FLEN/8, x10, x3, x5)

inst_1145:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x02f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x332 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x382 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x302f; op2val:0xb332;
op3val:0x2782; valaddr_reg:x8; val_offset:3369*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3369*FLEN/8, x10, x3, x5)

inst_1146:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x02f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x332 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x382 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x302f; op2val:0xb332;
op3val:0x2782; valaddr_reg:x8; val_offset:3372*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3372*FLEN/8, x10, x3, x5)

inst_1147:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x02f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x332 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x382 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x302f; op2val:0xb332;
op3val:0x2782; valaddr_reg:x8; val_offset:3375*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3375*FLEN/8, x10, x3, x5)

inst_1148:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x02f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x332 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x382 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x302f; op2val:0xb332;
op3val:0x2782; valaddr_reg:x8; val_offset:3378*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3378*FLEN/8, x10, x3, x5)

inst_1149:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x02f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x332 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x382 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x302f; op2val:0xb332;
op3val:0x2782; valaddr_reg:x8; val_offset:3381*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3381*FLEN/8, x10, x3, x5)

inst_1150:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x21e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x002 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x221 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x361e; op2val:0xbc02;
op3val:0x3621; valaddr_reg:x8; val_offset:3384*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3384*FLEN/8, x10, x3, x5)

inst_1151:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x21e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x002 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x221 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x361e; op2val:0xbc02;
op3val:0x3621; valaddr_reg:x8; val_offset:3387*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3387*FLEN/8, x10, x3, x5)

inst_1152:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x21e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x002 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x221 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x361e; op2val:0xbc02;
op3val:0x3621; valaddr_reg:x8; val_offset:3390*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3390*FLEN/8, x10, x3, x5)

inst_1153:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x21e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x002 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x221 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x361e; op2val:0xbc02;
op3val:0x3621; valaddr_reg:x8; val_offset:3393*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3393*FLEN/8, x10, x3, x5)

inst_1154:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x21e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x002 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x221 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x361e; op2val:0xbc02;
op3val:0x3621; valaddr_reg:x8; val_offset:3396*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3396*FLEN/8, x10, x3, x5)

inst_1155:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x03f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x23b and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x383f; op2val:0xbddd;
op3val:0x3a3b; valaddr_reg:x8; val_offset:3399*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3399*FLEN/8, x10, x3, x5)

inst_1156:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x03f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x23b and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x383f; op2val:0xbddd;
op3val:0x3a3b; valaddr_reg:x8; val_offset:3402*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3402*FLEN/8, x10, x3, x5)

inst_1157:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x03f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x23b and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x383f; op2val:0xbddd;
op3val:0x3a3b; valaddr_reg:x8; val_offset:3405*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3405*FLEN/8, x10, x3, x5)

inst_1158:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x03f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x23b and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x383f; op2val:0xbddd;
op3val:0x3a3b; valaddr_reg:x8; val_offset:3408*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3408*FLEN/8, x10, x3, x5)

inst_1159:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x03f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1dd and fs3 == 0 and fe3 == 0x0e and fm3 == 0x23b and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x383f; op2val:0xbddd;
op3val:0x3a3b; valaddr_reg:x8; val_offset:3411*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3411*FLEN/8, x10, x3, x5)

inst_1160:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x282 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3a9 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x23c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3282; op2val:0xbfa9;
op3val:0x363c; valaddr_reg:x8; val_offset:3414*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3414*FLEN/8, x10, x3, x5)

inst_1161:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x282 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3a9 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x23c and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3282; op2val:0xbfa9;
op3val:0x363c; valaddr_reg:x8; val_offset:3417*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3417*FLEN/8, x10, x3, x5)

inst_1162:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x282 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3a9 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x23c and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3282; op2val:0xbfa9;
op3val:0x363c; valaddr_reg:x8; val_offset:3420*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3420*FLEN/8, x10, x3, x5)

inst_1163:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x282 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3a9 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x23c and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3282; op2val:0xbfa9;
op3val:0x363c; valaddr_reg:x8; val_offset:3423*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3423*FLEN/8, x10, x3, x5)

inst_1164:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x282 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3a9 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x23c and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3282; op2val:0xbfa9;
op3val:0x363c; valaddr_reg:x8; val_offset:3426*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3426*FLEN/8, x10, x3, x5)

inst_1165:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x341 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x214 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ab4; op2val:0xbb41;
op3val:0x3a14; valaddr_reg:x8; val_offset:3429*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3429*FLEN/8, x10, x3, x5)

inst_1166:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x341 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x214 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ab4; op2val:0xbb41;
op3val:0x3a14; valaddr_reg:x8; val_offset:3432*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3432*FLEN/8, x10, x3, x5)

inst_1167:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x341 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x214 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ab4; op2val:0xbb41;
op3val:0x3a14; valaddr_reg:x8; val_offset:3435*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3435*FLEN/8, x10, x3, x5)

inst_1168:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x341 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x214 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ab4; op2val:0xbb41;
op3val:0x3a14; valaddr_reg:x8; val_offset:3438*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3438*FLEN/8, x10, x3, x5)

inst_1169:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2b4 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x341 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x214 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3ab4; op2val:0xbb41;
op3val:0x3a14; valaddr_reg:x8; val_offset:3441*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3441*FLEN/8, x10, x3, x5)

inst_1170:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1b2 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x070 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a3b; op2val:0xb5b2;
op3val:0x3470; valaddr_reg:x8; val_offset:3444*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3444*FLEN/8, x10, x3, x5)

inst_1171:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1b2 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x070 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a3b; op2val:0xb5b2;
op3val:0x3470; valaddr_reg:x8; val_offset:3447*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3447*FLEN/8, x10, x3, x5)

inst_1172:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1b2 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x070 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a3b; op2val:0xb5b2;
op3val:0x3470; valaddr_reg:x8; val_offset:3450*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3450*FLEN/8, x10, x3, x5)

inst_1173:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1b2 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x070 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a3b; op2val:0xb5b2;
op3val:0x3470; valaddr_reg:x8; val_offset:3453*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3453*FLEN/8, x10, x3, x5)

inst_1174:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x23b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x1b2 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x070 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a3b; op2val:0xb5b2;
op3val:0x3470; valaddr_reg:x8; val_offset:3456*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3456*FLEN/8, x10, x3, x5)

inst_1175:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x271 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3f0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x264 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3671; op2val:0xbff0;
op3val:0x3a64; valaddr_reg:x8; val_offset:3459*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3459*FLEN/8, x10, x3, x5)
RVTEST_SIGBASE(x3,signature_x3_9)

inst_1176:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x271 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3f0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x264 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3671; op2val:0xbff0;
op3val:0x3a64; valaddr_reg:x8; val_offset:3462*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3462*FLEN/8, x10, x3, x5)

inst_1177:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x271 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3f0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x264 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3671; op2val:0xbff0;
op3val:0x3a64; valaddr_reg:x8; val_offset:3465*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3465*FLEN/8, x10, x3, x5)

inst_1178:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x271 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3f0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x264 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3671; op2val:0xbff0;
op3val:0x3a64; valaddr_reg:x8; val_offset:3468*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3468*FLEN/8, x10, x3, x5)

inst_1179:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x271 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x3f0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x264 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3671; op2val:0xbff0;
op3val:0x3a64; valaddr_reg:x8; val_offset:3471*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3471*FLEN/8, x10, x3, x5)

inst_1180:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x197 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2fc and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ff; op2val:0xbd97;
op3val:0x36fc; valaddr_reg:x8; val_offset:3474*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3474*FLEN/8, x10, x3, x5)

inst_1181:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x197 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2fc and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ff; op2val:0xbd97;
op3val:0x36fc; valaddr_reg:x8; val_offset:3477*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3477*FLEN/8, x10, x3, x5)

inst_1182:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x197 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2fc and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ff; op2val:0xbd97;
op3val:0x36fc; valaddr_reg:x8; val_offset:3480*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3480*FLEN/8, x10, x3, x5)

inst_1183:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x197 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2fc and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ff; op2val:0xbd97;
op3val:0x36fc; valaddr_reg:x8; val_offset:3483*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3483*FLEN/8, x10, x3, x5)

inst_1184:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ff and fs2 == 1 and fe2 == 0x0f and fm2 == 0x197 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2fc and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ff; op2val:0xbd97;
op3val:0x36fc; valaddr_reg:x8; val_offset:3486*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3486*FLEN/8, x10, x3, x5)

inst_1185:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1de and fs2 == 1 and fe2 == 0x0e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x071 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39de; op2val:0xba0f;
op3val:0x3871; valaddr_reg:x8; val_offset:3489*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3489*FLEN/8, x10, x3, x5)

inst_1186:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1de and fs2 == 1 and fe2 == 0x0e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x071 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39de; op2val:0xba0f;
op3val:0x3871; valaddr_reg:x8; val_offset:3492*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3492*FLEN/8, x10, x3, x5)

inst_1187:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1de and fs2 == 1 and fe2 == 0x0e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x071 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39de; op2val:0xba0f;
op3val:0x3871; valaddr_reg:x8; val_offset:3495*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3495*FLEN/8, x10, x3, x5)

inst_1188:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1de and fs2 == 1 and fe2 == 0x0e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x071 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39de; op2val:0xba0f;
op3val:0x3871; valaddr_reg:x8; val_offset:3498*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3498*FLEN/8, x10, x3, x5)

inst_1189:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1de and fs2 == 1 and fe2 == 0x0e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x071 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39de; op2val:0xba0f;
op3val:0x3871; valaddr_reg:x8; val_offset:3501*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3501*FLEN/8, x10, x3, x5)

inst_1190:
// fs1 == 0 and fe1 == 0x07 and fm1 == 0x393 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x342 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2df and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1f93; op2val:0xd742;
op3val:0x3adf; valaddr_reg:x8; val_offset:3504*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3504*FLEN/8, x10, x3, x5)

inst_1191:
// fs1 == 0 and fe1 == 0x07 and fm1 == 0x393 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x342 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2df and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1f93; op2val:0xd742;
op3val:0x3adf; valaddr_reg:x8; val_offset:3507*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3507*FLEN/8, x10, x3, x5)

inst_1192:
// fs1 == 0 and fe1 == 0x07 and fm1 == 0x393 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x342 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2df and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1f93; op2val:0xd742;
op3val:0x3adf; valaddr_reg:x8; val_offset:3510*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3510*FLEN/8, x10, x3, x5)

inst_1193:
// fs1 == 0 and fe1 == 0x07 and fm1 == 0x393 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x342 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2df and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1f93; op2val:0xd742;
op3val:0x3adf; valaddr_reg:x8; val_offset:3513*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3513*FLEN/8, x10, x3, x5)

inst_1194:
// fs1 == 0 and fe1 == 0x07 and fm1 == 0x393 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x342 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2df and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x1f93; op2val:0xd742;
op3val:0x3adf; valaddr_reg:x8; val_offset:3516*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3516*FLEN/8, x10, x3, x5)

inst_1195:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x21b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x042 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x27f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a1b; op2val:0xb842;
op3val:0x367f; valaddr_reg:x8; val_offset:3519*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3519*FLEN/8, x10, x3, x5)

inst_1196:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x21b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x042 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x27f and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a1b; op2val:0xb842;
op3val:0x367f; valaddr_reg:x8; val_offset:3522*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3522*FLEN/8, x10, x3, x5)

inst_1197:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x21b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x042 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x27f and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a1b; op2val:0xb842;
op3val:0x367f; valaddr_reg:x8; val_offset:3525*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3525*FLEN/8, x10, x3, x5)

inst_1198:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x21b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x042 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x27f and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a1b; op2val:0xb842;
op3val:0x367f; valaddr_reg:x8; val_offset:3528*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3528*FLEN/8, x10, x3, x5)

inst_1199:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x21b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x042 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x27f and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a1b; op2val:0xb842;
op3val:0x367f; valaddr_reg:x8; val_offset:3531*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3531*FLEN/8, x10, x3, x5)

inst_1200:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x11f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3d6 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x103 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x311f; op2val:0xb7d6;
op3val:0x2d03; valaddr_reg:x8; val_offset:3534*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3534*FLEN/8, x10, x3, x5)

inst_1201:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x11f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3d6 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x103 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x311f; op2val:0xb7d6;
op3val:0x2d03; valaddr_reg:x8; val_offset:3537*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3537*FLEN/8, x10, x3, x5)

inst_1202:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x11f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3d6 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x103 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x311f; op2val:0xb7d6;
op3val:0x2d03; valaddr_reg:x8; val_offset:3540*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3540*FLEN/8, x10, x3, x5)

inst_1203:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x11f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3d6 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x103 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x311f; op2val:0xb7d6;
op3val:0x2d03; valaddr_reg:x8; val_offset:3543*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3543*FLEN/8, x10, x3, x5)

inst_1204:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x11f and fs2 == 1 and fe2 == 0x0d and fm2 == 0x3d6 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x103 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x311f; op2val:0xb7d6;
op3val:0x2d03; valaddr_reg:x8; val_offset:3546*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3546*FLEN/8, x10, x3, x5)

inst_1205:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ce and fs2 == 1 and fe2 == 0x0d and fm2 == 0x228 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x365 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ce; op2val:0xb628;
op3val:0x3365; valaddr_reg:x8; val_offset:3549*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3549*FLEN/8, x10, x3, x5)

inst_1206:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ce and fs2 == 1 and fe2 == 0x0d and fm2 == 0x228 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x365 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ce; op2val:0xb628;
op3val:0x3365; valaddr_reg:x8; val_offset:3552*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3552*FLEN/8, x10, x3, x5)

inst_1207:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ce and fs2 == 1 and fe2 == 0x0d and fm2 == 0x228 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x365 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ce; op2val:0xb628;
op3val:0x3365; valaddr_reg:x8; val_offset:3555*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3555*FLEN/8, x10, x3, x5)

inst_1208:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ce and fs2 == 1 and fe2 == 0x0d and fm2 == 0x228 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x365 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ce; op2val:0xb628;
op3val:0x3365; valaddr_reg:x8; val_offset:3558*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3558*FLEN/8, x10, x3, x5)

inst_1209:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0ce and fs2 == 1 and fe2 == 0x0d and fm2 == 0x228 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x365 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38ce; op2val:0xb628;
op3val:0x3365; valaddr_reg:x8; val_offset:3561*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3561*FLEN/8, x10, x3, x5)

inst_1210:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x30d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x192 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0e9 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b0d; op2val:0xb992;
op3val:0x38e9; valaddr_reg:x8; val_offset:3564*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3564*FLEN/8, x10, x3, x5)

inst_1211:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x30d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x192 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0e9 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b0d; op2val:0xb992;
op3val:0x38e9; valaddr_reg:x8; val_offset:3567*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3567*FLEN/8, x10, x3, x5)

inst_1212:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x30d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x192 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0e9 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b0d; op2val:0xb992;
op3val:0x38e9; valaddr_reg:x8; val_offset:3570*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3570*FLEN/8, x10, x3, x5)

inst_1213:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x30d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x192 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0e9 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b0d; op2val:0xb992;
op3val:0x38e9; valaddr_reg:x8; val_offset:3573*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3573*FLEN/8, x10, x3, x5)

inst_1214:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x30d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x192 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0e9 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b0d; op2val:0xb992;
op3val:0x38e9; valaddr_reg:x8; val_offset:3576*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3576*FLEN/8, x10, x3, x5)

inst_1215:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x094 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ae and fs3 == 0 and fe3 == 0x0d and fm3 == 0x15c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3094; op2val:0xc0ae;
op3val:0x355c; valaddr_reg:x8; val_offset:3579*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3579*FLEN/8, x10, x3, x5)

inst_1216:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x094 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ae and fs3 == 0 and fe3 == 0x0d and fm3 == 0x15c and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3094; op2val:0xc0ae;
op3val:0x355c; valaddr_reg:x8; val_offset:3582*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3582*FLEN/8, x10, x3, x5)

inst_1217:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x094 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ae and fs3 == 0 and fe3 == 0x0d and fm3 == 0x15c and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3094; op2val:0xc0ae;
op3val:0x355c; valaddr_reg:x8; val_offset:3585*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3585*FLEN/8, x10, x3, x5)

inst_1218:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x094 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ae and fs3 == 0 and fe3 == 0x0d and fm3 == 0x15c and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3094; op2val:0xc0ae;
op3val:0x355c; valaddr_reg:x8; val_offset:3588*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3588*FLEN/8, x10, x3, x5)

inst_1219:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x094 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ae and fs3 == 0 and fe3 == 0x0d and fm3 == 0x15c and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3094; op2val:0xc0ae;
op3val:0x355c; valaddr_reg:x8; val_offset:3591*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3591*FLEN/8, x10, x3, x5)

inst_1220:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1ce and fs3 == 0 and fe3 == 0x0d and fm3 == 0x26c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x386d; op2val:0xb9ce;
op3val:0x366c; valaddr_reg:x8; val_offset:3594*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3594*FLEN/8, x10, x3, x5)

inst_1221:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1ce and fs3 == 0 and fe3 == 0x0d and fm3 == 0x26c and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x386d; op2val:0xb9ce;
op3val:0x366c; valaddr_reg:x8; val_offset:3597*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3597*FLEN/8, x10, x3, x5)

inst_1222:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1ce and fs3 == 0 and fe3 == 0x0d and fm3 == 0x26c and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x386d; op2val:0xb9ce;
op3val:0x366c; valaddr_reg:x8; val_offset:3600*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3600*FLEN/8, x10, x3, x5)

inst_1223:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1ce and fs3 == 0 and fe3 == 0x0d and fm3 == 0x26c and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x386d; op2val:0xb9ce;
op3val:0x366c; valaddr_reg:x8; val_offset:3603*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3603*FLEN/8, x10, x3, x5)

inst_1224:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x06d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1ce and fs3 == 0 and fe3 == 0x0d and fm3 == 0x26c and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x386d; op2val:0xb9ce;
op3val:0x366c; valaddr_reg:x8; val_offset:3606*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3606*FLEN/8, x10, x3, x5)

inst_1225:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x019 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x30e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x33b and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3819; op2val:0xbb0e;
op3val:0x373b; valaddr_reg:x8; val_offset:3609*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3609*FLEN/8, x10, x3, x5)

inst_1226:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x019 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x30e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x33b and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3819; op2val:0xbb0e;
op3val:0x373b; valaddr_reg:x8; val_offset:3612*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3612*FLEN/8, x10, x3, x5)

inst_1227:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x019 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x30e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x33b and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3819; op2val:0xbb0e;
op3val:0x373b; valaddr_reg:x8; val_offset:3615*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3615*FLEN/8, x10, x3, x5)

inst_1228:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x019 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x30e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x33b and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3819; op2val:0xbb0e;
op3val:0x373b; valaddr_reg:x8; val_offset:3618*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3618*FLEN/8, x10, x3, x5)

inst_1229:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x019 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x30e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x33b and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3819; op2val:0xbb0e;
op3val:0x373b; valaddr_reg:x8; val_offset:3621*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3621*FLEN/8, x10, x3, x5)

inst_1230:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x36c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2c1 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x240 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f6c; op2val:0xb2c1;
op3val:0x2640; valaddr_reg:x8; val_offset:3624*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3624*FLEN/8, x10, x3, x5)

inst_1231:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x36c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2c1 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x240 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f6c; op2val:0xb2c1;
op3val:0x2640; valaddr_reg:x8; val_offset:3627*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3627*FLEN/8, x10, x3, x5)

inst_1232:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x36c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2c1 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x240 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f6c; op2val:0xb2c1;
op3val:0x2640; valaddr_reg:x8; val_offset:3630*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3630*FLEN/8, x10, x3, x5)

inst_1233:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x36c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2c1 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x240 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f6c; op2val:0xb2c1;
op3val:0x2640; valaddr_reg:x8; val_offset:3633*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3633*FLEN/8, x10, x3, x5)

inst_1234:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x36c and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2c1 and fs3 == 0 and fe3 == 0x09 and fm3 == 0x240 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f6c; op2val:0xb2c1;
op3val:0x2640; valaddr_reg:x8; val_offset:3636*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3636*FLEN/8, x10, x3, x5)

inst_1235:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x265 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0e7 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3d6 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a65; op2val:0xb4e7;
op3val:0x33d6; valaddr_reg:x8; val_offset:3639*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3639*FLEN/8, x10, x3, x5)

inst_1236:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x265 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0e7 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3d6 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a65; op2val:0xb4e7;
op3val:0x33d6; valaddr_reg:x8; val_offset:3642*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3642*FLEN/8, x10, x3, x5)

inst_1237:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x265 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0e7 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3d6 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a65; op2val:0xb4e7;
op3val:0x33d6; valaddr_reg:x8; val_offset:3645*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3645*FLEN/8, x10, x3, x5)

inst_1238:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x265 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0e7 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3d6 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a65; op2val:0xb4e7;
op3val:0x33d6; valaddr_reg:x8; val_offset:3648*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3648*FLEN/8, x10, x3, x5)

inst_1239:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x265 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0e7 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3d6 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a65; op2val:0xb4e7;
op3val:0x33d6; valaddr_reg:x8; val_offset:3651*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3651*FLEN/8, x10, x3, x5)

inst_1240:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x316 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x318 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x248 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2b16; op2val:0xc718;
op3val:0x3648; valaddr_reg:x8; val_offset:3654*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3654*FLEN/8, x10, x3, x5)

inst_1241:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x316 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x318 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x248 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2b16; op2val:0xc718;
op3val:0x3648; valaddr_reg:x8; val_offset:3657*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3657*FLEN/8, x10, x3, x5)

inst_1242:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x316 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x318 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x248 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2b16; op2val:0xc718;
op3val:0x3648; valaddr_reg:x8; val_offset:3660*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3660*FLEN/8, x10, x3, x5)

inst_1243:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x316 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x318 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x248 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2b16; op2val:0xc718;
op3val:0x3648; valaddr_reg:x8; val_offset:3663*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3663*FLEN/8, x10, x3, x5)

inst_1244:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x316 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x318 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x248 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2b16; op2val:0xc718;
op3val:0x3648; valaddr_reg:x8; val_offset:3666*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3666*FLEN/8, x10, x3, x5)

inst_1245:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x106 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x105 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37fe; op2val:0xbd06;
op3val:0x3905; valaddr_reg:x8; val_offset:3669*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3669*FLEN/8, x10, x3, x5)

inst_1246:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x106 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x105 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37fe; op2val:0xbd06;
op3val:0x3905; valaddr_reg:x8; val_offset:3672*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3672*FLEN/8, x10, x3, x5)

inst_1247:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x106 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x105 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37fe; op2val:0xbd06;
op3val:0x3905; valaddr_reg:x8; val_offset:3675*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3675*FLEN/8, x10, x3, x5)

inst_1248:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x106 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x105 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37fe; op2val:0xbd06;
op3val:0x3905; valaddr_reg:x8; val_offset:3678*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3678*FLEN/8, x10, x3, x5)

inst_1249:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x106 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x105 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37fe; op2val:0xbd06;
op3val:0x3905; valaddr_reg:x8; val_offset:3681*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3681*FLEN/8, x10, x3, x5)

inst_1250:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x020 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x280 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b5 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3820; op2val:0xba80;
op3val:0x36b5; valaddr_reg:x8; val_offset:3684*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3684*FLEN/8, x10, x3, x5)

inst_1251:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x020 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x280 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b5 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3820; op2val:0xba80;
op3val:0x36b5; valaddr_reg:x8; val_offset:3687*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3687*FLEN/8, x10, x3, x5)

inst_1252:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x020 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x280 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b5 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3820; op2val:0xba80;
op3val:0x36b5; valaddr_reg:x8; val_offset:3690*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3690*FLEN/8, x10, x3, x5)

inst_1253:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x020 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x280 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b5 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3820; op2val:0xba80;
op3val:0x36b5; valaddr_reg:x8; val_offset:3693*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3693*FLEN/8, x10, x3, x5)

inst_1254:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x020 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x280 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2b5 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3820; op2val:0xba80;
op3val:0x36b5; valaddr_reg:x8; val_offset:3696*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3696*FLEN/8, x10, x3, x5)

inst_1255:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x237 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x08f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x316 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3637; op2val:0xc08f;
op3val:0x3b16; valaddr_reg:x8; val_offset:3699*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3699*FLEN/8, x10, x3, x5)

inst_1256:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x237 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x08f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x316 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3637; op2val:0xc08f;
op3val:0x3b16; valaddr_reg:x8; val_offset:3702*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3702*FLEN/8, x10, x3, x5)

inst_1257:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x237 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x08f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x316 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3637; op2val:0xc08f;
op3val:0x3b16; valaddr_reg:x8; val_offset:3705*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3705*FLEN/8, x10, x3, x5)

inst_1258:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x237 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x08f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x316 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3637; op2val:0xc08f;
op3val:0x3b16; valaddr_reg:x8; val_offset:3708*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3708*FLEN/8, x10, x3, x5)

inst_1259:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x237 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x08f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x316 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3637; op2val:0xc08f;
op3val:0x3b16; valaddr_reg:x8; val_offset:3711*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3711*FLEN/8, x10, x3, x5)

inst_1260:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x0f and fm2 == 0x127 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x098 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x53fd; op2val:0xbd27;
op3val:0x4c98; valaddr_reg:x8; val_offset:3714*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3714*FLEN/8, x10, x3, x5)

inst_1261:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x0f and fm2 == 0x127 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x098 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x53fd; op2val:0xbd27;
op3val:0x4c98; valaddr_reg:x8; val_offset:3717*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3717*FLEN/8, x10, x3, x5)

inst_1262:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x0f and fm2 == 0x127 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x098 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x53fd; op2val:0xbd27;
op3val:0x4c98; valaddr_reg:x8; val_offset:3720*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3720*FLEN/8, x10, x3, x5)

inst_1263:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x0f and fm2 == 0x127 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x098 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x53fd; op2val:0xbd27;
op3val:0x4c98; valaddr_reg:x8; val_offset:3723*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3723*FLEN/8, x10, x3, x5)

inst_1264:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3fd and fs2 == 1 and fe2 == 0x0f and fm2 == 0x127 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x098 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x53fd; op2val:0xbd27;
op3val:0x4c98; valaddr_reg:x8; val_offset:3726*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3726*FLEN/8, x10, x3, x5)

inst_1265:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x06f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x05d and fs3 == 0 and fe3 == 0x12 and fm3 == 0x2bf and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x506f; op2val:0xc05d;
op3val:0x4abf; valaddr_reg:x8; val_offset:3729*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3729*FLEN/8, x10, x3, x5)

inst_1266:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x06f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x05d and fs3 == 0 and fe3 == 0x12 and fm3 == 0x2bf and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x506f; op2val:0xc05d;
op3val:0x4abf; valaddr_reg:x8; val_offset:3732*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3732*FLEN/8, x10, x3, x5)

inst_1267:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x06f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x05d and fs3 == 0 and fe3 == 0x12 and fm3 == 0x2bf and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x506f; op2val:0xc05d;
op3val:0x4abf; valaddr_reg:x8; val_offset:3735*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3735*FLEN/8, x10, x3, x5)

inst_1268:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x06f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x05d and fs3 == 0 and fe3 == 0x12 and fm3 == 0x2bf and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x506f; op2val:0xc05d;
op3val:0x4abf; valaddr_reg:x8; val_offset:3738*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3738*FLEN/8, x10, x3, x5)

inst_1269:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x06f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x05d and fs3 == 0 and fe3 == 0x12 and fm3 == 0x2bf and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x506f; op2val:0xc05d;
op3val:0x4abf; valaddr_reg:x8; val_offset:3741*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3741*FLEN/8, x10, x3, x5)

inst_1270:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x118 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2d6 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x1b3 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5118; op2val:0xbed6;
op3val:0x45b3; valaddr_reg:x8; val_offset:3744*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3744*FLEN/8, x10, x3, x5)

inst_1271:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x118 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2d6 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x1b3 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5118; op2val:0xbed6;
op3val:0x45b3; valaddr_reg:x8; val_offset:3747*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3747*FLEN/8, x10, x3, x5)

inst_1272:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x118 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2d6 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x1b3 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5118; op2val:0xbed6;
op3val:0x45b3; valaddr_reg:x8; val_offset:3750*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3750*FLEN/8, x10, x3, x5)

inst_1273:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x118 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2d6 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x1b3 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5118; op2val:0xbed6;
op3val:0x45b3; valaddr_reg:x8; val_offset:3753*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3753*FLEN/8, x10, x3, x5)

inst_1274:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x118 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2d6 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x1b3 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5118; op2val:0xbed6;
op3val:0x45b3; valaddr_reg:x8; val_offset:3756*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3756*FLEN/8, x10, x3, x5)

inst_1275:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x188 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x008 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x24f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4d88; op2val:0xc408;
op3val:0x4e4f; valaddr_reg:x8; val_offset:3759*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3759*FLEN/8, x10, x3, x5)

inst_1276:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x188 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x008 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x24f and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4d88; op2val:0xc408;
op3val:0x4e4f; valaddr_reg:x8; val_offset:3762*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3762*FLEN/8, x10, x3, x5)

inst_1277:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x188 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x008 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x24f and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4d88; op2val:0xc408;
op3val:0x4e4f; valaddr_reg:x8; val_offset:3765*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3765*FLEN/8, x10, x3, x5)

inst_1278:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x188 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x008 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x24f and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4d88; op2val:0xc408;
op3val:0x4e4f; valaddr_reg:x8; val_offset:3768*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3768*FLEN/8, x10, x3, x5)

inst_1279:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x188 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x008 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x24f and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4d88; op2val:0xc408;
op3val:0x4e4f; valaddr_reg:x8; val_offset:3771*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3771*FLEN/8, x10, x3, x5)

inst_1280:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x12e and fs2 == 1 and fe2 == 0x11 and fm2 == 0x09e and fs3 == 0 and fe3 == 0x13 and fm3 == 0x3ec and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4d2e; op2val:0xc49e;
op3val:0x4fec; valaddr_reg:x8; val_offset:3774*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3774*FLEN/8, x10, x3, x5)

inst_1281:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x12e and fs2 == 1 and fe2 == 0x11 and fm2 == 0x09e and fs3 == 0 and fe3 == 0x13 and fm3 == 0x3ec and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4d2e; op2val:0xc49e;
op3val:0x4fec; valaddr_reg:x8; val_offset:3777*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3777*FLEN/8, x10, x3, x5)

inst_1282:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x12e and fs2 == 1 and fe2 == 0x11 and fm2 == 0x09e and fs3 == 0 and fe3 == 0x13 and fm3 == 0x3ec and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4d2e; op2val:0xc49e;
op3val:0x4fec; valaddr_reg:x8; val_offset:3780*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3780*FLEN/8, x10, x3, x5)

inst_1283:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x12e and fs2 == 1 and fe2 == 0x11 and fm2 == 0x09e and fs3 == 0 and fe3 == 0x13 and fm3 == 0x3ec and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4d2e; op2val:0xc49e;
op3val:0x4fec; valaddr_reg:x8; val_offset:3783*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3783*FLEN/8, x10, x3, x5)

inst_1284:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x12e and fs2 == 1 and fe2 == 0x11 and fm2 == 0x09e and fs3 == 0 and fe3 == 0x13 and fm3 == 0x3ec and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4d2e; op2val:0xc49e;
op3val:0x4fec; valaddr_reg:x8; val_offset:3786*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3786*FLEN/8, x10, x3, x5)

inst_1285:
// fs1 == 0 and fe1 == 0x12 and fm1 == 0x17c and fs2 == 1 and fe2 == 0x12 and fm2 == 0x05f and fs3 == 0 and fe3 == 0x13 and fm3 == 0x3fa and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x497c; op2val:0xc85f;
op3val:0x4ffa; valaddr_reg:x8; val_offset:3789*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3789*FLEN/8, x10, x3, x5)

inst_1286:
// fs1 == 0 and fe1 == 0x12 and fm1 == 0x17c and fs2 == 1 and fe2 == 0x12 and fm2 == 0x05f and fs3 == 0 and fe3 == 0x13 and fm3 == 0x3fa and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x497c; op2val:0xc85f;
op3val:0x4ffa; valaddr_reg:x8; val_offset:3792*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3792*FLEN/8, x10, x3, x5)

inst_1287:
// fs1 == 0 and fe1 == 0x12 and fm1 == 0x17c and fs2 == 1 and fe2 == 0x12 and fm2 == 0x05f and fs3 == 0 and fe3 == 0x13 and fm3 == 0x3fa and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x497c; op2val:0xc85f;
op3val:0x4ffa; valaddr_reg:x8; val_offset:3795*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3795*FLEN/8, x10, x3, x5)

inst_1288:
// fs1 == 0 and fe1 == 0x12 and fm1 == 0x17c and fs2 == 1 and fe2 == 0x12 and fm2 == 0x05f and fs3 == 0 and fe3 == 0x13 and fm3 == 0x3fa and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x497c; op2val:0xc85f;
op3val:0x4ffa; valaddr_reg:x8; val_offset:3798*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3798*FLEN/8, x10, x3, x5)

inst_1289:
// fs1 == 0 and fe1 == 0x12 and fm1 == 0x17c and fs2 == 1 and fe2 == 0x12 and fm2 == 0x05f and fs3 == 0 and fe3 == 0x13 and fm3 == 0x3fa and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x497c; op2val:0xc85f;
op3val:0x4ffa; valaddr_reg:x8; val_offset:3801*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3801*FLEN/8, x10, x3, x5)

inst_1290:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x264 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x017 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x113 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5264; op2val:0xc017;
op3val:0x5113; valaddr_reg:x8; val_offset:3804*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3804*FLEN/8, x10, x3, x5)

inst_1291:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x264 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x017 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x113 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5264; op2val:0xc017;
op3val:0x5113; valaddr_reg:x8; val_offset:3807*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3807*FLEN/8, x10, x3, x5)

inst_1292:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x264 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x017 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x113 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5264; op2val:0xc017;
op3val:0x5113; valaddr_reg:x8; val_offset:3810*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3810*FLEN/8, x10, x3, x5)

inst_1293:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x264 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x017 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x113 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5264; op2val:0xc017;
op3val:0x5113; valaddr_reg:x8; val_offset:3813*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3813*FLEN/8, x10, x3, x5)

inst_1294:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x264 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x017 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x113 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5264; op2val:0xc017;
op3val:0x5113; valaddr_reg:x8; val_offset:3816*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3816*FLEN/8, x10, x3, x5)

inst_1295:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3c4 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x005 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x39b and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x53c4; op2val:0xc005;
op3val:0x539b; valaddr_reg:x8; val_offset:3819*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3819*FLEN/8, x10, x3, x5)

inst_1296:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3c4 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x005 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x39b and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x53c4; op2val:0xc005;
op3val:0x539b; valaddr_reg:x8; val_offset:3822*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3822*FLEN/8, x10, x3, x5)

inst_1297:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3c4 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x005 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x39b and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x53c4; op2val:0xc005;
op3val:0x539b; valaddr_reg:x8; val_offset:3825*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3825*FLEN/8, x10, x3, x5)

inst_1298:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3c4 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x005 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x39b and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x53c4; op2val:0xc005;
op3val:0x539b; valaddr_reg:x8; val_offset:3828*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3828*FLEN/8, x10, x3, x5)

inst_1299:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x3c4 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x005 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x39b and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x53c4; op2val:0xc005;
op3val:0x539b; valaddr_reg:x8; val_offset:3831*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3831*FLEN/8, x10, x3, x5)

inst_1300:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3c5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x214 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x39e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fc5; op2val:0xc214;
op3val:0x4f9e; valaddr_reg:x8; val_offset:3834*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3834*FLEN/8, x10, x3, x5)

inst_1301:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3c5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x214 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x39e and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fc5; op2val:0xc214;
op3val:0x4f9e; valaddr_reg:x8; val_offset:3837*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3837*FLEN/8, x10, x3, x5)

inst_1302:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3c5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x214 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x39e and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fc5; op2val:0xc214;
op3val:0x4f9e; valaddr_reg:x8; val_offset:3840*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3840*FLEN/8, x10, x3, x5)

inst_1303:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3c5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x214 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x39e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fc5; op2val:0xc214;
op3val:0x4f9e; valaddr_reg:x8; val_offset:3843*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3843*FLEN/8, x10, x3, x5)
RVTEST_SIGBASE(x3,signature_x3_10)

inst_1304:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3c5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x214 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x39e and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fc5; op2val:0xc214;
op3val:0x4f9e; valaddr_reg:x8; val_offset:3846*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3846*FLEN/8, x10, x3, x5)

inst_1305:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x221 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0e9 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x30d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5221; op2val:0xc0e9;
op3val:0x530d; valaddr_reg:x8; val_offset:3849*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3849*FLEN/8, x10, x3, x5)

inst_1306:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x221 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0e9 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x30d and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5221; op2val:0xc0e9;
op3val:0x530d; valaddr_reg:x8; val_offset:3852*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3852*FLEN/8, x10, x3, x5)

inst_1307:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x221 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0e9 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x30d and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5221; op2val:0xc0e9;
op3val:0x530d; valaddr_reg:x8; val_offset:3855*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3855*FLEN/8, x10, x3, x5)

inst_1308:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x221 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0e9 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x30d and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5221; op2val:0xc0e9;
op3val:0x530d; valaddr_reg:x8; val_offset:3858*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3858*FLEN/8, x10, x3, x5)

inst_1309:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x221 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0e9 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x30d and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5221; op2val:0xc0e9;
op3val:0x530d; valaddr_reg:x8; val_offset:3861*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3861*FLEN/8, x10, x3, x5)

inst_1310:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x062 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x21a and fs3 == 0 and fe3 == 0x14 and fm3 == 0x161 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5062; op2val:0xc21a;
op3val:0x5161; valaddr_reg:x8; val_offset:3864*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3864*FLEN/8, x10, x3, x5)

inst_1311:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x062 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x21a and fs3 == 0 and fe3 == 0x14 and fm3 == 0x161 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5062; op2val:0xc21a;
op3val:0x5161; valaddr_reg:x8; val_offset:3867*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3867*FLEN/8, x10, x3, x5)

inst_1312:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x062 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x21a and fs3 == 0 and fe3 == 0x14 and fm3 == 0x161 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5062; op2val:0xc21a;
op3val:0x5161; valaddr_reg:x8; val_offset:3870*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3870*FLEN/8, x10, x3, x5)

inst_1313:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x062 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x21a and fs3 == 0 and fe3 == 0x14 and fm3 == 0x161 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5062; op2val:0xc21a;
op3val:0x5161; valaddr_reg:x8; val_offset:3873*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3873*FLEN/8, x10, x3, x5)

inst_1314:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x062 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x21a and fs3 == 0 and fe3 == 0x14 and fm3 == 0x161 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5062; op2val:0xc21a;
op3val:0x5161; valaddr_reg:x8; val_offset:3876*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3876*FLEN/8, x10, x3, x5)

inst_1315:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x190 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x05f and fs3 == 0 and fe3 == 0x14 and fm3 == 0x02c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5190; op2val:0xc05f;
op3val:0x502c; valaddr_reg:x8; val_offset:3879*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3879*FLEN/8, x10, x3, x5)

inst_1316:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x190 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x05f and fs3 == 0 and fe3 == 0x14 and fm3 == 0x02c and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5190; op2val:0xc05f;
op3val:0x502c; valaddr_reg:x8; val_offset:3882*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3882*FLEN/8, x10, x3, x5)

inst_1317:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x190 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x05f and fs3 == 0 and fe3 == 0x14 and fm3 == 0x02c and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5190; op2val:0xc05f;
op3val:0x502c; valaddr_reg:x8; val_offset:3885*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3885*FLEN/8, x10, x3, x5)

inst_1318:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x190 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x05f and fs3 == 0 and fe3 == 0x14 and fm3 == 0x02c and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5190; op2val:0xc05f;
op3val:0x502c; valaddr_reg:x8; val_offset:3888*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3888*FLEN/8, x10, x3, x5)

inst_1319:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x190 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x05f and fs3 == 0 and fe3 == 0x14 and fm3 == 0x02c and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5190; op2val:0xc05f;
op3val:0x502c; valaddr_reg:x8; val_offset:3891*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3891*FLEN/8, x10, x3, x5)

inst_1320:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x020 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x177 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x291 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5020; op2val:0xc177;
op3val:0x4e91; valaddr_reg:x8; val_offset:3894*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3894*FLEN/8, x10, x3, x5)

inst_1321:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x020 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x177 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x291 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5020; op2val:0xc177;
op3val:0x4e91; valaddr_reg:x8; val_offset:3897*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3897*FLEN/8, x10, x3, x5)

inst_1322:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x020 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x177 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x291 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5020; op2val:0xc177;
op3val:0x4e91; valaddr_reg:x8; val_offset:3900*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3900*FLEN/8, x10, x3, x5)

inst_1323:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x020 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x177 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x291 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5020; op2val:0xc177;
op3val:0x4e91; valaddr_reg:x8; val_offset:3903*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3903*FLEN/8, x10, x3, x5)

inst_1324:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x020 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x177 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x291 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5020; op2val:0xc177;
op3val:0x4e91; valaddr_reg:x8; val_offset:3906*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3906*FLEN/8, x10, x3, x5)

inst_1325:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x351 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x27b and fs3 == 0 and fe3 == 0x13 and fm3 == 0x3b8 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4f51; op2val:0xc27b;
op3val:0x4fb8; valaddr_reg:x8; val_offset:3909*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3909*FLEN/8, x10, x3, x5)

inst_1326:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x351 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x27b and fs3 == 0 and fe3 == 0x13 and fm3 == 0x3b8 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4f51; op2val:0xc27b;
op3val:0x4fb8; valaddr_reg:x8; val_offset:3912*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3912*FLEN/8, x10, x3, x5)

inst_1327:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x351 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x27b and fs3 == 0 and fe3 == 0x13 and fm3 == 0x3b8 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4f51; op2val:0xc27b;
op3val:0x4fb8; valaddr_reg:x8; val_offset:3915*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3915*FLEN/8, x10, x3, x5)

inst_1328:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x351 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x27b and fs3 == 0 and fe3 == 0x13 and fm3 == 0x3b8 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4f51; op2val:0xc27b;
op3val:0x4fb8; valaddr_reg:x8; val_offset:3918*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3918*FLEN/8, x10, x3, x5)

inst_1329:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x351 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x27b and fs3 == 0 and fe3 == 0x13 and fm3 == 0x3b8 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4f51; op2val:0xc27b;
op3val:0x4fb8; valaddr_reg:x8; val_offset:3921*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3921*FLEN/8, x10, x3, x5)

inst_1330:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x272 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1d2 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x188 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5272; op2val:0xbdd2;
op3val:0x4988; valaddr_reg:x8; val_offset:3924*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3924*FLEN/8, x10, x3, x5)

inst_1331:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x272 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1d2 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x188 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5272; op2val:0xbdd2;
op3val:0x4988; valaddr_reg:x8; val_offset:3927*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3927*FLEN/8, x10, x3, x5)

inst_1332:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x272 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1d2 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x188 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5272; op2val:0xbdd2;
op3val:0x4988; valaddr_reg:x8; val_offset:3930*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3930*FLEN/8, x10, x3, x5)

inst_1333:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x272 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1d2 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x188 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5272; op2val:0xbdd2;
op3val:0x4988; valaddr_reg:x8; val_offset:3933*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3933*FLEN/8, x10, x3, x5)

inst_1334:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x272 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1d2 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x188 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5272; op2val:0xbdd2;
op3val:0x4988; valaddr_reg:x8; val_offset:3936*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3936*FLEN/8, x10, x3, x5)

inst_1335:
// fs1 == 0 and fe1 == 0x12 and fm1 == 0x034 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x352 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x365 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4834; op2val:0xcb52;
op3val:0x5365; valaddr_reg:x8; val_offset:3939*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3939*FLEN/8, x10, x3, x5)

inst_1336:
// fs1 == 0 and fe1 == 0x12 and fm1 == 0x034 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x352 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x365 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4834; op2val:0xcb52;
op3val:0x5365; valaddr_reg:x8; val_offset:3942*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3942*FLEN/8, x10, x3, x5)

inst_1337:
// fs1 == 0 and fe1 == 0x12 and fm1 == 0x034 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x352 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x365 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4834; op2val:0xcb52;
op3val:0x5365; valaddr_reg:x8; val_offset:3945*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3945*FLEN/8, x10, x3, x5)

inst_1338:
// fs1 == 0 and fe1 == 0x12 and fm1 == 0x034 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x352 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x365 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4834; op2val:0xcb52;
op3val:0x5365; valaddr_reg:x8; val_offset:3948*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3948*FLEN/8, x10, x3, x5)

inst_1339:
// fs1 == 0 and fe1 == 0x12 and fm1 == 0x034 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x352 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x365 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4834; op2val:0xcb52;
op3val:0x5365; valaddr_reg:x8; val_offset:3951*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3951*FLEN/8, x10, x3, x5)

inst_1340:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x024 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x292 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x19d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5024; op2val:0xc292;
op3val:0x519d; valaddr_reg:x8; val_offset:3954*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3954*FLEN/8, x10, x3, x5)

inst_1341:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x024 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x292 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x19d and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5024; op2val:0xc292;
op3val:0x519d; valaddr_reg:x8; val_offset:3957*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3957*FLEN/8, x10, x3, x5)

inst_1342:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x024 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x292 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x19d and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5024; op2val:0xc292;
op3val:0x519d; valaddr_reg:x8; val_offset:3960*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3960*FLEN/8, x10, x3, x5)

inst_1343:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x024 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x292 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x19d and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5024; op2val:0xc292;
op3val:0x519d; valaddr_reg:x8; val_offset:3963*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3963*FLEN/8, x10, x3, x5)

inst_1344:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x024 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x292 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x19d and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5024; op2val:0xc292;
op3val:0x519d; valaddr_reg:x8; val_offset:3966*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3966*FLEN/8, x10, x3, x5)

inst_1345:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x356 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x397 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1ec and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5356; op2val:0xbf97;
op3val:0x51ec; valaddr_reg:x8; val_offset:3969*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3969*FLEN/8, x10, x3, x5)

inst_1346:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x356 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x397 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1ec and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5356; op2val:0xbf97;
op3val:0x51ec; valaddr_reg:x8; val_offset:3972*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3972*FLEN/8, x10, x3, x5)

inst_1347:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x356 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x397 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1ec and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5356; op2val:0xbf97;
op3val:0x51ec; valaddr_reg:x8; val_offset:3975*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3975*FLEN/8, x10, x3, x5)

inst_1348:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x356 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x397 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1ec and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5356; op2val:0xbf97;
op3val:0x51ec; valaddr_reg:x8; val_offset:3978*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3978*FLEN/8, x10, x3, x5)

inst_1349:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x356 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x397 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1ec and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5356; op2val:0xbf97;
op3val:0x51ec; valaddr_reg:x8; val_offset:3981*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3981*FLEN/8, x10, x3, x5)

inst_1350:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x096 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2d0 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x39f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5096; op2val:0xc2d0;
op3val:0x539f; valaddr_reg:x8; val_offset:3984*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3984*FLEN/8, x10, x3, x5)

inst_1351:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x096 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2d0 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x39f and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5096; op2val:0xc2d0;
op3val:0x539f; valaddr_reg:x8; val_offset:3987*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 3987*FLEN/8, x10, x3, x5)

inst_1352:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x096 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2d0 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x39f and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5096; op2val:0xc2d0;
op3val:0x539f; valaddr_reg:x8; val_offset:3990*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 3990*FLEN/8, x10, x3, x5)

inst_1353:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x096 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2d0 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x39f and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5096; op2val:0xc2d0;
op3val:0x539f; valaddr_reg:x8; val_offset:3993*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 3993*FLEN/8, x10, x3, x5)

inst_1354:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x096 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2d0 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x39f and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5096; op2val:0xc2d0;
op3val:0x539f; valaddr_reg:x8; val_offset:3996*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 3996*FLEN/8, x10, x3, x5)

inst_1355:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x10a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x09e and fs3 == 0 and fe3 == 0x13 and fm3 == 0x349 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x510a; op2val:0xc09e;
op3val:0x4f49; valaddr_reg:x8; val_offset:3999*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 3999*FLEN/8, x10, x3, x5)

inst_1356:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x10a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x09e and fs3 == 0 and fe3 == 0x13 and fm3 == 0x349 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x510a; op2val:0xc09e;
op3val:0x4f49; valaddr_reg:x8; val_offset:4002*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4002*FLEN/8, x10, x3, x5)

inst_1357:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x10a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x09e and fs3 == 0 and fe3 == 0x13 and fm3 == 0x349 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x510a; op2val:0xc09e;
op3val:0x4f49; valaddr_reg:x8; val_offset:4005*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4005*FLEN/8, x10, x3, x5)

inst_1358:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x10a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x09e and fs3 == 0 and fe3 == 0x13 and fm3 == 0x349 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x510a; op2val:0xc09e;
op3val:0x4f49; valaddr_reg:x8; val_offset:4008*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4008*FLEN/8, x10, x3, x5)

inst_1359:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x10a and fs2 == 1 and fe2 == 0x10 and fm2 == 0x09e and fs3 == 0 and fe3 == 0x13 and fm3 == 0x349 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x510a; op2val:0xc09e;
op3val:0x4f49; valaddr_reg:x8; val_offset:4011*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4011*FLEN/8, x10, x3, x5)

inst_1360:
// fs1 == 0 and fe1 == 0x12 and fm1 == 0x241 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1ff and fs3 == 0 and fe3 == 0x12 and fm3 == 0x184 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4a41; op2val:0xc5ff;
op3val:0x4984; valaddr_reg:x8; val_offset:4014*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4014*FLEN/8, x10, x3, x5)

inst_1361:
// fs1 == 0 and fe1 == 0x12 and fm1 == 0x241 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1ff and fs3 == 0 and fe3 == 0x12 and fm3 == 0x184 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4a41; op2val:0xc5ff;
op3val:0x4984; valaddr_reg:x8; val_offset:4017*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4017*FLEN/8, x10, x3, x5)

inst_1362:
// fs1 == 0 and fe1 == 0x12 and fm1 == 0x241 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1ff and fs3 == 0 and fe3 == 0x12 and fm3 == 0x184 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4a41; op2val:0xc5ff;
op3val:0x4984; valaddr_reg:x8; val_offset:4020*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4020*FLEN/8, x10, x3, x5)

inst_1363:
// fs1 == 0 and fe1 == 0x12 and fm1 == 0x241 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1ff and fs3 == 0 and fe3 == 0x12 and fm3 == 0x184 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4a41; op2val:0xc5ff;
op3val:0x4984; valaddr_reg:x8; val_offset:4023*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4023*FLEN/8, x10, x3, x5)

inst_1364:
// fs1 == 0 and fe1 == 0x12 and fm1 == 0x241 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1ff and fs3 == 0 and fe3 == 0x12 and fm3 == 0x184 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4a41; op2val:0xc5ff;
op3val:0x4984; valaddr_reg:x8; val_offset:4026*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4026*FLEN/8, x10, x3, x5)

inst_1365:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x25d and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x32f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x525d; op2val:0xc0c5;
op3val:0x532f; valaddr_reg:x8; val_offset:4029*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4029*FLEN/8, x10, x3, x5)

inst_1366:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x25d and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x32f and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x525d; op2val:0xc0c5;
op3val:0x532f; valaddr_reg:x8; val_offset:4032*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4032*FLEN/8, x10, x3, x5)

inst_1367:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x25d and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x32f and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x525d; op2val:0xc0c5;
op3val:0x532f; valaddr_reg:x8; val_offset:4035*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4035*FLEN/8, x10, x3, x5)

inst_1368:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x25d and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x32f and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x525d; op2val:0xc0c5;
op3val:0x532f; valaddr_reg:x8; val_offset:4038*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4038*FLEN/8, x10, x3, x5)

inst_1369:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x25d and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0c5 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x32f and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x525d; op2val:0xc0c5;
op3val:0x532f; valaddr_reg:x8; val_offset:4041*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4041*FLEN/8, x10, x3, x5)

inst_1370:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x1df and fs2 == 1 and fe2 == 0x11 and fm2 == 0x02f and fs3 == 0 and fe3 == 0x14 and fm3 == 0x04a and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4ddf; op2val:0xc42f;
op3val:0x504a; valaddr_reg:x8; val_offset:4044*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4044*FLEN/8, x10, x3, x5)

inst_1371:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x1df and fs2 == 1 and fe2 == 0x11 and fm2 == 0x02f and fs3 == 0 and fe3 == 0x14 and fm3 == 0x04a and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4ddf; op2val:0xc42f;
op3val:0x504a; valaddr_reg:x8; val_offset:4047*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4047*FLEN/8, x10, x3, x5)

inst_1372:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x1df and fs2 == 1 and fe2 == 0x11 and fm2 == 0x02f and fs3 == 0 and fe3 == 0x14 and fm3 == 0x04a and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4ddf; op2val:0xc42f;
op3val:0x504a; valaddr_reg:x8; val_offset:4050*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4050*FLEN/8, x10, x3, x5)

inst_1373:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x1df and fs2 == 1 and fe2 == 0x11 and fm2 == 0x02f and fs3 == 0 and fe3 == 0x14 and fm3 == 0x04a and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4ddf; op2val:0xc42f;
op3val:0x504a; valaddr_reg:x8; val_offset:4053*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4053*FLEN/8, x10, x3, x5)

inst_1374:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x1df and fs2 == 1 and fe2 == 0x11 and fm2 == 0x02f and fs3 == 0 and fe3 == 0x14 and fm3 == 0x04a and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4ddf; op2val:0xc42f;
op3val:0x504a; valaddr_reg:x8; val_offset:4056*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4056*FLEN/8, x10, x3, x5)

inst_1375:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x178 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0b8 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0e7 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5178; op2val:0xc0b8;
op3val:0x50e7; valaddr_reg:x8; val_offset:4059*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4059*FLEN/8, x10, x3, x5)

inst_1376:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x178 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0b8 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0e7 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5178; op2val:0xc0b8;
op3val:0x50e7; valaddr_reg:x8; val_offset:4062*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4062*FLEN/8, x10, x3, x5)

inst_1377:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x178 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0b8 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0e7 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5178; op2val:0xc0b8;
op3val:0x50e7; valaddr_reg:x8; val_offset:4065*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4065*FLEN/8, x10, x3, x5)

inst_1378:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x178 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0b8 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0e7 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5178; op2val:0xc0b8;
op3val:0x50e7; valaddr_reg:x8; val_offset:4068*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4068*FLEN/8, x10, x3, x5)

inst_1379:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x178 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0b8 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0e7 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5178; op2val:0xc0b8;
op3val:0x50e7; valaddr_reg:x8; val_offset:4071*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4071*FLEN/8, x10, x3, x5)

inst_1380:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x096 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2ac and fs3 == 0 and fe3 == 0x14 and fm3 == 0x34d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c96; op2val:0xc6ac;
op3val:0x534d; valaddr_reg:x8; val_offset:4074*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4074*FLEN/8, x10, x3, x5)

inst_1381:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x096 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2ac and fs3 == 0 and fe3 == 0x14 and fm3 == 0x34d and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c96; op2val:0xc6ac;
op3val:0x534d; valaddr_reg:x8; val_offset:4077*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4077*FLEN/8, x10, x3, x5)

inst_1382:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x096 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2ac and fs3 == 0 and fe3 == 0x14 and fm3 == 0x34d and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c96; op2val:0xc6ac;
op3val:0x534d; valaddr_reg:x8; val_offset:4080*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4080*FLEN/8, x10, x3, x5)

inst_1383:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x096 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2ac and fs3 == 0 and fe3 == 0x14 and fm3 == 0x34d and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c96; op2val:0xc6ac;
op3val:0x534d; valaddr_reg:x8; val_offset:4083*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4083*FLEN/8, x10, x3, x5)

inst_1384:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x096 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2ac and fs3 == 0 and fe3 == 0x14 and fm3 == 0x34d and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4c96; op2val:0xc6ac;
op3val:0x534d; valaddr_reg:x8; val_offset:4086*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4086*FLEN/8, x10, x3, x5)

inst_1385:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x078 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x226 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1c0 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5078; op2val:0xc226;
op3val:0x51c0; valaddr_reg:x8; val_offset:4089*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4089*FLEN/8, x10, x3, x5)

inst_1386:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x078 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x226 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1c0 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5078; op2val:0xc226;
op3val:0x51c0; valaddr_reg:x8; val_offset:4092*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4092*FLEN/8, x10, x3, x5)

inst_1387:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x078 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x226 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1c0 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5078; op2val:0xc226;
op3val:0x51c0; valaddr_reg:x8; val_offset:4095*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4095*FLEN/8, x10, x3, x5)

inst_1388:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x078 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x226 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1c0 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5078; op2val:0xc226;
op3val:0x51c0; valaddr_reg:x8; val_offset:4098*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4098*FLEN/8, x10, x3, x5)

inst_1389:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x078 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x226 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x1c0 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5078; op2val:0xc226;
op3val:0x51c0; valaddr_reg:x8; val_offset:4101*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4101*FLEN/8, x10, x3, x5)

inst_1390:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x18c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x02c and fs3 == 0 and fe3 == 0x13 and fm3 == 0x327 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x518c; op2val:0xc02c;
op3val:0x4f27; valaddr_reg:x8; val_offset:4104*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4104*FLEN/8, x10, x3, x5)

inst_1391:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x18c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x02c and fs3 == 0 and fe3 == 0x13 and fm3 == 0x327 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x518c; op2val:0xc02c;
op3val:0x4f27; valaddr_reg:x8; val_offset:4107*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4107*FLEN/8, x10, x3, x5)

inst_1392:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x18c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x02c and fs3 == 0 and fe3 == 0x13 and fm3 == 0x327 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x518c; op2val:0xc02c;
op3val:0x4f27; valaddr_reg:x8; val_offset:4110*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4110*FLEN/8, x10, x3, x5)

inst_1393:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x18c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x02c and fs3 == 0 and fe3 == 0x13 and fm3 == 0x327 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x518c; op2val:0xc02c;
op3val:0x4f27; valaddr_reg:x8; val_offset:4113*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4113*FLEN/8, x10, x3, x5)

inst_1394:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x18c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x02c and fs3 == 0 and fe3 == 0x13 and fm3 == 0x327 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x518c; op2val:0xc02c;
op3val:0x4f27; valaddr_reg:x8; val_offset:4116*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4116*FLEN/8, x10, x3, x5)

inst_1395:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2d0 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x27b and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51a6; op2val:0xbed0;
op3val:0x4a7b; valaddr_reg:x8; val_offset:4119*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4119*FLEN/8, x10, x3, x5)

inst_1396:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2d0 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x27b and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51a6; op2val:0xbed0;
op3val:0x4a7b; valaddr_reg:x8; val_offset:4122*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4122*FLEN/8, x10, x3, x5)

inst_1397:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2d0 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x27b and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51a6; op2val:0xbed0;
op3val:0x4a7b; valaddr_reg:x8; val_offset:4125*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4125*FLEN/8, x10, x3, x5)

inst_1398:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2d0 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x27b and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51a6; op2val:0xbed0;
op3val:0x4a7b; valaddr_reg:x8; val_offset:4128*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4128*FLEN/8, x10, x3, x5)

inst_1399:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2d0 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x27b and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51a6; op2val:0xbed0;
op3val:0x4a7b; valaddr_reg:x8; val_offset:4131*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4131*FLEN/8, x10, x3, x5)

inst_1400:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x070 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1f8 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x141 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5070; op2val:0xc1f8;
op3val:0x5141; valaddr_reg:x8; val_offset:4134*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4134*FLEN/8, x10, x3, x5)

inst_1401:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x070 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1f8 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x141 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5070; op2val:0xc1f8;
op3val:0x5141; valaddr_reg:x8; val_offset:4137*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4137*FLEN/8, x10, x3, x5)

inst_1402:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x070 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1f8 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x141 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5070; op2val:0xc1f8;
op3val:0x5141; valaddr_reg:x8; val_offset:4140*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4140*FLEN/8, x10, x3, x5)

inst_1403:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x070 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1f8 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x141 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5070; op2val:0xc1f8;
op3val:0x5141; valaddr_reg:x8; val_offset:4143*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4143*FLEN/8, x10, x3, x5)

inst_1404:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x070 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1f8 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x141 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5070; op2val:0xc1f8;
op3val:0x5141; valaddr_reg:x8; val_offset:4146*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4146*FLEN/8, x10, x3, x5)

inst_1405:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x114 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x01a and fs3 == 0 and fe3 == 0x13 and fm3 == 0x0da and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5114; op2val:0xc01a;
op3val:0x4cda; valaddr_reg:x8; val_offset:4149*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4149*FLEN/8, x10, x3, x5)

inst_1406:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x114 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x01a and fs3 == 0 and fe3 == 0x13 and fm3 == 0x0da and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5114; op2val:0xc01a;
op3val:0x4cda; valaddr_reg:x8; val_offset:4152*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4152*FLEN/8, x10, x3, x5)

inst_1407:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x114 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x01a and fs3 == 0 and fe3 == 0x13 and fm3 == 0x0da and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5114; op2val:0xc01a;
op3val:0x4cda; valaddr_reg:x8; val_offset:4155*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4155*FLEN/8, x10, x3, x5)

inst_1408:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x114 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x01a and fs3 == 0 and fe3 == 0x13 and fm3 == 0x0da and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5114; op2val:0xc01a;
op3val:0x4cda; valaddr_reg:x8; val_offset:4158*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4158*FLEN/8, x10, x3, x5)

inst_1409:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x114 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x01a and fs3 == 0 and fe3 == 0x13 and fm3 == 0x0da and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5114; op2val:0xc01a;
op3val:0x4cda; valaddr_reg:x8; val_offset:4161*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4161*FLEN/8, x10, x3, x5)

inst_1410:
// fs1 == 0 and fe1 == 0x12 and fm1 == 0x237 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1bd and fs3 == 0 and fe3 == 0x11 and fm3 == 0x361 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4a37; op2val:0xc5bd;
op3val:0x4761; valaddr_reg:x8; val_offset:4164*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4164*FLEN/8, x10, x3, x5)

inst_1411:
// fs1 == 0 and fe1 == 0x12 and fm1 == 0x237 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1bd and fs3 == 0 and fe3 == 0x11 and fm3 == 0x361 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4a37; op2val:0xc5bd;
op3val:0x4761; valaddr_reg:x8; val_offset:4167*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4167*FLEN/8, x10, x3, x5)

inst_1412:
// fs1 == 0 and fe1 == 0x12 and fm1 == 0x237 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1bd and fs3 == 0 and fe3 == 0x11 and fm3 == 0x361 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4a37; op2val:0xc5bd;
op3val:0x4761; valaddr_reg:x8; val_offset:4170*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4170*FLEN/8, x10, x3, x5)

inst_1413:
// fs1 == 0 and fe1 == 0x12 and fm1 == 0x237 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1bd and fs3 == 0 and fe3 == 0x11 and fm3 == 0x361 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4a37; op2val:0xc5bd;
op3val:0x4761; valaddr_reg:x8; val_offset:4173*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4173*FLEN/8, x10, x3, x5)

inst_1414:
// fs1 == 0 and fe1 == 0x12 and fm1 == 0x237 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x1bd and fs3 == 0 and fe3 == 0x11 and fm3 == 0x361 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4a37; op2val:0xc5bd;
op3val:0x4761; valaddr_reg:x8; val_offset:4176*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4176*FLEN/8, x10, x3, x5)

inst_1415:
// fs1 == 0 and fe1 == 0x12 and fm1 == 0x066 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x05a and fs3 == 0 and fe3 == 0x12 and fm3 == 0x24e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4866; op2val:0xc85a;
op3val:0x4a4e; valaddr_reg:x8; val_offset:4179*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4179*FLEN/8, x10, x3, x5)

inst_1416:
// fs1 == 0 and fe1 == 0x12 and fm1 == 0x066 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x05a and fs3 == 0 and fe3 == 0x12 and fm3 == 0x24e and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4866; op2val:0xc85a;
op3val:0x4a4e; valaddr_reg:x8; val_offset:4182*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4182*FLEN/8, x10, x3, x5)

inst_1417:
// fs1 == 0 and fe1 == 0x12 and fm1 == 0x066 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x05a and fs3 == 0 and fe3 == 0x12 and fm3 == 0x24e and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4866; op2val:0xc85a;
op3val:0x4a4e; valaddr_reg:x8; val_offset:4185*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4185*FLEN/8, x10, x3, x5)

inst_1418:
// fs1 == 0 and fe1 == 0x12 and fm1 == 0x066 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x05a and fs3 == 0 and fe3 == 0x12 and fm3 == 0x24e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4866; op2val:0xc85a;
op3val:0x4a4e; valaddr_reg:x8; val_offset:4188*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4188*FLEN/8, x10, x3, x5)

inst_1419:
// fs1 == 0 and fe1 == 0x12 and fm1 == 0x066 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x05a and fs3 == 0 and fe3 == 0x12 and fm3 == 0x24e and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4866; op2val:0xc85a;
op3val:0x4a4e; valaddr_reg:x8; val_offset:4191*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4191*FLEN/8, x10, x3, x5)

inst_1420:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3e5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x262 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x09a and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fe5; op2val:0xc262;
op3val:0x509a; valaddr_reg:x8; val_offset:4194*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4194*FLEN/8, x10, x3, x5)

inst_1421:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3e5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x262 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x09a and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fe5; op2val:0xc262;
op3val:0x509a; valaddr_reg:x8; val_offset:4197*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4197*FLEN/8, x10, x3, x5)

inst_1422:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3e5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x262 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x09a and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fe5; op2val:0xc262;
op3val:0x509a; valaddr_reg:x8; val_offset:4200*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4200*FLEN/8, x10, x3, x5)

inst_1423:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3e5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x262 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x09a and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fe5; op2val:0xc262;
op3val:0x509a; valaddr_reg:x8; val_offset:4203*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4203*FLEN/8, x10, x3, x5)

inst_1424:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3e5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x262 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x09a and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fe5; op2val:0xc262;
op3val:0x509a; valaddr_reg:x8; val_offset:4206*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4206*FLEN/8, x10, x3, x5)

inst_1425:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1af and fs2 == 1 and fe2 == 0x10 and fm2 == 0x012 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x326 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51af; op2val:0xc012;
op3val:0x4f26; valaddr_reg:x8; val_offset:4209*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4209*FLEN/8, x10, x3, x5)

inst_1426:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1af and fs2 == 1 and fe2 == 0x10 and fm2 == 0x012 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x326 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51af; op2val:0xc012;
op3val:0x4f26; valaddr_reg:x8; val_offset:4212*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4212*FLEN/8, x10, x3, x5)

inst_1427:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1af and fs2 == 1 and fe2 == 0x10 and fm2 == 0x012 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x326 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51af; op2val:0xc012;
op3val:0x4f26; valaddr_reg:x8; val_offset:4215*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4215*FLEN/8, x10, x3, x5)

inst_1428:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1af and fs2 == 1 and fe2 == 0x10 and fm2 == 0x012 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x326 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51af; op2val:0xc012;
op3val:0x4f26; valaddr_reg:x8; val_offset:4218*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4218*FLEN/8, x10, x3, x5)

inst_1429:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x1af and fs2 == 1 and fe2 == 0x10 and fm2 == 0x012 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x326 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x51af; op2val:0xc012;
op3val:0x4f26; valaddr_reg:x8; val_offset:4221*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4221*FLEN/8, x10, x3, x5)

inst_1430:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x22b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x16a and fs3 == 0 and fe3 == 0x10 and fm3 == 0x1bb and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x522b; op2val:0xbd6a;
op3val:0x41bb; valaddr_reg:x8; val_offset:4224*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4224*FLEN/8, x10, x3, x5)

inst_1431:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x22b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x16a and fs3 == 0 and fe3 == 0x10 and fm3 == 0x1bb and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x522b; op2val:0xbd6a;
op3val:0x41bb; valaddr_reg:x8; val_offset:4227*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4227*FLEN/8, x10, x3, x5)
RVTEST_SIGBASE(x3,signature_x3_11)

inst_1432:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x22b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x16a and fs3 == 0 and fe3 == 0x10 and fm3 == 0x1bb and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x522b; op2val:0xbd6a;
op3val:0x41bb; valaddr_reg:x8; val_offset:4230*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4230*FLEN/8, x10, x3, x5)

inst_1433:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x22b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x16a and fs3 == 0 and fe3 == 0x10 and fm3 == 0x1bb and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x522b; op2val:0xbd6a;
op3val:0x41bb; valaddr_reg:x8; val_offset:4233*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4233*FLEN/8, x10, x3, x5)

inst_1434:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x22b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x16a and fs3 == 0 and fe3 == 0x10 and fm3 == 0x1bb and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x522b; op2val:0xbd6a;
op3val:0x41bb; valaddr_reg:x8; val_offset:4236*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4236*FLEN/8, x10, x3, x5)

inst_1435:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x1bc and fs2 == 1 and fe2 == 0x10 and fm2 == 0x252 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x042 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4dbc; op2val:0xc252;
op3val:0x4842; valaddr_reg:x8; val_offset:4239*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4239*FLEN/8, x10, x3, x5)

inst_1436:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x1bc and fs2 == 1 and fe2 == 0x10 and fm2 == 0x252 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x042 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4dbc; op2val:0xc252;
op3val:0x4842; valaddr_reg:x8; val_offset:4242*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4242*FLEN/8, x10, x3, x5)

inst_1437:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x1bc and fs2 == 1 and fe2 == 0x10 and fm2 == 0x252 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x042 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4dbc; op2val:0xc252;
op3val:0x4842; valaddr_reg:x8; val_offset:4245*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4245*FLEN/8, x10, x3, x5)

inst_1438:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x1bc and fs2 == 1 and fe2 == 0x10 and fm2 == 0x252 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x042 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4dbc; op2val:0xc252;
op3val:0x4842; valaddr_reg:x8; val_offset:4248*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4248*FLEN/8, x10, x3, x5)

inst_1439:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x1bc and fs2 == 1 and fe2 == 0x10 and fm2 == 0x252 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x042 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4dbc; op2val:0xc252;
op3val:0x4842; valaddr_reg:x8; val_offset:4251*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4251*FLEN/8, x10, x3, x5)

inst_1440:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x031 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x206 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0a2 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5031; op2val:0xc206;
op3val:0x50a2; valaddr_reg:x8; val_offset:4254*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4254*FLEN/8, x10, x3, x5)

inst_1441:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x031 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x206 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0a2 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5031; op2val:0xc206;
op3val:0x50a2; valaddr_reg:x8; val_offset:4257*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4257*FLEN/8, x10, x3, x5)

inst_1442:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x031 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x206 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0a2 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5031; op2val:0xc206;
op3val:0x50a2; valaddr_reg:x8; val_offset:4260*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4260*FLEN/8, x10, x3, x5)

inst_1443:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x031 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x206 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0a2 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5031; op2val:0xc206;
op3val:0x50a2; valaddr_reg:x8; val_offset:4263*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4263*FLEN/8, x10, x3, x5)

inst_1444:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x031 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x206 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x0a2 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x5031; op2val:0xc206;
op3val:0x50a2; valaddr_reg:x8; val_offset:4266*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4266*FLEN/8, x10, x3, x5)

inst_1445:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0b8 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ec and fs3 == 0 and fe3 == 0x13 and fm3 == 0x33c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x50b8; op2val:0xc0ec;
op3val:0x4f3c; valaddr_reg:x8; val_offset:4269*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4269*FLEN/8, x10, x3, x5)

inst_1446:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0b8 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ec and fs3 == 0 and fe3 == 0x13 and fm3 == 0x33c and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x50b8; op2val:0xc0ec;
op3val:0x4f3c; valaddr_reg:x8; val_offset:4272*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4272*FLEN/8, x10, x3, x5)

inst_1447:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0b8 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ec and fs3 == 0 and fe3 == 0x13 and fm3 == 0x33c and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x50b8; op2val:0xc0ec;
op3val:0x4f3c; valaddr_reg:x8; val_offset:4275*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4275*FLEN/8, x10, x3, x5)

inst_1448:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0b8 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ec and fs3 == 0 and fe3 == 0x13 and fm3 == 0x33c and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x50b8; op2val:0xc0ec;
op3val:0x4f3c; valaddr_reg:x8; val_offset:4278*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4278*FLEN/8, x10, x3, x5)

inst_1449:
// fs1 == 0 and fe1 == 0x14 and fm1 == 0x0b8 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0ec and fs3 == 0 and fe3 == 0x13 and fm3 == 0x33c and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x50b8; op2val:0xc0ec;
op3val:0x4f3c; valaddr_reg:x8; val_offset:4281*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4281*FLEN/8, x10, x3, x5)

inst_1450:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x20c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x315 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x16c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e0c; op2val:0xc315;
op3val:0x4d6c; valaddr_reg:x8; val_offset:4284*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4284*FLEN/8, x10, x3, x5)

inst_1451:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x20c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x315 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x16c and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e0c; op2val:0xc315;
op3val:0x4d6c; valaddr_reg:x8; val_offset:4287*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4287*FLEN/8, x10, x3, x5)

inst_1452:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x20c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x315 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x16c and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e0c; op2val:0xc315;
op3val:0x4d6c; valaddr_reg:x8; val_offset:4290*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4290*FLEN/8, x10, x3, x5)

inst_1453:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x20c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x315 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x16c and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e0c; op2val:0xc315;
op3val:0x4d6c; valaddr_reg:x8; val_offset:4293*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4293*FLEN/8, x10, x3, x5)

inst_1454:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x20c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x315 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x16c and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4e0c; op2val:0xc315;
op3val:0x4d6c; valaddr_reg:x8; val_offset:4296*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4296*FLEN/8, x10, x3, x5)

inst_1455:
// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3b1 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x104 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x297 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x47b1; op2val:0xc904;
op3val:0x4a97; valaddr_reg:x8; val_offset:4299*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4299*FLEN/8, x10, x3, x5)

inst_1456:
// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3b1 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x104 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x297 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x47b1; op2val:0xc904;
op3val:0x4a97; valaddr_reg:x8; val_offset:4302*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4302*FLEN/8, x10, x3, x5)

inst_1457:
// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3b1 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x104 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x297 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x47b1; op2val:0xc904;
op3val:0x4a97; valaddr_reg:x8; val_offset:4305*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4305*FLEN/8, x10, x3, x5)

inst_1458:
// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3b1 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x104 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x297 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x47b1; op2val:0xc904;
op3val:0x4a97; valaddr_reg:x8; val_offset:4308*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4308*FLEN/8, x10, x3, x5)

inst_1459:
// fs1 == 0 and fe1 == 0x11 and fm1 == 0x3b1 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x104 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x297 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x47b1; op2val:0xc904;
op3val:0x4a97; valaddr_reg:x8; val_offset:4311*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4311*FLEN/8, x10, x3, x5)

inst_1460:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3ea and fs2 == 1 and fe2 == 0x10 and fm2 == 0x25d and fs3 == 0 and fe3 == 0x14 and fm3 == 0x098 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fea; op2val:0xc25d;
op3val:0x5098; valaddr_reg:x8; val_offset:4314*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4314*FLEN/8, x10, x3, x5)

inst_1461:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3ea and fs2 == 1 and fe2 == 0x10 and fm2 == 0x25d and fs3 == 0 and fe3 == 0x14 and fm3 == 0x098 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fea; op2val:0xc25d;
op3val:0x5098; valaddr_reg:x8; val_offset:4317*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4317*FLEN/8, x10, x3, x5)

inst_1462:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3ea and fs2 == 1 and fe2 == 0x10 and fm2 == 0x25d and fs3 == 0 and fe3 == 0x14 and fm3 == 0x098 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fea; op2val:0xc25d;
op3val:0x5098; valaddr_reg:x8; val_offset:4320*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4320*FLEN/8, x10, x3, x5)

inst_1463:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3ea and fs2 == 1 and fe2 == 0x10 and fm2 == 0x25d and fs3 == 0 and fe3 == 0x14 and fm3 == 0x098 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fea; op2val:0xc25d;
op3val:0x5098; valaddr_reg:x8; val_offset:4323*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4323*FLEN/8, x10, x3, x5)

inst_1464:
// fs1 == 0 and fe1 == 0x13 and fm1 == 0x3ea and fs2 == 1 and fe2 == 0x10 and fm2 == 0x25d and fs3 == 0 and fe3 == 0x14 and fm3 == 0x098 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4fea; op2val:0xc25d;
op3val:0x5098; valaddr_reg:x8; val_offset:4326*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4326*FLEN/8, x10, x3, x5)

inst_1465:
// fs1 == 0 and fe1 == 0x11 and fm1 == 0x355 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x008 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x2c8 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4755; op2val:0xcc08;
op3val:0x52c8; valaddr_reg:x8; val_offset:4329*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4329*FLEN/8, x10, x3, x5)

inst_1466:
// fs1 == 0 and fe1 == 0x11 and fm1 == 0x355 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x008 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x2c8 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4755; op2val:0xcc08;
op3val:0x52c8; valaddr_reg:x8; val_offset:4332*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4332*FLEN/8, x10, x3, x5)

inst_1467:
// fs1 == 0 and fe1 == 0x11 and fm1 == 0x355 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x008 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x2c8 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4755; op2val:0xcc08;
op3val:0x52c8; valaddr_reg:x8; val_offset:4335*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4335*FLEN/8, x10, x3, x5)

inst_1468:
// fs1 == 0 and fe1 == 0x11 and fm1 == 0x355 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x008 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x2c8 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4755; op2val:0xcc08;
op3val:0x52c8; valaddr_reg:x8; val_offset:4338*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4338*FLEN/8, x10, x3, x5)

inst_1469:
// fs1 == 0 and fe1 == 0x11 and fm1 == 0x355 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x008 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x2c8 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x4755; op2val:0xcc08;
op3val:0x52c8; valaddr_reg:x8; val_offset:4341*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4341*FLEN/8, x10, x3, x5)

inst_1470:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x379 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x305 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc8; op2val:0xbb79;
op3val:0x3b05; valaddr_reg:x8; val_offset:4344*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4344*FLEN/8, x10, x3, x5)

inst_1471:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x379 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x305 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc8; op2val:0xbb79;
op3val:0x3b05; valaddr_reg:x8; val_offset:4347*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4347*FLEN/8, x10, x3, x5)

inst_1472:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x379 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x305 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc8; op2val:0xbb79;
op3val:0x3b05; valaddr_reg:x8; val_offset:4350*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4350*FLEN/8, x10, x3, x5)

inst_1473:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x379 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x305 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc8; op2val:0xbb79;
op3val:0x3b05; valaddr_reg:x8; val_offset:4353*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4353*FLEN/8, x10, x3, x5)

inst_1474:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3c8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x379 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x305 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3bc8; op2val:0xbb79;
op3val:0x3b05; valaddr_reg:x8; val_offset:4356*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4356*FLEN/8, x10, x3, x5)

inst_1475:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x087 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x102 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x16b and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3887; op2val:0xbd02;
op3val:0x396b; valaddr_reg:x8; val_offset:4359*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4359*FLEN/8, x10, x3, x5)

inst_1476:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x087 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x102 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x16b and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3887; op2val:0xbd02;
op3val:0x396b; valaddr_reg:x8; val_offset:4362*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4362*FLEN/8, x10, x3, x5)

inst_1477:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x087 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x102 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x16b and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3887; op2val:0xbd02;
op3val:0x396b; valaddr_reg:x8; val_offset:4365*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4365*FLEN/8, x10, x3, x5)

inst_1478:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x087 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x102 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x16b and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3887; op2val:0xbd02;
op3val:0x396b; valaddr_reg:x8; val_offset:4368*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4368*FLEN/8, x10, x3, x5)

inst_1479:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x087 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x102 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x16b and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3887; op2val:0xbd02;
op3val:0x396b; valaddr_reg:x8; val_offset:4371*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4371*FLEN/8, x10, x3, x5)

inst_1480:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1d9 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x14e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37f0; op2val:0xb9d9;
op3val:0x354e; valaddr_reg:x8; val_offset:4374*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4374*FLEN/8, x10, x3, x5)

inst_1481:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1d9 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x14e and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37f0; op2val:0xb9d9;
op3val:0x354e; valaddr_reg:x8; val_offset:4377*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4377*FLEN/8, x10, x3, x5)

inst_1482:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1d9 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x14e and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37f0; op2val:0xb9d9;
op3val:0x354e; valaddr_reg:x8; val_offset:4380*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4380*FLEN/8, x10, x3, x5)

inst_1483:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1d9 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x14e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37f0; op2val:0xb9d9;
op3val:0x354e; valaddr_reg:x8; val_offset:4383*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4383*FLEN/8, x10, x3, x5)

inst_1484:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x3f0 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x1d9 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x14e and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x37f0; op2val:0xb9d9;
op3val:0x354e; valaddr_reg:x8; val_offset:4386*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4386*FLEN/8, x10, x3, x5)

inst_1485:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x11c and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3aa and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36c8; op2val:0xb91c;
op3val:0x33aa; valaddr_reg:x8; val_offset:4389*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4389*FLEN/8, x10, x3, x5)

inst_1486:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x11c and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3aa and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36c8; op2val:0xb91c;
op3val:0x33aa; valaddr_reg:x8; val_offset:4392*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4392*FLEN/8, x10, x3, x5)

inst_1487:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x11c and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3aa and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36c8; op2val:0xb91c;
op3val:0x33aa; valaddr_reg:x8; val_offset:4395*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4395*FLEN/8, x10, x3, x5)

inst_1488:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x11c and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3aa and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36c8; op2val:0xb91c;
op3val:0x33aa; valaddr_reg:x8; val_offset:4398*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4398*FLEN/8, x10, x3, x5)

inst_1489:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x2c8 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x11c and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3aa and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x36c8; op2val:0xb91c;
op3val:0x33aa; valaddr_reg:x8; val_offset:4401*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4401*FLEN/8, x10, x3, x5)

inst_1490:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x186 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x184 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x385b; op2val:0xb986;
op3val:0x3584; valaddr_reg:x8; val_offset:4404*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4404*FLEN/8, x10, x3, x5)

inst_1491:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x186 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x184 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x385b; op2val:0xb986;
op3val:0x3584; valaddr_reg:x8; val_offset:4407*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4407*FLEN/8, x10, x3, x5)

inst_1492:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x186 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x184 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x385b; op2val:0xb986;
op3val:0x3584; valaddr_reg:x8; val_offset:4410*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4410*FLEN/8, x10, x3, x5)

inst_1493:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x186 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x184 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x385b; op2val:0xb986;
op3val:0x3584; valaddr_reg:x8; val_offset:4413*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4413*FLEN/8, x10, x3, x5)

inst_1494:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x05b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x186 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x184 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x385b; op2val:0xb986;
op3val:0x3584; valaddr_reg:x8; val_offset:4416*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4416*FLEN/8, x10, x3, x5)

inst_1495:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c2 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x21c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x305 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38c2; op2val:0xbe1c;
op3val:0x3b05; valaddr_reg:x8; val_offset:4419*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4419*FLEN/8, x10, x3, x5)

inst_1496:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c2 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x21c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x305 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38c2; op2val:0xbe1c;
op3val:0x3b05; valaddr_reg:x8; val_offset:4422*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4422*FLEN/8, x10, x3, x5)

inst_1497:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c2 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x21c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x305 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38c2; op2val:0xbe1c;
op3val:0x3b05; valaddr_reg:x8; val_offset:4425*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4425*FLEN/8, x10, x3, x5)

inst_1498:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c2 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x21c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x305 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38c2; op2val:0xbe1c;
op3val:0x3b05; valaddr_reg:x8; val_offset:4428*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4428*FLEN/8, x10, x3, x5)

inst_1499:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x0c2 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x21c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x305 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x38c2; op2val:0xbe1c;
op3val:0x3b05; valaddr_reg:x8; val_offset:4431*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4431*FLEN/8, x10, x3, x5)

inst_1500:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x35e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x297 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6c; op2val:0xbb5e;
op3val:0x3a97; valaddr_reg:x8; val_offset:4434*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4434*FLEN/8, x10, x3, x5)

inst_1501:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x35e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x297 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6c; op2val:0xbb5e;
op3val:0x3a97; valaddr_reg:x8; val_offset:4437*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4437*FLEN/8, x10, x3, x5)

inst_1502:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x35e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x297 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6c; op2val:0xbb5e;
op3val:0x3a97; valaddr_reg:x8; val_offset:4440*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4440*FLEN/8, x10, x3, x5)

inst_1503:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x35e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x297 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6c; op2val:0xbb5e;
op3val:0x3a97; valaddr_reg:x8; val_offset:4443*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4443*FLEN/8, x10, x3, x5)

inst_1504:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x35e and fs3 == 0 and fe3 == 0x0e and fm3 == 0x297 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6c; op2val:0xbb5e;
op3val:0x3a97; valaddr_reg:x8; val_offset:4446*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4446*FLEN/8, x10, x3, x5)

inst_1505:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x08f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x15c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1dc and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x388f; op2val:0xbd5c;
op3val:0x39dc; valaddr_reg:x8; val_offset:4449*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4449*FLEN/8, x10, x3, x5)

inst_1506:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x08f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x15c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1dc and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x388f; op2val:0xbd5c;
op3val:0x39dc; valaddr_reg:x8; val_offset:4452*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4452*FLEN/8, x10, x3, x5)

inst_1507:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x08f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x15c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1dc and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x388f; op2val:0xbd5c;
op3val:0x39dc; valaddr_reg:x8; val_offset:4455*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4455*FLEN/8, x10, x3, x5)

inst_1508:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x08f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x15c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1dc and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x388f; op2val:0xbd5c;
op3val:0x39dc; valaddr_reg:x8; val_offset:4458*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4458*FLEN/8, x10, x3, x5)

inst_1509:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x08f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x15c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1dc and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x388f; op2val:0xbd5c;
op3val:0x39dc; valaddr_reg:x8; val_offset:4461*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4461*FLEN/8, x10, x3, x5)

inst_1510:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x34f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2bd and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1a8 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x374f; op2val:0xbabd;
op3val:0x35a8; valaddr_reg:x8; val_offset:4464*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4464*FLEN/8, x10, x3, x5)

inst_1511:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x34f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2bd and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1a8 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x374f; op2val:0xbabd;
op3val:0x35a8; valaddr_reg:x8; val_offset:4467*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4467*FLEN/8, x10, x3, x5)

inst_1512:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x34f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2bd and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1a8 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x374f; op2val:0xbabd;
op3val:0x35a8; valaddr_reg:x8; val_offset:4470*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4470*FLEN/8, x10, x3, x5)

inst_1513:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x34f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2bd and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1a8 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x374f; op2val:0xbabd;
op3val:0x35a8; valaddr_reg:x8; val_offset:4473*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4473*FLEN/8, x10, x3, x5)

inst_1514:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x34f and fs2 == 1 and fe2 == 0x0e and fm2 == 0x2bd and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1a8 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x374f; op2val:0xbabd;
op3val:0x35a8; valaddr_reg:x8; val_offset:4476*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4476*FLEN/8, x10, x3, x5)

inst_1515:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x301 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x00c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2d6 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f01; op2val:0xc80c;
op3val:0x3ad6; valaddr_reg:x8; val_offset:4479*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4479*FLEN/8, x10, x3, x5)

inst_1516:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x301 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x00c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2d6 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f01; op2val:0xc80c;
op3val:0x3ad6; valaddr_reg:x8; val_offset:4482*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4482*FLEN/8, x10, x3, x5)

inst_1517:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x301 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x00c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2d6 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f01; op2val:0xc80c;
op3val:0x3ad6; valaddr_reg:x8; val_offset:4485*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4485*FLEN/8, x10, x3, x5)

inst_1518:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x301 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x00c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2d6 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f01; op2val:0xc80c;
op3val:0x3ad6; valaddr_reg:x8; val_offset:4488*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4488*FLEN/8, x10, x3, x5)

inst_1519:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x301 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x00c and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2d6 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f01; op2val:0xc80c;
op3val:0x3ad6; valaddr_reg:x8; val_offset:4491*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4491*FLEN/8, x10, x3, x5)

inst_1520:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x31f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3fd and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ca0; op2val:0xcb1f;
op3val:0x3bfd; valaddr_reg:x8; val_offset:4494*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4494*FLEN/8, x10, x3, x5)

inst_1521:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x31f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3fd and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ca0; op2val:0xcb1f;
op3val:0x3bfd; valaddr_reg:x8; val_offset:4497*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4497*FLEN/8, x10, x3, x5)

inst_1522:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x31f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3fd and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ca0; op2val:0xcb1f;
op3val:0x3bfd; valaddr_reg:x8; val_offset:4500*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4500*FLEN/8, x10, x3, x5)

inst_1523:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x31f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3fd and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ca0; op2val:0xcb1f;
op3val:0x3bfd; valaddr_reg:x8; val_offset:4503*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4503*FLEN/8, x10, x3, x5)

inst_1524:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x31f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3fd and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2ca0; op2val:0xcb1f;
op3val:0x3bfd; valaddr_reg:x8; val_offset:4506*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4506*FLEN/8, x10, x3, x5)

inst_1525:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x06e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x076 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x1e2 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x306e; op2val:0xb876;
op3val:0x29e2; valaddr_reg:x8; val_offset:4509*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4509*FLEN/8, x10, x3, x5)

inst_1526:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x06e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x076 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x1e2 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x306e; op2val:0xb876;
op3val:0x29e2; valaddr_reg:x8; val_offset:4512*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4512*FLEN/8, x10, x3, x5)

inst_1527:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x06e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x076 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x1e2 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x306e; op2val:0xb876;
op3val:0x29e2; valaddr_reg:x8; val_offset:4515*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4515*FLEN/8, x10, x3, x5)

inst_1528:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x06e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x076 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x1e2 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x306e; op2val:0xb876;
op3val:0x29e2; valaddr_reg:x8; val_offset:4518*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4518*FLEN/8, x10, x3, x5)

inst_1529:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x06e and fs2 == 1 and fe2 == 0x0e and fm2 == 0x076 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x1e2 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x306e; op2val:0xb876;
op3val:0x29e2; valaddr_reg:x8; val_offset:4521*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4521*FLEN/8, x10, x3, x5)

inst_1530:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x12b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x261 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x33e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x392b; op2val:0xb661;
op3val:0x333e; valaddr_reg:x8; val_offset:4524*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4524*FLEN/8, x10, x3, x5)

inst_1531:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x12b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x261 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x33e and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x392b; op2val:0xb661;
op3val:0x333e; valaddr_reg:x8; val_offset:4527*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4527*FLEN/8, x10, x3, x5)

inst_1532:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x12b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x261 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x33e and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x392b; op2val:0xb661;
op3val:0x333e; valaddr_reg:x8; val_offset:4530*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4530*FLEN/8, x10, x3, x5)

inst_1533:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x12b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x261 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x33e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x392b; op2val:0xb661;
op3val:0x333e; valaddr_reg:x8; val_offset:4533*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4533*FLEN/8, x10, x3, x5)

inst_1534:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x12b and fs2 == 1 and fe2 == 0x0d and fm2 == 0x261 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x33e and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x392b; op2val:0xb661;
op3val:0x333e; valaddr_reg:x8; val_offset:4536*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4536*FLEN/8, x10, x3, x5)

inst_1535:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x015 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3a0 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x349 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3815; op2val:0xbba0;
op3val:0x3749; valaddr_reg:x8; val_offset:4539*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4539*FLEN/8, x10, x3, x5)

inst_1536:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x015 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3a0 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x349 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3815; op2val:0xbba0;
op3val:0x3749; valaddr_reg:x8; val_offset:4542*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4542*FLEN/8, x10, x3, x5)

inst_1537:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x015 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3a0 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x349 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3815; op2val:0xbba0;
op3val:0x3749; valaddr_reg:x8; val_offset:4545*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4545*FLEN/8, x10, x3, x5)

inst_1538:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x015 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3a0 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x349 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3815; op2val:0xbba0;
op3val:0x3749; valaddr_reg:x8; val_offset:4548*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4548*FLEN/8, x10, x3, x5)

inst_1539:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x015 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x3a0 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x349 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3815; op2val:0xbba0;
op3val:0x3749; valaddr_reg:x8; val_offset:4551*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4551*FLEN/8, x10, x3, x5)

inst_1540:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x16c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x19f and fs3 == 0 and fe3 == 0x0b and fm3 == 0x19e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x316c; op2val:0xb99f;
op3val:0x2d9e; valaddr_reg:x8; val_offset:4554*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4554*FLEN/8, x10, x3, x5)

inst_1541:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x16c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x19f and fs3 == 0 and fe3 == 0x0b and fm3 == 0x19e and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x316c; op2val:0xb99f;
op3val:0x2d9e; valaddr_reg:x8; val_offset:4557*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4557*FLEN/8, x10, x3, x5)

inst_1542:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x16c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x19f and fs3 == 0 and fe3 == 0x0b and fm3 == 0x19e and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x316c; op2val:0xb99f;
op3val:0x2d9e; valaddr_reg:x8; val_offset:4560*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4560*FLEN/8, x10, x3, x5)

inst_1543:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x16c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x19f and fs3 == 0 and fe3 == 0x0b and fm3 == 0x19e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x316c; op2val:0xb99f;
op3val:0x2d9e; valaddr_reg:x8; val_offset:4563*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4563*FLEN/8, x10, x3, x5)

inst_1544:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x16c and fs2 == 1 and fe2 == 0x0e and fm2 == 0x19f and fs3 == 0 and fe3 == 0x0b and fm3 == 0x19e and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x316c; op2val:0xb99f;
op3val:0x2d9e; valaddr_reg:x8; val_offset:4566*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4566*FLEN/8, x10, x3, x5)

inst_1545:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ac and fs2 == 1 and fe2 == 0x0f and fm2 == 0x09d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x24c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ac; op2val:0xbc9d;
op3val:0x3a4c; valaddr_reg:x8; val_offset:4569*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4569*FLEN/8, x10, x3, x5)

inst_1546:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ac and fs2 == 1 and fe2 == 0x0f and fm2 == 0x09d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x24c and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ac; op2val:0xbc9d;
op3val:0x3a4c; valaddr_reg:x8; val_offset:4572*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4572*FLEN/8, x10, x3, x5)

inst_1547:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ac and fs2 == 1 and fe2 == 0x0f and fm2 == 0x09d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x24c and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ac; op2val:0xbc9d;
op3val:0x3a4c; valaddr_reg:x8; val_offset:4575*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4575*FLEN/8, x10, x3, x5)

inst_1548:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ac and fs2 == 1 and fe2 == 0x0f and fm2 == 0x09d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x24c and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ac; op2val:0xbc9d;
op3val:0x3a4c; valaddr_reg:x8; val_offset:4578*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4578*FLEN/8, x10, x3, x5)

inst_1549:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1ac and fs2 == 1 and fe2 == 0x0f and fm2 == 0x09d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x24c and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39ac; op2val:0xbc9d;
op3val:0x3a4c; valaddr_reg:x8; val_offset:4581*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4581*FLEN/8, x10, x3, x5)

inst_1550:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x330 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x013 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2d3 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f30; op2val:0xc413;
op3val:0x36d3; valaddr_reg:x8; val_offset:4584*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4584*FLEN/8, x10, x3, x5)

inst_1551:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x330 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x013 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2d3 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f30; op2val:0xc413;
op3val:0x36d3; valaddr_reg:x8; val_offset:4587*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4587*FLEN/8, x10, x3, x5)

inst_1552:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x330 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x013 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2d3 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f30; op2val:0xc413;
op3val:0x36d3; valaddr_reg:x8; val_offset:4590*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4590*FLEN/8, x10, x3, x5)

inst_1553:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x330 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x013 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2d3 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f30; op2val:0xc413;
op3val:0x36d3; valaddr_reg:x8; val_offset:4593*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4593*FLEN/8, x10, x3, x5)

inst_1554:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x330 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x013 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x2d3 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f30; op2val:0xc413;
op3val:0x36d3; valaddr_reg:x8; val_offset:4596*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4596*FLEN/8, x10, x3, x5)

inst_1555:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x00b and fs2 == 1 and fe2 == 0x11 and fm2 == 0x276 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x249 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x300b; op2val:0xc676;
op3val:0x3a49; valaddr_reg:x8; val_offset:4599*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4599*FLEN/8, x10, x3, x5)

inst_1556:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x00b and fs2 == 1 and fe2 == 0x11 and fm2 == 0x276 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x249 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x300b; op2val:0xc676;
op3val:0x3a49; valaddr_reg:x8; val_offset:4602*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4602*FLEN/8, x10, x3, x5)

inst_1557:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x00b and fs2 == 1 and fe2 == 0x11 and fm2 == 0x276 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x249 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x300b; op2val:0xc676;
op3val:0x3a49; valaddr_reg:x8; val_offset:4605*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4605*FLEN/8, x10, x3, x5)

inst_1558:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x00b and fs2 == 1 and fe2 == 0x11 and fm2 == 0x276 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x249 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x300b; op2val:0xc676;
op3val:0x3a49; valaddr_reg:x8; val_offset:4608*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4608*FLEN/8, x10, x3, x5)

inst_1559:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x00b and fs2 == 1 and fe2 == 0x11 and fm2 == 0x276 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x249 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x300b; op2val:0xc676;
op3val:0x3a49; valaddr_reg:x8; val_offset:4611*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4611*FLEN/8, x10, x3, x5)
RVTEST_SIGBASE(x3,signature_x3_12)

inst_1560:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1ad and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0f1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2c3 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31ad; op2val:0xc4f1;
op3val:0x3ac3; valaddr_reg:x8; val_offset:4614*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4614*FLEN/8, x10, x3, x5)

inst_1561:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1ad and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0f1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2c3 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31ad; op2val:0xc4f1;
op3val:0x3ac3; valaddr_reg:x8; val_offset:4617*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4617*FLEN/8, x10, x3, x5)

inst_1562:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1ad and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0f1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2c3 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31ad; op2val:0xc4f1;
op3val:0x3ac3; valaddr_reg:x8; val_offset:4620*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4620*FLEN/8, x10, x3, x5)

inst_1563:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1ad and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0f1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2c3 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31ad; op2val:0xc4f1;
op3val:0x3ac3; valaddr_reg:x8; val_offset:4623*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4623*FLEN/8, x10, x3, x5)

inst_1564:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x1ad and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0f1 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2c3 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x31ad; op2val:0xc4f1;
op3val:0x3ac3; valaddr_reg:x8; val_offset:4626*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4626*FLEN/8, x10, x3, x5)

inst_1565:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2dc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x303 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1c3 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3adc; op2val:0xbb03;
op3val:0x39c3; valaddr_reg:x8; val_offset:4629*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4629*FLEN/8, x10, x3, x5)

inst_1566:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2dc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x303 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1c3 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3adc; op2val:0xbb03;
op3val:0x39c3; valaddr_reg:x8; val_offset:4632*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4632*FLEN/8, x10, x3, x5)

inst_1567:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2dc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x303 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1c3 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3adc; op2val:0xbb03;
op3val:0x39c3; valaddr_reg:x8; val_offset:4635*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4635*FLEN/8, x10, x3, x5)

inst_1568:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2dc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x303 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1c3 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3adc; op2val:0xbb03;
op3val:0x39c3; valaddr_reg:x8; val_offset:4638*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4638*FLEN/8, x10, x3, x5)

inst_1569:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2dc and fs2 == 1 and fe2 == 0x0e and fm2 == 0x303 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1c3 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3adc; op2val:0xbb03;
op3val:0x39c3; valaddr_reg:x8; val_offset:4641*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4641*FLEN/8, x10, x3, x5)

inst_1570:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x27d and fs2 == 1 and fe2 == 0x11 and fm2 == 0x277 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e7d; op2val:0xc677;
op3val:0x38ff; valaddr_reg:x8; val_offset:4644*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4644*FLEN/8, x10, x3, x5)

inst_1571:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x27d and fs2 == 1 and fe2 == 0x11 and fm2 == 0x277 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0ff and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e7d; op2val:0xc677;
op3val:0x38ff; valaddr_reg:x8; val_offset:4647*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4647*FLEN/8, x10, x3, x5)

inst_1572:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x27d and fs2 == 1 and fe2 == 0x11 and fm2 == 0x277 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0ff and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e7d; op2val:0xc677;
op3val:0x38ff; valaddr_reg:x8; val_offset:4650*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4650*FLEN/8, x10, x3, x5)

inst_1573:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x27d and fs2 == 1 and fe2 == 0x11 and fm2 == 0x277 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0ff and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e7d; op2val:0xc677;
op3val:0x38ff; valaddr_reg:x8; val_offset:4653*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4653*FLEN/8, x10, x3, x5)

inst_1574:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x27d and fs2 == 1 and fe2 == 0x11 and fm2 == 0x277 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0ff and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2e7d; op2val:0xc677;
op3val:0x38ff; valaddr_reg:x8; val_offset:4656*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4656*FLEN/8, x10, x3, x5)

inst_1575:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x096 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x13d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1c2 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3896; op2val:0xbd3d;
op3val:0x39c2; valaddr_reg:x8; val_offset:4659*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4659*FLEN/8, x10, x3, x5)

inst_1576:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x096 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x13d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1c2 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3896; op2val:0xbd3d;
op3val:0x39c2; valaddr_reg:x8; val_offset:4662*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4662*FLEN/8, x10, x3, x5)

inst_1577:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x096 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x13d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1c2 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3896; op2val:0xbd3d;
op3val:0x39c2; valaddr_reg:x8; val_offset:4665*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4665*FLEN/8, x10, x3, x5)

inst_1578:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x096 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x13d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1c2 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3896; op2val:0xbd3d;
op3val:0x39c2; valaddr_reg:x8; val_offset:4668*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4668*FLEN/8, x10, x3, x5)

inst_1579:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x096 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x13d and fs3 == 0 and fe3 == 0x0e and fm3 == 0x1c2 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3896; op2val:0xbd3d;
op3val:0x39c2; valaddr_reg:x8; val_offset:4671*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4671*FLEN/8, x10, x3, x5)

inst_1580:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x134 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x093 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6b; op2val:0xb934;
op3val:0x3893; valaddr_reg:x8; val_offset:4674*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4674*FLEN/8, x10, x3, x5)

inst_1581:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x134 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x093 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6b; op2val:0xb934;
op3val:0x3893; valaddr_reg:x8; val_offset:4677*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4677*FLEN/8, x10, x3, x5)

inst_1582:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x134 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x093 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6b; op2val:0xb934;
op3val:0x3893; valaddr_reg:x8; val_offset:4680*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4680*FLEN/8, x10, x3, x5)

inst_1583:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x134 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x093 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6b; op2val:0xb934;
op3val:0x3893; valaddr_reg:x8; val_offset:4683*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4683*FLEN/8, x10, x3, x5)

inst_1584:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x36b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x134 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x093 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b6b; op2val:0xb934;
op3val:0x3893; valaddr_reg:x8; val_offset:4686*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4686*FLEN/8, x10, x3, x5)

inst_1585:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x026 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x173 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x168 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3826; op2val:0xbd73;
op3val:0x3968; valaddr_reg:x8; val_offset:4689*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4689*FLEN/8, x10, x3, x5)

inst_1586:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x026 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x173 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x168 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3826; op2val:0xbd73;
op3val:0x3968; valaddr_reg:x8; val_offset:4692*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4692*FLEN/8, x10, x3, x5)

inst_1587:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x026 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x173 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x168 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3826; op2val:0xbd73;
op3val:0x3968; valaddr_reg:x8; val_offset:4695*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4695*FLEN/8, x10, x3, x5)

inst_1588:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x026 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x173 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x168 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3826; op2val:0xbd73;
op3val:0x3968; valaddr_reg:x8; val_offset:4698*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4698*FLEN/8, x10, x3, x5)

inst_1589:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x026 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x173 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x168 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3826; op2val:0xbd73;
op3val:0x3968; valaddr_reg:x8; val_offset:4701*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4701*FLEN/8, x10, x3, x5)

inst_1590:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ac and fs2 == 1 and fe2 == 0x10 and fm2 == 0x101 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x199 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ac; op2val:0xc101;
op3val:0x3999; valaddr_reg:x8; val_offset:4704*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4704*FLEN/8, x10, x3, x5)

inst_1591:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ac and fs2 == 1 and fe2 == 0x10 and fm2 == 0x101 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x199 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ac; op2val:0xc101;
op3val:0x3999; valaddr_reg:x8; val_offset:4707*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4707*FLEN/8, x10, x3, x5)

inst_1592:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ac and fs2 == 1 and fe2 == 0x10 and fm2 == 0x101 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x199 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ac; op2val:0xc101;
op3val:0x3999; valaddr_reg:x8; val_offset:4710*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4710*FLEN/8, x10, x3, x5)

inst_1593:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ac and fs2 == 1 and fe2 == 0x10 and fm2 == 0x101 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x199 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ac; op2val:0xc101;
op3val:0x3999; valaddr_reg:x8; val_offset:4713*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4713*FLEN/8, x10, x3, x5)

inst_1594:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ac and fs2 == 1 and fe2 == 0x10 and fm2 == 0x101 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x199 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ac; op2val:0xc101;
op3val:0x3999; valaddr_reg:x8; val_offset:4716*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4716*FLEN/8, x10, x3, x5)

inst_1595:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x288 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e3 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x39f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2a88; op2val:0xc1e3;
op3val:0x2f9f; valaddr_reg:x8; val_offset:4719*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4719*FLEN/8, x10, x3, x5)

inst_1596:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x288 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e3 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x39f and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2a88; op2val:0xc1e3;
op3val:0x2f9f; valaddr_reg:x8; val_offset:4722*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4722*FLEN/8, x10, x3, x5)

inst_1597:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x288 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e3 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x39f and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2a88; op2val:0xc1e3;
op3val:0x2f9f; valaddr_reg:x8; val_offset:4725*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4725*FLEN/8, x10, x3, x5)

inst_1598:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x288 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e3 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x39f and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2a88; op2val:0xc1e3;
op3val:0x2f9f; valaddr_reg:x8; val_offset:4728*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4728*FLEN/8, x10, x3, x5)

inst_1599:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x288 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e3 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x39f and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2a88; op2val:0xc1e3;
op3val:0x2f9f; valaddr_reg:x8; val_offset:4731*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4731*FLEN/8, x10, x3, x5)

inst_1600:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x307 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x03f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x336 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3707; op2val:0xc03f;
op3val:0x3b36; valaddr_reg:x8; val_offset:4734*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4734*FLEN/8, x10, x3, x5)

inst_1601:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x307 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x03f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x336 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3707; op2val:0xc03f;
op3val:0x3b36; valaddr_reg:x8; val_offset:4737*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4737*FLEN/8, x10, x3, x5)

inst_1602:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x307 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x03f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x336 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3707; op2val:0xc03f;
op3val:0x3b36; valaddr_reg:x8; val_offset:4740*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4740*FLEN/8, x10, x3, x5)

inst_1603:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x307 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x03f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x336 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3707; op2val:0xc03f;
op3val:0x3b36; valaddr_reg:x8; val_offset:4743*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4743*FLEN/8, x10, x3, x5)

inst_1604:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x307 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x03f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x336 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3707; op2val:0xc03f;
op3val:0x3b36; valaddr_reg:x8; val_offset:4746*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4746*FLEN/8, x10, x3, x5)

inst_1605:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x353 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x382 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x25f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3753; op2val:0xbb82;
op3val:0x365f; valaddr_reg:x8; val_offset:4749*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4749*FLEN/8, x10, x3, x5)

inst_1606:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x353 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x382 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x25f and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3753; op2val:0xbb82;
op3val:0x365f; valaddr_reg:x8; val_offset:4752*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4752*FLEN/8, x10, x3, x5)

inst_1607:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x353 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x382 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x25f and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3753; op2val:0xbb82;
op3val:0x365f; valaddr_reg:x8; val_offset:4755*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4755*FLEN/8, x10, x3, x5)

inst_1608:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x353 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x382 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x25f and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3753; op2val:0xbb82;
op3val:0x365f; valaddr_reg:x8; val_offset:4758*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4758*FLEN/8, x10, x3, x5)

inst_1609:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x353 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x382 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x25f and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3753; op2val:0xbb82;
op3val:0x365f; valaddr_reg:x8; val_offset:4761*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4761*FLEN/8, x10, x3, x5)

inst_1610:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ec and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2b0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0b4 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ec; op2val:0xbeb0;
op3val:0x38b4; valaddr_reg:x8; val_offset:4764*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4764*FLEN/8, x10, x3, x5)

inst_1611:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ec and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2b0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0b4 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ec; op2val:0xbeb0;
op3val:0x38b4; valaddr_reg:x8; val_offset:4767*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4767*FLEN/8, x10, x3, x5)

inst_1612:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ec and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2b0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0b4 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ec; op2val:0xbeb0;
op3val:0x38b4; valaddr_reg:x8; val_offset:4770*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4770*FLEN/8, x10, x3, x5)

inst_1613:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ec and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2b0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0b4 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ec; op2val:0xbeb0;
op3val:0x38b4; valaddr_reg:x8; val_offset:4773*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4773*FLEN/8, x10, x3, x5)

inst_1614:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x1ec and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2b0 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x0b4 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x35ec; op2val:0xbeb0;
op3val:0x38b4; valaddr_reg:x8; val_offset:4776*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4776*FLEN/8, x10, x3, x5)

inst_1615:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c3 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x310 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x068 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34c3; op2val:0xb310;
op3val:0x2868; valaddr_reg:x8; val_offset:4779*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4779*FLEN/8, x10, x3, x5)

inst_1616:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c3 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x310 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x068 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34c3; op2val:0xb310;
op3val:0x2868; valaddr_reg:x8; val_offset:4782*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4782*FLEN/8, x10, x3, x5)

inst_1617:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c3 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x310 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x068 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34c3; op2val:0xb310;
op3val:0x2868; valaddr_reg:x8; val_offset:4785*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4785*FLEN/8, x10, x3, x5)

inst_1618:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c3 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x310 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x068 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34c3; op2val:0xb310;
op3val:0x2868; valaddr_reg:x8; val_offset:4788*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4788*FLEN/8, x10, x3, x5)

inst_1619:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0c3 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x310 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x068 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34c3; op2val:0xb310;
op3val:0x2868; valaddr_reg:x8; val_offset:4791*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4791*FLEN/8, x10, x3, x5)

inst_1620:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x11d and fs2 == 1 and fe2 == 0x10 and fm2 == 0x234 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3ae and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x351d; op2val:0xc234;
op3val:0x3bae; valaddr_reg:x8; val_offset:4794*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4794*FLEN/8, x10, x3, x5)

inst_1621:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x11d and fs2 == 1 and fe2 == 0x10 and fm2 == 0x234 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3ae and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x351d; op2val:0xc234;
op3val:0x3bae; valaddr_reg:x8; val_offset:4797*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4797*FLEN/8, x10, x3, x5)

inst_1622:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x11d and fs2 == 1 and fe2 == 0x10 and fm2 == 0x234 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3ae and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x351d; op2val:0xc234;
op3val:0x3bae; valaddr_reg:x8; val_offset:4800*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4800*FLEN/8, x10, x3, x5)

inst_1623:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x11d and fs2 == 1 and fe2 == 0x10 and fm2 == 0x234 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3ae and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x351d; op2val:0xc234;
op3val:0x3bae; valaddr_reg:x8; val_offset:4803*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4803*FLEN/8, x10, x3, x5)

inst_1624:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x11d and fs2 == 1 and fe2 == 0x10 and fm2 == 0x234 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3ae and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x351d; op2val:0xc234;
op3val:0x3bae; valaddr_reg:x8; val_offset:4806*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4806*FLEN/8, x10, x3, x5)

inst_1625:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x243 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x05e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x257 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3643; op2val:0xbc5e;
op3val:0x3657; valaddr_reg:x8; val_offset:4809*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4809*FLEN/8, x10, x3, x5)

inst_1626:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x243 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x05e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x257 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3643; op2val:0xbc5e;
op3val:0x3657; valaddr_reg:x8; val_offset:4812*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4812*FLEN/8, x10, x3, x5)

inst_1627:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x243 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x05e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x257 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3643; op2val:0xbc5e;
op3val:0x3657; valaddr_reg:x8; val_offset:4815*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4815*FLEN/8, x10, x3, x5)

inst_1628:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x243 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x05e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x257 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3643; op2val:0xbc5e;
op3val:0x3657; valaddr_reg:x8; val_offset:4818*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4818*FLEN/8, x10, x3, x5)

inst_1629:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x243 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x05e and fs3 == 0 and fe3 == 0x0d and fm3 == 0x257 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3643; op2val:0xbc5e;
op3val:0x3657; valaddr_reg:x8; val_offset:4821*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4821*FLEN/8, x10, x3, x5)

inst_1630:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x026 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1d4 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x378c; op2val:0xb426;
op3val:0x2dd4; valaddr_reg:x8; val_offset:4824*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4824*FLEN/8, x10, x3, x5)

inst_1631:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x026 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1d4 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x378c; op2val:0xb426;
op3val:0x2dd4; valaddr_reg:x8; val_offset:4827*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4827*FLEN/8, x10, x3, x5)

inst_1632:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x026 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1d4 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x378c; op2val:0xb426;
op3val:0x2dd4; valaddr_reg:x8; val_offset:4830*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4830*FLEN/8, x10, x3, x5)

inst_1633:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x026 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1d4 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x378c; op2val:0xb426;
op3val:0x2dd4; valaddr_reg:x8; val_offset:4833*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4833*FLEN/8, x10, x3, x5)

inst_1634:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x38c and fs2 == 1 and fe2 == 0x0d and fm2 == 0x026 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1d4 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x378c; op2val:0xb426;
op3val:0x2dd4; valaddr_reg:x8; val_offset:4836*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4836*FLEN/8, x10, x3, x5)

inst_1635:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x398 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x046 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3dd and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b98; op2val:0xbc46;
op3val:0x3bdd; valaddr_reg:x8; val_offset:4839*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4839*FLEN/8, x10, x3, x5)

inst_1636:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x398 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x046 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3dd and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b98; op2val:0xbc46;
op3val:0x3bdd; valaddr_reg:x8; val_offset:4842*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4842*FLEN/8, x10, x3, x5)

inst_1637:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x398 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x046 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3dd and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b98; op2val:0xbc46;
op3val:0x3bdd; valaddr_reg:x8; val_offset:4845*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4845*FLEN/8, x10, x3, x5)

inst_1638:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x398 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x046 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3dd and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b98; op2val:0xbc46;
op3val:0x3bdd; valaddr_reg:x8; val_offset:4848*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4848*FLEN/8, x10, x3, x5)

inst_1639:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x398 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x046 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x3dd and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b98; op2val:0xbc46;
op3val:0x3bdd; valaddr_reg:x8; val_offset:4851*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4851*FLEN/8, x10, x3, x5)

inst_1640:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ce and fs2 == 1 and fe2 == 0x10 and fm2 == 0x238 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x338 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ce; op2val:0xc238;
op3val:0x3b38; valaddr_reg:x8; val_offset:4854*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4854*FLEN/8, x10, x3, x5)

inst_1641:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ce and fs2 == 1 and fe2 == 0x10 and fm2 == 0x238 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x338 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ce; op2val:0xc238;
op3val:0x3b38; valaddr_reg:x8; val_offset:4857*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4857*FLEN/8, x10, x3, x5)

inst_1642:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ce and fs2 == 1 and fe2 == 0x10 and fm2 == 0x238 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x338 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ce; op2val:0xc238;
op3val:0x3b38; valaddr_reg:x8; val_offset:4860*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4860*FLEN/8, x10, x3, x5)

inst_1643:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ce and fs2 == 1 and fe2 == 0x10 and fm2 == 0x238 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x338 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ce; op2val:0xc238;
op3val:0x3b38; valaddr_reg:x8; val_offset:4863*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4863*FLEN/8, x10, x3, x5)

inst_1644:
// fs1 == 0 and fe1 == 0x0d and fm1 == 0x0ce and fs2 == 1 and fe2 == 0x10 and fm2 == 0x238 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x338 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x34ce; op2val:0xc238;
op3val:0x3b38; valaddr_reg:x8; val_offset:4866*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4866*FLEN/8, x10, x3, x5)

inst_1645:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x0d and fm2 == 0x06b and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2a9 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aef; op2val:0xb46b;
op3val:0x32a9; valaddr_reg:x8; val_offset:4869*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4869*FLEN/8, x10, x3, x5)

inst_1646:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x0d and fm2 == 0x06b and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2a9 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aef; op2val:0xb46b;
op3val:0x32a9; valaddr_reg:x8; val_offset:4872*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4872*FLEN/8, x10, x3, x5)

inst_1647:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x0d and fm2 == 0x06b and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2a9 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aef; op2val:0xb46b;
op3val:0x32a9; valaddr_reg:x8; val_offset:4875*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4875*FLEN/8, x10, x3, x5)

inst_1648:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x0d and fm2 == 0x06b and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2a9 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aef; op2val:0xb46b;
op3val:0x32a9; valaddr_reg:x8; val_offset:4878*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4878*FLEN/8, x10, x3, x5)

inst_1649:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x0d and fm2 == 0x06b and fs3 == 0 and fe3 == 0x0c and fm3 == 0x2a9 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3aef; op2val:0xb46b;
op3val:0x32a9; valaddr_reg:x8; val_offset:4881*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4881*FLEN/8, x10, x3, x5)

inst_1650:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x132 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x052 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x09e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3932; op2val:0xb452;
op3val:0x309e; valaddr_reg:x8; val_offset:4884*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4884*FLEN/8, x10, x3, x5)

inst_1651:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x132 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x052 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x09e and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3932; op2val:0xb452;
op3val:0x309e; valaddr_reg:x8; val_offset:4887*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4887*FLEN/8, x10, x3, x5)

inst_1652:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x132 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x052 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x09e and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3932; op2val:0xb452;
op3val:0x309e; valaddr_reg:x8; val_offset:4890*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4890*FLEN/8, x10, x3, x5)

inst_1653:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x132 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x052 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x09e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3932; op2val:0xb452;
op3val:0x309e; valaddr_reg:x8; val_offset:4893*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4893*FLEN/8, x10, x3, x5)

inst_1654:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x132 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x052 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x09e and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3932; op2val:0xb452;
op3val:0x309e; valaddr_reg:x8; val_offset:4896*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4896*FLEN/8, x10, x3, x5)

inst_1655:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x32c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2f2 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1ba and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x332c; op2val:0xbef2;
op3val:0x35ba; valaddr_reg:x8; val_offset:4899*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4899*FLEN/8, x10, x3, x5)

inst_1656:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x32c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2f2 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1ba and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x332c; op2val:0xbef2;
op3val:0x35ba; valaddr_reg:x8; val_offset:4902*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4902*FLEN/8, x10, x3, x5)

inst_1657:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x32c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2f2 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1ba and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x332c; op2val:0xbef2;
op3val:0x35ba; valaddr_reg:x8; val_offset:4905*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4905*FLEN/8, x10, x3, x5)

inst_1658:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x32c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2f2 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1ba and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x332c; op2val:0xbef2;
op3val:0x35ba; valaddr_reg:x8; val_offset:4908*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4908*FLEN/8, x10, x3, x5)

inst_1659:
// fs1 == 0 and fe1 == 0x0c and fm1 == 0x32c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2f2 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1ba and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x332c; op2val:0xbef2;
op3val:0x35ba; valaddr_reg:x8; val_offset:4911*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4911*FLEN/8, x10, x3, x5)

inst_1660:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x138 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1d5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x35c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3938; op2val:0xbdd5;
op3val:0x3b5c; valaddr_reg:x8; val_offset:4914*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4914*FLEN/8, x10, x3, x5)

inst_1661:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x138 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1d5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x35c and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3938; op2val:0xbdd5;
op3val:0x3b5c; valaddr_reg:x8; val_offset:4917*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4917*FLEN/8, x10, x3, x5)

inst_1662:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x138 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1d5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x35c and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3938; op2val:0xbdd5;
op3val:0x3b5c; valaddr_reg:x8; val_offset:4920*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4920*FLEN/8, x10, x3, x5)

inst_1663:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x138 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1d5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x35c and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3938; op2val:0xbdd5;
op3val:0x3b5c; valaddr_reg:x8; val_offset:4923*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4923*FLEN/8, x10, x3, x5)

inst_1664:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x138 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1d5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x35c and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3938; op2val:0xbdd5;
op3val:0x3b5c; valaddr_reg:x8; val_offset:4926*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4926*FLEN/8, x10, x3, x5)

inst_1665:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2f7 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2e6 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x102 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2af7; op2val:0xc2e6;
op3val:0x3102; valaddr_reg:x8; val_offset:4929*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4929*FLEN/8, x10, x3, x5)

inst_1666:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2f7 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2e6 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x102 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2af7; op2val:0xc2e6;
op3val:0x3102; valaddr_reg:x8; val_offset:4932*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4932*FLEN/8, x10, x3, x5)

inst_1667:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2f7 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2e6 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x102 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2af7; op2val:0xc2e6;
op3val:0x3102; valaddr_reg:x8; val_offset:4935*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4935*FLEN/8, x10, x3, x5)

inst_1668:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2f7 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2e6 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x102 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2af7; op2val:0xc2e6;
op3val:0x3102; valaddr_reg:x8; val_offset:4938*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4938*FLEN/8, x10, x3, x5)

inst_1669:
// fs1 == 0 and fe1 == 0x0a and fm1 == 0x2f7 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2e6 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x102 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2af7; op2val:0xc2e6;
op3val:0x3102; valaddr_reg:x8; val_offset:4941*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4941*FLEN/8, x10, x3, x5)

inst_1670:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x320 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0d5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x00e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f20; op2val:0xc4d5;
op3val:0x380e; valaddr_reg:x8; val_offset:4944*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4944*FLEN/8, x10, x3, x5)

inst_1671:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x320 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0d5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x00e and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f20; op2val:0xc4d5;
op3val:0x380e; valaddr_reg:x8; val_offset:4947*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4947*FLEN/8, x10, x3, x5)

inst_1672:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x320 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0d5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x00e and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f20; op2val:0xc4d5;
op3val:0x380e; valaddr_reg:x8; val_offset:4950*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4950*FLEN/8, x10, x3, x5)

inst_1673:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x320 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0d5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x00e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f20; op2val:0xc4d5;
op3val:0x380e; valaddr_reg:x8; val_offset:4953*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4953*FLEN/8, x10, x3, x5)

inst_1674:
// fs1 == 0 and fe1 == 0x0b and fm1 == 0x320 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x0d5 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x00e and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x2f20; op2val:0xc4d5;
op3val:0x380e; valaddr_reg:x8; val_offset:4956*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4956*FLEN/8, x10, x3, x5)

inst_1675:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0a6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x245 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39d2; op2val:0xb8a6;
op3val:0x3645; valaddr_reg:x8; val_offset:4959*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4959*FLEN/8, x10, x3, x5)

inst_1676:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0a6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x245 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39d2; op2val:0xb8a6;
op3val:0x3645; valaddr_reg:x8; val_offset:4962*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4962*FLEN/8, x10, x3, x5)

inst_1677:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0a6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x245 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39d2; op2val:0xb8a6;
op3val:0x3645; valaddr_reg:x8; val_offset:4965*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4965*FLEN/8, x10, x3, x5)

inst_1678:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0a6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x245 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39d2; op2val:0xb8a6;
op3val:0x3645; valaddr_reg:x8; val_offset:4968*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4968*FLEN/8, x10, x3, x5)

inst_1679:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x1d2 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0a6 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x245 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x39d2; op2val:0xb8a6;
op3val:0x3645; valaddr_reg:x8; val_offset:4971*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4971*FLEN/8, x10, x3, x5)

inst_1680:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x22f and fs2 == 1 and fe2 == 0x0a and fm2 == 0x23d and fs3 == 0 and fe3 == 0x0a and fm3 == 0x0d3 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a2f; op2val:0xaa3d;
op3val:0x28d3; valaddr_reg:x8; val_offset:4974*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4974*FLEN/8, x10, x3, x5)

inst_1681:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x22f and fs2 == 1 and fe2 == 0x0a and fm2 == 0x23d and fs3 == 0 and fe3 == 0x0a and fm3 == 0x0d3 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a2f; op2val:0xaa3d;
op3val:0x28d3; valaddr_reg:x8; val_offset:4977*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4977*FLEN/8, x10, x3, x5)

inst_1682:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x22f and fs2 == 1 and fe2 == 0x0a and fm2 == 0x23d and fs3 == 0 and fe3 == 0x0a and fm3 == 0x0d3 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a2f; op2val:0xaa3d;
op3val:0x28d3; valaddr_reg:x8; val_offset:4980*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4980*FLEN/8, x10, x3, x5)

inst_1683:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x22f and fs2 == 1 and fe2 == 0x0a and fm2 == 0x23d and fs3 == 0 and fe3 == 0x0a and fm3 == 0x0d3 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3a2f; op2val:0xaa3d;
op3val:0x28d3; valaddr_reg:x8; val_offset:4983*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4983*FLEN/8, x10, x3, x5)

inst_1684:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fd and fs2 == 1 and fe2 == 0x0d and fm2 == 0x167 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0b9 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3afd; op2val:0xb567;
op3val:0x34b9; valaddr_reg:x8; val_offset:4986*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 4986*FLEN/8, x10, x3, x5)

inst_1685:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fd and fs2 == 1 and fe2 == 0x0d and fm2 == 0x167 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0b9 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3afd; op2val:0xb567;
op3val:0x34b9; valaddr_reg:x8; val_offset:4989*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 4989*FLEN/8, x10, x3, x5)

inst_1686:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fd and fs2 == 1 and fe2 == 0x0d and fm2 == 0x167 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0b9 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3afd; op2val:0xb567;
op3val:0x34b9; valaddr_reg:x8; val_offset:4992*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 64, 0, x8, 4992*FLEN/8, x10, x3, x5)

inst_1687:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fd and fs2 == 1 and fe2 == 0x0d and fm2 == 0x167 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0b9 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3afd; op2val:0xb567;
op3val:0x34b9; valaddr_reg:x8; val_offset:4995*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 96, 0, x8, 4995*FLEN/8, x10, x3, x5)
RVTEST_SIGBASE(x3,signature_x3_13)

inst_1688:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x2fd and fs2 == 1 and fe2 == 0x0d and fm2 == 0x167 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0b9 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3afd; op2val:0xb567;
op3val:0x34b9; valaddr_reg:x8; val_offset:4998*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 128, 0, x8, 4998*FLEN/8, x10, x3, x5)

inst_1689:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x351 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x294 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x205 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b51; op2val:0xba94;
op3val:0x3a05; valaddr_reg:x8; val_offset:5001*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 0, 0, x8, 5001*FLEN/8, x10, x3, x5)

inst_1690:
// fs1 == 0 and fe1 == 0x0e and fm1 == 0x351 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x294 and fs3 == 0 and fe3 == 0x0e and fm3 == 0x205 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0xffff and rs3_sgn_prefix == 0x0000  
/* opcode: fnmsub.h ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x3b51; op2val:0xba94;
op3val:0x3a05; valaddr_reg:x8; val_offset:5004*FLEN/8; rmval:dyn;
testreg:x5; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.h, x31, x30, x29, x28, dyn, 32, 0, x8, 5004*FLEN/8, x10, x3, x5)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(14895,32,FLEN)
NAN_BOXED(14895,16,FLEN)
NAN_BOXED(10451,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(43581,16,FLEN)
NAN_BOXED(10451,32,FLEN)
NAN_BOXED(14895,32,FLEN)
NAN_BOXED(43581,16,FLEN)
NAN_BOXED(10451,32,FLEN)
NAN_BOXED(14895,32,FLEN)
NAN_BOXED(43581,16,FLEN)
NAN_BOXED(14895,32,FLEN)
NAN_BOXED(14895,32,FLEN)
NAN_BOXED(14895,16,FLEN)
NAN_BOXED(14895,32,FLEN)
NAN_BOXED(15101,32,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(13497,32,FLEN)
NAN_BOXED(15101,32,FLEN)
NAN_BOXED(46439,16,FLEN)
NAN_BOXED(46439,32,FLEN)
NAN_BOXED(15101,32,FLEN)
NAN_BOXED(46439,16,FLEN)
NAN_BOXED(15101,32,FLEN)
NAN_BOXED(15101,32,FLEN)
NAN_BOXED(15101,16,FLEN)
NAN_BOXED(15101,32,FLEN)
NAN_BOXED(15101,32,FLEN)
NAN_BOXED(15101,16,FLEN)
NAN_BOXED(13497,32,FLEN)
NAN_BOXED(15185,32,FLEN)
NAN_BOXED(47764,16,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(15185,32,FLEN)
NAN_BOXED(47764,16,FLEN)
NAN_BOXED(47764,32,FLEN)
test_dataset_1:
NAN_BOXED(15185,32,FLEN)
NAN_BOXED(47764,16,FLEN)
NAN_BOXED(14853,32,FLEN)
NAN_BOXED(15185,32,FLEN)
NAN_BOXED(47764,16,FLEN)
NAN_BOXED(14853,32,FLEN)
NAN_BOXED(15185,32,FLEN)
NAN_BOXED(47764,16,FLEN)
NAN_BOXED(14853,32,FLEN)
NAN_BOXED(4899,32,FLEN)
NAN_BOXED(58134,16,FLEN)
NAN_BOXED(14931,32,FLEN)
NAN_BOXED(4899,32,FLEN)
NAN_BOXED(58134,16,FLEN)
NAN_BOXED(14931,32,FLEN)
NAN_BOXED(4899,32,FLEN)
NAN_BOXED(58134,16,FLEN)
NAN_BOXED(14931,32,FLEN)
NAN_BOXED(4899,32,FLEN)
NAN_BOXED(58134,16,FLEN)
NAN_BOXED(14931,32,FLEN)
NAN_BOXED(4899,32,FLEN)
NAN_BOXED(58134,16,FLEN)
NAN_BOXED(14931,32,FLEN)
NAN_BOXED(13754,32,FLEN)
NAN_BOXED(48650,16,FLEN)
NAN_BOXED(14419,32,FLEN)
NAN_BOXED(13754,32,FLEN)
NAN_BOXED(48650,16,FLEN)
NAN_BOXED(14419,32,FLEN)
test_dataset_2:
NAN_BOXED(13754,16,FLEN)
NAN_BOXED(48650,16,FLEN)
NAN_BOXED(14419,16,FLEN)
NAN_BOXED(13754,16,FLEN)
NAN_BOXED(48650,16,FLEN)
NAN_BOXED(14419,16,FLEN)
NAN_BOXED(13754,16,FLEN)
NAN_BOXED(48650,16,FLEN)
NAN_BOXED(14419,16,FLEN)
NAN_BOXED(14431,16,FLEN)
NAN_BOXED(47971,16,FLEN)
NAN_BOXED(14346,16,FLEN)
NAN_BOXED(14431,16,FLEN)
NAN_BOXED(47971,16,FLEN)
NAN_BOXED(14346,16,FLEN)
NAN_BOXED(14431,16,FLEN)
NAN_BOXED(47971,16,FLEN)
NAN_BOXED(14346,16,FLEN)
NAN_BOXED(14431,16,FLEN)
NAN_BOXED(47971,16,FLEN)
NAN_BOXED(14346,16,FLEN)
NAN_BOXED(14431,16,FLEN)
NAN_BOXED(47971,16,FLEN)
NAN_BOXED(14346,16,FLEN)
NAN_BOXED(14966,16,FLEN)
NAN_BOXED(45750,16,FLEN)
NAN_BOXED(12652,16,FLEN)
NAN_BOXED(14966,16,FLEN)
NAN_BOXED(45750,16,FLEN)
NAN_BOXED(12652,16,FLEN)
NAN_BOXED(14966,16,FLEN)
NAN_BOXED(45750,16,FLEN)
NAN_BOXED(12652,16,FLEN)
NAN_BOXED(14966,16,FLEN)
NAN_BOXED(45750,16,FLEN)
NAN_BOXED(12652,16,FLEN)
NAN_BOXED(14966,16,FLEN)
NAN_BOXED(45750,16,FLEN)
NAN_BOXED(12652,16,FLEN)
NAN_BOXED(15176,16,FLEN)
NAN_BOXED(47802,16,FLEN)
NAN_BOXED(14880,16,FLEN)
NAN_BOXED(15176,16,FLEN)
NAN_BOXED(47802,16,FLEN)
NAN_BOXED(14880,16,FLEN)
NAN_BOXED(15176,16,FLEN)
NAN_BOXED(47802,16,FLEN)
NAN_BOXED(14880,16,FLEN)
NAN_BOXED(15176,16,FLEN)
NAN_BOXED(47802,16,FLEN)
NAN_BOXED(14880,16,FLEN)
NAN_BOXED(15176,16,FLEN)
NAN_BOXED(47802,16,FLEN)
NAN_BOXED(14880,16,FLEN)
NAN_BOXED(15319,16,FLEN)
NAN_BOXED(47612,16,FLEN)
NAN_BOXED(14813,16,FLEN)
NAN_BOXED(15319,16,FLEN)
NAN_BOXED(47612,16,FLEN)
NAN_BOXED(14813,16,FLEN)
NAN_BOXED(15319,16,FLEN)
NAN_BOXED(47612,16,FLEN)
NAN_BOXED(14813,16,FLEN)
NAN_BOXED(15319,16,FLEN)
NAN_BOXED(47612,16,FLEN)
NAN_BOXED(14813,16,FLEN)
NAN_BOXED(15319,16,FLEN)
NAN_BOXED(47612,16,FLEN)
NAN_BOXED(14813,16,FLEN)
NAN_BOXED(14525,16,FLEN)
NAN_BOXED(45386,16,FLEN)
NAN_BOXED(11844,16,FLEN)
NAN_BOXED(14525,16,FLEN)
NAN_BOXED(45386,16,FLEN)
NAN_BOXED(11844,16,FLEN)
NAN_BOXED(14525,16,FLEN)
NAN_BOXED(45386,16,FLEN)
NAN_BOXED(11844,16,FLEN)
NAN_BOXED(14525,16,FLEN)
NAN_BOXED(45386,16,FLEN)
NAN_BOXED(11844,16,FLEN)
NAN_BOXED(14525,16,FLEN)
NAN_BOXED(45386,16,FLEN)
NAN_BOXED(11844,16,FLEN)
NAN_BOXED(14583,16,FLEN)
NAN_BOXED(48565,16,FLEN)
NAN_BOXED(15127,16,FLEN)
NAN_BOXED(14583,16,FLEN)
NAN_BOXED(48565,16,FLEN)
NAN_BOXED(15127,16,FLEN)
NAN_BOXED(14583,16,FLEN)
NAN_BOXED(48565,16,FLEN)
NAN_BOXED(15127,16,FLEN)
NAN_BOXED(14583,16,FLEN)
NAN_BOXED(48565,16,FLEN)
NAN_BOXED(15127,16,FLEN)
NAN_BOXED(14583,16,FLEN)
NAN_BOXED(48565,16,FLEN)
NAN_BOXED(15127,16,FLEN)
NAN_BOXED(14830,16,FLEN)
NAN_BOXED(41420,16,FLEN)
NAN_BOXED(8268,16,FLEN)
NAN_BOXED(14830,16,FLEN)
NAN_BOXED(41420,16,FLEN)
NAN_BOXED(8268,16,FLEN)
NAN_BOXED(14830,16,FLEN)
NAN_BOXED(41420,16,FLEN)
NAN_BOXED(8268,16,FLEN)
NAN_BOXED(14830,16,FLEN)
NAN_BOXED(41420,16,FLEN)
NAN_BOXED(8268,16,FLEN)
NAN_BOXED(14830,16,FLEN)
NAN_BOXED(41420,16,FLEN)
NAN_BOXED(8268,16,FLEN)
NAN_BOXED(15230,16,FLEN)
NAN_BOXED(46716,16,FLEN)
NAN_BOXED(13843,16,FLEN)
NAN_BOXED(15230,16,FLEN)
NAN_BOXED(46716,16,FLEN)
NAN_BOXED(13843,16,FLEN)
NAN_BOXED(15230,16,FLEN)
NAN_BOXED(46716,16,FLEN)
NAN_BOXED(13843,16,FLEN)
NAN_BOXED(15230,16,FLEN)
NAN_BOXED(46716,16,FLEN)
NAN_BOXED(13843,16,FLEN)
NAN_BOXED(15230,16,FLEN)
NAN_BOXED(46716,16,FLEN)
NAN_BOXED(13843,16,FLEN)
NAN_BOXED(14587,16,FLEN)
NAN_BOXED(47195,16,FLEN)
NAN_BOXED(13677,16,FLEN)
NAN_BOXED(14587,16,FLEN)
NAN_BOXED(47195,16,FLEN)
NAN_BOXED(13677,16,FLEN)
NAN_BOXED(14587,16,FLEN)
NAN_BOXED(47195,16,FLEN)
NAN_BOXED(13677,16,FLEN)
NAN_BOXED(14587,16,FLEN)
NAN_BOXED(47195,16,FLEN)
NAN_BOXED(13677,16,FLEN)
NAN_BOXED(14587,16,FLEN)
NAN_BOXED(47195,16,FLEN)
NAN_BOXED(13677,16,FLEN)
NAN_BOXED(14666,16,FLEN)
NAN_BOXED(46967,16,FLEN)
NAN_BOXED(13552,16,FLEN)
NAN_BOXED(14666,16,FLEN)
NAN_BOXED(46967,16,FLEN)
NAN_BOXED(13552,16,FLEN)
NAN_BOXED(14666,16,FLEN)
NAN_BOXED(46967,16,FLEN)
NAN_BOXED(13552,16,FLEN)
NAN_BOXED(14666,16,FLEN)
NAN_BOXED(46967,16,FLEN)
NAN_BOXED(13552,16,FLEN)
NAN_BOXED(14666,16,FLEN)
NAN_BOXED(46967,16,FLEN)
NAN_BOXED(13552,16,FLEN)
NAN_BOXED(14340,16,FLEN)
NAN_BOXED(47507,16,FLEN)
NAN_BOXED(13722,16,FLEN)
NAN_BOXED(14340,16,FLEN)
NAN_BOXED(47507,16,FLEN)
NAN_BOXED(13722,16,FLEN)
NAN_BOXED(14340,16,FLEN)
NAN_BOXED(47507,16,FLEN)
NAN_BOXED(13722,16,FLEN)
NAN_BOXED(14340,16,FLEN)
NAN_BOXED(47507,16,FLEN)
NAN_BOXED(13722,16,FLEN)
NAN_BOXED(14340,16,FLEN)
NAN_BOXED(47507,16,FLEN)
NAN_BOXED(13722,16,FLEN)
NAN_BOXED(11855,16,FLEN)
NAN_BOXED(50238,16,FLEN)
NAN_BOXED(14002,16,FLEN)
NAN_BOXED(11855,16,FLEN)
NAN_BOXED(50238,16,FLEN)
NAN_BOXED(14002,16,FLEN)
NAN_BOXED(11855,16,FLEN)
NAN_BOXED(50238,16,FLEN)
NAN_BOXED(14002,16,FLEN)
NAN_BOXED(11855,16,FLEN)
NAN_BOXED(50238,16,FLEN)
NAN_BOXED(14002,16,FLEN)
NAN_BOXED(11855,16,FLEN)
NAN_BOXED(50238,16,FLEN)
NAN_BOXED(14002,16,FLEN)
NAN_BOXED(15068,16,FLEN)
NAN_BOXED(48220,16,FLEN)
NAN_BOXED(15228,16,FLEN)
NAN_BOXED(15068,16,FLEN)
NAN_BOXED(48220,16,FLEN)
NAN_BOXED(15228,16,FLEN)
NAN_BOXED(15068,16,FLEN)
NAN_BOXED(48220,16,FLEN)
NAN_BOXED(15228,16,FLEN)
NAN_BOXED(15068,16,FLEN)
NAN_BOXED(48220,16,FLEN)
NAN_BOXED(15228,16,FLEN)
NAN_BOXED(15068,16,FLEN)
NAN_BOXED(48220,16,FLEN)
NAN_BOXED(15228,16,FLEN)
NAN_BOXED(10983,16,FLEN)
NAN_BOXED(51389,16,FLEN)
NAN_BOXED(14359,16,FLEN)
NAN_BOXED(10983,16,FLEN)
NAN_BOXED(51389,16,FLEN)
NAN_BOXED(14359,16,FLEN)
NAN_BOXED(10983,16,FLEN)
NAN_BOXED(51389,16,FLEN)
NAN_BOXED(14359,16,FLEN)
NAN_BOXED(10983,16,FLEN)
NAN_BOXED(51389,16,FLEN)
NAN_BOXED(14359,16,FLEN)
NAN_BOXED(10983,16,FLEN)
NAN_BOXED(51389,16,FLEN)
NAN_BOXED(14359,16,FLEN)
NAN_BOXED(14962,16,FLEN)
NAN_BOXED(44104,16,FLEN)
NAN_BOXED(10984,16,FLEN)
NAN_BOXED(14962,16,FLEN)
NAN_BOXED(44104,16,FLEN)
NAN_BOXED(10984,16,FLEN)
NAN_BOXED(14962,16,FLEN)
NAN_BOXED(44104,16,FLEN)
NAN_BOXED(10984,16,FLEN)
NAN_BOXED(14962,16,FLEN)
NAN_BOXED(44104,16,FLEN)
NAN_BOXED(10984,16,FLEN)
NAN_BOXED(14962,16,FLEN)
NAN_BOXED(44104,16,FLEN)
NAN_BOXED(10984,16,FLEN)
NAN_BOXED(14012,16,FLEN)
NAN_BOXED(47398,16,FLEN)
NAN_BOXED(13398,16,FLEN)
NAN_BOXED(14012,16,FLEN)
NAN_BOXED(47398,16,FLEN)
NAN_BOXED(13398,16,FLEN)
NAN_BOXED(14012,16,FLEN)
NAN_BOXED(47398,16,FLEN)
NAN_BOXED(13398,16,FLEN)
NAN_BOXED(14012,16,FLEN)
NAN_BOXED(47398,16,FLEN)
NAN_BOXED(13398,16,FLEN)
NAN_BOXED(14012,16,FLEN)
NAN_BOXED(47398,16,FLEN)
NAN_BOXED(13398,16,FLEN)
NAN_BOXED(12190,16,FLEN)
NAN_BOXED(50688,16,FLEN)
NAN_BOXED(14774,16,FLEN)
NAN_BOXED(12190,16,FLEN)
NAN_BOXED(50688,16,FLEN)
NAN_BOXED(14774,16,FLEN)
NAN_BOXED(12190,16,FLEN)
NAN_BOXED(50688,16,FLEN)
NAN_BOXED(14774,16,FLEN)
NAN_BOXED(12190,16,FLEN)
NAN_BOXED(50688,16,FLEN)
NAN_BOXED(14774,16,FLEN)
NAN_BOXED(12190,16,FLEN)
NAN_BOXED(50688,16,FLEN)
NAN_BOXED(14774,16,FLEN)
NAN_BOXED(14629,16,FLEN)
NAN_BOXED(45584,16,FLEN)
NAN_BOXED(12237,16,FLEN)
NAN_BOXED(14629,16,FLEN)
NAN_BOXED(45584,16,FLEN)
NAN_BOXED(12237,16,FLEN)
NAN_BOXED(14629,16,FLEN)
NAN_BOXED(45584,16,FLEN)
NAN_BOXED(12237,16,FLEN)
NAN_BOXED(14629,16,FLEN)
NAN_BOXED(45584,16,FLEN)
NAN_BOXED(12237,16,FLEN)
NAN_BOXED(14629,16,FLEN)
NAN_BOXED(45584,16,FLEN)
NAN_BOXED(12237,16,FLEN)
NAN_BOXED(15083,16,FLEN)
NAN_BOXED(46172,16,FLEN)
NAN_BOXED(13194,16,FLEN)
NAN_BOXED(15083,16,FLEN)
NAN_BOXED(46172,16,FLEN)
NAN_BOXED(13194,16,FLEN)
NAN_BOXED(15083,16,FLEN)
NAN_BOXED(46172,16,FLEN)
NAN_BOXED(13194,16,FLEN)
NAN_BOXED(15083,16,FLEN)
NAN_BOXED(46172,16,FLEN)
NAN_BOXED(13194,16,FLEN)
NAN_BOXED(15083,16,FLEN)
NAN_BOXED(46172,16,FLEN)
NAN_BOXED(13194,16,FLEN)
NAN_BOXED(15160,16,FLEN)
NAN_BOXED(46462,16,FLEN)
NAN_BOXED(13557,16,FLEN)
NAN_BOXED(15160,16,FLEN)
NAN_BOXED(46462,16,FLEN)
NAN_BOXED(13557,16,FLEN)
NAN_BOXED(15160,16,FLEN)
NAN_BOXED(46462,16,FLEN)
NAN_BOXED(13557,16,FLEN)
NAN_BOXED(15160,16,FLEN)
NAN_BOXED(46462,16,FLEN)
NAN_BOXED(13557,16,FLEN)
NAN_BOXED(15160,16,FLEN)
NAN_BOXED(46462,16,FLEN)
NAN_BOXED(13557,16,FLEN)
NAN_BOXED(13508,16,FLEN)
NAN_BOXED(45407,16,FLEN)
NAN_BOXED(10854,16,FLEN)
NAN_BOXED(13508,16,FLEN)
NAN_BOXED(45407,16,FLEN)
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NAN_BOXED(14642,16,FLEN)
NAN_BOXED(46162,16,FLEN)
NAN_BOXED(12446,16,FLEN)
NAN_BOXED(14642,16,FLEN)
NAN_BOXED(46162,16,FLEN)
NAN_BOXED(12446,16,FLEN)
NAN_BOXED(13100,16,FLEN)
NAN_BOXED(48882,16,FLEN)
NAN_BOXED(13754,16,FLEN)
NAN_BOXED(13100,16,FLEN)
NAN_BOXED(48882,16,FLEN)
NAN_BOXED(13754,16,FLEN)
NAN_BOXED(13100,16,FLEN)
NAN_BOXED(48882,16,FLEN)
NAN_BOXED(13754,16,FLEN)
NAN_BOXED(13100,16,FLEN)
NAN_BOXED(48882,16,FLEN)
NAN_BOXED(13754,16,FLEN)
NAN_BOXED(13100,16,FLEN)
NAN_BOXED(48882,16,FLEN)
NAN_BOXED(13754,16,FLEN)
NAN_BOXED(14648,16,FLEN)
NAN_BOXED(48597,16,FLEN)
NAN_BOXED(15196,16,FLEN)
NAN_BOXED(14648,16,FLEN)
NAN_BOXED(48597,16,FLEN)
NAN_BOXED(15196,16,FLEN)
NAN_BOXED(14648,16,FLEN)
NAN_BOXED(48597,16,FLEN)
NAN_BOXED(15196,16,FLEN)
NAN_BOXED(14648,16,FLEN)
NAN_BOXED(48597,16,FLEN)
NAN_BOXED(15196,16,FLEN)
NAN_BOXED(14648,16,FLEN)
NAN_BOXED(48597,16,FLEN)
NAN_BOXED(15196,16,FLEN)
NAN_BOXED(10999,16,FLEN)
NAN_BOXED(49894,16,FLEN)
NAN_BOXED(12546,16,FLEN)
NAN_BOXED(10999,16,FLEN)
NAN_BOXED(49894,16,FLEN)
NAN_BOXED(12546,16,FLEN)
NAN_BOXED(10999,16,FLEN)
NAN_BOXED(49894,16,FLEN)
NAN_BOXED(12546,16,FLEN)
NAN_BOXED(10999,16,FLEN)
NAN_BOXED(49894,16,FLEN)
NAN_BOXED(12546,16,FLEN)
NAN_BOXED(10999,16,FLEN)
NAN_BOXED(49894,16,FLEN)
NAN_BOXED(12546,16,FLEN)
NAN_BOXED(12064,16,FLEN)
NAN_BOXED(50389,16,FLEN)
NAN_BOXED(14350,16,FLEN)
NAN_BOXED(12064,16,FLEN)
NAN_BOXED(50389,16,FLEN)
NAN_BOXED(14350,16,FLEN)
NAN_BOXED(12064,16,FLEN)
NAN_BOXED(50389,16,FLEN)
NAN_BOXED(14350,16,FLEN)
NAN_BOXED(12064,16,FLEN)
NAN_BOXED(50389,16,FLEN)
NAN_BOXED(14350,16,FLEN)
NAN_BOXED(12064,16,FLEN)
NAN_BOXED(50389,16,FLEN)
NAN_BOXED(14350,16,FLEN)
NAN_BOXED(14802,16,FLEN)
NAN_BOXED(47270,16,FLEN)
NAN_BOXED(13893,16,FLEN)
NAN_BOXED(14802,16,FLEN)
NAN_BOXED(47270,16,FLEN)
NAN_BOXED(13893,16,FLEN)
NAN_BOXED(14802,16,FLEN)
NAN_BOXED(47270,16,FLEN)
NAN_BOXED(13893,16,FLEN)
NAN_BOXED(14802,16,FLEN)
NAN_BOXED(47270,16,FLEN)
NAN_BOXED(13893,16,FLEN)
NAN_BOXED(14802,16,FLEN)
NAN_BOXED(47270,16,FLEN)
NAN_BOXED(13893,16,FLEN)
NAN_BOXED(14895,16,FLEN)
NAN_BOXED(43581,16,FLEN)
NAN_BOXED(10451,16,FLEN)
NAN_BOXED(14895,16,FLEN)
NAN_BOXED(43581,16,FLEN)
NAN_BOXED(10451,16,FLEN)
NAN_BOXED(14895,16,FLEN)
NAN_BOXED(43581,16,FLEN)
NAN_BOXED(10451,16,FLEN)
NAN_BOXED(14895,16,FLEN)
NAN_BOXED(43581,16,FLEN)
NAN_BOXED(10451,16,FLEN)
NAN_BOXED(15101,16,FLEN)
NAN_BOXED(46439,16,FLEN)
NAN_BOXED(13497,16,FLEN)
NAN_BOXED(15101,16,FLEN)
NAN_BOXED(46439,16,FLEN)
NAN_BOXED(13497,16,FLEN)
NAN_BOXED(15101,16,FLEN)
NAN_BOXED(46439,16,FLEN)
NAN_BOXED(13497,16,FLEN)
NAN_BOXED(15101,16,FLEN)
NAN_BOXED(46439,16,FLEN)
NAN_BOXED(13497,16,FLEN)
NAN_BOXED(15101,16,FLEN)
NAN_BOXED(46439,16,FLEN)
NAN_BOXED(13497,16,FLEN)
NAN_BOXED(15185,16,FLEN)
NAN_BOXED(47764,16,FLEN)
NAN_BOXED(14853,16,FLEN)
NAN_BOXED(15185,16,FLEN)
NAN_BOXED(47764,16,FLEN)
NAN_BOXED(14853,16,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;



signature_x4_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x4_1:
    .fill 28*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_0:
    .fill 20*((SIGALIGN)/4),4,0xdeadbeef


signature_x3_0:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x3_1:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x3_2:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x3_3:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x3_4:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x3_5:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x3_6:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x3_7:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x3_8:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x3_9:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x3_10:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x3_11:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x3_12:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x3_13:
    .fill 6*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;

mtrap_sigptr:
    .fill 64*XLEN/32,4,0xdeadbeef

tsig_end_canary:
CANARY;
#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif


sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
