
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.7.1
// timestamp : Fri Jun 17 14:17:59 2022 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /scratch/pawan/work/normalised/RV32F/fmadd.s.cgf \
 \
//                  -- xlen 32  \
//                  --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fmadd.s instruction of the RISC-V RV32F_Zicsr,RV32FD_Zicsr,RV64F_Zicsr,RV64FD_Zicsr extension for the fmadd_b15 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*);def TEST_CASE_1=True;",fmadd_b15)
RVTEST_CASE(1,"//check ISA:=regex(.*E.*F.*);def TEST_CASE_1=True;",fmadd_b15)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_15360:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1799a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9799a1; op2val:0x0;
op3val:0x8003ff; valaddr_reg:x3; val_offset:46080*0 + 3*-1*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46080*0 + 3*0*FLEN/8, x4, x1, x2)

inst_15361:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1799a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9799a1; op2val:0x0;
op3val:0x8007ff; valaddr_reg:x3; val_offset:46083*0 + 3*0*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46083*0 + 3*1*FLEN/8, x4, x1, x2)

inst_15362:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1799a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9799a1; op2val:0x0;
op3val:0x800fff; valaddr_reg:x3; val_offset:46086*0 + 3*1*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46086*0 + 3*2*FLEN/8, x4, x1, x2)

inst_15363:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1799a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9799a1; op2val:0x0;
op3val:0x801fff; valaddr_reg:x3; val_offset:46089*0 + 3*2*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46089*0 + 3*3*FLEN/8, x4, x1, x2)

inst_15364:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1799a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9799a1; op2val:0x0;
op3val:0x803fff; valaddr_reg:x3; val_offset:46092*0 + 3*3*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46092*0 + 3*4*FLEN/8, x4, x1, x2)

inst_15365:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1799a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9799a1; op2val:0x0;
op3val:0x807fff; valaddr_reg:x3; val_offset:46095*0 + 3*4*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46095*0 + 3*5*FLEN/8, x4, x1, x2)

inst_15366:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1799a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9799a1; op2val:0x0;
op3val:0x80ffff; valaddr_reg:x3; val_offset:46098*0 + 3*5*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46098*0 + 3*6*FLEN/8, x4, x1, x2)

inst_15367:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1799a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9799a1; op2val:0x0;
op3val:0x81ffff; valaddr_reg:x3; val_offset:46101*0 + 3*6*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46101*0 + 3*7*FLEN/8, x4, x1, x2)

inst_15368:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1799a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9799a1; op2val:0x0;
op3val:0x83ffff; valaddr_reg:x3; val_offset:46104*0 + 3*7*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46104*0 + 3*8*FLEN/8, x4, x1, x2)

inst_15369:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1799a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9799a1; op2val:0x0;
op3val:0x87ffff; valaddr_reg:x3; val_offset:46107*0 + 3*8*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46107*0 + 3*9*FLEN/8, x4, x1, x2)

inst_15370:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1799a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9799a1; op2val:0x0;
op3val:0x8fffff; valaddr_reg:x3; val_offset:46110*0 + 3*9*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46110*0 + 3*10*FLEN/8, x4, x1, x2)

inst_15371:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1799a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9799a1; op2val:0x0;
op3val:0x9fffff; valaddr_reg:x3; val_offset:46113*0 + 3*10*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46113*0 + 3*11*FLEN/8, x4, x1, x2)

inst_15372:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1799a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9799a1; op2val:0x0;
op3val:0xbfffff; valaddr_reg:x3; val_offset:46116*0 + 3*11*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46116*0 + 3*12*FLEN/8, x4, x1, x2)

inst_15373:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1799a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9799a1; op2val:0x0;
op3val:0xc00000; valaddr_reg:x3; val_offset:46119*0 + 3*12*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46119*0 + 3*13*FLEN/8, x4, x1, x2)

inst_15374:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1799a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9799a1; op2val:0x0;
op3val:0xe00000; valaddr_reg:x3; val_offset:46122*0 + 3*13*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46122*0 + 3*14*FLEN/8, x4, x1, x2)

inst_15375:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1799a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9799a1; op2val:0x0;
op3val:0xf00000; valaddr_reg:x3; val_offset:46125*0 + 3*14*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46125*0 + 3*15*FLEN/8, x4, x1, x2)

inst_15376:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1799a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9799a1; op2val:0x0;
op3val:0xf80000; valaddr_reg:x3; val_offset:46128*0 + 3*15*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46128*0 + 3*16*FLEN/8, x4, x1, x2)

inst_15377:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1799a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9799a1; op2val:0x0;
op3val:0xfc0000; valaddr_reg:x3; val_offset:46131*0 + 3*16*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46131*0 + 3*17*FLEN/8, x4, x1, x2)

inst_15378:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1799a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9799a1; op2val:0x0;
op3val:0xfe0000; valaddr_reg:x3; val_offset:46134*0 + 3*17*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46134*0 + 3*18*FLEN/8, x4, x1, x2)

inst_15379:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1799a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9799a1; op2val:0x0;
op3val:0xff0000; valaddr_reg:x3; val_offset:46137*0 + 3*18*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46137*0 + 3*19*FLEN/8, x4, x1, x2)

inst_15380:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1799a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9799a1; op2val:0x0;
op3val:0xff8000; valaddr_reg:x3; val_offset:46140*0 + 3*19*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46140*0 + 3*20*FLEN/8, x4, x1, x2)

inst_15381:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1799a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9799a1; op2val:0x0;
op3val:0xffc000; valaddr_reg:x3; val_offset:46143*0 + 3*20*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46143*0 + 3*21*FLEN/8, x4, x1, x2)

inst_15382:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1799a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9799a1; op2val:0x0;
op3val:0xffe000; valaddr_reg:x3; val_offset:46146*0 + 3*21*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46146*0 + 3*22*FLEN/8, x4, x1, x2)

inst_15383:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1799a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9799a1; op2val:0x0;
op3val:0xfff000; valaddr_reg:x3; val_offset:46149*0 + 3*22*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46149*0 + 3*23*FLEN/8, x4, x1, x2)

inst_15384:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1799a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9799a1; op2val:0x0;
op3val:0xfff800; valaddr_reg:x3; val_offset:46152*0 + 3*23*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46152*0 + 3*24*FLEN/8, x4, x1, x2)

inst_15385:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1799a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9799a1; op2val:0x0;
op3val:0xfffc00; valaddr_reg:x3; val_offset:46155*0 + 3*24*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46155*0 + 3*25*FLEN/8, x4, x1, x2)

inst_15386:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1799a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9799a1; op2val:0x0;
op3val:0xfffe00; valaddr_reg:x3; val_offset:46158*0 + 3*25*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46158*0 + 3*26*FLEN/8, x4, x1, x2)

inst_15387:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1799a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9799a1; op2val:0x0;
op3val:0xffff00; valaddr_reg:x3; val_offset:46161*0 + 3*26*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46161*0 + 3*27*FLEN/8, x4, x1, x2)

inst_15388:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1799a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9799a1; op2val:0x0;
op3val:0xffff80; valaddr_reg:x3; val_offset:46164*0 + 3*27*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46164*0 + 3*28*FLEN/8, x4, x1, x2)

inst_15389:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1799a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9799a1; op2val:0x0;
op3val:0xffffc0; valaddr_reg:x3; val_offset:46167*0 + 3*28*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46167*0 + 3*29*FLEN/8, x4, x1, x2)

inst_15390:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1799a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9799a1; op2val:0x0;
op3val:0xffffe0; valaddr_reg:x3; val_offset:46170*0 + 3*29*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46170*0 + 3*30*FLEN/8, x4, x1, x2)

inst_15391:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1799a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9799a1; op2val:0x0;
op3val:0xfffff0; valaddr_reg:x3; val_offset:46173*0 + 3*30*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46173*0 + 3*31*FLEN/8, x4, x1, x2)

inst_15392:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1799a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9799a1; op2val:0x0;
op3val:0xfffff8; valaddr_reg:x3; val_offset:46176*0 + 3*31*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46176*0 + 3*32*FLEN/8, x4, x1, x2)

inst_15393:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1799a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9799a1; op2val:0x0;
op3val:0xfffffc; valaddr_reg:x3; val_offset:46179*0 + 3*32*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46179*0 + 3*33*FLEN/8, x4, x1, x2)

inst_15394:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1799a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9799a1; op2val:0x0;
op3val:0xfffffe; valaddr_reg:x3; val_offset:46182*0 + 3*33*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46182*0 + 3*34*FLEN/8, x4, x1, x2)

inst_15395:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1799a1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9799a1; op2val:0x0;
op3val:0xffffff; valaddr_reg:x3; val_offset:46185*0 + 3*34*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46185*0 + 3*35*FLEN/8, x4, x1, x2)

inst_15396:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xeb and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xf5800000; valaddr_reg:x3; val_offset:46188*0 + 3*35*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46188*0 + 3*36*FLEN/8, x4, x1, x2)

inst_15397:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xeb and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xf5800001; valaddr_reg:x3; val_offset:46191*0 + 3*36*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46191*0 + 3*37*FLEN/8, x4, x1, x2)

inst_15398:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xeb and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xf5800003; valaddr_reg:x3; val_offset:46194*0 + 3*37*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46194*0 + 3*38*FLEN/8, x4, x1, x2)

inst_15399:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xeb and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xf5800007; valaddr_reg:x3; val_offset:46197*0 + 3*38*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46197*0 + 3*39*FLEN/8, x4, x1, x2)

inst_15400:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xeb and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xf580000f; valaddr_reg:x3; val_offset:46200*0 + 3*39*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46200*0 + 3*40*FLEN/8, x4, x1, x2)

inst_15401:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xeb and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xf580001f; valaddr_reg:x3; val_offset:46203*0 + 3*40*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46203*0 + 3*41*FLEN/8, x4, x1, x2)

inst_15402:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xeb and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xf580003f; valaddr_reg:x3; val_offset:46206*0 + 3*41*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46206*0 + 3*42*FLEN/8, x4, x1, x2)

inst_15403:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xeb and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xf580007f; valaddr_reg:x3; val_offset:46209*0 + 3*42*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46209*0 + 3*43*FLEN/8, x4, x1, x2)

inst_15404:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xeb and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xf58000ff; valaddr_reg:x3; val_offset:46212*0 + 3*43*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46212*0 + 3*44*FLEN/8, x4, x1, x2)

inst_15405:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xeb and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xf58001ff; valaddr_reg:x3; val_offset:46215*0 + 3*44*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46215*0 + 3*45*FLEN/8, x4, x1, x2)

inst_15406:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xeb and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xf58003ff; valaddr_reg:x3; val_offset:46218*0 + 3*45*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46218*0 + 3*46*FLEN/8, x4, x1, x2)

inst_15407:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xeb and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xf58007ff; valaddr_reg:x3; val_offset:46221*0 + 3*46*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46221*0 + 3*47*FLEN/8, x4, x1, x2)

inst_15408:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xeb and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xf5800fff; valaddr_reg:x3; val_offset:46224*0 + 3*47*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46224*0 + 3*48*FLEN/8, x4, x1, x2)

inst_15409:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xeb and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xf5801fff; valaddr_reg:x3; val_offset:46227*0 + 3*48*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46227*0 + 3*49*FLEN/8, x4, x1, x2)

inst_15410:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xeb and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xf5803fff; valaddr_reg:x3; val_offset:46230*0 + 3*49*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46230*0 + 3*50*FLEN/8, x4, x1, x2)

inst_15411:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xeb and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xf5807fff; valaddr_reg:x3; val_offset:46233*0 + 3*50*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46233*0 + 3*51*FLEN/8, x4, x1, x2)

inst_15412:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xeb and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xf580ffff; valaddr_reg:x3; val_offset:46236*0 + 3*51*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46236*0 + 3*52*FLEN/8, x4, x1, x2)

inst_15413:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xeb and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xf581ffff; valaddr_reg:x3; val_offset:46239*0 + 3*52*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46239*0 + 3*53*FLEN/8, x4, x1, x2)

inst_15414:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xeb and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xf583ffff; valaddr_reg:x3; val_offset:46242*0 + 3*53*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46242*0 + 3*54*FLEN/8, x4, x1, x2)

inst_15415:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xeb and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xf587ffff; valaddr_reg:x3; val_offset:46245*0 + 3*54*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46245*0 + 3*55*FLEN/8, x4, x1, x2)

inst_15416:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xeb and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xf58fffff; valaddr_reg:x3; val_offset:46248*0 + 3*55*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46248*0 + 3*56*FLEN/8, x4, x1, x2)

inst_15417:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xeb and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xf59fffff; valaddr_reg:x3; val_offset:46251*0 + 3*56*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46251*0 + 3*57*FLEN/8, x4, x1, x2)

inst_15418:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xeb and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xf5bfffff; valaddr_reg:x3; val_offset:46254*0 + 3*57*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46254*0 + 3*58*FLEN/8, x4, x1, x2)

inst_15419:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xeb and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xf5c00000; valaddr_reg:x3; val_offset:46257*0 + 3*58*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46257*0 + 3*59*FLEN/8, x4, x1, x2)

inst_15420:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xeb and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xf5e00000; valaddr_reg:x3; val_offset:46260*0 + 3*59*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46260*0 + 3*60*FLEN/8, x4, x1, x2)

inst_15421:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xeb and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xf5f00000; valaddr_reg:x3; val_offset:46263*0 + 3*60*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46263*0 + 3*61*FLEN/8, x4, x1, x2)

inst_15422:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xeb and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xf5f80000; valaddr_reg:x3; val_offset:46266*0 + 3*61*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46266*0 + 3*62*FLEN/8, x4, x1, x2)

inst_15423:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xeb and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xf5fc0000; valaddr_reg:x3; val_offset:46269*0 + 3*62*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46269*0 + 3*63*FLEN/8, x4, x1, x2)

inst_15424:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xeb and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xf5fe0000; valaddr_reg:x3; val_offset:46272*0 + 3*63*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46272*0 + 3*64*FLEN/8, x4, x1, x2)

inst_15425:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xeb and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xf5ff0000; valaddr_reg:x3; val_offset:46275*0 + 3*64*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46275*0 + 3*65*FLEN/8, x4, x1, x2)

inst_15426:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xeb and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xf5ff8000; valaddr_reg:x3; val_offset:46278*0 + 3*65*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46278*0 + 3*66*FLEN/8, x4, x1, x2)

inst_15427:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xeb and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xf5ffc000; valaddr_reg:x3; val_offset:46281*0 + 3*66*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46281*0 + 3*67*FLEN/8, x4, x1, x2)

inst_15428:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xeb and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xf5ffe000; valaddr_reg:x3; val_offset:46284*0 + 3*67*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46284*0 + 3*68*FLEN/8, x4, x1, x2)

inst_15429:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xeb and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xf5fff000; valaddr_reg:x3; val_offset:46287*0 + 3*68*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46287*0 + 3*69*FLEN/8, x4, x1, x2)

inst_15430:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xeb and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xf5fff800; valaddr_reg:x3; val_offset:46290*0 + 3*69*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46290*0 + 3*70*FLEN/8, x4, x1, x2)

inst_15431:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xeb and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xf5fffc00; valaddr_reg:x3; val_offset:46293*0 + 3*70*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46293*0 + 3*71*FLEN/8, x4, x1, x2)

inst_15432:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xeb and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xf5fffe00; valaddr_reg:x3; val_offset:46296*0 + 3*71*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46296*0 + 3*72*FLEN/8, x4, x1, x2)

inst_15433:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xeb and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xf5ffff00; valaddr_reg:x3; val_offset:46299*0 + 3*72*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46299*0 + 3*73*FLEN/8, x4, x1, x2)

inst_15434:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xeb and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xf5ffff80; valaddr_reg:x3; val_offset:46302*0 + 3*73*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46302*0 + 3*74*FLEN/8, x4, x1, x2)

inst_15435:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xeb and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xf5ffffc0; valaddr_reg:x3; val_offset:46305*0 + 3*74*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46305*0 + 3*75*FLEN/8, x4, x1, x2)

inst_15436:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xeb and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xf5ffffe0; valaddr_reg:x3; val_offset:46308*0 + 3*75*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46308*0 + 3*76*FLEN/8, x4, x1, x2)

inst_15437:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xeb and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xf5fffff0; valaddr_reg:x3; val_offset:46311*0 + 3*76*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46311*0 + 3*77*FLEN/8, x4, x1, x2)

inst_15438:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xeb and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xf5fffff8; valaddr_reg:x3; val_offset:46314*0 + 3*77*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46314*0 + 3*78*FLEN/8, x4, x1, x2)

inst_15439:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xeb and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xf5fffffc; valaddr_reg:x3; val_offset:46317*0 + 3*78*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46317*0 + 3*79*FLEN/8, x4, x1, x2)

inst_15440:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xeb and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xf5fffffe; valaddr_reg:x3; val_offset:46320*0 + 3*79*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46320*0 + 3*80*FLEN/8, x4, x1, x2)

inst_15441:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xeb and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xf5ffffff; valaddr_reg:x3; val_offset:46323*0 + 3*80*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46323*0 + 3*81*FLEN/8, x4, x1, x2)

inst_15442:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xff000001; valaddr_reg:x3; val_offset:46326*0 + 3*81*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46326*0 + 3*82*FLEN/8, x4, x1, x2)

inst_15443:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xff000003; valaddr_reg:x3; val_offset:46329*0 + 3*82*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46329*0 + 3*83*FLEN/8, x4, x1, x2)

inst_15444:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xff000007; valaddr_reg:x3; val_offset:46332*0 + 3*83*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46332*0 + 3*84*FLEN/8, x4, x1, x2)

inst_15445:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xff199999; valaddr_reg:x3; val_offset:46335*0 + 3*84*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46335*0 + 3*85*FLEN/8, x4, x1, x2)

inst_15446:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xff249249; valaddr_reg:x3; val_offset:46338*0 + 3*85*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46338*0 + 3*86*FLEN/8, x4, x1, x2)

inst_15447:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xff333333; valaddr_reg:x3; val_offset:46341*0 + 3*86*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46341*0 + 3*87*FLEN/8, x4, x1, x2)

inst_15448:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xff36db6d; valaddr_reg:x3; val_offset:46344*0 + 3*87*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46344*0 + 3*88*FLEN/8, x4, x1, x2)

inst_15449:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xff3bbbbb; valaddr_reg:x3; val_offset:46347*0 + 3*88*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46347*0 + 3*89*FLEN/8, x4, x1, x2)

inst_15450:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xff444444; valaddr_reg:x3; val_offset:46350*0 + 3*89*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46350*0 + 3*90*FLEN/8, x4, x1, x2)

inst_15451:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xff4ccccc; valaddr_reg:x3; val_offset:46353*0 + 3*90*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46353*0 + 3*91*FLEN/8, x4, x1, x2)

inst_15452:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xff5b6db6; valaddr_reg:x3; val_offset:46356*0 + 3*91*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46356*0 + 3*92*FLEN/8, x4, x1, x2)

inst_15453:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xff666666; valaddr_reg:x3; val_offset:46359*0 + 3*92*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46359*0 + 3*93*FLEN/8, x4, x1, x2)

inst_15454:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xff6db6db; valaddr_reg:x3; val_offset:46362*0 + 3*93*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46362*0 + 3*94*FLEN/8, x4, x1, x2)

inst_15455:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xff7ffff8; valaddr_reg:x3; val_offset:46365*0 + 3*94*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46365*0 + 3*95*FLEN/8, x4, x1, x2)

inst_15456:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xff7ffffc; valaddr_reg:x3; val_offset:46368*0 + 3*95*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46368*0 + 3*96*FLEN/8, x4, x1, x2)

inst_15457:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x18277b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x575c44 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e98277b; op2val:0xc0575c44;
op3val:0xff7ffffe; valaddr_reg:x3; val_offset:46371*0 + 3*96*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46371*0 + 3*97*FLEN/8, x4, x1, x2)

inst_15458:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xc9 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xe4800000; valaddr_reg:x3; val_offset:46374*0 + 3*97*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46374*0 + 3*98*FLEN/8, x4, x1, x2)

inst_15459:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xc9 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xe4800001; valaddr_reg:x3; val_offset:46377*0 + 3*98*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46377*0 + 3*99*FLEN/8, x4, x1, x2)

inst_15460:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xc9 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xe4800003; valaddr_reg:x3; val_offset:46380*0 + 3*99*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46380*0 + 3*100*FLEN/8, x4, x1, x2)

inst_15461:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xc9 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xe4800007; valaddr_reg:x3; val_offset:46383*0 + 3*100*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46383*0 + 3*101*FLEN/8, x4, x1, x2)

inst_15462:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xc9 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xe480000f; valaddr_reg:x3; val_offset:46386*0 + 3*101*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46386*0 + 3*102*FLEN/8, x4, x1, x2)

inst_15463:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xc9 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xe480001f; valaddr_reg:x3; val_offset:46389*0 + 3*102*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46389*0 + 3*103*FLEN/8, x4, x1, x2)

inst_15464:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xc9 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xe480003f; valaddr_reg:x3; val_offset:46392*0 + 3*103*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46392*0 + 3*104*FLEN/8, x4, x1, x2)

inst_15465:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xc9 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xe480007f; valaddr_reg:x3; val_offset:46395*0 + 3*104*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46395*0 + 3*105*FLEN/8, x4, x1, x2)

inst_15466:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xc9 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xe48000ff; valaddr_reg:x3; val_offset:46398*0 + 3*105*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46398*0 + 3*106*FLEN/8, x4, x1, x2)

inst_15467:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xc9 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xe48001ff; valaddr_reg:x3; val_offset:46401*0 + 3*106*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46401*0 + 3*107*FLEN/8, x4, x1, x2)

inst_15468:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xc9 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xe48003ff; valaddr_reg:x3; val_offset:46404*0 + 3*107*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46404*0 + 3*108*FLEN/8, x4, x1, x2)

inst_15469:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xc9 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xe48007ff; valaddr_reg:x3; val_offset:46407*0 + 3*108*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46407*0 + 3*109*FLEN/8, x4, x1, x2)

inst_15470:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xc9 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xe4800fff; valaddr_reg:x3; val_offset:46410*0 + 3*109*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46410*0 + 3*110*FLEN/8, x4, x1, x2)

inst_15471:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xc9 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xe4801fff; valaddr_reg:x3; val_offset:46413*0 + 3*110*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46413*0 + 3*111*FLEN/8, x4, x1, x2)

inst_15472:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xc9 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xe4803fff; valaddr_reg:x3; val_offset:46416*0 + 3*111*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46416*0 + 3*112*FLEN/8, x4, x1, x2)

inst_15473:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xc9 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xe4807fff; valaddr_reg:x3; val_offset:46419*0 + 3*112*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46419*0 + 3*113*FLEN/8, x4, x1, x2)

inst_15474:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xc9 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xe480ffff; valaddr_reg:x3; val_offset:46422*0 + 3*113*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46422*0 + 3*114*FLEN/8, x4, x1, x2)

inst_15475:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xc9 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xe481ffff; valaddr_reg:x3; val_offset:46425*0 + 3*114*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46425*0 + 3*115*FLEN/8, x4, x1, x2)

inst_15476:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xc9 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xe483ffff; valaddr_reg:x3; val_offset:46428*0 + 3*115*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46428*0 + 3*116*FLEN/8, x4, x1, x2)

inst_15477:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xc9 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xe487ffff; valaddr_reg:x3; val_offset:46431*0 + 3*116*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46431*0 + 3*117*FLEN/8, x4, x1, x2)

inst_15478:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xc9 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xe48fffff; valaddr_reg:x3; val_offset:46434*0 + 3*117*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46434*0 + 3*118*FLEN/8, x4, x1, x2)

inst_15479:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xc9 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xe49fffff; valaddr_reg:x3; val_offset:46437*0 + 3*118*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46437*0 + 3*119*FLEN/8, x4, x1, x2)

inst_15480:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xc9 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xe4bfffff; valaddr_reg:x3; val_offset:46440*0 + 3*119*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46440*0 + 3*120*FLEN/8, x4, x1, x2)

inst_15481:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xc9 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xe4c00000; valaddr_reg:x3; val_offset:46443*0 + 3*120*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46443*0 + 3*121*FLEN/8, x4, x1, x2)

inst_15482:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xc9 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xe4e00000; valaddr_reg:x3; val_offset:46446*0 + 3*121*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46446*0 + 3*122*FLEN/8, x4, x1, x2)

inst_15483:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xc9 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xe4f00000; valaddr_reg:x3; val_offset:46449*0 + 3*122*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46449*0 + 3*123*FLEN/8, x4, x1, x2)

inst_15484:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xc9 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xe4f80000; valaddr_reg:x3; val_offset:46452*0 + 3*123*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46452*0 + 3*124*FLEN/8, x4, x1, x2)

inst_15485:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xc9 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xe4fc0000; valaddr_reg:x3; val_offset:46455*0 + 3*124*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46455*0 + 3*125*FLEN/8, x4, x1, x2)

inst_15486:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xc9 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xe4fe0000; valaddr_reg:x3; val_offset:46458*0 + 3*125*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46458*0 + 3*126*FLEN/8, x4, x1, x2)

inst_15487:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xc9 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xe4ff0000; valaddr_reg:x3; val_offset:46461*0 + 3*126*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46461*0 + 3*127*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_2)

inst_15488:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xc9 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xe4ff8000; valaddr_reg:x3; val_offset:46464*0 + 3*127*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46464*0 + 3*128*FLEN/8, x4, x1, x2)

inst_15489:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xc9 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xe4ffc000; valaddr_reg:x3; val_offset:46467*0 + 3*128*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46467*0 + 3*129*FLEN/8, x4, x1, x2)

inst_15490:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xc9 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xe4ffe000; valaddr_reg:x3; val_offset:46470*0 + 3*129*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46470*0 + 3*130*FLEN/8, x4, x1, x2)

inst_15491:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xc9 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xe4fff000; valaddr_reg:x3; val_offset:46473*0 + 3*130*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46473*0 + 3*131*FLEN/8, x4, x1, x2)

inst_15492:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xc9 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xe4fff800; valaddr_reg:x3; val_offset:46476*0 + 3*131*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46476*0 + 3*132*FLEN/8, x4, x1, x2)

inst_15493:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xc9 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xe4fffc00; valaddr_reg:x3; val_offset:46479*0 + 3*132*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46479*0 + 3*133*FLEN/8, x4, x1, x2)

inst_15494:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xc9 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xe4fffe00; valaddr_reg:x3; val_offset:46482*0 + 3*133*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46482*0 + 3*134*FLEN/8, x4, x1, x2)

inst_15495:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xc9 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xe4ffff00; valaddr_reg:x3; val_offset:46485*0 + 3*134*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46485*0 + 3*135*FLEN/8, x4, x1, x2)

inst_15496:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xc9 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xe4ffff80; valaddr_reg:x3; val_offset:46488*0 + 3*135*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46488*0 + 3*136*FLEN/8, x4, x1, x2)

inst_15497:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xc9 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xe4ffffc0; valaddr_reg:x3; val_offset:46491*0 + 3*136*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46491*0 + 3*137*FLEN/8, x4, x1, x2)

inst_15498:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xc9 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xe4ffffe0; valaddr_reg:x3; val_offset:46494*0 + 3*137*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46494*0 + 3*138*FLEN/8, x4, x1, x2)

inst_15499:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xc9 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xe4fffff0; valaddr_reg:x3; val_offset:46497*0 + 3*138*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46497*0 + 3*139*FLEN/8, x4, x1, x2)

inst_15500:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xc9 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xe4fffff8; valaddr_reg:x3; val_offset:46500*0 + 3*139*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46500*0 + 3*140*FLEN/8, x4, x1, x2)

inst_15501:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xc9 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xe4fffffc; valaddr_reg:x3; val_offset:46503*0 + 3*140*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46503*0 + 3*141*FLEN/8, x4, x1, x2)

inst_15502:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xc9 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xe4fffffe; valaddr_reg:x3; val_offset:46506*0 + 3*141*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46506*0 + 3*142*FLEN/8, x4, x1, x2)

inst_15503:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xc9 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xe4ffffff; valaddr_reg:x3; val_offset:46509*0 + 3*142*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46509*0 + 3*143*FLEN/8, x4, x1, x2)

inst_15504:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xff000001; valaddr_reg:x3; val_offset:46512*0 + 3*143*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46512*0 + 3*144*FLEN/8, x4, x1, x2)

inst_15505:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xff000003; valaddr_reg:x3; val_offset:46515*0 + 3*144*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46515*0 + 3*145*FLEN/8, x4, x1, x2)

inst_15506:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xff000007; valaddr_reg:x3; val_offset:46518*0 + 3*145*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46518*0 + 3*146*FLEN/8, x4, x1, x2)

inst_15507:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xff199999; valaddr_reg:x3; val_offset:46521*0 + 3*146*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46521*0 + 3*147*FLEN/8, x4, x1, x2)

inst_15508:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xff249249; valaddr_reg:x3; val_offset:46524*0 + 3*147*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46524*0 + 3*148*FLEN/8, x4, x1, x2)

inst_15509:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xff333333; valaddr_reg:x3; val_offset:46527*0 + 3*148*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46527*0 + 3*149*FLEN/8, x4, x1, x2)

inst_15510:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xff36db6d; valaddr_reg:x3; val_offset:46530*0 + 3*149*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46530*0 + 3*150*FLEN/8, x4, x1, x2)

inst_15511:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xff3bbbbb; valaddr_reg:x3; val_offset:46533*0 + 3*150*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46533*0 + 3*151*FLEN/8, x4, x1, x2)

inst_15512:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xff444444; valaddr_reg:x3; val_offset:46536*0 + 3*151*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46536*0 + 3*152*FLEN/8, x4, x1, x2)

inst_15513:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xff4ccccc; valaddr_reg:x3; val_offset:46539*0 + 3*152*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46539*0 + 3*153*FLEN/8, x4, x1, x2)

inst_15514:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xff5b6db6; valaddr_reg:x3; val_offset:46542*0 + 3*153*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46542*0 + 3*154*FLEN/8, x4, x1, x2)

inst_15515:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xff666666; valaddr_reg:x3; val_offset:46545*0 + 3*154*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46545*0 + 3*155*FLEN/8, x4, x1, x2)

inst_15516:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xff6db6db; valaddr_reg:x3; val_offset:46548*0 + 3*155*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46548*0 + 3*156*FLEN/8, x4, x1, x2)

inst_15517:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xff7ffff8; valaddr_reg:x3; val_offset:46551*0 + 3*156*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46551*0 + 3*157*FLEN/8, x4, x1, x2)

inst_15518:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xff7ffffc; valaddr_reg:x3; val_offset:46554*0 + 3*157*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46554*0 + 3*158*FLEN/8, x4, x1, x2)

inst_15519:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19215d and fs2 == 1 and fe2 == 0x80 and fm2 == 0x55fcd6 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99215d; op2val:0xc055fcd6;
op3val:0xff7ffffe; valaddr_reg:x3; val_offset:46557*0 + 3*158*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46557*0 + 3*159*FLEN/8, x4, x1, x2)

inst_15520:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x3; val_offset:46560*0 + 3*159*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46560*0 + 3*160*FLEN/8, x4, x1, x2)

inst_15521:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0x80000003; valaddr_reg:x3; val_offset:46563*0 + 3*160*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46563*0 + 3*161*FLEN/8, x4, x1, x2)

inst_15522:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0x80000007; valaddr_reg:x3; val_offset:46566*0 + 3*161*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46566*0 + 3*162*FLEN/8, x4, x1, x2)

inst_15523:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0x80199999; valaddr_reg:x3; val_offset:46569*0 + 3*162*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46569*0 + 3*163*FLEN/8, x4, x1, x2)

inst_15524:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0x80249249; valaddr_reg:x3; val_offset:46572*0 + 3*163*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46572*0 + 3*164*FLEN/8, x4, x1, x2)

inst_15525:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0x80333333; valaddr_reg:x3; val_offset:46575*0 + 3*164*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46575*0 + 3*165*FLEN/8, x4, x1, x2)

inst_15526:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0x8036db6d; valaddr_reg:x3; val_offset:46578*0 + 3*165*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46578*0 + 3*166*FLEN/8, x4, x1, x2)

inst_15527:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0x803bbbbb; valaddr_reg:x3; val_offset:46581*0 + 3*166*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46581*0 + 3*167*FLEN/8, x4, x1, x2)

inst_15528:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0x80444444; valaddr_reg:x3; val_offset:46584*0 + 3*167*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46584*0 + 3*168*FLEN/8, x4, x1, x2)

inst_15529:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0x804ccccc; valaddr_reg:x3; val_offset:46587*0 + 3*168*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46587*0 + 3*169*FLEN/8, x4, x1, x2)

inst_15530:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0x805b6db6; valaddr_reg:x3; val_offset:46590*0 + 3*169*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46590*0 + 3*170*FLEN/8, x4, x1, x2)

inst_15531:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0x80666666; valaddr_reg:x3; val_offset:46593*0 + 3*170*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46593*0 + 3*171*FLEN/8, x4, x1, x2)

inst_15532:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0x806db6db; valaddr_reg:x3; val_offset:46596*0 + 3*171*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46596*0 + 3*172*FLEN/8, x4, x1, x2)

inst_15533:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0x807ffff8; valaddr_reg:x3; val_offset:46599*0 + 3*172*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46599*0 + 3*173*FLEN/8, x4, x1, x2)

inst_15534:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0x807ffffc; valaddr_reg:x3; val_offset:46602*0 + 3*173*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46602*0 + 3*174*FLEN/8, x4, x1, x2)

inst_15535:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x3; val_offset:46605*0 + 3*174*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46605*0 + 3*175*FLEN/8, x4, x1, x2)

inst_15536:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xf8 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0xfc000000; valaddr_reg:x3; val_offset:46608*0 + 3*175*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46608*0 + 3*176*FLEN/8, x4, x1, x2)

inst_15537:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xf8 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0xfc000001; valaddr_reg:x3; val_offset:46611*0 + 3*176*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46611*0 + 3*177*FLEN/8, x4, x1, x2)

inst_15538:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xf8 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0xfc000003; valaddr_reg:x3; val_offset:46614*0 + 3*177*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46614*0 + 3*178*FLEN/8, x4, x1, x2)

inst_15539:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xf8 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0xfc000007; valaddr_reg:x3; val_offset:46617*0 + 3*178*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46617*0 + 3*179*FLEN/8, x4, x1, x2)

inst_15540:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xf8 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0xfc00000f; valaddr_reg:x3; val_offset:46620*0 + 3*179*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46620*0 + 3*180*FLEN/8, x4, x1, x2)

inst_15541:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xf8 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0xfc00001f; valaddr_reg:x3; val_offset:46623*0 + 3*180*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46623*0 + 3*181*FLEN/8, x4, x1, x2)

inst_15542:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xf8 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0xfc00003f; valaddr_reg:x3; val_offset:46626*0 + 3*181*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46626*0 + 3*182*FLEN/8, x4, x1, x2)

inst_15543:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xf8 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0xfc00007f; valaddr_reg:x3; val_offset:46629*0 + 3*182*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46629*0 + 3*183*FLEN/8, x4, x1, x2)

inst_15544:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xf8 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0xfc0000ff; valaddr_reg:x3; val_offset:46632*0 + 3*183*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46632*0 + 3*184*FLEN/8, x4, x1, x2)

inst_15545:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xf8 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0xfc0001ff; valaddr_reg:x3; val_offset:46635*0 + 3*184*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46635*0 + 3*185*FLEN/8, x4, x1, x2)

inst_15546:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xf8 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0xfc0003ff; valaddr_reg:x3; val_offset:46638*0 + 3*185*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46638*0 + 3*186*FLEN/8, x4, x1, x2)

inst_15547:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xf8 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0xfc0007ff; valaddr_reg:x3; val_offset:46641*0 + 3*186*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46641*0 + 3*187*FLEN/8, x4, x1, x2)

inst_15548:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xf8 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0xfc000fff; valaddr_reg:x3; val_offset:46644*0 + 3*187*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46644*0 + 3*188*FLEN/8, x4, x1, x2)

inst_15549:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xf8 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0xfc001fff; valaddr_reg:x3; val_offset:46647*0 + 3*188*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46647*0 + 3*189*FLEN/8, x4, x1, x2)

inst_15550:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xf8 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0xfc003fff; valaddr_reg:x3; val_offset:46650*0 + 3*189*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46650*0 + 3*190*FLEN/8, x4, x1, x2)

inst_15551:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xf8 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0xfc007fff; valaddr_reg:x3; val_offset:46653*0 + 3*190*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46653*0 + 3*191*FLEN/8, x4, x1, x2)

inst_15552:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xf8 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0xfc00ffff; valaddr_reg:x3; val_offset:46656*0 + 3*191*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46656*0 + 3*192*FLEN/8, x4, x1, x2)

inst_15553:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xf8 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0xfc01ffff; valaddr_reg:x3; val_offset:46659*0 + 3*192*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46659*0 + 3*193*FLEN/8, x4, x1, x2)

inst_15554:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xf8 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0xfc03ffff; valaddr_reg:x3; val_offset:46662*0 + 3*193*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46662*0 + 3*194*FLEN/8, x4, x1, x2)

inst_15555:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xf8 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0xfc07ffff; valaddr_reg:x3; val_offset:46665*0 + 3*194*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46665*0 + 3*195*FLEN/8, x4, x1, x2)

inst_15556:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xf8 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0xfc0fffff; valaddr_reg:x3; val_offset:46668*0 + 3*195*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46668*0 + 3*196*FLEN/8, x4, x1, x2)

inst_15557:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xf8 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0xfc1fffff; valaddr_reg:x3; val_offset:46671*0 + 3*196*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46671*0 + 3*197*FLEN/8, x4, x1, x2)

inst_15558:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xf8 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0xfc3fffff; valaddr_reg:x3; val_offset:46674*0 + 3*197*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46674*0 + 3*198*FLEN/8, x4, x1, x2)

inst_15559:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xf8 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0xfc400000; valaddr_reg:x3; val_offset:46677*0 + 3*198*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46677*0 + 3*199*FLEN/8, x4, x1, x2)

inst_15560:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xf8 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0xfc600000; valaddr_reg:x3; val_offset:46680*0 + 3*199*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46680*0 + 3*200*FLEN/8, x4, x1, x2)

inst_15561:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xf8 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0xfc700000; valaddr_reg:x3; val_offset:46683*0 + 3*200*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46683*0 + 3*201*FLEN/8, x4, x1, x2)

inst_15562:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xf8 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0xfc780000; valaddr_reg:x3; val_offset:46686*0 + 3*201*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46686*0 + 3*202*FLEN/8, x4, x1, x2)

inst_15563:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xf8 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0xfc7c0000; valaddr_reg:x3; val_offset:46689*0 + 3*202*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46689*0 + 3*203*FLEN/8, x4, x1, x2)

inst_15564:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xf8 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0xfc7e0000; valaddr_reg:x3; val_offset:46692*0 + 3*203*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46692*0 + 3*204*FLEN/8, x4, x1, x2)

inst_15565:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xf8 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0xfc7f0000; valaddr_reg:x3; val_offset:46695*0 + 3*204*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46695*0 + 3*205*FLEN/8, x4, x1, x2)

inst_15566:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xf8 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0xfc7f8000; valaddr_reg:x3; val_offset:46698*0 + 3*205*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46698*0 + 3*206*FLEN/8, x4, x1, x2)

inst_15567:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xf8 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0xfc7fc000; valaddr_reg:x3; val_offset:46701*0 + 3*206*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46701*0 + 3*207*FLEN/8, x4, x1, x2)

inst_15568:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xf8 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0xfc7fe000; valaddr_reg:x3; val_offset:46704*0 + 3*207*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46704*0 + 3*208*FLEN/8, x4, x1, x2)

inst_15569:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xf8 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0xfc7ff000; valaddr_reg:x3; val_offset:46707*0 + 3*208*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46707*0 + 3*209*FLEN/8, x4, x1, x2)

inst_15570:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xf8 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0xfc7ff800; valaddr_reg:x3; val_offset:46710*0 + 3*209*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46710*0 + 3*210*FLEN/8, x4, x1, x2)

inst_15571:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xf8 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0xfc7ffc00; valaddr_reg:x3; val_offset:46713*0 + 3*210*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46713*0 + 3*211*FLEN/8, x4, x1, x2)

inst_15572:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xf8 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0xfc7ffe00; valaddr_reg:x3; val_offset:46716*0 + 3*211*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46716*0 + 3*212*FLEN/8, x4, x1, x2)

inst_15573:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xf8 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0xfc7fff00; valaddr_reg:x3; val_offset:46719*0 + 3*212*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46719*0 + 3*213*FLEN/8, x4, x1, x2)

inst_15574:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xf8 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0xfc7fff80; valaddr_reg:x3; val_offset:46722*0 + 3*213*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46722*0 + 3*214*FLEN/8, x4, x1, x2)

inst_15575:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xf8 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0xfc7fffc0; valaddr_reg:x3; val_offset:46725*0 + 3*214*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46725*0 + 3*215*FLEN/8, x4, x1, x2)

inst_15576:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xf8 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0xfc7fffe0; valaddr_reg:x3; val_offset:46728*0 + 3*215*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46728*0 + 3*216*FLEN/8, x4, x1, x2)

inst_15577:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xf8 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0xfc7ffff0; valaddr_reg:x3; val_offset:46731*0 + 3*216*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46731*0 + 3*217*FLEN/8, x4, x1, x2)

inst_15578:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xf8 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0xfc7ffff8; valaddr_reg:x3; val_offset:46734*0 + 3*217*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46734*0 + 3*218*FLEN/8, x4, x1, x2)

inst_15579:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xf8 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0xfc7ffffc; valaddr_reg:x3; val_offset:46737*0 + 3*218*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46737*0 + 3*219*FLEN/8, x4, x1, x2)

inst_15580:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xf8 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0xfc7ffffe; valaddr_reg:x3; val_offset:46740*0 + 3*219*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46740*0 + 3*220*FLEN/8, x4, x1, x2)

inst_15581:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1925f2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0xf8 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9925f2; op2val:0x80000000;
op3val:0xfc7fffff; valaddr_reg:x3; val_offset:46743*0 + 3*220*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46743*0 + 3*221*FLEN/8, x4, x1, x2)

inst_15582:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x1; valaddr_reg:x3; val_offset:46746*0 + 3*221*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46746*0 + 3*222*FLEN/8, x4, x1, x2)

inst_15583:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x3; valaddr_reg:x3; val_offset:46749*0 + 3*222*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46749*0 + 3*223*FLEN/8, x4, x1, x2)

inst_15584:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x7; valaddr_reg:x3; val_offset:46752*0 + 3*223*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46752*0 + 3*224*FLEN/8, x4, x1, x2)

inst_15585:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x199999; valaddr_reg:x3; val_offset:46755*0 + 3*224*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46755*0 + 3*225*FLEN/8, x4, x1, x2)

inst_15586:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x249249; valaddr_reg:x3; val_offset:46758*0 + 3*225*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46758*0 + 3*226*FLEN/8, x4, x1, x2)

inst_15587:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x333333; valaddr_reg:x3; val_offset:46761*0 + 3*226*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46761*0 + 3*227*FLEN/8, x4, x1, x2)

inst_15588:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x36db6d; valaddr_reg:x3; val_offset:46764*0 + 3*227*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46764*0 + 3*228*FLEN/8, x4, x1, x2)

inst_15589:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x3bbbbb; valaddr_reg:x3; val_offset:46767*0 + 3*228*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46767*0 + 3*229*FLEN/8, x4, x1, x2)

inst_15590:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x444444; valaddr_reg:x3; val_offset:46770*0 + 3*229*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46770*0 + 3*230*FLEN/8, x4, x1, x2)

inst_15591:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x4ccccc; valaddr_reg:x3; val_offset:46773*0 + 3*230*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46773*0 + 3*231*FLEN/8, x4, x1, x2)

inst_15592:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x5b6db6; valaddr_reg:x3; val_offset:46776*0 + 3*231*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46776*0 + 3*232*FLEN/8, x4, x1, x2)

inst_15593:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x666666; valaddr_reg:x3; val_offset:46779*0 + 3*232*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46779*0 + 3*233*FLEN/8, x4, x1, x2)

inst_15594:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x6db6db; valaddr_reg:x3; val_offset:46782*0 + 3*233*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46782*0 + 3*234*FLEN/8, x4, x1, x2)

inst_15595:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x7ffff8; valaddr_reg:x3; val_offset:46785*0 + 3*234*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46785*0 + 3*235*FLEN/8, x4, x1, x2)

inst_15596:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x7ffffc; valaddr_reg:x3; val_offset:46788*0 + 3*235*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46788*0 + 3*236*FLEN/8, x4, x1, x2)

inst_15597:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x7ffffe; valaddr_reg:x3; val_offset:46791*0 + 3*236*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46791*0 + 3*237*FLEN/8, x4, x1, x2)

inst_15598:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x5000000; valaddr_reg:x3; val_offset:46794*0 + 3*237*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46794*0 + 3*238*FLEN/8, x4, x1, x2)

inst_15599:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x5000001; valaddr_reg:x3; val_offset:46797*0 + 3*238*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46797*0 + 3*239*FLEN/8, x4, x1, x2)

inst_15600:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x5000003; valaddr_reg:x3; val_offset:46800*0 + 3*239*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46800*0 + 3*240*FLEN/8, x4, x1, x2)

inst_15601:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x5000007; valaddr_reg:x3; val_offset:46803*0 + 3*240*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46803*0 + 3*241*FLEN/8, x4, x1, x2)

inst_15602:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x500000f; valaddr_reg:x3; val_offset:46806*0 + 3*241*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46806*0 + 3*242*FLEN/8, x4, x1, x2)

inst_15603:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x500001f; valaddr_reg:x3; val_offset:46809*0 + 3*242*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46809*0 + 3*243*FLEN/8, x4, x1, x2)

inst_15604:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x500003f; valaddr_reg:x3; val_offset:46812*0 + 3*243*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46812*0 + 3*244*FLEN/8, x4, x1, x2)

inst_15605:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x500007f; valaddr_reg:x3; val_offset:46815*0 + 3*244*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46815*0 + 3*245*FLEN/8, x4, x1, x2)

inst_15606:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x50000ff; valaddr_reg:x3; val_offset:46818*0 + 3*245*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46818*0 + 3*246*FLEN/8, x4, x1, x2)

inst_15607:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x50001ff; valaddr_reg:x3; val_offset:46821*0 + 3*246*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46821*0 + 3*247*FLEN/8, x4, x1, x2)

inst_15608:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x50003ff; valaddr_reg:x3; val_offset:46824*0 + 3*247*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46824*0 + 3*248*FLEN/8, x4, x1, x2)

inst_15609:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x50007ff; valaddr_reg:x3; val_offset:46827*0 + 3*248*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46827*0 + 3*249*FLEN/8, x4, x1, x2)

inst_15610:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x5000fff; valaddr_reg:x3; val_offset:46830*0 + 3*249*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46830*0 + 3*250*FLEN/8, x4, x1, x2)

inst_15611:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x5001fff; valaddr_reg:x3; val_offset:46833*0 + 3*250*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46833*0 + 3*251*FLEN/8, x4, x1, x2)

inst_15612:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x5003fff; valaddr_reg:x3; val_offset:46836*0 + 3*251*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46836*0 + 3*252*FLEN/8, x4, x1, x2)

inst_15613:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x5007fff; valaddr_reg:x3; val_offset:46839*0 + 3*252*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46839*0 + 3*253*FLEN/8, x4, x1, x2)

inst_15614:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x500ffff; valaddr_reg:x3; val_offset:46842*0 + 3*253*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46842*0 + 3*254*FLEN/8, x4, x1, x2)

inst_15615:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x501ffff; valaddr_reg:x3; val_offset:46845*0 + 3*254*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46845*0 + 3*255*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_3)

inst_15616:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x503ffff; valaddr_reg:x3; val_offset:46848*0 + 3*256*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46848*0 + 3*256*FLEN/8, x4, x1, x2)

inst_15617:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x507ffff; valaddr_reg:x3; val_offset:46851*0 + 3*257*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46851*0 + 3*257*FLEN/8, x4, x1, x2)

inst_15618:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x50fffff; valaddr_reg:x3; val_offset:46854*0 + 3*258*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46854*0 + 3*258*FLEN/8, x4, x1, x2)

inst_15619:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x51fffff; valaddr_reg:x3; val_offset:46857*0 + 3*259*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46857*0 + 3*259*FLEN/8, x4, x1, x2)

inst_15620:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x53fffff; valaddr_reg:x3; val_offset:46860*0 + 3*260*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46860*0 + 3*260*FLEN/8, x4, x1, x2)

inst_15621:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x5400000; valaddr_reg:x3; val_offset:46863*0 + 3*261*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46863*0 + 3*261*FLEN/8, x4, x1, x2)

inst_15622:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x5600000; valaddr_reg:x3; val_offset:46866*0 + 3*262*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46866*0 + 3*262*FLEN/8, x4, x1, x2)

inst_15623:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x5700000; valaddr_reg:x3; val_offset:46869*0 + 3*263*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46869*0 + 3*263*FLEN/8, x4, x1, x2)

inst_15624:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x5780000; valaddr_reg:x3; val_offset:46872*0 + 3*264*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46872*0 + 3*264*FLEN/8, x4, x1, x2)

inst_15625:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x57c0000; valaddr_reg:x3; val_offset:46875*0 + 3*265*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46875*0 + 3*265*FLEN/8, x4, x1, x2)

inst_15626:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x57e0000; valaddr_reg:x3; val_offset:46878*0 + 3*266*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46878*0 + 3*266*FLEN/8, x4, x1, x2)

inst_15627:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x57f0000; valaddr_reg:x3; val_offset:46881*0 + 3*267*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46881*0 + 3*267*FLEN/8, x4, x1, x2)

inst_15628:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x57f8000; valaddr_reg:x3; val_offset:46884*0 + 3*268*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46884*0 + 3*268*FLEN/8, x4, x1, x2)

inst_15629:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x57fc000; valaddr_reg:x3; val_offset:46887*0 + 3*269*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46887*0 + 3*269*FLEN/8, x4, x1, x2)

inst_15630:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x57fe000; valaddr_reg:x3; val_offset:46890*0 + 3*270*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46890*0 + 3*270*FLEN/8, x4, x1, x2)

inst_15631:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x57ff000; valaddr_reg:x3; val_offset:46893*0 + 3*271*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46893*0 + 3*271*FLEN/8, x4, x1, x2)

inst_15632:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x57ff800; valaddr_reg:x3; val_offset:46896*0 + 3*272*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46896*0 + 3*272*FLEN/8, x4, x1, x2)

inst_15633:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x57ffc00; valaddr_reg:x3; val_offset:46899*0 + 3*273*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46899*0 + 3*273*FLEN/8, x4, x1, x2)

inst_15634:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x57ffe00; valaddr_reg:x3; val_offset:46902*0 + 3*274*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46902*0 + 3*274*FLEN/8, x4, x1, x2)

inst_15635:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x57fff00; valaddr_reg:x3; val_offset:46905*0 + 3*275*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46905*0 + 3*275*FLEN/8, x4, x1, x2)

inst_15636:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x57fff80; valaddr_reg:x3; val_offset:46908*0 + 3*276*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46908*0 + 3*276*FLEN/8, x4, x1, x2)

inst_15637:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x57fffc0; valaddr_reg:x3; val_offset:46911*0 + 3*277*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46911*0 + 3*277*FLEN/8, x4, x1, x2)

inst_15638:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x57fffe0; valaddr_reg:x3; val_offset:46914*0 + 3*278*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46914*0 + 3*278*FLEN/8, x4, x1, x2)

inst_15639:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x57ffff0; valaddr_reg:x3; val_offset:46917*0 + 3*279*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46917*0 + 3*279*FLEN/8, x4, x1, x2)

inst_15640:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x57ffff8; valaddr_reg:x3; val_offset:46920*0 + 3*280*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46920*0 + 3*280*FLEN/8, x4, x1, x2)

inst_15641:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x57ffffc; valaddr_reg:x3; val_offset:46923*0 + 3*281*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46923*0 + 3*281*FLEN/8, x4, x1, x2)

inst_15642:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x57ffffe; valaddr_reg:x3; val_offset:46926*0 + 3*282*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46926*0 + 3*282*FLEN/8, x4, x1, x2)

inst_15643:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ad123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0a and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ad123; op2val:0x0;
op3val:0x57fffff; valaddr_reg:x3; val_offset:46929*0 + 3*283*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46929*0 + 3*283*FLEN/8, x4, x1, x2)

inst_15644:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0x60 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xb0000000; valaddr_reg:x3; val_offset:46932*0 + 3*284*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46932*0 + 3*284*FLEN/8, x4, x1, x2)

inst_15645:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0x60 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xb0000001; valaddr_reg:x3; val_offset:46935*0 + 3*285*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46935*0 + 3*285*FLEN/8, x4, x1, x2)

inst_15646:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0x60 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xb0000003; valaddr_reg:x3; val_offset:46938*0 + 3*286*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46938*0 + 3*286*FLEN/8, x4, x1, x2)

inst_15647:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0x60 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xb0000007; valaddr_reg:x3; val_offset:46941*0 + 3*287*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46941*0 + 3*287*FLEN/8, x4, x1, x2)

inst_15648:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0x60 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xb000000f; valaddr_reg:x3; val_offset:46944*0 + 3*288*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46944*0 + 3*288*FLEN/8, x4, x1, x2)

inst_15649:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0x60 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xb000001f; valaddr_reg:x3; val_offset:46947*0 + 3*289*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46947*0 + 3*289*FLEN/8, x4, x1, x2)

inst_15650:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0x60 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xb000003f; valaddr_reg:x3; val_offset:46950*0 + 3*290*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46950*0 + 3*290*FLEN/8, x4, x1, x2)

inst_15651:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0x60 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xb000007f; valaddr_reg:x3; val_offset:46953*0 + 3*291*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46953*0 + 3*291*FLEN/8, x4, x1, x2)

inst_15652:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0x60 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xb00000ff; valaddr_reg:x3; val_offset:46956*0 + 3*292*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46956*0 + 3*292*FLEN/8, x4, x1, x2)

inst_15653:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0x60 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xb00001ff; valaddr_reg:x3; val_offset:46959*0 + 3*293*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46959*0 + 3*293*FLEN/8, x4, x1, x2)

inst_15654:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0x60 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xb00003ff; valaddr_reg:x3; val_offset:46962*0 + 3*294*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46962*0 + 3*294*FLEN/8, x4, x1, x2)

inst_15655:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0x60 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xb00007ff; valaddr_reg:x3; val_offset:46965*0 + 3*295*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46965*0 + 3*295*FLEN/8, x4, x1, x2)

inst_15656:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0x60 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xb0000fff; valaddr_reg:x3; val_offset:46968*0 + 3*296*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46968*0 + 3*296*FLEN/8, x4, x1, x2)

inst_15657:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0x60 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xb0001fff; valaddr_reg:x3; val_offset:46971*0 + 3*297*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46971*0 + 3*297*FLEN/8, x4, x1, x2)

inst_15658:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0x60 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xb0003fff; valaddr_reg:x3; val_offset:46974*0 + 3*298*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46974*0 + 3*298*FLEN/8, x4, x1, x2)

inst_15659:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0x60 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xb0007fff; valaddr_reg:x3; val_offset:46977*0 + 3*299*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46977*0 + 3*299*FLEN/8, x4, x1, x2)

inst_15660:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0x60 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xb000ffff; valaddr_reg:x3; val_offset:46980*0 + 3*300*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46980*0 + 3*300*FLEN/8, x4, x1, x2)

inst_15661:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0x60 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xb001ffff; valaddr_reg:x3; val_offset:46983*0 + 3*301*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46983*0 + 3*301*FLEN/8, x4, x1, x2)

inst_15662:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0x60 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xb003ffff; valaddr_reg:x3; val_offset:46986*0 + 3*302*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46986*0 + 3*302*FLEN/8, x4, x1, x2)

inst_15663:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0x60 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xb007ffff; valaddr_reg:x3; val_offset:46989*0 + 3*303*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46989*0 + 3*303*FLEN/8, x4, x1, x2)

inst_15664:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0x60 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xb00fffff; valaddr_reg:x3; val_offset:46992*0 + 3*304*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46992*0 + 3*304*FLEN/8, x4, x1, x2)

inst_15665:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0x60 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xb01fffff; valaddr_reg:x3; val_offset:46995*0 + 3*305*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46995*0 + 3*305*FLEN/8, x4, x1, x2)

inst_15666:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0x60 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xb03fffff; valaddr_reg:x3; val_offset:46998*0 + 3*306*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46998*0 + 3*306*FLEN/8, x4, x1, x2)

inst_15667:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0x60 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xb0400000; valaddr_reg:x3; val_offset:47001*0 + 3*307*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47001*0 + 3*307*FLEN/8, x4, x1, x2)

inst_15668:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0x60 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xb0600000; valaddr_reg:x3; val_offset:47004*0 + 3*308*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47004*0 + 3*308*FLEN/8, x4, x1, x2)

inst_15669:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0x60 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xb0700000; valaddr_reg:x3; val_offset:47007*0 + 3*309*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47007*0 + 3*309*FLEN/8, x4, x1, x2)

inst_15670:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0x60 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xb0780000; valaddr_reg:x3; val_offset:47010*0 + 3*310*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47010*0 + 3*310*FLEN/8, x4, x1, x2)

inst_15671:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0x60 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xb07c0000; valaddr_reg:x3; val_offset:47013*0 + 3*311*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47013*0 + 3*311*FLEN/8, x4, x1, x2)

inst_15672:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0x60 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xb07e0000; valaddr_reg:x3; val_offset:47016*0 + 3*312*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47016*0 + 3*312*FLEN/8, x4, x1, x2)

inst_15673:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0x60 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xb07f0000; valaddr_reg:x3; val_offset:47019*0 + 3*313*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47019*0 + 3*313*FLEN/8, x4, x1, x2)

inst_15674:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0x60 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xb07f8000; valaddr_reg:x3; val_offset:47022*0 + 3*314*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47022*0 + 3*314*FLEN/8, x4, x1, x2)

inst_15675:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0x60 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xb07fc000; valaddr_reg:x3; val_offset:47025*0 + 3*315*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47025*0 + 3*315*FLEN/8, x4, x1, x2)

inst_15676:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0x60 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xb07fe000; valaddr_reg:x3; val_offset:47028*0 + 3*316*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47028*0 + 3*316*FLEN/8, x4, x1, x2)

inst_15677:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0x60 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xb07ff000; valaddr_reg:x3; val_offset:47031*0 + 3*317*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47031*0 + 3*317*FLEN/8, x4, x1, x2)

inst_15678:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0x60 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xb07ff800; valaddr_reg:x3; val_offset:47034*0 + 3*318*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47034*0 + 3*318*FLEN/8, x4, x1, x2)

inst_15679:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0x60 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xb07ffc00; valaddr_reg:x3; val_offset:47037*0 + 3*319*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47037*0 + 3*319*FLEN/8, x4, x1, x2)

inst_15680:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0x60 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xb07ffe00; valaddr_reg:x3; val_offset:47040*0 + 3*320*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47040*0 + 3*320*FLEN/8, x4, x1, x2)

inst_15681:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0x60 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xb07fff00; valaddr_reg:x3; val_offset:47043*0 + 3*321*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47043*0 + 3*321*FLEN/8, x4, x1, x2)

inst_15682:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0x60 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xb07fff80; valaddr_reg:x3; val_offset:47046*0 + 3*322*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47046*0 + 3*322*FLEN/8, x4, x1, x2)

inst_15683:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0x60 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xb07fffc0; valaddr_reg:x3; val_offset:47049*0 + 3*323*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47049*0 + 3*323*FLEN/8, x4, x1, x2)

inst_15684:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0x60 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xb07fffe0; valaddr_reg:x3; val_offset:47052*0 + 3*324*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47052*0 + 3*324*FLEN/8, x4, x1, x2)

inst_15685:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0x60 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xb07ffff0; valaddr_reg:x3; val_offset:47055*0 + 3*325*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47055*0 + 3*325*FLEN/8, x4, x1, x2)

inst_15686:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0x60 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xb07ffff8; valaddr_reg:x3; val_offset:47058*0 + 3*326*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47058*0 + 3*326*FLEN/8, x4, x1, x2)

inst_15687:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0x60 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xb07ffffc; valaddr_reg:x3; val_offset:47061*0 + 3*327*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47061*0 + 3*327*FLEN/8, x4, x1, x2)

inst_15688:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0x60 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xb07ffffe; valaddr_reg:x3; val_offset:47064*0 + 3*328*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47064*0 + 3*328*FLEN/8, x4, x1, x2)

inst_15689:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0x60 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xb07fffff; valaddr_reg:x3; val_offset:47067*0 + 3*329*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47067*0 + 3*329*FLEN/8, x4, x1, x2)

inst_15690:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0xfe and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xff000001; valaddr_reg:x3; val_offset:47070*0 + 3*330*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47070*0 + 3*330*FLEN/8, x4, x1, x2)

inst_15691:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0xfe and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xff000003; valaddr_reg:x3; val_offset:47073*0 + 3*331*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47073*0 + 3*331*FLEN/8, x4, x1, x2)

inst_15692:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0xfe and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xff000007; valaddr_reg:x3; val_offset:47076*0 + 3*332*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47076*0 + 3*332*FLEN/8, x4, x1, x2)

inst_15693:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0xfe and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xff199999; valaddr_reg:x3; val_offset:47079*0 + 3*333*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47079*0 + 3*333*FLEN/8, x4, x1, x2)

inst_15694:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0xfe and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xff249249; valaddr_reg:x3; val_offset:47082*0 + 3*334*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47082*0 + 3*334*FLEN/8, x4, x1, x2)

inst_15695:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0xfe and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xff333333; valaddr_reg:x3; val_offset:47085*0 + 3*335*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47085*0 + 3*335*FLEN/8, x4, x1, x2)

inst_15696:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0xfe and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xff36db6d; valaddr_reg:x3; val_offset:47088*0 + 3*336*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47088*0 + 3*336*FLEN/8, x4, x1, x2)

inst_15697:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0xfe and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xff3bbbbb; valaddr_reg:x3; val_offset:47091*0 + 3*337*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47091*0 + 3*337*FLEN/8, x4, x1, x2)

inst_15698:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0xfe and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xff444444; valaddr_reg:x3; val_offset:47094*0 + 3*338*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47094*0 + 3*338*FLEN/8, x4, x1, x2)

inst_15699:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0xfe and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xff4ccccc; valaddr_reg:x3; val_offset:47097*0 + 3*339*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47097*0 + 3*339*FLEN/8, x4, x1, x2)

inst_15700:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0xfe and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xff5b6db6; valaddr_reg:x3; val_offset:47100*0 + 3*340*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47100*0 + 3*340*FLEN/8, x4, x1, x2)

inst_15701:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0xfe and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xff666666; valaddr_reg:x3; val_offset:47103*0 + 3*341*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47103*0 + 3*341*FLEN/8, x4, x1, x2)

inst_15702:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0xfe and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xff6db6db; valaddr_reg:x3; val_offset:47106*0 + 3*342*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47106*0 + 3*342*FLEN/8, x4, x1, x2)

inst_15703:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xff7ffff8; valaddr_reg:x3; val_offset:47109*0 + 3*343*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47109*0 + 3*343*FLEN/8, x4, x1, x2)

inst_15704:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xff7ffffc; valaddr_reg:x3; val_offset:47112*0 + 3*344*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47112*0 + 3*344*FLEN/8, x4, x1, x2)

inst_15705:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1ce997 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x50d46d and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9ce997; op2val:0xc050d46d;
op3val:0xff7ffffe; valaddr_reg:x3; val_offset:47115*0 + 3*345*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47115*0 + 3*345*FLEN/8, x4, x1, x2)

inst_15706:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0x800001; valaddr_reg:x3; val_offset:47118*0 + 3*346*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47118*0 + 3*346*FLEN/8, x4, x1, x2)

inst_15707:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0x800003; valaddr_reg:x3; val_offset:47121*0 + 3*347*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47121*0 + 3*347*FLEN/8, x4, x1, x2)

inst_15708:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0x800007; valaddr_reg:x3; val_offset:47124*0 + 3*348*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47124*0 + 3*348*FLEN/8, x4, x1, x2)

inst_15709:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0x999999; valaddr_reg:x3; val_offset:47127*0 + 3*349*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47127*0 + 3*349*FLEN/8, x4, x1, x2)

inst_15710:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0xa49249; valaddr_reg:x3; val_offset:47130*0 + 3*350*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47130*0 + 3*350*FLEN/8, x4, x1, x2)

inst_15711:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0xb33333; valaddr_reg:x3; val_offset:47133*0 + 3*351*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47133*0 + 3*351*FLEN/8, x4, x1, x2)

inst_15712:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0xb6db6d; valaddr_reg:x3; val_offset:47136*0 + 3*352*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47136*0 + 3*352*FLEN/8, x4, x1, x2)

inst_15713:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0xbbbbbb; valaddr_reg:x3; val_offset:47139*0 + 3*353*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47139*0 + 3*353*FLEN/8, x4, x1, x2)

inst_15714:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0xc44444; valaddr_reg:x3; val_offset:47142*0 + 3*354*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47142*0 + 3*354*FLEN/8, x4, x1, x2)

inst_15715:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0xcccccc; valaddr_reg:x3; val_offset:47145*0 + 3*355*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47145*0 + 3*355*FLEN/8, x4, x1, x2)

inst_15716:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0xdb6db6; valaddr_reg:x3; val_offset:47148*0 + 3*356*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47148*0 + 3*356*FLEN/8, x4, x1, x2)

inst_15717:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0xe66666; valaddr_reg:x3; val_offset:47151*0 + 3*357*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47151*0 + 3*357*FLEN/8, x4, x1, x2)

inst_15718:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0xedb6db; valaddr_reg:x3; val_offset:47154*0 + 3*358*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47154*0 + 3*358*FLEN/8, x4, x1, x2)

inst_15719:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0xfffff8; valaddr_reg:x3; val_offset:47157*0 + 3*359*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47157*0 + 3*359*FLEN/8, x4, x1, x2)

inst_15720:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0xfffffc; valaddr_reg:x3; val_offset:47160*0 + 3*360*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47160*0 + 3*360*FLEN/8, x4, x1, x2)

inst_15721:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0xfffffe; valaddr_reg:x3; val_offset:47163*0 + 3*361*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47163*0 + 3*361*FLEN/8, x4, x1, x2)

inst_15722:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0x4000000; valaddr_reg:x3; val_offset:47166*0 + 3*362*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47166*0 + 3*362*FLEN/8, x4, x1, x2)

inst_15723:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0x4000001; valaddr_reg:x3; val_offset:47169*0 + 3*363*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47169*0 + 3*363*FLEN/8, x4, x1, x2)

inst_15724:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0x4000003; valaddr_reg:x3; val_offset:47172*0 + 3*364*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47172*0 + 3*364*FLEN/8, x4, x1, x2)

inst_15725:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0x4000007; valaddr_reg:x3; val_offset:47175*0 + 3*365*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47175*0 + 3*365*FLEN/8, x4, x1, x2)

inst_15726:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0x400000f; valaddr_reg:x3; val_offset:47178*0 + 3*366*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47178*0 + 3*366*FLEN/8, x4, x1, x2)

inst_15727:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0x400001f; valaddr_reg:x3; val_offset:47181*0 + 3*367*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47181*0 + 3*367*FLEN/8, x4, x1, x2)

inst_15728:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0x400003f; valaddr_reg:x3; val_offset:47184*0 + 3*368*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47184*0 + 3*368*FLEN/8, x4, x1, x2)

inst_15729:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0x400007f; valaddr_reg:x3; val_offset:47187*0 + 3*369*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47187*0 + 3*369*FLEN/8, x4, x1, x2)

inst_15730:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0x40000ff; valaddr_reg:x3; val_offset:47190*0 + 3*370*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47190*0 + 3*370*FLEN/8, x4, x1, x2)

inst_15731:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0x40001ff; valaddr_reg:x3; val_offset:47193*0 + 3*371*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47193*0 + 3*371*FLEN/8, x4, x1, x2)

inst_15732:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0x40003ff; valaddr_reg:x3; val_offset:47196*0 + 3*372*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47196*0 + 3*372*FLEN/8, x4, x1, x2)

inst_15733:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0x40007ff; valaddr_reg:x3; val_offset:47199*0 + 3*373*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47199*0 + 3*373*FLEN/8, x4, x1, x2)

inst_15734:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0x4000fff; valaddr_reg:x3; val_offset:47202*0 + 3*374*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47202*0 + 3*374*FLEN/8, x4, x1, x2)

inst_15735:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0x4001fff; valaddr_reg:x3; val_offset:47205*0 + 3*375*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47205*0 + 3*375*FLEN/8, x4, x1, x2)

inst_15736:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0x4003fff; valaddr_reg:x3; val_offset:47208*0 + 3*376*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47208*0 + 3*376*FLEN/8, x4, x1, x2)

inst_15737:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0x4007fff; valaddr_reg:x3; val_offset:47211*0 + 3*377*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47211*0 + 3*377*FLEN/8, x4, x1, x2)

inst_15738:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0x400ffff; valaddr_reg:x3; val_offset:47214*0 + 3*378*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47214*0 + 3*378*FLEN/8, x4, x1, x2)

inst_15739:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0x401ffff; valaddr_reg:x3; val_offset:47217*0 + 3*379*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47217*0 + 3*379*FLEN/8, x4, x1, x2)

inst_15740:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0x403ffff; valaddr_reg:x3; val_offset:47220*0 + 3*380*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47220*0 + 3*380*FLEN/8, x4, x1, x2)

inst_15741:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0x407ffff; valaddr_reg:x3; val_offset:47223*0 + 3*381*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47223*0 + 3*381*FLEN/8, x4, x1, x2)

inst_15742:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0x40fffff; valaddr_reg:x3; val_offset:47226*0 + 3*382*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47226*0 + 3*382*FLEN/8, x4, x1, x2)

inst_15743:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0x41fffff; valaddr_reg:x3; val_offset:47229*0 + 3*383*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47229*0 + 3*383*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_4)

inst_15744:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0x43fffff; valaddr_reg:x3; val_offset:47232*0 + 3*384*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47232*0 + 3*384*FLEN/8, x4, x1, x2)

inst_15745:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0x4400000; valaddr_reg:x3; val_offset:47235*0 + 3*385*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47235*0 + 3*385*FLEN/8, x4, x1, x2)

inst_15746:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0x4600000; valaddr_reg:x3; val_offset:47238*0 + 3*386*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47238*0 + 3*386*FLEN/8, x4, x1, x2)

inst_15747:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0x4700000; valaddr_reg:x3; val_offset:47241*0 + 3*387*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47241*0 + 3*387*FLEN/8, x4, x1, x2)

inst_15748:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0x4780000; valaddr_reg:x3; val_offset:47244*0 + 3*388*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47244*0 + 3*388*FLEN/8, x4, x1, x2)

inst_15749:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0x47c0000; valaddr_reg:x3; val_offset:47247*0 + 3*389*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47247*0 + 3*389*FLEN/8, x4, x1, x2)

inst_15750:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0x47e0000; valaddr_reg:x3; val_offset:47250*0 + 3*390*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47250*0 + 3*390*FLEN/8, x4, x1, x2)

inst_15751:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0x47f0000; valaddr_reg:x3; val_offset:47253*0 + 3*391*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47253*0 + 3*391*FLEN/8, x4, x1, x2)

inst_15752:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0x47f8000; valaddr_reg:x3; val_offset:47256*0 + 3*392*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47256*0 + 3*392*FLEN/8, x4, x1, x2)

inst_15753:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0x47fc000; valaddr_reg:x3; val_offset:47259*0 + 3*393*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47259*0 + 3*393*FLEN/8, x4, x1, x2)

inst_15754:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0x47fe000; valaddr_reg:x3; val_offset:47262*0 + 3*394*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47262*0 + 3*394*FLEN/8, x4, x1, x2)

inst_15755:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0x47ff000; valaddr_reg:x3; val_offset:47265*0 + 3*395*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47265*0 + 3*395*FLEN/8, x4, x1, x2)

inst_15756:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0x47ff800; valaddr_reg:x3; val_offset:47268*0 + 3*396*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47268*0 + 3*396*FLEN/8, x4, x1, x2)

inst_15757:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0x47ffc00; valaddr_reg:x3; val_offset:47271*0 + 3*397*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47271*0 + 3*397*FLEN/8, x4, x1, x2)

inst_15758:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0x47ffe00; valaddr_reg:x3; val_offset:47274*0 + 3*398*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47274*0 + 3*398*FLEN/8, x4, x1, x2)

inst_15759:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0x47fff00; valaddr_reg:x3; val_offset:47277*0 + 3*399*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47277*0 + 3*399*FLEN/8, x4, x1, x2)

inst_15760:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0x47fff80; valaddr_reg:x3; val_offset:47280*0 + 3*400*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47280*0 + 3*400*FLEN/8, x4, x1, x2)

inst_15761:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0x47fffc0; valaddr_reg:x3; val_offset:47283*0 + 3*401*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47283*0 + 3*401*FLEN/8, x4, x1, x2)

inst_15762:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0x47fffe0; valaddr_reg:x3; val_offset:47286*0 + 3*402*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47286*0 + 3*402*FLEN/8, x4, x1, x2)

inst_15763:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0x47ffff0; valaddr_reg:x3; val_offset:47289*0 + 3*403*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47289*0 + 3*403*FLEN/8, x4, x1, x2)

inst_15764:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0x47ffff8; valaddr_reg:x3; val_offset:47292*0 + 3*404*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47292*0 + 3*404*FLEN/8, x4, x1, x2)

inst_15765:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0x47ffffc; valaddr_reg:x3; val_offset:47295*0 + 3*405*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47295*0 + 3*405*FLEN/8, x4, x1, x2)

inst_15766:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0x47ffffe; valaddr_reg:x3; val_offset:47298*0 + 3*406*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47298*0 + 3*406*FLEN/8, x4, x1, x2)

inst_15767:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1de0b9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x08 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9de0b9; op2val:0x0;
op3val:0x47fffff; valaddr_reg:x3; val_offset:47301*0 + 3*407*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47301*0 + 3*407*FLEN/8, x4, x1, x2)

inst_15768:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x1; valaddr_reg:x3; val_offset:47304*0 + 3*408*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47304*0 + 3*408*FLEN/8, x4, x1, x2)

inst_15769:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x3; valaddr_reg:x3; val_offset:47307*0 + 3*409*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47307*0 + 3*409*FLEN/8, x4, x1, x2)

inst_15770:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x7; valaddr_reg:x3; val_offset:47310*0 + 3*410*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47310*0 + 3*410*FLEN/8, x4, x1, x2)

inst_15771:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x199999; valaddr_reg:x3; val_offset:47313*0 + 3*411*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47313*0 + 3*411*FLEN/8, x4, x1, x2)

inst_15772:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x249249; valaddr_reg:x3; val_offset:47316*0 + 3*412*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47316*0 + 3*412*FLEN/8, x4, x1, x2)

inst_15773:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x333333; valaddr_reg:x3; val_offset:47319*0 + 3*413*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47319*0 + 3*413*FLEN/8, x4, x1, x2)

inst_15774:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x36db6d; valaddr_reg:x3; val_offset:47322*0 + 3*414*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47322*0 + 3*414*FLEN/8, x4, x1, x2)

inst_15775:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x3bbbbb; valaddr_reg:x3; val_offset:47325*0 + 3*415*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47325*0 + 3*415*FLEN/8, x4, x1, x2)

inst_15776:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x444444; valaddr_reg:x3; val_offset:47328*0 + 3*416*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47328*0 + 3*416*FLEN/8, x4, x1, x2)

inst_15777:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x4ccccc; valaddr_reg:x3; val_offset:47331*0 + 3*417*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47331*0 + 3*417*FLEN/8, x4, x1, x2)

inst_15778:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x5b6db6; valaddr_reg:x3; val_offset:47334*0 + 3*418*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47334*0 + 3*418*FLEN/8, x4, x1, x2)

inst_15779:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x666666; valaddr_reg:x3; val_offset:47337*0 + 3*419*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47337*0 + 3*419*FLEN/8, x4, x1, x2)

inst_15780:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x6db6db; valaddr_reg:x3; val_offset:47340*0 + 3*420*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47340*0 + 3*420*FLEN/8, x4, x1, x2)

inst_15781:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x7ffff8; valaddr_reg:x3; val_offset:47343*0 + 3*421*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47343*0 + 3*421*FLEN/8, x4, x1, x2)

inst_15782:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x7ffffc; valaddr_reg:x3; val_offset:47346*0 + 3*422*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47346*0 + 3*422*FLEN/8, x4, x1, x2)

inst_15783:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x7ffffe; valaddr_reg:x3; val_offset:47349*0 + 3*423*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47349*0 + 3*423*FLEN/8, x4, x1, x2)

inst_15784:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x6000000; valaddr_reg:x3; val_offset:47352*0 + 3*424*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47352*0 + 3*424*FLEN/8, x4, x1, x2)

inst_15785:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x6000001; valaddr_reg:x3; val_offset:47355*0 + 3*425*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47355*0 + 3*425*FLEN/8, x4, x1, x2)

inst_15786:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x6000003; valaddr_reg:x3; val_offset:47358*0 + 3*426*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47358*0 + 3*426*FLEN/8, x4, x1, x2)

inst_15787:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x6000007; valaddr_reg:x3; val_offset:47361*0 + 3*427*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47361*0 + 3*427*FLEN/8, x4, x1, x2)

inst_15788:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x600000f; valaddr_reg:x3; val_offset:47364*0 + 3*428*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47364*0 + 3*428*FLEN/8, x4, x1, x2)

inst_15789:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x600001f; valaddr_reg:x3; val_offset:47367*0 + 3*429*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47367*0 + 3*429*FLEN/8, x4, x1, x2)

inst_15790:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x600003f; valaddr_reg:x3; val_offset:47370*0 + 3*430*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47370*0 + 3*430*FLEN/8, x4, x1, x2)

inst_15791:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x600007f; valaddr_reg:x3; val_offset:47373*0 + 3*431*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47373*0 + 3*431*FLEN/8, x4, x1, x2)

inst_15792:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x60000ff; valaddr_reg:x3; val_offset:47376*0 + 3*432*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47376*0 + 3*432*FLEN/8, x4, x1, x2)

inst_15793:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x60001ff; valaddr_reg:x3; val_offset:47379*0 + 3*433*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47379*0 + 3*433*FLEN/8, x4, x1, x2)

inst_15794:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x60003ff; valaddr_reg:x3; val_offset:47382*0 + 3*434*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47382*0 + 3*434*FLEN/8, x4, x1, x2)

inst_15795:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x60007ff; valaddr_reg:x3; val_offset:47385*0 + 3*435*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47385*0 + 3*435*FLEN/8, x4, x1, x2)

inst_15796:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x6000fff; valaddr_reg:x3; val_offset:47388*0 + 3*436*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47388*0 + 3*436*FLEN/8, x4, x1, x2)

inst_15797:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x6001fff; valaddr_reg:x3; val_offset:47391*0 + 3*437*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47391*0 + 3*437*FLEN/8, x4, x1, x2)

inst_15798:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x6003fff; valaddr_reg:x3; val_offset:47394*0 + 3*438*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47394*0 + 3*438*FLEN/8, x4, x1, x2)

inst_15799:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x6007fff; valaddr_reg:x3; val_offset:47397*0 + 3*439*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47397*0 + 3*439*FLEN/8, x4, x1, x2)

inst_15800:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x600ffff; valaddr_reg:x3; val_offset:47400*0 + 3*440*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47400*0 + 3*440*FLEN/8, x4, x1, x2)

inst_15801:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x601ffff; valaddr_reg:x3; val_offset:47403*0 + 3*441*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47403*0 + 3*441*FLEN/8, x4, x1, x2)

inst_15802:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x603ffff; valaddr_reg:x3; val_offset:47406*0 + 3*442*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47406*0 + 3*442*FLEN/8, x4, x1, x2)

inst_15803:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x607ffff; valaddr_reg:x3; val_offset:47409*0 + 3*443*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47409*0 + 3*443*FLEN/8, x4, x1, x2)

inst_15804:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x60fffff; valaddr_reg:x3; val_offset:47412*0 + 3*444*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47412*0 + 3*444*FLEN/8, x4, x1, x2)

inst_15805:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x61fffff; valaddr_reg:x3; val_offset:47415*0 + 3*445*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47415*0 + 3*445*FLEN/8, x4, x1, x2)

inst_15806:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x63fffff; valaddr_reg:x3; val_offset:47418*0 + 3*446*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47418*0 + 3*446*FLEN/8, x4, x1, x2)

inst_15807:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x6400000; valaddr_reg:x3; val_offset:47421*0 + 3*447*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47421*0 + 3*447*FLEN/8, x4, x1, x2)

inst_15808:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x6600000; valaddr_reg:x3; val_offset:47424*0 + 3*448*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47424*0 + 3*448*FLEN/8, x4, x1, x2)

inst_15809:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x6700000; valaddr_reg:x3; val_offset:47427*0 + 3*449*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47427*0 + 3*449*FLEN/8, x4, x1, x2)

inst_15810:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x6780000; valaddr_reg:x3; val_offset:47430*0 + 3*450*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47430*0 + 3*450*FLEN/8, x4, x1, x2)

inst_15811:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x67c0000; valaddr_reg:x3; val_offset:47433*0 + 3*451*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47433*0 + 3*451*FLEN/8, x4, x1, x2)

inst_15812:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x67e0000; valaddr_reg:x3; val_offset:47436*0 + 3*452*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47436*0 + 3*452*FLEN/8, x4, x1, x2)

inst_15813:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x67f0000; valaddr_reg:x3; val_offset:47439*0 + 3*453*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47439*0 + 3*453*FLEN/8, x4, x1, x2)

inst_15814:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x67f8000; valaddr_reg:x3; val_offset:47442*0 + 3*454*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47442*0 + 3*454*FLEN/8, x4, x1, x2)

inst_15815:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x67fc000; valaddr_reg:x3; val_offset:47445*0 + 3*455*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47445*0 + 3*455*FLEN/8, x4, x1, x2)

inst_15816:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x67fe000; valaddr_reg:x3; val_offset:47448*0 + 3*456*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47448*0 + 3*456*FLEN/8, x4, x1, x2)

inst_15817:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x67ff000; valaddr_reg:x3; val_offset:47451*0 + 3*457*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47451*0 + 3*457*FLEN/8, x4, x1, x2)

inst_15818:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x67ff800; valaddr_reg:x3; val_offset:47454*0 + 3*458*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47454*0 + 3*458*FLEN/8, x4, x1, x2)

inst_15819:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x67ffc00; valaddr_reg:x3; val_offset:47457*0 + 3*459*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47457*0 + 3*459*FLEN/8, x4, x1, x2)

inst_15820:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x67ffe00; valaddr_reg:x3; val_offset:47460*0 + 3*460*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47460*0 + 3*460*FLEN/8, x4, x1, x2)

inst_15821:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x67fff00; valaddr_reg:x3; val_offset:47463*0 + 3*461*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47463*0 + 3*461*FLEN/8, x4, x1, x2)

inst_15822:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x67fff80; valaddr_reg:x3; val_offset:47466*0 + 3*462*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47466*0 + 3*462*FLEN/8, x4, x1, x2)

inst_15823:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x67fffc0; valaddr_reg:x3; val_offset:47469*0 + 3*463*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47469*0 + 3*463*FLEN/8, x4, x1, x2)

inst_15824:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x67fffe0; valaddr_reg:x3; val_offset:47472*0 + 3*464*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47472*0 + 3*464*FLEN/8, x4, x1, x2)

inst_15825:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x67ffff0; valaddr_reg:x3; val_offset:47475*0 + 3*465*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47475*0 + 3*465*FLEN/8, x4, x1, x2)

inst_15826:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x67ffff8; valaddr_reg:x3; val_offset:47478*0 + 3*466*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47478*0 + 3*466*FLEN/8, x4, x1, x2)

inst_15827:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x67ffffc; valaddr_reg:x3; val_offset:47481*0 + 3*467*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47481*0 + 3*467*FLEN/8, x4, x1, x2)

inst_15828:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x67ffffe; valaddr_reg:x3; val_offset:47484*0 + 3*468*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47484*0 + 3*468*FLEN/8, x4, x1, x2)

inst_15829:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f40ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0c and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f40ca; op2val:0x0;
op3val:0x67fffff; valaddr_reg:x3; val_offset:47487*0 + 3*469*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47487*0 + 3*469*FLEN/8, x4, x1, x2)

inst_15830:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfa and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xfd000000; valaddr_reg:x3; val_offset:47490*0 + 3*470*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47490*0 + 3*470*FLEN/8, x4, x1, x2)

inst_15831:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfa and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xfd000001; valaddr_reg:x3; val_offset:47493*0 + 3*471*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47493*0 + 3*471*FLEN/8, x4, x1, x2)

inst_15832:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfa and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xfd000003; valaddr_reg:x3; val_offset:47496*0 + 3*472*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47496*0 + 3*472*FLEN/8, x4, x1, x2)

inst_15833:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfa and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xfd000007; valaddr_reg:x3; val_offset:47499*0 + 3*473*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47499*0 + 3*473*FLEN/8, x4, x1, x2)

inst_15834:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfa and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xfd00000f; valaddr_reg:x3; val_offset:47502*0 + 3*474*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47502*0 + 3*474*FLEN/8, x4, x1, x2)

inst_15835:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfa and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xfd00001f; valaddr_reg:x3; val_offset:47505*0 + 3*475*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47505*0 + 3*475*FLEN/8, x4, x1, x2)

inst_15836:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfa and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xfd00003f; valaddr_reg:x3; val_offset:47508*0 + 3*476*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47508*0 + 3*476*FLEN/8, x4, x1, x2)

inst_15837:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfa and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xfd00007f; valaddr_reg:x3; val_offset:47511*0 + 3*477*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47511*0 + 3*477*FLEN/8, x4, x1, x2)

inst_15838:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfa and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xfd0000ff; valaddr_reg:x3; val_offset:47514*0 + 3*478*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47514*0 + 3*478*FLEN/8, x4, x1, x2)

inst_15839:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfa and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xfd0001ff; valaddr_reg:x3; val_offset:47517*0 + 3*479*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47517*0 + 3*479*FLEN/8, x4, x1, x2)

inst_15840:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfa and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xfd0003ff; valaddr_reg:x3; val_offset:47520*0 + 3*480*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47520*0 + 3*480*FLEN/8, x4, x1, x2)

inst_15841:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfa and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xfd0007ff; valaddr_reg:x3; val_offset:47523*0 + 3*481*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47523*0 + 3*481*FLEN/8, x4, x1, x2)

inst_15842:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfa and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xfd000fff; valaddr_reg:x3; val_offset:47526*0 + 3*482*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47526*0 + 3*482*FLEN/8, x4, x1, x2)

inst_15843:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfa and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xfd001fff; valaddr_reg:x3; val_offset:47529*0 + 3*483*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47529*0 + 3*483*FLEN/8, x4, x1, x2)

inst_15844:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfa and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xfd003fff; valaddr_reg:x3; val_offset:47532*0 + 3*484*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47532*0 + 3*484*FLEN/8, x4, x1, x2)

inst_15845:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfa and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xfd007fff; valaddr_reg:x3; val_offset:47535*0 + 3*485*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47535*0 + 3*485*FLEN/8, x4, x1, x2)

inst_15846:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfa and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xfd00ffff; valaddr_reg:x3; val_offset:47538*0 + 3*486*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47538*0 + 3*486*FLEN/8, x4, x1, x2)

inst_15847:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfa and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xfd01ffff; valaddr_reg:x3; val_offset:47541*0 + 3*487*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47541*0 + 3*487*FLEN/8, x4, x1, x2)

inst_15848:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfa and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xfd03ffff; valaddr_reg:x3; val_offset:47544*0 + 3*488*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47544*0 + 3*488*FLEN/8, x4, x1, x2)

inst_15849:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfa and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xfd07ffff; valaddr_reg:x3; val_offset:47547*0 + 3*489*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47547*0 + 3*489*FLEN/8, x4, x1, x2)

inst_15850:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfa and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xfd0fffff; valaddr_reg:x3; val_offset:47550*0 + 3*490*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47550*0 + 3*490*FLEN/8, x4, x1, x2)

inst_15851:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfa and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xfd1fffff; valaddr_reg:x3; val_offset:47553*0 + 3*491*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47553*0 + 3*491*FLEN/8, x4, x1, x2)

inst_15852:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfa and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xfd3fffff; valaddr_reg:x3; val_offset:47556*0 + 3*492*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47556*0 + 3*492*FLEN/8, x4, x1, x2)

inst_15853:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfa and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xfd400000; valaddr_reg:x3; val_offset:47559*0 + 3*493*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47559*0 + 3*493*FLEN/8, x4, x1, x2)

inst_15854:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfa and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xfd600000; valaddr_reg:x3; val_offset:47562*0 + 3*494*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47562*0 + 3*494*FLEN/8, x4, x1, x2)

inst_15855:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfa and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xfd700000; valaddr_reg:x3; val_offset:47565*0 + 3*495*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47565*0 + 3*495*FLEN/8, x4, x1, x2)

inst_15856:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfa and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xfd780000; valaddr_reg:x3; val_offset:47568*0 + 3*496*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47568*0 + 3*496*FLEN/8, x4, x1, x2)

inst_15857:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfa and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xfd7c0000; valaddr_reg:x3; val_offset:47571*0 + 3*497*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47571*0 + 3*497*FLEN/8, x4, x1, x2)

inst_15858:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfa and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xfd7e0000; valaddr_reg:x3; val_offset:47574*0 + 3*498*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47574*0 + 3*498*FLEN/8, x4, x1, x2)

inst_15859:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfa and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xfd7f0000; valaddr_reg:x3; val_offset:47577*0 + 3*499*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47577*0 + 3*499*FLEN/8, x4, x1, x2)

inst_15860:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfa and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xfd7f8000; valaddr_reg:x3; val_offset:47580*0 + 3*500*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47580*0 + 3*500*FLEN/8, x4, x1, x2)

inst_15861:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfa and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xfd7fc000; valaddr_reg:x3; val_offset:47583*0 + 3*501*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47583*0 + 3*501*FLEN/8, x4, x1, x2)

inst_15862:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfa and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xfd7fe000; valaddr_reg:x3; val_offset:47586*0 + 3*502*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47586*0 + 3*502*FLEN/8, x4, x1, x2)

inst_15863:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfa and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xfd7ff000; valaddr_reg:x3; val_offset:47589*0 + 3*503*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47589*0 + 3*503*FLEN/8, x4, x1, x2)

inst_15864:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfa and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xfd7ff800; valaddr_reg:x3; val_offset:47592*0 + 3*504*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47592*0 + 3*504*FLEN/8, x4, x1, x2)

inst_15865:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfa and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xfd7ffc00; valaddr_reg:x3; val_offset:47595*0 + 3*505*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47595*0 + 3*505*FLEN/8, x4, x1, x2)

inst_15866:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfa and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xfd7ffe00; valaddr_reg:x3; val_offset:47598*0 + 3*506*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47598*0 + 3*506*FLEN/8, x4, x1, x2)

inst_15867:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfa and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xfd7fff00; valaddr_reg:x3; val_offset:47601*0 + 3*507*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47601*0 + 3*507*FLEN/8, x4, x1, x2)

inst_15868:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfa and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xfd7fff80; valaddr_reg:x3; val_offset:47604*0 + 3*508*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47604*0 + 3*508*FLEN/8, x4, x1, x2)

inst_15869:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfa and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xfd7fffc0; valaddr_reg:x3; val_offset:47607*0 + 3*509*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47607*0 + 3*509*FLEN/8, x4, x1, x2)

inst_15870:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfa and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xfd7fffe0; valaddr_reg:x3; val_offset:47610*0 + 3*510*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47610*0 + 3*510*FLEN/8, x4, x1, x2)

inst_15871:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfa and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xfd7ffff0; valaddr_reg:x3; val_offset:47613*0 + 3*511*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47613*0 + 3*511*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_5)

inst_15872:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfa and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xfd7ffff8; valaddr_reg:x3; val_offset:47616*0 + 3*512*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47616*0 + 3*512*FLEN/8, x4, x1, x2)

inst_15873:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfa and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xfd7ffffc; valaddr_reg:x3; val_offset:47619*0 + 3*513*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47619*0 + 3*513*FLEN/8, x4, x1, x2)

inst_15874:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfa and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xfd7ffffe; valaddr_reg:x3; val_offset:47622*0 + 3*514*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47622*0 + 3*514*FLEN/8, x4, x1, x2)

inst_15875:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfa and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xfd7fffff; valaddr_reg:x3; val_offset:47625*0 + 3*515*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47625*0 + 3*515*FLEN/8, x4, x1, x2)

inst_15876:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xff000001; valaddr_reg:x3; val_offset:47628*0 + 3*516*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47628*0 + 3*516*FLEN/8, x4, x1, x2)

inst_15877:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xff000003; valaddr_reg:x3; val_offset:47631*0 + 3*517*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47631*0 + 3*517*FLEN/8, x4, x1, x2)

inst_15878:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xff000007; valaddr_reg:x3; val_offset:47634*0 + 3*518*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47634*0 + 3*518*FLEN/8, x4, x1, x2)

inst_15879:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xff199999; valaddr_reg:x3; val_offset:47637*0 + 3*519*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47637*0 + 3*519*FLEN/8, x4, x1, x2)

inst_15880:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xff249249; valaddr_reg:x3; val_offset:47640*0 + 3*520*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47640*0 + 3*520*FLEN/8, x4, x1, x2)

inst_15881:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xff333333; valaddr_reg:x3; val_offset:47643*0 + 3*521*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47643*0 + 3*521*FLEN/8, x4, x1, x2)

inst_15882:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xff36db6d; valaddr_reg:x3; val_offset:47646*0 + 3*522*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47646*0 + 3*522*FLEN/8, x4, x1, x2)

inst_15883:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xff3bbbbb; valaddr_reg:x3; val_offset:47649*0 + 3*523*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47649*0 + 3*523*FLEN/8, x4, x1, x2)

inst_15884:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xff444444; valaddr_reg:x3; val_offset:47652*0 + 3*524*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47652*0 + 3*524*FLEN/8, x4, x1, x2)

inst_15885:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xff4ccccc; valaddr_reg:x3; val_offset:47655*0 + 3*525*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47655*0 + 3*525*FLEN/8, x4, x1, x2)

inst_15886:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xff5b6db6; valaddr_reg:x3; val_offset:47658*0 + 3*526*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47658*0 + 3*526*FLEN/8, x4, x1, x2)

inst_15887:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xff666666; valaddr_reg:x3; val_offset:47661*0 + 3*527*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47661*0 + 3*527*FLEN/8, x4, x1, x2)

inst_15888:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xff6db6db; valaddr_reg:x3; val_offset:47664*0 + 3*528*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47664*0 + 3*528*FLEN/8, x4, x1, x2)

inst_15889:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xff7ffff8; valaddr_reg:x3; val_offset:47667*0 + 3*529*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47667*0 + 3*529*FLEN/8, x4, x1, x2)

inst_15890:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xff7ffffc; valaddr_reg:x3; val_offset:47670*0 + 3*530*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47670*0 + 3*530*FLEN/8, x4, x1, x2)

inst_15891:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f4b7c and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4db4e0 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f4b7c; op2val:0xc04db4e0;
op3val:0xff7ffffe; valaddr_reg:x3; val_offset:47673*0 + 3*531*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47673*0 + 3*531*FLEN/8, x4, x1, x2)

inst_15892:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x64 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xb2000000; valaddr_reg:x3; val_offset:47676*0 + 3*532*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47676*0 + 3*532*FLEN/8, x4, x1, x2)

inst_15893:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x64 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xb2000001; valaddr_reg:x3; val_offset:47679*0 + 3*533*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47679*0 + 3*533*FLEN/8, x4, x1, x2)

inst_15894:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x64 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xb2000003; valaddr_reg:x3; val_offset:47682*0 + 3*534*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47682*0 + 3*534*FLEN/8, x4, x1, x2)

inst_15895:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x64 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xb2000007; valaddr_reg:x3; val_offset:47685*0 + 3*535*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47685*0 + 3*535*FLEN/8, x4, x1, x2)

inst_15896:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x64 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xb200000f; valaddr_reg:x3; val_offset:47688*0 + 3*536*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47688*0 + 3*536*FLEN/8, x4, x1, x2)

inst_15897:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x64 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xb200001f; valaddr_reg:x3; val_offset:47691*0 + 3*537*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47691*0 + 3*537*FLEN/8, x4, x1, x2)

inst_15898:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x64 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xb200003f; valaddr_reg:x3; val_offset:47694*0 + 3*538*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47694*0 + 3*538*FLEN/8, x4, x1, x2)

inst_15899:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x64 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xb200007f; valaddr_reg:x3; val_offset:47697*0 + 3*539*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47697*0 + 3*539*FLEN/8, x4, x1, x2)

inst_15900:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x64 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xb20000ff; valaddr_reg:x3; val_offset:47700*0 + 3*540*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47700*0 + 3*540*FLEN/8, x4, x1, x2)

inst_15901:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x64 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xb20001ff; valaddr_reg:x3; val_offset:47703*0 + 3*541*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47703*0 + 3*541*FLEN/8, x4, x1, x2)

inst_15902:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x64 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xb20003ff; valaddr_reg:x3; val_offset:47706*0 + 3*542*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47706*0 + 3*542*FLEN/8, x4, x1, x2)

inst_15903:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x64 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xb20007ff; valaddr_reg:x3; val_offset:47709*0 + 3*543*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47709*0 + 3*543*FLEN/8, x4, x1, x2)

inst_15904:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x64 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xb2000fff; valaddr_reg:x3; val_offset:47712*0 + 3*544*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47712*0 + 3*544*FLEN/8, x4, x1, x2)

inst_15905:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x64 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xb2001fff; valaddr_reg:x3; val_offset:47715*0 + 3*545*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47715*0 + 3*545*FLEN/8, x4, x1, x2)

inst_15906:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x64 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xb2003fff; valaddr_reg:x3; val_offset:47718*0 + 3*546*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47718*0 + 3*546*FLEN/8, x4, x1, x2)

inst_15907:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x64 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xb2007fff; valaddr_reg:x3; val_offset:47721*0 + 3*547*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47721*0 + 3*547*FLEN/8, x4, x1, x2)

inst_15908:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x64 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xb200ffff; valaddr_reg:x3; val_offset:47724*0 + 3*548*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47724*0 + 3*548*FLEN/8, x4, x1, x2)

inst_15909:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x64 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xb201ffff; valaddr_reg:x3; val_offset:47727*0 + 3*549*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47727*0 + 3*549*FLEN/8, x4, x1, x2)

inst_15910:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x64 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xb203ffff; valaddr_reg:x3; val_offset:47730*0 + 3*550*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47730*0 + 3*550*FLEN/8, x4, x1, x2)

inst_15911:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x64 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xb207ffff; valaddr_reg:x3; val_offset:47733*0 + 3*551*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47733*0 + 3*551*FLEN/8, x4, x1, x2)

inst_15912:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x64 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xb20fffff; valaddr_reg:x3; val_offset:47736*0 + 3*552*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47736*0 + 3*552*FLEN/8, x4, x1, x2)

inst_15913:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x64 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xb21fffff; valaddr_reg:x3; val_offset:47739*0 + 3*553*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47739*0 + 3*553*FLEN/8, x4, x1, x2)

inst_15914:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x64 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xb23fffff; valaddr_reg:x3; val_offset:47742*0 + 3*554*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47742*0 + 3*554*FLEN/8, x4, x1, x2)

inst_15915:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x64 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xb2400000; valaddr_reg:x3; val_offset:47745*0 + 3*555*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47745*0 + 3*555*FLEN/8, x4, x1, x2)

inst_15916:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x64 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xb2600000; valaddr_reg:x3; val_offset:47748*0 + 3*556*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47748*0 + 3*556*FLEN/8, x4, x1, x2)

inst_15917:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x64 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xb2700000; valaddr_reg:x3; val_offset:47751*0 + 3*557*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47751*0 + 3*557*FLEN/8, x4, x1, x2)

inst_15918:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x64 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xb2780000; valaddr_reg:x3; val_offset:47754*0 + 3*558*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47754*0 + 3*558*FLEN/8, x4, x1, x2)

inst_15919:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x64 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xb27c0000; valaddr_reg:x3; val_offset:47757*0 + 3*559*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47757*0 + 3*559*FLEN/8, x4, x1, x2)

inst_15920:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x64 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xb27e0000; valaddr_reg:x3; val_offset:47760*0 + 3*560*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47760*0 + 3*560*FLEN/8, x4, x1, x2)

inst_15921:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x64 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xb27f0000; valaddr_reg:x3; val_offset:47763*0 + 3*561*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47763*0 + 3*561*FLEN/8, x4, x1, x2)

inst_15922:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x64 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xb27f8000; valaddr_reg:x3; val_offset:47766*0 + 3*562*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47766*0 + 3*562*FLEN/8, x4, x1, x2)

inst_15923:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x64 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xb27fc000; valaddr_reg:x3; val_offset:47769*0 + 3*563*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47769*0 + 3*563*FLEN/8, x4, x1, x2)

inst_15924:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x64 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xb27fe000; valaddr_reg:x3; val_offset:47772*0 + 3*564*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47772*0 + 3*564*FLEN/8, x4, x1, x2)

inst_15925:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x64 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xb27ff000; valaddr_reg:x3; val_offset:47775*0 + 3*565*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47775*0 + 3*565*FLEN/8, x4, x1, x2)

inst_15926:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x64 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xb27ff800; valaddr_reg:x3; val_offset:47778*0 + 3*566*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47778*0 + 3*566*FLEN/8, x4, x1, x2)

inst_15927:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x64 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xb27ffc00; valaddr_reg:x3; val_offset:47781*0 + 3*567*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47781*0 + 3*567*FLEN/8, x4, x1, x2)

inst_15928:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x64 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xb27ffe00; valaddr_reg:x3; val_offset:47784*0 + 3*568*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47784*0 + 3*568*FLEN/8, x4, x1, x2)

inst_15929:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x64 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xb27fff00; valaddr_reg:x3; val_offset:47787*0 + 3*569*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47787*0 + 3*569*FLEN/8, x4, x1, x2)

inst_15930:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x64 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xb27fff80; valaddr_reg:x3; val_offset:47790*0 + 3*570*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47790*0 + 3*570*FLEN/8, x4, x1, x2)

inst_15931:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x64 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xb27fffc0; valaddr_reg:x3; val_offset:47793*0 + 3*571*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47793*0 + 3*571*FLEN/8, x4, x1, x2)

inst_15932:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x64 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xb27fffe0; valaddr_reg:x3; val_offset:47796*0 + 3*572*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47796*0 + 3*572*FLEN/8, x4, x1, x2)

inst_15933:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x64 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xb27ffff0; valaddr_reg:x3; val_offset:47799*0 + 3*573*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47799*0 + 3*573*FLEN/8, x4, x1, x2)

inst_15934:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x64 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xb27ffff8; valaddr_reg:x3; val_offset:47802*0 + 3*574*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47802*0 + 3*574*FLEN/8, x4, x1, x2)

inst_15935:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x64 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xb27ffffc; valaddr_reg:x3; val_offset:47805*0 + 3*575*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47805*0 + 3*575*FLEN/8, x4, x1, x2)

inst_15936:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x64 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xb27ffffe; valaddr_reg:x3; val_offset:47808*0 + 3*576*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47808*0 + 3*576*FLEN/8, x4, x1, x2)

inst_15937:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x64 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xb27fffff; valaddr_reg:x3; val_offset:47811*0 + 3*577*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47811*0 + 3*577*FLEN/8, x4, x1, x2)

inst_15938:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xbf800001; valaddr_reg:x3; val_offset:47814*0 + 3*578*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47814*0 + 3*578*FLEN/8, x4, x1, x2)

inst_15939:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xbf800003; valaddr_reg:x3; val_offset:47817*0 + 3*579*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47817*0 + 3*579*FLEN/8, x4, x1, x2)

inst_15940:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xbf800007; valaddr_reg:x3; val_offset:47820*0 + 3*580*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47820*0 + 3*580*FLEN/8, x4, x1, x2)

inst_15941:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xbf999999; valaddr_reg:x3; val_offset:47823*0 + 3*581*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47823*0 + 3*581*FLEN/8, x4, x1, x2)

inst_15942:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xbfa49249; valaddr_reg:x3; val_offset:47826*0 + 3*582*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47826*0 + 3*582*FLEN/8, x4, x1, x2)

inst_15943:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xbfb33333; valaddr_reg:x3; val_offset:47829*0 + 3*583*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47829*0 + 3*583*FLEN/8, x4, x1, x2)

inst_15944:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xbfb6db6d; valaddr_reg:x3; val_offset:47832*0 + 3*584*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47832*0 + 3*584*FLEN/8, x4, x1, x2)

inst_15945:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xbfbbbbbb; valaddr_reg:x3; val_offset:47835*0 + 3*585*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47835*0 + 3*585*FLEN/8, x4, x1, x2)

inst_15946:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xbfc44444; valaddr_reg:x3; val_offset:47838*0 + 3*586*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47838*0 + 3*586*FLEN/8, x4, x1, x2)

inst_15947:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xbfcccccc; valaddr_reg:x3; val_offset:47841*0 + 3*587*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47841*0 + 3*587*FLEN/8, x4, x1, x2)

inst_15948:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xbfdb6db6; valaddr_reg:x3; val_offset:47844*0 + 3*588*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47844*0 + 3*588*FLEN/8, x4, x1, x2)

inst_15949:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xbfe66666; valaddr_reg:x3; val_offset:47847*0 + 3*589*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47847*0 + 3*589*FLEN/8, x4, x1, x2)

inst_15950:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xbfedb6db; valaddr_reg:x3; val_offset:47850*0 + 3*590*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47850*0 + 3*590*FLEN/8, x4, x1, x2)

inst_15951:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xbffffff8; valaddr_reg:x3; val_offset:47853*0 + 3*591*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47853*0 + 3*591*FLEN/8, x4, x1, x2)

inst_15952:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xbffffffc; valaddr_reg:x3; val_offset:47856*0 + 3*592*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47856*0 + 3*592*FLEN/8, x4, x1, x2)

inst_15953:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f69aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x66c6f7 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f69aa; op2val:0x8066c6f7;
op3val:0xbffffffe; valaddr_reg:x3; val_offset:47859*0 + 3*593*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47859*0 + 3*593*FLEN/8, x4, x1, x2)

inst_15954:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x80800001; valaddr_reg:x3; val_offset:47862*0 + 3*594*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47862*0 + 3*594*FLEN/8, x4, x1, x2)

inst_15955:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x80800003; valaddr_reg:x3; val_offset:47865*0 + 3*595*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47865*0 + 3*595*FLEN/8, x4, x1, x2)

inst_15956:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x80800007; valaddr_reg:x3; val_offset:47868*0 + 3*596*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47868*0 + 3*596*FLEN/8, x4, x1, x2)

inst_15957:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x80999999; valaddr_reg:x3; val_offset:47871*0 + 3*597*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47871*0 + 3*597*FLEN/8, x4, x1, x2)

inst_15958:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x80a49249; valaddr_reg:x3; val_offset:47874*0 + 3*598*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47874*0 + 3*598*FLEN/8, x4, x1, x2)

inst_15959:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x80b33333; valaddr_reg:x3; val_offset:47877*0 + 3*599*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47877*0 + 3*599*FLEN/8, x4, x1, x2)

inst_15960:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x80b6db6d; valaddr_reg:x3; val_offset:47880*0 + 3*600*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47880*0 + 3*600*FLEN/8, x4, x1, x2)

inst_15961:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x80bbbbbb; valaddr_reg:x3; val_offset:47883*0 + 3*601*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47883*0 + 3*601*FLEN/8, x4, x1, x2)

inst_15962:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x80c44444; valaddr_reg:x3; val_offset:47886*0 + 3*602*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47886*0 + 3*602*FLEN/8, x4, x1, x2)

inst_15963:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x80cccccc; valaddr_reg:x3; val_offset:47889*0 + 3*603*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47889*0 + 3*603*FLEN/8, x4, x1, x2)

inst_15964:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x80db6db6; valaddr_reg:x3; val_offset:47892*0 + 3*604*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47892*0 + 3*604*FLEN/8, x4, x1, x2)

inst_15965:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x80e66666; valaddr_reg:x3; val_offset:47895*0 + 3*605*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47895*0 + 3*605*FLEN/8, x4, x1, x2)

inst_15966:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x80edb6db; valaddr_reg:x3; val_offset:47898*0 + 3*606*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47898*0 + 3*606*FLEN/8, x4, x1, x2)

inst_15967:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x80fffff8; valaddr_reg:x3; val_offset:47901*0 + 3*607*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47901*0 + 3*607*FLEN/8, x4, x1, x2)

inst_15968:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x80fffffc; valaddr_reg:x3; val_offset:47904*0 + 3*608*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47904*0 + 3*608*FLEN/8, x4, x1, x2)

inst_15969:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x80fffffe; valaddr_reg:x3; val_offset:47907*0 + 3*609*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47907*0 + 3*609*FLEN/8, x4, x1, x2)

inst_15970:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x8f800000; valaddr_reg:x3; val_offset:47910*0 + 3*610*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47910*0 + 3*610*FLEN/8, x4, x1, x2)

inst_15971:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x8f800001; valaddr_reg:x3; val_offset:47913*0 + 3*611*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47913*0 + 3*611*FLEN/8, x4, x1, x2)

inst_15972:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x8f800003; valaddr_reg:x3; val_offset:47916*0 + 3*612*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47916*0 + 3*612*FLEN/8, x4, x1, x2)

inst_15973:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x8f800007; valaddr_reg:x3; val_offset:47919*0 + 3*613*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47919*0 + 3*613*FLEN/8, x4, x1, x2)

inst_15974:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x8f80000f; valaddr_reg:x3; val_offset:47922*0 + 3*614*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47922*0 + 3*614*FLEN/8, x4, x1, x2)

inst_15975:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x8f80001f; valaddr_reg:x3; val_offset:47925*0 + 3*615*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47925*0 + 3*615*FLEN/8, x4, x1, x2)

inst_15976:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x8f80003f; valaddr_reg:x3; val_offset:47928*0 + 3*616*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47928*0 + 3*616*FLEN/8, x4, x1, x2)

inst_15977:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x8f80007f; valaddr_reg:x3; val_offset:47931*0 + 3*617*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47931*0 + 3*617*FLEN/8, x4, x1, x2)

inst_15978:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x8f8000ff; valaddr_reg:x3; val_offset:47934*0 + 3*618*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47934*0 + 3*618*FLEN/8, x4, x1, x2)

inst_15979:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x8f8001ff; valaddr_reg:x3; val_offset:47937*0 + 3*619*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47937*0 + 3*619*FLEN/8, x4, x1, x2)

inst_15980:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x8f8003ff; valaddr_reg:x3; val_offset:47940*0 + 3*620*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47940*0 + 3*620*FLEN/8, x4, x1, x2)

inst_15981:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x8f8007ff; valaddr_reg:x3; val_offset:47943*0 + 3*621*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47943*0 + 3*621*FLEN/8, x4, x1, x2)

inst_15982:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x8f800fff; valaddr_reg:x3; val_offset:47946*0 + 3*622*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47946*0 + 3*622*FLEN/8, x4, x1, x2)

inst_15983:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x8f801fff; valaddr_reg:x3; val_offset:47949*0 + 3*623*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47949*0 + 3*623*FLEN/8, x4, x1, x2)

inst_15984:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x8f803fff; valaddr_reg:x3; val_offset:47952*0 + 3*624*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47952*0 + 3*624*FLEN/8, x4, x1, x2)

inst_15985:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x8f807fff; valaddr_reg:x3; val_offset:47955*0 + 3*625*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47955*0 + 3*625*FLEN/8, x4, x1, x2)

inst_15986:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x8f80ffff; valaddr_reg:x3; val_offset:47958*0 + 3*626*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47958*0 + 3*626*FLEN/8, x4, x1, x2)

inst_15987:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x8f81ffff; valaddr_reg:x3; val_offset:47961*0 + 3*627*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47961*0 + 3*627*FLEN/8, x4, x1, x2)

inst_15988:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x8f83ffff; valaddr_reg:x3; val_offset:47964*0 + 3*628*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47964*0 + 3*628*FLEN/8, x4, x1, x2)

inst_15989:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x8f87ffff; valaddr_reg:x3; val_offset:47967*0 + 3*629*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47967*0 + 3*629*FLEN/8, x4, x1, x2)

inst_15990:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x8f8fffff; valaddr_reg:x3; val_offset:47970*0 + 3*630*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47970*0 + 3*630*FLEN/8, x4, x1, x2)

inst_15991:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x8f9fffff; valaddr_reg:x3; val_offset:47973*0 + 3*631*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47973*0 + 3*631*FLEN/8, x4, x1, x2)

inst_15992:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x8fbfffff; valaddr_reg:x3; val_offset:47976*0 + 3*632*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47976*0 + 3*632*FLEN/8, x4, x1, x2)

inst_15993:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x8fc00000; valaddr_reg:x3; val_offset:47979*0 + 3*633*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47979*0 + 3*633*FLEN/8, x4, x1, x2)

inst_15994:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x8fe00000; valaddr_reg:x3; val_offset:47982*0 + 3*634*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47982*0 + 3*634*FLEN/8, x4, x1, x2)

inst_15995:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x8ff00000; valaddr_reg:x3; val_offset:47985*0 + 3*635*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47985*0 + 3*635*FLEN/8, x4, x1, x2)

inst_15996:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x8ff80000; valaddr_reg:x3; val_offset:47988*0 + 3*636*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47988*0 + 3*636*FLEN/8, x4, x1, x2)

inst_15997:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x8ffc0000; valaddr_reg:x3; val_offset:47991*0 + 3*637*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47991*0 + 3*637*FLEN/8, x4, x1, x2)

inst_15998:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x8ffe0000; valaddr_reg:x3; val_offset:47994*0 + 3*638*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47994*0 + 3*638*FLEN/8, x4, x1, x2)

inst_15999:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x8fff0000; valaddr_reg:x3; val_offset:47997*0 + 3*639*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 47997*0 + 3*639*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_6)

inst_16000:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x8fff8000; valaddr_reg:x3; val_offset:48000*0 + 3*640*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48000*0 + 3*640*FLEN/8, x4, x1, x2)

inst_16001:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x8fffc000; valaddr_reg:x3; val_offset:48003*0 + 3*641*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48003*0 + 3*641*FLEN/8, x4, x1, x2)

inst_16002:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x8fffe000; valaddr_reg:x3; val_offset:48006*0 + 3*642*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48006*0 + 3*642*FLEN/8, x4, x1, x2)

inst_16003:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x8ffff000; valaddr_reg:x3; val_offset:48009*0 + 3*643*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48009*0 + 3*643*FLEN/8, x4, x1, x2)

inst_16004:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x8ffff800; valaddr_reg:x3; val_offset:48012*0 + 3*644*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48012*0 + 3*644*FLEN/8, x4, x1, x2)

inst_16005:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x8ffffc00; valaddr_reg:x3; val_offset:48015*0 + 3*645*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48015*0 + 3*645*FLEN/8, x4, x1, x2)

inst_16006:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x8ffffe00; valaddr_reg:x3; val_offset:48018*0 + 3*646*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48018*0 + 3*646*FLEN/8, x4, x1, x2)

inst_16007:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x8fffff00; valaddr_reg:x3; val_offset:48021*0 + 3*647*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48021*0 + 3*647*FLEN/8, x4, x1, x2)

inst_16008:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x8fffff80; valaddr_reg:x3; val_offset:48024*0 + 3*648*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48024*0 + 3*648*FLEN/8, x4, x1, x2)

inst_16009:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x8fffffc0; valaddr_reg:x3; val_offset:48027*0 + 3*649*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48027*0 + 3*649*FLEN/8, x4, x1, x2)

inst_16010:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x8fffffe0; valaddr_reg:x3; val_offset:48030*0 + 3*650*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48030*0 + 3*650*FLEN/8, x4, x1, x2)

inst_16011:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x8ffffff0; valaddr_reg:x3; val_offset:48033*0 + 3*651*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48033*0 + 3*651*FLEN/8, x4, x1, x2)

inst_16012:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x8ffffff8; valaddr_reg:x3; val_offset:48036*0 + 3*652*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48036*0 + 3*652*FLEN/8, x4, x1, x2)

inst_16013:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x8ffffffc; valaddr_reg:x3; val_offset:48039*0 + 3*653*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48039*0 + 3*653*FLEN/8, x4, x1, x2)

inst_16014:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x8ffffffe; valaddr_reg:x3; val_offset:48042*0 + 3*654*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48042*0 + 3*654*FLEN/8, x4, x1, x2)

inst_16015:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1f9b30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9f9b30; op2val:0x80000000;
op3val:0x8fffffff; valaddr_reg:x3; val_offset:48045*0 + 3*655*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48045*0 + 3*655*FLEN/8, x4, x1, x2)

inst_16016:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xf6 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7b000000; valaddr_reg:x3; val_offset:48048*0 + 3*656*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48048*0 + 3*656*FLEN/8, x4, x1, x2)

inst_16017:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xf6 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7b000001; valaddr_reg:x3; val_offset:48051*0 + 3*657*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48051*0 + 3*657*FLEN/8, x4, x1, x2)

inst_16018:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xf6 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7b000003; valaddr_reg:x3; val_offset:48054*0 + 3*658*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48054*0 + 3*658*FLEN/8, x4, x1, x2)

inst_16019:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xf6 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7b000007; valaddr_reg:x3; val_offset:48057*0 + 3*659*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48057*0 + 3*659*FLEN/8, x4, x1, x2)

inst_16020:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xf6 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7b00000f; valaddr_reg:x3; val_offset:48060*0 + 3*660*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48060*0 + 3*660*FLEN/8, x4, x1, x2)

inst_16021:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xf6 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7b00001f; valaddr_reg:x3; val_offset:48063*0 + 3*661*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48063*0 + 3*661*FLEN/8, x4, x1, x2)

inst_16022:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xf6 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7b00003f; valaddr_reg:x3; val_offset:48066*0 + 3*662*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48066*0 + 3*662*FLEN/8, x4, x1, x2)

inst_16023:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xf6 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7b00007f; valaddr_reg:x3; val_offset:48069*0 + 3*663*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48069*0 + 3*663*FLEN/8, x4, x1, x2)

inst_16024:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xf6 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7b0000ff; valaddr_reg:x3; val_offset:48072*0 + 3*664*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48072*0 + 3*664*FLEN/8, x4, x1, x2)

inst_16025:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xf6 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7b0001ff; valaddr_reg:x3; val_offset:48075*0 + 3*665*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48075*0 + 3*665*FLEN/8, x4, x1, x2)

inst_16026:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xf6 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7b0003ff; valaddr_reg:x3; val_offset:48078*0 + 3*666*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48078*0 + 3*666*FLEN/8, x4, x1, x2)

inst_16027:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xf6 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7b0007ff; valaddr_reg:x3; val_offset:48081*0 + 3*667*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48081*0 + 3*667*FLEN/8, x4, x1, x2)

inst_16028:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xf6 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7b000fff; valaddr_reg:x3; val_offset:48084*0 + 3*668*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48084*0 + 3*668*FLEN/8, x4, x1, x2)

inst_16029:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xf6 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7b001fff; valaddr_reg:x3; val_offset:48087*0 + 3*669*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48087*0 + 3*669*FLEN/8, x4, x1, x2)

inst_16030:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xf6 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7b003fff; valaddr_reg:x3; val_offset:48090*0 + 3*670*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48090*0 + 3*670*FLEN/8, x4, x1, x2)

inst_16031:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xf6 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7b007fff; valaddr_reg:x3; val_offset:48093*0 + 3*671*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48093*0 + 3*671*FLEN/8, x4, x1, x2)

inst_16032:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xf6 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7b00ffff; valaddr_reg:x3; val_offset:48096*0 + 3*672*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48096*0 + 3*672*FLEN/8, x4, x1, x2)

inst_16033:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xf6 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7b01ffff; valaddr_reg:x3; val_offset:48099*0 + 3*673*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48099*0 + 3*673*FLEN/8, x4, x1, x2)

inst_16034:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xf6 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7b03ffff; valaddr_reg:x3; val_offset:48102*0 + 3*674*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48102*0 + 3*674*FLEN/8, x4, x1, x2)

inst_16035:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xf6 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7b07ffff; valaddr_reg:x3; val_offset:48105*0 + 3*675*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48105*0 + 3*675*FLEN/8, x4, x1, x2)

inst_16036:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xf6 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7b0fffff; valaddr_reg:x3; val_offset:48108*0 + 3*676*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48108*0 + 3*676*FLEN/8, x4, x1, x2)

inst_16037:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xf6 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7b1fffff; valaddr_reg:x3; val_offset:48111*0 + 3*677*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48111*0 + 3*677*FLEN/8, x4, x1, x2)

inst_16038:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xf6 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7b3fffff; valaddr_reg:x3; val_offset:48114*0 + 3*678*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48114*0 + 3*678*FLEN/8, x4, x1, x2)

inst_16039:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xf6 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7b400000; valaddr_reg:x3; val_offset:48117*0 + 3*679*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48117*0 + 3*679*FLEN/8, x4, x1, x2)

inst_16040:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xf6 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7b600000; valaddr_reg:x3; val_offset:48120*0 + 3*680*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48120*0 + 3*680*FLEN/8, x4, x1, x2)

inst_16041:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xf6 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7b700000; valaddr_reg:x3; val_offset:48123*0 + 3*681*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48123*0 + 3*681*FLEN/8, x4, x1, x2)

inst_16042:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xf6 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7b780000; valaddr_reg:x3; val_offset:48126*0 + 3*682*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48126*0 + 3*682*FLEN/8, x4, x1, x2)

inst_16043:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xf6 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7b7c0000; valaddr_reg:x3; val_offset:48129*0 + 3*683*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48129*0 + 3*683*FLEN/8, x4, x1, x2)

inst_16044:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xf6 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7b7e0000; valaddr_reg:x3; val_offset:48132*0 + 3*684*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48132*0 + 3*684*FLEN/8, x4, x1, x2)

inst_16045:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xf6 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7b7f0000; valaddr_reg:x3; val_offset:48135*0 + 3*685*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48135*0 + 3*685*FLEN/8, x4, x1, x2)

inst_16046:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xf6 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7b7f8000; valaddr_reg:x3; val_offset:48138*0 + 3*686*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48138*0 + 3*686*FLEN/8, x4, x1, x2)

inst_16047:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xf6 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7b7fc000; valaddr_reg:x3; val_offset:48141*0 + 3*687*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48141*0 + 3*687*FLEN/8, x4, x1, x2)

inst_16048:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xf6 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7b7fe000; valaddr_reg:x3; val_offset:48144*0 + 3*688*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48144*0 + 3*688*FLEN/8, x4, x1, x2)

inst_16049:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xf6 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7b7ff000; valaddr_reg:x3; val_offset:48147*0 + 3*689*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48147*0 + 3*689*FLEN/8, x4, x1, x2)

inst_16050:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xf6 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7b7ff800; valaddr_reg:x3; val_offset:48150*0 + 3*690*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48150*0 + 3*690*FLEN/8, x4, x1, x2)

inst_16051:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xf6 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7b7ffc00; valaddr_reg:x3; val_offset:48153*0 + 3*691*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48153*0 + 3*691*FLEN/8, x4, x1, x2)

inst_16052:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xf6 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7b7ffe00; valaddr_reg:x3; val_offset:48156*0 + 3*692*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48156*0 + 3*692*FLEN/8, x4, x1, x2)

inst_16053:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xf6 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7b7fff00; valaddr_reg:x3; val_offset:48159*0 + 3*693*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48159*0 + 3*693*FLEN/8, x4, x1, x2)

inst_16054:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xf6 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7b7fff80; valaddr_reg:x3; val_offset:48162*0 + 3*694*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48162*0 + 3*694*FLEN/8, x4, x1, x2)

inst_16055:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xf6 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7b7fffc0; valaddr_reg:x3; val_offset:48165*0 + 3*695*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48165*0 + 3*695*FLEN/8, x4, x1, x2)

inst_16056:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xf6 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7b7fffe0; valaddr_reg:x3; val_offset:48168*0 + 3*696*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48168*0 + 3*696*FLEN/8, x4, x1, x2)

inst_16057:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xf6 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7b7ffff0; valaddr_reg:x3; val_offset:48171*0 + 3*697*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48171*0 + 3*697*FLEN/8, x4, x1, x2)

inst_16058:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xf6 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7b7ffff8; valaddr_reg:x3; val_offset:48174*0 + 3*698*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48174*0 + 3*698*FLEN/8, x4, x1, x2)

inst_16059:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xf6 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7b7ffffc; valaddr_reg:x3; val_offset:48177*0 + 3*699*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48177*0 + 3*699*FLEN/8, x4, x1, x2)

inst_16060:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xf6 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7b7ffffe; valaddr_reg:x3; val_offset:48180*0 + 3*700*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48180*0 + 3*700*FLEN/8, x4, x1, x2)

inst_16061:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xf6 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7b7fffff; valaddr_reg:x3; val_offset:48183*0 + 3*701*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48183*0 + 3*701*FLEN/8, x4, x1, x2)

inst_16062:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7f000001; valaddr_reg:x3; val_offset:48186*0 + 3*702*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48186*0 + 3*702*FLEN/8, x4, x1, x2)

inst_16063:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7f000003; valaddr_reg:x3; val_offset:48189*0 + 3*703*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48189*0 + 3*703*FLEN/8, x4, x1, x2)

inst_16064:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7f000007; valaddr_reg:x3; val_offset:48192*0 + 3*704*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48192*0 + 3*704*FLEN/8, x4, x1, x2)

inst_16065:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7f199999; valaddr_reg:x3; val_offset:48195*0 + 3*705*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48195*0 + 3*705*FLEN/8, x4, x1, x2)

inst_16066:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7f249249; valaddr_reg:x3; val_offset:48198*0 + 3*706*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48198*0 + 3*706*FLEN/8, x4, x1, x2)

inst_16067:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7f333333; valaddr_reg:x3; val_offset:48201*0 + 3*707*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48201*0 + 3*707*FLEN/8, x4, x1, x2)

inst_16068:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7f36db6d; valaddr_reg:x3; val_offset:48204*0 + 3*708*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48204*0 + 3*708*FLEN/8, x4, x1, x2)

inst_16069:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7f3bbbbb; valaddr_reg:x3; val_offset:48207*0 + 3*709*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48207*0 + 3*709*FLEN/8, x4, x1, x2)

inst_16070:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7f444444; valaddr_reg:x3; val_offset:48210*0 + 3*710*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48210*0 + 3*710*FLEN/8, x4, x1, x2)

inst_16071:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7f4ccccc; valaddr_reg:x3; val_offset:48213*0 + 3*711*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48213*0 + 3*711*FLEN/8, x4, x1, x2)

inst_16072:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7f5b6db6; valaddr_reg:x3; val_offset:48216*0 + 3*712*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48216*0 + 3*712*FLEN/8, x4, x1, x2)

inst_16073:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7f666666; valaddr_reg:x3; val_offset:48219*0 + 3*713*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48219*0 + 3*713*FLEN/8, x4, x1, x2)

inst_16074:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7f6db6db; valaddr_reg:x3; val_offset:48222*0 + 3*714*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48222*0 + 3*714*FLEN/8, x4, x1, x2)

inst_16075:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7f7ffff8; valaddr_reg:x3; val_offset:48225*0 + 3*715*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48225*0 + 3*715*FLEN/8, x4, x1, x2)

inst_16076:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7f7ffffc; valaddr_reg:x3; val_offset:48228*0 + 3*716*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48228*0 + 3*716*FLEN/8, x4, x1, x2)

inst_16077:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x20081f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4cc266 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea0081f; op2val:0x404cc266;
op3val:0x7f7ffffe; valaddr_reg:x3; val_offset:48231*0 + 3*717*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48231*0 + 3*717*FLEN/8, x4, x1, x2)

inst_16078:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2022af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4ca070 and fs3 == 0 and fe3 == 0xbe and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea022af; op2val:0x404ca070;
op3val:0x5f000000; valaddr_reg:x3; val_offset:48234*0 + 3*718*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48234*0 + 3*718*FLEN/8, x4, x1, x2)

inst_16079:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2022af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4ca070 and fs3 == 0 and fe3 == 0xbe and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea022af; op2val:0x404ca070;
op3val:0x5f000001; valaddr_reg:x3; val_offset:48237*0 + 3*719*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48237*0 + 3*719*FLEN/8, x4, x1, x2)

inst_16080:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2022af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4ca070 and fs3 == 0 and fe3 == 0xbe and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea022af; op2val:0x404ca070;
op3val:0x5f000003; valaddr_reg:x3; val_offset:48240*0 + 3*720*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48240*0 + 3*720*FLEN/8, x4, x1, x2)

inst_16081:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2022af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4ca070 and fs3 == 0 and fe3 == 0xbe and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea022af; op2val:0x404ca070;
op3val:0x5f000007; valaddr_reg:x3; val_offset:48243*0 + 3*721*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48243*0 + 3*721*FLEN/8, x4, x1, x2)

inst_16082:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2022af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4ca070 and fs3 == 0 and fe3 == 0xbe and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea022af; op2val:0x404ca070;
op3val:0x5f00000f; valaddr_reg:x3; val_offset:48246*0 + 3*722*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48246*0 + 3*722*FLEN/8, x4, x1, x2)

inst_16083:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2022af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4ca070 and fs3 == 0 and fe3 == 0xbe and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea022af; op2val:0x404ca070;
op3val:0x5f00001f; valaddr_reg:x3; val_offset:48249*0 + 3*723*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48249*0 + 3*723*FLEN/8, x4, x1, x2)

inst_16084:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2022af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4ca070 and fs3 == 0 and fe3 == 0xbe and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea022af; op2val:0x404ca070;
op3val:0x5f00003f; valaddr_reg:x3; val_offset:48252*0 + 3*724*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48252*0 + 3*724*FLEN/8, x4, x1, x2)

inst_16085:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2022af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4ca070 and fs3 == 0 and fe3 == 0xbe and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea022af; op2val:0x404ca070;
op3val:0x5f00007f; valaddr_reg:x3; val_offset:48255*0 + 3*725*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48255*0 + 3*725*FLEN/8, x4, x1, x2)

inst_16086:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2022af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4ca070 and fs3 == 0 and fe3 == 0xbe and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea022af; op2val:0x404ca070;
op3val:0x5f0000ff; valaddr_reg:x3; val_offset:48258*0 + 3*726*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48258*0 + 3*726*FLEN/8, x4, x1, x2)

inst_16087:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2022af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4ca070 and fs3 == 0 and fe3 == 0xbe and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea022af; op2val:0x404ca070;
op3val:0x5f0001ff; valaddr_reg:x3; val_offset:48261*0 + 3*727*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48261*0 + 3*727*FLEN/8, x4, x1, x2)

inst_16088:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2022af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4ca070 and fs3 == 0 and fe3 == 0xbe and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea022af; op2val:0x404ca070;
op3val:0x5f0003ff; valaddr_reg:x3; val_offset:48264*0 + 3*728*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48264*0 + 3*728*FLEN/8, x4, x1, x2)

inst_16089:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2022af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4ca070 and fs3 == 0 and fe3 == 0xbe and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea022af; op2val:0x404ca070;
op3val:0x5f0007ff; valaddr_reg:x3; val_offset:48267*0 + 3*729*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48267*0 + 3*729*FLEN/8, x4, x1, x2)

inst_16090:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2022af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4ca070 and fs3 == 0 and fe3 == 0xbe and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea022af; op2val:0x404ca070;
op3val:0x5f000fff; valaddr_reg:x3; val_offset:48270*0 + 3*730*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48270*0 + 3*730*FLEN/8, x4, x1, x2)

inst_16091:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2022af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4ca070 and fs3 == 0 and fe3 == 0xbe and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea022af; op2val:0x404ca070;
op3val:0x5f001fff; valaddr_reg:x3; val_offset:48273*0 + 3*731*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48273*0 + 3*731*FLEN/8, x4, x1, x2)

inst_16092:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2022af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4ca070 and fs3 == 0 and fe3 == 0xbe and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea022af; op2val:0x404ca070;
op3val:0x5f003fff; valaddr_reg:x3; val_offset:48276*0 + 3*732*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48276*0 + 3*732*FLEN/8, x4, x1, x2)

inst_16093:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2022af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4ca070 and fs3 == 0 and fe3 == 0xbe and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea022af; op2val:0x404ca070;
op3val:0x5f007fff; valaddr_reg:x3; val_offset:48279*0 + 3*733*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48279*0 + 3*733*FLEN/8, x4, x1, x2)

inst_16094:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2022af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4ca070 and fs3 == 0 and fe3 == 0xbe and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea022af; op2val:0x404ca070;
op3val:0x5f00ffff; valaddr_reg:x3; val_offset:48282*0 + 3*734*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48282*0 + 3*734*FLEN/8, x4, x1, x2)

inst_16095:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2022af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4ca070 and fs3 == 0 and fe3 == 0xbe and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea022af; op2val:0x404ca070;
op3val:0x5f01ffff; valaddr_reg:x3; val_offset:48285*0 + 3*735*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48285*0 + 3*735*FLEN/8, x4, x1, x2)

inst_16096:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2022af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4ca070 and fs3 == 0 and fe3 == 0xbe and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea022af; op2val:0x404ca070;
op3val:0x5f03ffff; valaddr_reg:x3; val_offset:48288*0 + 3*736*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48288*0 + 3*736*FLEN/8, x4, x1, x2)

inst_16097:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2022af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4ca070 and fs3 == 0 and fe3 == 0xbe and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea022af; op2val:0x404ca070;
op3val:0x5f07ffff; valaddr_reg:x3; val_offset:48291*0 + 3*737*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48291*0 + 3*737*FLEN/8, x4, x1, x2)

inst_16098:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2022af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4ca070 and fs3 == 0 and fe3 == 0xbe and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea022af; op2val:0x404ca070;
op3val:0x5f0fffff; valaddr_reg:x3; val_offset:48294*0 + 3*738*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48294*0 + 3*738*FLEN/8, x4, x1, x2)

inst_16099:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2022af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4ca070 and fs3 == 0 and fe3 == 0xbe and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea022af; op2val:0x404ca070;
op3val:0x5f1fffff; valaddr_reg:x3; val_offset:48297*0 + 3*739*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48297*0 + 3*739*FLEN/8, x4, x1, x2)

inst_16100:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2022af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4ca070 and fs3 == 0 and fe3 == 0xbe and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea022af; op2val:0x404ca070;
op3val:0x5f3fffff; valaddr_reg:x3; val_offset:48300*0 + 3*740*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48300*0 + 3*740*FLEN/8, x4, x1, x2)

inst_16101:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2022af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4ca070 and fs3 == 0 and fe3 == 0xbe and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea022af; op2val:0x404ca070;
op3val:0x5f400000; valaddr_reg:x3; val_offset:48303*0 + 3*741*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48303*0 + 3*741*FLEN/8, x4, x1, x2)

inst_16102:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2022af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4ca070 and fs3 == 0 and fe3 == 0xbe and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea022af; op2val:0x404ca070;
op3val:0x5f600000; valaddr_reg:x3; val_offset:48306*0 + 3*742*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48306*0 + 3*742*FLEN/8, x4, x1, x2)

inst_16103:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2022af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4ca070 and fs3 == 0 and fe3 == 0xbe and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea022af; op2val:0x404ca070;
op3val:0x5f700000; valaddr_reg:x3; val_offset:48309*0 + 3*743*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48309*0 + 3*743*FLEN/8, x4, x1, x2)

inst_16104:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2022af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4ca070 and fs3 == 0 and fe3 == 0xbe and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea022af; op2val:0x404ca070;
op3val:0x5f780000; valaddr_reg:x3; val_offset:48312*0 + 3*744*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48312*0 + 3*744*FLEN/8, x4, x1, x2)

inst_16105:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2022af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4ca070 and fs3 == 0 and fe3 == 0xbe and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea022af; op2val:0x404ca070;
op3val:0x5f7c0000; valaddr_reg:x3; val_offset:48315*0 + 3*745*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48315*0 + 3*745*FLEN/8, x4, x1, x2)

inst_16106:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2022af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4ca070 and fs3 == 0 and fe3 == 0xbe and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea022af; op2val:0x404ca070;
op3val:0x5f7e0000; valaddr_reg:x3; val_offset:48318*0 + 3*746*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48318*0 + 3*746*FLEN/8, x4, x1, x2)

inst_16107:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2022af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4ca070 and fs3 == 0 and fe3 == 0xbe and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea022af; op2val:0x404ca070;
op3val:0x5f7f0000; valaddr_reg:x3; val_offset:48321*0 + 3*747*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48321*0 + 3*747*FLEN/8, x4, x1, x2)

inst_16108:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2022af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4ca070 and fs3 == 0 and fe3 == 0xbe and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea022af; op2val:0x404ca070;
op3val:0x5f7f8000; valaddr_reg:x3; val_offset:48324*0 + 3*748*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48324*0 + 3*748*FLEN/8, x4, x1, x2)

inst_16109:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2022af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4ca070 and fs3 == 0 and fe3 == 0xbe and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea022af; op2val:0x404ca070;
op3val:0x5f7fc000; valaddr_reg:x3; val_offset:48327*0 + 3*749*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48327*0 + 3*749*FLEN/8, x4, x1, x2)

inst_16110:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2022af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4ca070 and fs3 == 0 and fe3 == 0xbe and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea022af; op2val:0x404ca070;
op3val:0x5f7fe000; valaddr_reg:x3; val_offset:48330*0 + 3*750*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48330*0 + 3*750*FLEN/8, x4, x1, x2)

inst_16111:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2022af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4ca070 and fs3 == 0 and fe3 == 0xbe and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea022af; op2val:0x404ca070;
op3val:0x5f7ff000; valaddr_reg:x3; val_offset:48333*0 + 3*751*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48333*0 + 3*751*FLEN/8, x4, x1, x2)

inst_16112:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2022af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4ca070 and fs3 == 0 and fe3 == 0xbe and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea022af; op2val:0x404ca070;
op3val:0x5f7ff800; valaddr_reg:x3; val_offset:48336*0 + 3*752*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48336*0 + 3*752*FLEN/8, x4, x1, x2)

inst_16113:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2022af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4ca070 and fs3 == 0 and fe3 == 0xbe and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea022af; op2val:0x404ca070;
op3val:0x5f7ffc00; valaddr_reg:x3; val_offset:48339*0 + 3*753*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48339*0 + 3*753*FLEN/8, x4, x1, x2)

inst_16114:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2022af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4ca070 and fs3 == 0 and fe3 == 0xbe and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea022af; op2val:0x404ca070;
op3val:0x5f7ffe00; valaddr_reg:x3; val_offset:48342*0 + 3*754*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48342*0 + 3*754*FLEN/8, x4, x1, x2)

inst_16115:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2022af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4ca070 and fs3 == 0 and fe3 == 0xbe and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea022af; op2val:0x404ca070;
op3val:0x5f7fff00; valaddr_reg:x3; val_offset:48345*0 + 3*755*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48345*0 + 3*755*FLEN/8, x4, x1, x2)

inst_16116:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2022af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4ca070 and fs3 == 0 and fe3 == 0xbe and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea022af; op2val:0x404ca070;
op3val:0x5f7fff80; valaddr_reg:x3; val_offset:48348*0 + 3*756*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48348*0 + 3*756*FLEN/8, x4, x1, x2)

inst_16117:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2022af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4ca070 and fs3 == 0 and fe3 == 0xbe and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea022af; op2val:0x404ca070;
op3val:0x5f7fffc0; valaddr_reg:x3; val_offset:48351*0 + 3*757*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48351*0 + 3*757*FLEN/8, x4, x1, x2)

inst_16118:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2022af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4ca070 and fs3 == 0 and fe3 == 0xbe and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea022af; op2val:0x404ca070;
op3val:0x5f7fffe0; valaddr_reg:x3; val_offset:48354*0 + 3*758*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48354*0 + 3*758*FLEN/8, x4, x1, x2)

inst_16119:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2022af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4ca070 and fs3 == 0 and fe3 == 0xbe and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea022af; op2val:0x404ca070;
op3val:0x5f7ffff0; valaddr_reg:x3; val_offset:48357*0 + 3*759*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48357*0 + 3*759*FLEN/8, x4, x1, x2)

inst_16120:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2022af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4ca070 and fs3 == 0 and fe3 == 0xbe and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea022af; op2val:0x404ca070;
op3val:0x5f7ffff8; valaddr_reg:x3; val_offset:48360*0 + 3*760*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48360*0 + 3*760*FLEN/8, x4, x1, x2)

inst_16121:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2022af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4ca070 and fs3 == 0 and fe3 == 0xbe and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea022af; op2val:0x404ca070;
op3val:0x5f7ffffc; valaddr_reg:x3; val_offset:48363*0 + 3*761*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48363*0 + 3*761*FLEN/8, x4, x1, x2)

inst_16122:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2022af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4ca070 and fs3 == 0 and fe3 == 0xbe and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea022af; op2val:0x404ca070;
op3val:0x5f7ffffe; valaddr_reg:x3; val_offset:48366*0 + 3*762*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48366*0 + 3*762*FLEN/8, x4, x1, x2)

inst_16123:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2022af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4ca070 and fs3 == 0 and fe3 == 0xbe and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea022af; op2val:0x404ca070;
op3val:0x5f7fffff; valaddr_reg:x3; val_offset:48369*0 + 3*763*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48369*0 + 3*763*FLEN/8, x4, x1, x2)

inst_16124:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2022af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4ca070 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea022af; op2val:0x404ca070;
op3val:0x7f000001; valaddr_reg:x3; val_offset:48372*0 + 3*764*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48372*0 + 3*764*FLEN/8, x4, x1, x2)

inst_16125:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2022af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4ca070 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea022af; op2val:0x404ca070;
op3val:0x7f000003; valaddr_reg:x3; val_offset:48375*0 + 3*765*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48375*0 + 3*765*FLEN/8, x4, x1, x2)

inst_16126:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2022af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4ca070 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea022af; op2val:0x404ca070;
op3val:0x7f000007; valaddr_reg:x3; val_offset:48378*0 + 3*766*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48378*0 + 3*766*FLEN/8, x4, x1, x2)

inst_16127:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x2022af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x4ca070 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ea022af; op2val:0x404ca070;
op3val:0x7f199999; valaddr_reg:x3; val_offset:48381*0 + 3*767*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 48381*0 + 3*767*FLEN/8, x4, x1, x2)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0x7e9799a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8003ff,32,FLEN)
NAN_BOXED(0x7e9799a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8007ff,32,FLEN)
NAN_BOXED(0x7e9799a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800fff,32,FLEN)
NAN_BOXED(0x7e9799a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x801fff,32,FLEN)
NAN_BOXED(0x7e9799a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x803fff,32,FLEN)
NAN_BOXED(0x7e9799a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x807fff,32,FLEN)
NAN_BOXED(0x7e9799a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x80ffff,32,FLEN)
NAN_BOXED(0x7e9799a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x81ffff,32,FLEN)
NAN_BOXED(0x7e9799a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x83ffff,32,FLEN)
NAN_BOXED(0x7e9799a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87ffff,32,FLEN)
NAN_BOXED(0x7e9799a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8fffff,32,FLEN)
NAN_BOXED(0x7e9799a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x9fffff,32,FLEN)
NAN_BOXED(0x7e9799a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbfffff,32,FLEN)
NAN_BOXED(0x7e9799a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xc00000,32,FLEN)
NAN_BOXED(0x7e9799a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe00000,32,FLEN)
NAN_BOXED(0x7e9799a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf00000,32,FLEN)
NAN_BOXED(0x7e9799a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf80000,32,FLEN)
NAN_BOXED(0x7e9799a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfc0000,32,FLEN)
NAN_BOXED(0x7e9799a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfe0000,32,FLEN)
NAN_BOXED(0x7e9799a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xff0000,32,FLEN)
NAN_BOXED(0x7e9799a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xff8000,32,FLEN)
NAN_BOXED(0x7e9799a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xffc000,32,FLEN)
NAN_BOXED(0x7e9799a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xffe000,32,FLEN)
NAN_BOXED(0x7e9799a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfff000,32,FLEN)
NAN_BOXED(0x7e9799a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfff800,32,FLEN)
NAN_BOXED(0x7e9799a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffc00,32,FLEN)
NAN_BOXED(0x7e9799a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffe00,32,FLEN)
NAN_BOXED(0x7e9799a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xffff00,32,FLEN)
NAN_BOXED(0x7e9799a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xffff80,32,FLEN)
NAN_BOXED(0x7e9799a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xffffc0,32,FLEN)
NAN_BOXED(0x7e9799a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xffffe0,32,FLEN)
NAN_BOXED(0x7e9799a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffff0,32,FLEN)
NAN_BOXED(0x7e9799a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffff8,32,FLEN)
NAN_BOXED(0x7e9799a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffffc,32,FLEN)
NAN_BOXED(0x7e9799a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffffe,32,FLEN)
NAN_BOXED(0x7e9799a1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xffffff,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xf5800000,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xf5800001,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xf5800003,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xf5800007,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xf580000f,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xf580001f,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xf580003f,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xf580007f,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xf58000ff,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xf58001ff,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xf58003ff,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xf58007ff,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xf5800fff,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xf5801fff,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xf5803fff,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xf5807fff,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xf580ffff,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xf581ffff,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xf583ffff,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xf587ffff,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xf58fffff,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xf59fffff,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xf5bfffff,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xf5c00000,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xf5e00000,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xf5f00000,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xf5f80000,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xf5fc0000,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xf5fe0000,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xf5ff0000,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xf5ff8000,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xf5ffc000,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xf5ffe000,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xf5fff000,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xf5fff800,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xf5fffc00,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xf5fffe00,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xf5ffff00,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xf5ffff80,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xf5ffffc0,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xf5ffffe0,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xf5fffff0,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xf5fffff8,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xf5fffffc,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xf5fffffe,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xf5ffffff,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xff000001,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xff000003,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xff000007,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xff199999,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xff249249,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xff333333,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xff36db6d,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xff3bbbbb,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xff444444,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xff4ccccc,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xff5b6db6,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xff666666,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xff6db6db,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xff7ffff8,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xff7ffffc,32,FLEN)
NAN_BOXED(0x7e98277b,32,FLEN)
NAN_BOXED(0xc0575c44,32,FLEN)
NAN_BOXED(0xff7ffffe,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xe4800000,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xe4800001,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xe4800003,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xe4800007,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xe480000f,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xe480001f,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xe480003f,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xe480007f,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xe48000ff,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xe48001ff,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xe48003ff,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xe48007ff,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xe4800fff,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xe4801fff,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xe4803fff,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xe4807fff,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xe480ffff,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xe481ffff,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xe483ffff,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xe487ffff,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xe48fffff,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xe49fffff,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xe4bfffff,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xe4c00000,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xe4e00000,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xe4f00000,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xe4f80000,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xe4fc0000,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xe4fe0000,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xe4ff0000,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xe4ff8000,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xe4ffc000,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xe4ffe000,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xe4fff000,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xe4fff800,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xe4fffc00,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xe4fffe00,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xe4ffff00,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xe4ffff80,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xe4ffffc0,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xe4ffffe0,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xe4fffff0,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xe4fffff8,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xe4fffffc,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xe4fffffe,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xe4ffffff,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xff000001,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xff000003,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xff000007,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xff199999,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xff249249,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xff333333,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xff36db6d,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xff3bbbbb,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xff444444,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xff4ccccc,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xff5b6db6,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xff666666,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xff6db6db,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xff7ffff8,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xff7ffffc,32,FLEN)
NAN_BOXED(0x7e99215d,32,FLEN)
NAN_BOXED(0xc055fcd6,32,FLEN)
NAN_BOXED(0xff7ffffe,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000001,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000003,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000007,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80199999,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80249249,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80333333,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8036db6d,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x803bbbbb,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80444444,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x804ccccc,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x805b6db6,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80666666,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x806db6db,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffff8,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffc,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffe,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0xfc000000,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0xfc000001,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0xfc000003,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0xfc000007,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0xfc00000f,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0xfc00001f,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0xfc00003f,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0xfc00007f,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0xfc0000ff,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0xfc0001ff,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0xfc0003ff,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0xfc0007ff,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0xfc000fff,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0xfc001fff,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0xfc003fff,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0xfc007fff,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0xfc00ffff,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0xfc01ffff,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0xfc03ffff,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0xfc07ffff,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0xfc0fffff,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0xfc1fffff,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0xfc3fffff,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0xfc400000,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0xfc600000,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0xfc700000,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0xfc780000,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0xfc7c0000,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0xfc7e0000,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0xfc7f0000,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0xfc7f8000,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0xfc7fc000,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0xfc7fe000,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0xfc7ff000,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0xfc7ff800,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0xfc7ffc00,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0xfc7ffe00,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0xfc7fff00,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0xfc7fff80,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0xfc7fffc0,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0xfc7fffe0,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0xfc7ffff0,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0xfc7ffff8,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0xfc7ffffc,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0xfc7ffffe,32,FLEN)
NAN_BOXED(0x7e9925f2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0xfc7fffff,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x199999,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x249249,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x333333,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x36db6d,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3bbbbb,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x444444,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4ccccc,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5b6db6,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x666666,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6db6db,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffff8,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffc,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffe,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5000000,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5000001,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5000003,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5000007,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x500000f,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x500001f,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x500003f,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x500007f,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x50000ff,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x50001ff,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x50003ff,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x50007ff,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5000fff,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5001fff,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5003fff,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5007fff,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x500ffff,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x501ffff,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x503ffff,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x507ffff,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x50fffff,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x51fffff,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x53fffff,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5400000,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5600000,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5700000,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5780000,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x57c0000,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x57e0000,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x57f0000,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x57f8000,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x57fc000,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x57fe000,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x57ff000,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x57ff800,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x57ffc00,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x57ffe00,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x57fff00,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x57fff80,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x57fffc0,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x57fffe0,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x57ffff0,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x57ffff8,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x57ffffc,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x57ffffe,32,FLEN)
NAN_BOXED(0x7e9ad123,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x57fffff,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xb0000000,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xb0000001,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xb0000003,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xb0000007,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xb000000f,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xb000001f,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xb000003f,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xb000007f,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xb00000ff,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xb00001ff,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xb00003ff,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xb00007ff,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xb0000fff,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xb0001fff,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xb0003fff,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xb0007fff,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xb000ffff,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xb001ffff,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xb003ffff,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xb007ffff,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xb00fffff,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xb01fffff,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xb03fffff,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xb0400000,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xb0600000,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xb0700000,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xb0780000,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xb07c0000,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xb07e0000,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xb07f0000,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xb07f8000,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xb07fc000,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xb07fe000,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xb07ff000,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xb07ff800,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xb07ffc00,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xb07ffe00,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xb07fff00,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xb07fff80,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xb07fffc0,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xb07fffe0,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xb07ffff0,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xb07ffff8,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xb07ffffc,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xb07ffffe,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xb07fffff,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xff000001,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xff000003,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xff000007,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xff199999,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xff249249,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xff333333,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xff36db6d,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xff3bbbbb,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xff444444,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xff4ccccc,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xff5b6db6,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xff666666,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xff6db6db,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xff7ffff8,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xff7ffffc,32,FLEN)
NAN_BOXED(0x7e9ce997,32,FLEN)
NAN_BOXED(0xc050d46d,32,FLEN)
NAN_BOXED(0xff7ffffe,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800001,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800003,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800007,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x999999,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa49249,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb33333,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb6db6d,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbbbbbb,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xc44444,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xcccccc,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xdb6db6,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe66666,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xedb6db,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffff8,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffffc,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffffe,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4000000,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4000001,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4000003,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4000007,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x400000f,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x400001f,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x400003f,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x400007f,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x40000ff,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x40001ff,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x40003ff,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x40007ff,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4000fff,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4001fff,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4003fff,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4007fff,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x400ffff,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x401ffff,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x403ffff,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x407ffff,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x40fffff,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x41fffff,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x43fffff,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4400000,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4600000,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4700000,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4780000,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x47c0000,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x47e0000,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x47f0000,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x47f8000,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x47fc000,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x47fe000,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x47ff000,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x47ff800,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x47ffc00,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x47ffe00,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x47fff00,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x47fff80,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x47fffc0,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x47fffe0,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x47ffff0,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x47ffff8,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x47ffffc,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x47ffffe,32,FLEN)
NAN_BOXED(0x7e9de0b9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x47fffff,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x199999,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x249249,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x333333,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x36db6d,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3bbbbb,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x444444,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4ccccc,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5b6db6,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x666666,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6db6db,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffff8,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffc,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffe,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6000000,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6000001,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6000003,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6000007,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x600000f,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x600001f,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x600003f,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x600007f,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x60000ff,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x60001ff,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x60003ff,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x60007ff,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6000fff,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6001fff,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6003fff,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6007fff,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x600ffff,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x601ffff,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x603ffff,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x607ffff,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x60fffff,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x61fffff,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x63fffff,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6400000,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6600000,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6700000,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6780000,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x67c0000,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x67e0000,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x67f0000,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x67f8000,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x67fc000,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x67fe000,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x67ff000,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x67ff800,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x67ffc00,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x67ffe00,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x67fff00,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x67fff80,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x67fffc0,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x67fffe0,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x67ffff0,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x67ffff8,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x67ffffc,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x67ffffe,32,FLEN)
NAN_BOXED(0x7e9f40ca,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x67fffff,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xfd000000,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xfd000001,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xfd000003,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xfd000007,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xfd00000f,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xfd00001f,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xfd00003f,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xfd00007f,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xfd0000ff,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xfd0001ff,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xfd0003ff,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xfd0007ff,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xfd000fff,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xfd001fff,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xfd003fff,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xfd007fff,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xfd00ffff,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xfd01ffff,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xfd03ffff,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xfd07ffff,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xfd0fffff,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xfd1fffff,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xfd3fffff,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xfd400000,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xfd600000,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xfd700000,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xfd780000,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xfd7c0000,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xfd7e0000,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xfd7f0000,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xfd7f8000,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xfd7fc000,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xfd7fe000,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xfd7ff000,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xfd7ff800,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xfd7ffc00,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xfd7ffe00,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xfd7fff00,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xfd7fff80,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xfd7fffc0,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xfd7fffe0,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xfd7ffff0,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xfd7ffff8,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xfd7ffffc,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xfd7ffffe,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xfd7fffff,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xff000001,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xff000003,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xff000007,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xff199999,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xff249249,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xff333333,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xff36db6d,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xff3bbbbb,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xff444444,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xff4ccccc,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xff5b6db6,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xff666666,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xff6db6db,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xff7ffff8,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xff7ffffc,32,FLEN)
NAN_BOXED(0x7e9f4b7c,32,FLEN)
NAN_BOXED(0xc04db4e0,32,FLEN)
NAN_BOXED(0xff7ffffe,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xb2000000,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xb2000001,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xb2000003,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xb2000007,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xb200000f,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xb200001f,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xb200003f,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xb200007f,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xb20000ff,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xb20001ff,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xb20003ff,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xb20007ff,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xb2000fff,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xb2001fff,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xb2003fff,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xb2007fff,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xb200ffff,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xb201ffff,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xb203ffff,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xb207ffff,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xb20fffff,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xb21fffff,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xb23fffff,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xb2400000,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xb2600000,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xb2700000,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xb2780000,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xb27c0000,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xb27e0000,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xb27f0000,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xb27f8000,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xb27fc000,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xb27fe000,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xb27ff000,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xb27ff800,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xb27ffc00,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xb27ffe00,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xb27fff00,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xb27fff80,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xb27fffc0,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xb27fffe0,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xb27ffff0,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xb27ffff8,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xb27ffffc,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xb27ffffe,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xb27fffff,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xbf800001,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xbf800003,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xbf800007,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xbf999999,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xbfa49249,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xbfb33333,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xbfb6db6d,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xbfbbbbbb,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xbfc44444,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xbfcccccc,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xbfdb6db6,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xbfe66666,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xbfedb6db,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xbffffff8,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xbffffffc,32,FLEN)
NAN_BOXED(0x7e9f69aa,32,FLEN)
NAN_BOXED(0x8066c6f7,32,FLEN)
NAN_BOXED(0xbffffffe,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80800001,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80800003,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80800007,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80999999,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80a49249,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80b33333,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80b6db6d,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80bbbbbb,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80c44444,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80cccccc,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80db6db6,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80e66666,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80edb6db,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80fffff8,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80fffffc,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80fffffe,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8f800000,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8f800001,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8f800003,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8f800007,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8f80000f,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8f80001f,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8f80003f,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8f80007f,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8f8000ff,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8f8001ff,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8f8003ff,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8f8007ff,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8f800fff,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8f801fff,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8f803fff,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8f807fff,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8f80ffff,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8f81ffff,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8f83ffff,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8f87ffff,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8f8fffff,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8f9fffff,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8fbfffff,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8fc00000,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8fe00000,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8ff00000,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8ff80000,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8ffc0000,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8ffe0000,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8fff0000,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8fff8000,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8fffc000,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8fffe000,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8ffff000,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8ffff800,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8ffffc00,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8ffffe00,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8fffff00,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8fffff80,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8fffffc0,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8fffffe0,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8ffffff0,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8ffffff8,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8ffffffc,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8ffffffe,32,FLEN)
NAN_BOXED(0x7e9f9b30,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8fffffff,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7b000000,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7b000001,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7b000003,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7b000007,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7b00000f,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7b00001f,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7b00003f,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7b00007f,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7b0000ff,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7b0001ff,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7b0003ff,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7b0007ff,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7b000fff,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7b001fff,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7b003fff,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7b007fff,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7b00ffff,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7b01ffff,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7b03ffff,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7b07ffff,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7b0fffff,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7b1fffff,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7b3fffff,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7b400000,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7b600000,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7b700000,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7b780000,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7b7c0000,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7b7e0000,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7b7f0000,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7b7f8000,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7b7fc000,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7b7fe000,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7b7ff000,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7b7ff800,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7b7ffc00,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7b7ffe00,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7b7fff00,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7b7fff80,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7b7fffc0,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7b7fffe0,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7b7ffff0,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7b7ffff8,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7b7ffffc,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7b7ffffe,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7b7fffff,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7f000001,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7f000003,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7f000007,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7f199999,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7f249249,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7f333333,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7f36db6d,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7f3bbbbb,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7f444444,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7f4ccccc,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7f5b6db6,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7f666666,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7f6db6db,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7f7ffff8,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7f7ffffc,32,FLEN)
NAN_BOXED(0x7ea0081f,32,FLEN)
NAN_BOXED(0x404cc266,32,FLEN)
NAN_BOXED(0x7f7ffffe,32,FLEN)
NAN_BOXED(0x7ea022af,32,FLEN)
NAN_BOXED(0x404ca070,32,FLEN)
NAN_BOXED(0x5f000000,32,FLEN)
NAN_BOXED(0x7ea022af,32,FLEN)
NAN_BOXED(0x404ca070,32,FLEN)
NAN_BOXED(0x5f000001,32,FLEN)
NAN_BOXED(0x7ea022af,32,FLEN)
NAN_BOXED(0x404ca070,32,FLEN)
NAN_BOXED(0x5f000003,32,FLEN)
NAN_BOXED(0x7ea022af,32,FLEN)
NAN_BOXED(0x404ca070,32,FLEN)
NAN_BOXED(0x5f000007,32,FLEN)
NAN_BOXED(0x7ea022af,32,FLEN)
NAN_BOXED(0x404ca070,32,FLEN)
NAN_BOXED(0x5f00000f,32,FLEN)
NAN_BOXED(0x7ea022af,32,FLEN)
NAN_BOXED(0x404ca070,32,FLEN)
NAN_BOXED(0x5f00001f,32,FLEN)
NAN_BOXED(0x7ea022af,32,FLEN)
NAN_BOXED(0x404ca070,32,FLEN)
NAN_BOXED(0x5f00003f,32,FLEN)
NAN_BOXED(0x7ea022af,32,FLEN)
NAN_BOXED(0x404ca070,32,FLEN)
NAN_BOXED(0x5f00007f,32,FLEN)
NAN_BOXED(0x7ea022af,32,FLEN)
NAN_BOXED(0x404ca070,32,FLEN)
NAN_BOXED(0x5f0000ff,32,FLEN)
NAN_BOXED(0x7ea022af,32,FLEN)
NAN_BOXED(0x404ca070,32,FLEN)
NAN_BOXED(0x5f0001ff,32,FLEN)
NAN_BOXED(0x7ea022af,32,FLEN)
NAN_BOXED(0x404ca070,32,FLEN)
NAN_BOXED(0x5f0003ff,32,FLEN)
NAN_BOXED(0x7ea022af,32,FLEN)
NAN_BOXED(0x404ca070,32,FLEN)
NAN_BOXED(0x5f0007ff,32,FLEN)
NAN_BOXED(0x7ea022af,32,FLEN)
NAN_BOXED(0x404ca070,32,FLEN)
NAN_BOXED(0x5f000fff,32,FLEN)
NAN_BOXED(0x7ea022af,32,FLEN)
NAN_BOXED(0x404ca070,32,FLEN)
NAN_BOXED(0x5f001fff,32,FLEN)
NAN_BOXED(0x7ea022af,32,FLEN)
NAN_BOXED(0x404ca070,32,FLEN)
NAN_BOXED(0x5f003fff,32,FLEN)
NAN_BOXED(0x7ea022af,32,FLEN)
NAN_BOXED(0x404ca070,32,FLEN)
NAN_BOXED(0x5f007fff,32,FLEN)
NAN_BOXED(0x7ea022af,32,FLEN)
NAN_BOXED(0x404ca070,32,FLEN)
NAN_BOXED(0x5f00ffff,32,FLEN)
NAN_BOXED(0x7ea022af,32,FLEN)
NAN_BOXED(0x404ca070,32,FLEN)
NAN_BOXED(0x5f01ffff,32,FLEN)
NAN_BOXED(0x7ea022af,32,FLEN)
NAN_BOXED(0x404ca070,32,FLEN)
NAN_BOXED(0x5f03ffff,32,FLEN)
NAN_BOXED(0x7ea022af,32,FLEN)
NAN_BOXED(0x404ca070,32,FLEN)
NAN_BOXED(0x5f07ffff,32,FLEN)
NAN_BOXED(0x7ea022af,32,FLEN)
NAN_BOXED(0x404ca070,32,FLEN)
NAN_BOXED(0x5f0fffff,32,FLEN)
NAN_BOXED(0x7ea022af,32,FLEN)
NAN_BOXED(0x404ca070,32,FLEN)
NAN_BOXED(0x5f1fffff,32,FLEN)
NAN_BOXED(0x7ea022af,32,FLEN)
NAN_BOXED(0x404ca070,32,FLEN)
NAN_BOXED(0x5f3fffff,32,FLEN)
NAN_BOXED(0x7ea022af,32,FLEN)
NAN_BOXED(0x404ca070,32,FLEN)
NAN_BOXED(0x5f400000,32,FLEN)
NAN_BOXED(0x7ea022af,32,FLEN)
NAN_BOXED(0x404ca070,32,FLEN)
NAN_BOXED(0x5f600000,32,FLEN)
NAN_BOXED(0x7ea022af,32,FLEN)
NAN_BOXED(0x404ca070,32,FLEN)
NAN_BOXED(0x5f700000,32,FLEN)
NAN_BOXED(0x7ea022af,32,FLEN)
NAN_BOXED(0x404ca070,32,FLEN)
NAN_BOXED(0x5f780000,32,FLEN)
NAN_BOXED(0x7ea022af,32,FLEN)
NAN_BOXED(0x404ca070,32,FLEN)
NAN_BOXED(0x5f7c0000,32,FLEN)
NAN_BOXED(0x7ea022af,32,FLEN)
NAN_BOXED(0x404ca070,32,FLEN)
NAN_BOXED(0x5f7e0000,32,FLEN)
NAN_BOXED(0x7ea022af,32,FLEN)
NAN_BOXED(0x404ca070,32,FLEN)
NAN_BOXED(0x5f7f0000,32,FLEN)
NAN_BOXED(0x7ea022af,32,FLEN)
NAN_BOXED(0x404ca070,32,FLEN)
NAN_BOXED(0x5f7f8000,32,FLEN)
NAN_BOXED(0x7ea022af,32,FLEN)
NAN_BOXED(0x404ca070,32,FLEN)
NAN_BOXED(0x5f7fc000,32,FLEN)
NAN_BOXED(0x7ea022af,32,FLEN)
NAN_BOXED(0x404ca070,32,FLEN)
NAN_BOXED(0x5f7fe000,32,FLEN)
NAN_BOXED(0x7ea022af,32,FLEN)
NAN_BOXED(0x404ca070,32,FLEN)
NAN_BOXED(0x5f7ff000,32,FLEN)
NAN_BOXED(0x7ea022af,32,FLEN)
NAN_BOXED(0x404ca070,32,FLEN)
NAN_BOXED(0x5f7ff800,32,FLEN)
NAN_BOXED(0x7ea022af,32,FLEN)
NAN_BOXED(0x404ca070,32,FLEN)
NAN_BOXED(0x5f7ffc00,32,FLEN)
NAN_BOXED(0x7ea022af,32,FLEN)
NAN_BOXED(0x404ca070,32,FLEN)
NAN_BOXED(0x5f7ffe00,32,FLEN)
NAN_BOXED(0x7ea022af,32,FLEN)
NAN_BOXED(0x404ca070,32,FLEN)
NAN_BOXED(0x5f7fff00,32,FLEN)
NAN_BOXED(0x7ea022af,32,FLEN)
NAN_BOXED(0x404ca070,32,FLEN)
NAN_BOXED(0x5f7fff80,32,FLEN)
NAN_BOXED(0x7ea022af,32,FLEN)
NAN_BOXED(0x404ca070,32,FLEN)
NAN_BOXED(0x5f7fffc0,32,FLEN)
NAN_BOXED(0x7ea022af,32,FLEN)
NAN_BOXED(0x404ca070,32,FLEN)
NAN_BOXED(0x5f7fffe0,32,FLEN)
NAN_BOXED(0x7ea022af,32,FLEN)
NAN_BOXED(0x404ca070,32,FLEN)
NAN_BOXED(0x5f7ffff0,32,FLEN)
NAN_BOXED(0x7ea022af,32,FLEN)
NAN_BOXED(0x404ca070,32,FLEN)
NAN_BOXED(0x5f7ffff8,32,FLEN)
NAN_BOXED(0x7ea022af,32,FLEN)
NAN_BOXED(0x404ca070,32,FLEN)
NAN_BOXED(0x5f7ffffc,32,FLEN)
NAN_BOXED(0x7ea022af,32,FLEN)
NAN_BOXED(0x404ca070,32,FLEN)
NAN_BOXED(0x5f7ffffe,32,FLEN)
NAN_BOXED(0x7ea022af,32,FLEN)
NAN_BOXED(0x404ca070,32,FLEN)
NAN_BOXED(0x5f7fffff,32,FLEN)
NAN_BOXED(0x7ea022af,32,FLEN)
NAN_BOXED(0x404ca070,32,FLEN)
NAN_BOXED(0x7f000001,32,FLEN)
NAN_BOXED(0x7ea022af,32,FLEN)
NAN_BOXED(0x404ca070,32,FLEN)
NAN_BOXED(0x7f000003,32,FLEN)
NAN_BOXED(0x7ea022af,32,FLEN)
NAN_BOXED(0x404ca070,32,FLEN)
NAN_BOXED(0x7f000007,32,FLEN)
NAN_BOXED(0x7ea022af,32,FLEN)
NAN_BOXED(0x404ca070,32,FLEN)
NAN_BOXED(0x7f199999,32,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;


signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_2:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_3:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_4:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_5:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_6:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine

tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
    .fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;

#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif

sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
