
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.11.0
// timestamp : Mon Feb  5 07:40:16 2024 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fnmsub.s.cgf \
 \
//                  -- xlen 64  \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fnmsub.s instruction of the RISC-V RV64_Zfinx,RV64_Zdinx extension for the fnmsub_b4 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV64I_Zfinx,RV64I_Zdinx")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*);def TEST_CASE_1=True;",fnmsub_b4)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_0:
// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==x30, rs2==x31, rs3==x29, rd==x31,fs1 == 0 and fe1 == 0xfc and fm1 == 0x2e1c2f and fs2 == 1 and fe2 == 0x82 and fm2 == 0x0a7db2 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x38c2b9 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x31; op3:x29; dest:x31; op1val:0x7e2e1c2f; op2val:0xc10a7db2;
op3val:0x7f38c2b9; valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x31, x29, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)

inst_1:
// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==x29, rs2==x30, rs3==x31, rd==x29,fs1 == 0 and fe1 == 0xfc and fm1 == 0x2e1c2f and fs2 == 1 and fe2 == 0x82 and fm2 == 0x0a7db2 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x38c2b9 and fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x29; op2:x30; op3:x31; dest:x29; op1val:0x7e2e1c2f; op2val:0xc10a7db2;
op3val:0x7f38c2b9; valaddr_reg:x3; val_offset:3*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.s, x29, x29, x30, x31, dyn, 32, 0, x3, 3*FLEN/8, x4, x1, x2)

inst_2:
// rs1 == rs2 == rd != rs3, rs1==x28, rs2==x28, rs3==x30, rd==x28,fs1 == 0 and fe1 == 0xfc and fm1 == 0x2e1c2f and fs2 == 1 and fe2 == 0x82 and fm2 == 0x0a7db2 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x38c2b9 and fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x28; op2:x28; op3:x30; dest:x28; op1val:0x7e2e1c2f; op2val:0x7e2e1c2f;
op3val:0x7f38c2b9; valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.s, x28, x28, x28, x30, dyn, 64, 0, x3, 6*FLEN/8, x4, x1, x2)

inst_3:
// rd == rs2 == rs3 != rs1, rs1==x31, rs2==x27, rs3==x27, rd==x27,fs1 == 0 and fe1 == 0xfc and fm1 == 0x2e1c2f and fs2 == 1 and fe2 == 0x82 and fm2 == 0x0a7db2 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x38c2b9 and fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x31; op2:x27; op3:x27; dest:x27; op1val:0x7e2e1c2f; op2val:0xc10a7db2;
op3val:0xc10a7db2; valaddr_reg:x3; val_offset:9*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.s, x27, x31, x27, x27, dyn, 96, 0, x3, 9*FLEN/8, x4, x1, x2)

inst_4:
// rs1 == rs2 == rs3 != rd, rs1==x26, rs2==x26, rs3==x26, rd==x30,fs1 == 0 and fe1 == 0xfc and fm1 == 0x2e1c2f and fs2 == 1 and fe2 == 0x82 and fm2 == 0x0a7db2 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x38c2b9 and fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x26; op2:x26; op3:x26; dest:x30; op1val:0x7e2e1c2f; op2val:0x7e2e1c2f;
op3val:0x7e2e1c2f; valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.s, x30, x26, x26, x26, dyn, 128, 0, x3, 12*FLEN/8, x4, x1, x2)

inst_5:
// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==x25, rs2==x29, rs3==x25, rd==x26,fs1 == 0 and fe1 == 0xfb and fm1 == 0x420b54 and fs2 == 1 and fe2 == 0x82 and fm2 == 0x57eaea and fs3 == 0 and fe3 == 0xfe and fm3 == 0x075328 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x25; op2:x29; op3:x25; dest:x26; op1val:0x7dc20b54; op2val:0xc157eaea;
op3val:0x7dc20b54; valaddr_reg:x3; val_offset:15*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, x26, x25, x29, x25, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2)

inst_6:
// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==x27, rs2==x24, rs3==x24, rd==x25,fs1 == 0 and fe1 == 0xfb and fm1 == 0x420b54 and fs2 == 1 and fe2 == 0x82 and fm2 == 0x57eaea and fs3 == 0 and fe3 == 0xfe and fm3 == 0x075328 and fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x27; op2:x24; op3:x24; dest:x25; op1val:0x7dc20b54; op2val:0xc157eaea;
op3val:0xc157eaea; valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.s, x25, x27, x24, x24, dyn, 32, 0, x3, 18*FLEN/8, x4, x1, x2)

inst_7:
// rs1 == rd == rs3 != rs2, rs1==x23, rs2==x25, rs3==x23, rd==x23,fs1 == 0 and fe1 == 0xfb and fm1 == 0x420b54 and fs2 == 1 and fe2 == 0x82 and fm2 == 0x57eaea and fs3 == 0 and fe3 == 0xfe and fm3 == 0x075328 and fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x23; op2:x25; op3:x23; dest:x23; op1val:0x7dc20b54; op2val:0xc157eaea;
op3val:0x7dc20b54; valaddr_reg:x3; val_offset:21*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.s, x23, x23, x25, x23, dyn, 64, 0, x3, 21*FLEN/8, x4, x1, x2)

inst_8:
// rs1 == rs2 == rs3 == rd, rs1==x22, rs2==x22, rs3==x22, rd==x22,fs1 == 0 and fe1 == 0xfb and fm1 == 0x420b54 and fs2 == 1 and fe2 == 0x82 and fm2 == 0x57eaea and fs3 == 0 and fe3 == 0xfe and fm3 == 0x075328 and fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x22; op2:x22; op3:x22; dest:x22; op1val:0x7dc20b54; op2val:0x7dc20b54;
op3val:0x7dc20b54; valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.s, x22, x22, x22, x22, dyn, 96, 0, x3, 24*FLEN/8, x4, x1, x2)

inst_9:
// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==x24, rs2==x23, rs3==x21, rd==x21,fs1 == 0 and fe1 == 0xfb and fm1 == 0x420b54 and fs2 == 1 and fe2 == 0x82 and fm2 == 0x57eaea and fs3 == 0 and fe3 == 0xfe and fm3 == 0x075328 and fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x24; op2:x23; op3:x21; dest:x21; op1val:0x7dc20b54; op2val:0xc157eaea;
op3val:0x7f075328; valaddr_reg:x3; val_offset:27*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.s, x21, x24, x23, x21, dyn, 128, 0, x3, 27*FLEN/8, x4, x1, x2)

inst_10:
// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==x21, rs2==x20, rs3==x28, rd==x24,fs1 == 0 and fe1 == 0xfb and fm1 == 0x02d835 and fs2 == 1 and fe2 == 0x82 and fm2 == 0x6a4d3e and fs3 == 0 and fe3 == 0xfc and fm3 == 0x3e08e0 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x21; op2:x20; op3:x28; dest:x24; op1val:0x7d82d835; op2val:0xc16a4d3e;
op3val:0x7e3e08e0; valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, x24, x21, x20, x28, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)

inst_11:
// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==x19, rs2==x19, rs3==x18, rd==x20,fs1 == 0 and fe1 == 0xfb and fm1 == 0x02d835 and fs2 == 1 and fe2 == 0x82 and fm2 == 0x6a4d3e and fs3 == 0 and fe3 == 0xfc and fm3 == 0x3e08e0 and fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x19; op2:x19; op3:x18; dest:x20; op1val:0x7d82d835; op2val:0x7d82d835;
op3val:0x7e3e08e0; valaddr_reg:x3; val_offset:33*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.s, x20, x19, x19, x18, dyn, 32, 0, x3, 33*FLEN/8, x4, x1, x2)

inst_12:
// rs1==x18, rs2==x21, rs3==x20, rd==x19,fs1 == 0 and fe1 == 0xfb and fm1 == 0x02d835 and fs2 == 1 and fe2 == 0x82 and fm2 == 0x6a4d3e and fs3 == 0 and fe3 == 0xfc and fm3 == 0x3e08e0 and fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x18; op2:x21; op3:x20; dest:x19; op1val:0x7d82d835; op2val:0xc16a4d3e;
op3val:0x7e3e08e0; valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.s, x19, x18, x21, x20, dyn, 64, 0, x3, 36*FLEN/8, x4, x1, x2)

inst_13:
// rs1==x20, rs2==x17, rs3==x19, rd==x18,fs1 == 0 and fe1 == 0xfb and fm1 == 0x02d835 and fs2 == 1 and fe2 == 0x82 and fm2 == 0x6a4d3e and fs3 == 0 and fe3 == 0xfc and fm3 == 0x3e08e0 and fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x20; op2:x17; op3:x19; dest:x18; op1val:0x7d82d835; op2val:0xc16a4d3e;
op3val:0x7e3e08e0; valaddr_reg:x3; val_offset:39*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.s, x18, x20, x17, x19, dyn, 96, 0, x3, 39*FLEN/8, x4, x1, x2)

inst_14:
// rs1==x16, rs2==x18, rs3==x15, rd==x17,fs1 == 0 and fe1 == 0xfb and fm1 == 0x02d835 and fs2 == 1 and fe2 == 0x82 and fm2 == 0x6a4d3e and fs3 == 0 and fe3 == 0xfc and fm3 == 0x3e08e0 and fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x16; op2:x18; op3:x15; dest:x17; op1val:0x7d82d835; op2val:0xc16a4d3e;
op3val:0x7e3e08e0; valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.s, x17, x16, x18, x15, dyn, 128, 0, x3, 42*FLEN/8, x4, x1, x2)

inst_15:
// rs1==x17, rs2==x15, rs3==x14, rd==x16,fs1 == 0 and fe1 == 0xfe and fm1 == 0x3fd529 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x1af01b and fs3 == 0 and fe3 == 0xfc and fm3 == 0x20d13f and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x17; op2:x15; op3:x14; dest:x16; op1val:0x7f3fd529; op2val:0xbf9af01b;
op3val:0x7e20d13f; valaddr_reg:x3; val_offset:45*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, x16, x17, x15, x14, dyn, 0, 0, x3, 45*FLEN/8, x4, x1, x2)

inst_16:
// rs1==x14, rs2==x16, rs3==x17, rd==x15,fs1 == 0 and fe1 == 0xfe and fm1 == 0x3fd529 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x1af01b and fs3 == 0 and fe3 == 0xfc and fm3 == 0x20d13f and fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x14; op2:x16; op3:x17; dest:x15; op1val:0x7f3fd529; op2val:0xbf9af01b;
op3val:0x7e20d13f; valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.s, x15, x14, x16, x17, dyn, 32, 0, x3, 48*FLEN/8, x4, x1, x2)

inst_17:
// rs1==x15, rs2==x13, rs3==x16, rd==x14,fs1 == 0 and fe1 == 0xfe and fm1 == 0x3fd529 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x1af01b and fs3 == 0 and fe3 == 0xfc and fm3 == 0x20d13f and fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x15; op2:x13; op3:x16; dest:x14; op1val:0x7f3fd529; op2val:0xbf9af01b;
op3val:0x7e20d13f; valaddr_reg:x3; val_offset:51*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.s, x14, x15, x13, x16, dyn, 64, 0, x3, 51*FLEN/8, x4, x1, x2)

inst_18:
// rs1==x12, rs2==x14, rs3==x11, rd==x13,fs1 == 0 and fe1 == 0xfe and fm1 == 0x3fd529 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x1af01b and fs3 == 0 and fe3 == 0xfc and fm3 == 0x20d13f and fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x12; op2:x14; op3:x11; dest:x13; op1val:0x7f3fd529; op2val:0xbf9af01b;
op3val:0x7e20d13f; valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.s, x13, x12, x14, x11, dyn, 96, 0, x3, 54*FLEN/8, x4, x1, x2)

inst_19:
// rs1==x13, rs2==x11, rs3==x10, rd==x12,fs1 == 0 and fe1 == 0xfe and fm1 == 0x3fd529 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x1af01b and fs3 == 0 and fe3 == 0xfc and fm3 == 0x20d13f and fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x13; op2:x11; op3:x10; dest:x12; op1val:0x7f3fd529; op2val:0xbf9af01b;
op3val:0x7e20d13f; valaddr_reg:x3; val_offset:57*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.s, x12, x13, x11, x10, dyn, 128, 0, x3, 57*FLEN/8, x4, x1, x2)

inst_20:
// rs1==x10, rs2==x12, rs3==x13, rd==x11,fs1 == 0 and fe1 == 0xfd and fm1 == 0x767a3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x117d17 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x304eaf and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x10; op2:x12; op3:x13; dest:x11; op1val:0x7ef67a3b; op2val:0xc0117d17;
op3val:0x7eb04eaf; valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, x11, x10, x12, x13, dyn, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
RVTEST_VALBASEUPD(x12,test_dataset_1)

inst_21:
// rs1==x11, rs2==x9, rs3==x12, rd==x10,fs1 == 0 and fe1 == 0xfd and fm1 == 0x767a3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x117d17 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x304eaf and fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x11; op2:x9; op3:x12; dest:x10; op1val:0x7ef67a3b; op2val:0xc0117d17;
op3val:0x7eb04eaf; valaddr_reg:x12; val_offset:0*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.s, x10, x11, x9, x12, dyn, 32, 0, x12, 0*FLEN/8, x13, x1, x2)

inst_22:
// rs1==x8, rs2==x10, rs3==x7, rd==x9,fs1 == 0 and fe1 == 0xfd and fm1 == 0x767a3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x117d17 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x304eaf and fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x8; op2:x10; op3:x7; dest:x9; op1val:0x7ef67a3b; op2val:0xc0117d17;
op3val:0x7eb04eaf; valaddr_reg:x12; val_offset:3*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.s, x9, x8, x10, x7, dyn, 64, 0, x12, 3*FLEN/8, x13, x1, x2)

inst_23:
// rs1==x9, rs2==x7, rs3==x6, rd==x8,fs1 == 0 and fe1 == 0xfd and fm1 == 0x767a3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x117d17 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x304eaf and fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x9; op2:x7; op3:x6; dest:x8; op1val:0x7ef67a3b; op2val:0xc0117d17;
op3val:0x7eb04eaf; valaddr_reg:x12; val_offset:6*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.s, x8, x9, x7, x6, dyn, 96, 0, x12, 6*FLEN/8, x13, x1, x10)
RVTEST_SIGBASE(x9,signature_x9_0)

inst_24:
// rs1==x6, rs2==x8, rs3==x9, rd==x7,fs1 == 0 and fe1 == 0xfd and fm1 == 0x767a3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x117d17 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x304eaf and fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x6; op2:x8; op3:x9; dest:x7; op1val:0x7ef67a3b; op2val:0xc0117d17;
op3val:0x7eb04eaf; valaddr_reg:x12; val_offset:9*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.s, x7, x6, x8, x9, dyn, 128, 0, x12, 9*FLEN/8, x13, x9, x10)

inst_25:
// rs1==x7, rs2==x5, rs3==x8, rd==x6,fs1 == 0 and fe1 == 0xfd and fm1 == 0x2e00ba and fs2 == 1 and fe2 == 0x80 and fm2 == 0x532663 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x3e12c6 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x7; op2:x5; op3:x8; dest:x6; op1val:0x7eae00ba; op2val:0xc0532663;
op3val:0x7ebe12c6; valaddr_reg:x12; val_offset:12*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, x6, x7, x5, x8, dyn, 0, 0, x12, 12*FLEN/8, x13, x9, x10)

inst_26:
// rs1==x4, rs2==x6, rs3==x3, rd==x5,fs1 == 0 and fe1 == 0xfd and fm1 == 0x2e00ba and fs2 == 1 and fe2 == 0x80 and fm2 == 0x532663 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x3e12c6 and fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x4; op2:x6; op3:x3; dest:x5; op1val:0x7eae00ba; op2val:0xc0532663;
op3val:0x7ebe12c6; valaddr_reg:x12; val_offset:15*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.s, x5, x4, x6, x3, dyn, 32, 0, x12, 15*FLEN/8, x13, x9, x10)

inst_27:
// rs1==x5, rs2==x3, rs3==x2, rd==x4,fs1 == 0 and fe1 == 0xfd and fm1 == 0x2e00ba and fs2 == 1 and fe2 == 0x80 and fm2 == 0x532663 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x3e12c6 and fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x5; op2:x3; op3:x2; dest:x4; op1val:0x7eae00ba; op2val:0xc0532663;
op3val:0x7ebe12c6; valaddr_reg:x12; val_offset:18*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.s, x4, x5, x3, x2, dyn, 64, 0, x12, 18*FLEN/8, x13, x9, x10)

inst_28:
// rs1==x2, rs2==x4, rs3==x5, rd==x3,fs1 == 0 and fe1 == 0xfd and fm1 == 0x2e00ba and fs2 == 1 and fe2 == 0x80 and fm2 == 0x532663 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x3e12c6 and fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x2; op2:x4; op3:x5; dest:x3; op1val:0x7eae00ba; op2val:0xc0532663;
op3val:0x7ebe12c6; valaddr_reg:x12; val_offset:21*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.s, x3, x2, x4, x5, dyn, 96, 0, x12, 21*FLEN/8, x13, x9, x10)

inst_29:
// rs1==x3, rs2==x1, rs3==x4, rd==x2,fs1 == 0 and fe1 == 0xfd and fm1 == 0x2e00ba and fs2 == 1 and fe2 == 0x80 and fm2 == 0x532663 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x3e12c6 and fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x3; op2:x1; op3:x4; dest:x2; op1val:0x7eae00ba; op2val:0xc0532663;
op3val:0x7ebe12c6; valaddr_reg:x12; val_offset:24*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.s, x2, x3, x1, x4, dyn, 128, 0, x12, 24*FLEN/8, x13, x9, x10)

inst_30:
// rs1==x1,fs1 == 0 and fe1 == 0xfc and fm1 == 0x13a21e and fs2 == 1 and fe2 == 0x82 and fm2 == 0x185c39 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1f75c7 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x1; op2:x30; op3:x29; dest:x31; op1val:0x7e13a21e; op2val:0xc1185c39;
op3val:0x7f1f75c7; valaddr_reg:x12; val_offset:27*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, x31, x1, x30, x29, dyn, 0, 0, x12, 27*FLEN/8, x13, x9, x10)

inst_31:
// rs1==x0,fs1 == 0 and fe1 == 0xfc and fm1 == 0x13a21e and fs2 == 1 and fe2 == 0x82 and fm2 == 0x185c39 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1f75c7 and fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x0; op2:x30; op3:x29; dest:x31; op1val:0x0; op2val:0xc1185c39;
op3val:0x7f1f75c7; valaddr_reg:x12; val_offset:30*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.s, x31, x0, x30, x29, dyn, 32, 0, x12, 30*FLEN/8, x13, x9, x10)

inst_32:
// rs2==x2,fs1 == 0 and fe1 == 0xfc and fm1 == 0x13a21e and fs2 == 1 and fe2 == 0x82 and fm2 == 0x185c39 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1f75c7 and fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x2; op3:x29; dest:x31; op1val:0x7e13a21e; op2val:0xc1185c39;
op3val:0x7f1f75c7; valaddr_reg:x12; val_offset:33*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x2, x29, dyn, 64, 0, x12, 33*FLEN/8, x13, x9, x10)

inst_33:
// rs2==x0,fs1 == 0 and fe1 == 0xfc and fm1 == 0x13a21e and fs2 == 1 and fe2 == 0x82 and fm2 == 0x185c39 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1f75c7 and fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x0; op3:x29; dest:x31; op1val:0x7e13a21e; op2val:0x0;
op3val:0x7f1f75c7; valaddr_reg:x12; val_offset:36*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x0, x29, dyn, 96, 0, x12, 36*FLEN/8, x13, x9, x10)

inst_34:
// rs3==x1,fs1 == 0 and fe1 == 0xfc and fm1 == 0x13a21e and fs2 == 1 and fe2 == 0x82 and fm2 == 0x185c39 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1f75c7 and fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x1; dest:x31; op1val:0x7e13a21e; op2val:0xc1185c39;
op3val:0x7f1f75c7; valaddr_reg:x12; val_offset:39*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x1, dyn, 128, 0, x12, 39*FLEN/8, x13, x9, x10)

inst_35:
// rs3==x0,fs1 == 0 and fe1 == 0xfb and fm1 == 0x0992a2 and fs2 == 1 and fe2 == 0x82 and fm2 == 0x5c7972 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x33da3d and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x0; dest:x31; op1val:0x7d8992a2; op2val:0xc15c7972;
op3val:0x0; valaddr_reg:x12; val_offset:42*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x0, dyn, 0, 0, x12, 42*FLEN/8, x13, x9, x10)

inst_36:
// rd==x1,fs1 == 0 and fe1 == 0xfb and fm1 == 0x0992a2 and fs2 == 1 and fe2 == 0x82 and fm2 == 0x5c7972 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x33da3d and fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x31; op2:x30; op3:x29; dest:x1; op1val:0x7d8992a2; op2val:0xc15c7972;
op3val:0x7e33da3d; valaddr_reg:x12; val_offset:45*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.s, x1, x31, x30, x29, dyn, 32, 0, x12, 45*FLEN/8, x13, x9, x10)

inst_37:
// rd==x0,fs1 == 0 and fe1 == 0xfb and fm1 == 0x0992a2 and fs2 == 1 and fe2 == 0x82 and fm2 == 0x5c7972 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x33da3d and fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x31; op2:x30; op3:x29; dest:x0; op1val:0x7d8992a2; op2val:0xc15c7972;
op3val:0x7e33da3d; valaddr_reg:x12; val_offset:48*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.s, x0, x31, x30, x29, dyn, 64, 0, x12, 48*FLEN/8, x13, x9, x10)

inst_38:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0992a2 and fs2 == 1 and fe2 == 0x82 and fm2 == 0x5c7972 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x33da3d and fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d8992a2; op2val:0xc15c7972;
op3val:0x7e33da3d; valaddr_reg:x12; val_offset:51*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 96, 0, x12, 51*FLEN/8, x13, x9, x10)

inst_39:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0992a2 and fs2 == 1 and fe2 == 0x82 and fm2 == 0x5c7972 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x33da3d and fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d8992a2; op2val:0xc15c7972;
op3val:0x7e33da3d; valaddr_reg:x12; val_offset:54*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 128, 0, x12, 54*FLEN/8, x13, x9, x10)

inst_40:
// fs1 == 0 and fe1 == 0xf8 and fm1 == 0x75a735 and fs2 == 1 and fe2 == 0x84 and fm2 == 0x7d76b3 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x4ce09d and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c75a735; op2val:0xc27d76b3;
op3val:0x7e4ce09d; valaddr_reg:x12; val_offset:57*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 0, 0, x12, 57*FLEN/8, x13, x9, x10)

inst_41:
// fs1 == 0 and fe1 == 0xf8 and fm1 == 0x75a735 and fs2 == 1 and fe2 == 0x84 and fm2 == 0x7d76b3 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x4ce09d and fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c75a735; op2val:0xc27d76b3;
op3val:0x7e4ce09d; valaddr_reg:x12; val_offset:60*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 32, 0, x12, 60*FLEN/8, x13, x9, x10)

inst_42:
// fs1 == 0 and fe1 == 0xf8 and fm1 == 0x75a735 and fs2 == 1 and fe2 == 0x84 and fm2 == 0x7d76b3 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x4ce09d and fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c75a735; op2val:0xc27d76b3;
op3val:0x7e4ce09d; valaddr_reg:x12; val_offset:63*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 64, 0, x12, 63*FLEN/8, x13, x9, x10)

inst_43:
// fs1 == 0 and fe1 == 0xf8 and fm1 == 0x75a735 and fs2 == 1 and fe2 == 0x84 and fm2 == 0x7d76b3 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x4ce09d and fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c75a735; op2val:0xc27d76b3;
op3val:0x7e4ce09d; valaddr_reg:x12; val_offset:66*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 96, 0, x12, 66*FLEN/8, x13, x9, x10)

inst_44:
// fs1 == 0 and fe1 == 0xf8 and fm1 == 0x75a735 and fs2 == 1 and fe2 == 0x84 and fm2 == 0x7d76b3 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x4ce09d and fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7c75a735; op2val:0xc27d76b3;
op3val:0x7e4ce09d; valaddr_reg:x12; val_offset:69*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 128, 0, x12, 69*FLEN/8, x13, x9, x10)

inst_45:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1c8afc and fs2 == 1 and fe2 == 0x81 and fm2 == 0x154df4 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2d3243 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9c8afc; op2val:0xc0954df4;
op3val:0x7f2d3243; valaddr_reg:x12; val_offset:72*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 0, 0, x12, 72*FLEN/8, x13, x9, x10)

inst_46:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1c8afc and fs2 == 1 and fe2 == 0x81 and fm2 == 0x154df4 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2d3243 and fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9c8afc; op2val:0xc0954df4;
op3val:0x7f2d3243; valaddr_reg:x12; val_offset:75*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 32, 0, x12, 75*FLEN/8, x13, x9, x10)

inst_47:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1c8afc and fs2 == 1 and fe2 == 0x81 and fm2 == 0x154df4 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2d3243 and fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9c8afc; op2val:0xc0954df4;
op3val:0x7f2d3243; valaddr_reg:x12; val_offset:78*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 64, 0, x12, 78*FLEN/8, x13, x9, x10)

inst_48:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1c8afc and fs2 == 1 and fe2 == 0x81 and fm2 == 0x154df4 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2d3243 and fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9c8afc; op2val:0xc0954df4;
op3val:0x7f2d3243; valaddr_reg:x12; val_offset:81*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 96, 0, x12, 81*FLEN/8, x13, x9, x10)

inst_49:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1c8afc and fs2 == 1 and fe2 == 0x81 and fm2 == 0x154df4 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x2d3243 and fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9c8afc; op2val:0xc0954df4;
op3val:0x7f2d3243; valaddr_reg:x12; val_offset:84*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 128, 0, x12, 84*FLEN/8, x13, x9, x10)

inst_50:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1190a0 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3c0882 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x2eb0d1 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9190a0; op2val:0xc03c0882;
op3val:0x7daeb0d1; valaddr_reg:x12; val_offset:87*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 0, 0, x12, 87*FLEN/8, x13, x9, x10)

inst_51:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1190a0 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3c0882 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x2eb0d1 and fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9190a0; op2val:0xc03c0882;
op3val:0x7daeb0d1; valaddr_reg:x12; val_offset:90*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 32, 0, x12, 90*FLEN/8, x13, x9, x10)

inst_52:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1190a0 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3c0882 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x2eb0d1 and fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9190a0; op2val:0xc03c0882;
op3val:0x7daeb0d1; valaddr_reg:x12; val_offset:93*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 64, 0, x12, 93*FLEN/8, x13, x9, x10)

inst_53:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1190a0 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3c0882 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x2eb0d1 and fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9190a0; op2val:0xc03c0882;
op3val:0x7daeb0d1; valaddr_reg:x12; val_offset:96*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 96, 0, x12, 96*FLEN/8, x13, x9, x10)

inst_54:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1190a0 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3c0882 and fs3 == 0 and fe3 == 0xfb and fm3 == 0x2eb0d1 and fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e9190a0; op2val:0xc03c0882;
op3val:0x7daeb0d1; valaddr_reg:x12; val_offset:99*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 128, 0, x12, 99*FLEN/8, x13, x9, x10)

inst_55:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x466afe and fs2 == 1 and fe2 == 0x81 and fm2 == 0x76adec and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3e633d and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e466afe; op2val:0xc0f6adec;
op3val:0x7f3e633d; valaddr_reg:x12; val_offset:102*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 0, 0, x12, 102*FLEN/8, x13, x9, x10)

inst_56:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x466afe and fs2 == 1 and fe2 == 0x81 and fm2 == 0x76adec and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3e633d and fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e466afe; op2val:0xc0f6adec;
op3val:0x7f3e633d; valaddr_reg:x12; val_offset:105*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 32, 0, x12, 105*FLEN/8, x13, x9, x10)

inst_57:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x466afe and fs2 == 1 and fe2 == 0x81 and fm2 == 0x76adec and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3e633d and fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e466afe; op2val:0xc0f6adec;
op3val:0x7f3e633d; valaddr_reg:x12; val_offset:108*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 64, 0, x12, 108*FLEN/8, x13, x9, x10)

inst_58:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x466afe and fs2 == 1 and fe2 == 0x81 and fm2 == 0x76adec and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3e633d and fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e466afe; op2val:0xc0f6adec;
op3val:0x7f3e633d; valaddr_reg:x12; val_offset:111*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 96, 0, x12, 111*FLEN/8, x13, x9, x10)

inst_59:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x466afe and fs2 == 1 and fe2 == 0x81 and fm2 == 0x76adec and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3e633d and fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e466afe; op2val:0xc0f6adec;
op3val:0x7f3e633d; valaddr_reg:x12; val_offset:114*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 128, 0, x12, 114*FLEN/8, x13, x9, x10)

inst_60:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x41cef4 and fs2 == 1 and fe2 == 0x83 and fm2 == 0x4d7248 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x6e24fd and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d41cef4; op2val:0xc1cd7248;
op3val:0x7eee24fd; valaddr_reg:x12; val_offset:117*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 0, 0, x12, 117*FLEN/8, x13, x9, x10)

inst_61:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x41cef4 and fs2 == 1 and fe2 == 0x83 and fm2 == 0x4d7248 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x6e24fd and fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d41cef4; op2val:0xc1cd7248;
op3val:0x7eee24fd; valaddr_reg:x12; val_offset:120*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 32, 0, x12, 120*FLEN/8, x13, x9, x10)

inst_62:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x41cef4 and fs2 == 1 and fe2 == 0x83 and fm2 == 0x4d7248 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x6e24fd and fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d41cef4; op2val:0xc1cd7248;
op3val:0x7eee24fd; valaddr_reg:x12; val_offset:123*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 64, 0, x12, 123*FLEN/8, x13, x9, x10)

inst_63:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x41cef4 and fs2 == 1 and fe2 == 0x83 and fm2 == 0x4d7248 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x6e24fd and fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d41cef4; op2val:0xc1cd7248;
op3val:0x7eee24fd; valaddr_reg:x12; val_offset:126*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 96, 0, x12, 126*FLEN/8, x13, x9, x10)

inst_64:
// fs1 == 0 and fe1 == 0xfa and fm1 == 0x41cef4 and fs2 == 1 and fe2 == 0x83 and fm2 == 0x4d7248 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x6e24fd and fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d41cef4; op2val:0xc1cd7248;
op3val:0x7eee24fd; valaddr_reg:x12; val_offset:129*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 128, 0, x12, 129*FLEN/8, x13, x9, x10)

inst_65:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10d8c5 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x0ce591 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7dc386 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e90d8c5; op2val:0xc08ce591;
op3val:0x7efdc386; valaddr_reg:x12; val_offset:132*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 0, 0, x12, 132*FLEN/8, x13, x9, x10)

inst_66:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10d8c5 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x0ce591 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7dc386 and fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e90d8c5; op2val:0xc08ce591;
op3val:0x7efdc386; valaddr_reg:x12; val_offset:135*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 32, 0, x12, 135*FLEN/8, x13, x9, x10)

inst_67:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10d8c5 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x0ce591 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7dc386 and fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e90d8c5; op2val:0xc08ce591;
op3val:0x7efdc386; valaddr_reg:x12; val_offset:138*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 64, 0, x12, 138*FLEN/8, x13, x9, x10)

inst_68:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10d8c5 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x0ce591 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7dc386 and fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e90d8c5; op2val:0xc08ce591;
op3val:0x7efdc386; valaddr_reg:x12; val_offset:141*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 96, 0, x12, 141*FLEN/8, x13, x9, x10)

inst_69:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10d8c5 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x0ce591 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7dc386 and fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e90d8c5; op2val:0xc08ce591;
op3val:0x7efdc386; valaddr_reg:x12; val_offset:144*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 128, 0, x12, 144*FLEN/8, x13, x9, x10)

inst_70:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x01f5dd and fs2 == 1 and fe2 == 0x80 and fm2 == 0x1a5d90 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x04bacd and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e81f5dd; op2val:0xc01a5d90;
op3val:0x7f04bacd; valaddr_reg:x12; val_offset:147*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 0, 0, x12, 147*FLEN/8, x13, x9, x10)

inst_71:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x01f5dd and fs2 == 1 and fe2 == 0x80 and fm2 == 0x1a5d90 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x04bacd and fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e81f5dd; op2val:0xc01a5d90;
op3val:0x7f04bacd; valaddr_reg:x12; val_offset:150*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 32, 0, x12, 150*FLEN/8, x13, x9, x10)

inst_72:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x01f5dd and fs2 == 1 and fe2 == 0x80 and fm2 == 0x1a5d90 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x04bacd and fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e81f5dd; op2val:0xc01a5d90;
op3val:0x7f04bacd; valaddr_reg:x12; val_offset:153*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 64, 0, x12, 153*FLEN/8, x13, x9, x10)

inst_73:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x01f5dd and fs2 == 1 and fe2 == 0x80 and fm2 == 0x1a5d90 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x04bacd and fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e81f5dd; op2val:0xc01a5d90;
op3val:0x7f04bacd; valaddr_reg:x12; val_offset:156*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 96, 0, x12, 156*FLEN/8, x13, x9, x10)

inst_74:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x01f5dd and fs2 == 1 and fe2 == 0x80 and fm2 == 0x1a5d90 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x04bacd and fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e81f5dd; op2val:0xc01a5d90;
op3val:0x7f04bacd; valaddr_reg:x12; val_offset:159*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 128, 0, x12, 159*FLEN/8, x13, x9, x10)

inst_75:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3f1227 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x06fb59 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x797e34 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ebf1227; op2val:0xbf86fb59;
op3val:0x7ef97e34; valaddr_reg:x12; val_offset:162*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 0, 0, x12, 162*FLEN/8, x13, x9, x10)

inst_76:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3f1227 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x06fb59 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x797e34 and fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ebf1227; op2val:0xbf86fb59;
op3val:0x7ef97e34; valaddr_reg:x12; val_offset:165*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 32, 0, x12, 165*FLEN/8, x13, x9, x10)

inst_77:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3f1227 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x06fb59 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x797e34 and fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ebf1227; op2val:0xbf86fb59;
op3val:0x7ef97e34; valaddr_reg:x12; val_offset:168*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 64, 0, x12, 168*FLEN/8, x13, x9, x10)

inst_78:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3f1227 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x06fb59 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x797e34 and fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ebf1227; op2val:0xbf86fb59;
op3val:0x7ef97e34; valaddr_reg:x12; val_offset:171*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 96, 0, x12, 171*FLEN/8, x13, x9, x10)

inst_79:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3f1227 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x06fb59 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x797e34 and fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ebf1227; op2val:0xbf86fb59;
op3val:0x7ef97e34; valaddr_reg:x12; val_offset:174*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 128, 0, x12, 174*FLEN/8, x13, x9, x10)

inst_80:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2d1061 and fs2 == 1 and fe2 == 0x7e and fm2 == 0x6c2a47 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x5f4f5d and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f2d1061; op2val:0xbf6c2a47;
op3val:0x7edf4f5d; valaddr_reg:x12; val_offset:177*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 0, 0, x12, 177*FLEN/8, x13, x9, x10)

inst_81:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2d1061 and fs2 == 1 and fe2 == 0x7e and fm2 == 0x6c2a47 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x5f4f5d and fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f2d1061; op2val:0xbf6c2a47;
op3val:0x7edf4f5d; valaddr_reg:x12; val_offset:180*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 32, 0, x12, 180*FLEN/8, x13, x9, x10)

inst_82:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2d1061 and fs2 == 1 and fe2 == 0x7e and fm2 == 0x6c2a47 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x5f4f5d and fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f2d1061; op2val:0xbf6c2a47;
op3val:0x7edf4f5d; valaddr_reg:x12; val_offset:183*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 64, 0, x12, 183*FLEN/8, x13, x9, x10)

inst_83:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2d1061 and fs2 == 1 and fe2 == 0x7e and fm2 == 0x6c2a47 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x5f4f5d and fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f2d1061; op2val:0xbf6c2a47;
op3val:0x7edf4f5d; valaddr_reg:x12; val_offset:186*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 96, 0, x12, 186*FLEN/8, x13, x9, x10)

inst_84:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2d1061 and fs2 == 1 and fe2 == 0x7e and fm2 == 0x6c2a47 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x5f4f5d and fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f2d1061; op2val:0xbf6c2a47;
op3val:0x7edf4f5d; valaddr_reg:x12; val_offset:189*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 128, 0, x12, 189*FLEN/8, x13, x9, x10)

inst_85:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x5a52ec and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2729b1 and fs3 == 0 and fe3 == 0xfa and fm3 == 0x45c160 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dda52ec; op2val:0x3fa729b1;
op3val:0x7d45c160; valaddr_reg:x12; val_offset:192*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 0, 0, x12, 192*FLEN/8, x13, x9, x10)

inst_86:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x5a52ec and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2729b1 and fs3 == 0 and fe3 == 0xfa and fm3 == 0x45c160 and fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dda52ec; op2val:0x3fa729b1;
op3val:0x7d45c160; valaddr_reg:x12; val_offset:195*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 32, 0, x12, 195*FLEN/8, x13, x9, x10)

inst_87:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x5a52ec and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2729b1 and fs3 == 0 and fe3 == 0xfa and fm3 == 0x45c160 and fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dda52ec; op2val:0x3fa729b1;
op3val:0x7d45c160; valaddr_reg:x12; val_offset:198*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 64, 0, x12, 198*FLEN/8, x13, x9, x10)

inst_88:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x5a52ec and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2729b1 and fs3 == 0 and fe3 == 0xfa and fm3 == 0x45c160 and fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dda52ec; op2val:0x3fa729b1;
op3val:0x7d45c160; valaddr_reg:x12; val_offset:201*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 96, 0, x12, 201*FLEN/8, x13, x9, x10)

inst_89:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x5a52ec and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2729b1 and fs3 == 0 and fe3 == 0xfa and fm3 == 0x45c160 and fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dda52ec; op2val:0x3fa729b1;
op3val:0x7d45c160; valaddr_reg:x12; val_offset:204*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 128, 0, x12, 204*FLEN/8, x13, x9, x10)

inst_90:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x35a451 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x05c40d and fs3 == 0 and fe3 == 0xfd and fm3 == 0x3ba5e6 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f35a451; op2val:0xbf85c40d;
op3val:0x7ebba5e6; valaddr_reg:x12; val_offset:207*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 0, 0, x12, 207*FLEN/8, x13, x9, x10)

inst_91:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x35a451 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x05c40d and fs3 == 0 and fe3 == 0xfd and fm3 == 0x3ba5e6 and fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f35a451; op2val:0xbf85c40d;
op3val:0x7ebba5e6; valaddr_reg:x12; val_offset:210*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 32, 0, x12, 210*FLEN/8, x13, x9, x10)

inst_92:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x35a451 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x05c40d and fs3 == 0 and fe3 == 0xfd and fm3 == 0x3ba5e6 and fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f35a451; op2val:0xbf85c40d;
op3val:0x7ebba5e6; valaddr_reg:x12; val_offset:213*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 64, 0, x12, 213*FLEN/8, x13, x9, x10)

inst_93:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x35a451 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x05c40d and fs3 == 0 and fe3 == 0xfd and fm3 == 0x3ba5e6 and fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f35a451; op2val:0xbf85c40d;
op3val:0x7ebba5e6; valaddr_reg:x12; val_offset:216*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 96, 0, x12, 216*FLEN/8, x13, x9, x10)

inst_94:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x35a451 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x05c40d and fs3 == 0 and fe3 == 0xfd and fm3 == 0x3ba5e6 and fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f35a451; op2val:0xbf85c40d;
op3val:0x7ebba5e6; valaddr_reg:x12; val_offset:219*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 128, 0, x12, 219*FLEN/8, x13, x9, x10)

inst_95:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x14e13e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x13426c and fs3 == 0 and fe3 == 0xfe and fm3 == 0x35a3f8 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e14e13e; op2val:0xc013426c;
op3val:0x7f35a3f8; valaddr_reg:x12; val_offset:222*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 0, 0, x12, 222*FLEN/8, x13, x9, x10)

inst_96:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x14e13e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x13426c and fs3 == 0 and fe3 == 0xfe and fm3 == 0x35a3f8 and fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e14e13e; op2val:0xc013426c;
op3val:0x7f35a3f8; valaddr_reg:x12; val_offset:225*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 32, 0, x12, 225*FLEN/8, x13, x9, x10)

inst_97:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x14e13e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x13426c and fs3 == 0 and fe3 == 0xfe and fm3 == 0x35a3f8 and fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e14e13e; op2val:0xc013426c;
op3val:0x7f35a3f8; valaddr_reg:x12; val_offset:228*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 64, 0, x12, 228*FLEN/8, x13, x9, x10)

inst_98:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x14e13e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x13426c and fs3 == 0 and fe3 == 0xfe and fm3 == 0x35a3f8 and fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e14e13e; op2val:0xc013426c;
op3val:0x7f35a3f8; valaddr_reg:x12; val_offset:231*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 96, 0, x12, 231*FLEN/8, x13, x9, x10)

inst_99:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x14e13e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x13426c and fs3 == 0 and fe3 == 0xfe and fm3 == 0x35a3f8 and fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e14e13e; op2val:0xc013426c;
op3val:0x7f35a3f8; valaddr_reg:x12; val_offset:234*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 128, 0, x12, 234*FLEN/8, x13, x9, x10)

inst_100:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e5241 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3f1f32 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x0bf4ed and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede5241; op2val:0xc03f1f32;
op3val:0x7f0bf4ed; valaddr_reg:x12; val_offset:237*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 0, 0, x12, 237*FLEN/8, x13, x9, x10)

inst_101:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e5241 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3f1f32 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x0bf4ed and fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede5241; op2val:0xc03f1f32;
op3val:0x7f0bf4ed; valaddr_reg:x12; val_offset:240*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 32, 0, x12, 240*FLEN/8, x13, x9, x10)

inst_102:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e5241 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3f1f32 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x0bf4ed and fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede5241; op2val:0xc03f1f32;
op3val:0x7f0bf4ed; valaddr_reg:x12; val_offset:243*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 64, 0, x12, 243*FLEN/8, x13, x9, x10)

inst_103:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e5241 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3f1f32 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x0bf4ed and fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede5241; op2val:0xc03f1f32;
op3val:0x7f0bf4ed; valaddr_reg:x12; val_offset:246*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 96, 0, x12, 246*FLEN/8, x13, x9, x10)

inst_104:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x5e5241 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3f1f32 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x0bf4ed and fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7ede5241; op2val:0xc03f1f32;
op3val:0x7f0bf4ed; valaddr_reg:x12; val_offset:249*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 128, 0, x12, 249*FLEN/8, x13, x9, x10)

inst_105:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2924ed and fs2 == 0 and fe2 == 0x7e and fm2 == 0x4f9565 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x5b61b5 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f2924ed; op2val:0x3f4f9565;
op3val:0x7e5b61b5; valaddr_reg:x12; val_offset:252*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 0, 0, x12, 252*FLEN/8, x13, x9, x10)

inst_106:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2924ed and fs2 == 0 and fe2 == 0x7e and fm2 == 0x4f9565 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x5b61b5 and fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f2924ed; op2val:0x3f4f9565;
op3val:0x7e5b61b5; valaddr_reg:x12; val_offset:255*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 32, 0, x12, 255*FLEN/8, x13, x9, x10)

inst_107:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2924ed and fs2 == 0 and fe2 == 0x7e and fm2 == 0x4f9565 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x5b61b5 and fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f2924ed; op2val:0x3f4f9565;
op3val:0x7e5b61b5; valaddr_reg:x12; val_offset:258*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 64, 0, x12, 258*FLEN/8, x13, x9, x10)

inst_108:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2924ed and fs2 == 0 and fe2 == 0x7e and fm2 == 0x4f9565 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x5b61b5 and fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f2924ed; op2val:0x3f4f9565;
op3val:0x7e5b61b5; valaddr_reg:x12; val_offset:261*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 96, 0, x12, 261*FLEN/8, x13, x9, x10)

inst_109:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2924ed and fs2 == 0 and fe2 == 0x7e and fm2 == 0x4f9565 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x5b61b5 and fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f2924ed; op2val:0x3f4f9565;
op3val:0x7e5b61b5; valaddr_reg:x12; val_offset:264*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 128, 0, x12, 264*FLEN/8, x13, x9, x10)

inst_110:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x08f8b6 and fs2 == 1 and fe2 == 0x82 and fm2 == 0x01195d and fs3 == 0 and fe3 == 0xfe and fm3 == 0x289736 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e88f8b6; op2val:0xc101195d;
op3val:0x7f289736; valaddr_reg:x12; val_offset:267*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 0, 0, x12, 267*FLEN/8, x13, x9, x10)

inst_111:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x08f8b6 and fs2 == 1 and fe2 == 0x82 and fm2 == 0x01195d and fs3 == 0 and fe3 == 0xfe and fm3 == 0x289736 and fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e88f8b6; op2val:0xc101195d;
op3val:0x7f289736; valaddr_reg:x12; val_offset:270*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 32, 0, x12, 270*FLEN/8, x13, x9, x10)

inst_112:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x08f8b6 and fs2 == 1 and fe2 == 0x82 and fm2 == 0x01195d and fs3 == 0 and fe3 == 0xfe and fm3 == 0x289736 and fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e88f8b6; op2val:0xc101195d;
op3val:0x7f289736; valaddr_reg:x12; val_offset:273*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 64, 0, x12, 273*FLEN/8, x13, x9, x10)

inst_113:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x08f8b6 and fs2 == 1 and fe2 == 0x82 and fm2 == 0x01195d and fs3 == 0 and fe3 == 0xfe and fm3 == 0x289736 and fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e88f8b6; op2val:0xc101195d;
op3val:0x7f289736; valaddr_reg:x12; val_offset:276*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 96, 0, x12, 276*FLEN/8, x13, x9, x10)

inst_114:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x08f8b6 and fs2 == 1 and fe2 == 0x82 and fm2 == 0x01195d and fs3 == 0 and fe3 == 0xfe and fm3 == 0x289736 and fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e88f8b6; op2val:0xc101195d;
op3val:0x7f289736; valaddr_reg:x12; val_offset:279*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 128, 0, x12, 279*FLEN/8, x13, x9, x10)

inst_115:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f529d and fs2 == 0 and fe2 == 0x82 and fm2 == 0x127aef and fs3 == 0 and fe3 == 0xfe and fm3 == 0x12bea4 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dcf529d; op2val:0x41127aef;
op3val:0x7f12bea4; valaddr_reg:x12; val_offset:282*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 0, 0, x12, 282*FLEN/8, x13, x9, x10)

inst_116:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f529d and fs2 == 0 and fe2 == 0x82 and fm2 == 0x127aef and fs3 == 0 and fe3 == 0xfe and fm3 == 0x12bea4 and fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dcf529d; op2val:0x41127aef;
op3val:0x7f12bea4; valaddr_reg:x12; val_offset:285*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 32, 0, x12, 285*FLEN/8, x13, x9, x10)

inst_117:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f529d and fs2 == 0 and fe2 == 0x82 and fm2 == 0x127aef and fs3 == 0 and fe3 == 0xfe and fm3 == 0x12bea4 and fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dcf529d; op2val:0x41127aef;
op3val:0x7f12bea4; valaddr_reg:x12; val_offset:288*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 64, 0, x12, 288*FLEN/8, x13, x9, x10)

inst_118:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f529d and fs2 == 0 and fe2 == 0x82 and fm2 == 0x127aef and fs3 == 0 and fe3 == 0xfe and fm3 == 0x12bea4 and fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dcf529d; op2val:0x41127aef;
op3val:0x7f12bea4; valaddr_reg:x12; val_offset:291*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 96, 0, x12, 291*FLEN/8, x13, x9, x10)

inst_119:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4f529d and fs2 == 0 and fe2 == 0x82 and fm2 == 0x127aef and fs3 == 0 and fe3 == 0xfe and fm3 == 0x12bea4 and fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dcf529d; op2val:0x41127aef;
op3val:0x7f12bea4; valaddr_reg:x12; val_offset:294*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 128, 0, x12, 294*FLEN/8, x13, x9, x10)

inst_120:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x15f05d and fs2 == 1 and fe2 == 0x84 and fm2 == 0x403025 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x0483c9 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d95f05d; op2val:0xc2403025;
op3val:0x7f0483c9; valaddr_reg:x12; val_offset:297*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 0, 0, x12, 297*FLEN/8, x13, x9, x10)

inst_121:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x15f05d and fs2 == 1 and fe2 == 0x84 and fm2 == 0x403025 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x0483c9 and fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d95f05d; op2val:0xc2403025;
op3val:0x7f0483c9; valaddr_reg:x12; val_offset:300*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 32, 0, x12, 300*FLEN/8, x13, x9, x10)

inst_122:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x15f05d and fs2 == 1 and fe2 == 0x84 and fm2 == 0x403025 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x0483c9 and fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d95f05d; op2val:0xc2403025;
op3val:0x7f0483c9; valaddr_reg:x12; val_offset:303*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 64, 0, x12, 303*FLEN/8, x13, x9, x10)

inst_123:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x15f05d and fs2 == 1 and fe2 == 0x84 and fm2 == 0x403025 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x0483c9 and fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d95f05d; op2val:0xc2403025;
op3val:0x7f0483c9; valaddr_reg:x12; val_offset:306*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 96, 0, x12, 306*FLEN/8, x13, x9, x10)

inst_124:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x15f05d and fs2 == 1 and fe2 == 0x84 and fm2 == 0x403025 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x0483c9 and fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d95f05d; op2val:0xc2403025;
op3val:0x7f0483c9; valaddr_reg:x12; val_offset:309*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 128, 0, x12, 309*FLEN/8, x13, x9, x10)

inst_125:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06cfd9 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0b00a7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x366662 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06cfd9; op2val:0x408b00a7;
op3val:0x7f366662; valaddr_reg:x12; val_offset:312*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 0, 0, x12, 312*FLEN/8, x13, x9, x10)

inst_126:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06cfd9 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0b00a7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x366662 and fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06cfd9; op2val:0x408b00a7;
op3val:0x7f366662; valaddr_reg:x12; val_offset:315*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 32, 0, x12, 315*FLEN/8, x13, x9, x10)

inst_127:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06cfd9 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0b00a7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x366662 and fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06cfd9; op2val:0x408b00a7;
op3val:0x7f366662; valaddr_reg:x12; val_offset:318*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 64, 0, x12, 318*FLEN/8, x13, x9, x10)

inst_128:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06cfd9 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0b00a7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x366662 and fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06cfd9; op2val:0x408b00a7;
op3val:0x7f366662; valaddr_reg:x12; val_offset:321*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 96, 0, x12, 321*FLEN/8, x13, x9, x10)

inst_129:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x06cfd9 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0b00a7 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x366662 and fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f06cfd9; op2val:0x408b00a7;
op3val:0x7f366662; valaddr_reg:x12; val_offset:324*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 128, 0, x12, 324*FLEN/8, x13, x9, x10)

inst_130:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21f35d and fs2 == 1 and fe2 == 0x82 and fm2 == 0x214d91 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x4163ff and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21f35d; op2val:0xc1214d91;
op3val:0x7ec163ff; valaddr_reg:x12; val_offset:327*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 0, 0, x12, 327*FLEN/8, x13, x9, x10)

inst_131:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21f35d and fs2 == 1 and fe2 == 0x82 and fm2 == 0x214d91 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x4163ff and fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21f35d; op2val:0xc1214d91;
op3val:0x7ec163ff; valaddr_reg:x12; val_offset:330*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 32, 0, x12, 330*FLEN/8, x13, x9, x10)

inst_132:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21f35d and fs2 == 1 and fe2 == 0x82 and fm2 == 0x214d91 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x4163ff and fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21f35d; op2val:0xc1214d91;
op3val:0x7ec163ff; valaddr_reg:x12; val_offset:333*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 64, 0, x12, 333*FLEN/8, x13, x9, x10)

inst_133:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21f35d and fs2 == 1 and fe2 == 0x82 and fm2 == 0x214d91 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x4163ff and fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21f35d; op2val:0xc1214d91;
op3val:0x7ec163ff; valaddr_reg:x12; val_offset:336*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 96, 0, x12, 336*FLEN/8, x13, x9, x10)

inst_134:
// fs1 == 0 and fe1 == 0xfe and fm1 == 0x21f35d and fs2 == 1 and fe2 == 0x82 and fm2 == 0x214d91 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x4163ff and fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7f21f35d; op2val:0xc1214d91;
op3val:0x7ec163ff; valaddr_reg:x12; val_offset:339*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 128, 0, x12, 339*FLEN/8, x13, x9, x10)

inst_135:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x17cb34 and fs2 == 0 and fe2 == 0x84 and fm2 == 0x1edd6b and fs3 == 0 and fe3 == 0xfb and fm3 == 0x66a542 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e17cb34; op2val:0x421edd6b;
op3val:0x7de6a542; valaddr_reg:x12; val_offset:342*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 0, 0, x12, 342*FLEN/8, x13, x9, x10)

inst_136:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x17cb34 and fs2 == 0 and fe2 == 0x84 and fm2 == 0x1edd6b and fs3 == 0 and fe3 == 0xfb and fm3 == 0x66a542 and fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e17cb34; op2val:0x421edd6b;
op3val:0x7de6a542; valaddr_reg:x12; val_offset:345*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 32, 0, x12, 345*FLEN/8, x13, x9, x10)

inst_137:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x17cb34 and fs2 == 0 and fe2 == 0x84 and fm2 == 0x1edd6b and fs3 == 0 and fe3 == 0xfb and fm3 == 0x66a542 and fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e17cb34; op2val:0x421edd6b;
op3val:0x7de6a542; valaddr_reg:x12; val_offset:348*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 64, 0, x12, 348*FLEN/8, x13, x9, x10)

inst_138:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x17cb34 and fs2 == 0 and fe2 == 0x84 and fm2 == 0x1edd6b and fs3 == 0 and fe3 == 0xfb and fm3 == 0x66a542 and fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e17cb34; op2val:0x421edd6b;
op3val:0x7de6a542; valaddr_reg:x12; val_offset:351*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 96, 0, x12, 351*FLEN/8, x13, x9, x10)

inst_139:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x17cb34 and fs2 == 0 and fe2 == 0x84 and fm2 == 0x1edd6b and fs3 == 0 and fe3 == 0xfb and fm3 == 0x66a542 and fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0x00000000 and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e17cb34; op2val:0x421edd6b;
op3val:0x7de6a542; valaddr_reg:x12; val_offset:354*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 128, 0, x12, 354*FLEN/8, x13, x9, x10)

inst_140:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2e1c2f and fs2 == 1 and fe2 == 0x82 and fm2 == 0x0a7db2 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x38c2b9 and fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e2e1c2f; op2val:0xc10a7db2;
op3val:0x7f38c2b9; valaddr_reg:x12; val_offset:357*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 64, 0, x12, 357*FLEN/8, x13, x9, x10)

inst_141:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2e1c2f and fs2 == 1 and fe2 == 0x82 and fm2 == 0x0a7db2 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x38c2b9 and fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e2e1c2f; op2val:0xc10a7db2;
op3val:0x7f38c2b9; valaddr_reg:x12; val_offset:360*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 96, 0, x12, 360*FLEN/8, x13, x9, x10)

inst_142:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2e1c2f and fs2 == 1 and fe2 == 0x82 and fm2 == 0x0a7db2 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x38c2b9 and fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e2e1c2f; op2val:0xc10a7db2;
op3val:0x7f38c2b9; valaddr_reg:x12; val_offset:363*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:128 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 128, 0, x12, 363*FLEN/8, x13, x9, x10)

inst_143:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x420b54 and fs2 == 1 and fe2 == 0x82 and fm2 == 0x57eaea and fs3 == 0 and fe3 == 0xfe and fm3 == 0x075328 and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dc20b54; op2val:0xc157eaea;
op3val:0x7f075328; valaddr_reg:x12; val_offset:366*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 0, 0, x12, 366*FLEN/8, x13, x9, x10)

inst_144:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x420b54 and fs2 == 1 and fe2 == 0x82 and fm2 == 0x57eaea and fs3 == 0 and fe3 == 0xfe and fm3 == 0x075328 and fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dc20b54; op2val:0xc157eaea;
op3val:0x7f075328; valaddr_reg:x12; val_offset:369*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 32, 0, x12, 369*FLEN/8, x13, x9, x10)

inst_145:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x420b54 and fs2 == 1 and fe2 == 0x82 and fm2 == 0x57eaea and fs3 == 0 and fe3 == 0xfe and fm3 == 0x075328 and fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dc20b54; op2val:0xc157eaea;
op3val:0x7f075328; valaddr_reg:x12; val_offset:372*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 64, 0, x12, 372*FLEN/8, x13, x9, x10)

inst_146:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x420b54 and fs2 == 1 and fe2 == 0x82 and fm2 == 0x57eaea and fs3 == 0 and fe3 == 0xfe and fm3 == 0x075328 and fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7dc20b54; op2val:0xc157eaea;
op3val:0x7f075328; valaddr_reg:x12; val_offset:375*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 96, 0, x12, 375*FLEN/8, x13, x9, x10)

inst_147:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x02d835 and fs2 == 1 and fe2 == 0x82 and fm2 == 0x6a4d3e and fs3 == 0 and fe3 == 0xfc and fm3 == 0x3e08e0 and fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d82d835; op2val:0xc16a4d3e;
op3val:0x7e3e08e0; valaddr_reg:x12; val_offset:378*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 32, 0, x12, 378*FLEN/8, x13, x9, x10)

inst_148:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x13a21e and fs2 == 1 and fe2 == 0x82 and fm2 == 0x185c39 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1f75c7 and fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e13a21e; op2val:0xc1185c39;
op3val:0x7f1f75c7; valaddr_reg:x12; val_offset:381*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:32 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 32, 0, x12, 381*FLEN/8, x13, x9, x10)

inst_149:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x13a21e and fs2 == 1 and fe2 == 0x82 and fm2 == 0x185c39 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x1f75c7 and fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7e13a21e; op2val:0xc1185c39;
op3val:0x7f1f75c7; valaddr_reg:x12; val_offset:384*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:96 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 96, 0, x12, 384*FLEN/8, x13, x9, x10)

inst_150:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0992a2 and fs2 == 1 and fe2 == 0x82 and fm2 == 0x5c7972 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x33da3d and fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d8992a2; op2val:0xc15c7972;
op3val:0x7e33da3d; valaddr_reg:x12; val_offset:387*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 0, 0, x12, 387*FLEN/8, x13, x9, x10)

inst_151:
// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0992a2 and fs2 == 1 and fe2 == 0x82 and fm2 == 0x5c7972 and fs3 == 0 and fe3 == 0xfc and fm3 == 0x33da3d and fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x00000000 and rs2_sgn_prefix == 0xffffffff and rs3_sgn_prefix == 0x00000000  
/* opcode: fnmsub.s ; op1:x30; op2:x29; op3:x28; dest:x31; op1val:0x7d8992a2; op2val:0xc15c7972;
op3val:0x7e33da3d; valaddr_reg:x12; val_offset:390*FLEN/8; rmval:dyn;
testreg:x10; fcsr_val:64 */
TEST_FPR4_OP(fnmsub.s, x31, x30, x29, x28, dyn, 64, 0, x12, 390*FLEN/8, x13, x9, x10)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(2116951087,64,FLEN)
NAN_BOXED(3238690226,32,FLEN)
NAN_BOXED(2134426297,64,FLEN)
NAN_BOXED(2116951087,64,FLEN)
NAN_BOXED(3238690226,32,FLEN)
NAN_BOXED(2134426297,64,FLEN)
NAN_BOXED(2116951087,64,FLEN)
NAN_BOXED(2116951087,32,FLEN)
NAN_BOXED(2134426297,64,FLEN)
NAN_BOXED(2116951087,64,FLEN)
NAN_BOXED(3238690226,32,FLEN)
NAN_BOXED(3238690226,64,FLEN)
NAN_BOXED(2116951087,64,FLEN)
NAN_BOXED(2116951087,32,FLEN)
NAN_BOXED(2116951087,64,FLEN)
NAN_BOXED(2109868884,64,FLEN)
NAN_BOXED(3243764458,32,FLEN)
NAN_BOXED(2109868884,64,FLEN)
NAN_BOXED(2109868884,64,FLEN)
NAN_BOXED(3243764458,32,FLEN)
NAN_BOXED(3243764458,64,FLEN)
NAN_BOXED(2109868884,64,FLEN)
NAN_BOXED(3243764458,32,FLEN)
NAN_BOXED(2109868884,64,FLEN)
NAN_BOXED(2109868884,64,FLEN)
NAN_BOXED(2109868884,32,FLEN)
NAN_BOXED(2109868884,64,FLEN)
NAN_BOXED(2109868884,64,FLEN)
NAN_BOXED(3243764458,32,FLEN)
NAN_BOXED(2131186472,64,FLEN)
NAN_BOXED(2105727029,64,FLEN)
NAN_BOXED(3244969278,32,FLEN)
NAN_BOXED(2117994720,64,FLEN)
NAN_BOXED(2105727029,64,FLEN)
NAN_BOXED(2105727029,32,FLEN)
NAN_BOXED(2117994720,64,FLEN)
NAN_BOXED(2105727029,64,FLEN)
NAN_BOXED(3244969278,32,FLEN)
NAN_BOXED(2117994720,64,FLEN)
NAN_BOXED(2105727029,64,FLEN)
NAN_BOXED(3244969278,32,FLEN)
NAN_BOXED(2117994720,64,FLEN)
NAN_BOXED(2105727029,64,FLEN)
NAN_BOXED(3244969278,32,FLEN)
NAN_BOXED(2117994720,64,FLEN)
NAN_BOXED(2134889769,64,FLEN)
NAN_BOXED(3214602267,32,FLEN)
NAN_BOXED(2116079935,64,FLEN)
NAN_BOXED(2134889769,64,FLEN)
NAN_BOXED(3214602267,32,FLEN)
NAN_BOXED(2116079935,64,FLEN)
NAN_BOXED(2134889769,64,FLEN)
NAN_BOXED(3214602267,32,FLEN)
NAN_BOXED(2116079935,64,FLEN)
NAN_BOXED(2134889769,64,FLEN)
NAN_BOXED(3214602267,32,FLEN)
NAN_BOXED(2116079935,64,FLEN)
NAN_BOXED(2134889769,64,FLEN)
NAN_BOXED(3214602267,32,FLEN)
NAN_BOXED(2116079935,64,FLEN)
NAN_BOXED(2130082363,64,FLEN)
NAN_BOXED(3222371607,32,FLEN)
NAN_BOXED(2125483695,64,FLEN)
test_dataset_1:
NAN_BOXED(2130082363,32,FLEN)
NAN_BOXED(3222371607,32,FLEN)
NAN_BOXED(2125483695,32,FLEN)
NAN_BOXED(2130082363,32,FLEN)
NAN_BOXED(3222371607,32,FLEN)
NAN_BOXED(2125483695,32,FLEN)
NAN_BOXED(2130082363,32,FLEN)
NAN_BOXED(3222371607,32,FLEN)
NAN_BOXED(2125483695,32,FLEN)
NAN_BOXED(2130082363,32,FLEN)
NAN_BOXED(3222371607,32,FLEN)
NAN_BOXED(2125483695,32,FLEN)
NAN_BOXED(2125332666,32,FLEN)
NAN_BOXED(3226674787,32,FLEN)
NAN_BOXED(2126385862,32,FLEN)
NAN_BOXED(2125332666,32,FLEN)
NAN_BOXED(3226674787,32,FLEN)
NAN_BOXED(2126385862,32,FLEN)
NAN_BOXED(2125332666,32,FLEN)
NAN_BOXED(3226674787,32,FLEN)
NAN_BOXED(2126385862,32,FLEN)
NAN_BOXED(2125332666,32,FLEN)
NAN_BOXED(3226674787,32,FLEN)
NAN_BOXED(2126385862,32,FLEN)
NAN_BOXED(2125332666,32,FLEN)
NAN_BOXED(3226674787,32,FLEN)
NAN_BOXED(2126385862,32,FLEN)
NAN_BOXED(2115215902,32,FLEN)
NAN_BOXED(3239599161,32,FLEN)
NAN_BOXED(2132768199,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(3239599161,32,FLEN)
NAN_BOXED(2132768199,32,FLEN)
NAN_BOXED(2115215902,32,FLEN)
NAN_BOXED(3239599161,32,FLEN)
NAN_BOXED(2132768199,32,FLEN)
NAN_BOXED(2115215902,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2132768199,32,FLEN)
NAN_BOXED(2115215902,32,FLEN)
NAN_BOXED(3239599161,32,FLEN)
NAN_BOXED(2132768199,32,FLEN)
NAN_BOXED(2106167970,32,FLEN)
NAN_BOXED(3244063090,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2106167970,32,FLEN)
NAN_BOXED(3244063090,32,FLEN)
NAN_BOXED(2117327421,32,FLEN)
NAN_BOXED(2106167970,32,FLEN)
NAN_BOXED(3244063090,32,FLEN)
NAN_BOXED(2117327421,32,FLEN)
NAN_BOXED(2106167970,32,FLEN)
NAN_BOXED(3244063090,32,FLEN)
NAN_BOXED(2117327421,32,FLEN)
NAN_BOXED(2106167970,32,FLEN)
NAN_BOXED(3244063090,32,FLEN)
NAN_BOXED(2117327421,32,FLEN)
NAN_BOXED(2088085301,32,FLEN)
NAN_BOXED(3263002291,32,FLEN)
NAN_BOXED(2118967453,32,FLEN)
NAN_BOXED(2088085301,32,FLEN)
NAN_BOXED(3263002291,32,FLEN)
NAN_BOXED(2118967453,32,FLEN)
NAN_BOXED(2088085301,32,FLEN)
NAN_BOXED(3263002291,32,FLEN)
NAN_BOXED(2118967453,32,FLEN)
NAN_BOXED(2088085301,32,FLEN)
NAN_BOXED(3263002291,32,FLEN)
NAN_BOXED(2118967453,32,FLEN)
NAN_BOXED(2088085301,32,FLEN)
NAN_BOXED(3263002291,32,FLEN)
NAN_BOXED(2118967453,32,FLEN)
NAN_BOXED(2124188412,32,FLEN)
NAN_BOXED(3231010292,32,FLEN)
NAN_BOXED(2133668419,32,FLEN)
NAN_BOXED(2124188412,32,FLEN)
NAN_BOXED(3231010292,32,FLEN)
NAN_BOXED(2133668419,32,FLEN)
NAN_BOXED(2124188412,32,FLEN)
NAN_BOXED(3231010292,32,FLEN)
NAN_BOXED(2133668419,32,FLEN)
NAN_BOXED(2124188412,32,FLEN)
NAN_BOXED(3231010292,32,FLEN)
NAN_BOXED(2133668419,32,FLEN)
NAN_BOXED(2124188412,32,FLEN)
NAN_BOXED(3231010292,32,FLEN)
NAN_BOXED(2133668419,32,FLEN)
NAN_BOXED(2123468960,32,FLEN)
NAN_BOXED(3225159810,32,FLEN)
NAN_BOXED(2108600529,32,FLEN)
NAN_BOXED(2123468960,32,FLEN)
NAN_BOXED(3225159810,32,FLEN)
NAN_BOXED(2108600529,32,FLEN)
NAN_BOXED(2123468960,32,FLEN)
NAN_BOXED(3225159810,32,FLEN)
NAN_BOXED(2108600529,32,FLEN)
NAN_BOXED(2123468960,32,FLEN)
NAN_BOXED(3225159810,32,FLEN)
NAN_BOXED(2108600529,32,FLEN)
NAN_BOXED(2123468960,32,FLEN)
NAN_BOXED(3225159810,32,FLEN)
NAN_BOXED(2108600529,32,FLEN)
NAN_BOXED(2118544126,32,FLEN)
NAN_BOXED(3237391852,32,FLEN)
NAN_BOXED(2134795069,32,FLEN)
NAN_BOXED(2118544126,32,FLEN)
NAN_BOXED(3237391852,32,FLEN)
NAN_BOXED(2134795069,32,FLEN)
NAN_BOXED(2118544126,32,FLEN)
NAN_BOXED(3237391852,32,FLEN)
NAN_BOXED(2134795069,32,FLEN)
NAN_BOXED(2118544126,32,FLEN)
NAN_BOXED(3237391852,32,FLEN)
NAN_BOXED(2134795069,32,FLEN)
NAN_BOXED(2118544126,32,FLEN)
NAN_BOXED(3237391852,32,FLEN)
NAN_BOXED(2134795069,32,FLEN)
NAN_BOXED(2101464820,32,FLEN)
NAN_BOXED(3251466824,32,FLEN)
NAN_BOXED(2129536253,32,FLEN)
NAN_BOXED(2101464820,32,FLEN)
NAN_BOXED(3251466824,32,FLEN)
NAN_BOXED(2129536253,32,FLEN)
NAN_BOXED(2101464820,32,FLEN)
NAN_BOXED(3251466824,32,FLEN)
NAN_BOXED(2129536253,32,FLEN)
NAN_BOXED(2101464820,32,FLEN)
NAN_BOXED(3251466824,32,FLEN)
NAN_BOXED(2129536253,32,FLEN)
NAN_BOXED(2101464820,32,FLEN)
NAN_BOXED(3251466824,32,FLEN)
NAN_BOXED(2129536253,32,FLEN)
NAN_BOXED(2123421893,32,FLEN)
NAN_BOXED(3230459281,32,FLEN)
NAN_BOXED(2130559878,32,FLEN)
NAN_BOXED(2123421893,32,FLEN)
NAN_BOXED(3230459281,32,FLEN)
NAN_BOXED(2130559878,32,FLEN)
NAN_BOXED(2123421893,32,FLEN)
NAN_BOXED(3230459281,32,FLEN)
NAN_BOXED(2130559878,32,FLEN)
NAN_BOXED(2123421893,32,FLEN)
NAN_BOXED(3230459281,32,FLEN)
NAN_BOXED(2130559878,32,FLEN)
NAN_BOXED(2123421893,32,FLEN)
NAN_BOXED(3230459281,32,FLEN)
NAN_BOXED(2130559878,32,FLEN)
NAN_BOXED(2122446301,32,FLEN)
NAN_BOXED(3222953360,32,FLEN)
NAN_BOXED(2131016397,32,FLEN)
NAN_BOXED(2122446301,32,FLEN)
NAN_BOXED(3222953360,32,FLEN)
NAN_BOXED(2131016397,32,FLEN)
NAN_BOXED(2122446301,32,FLEN)
NAN_BOXED(3222953360,32,FLEN)
NAN_BOXED(2131016397,32,FLEN)
NAN_BOXED(2122446301,32,FLEN)
NAN_BOXED(3222953360,32,FLEN)
NAN_BOXED(2131016397,32,FLEN)
NAN_BOXED(2122446301,32,FLEN)
NAN_BOXED(3222953360,32,FLEN)
NAN_BOXED(2131016397,32,FLEN)
NAN_BOXED(2126451239,32,FLEN)
NAN_BOXED(3213294425,32,FLEN)
NAN_BOXED(2130279988,32,FLEN)
NAN_BOXED(2126451239,32,FLEN)
NAN_BOXED(3213294425,32,FLEN)
NAN_BOXED(2130279988,32,FLEN)
NAN_BOXED(2126451239,32,FLEN)
NAN_BOXED(3213294425,32,FLEN)
NAN_BOXED(2130279988,32,FLEN)
NAN_BOXED(2126451239,32,FLEN)
NAN_BOXED(3213294425,32,FLEN)
NAN_BOXED(2130279988,32,FLEN)
NAN_BOXED(2126451239,32,FLEN)
NAN_BOXED(3213294425,32,FLEN)
NAN_BOXED(2130279988,32,FLEN)
NAN_BOXED(2133659745,32,FLEN)
NAN_BOXED(3211536967,32,FLEN)
NAN_BOXED(2128564061,32,FLEN)
NAN_BOXED(2133659745,32,FLEN)
NAN_BOXED(3211536967,32,FLEN)
NAN_BOXED(2128564061,32,FLEN)
NAN_BOXED(2133659745,32,FLEN)
NAN_BOXED(3211536967,32,FLEN)
NAN_BOXED(2128564061,32,FLEN)
NAN_BOXED(2133659745,32,FLEN)
NAN_BOXED(3211536967,32,FLEN)
NAN_BOXED(2128564061,32,FLEN)
NAN_BOXED(2133659745,32,FLEN)
NAN_BOXED(3211536967,32,FLEN)
NAN_BOXED(2128564061,32,FLEN)
NAN_BOXED(2111460076,32,FLEN)
NAN_BOXED(1067919793,32,FLEN)
NAN_BOXED(2101723488,32,FLEN)
NAN_BOXED(2111460076,32,FLEN)
NAN_BOXED(1067919793,32,FLEN)
NAN_BOXED(2101723488,32,FLEN)
NAN_BOXED(2111460076,32,FLEN)
NAN_BOXED(1067919793,32,FLEN)
NAN_BOXED(2101723488,32,FLEN)
NAN_BOXED(2111460076,32,FLEN)
NAN_BOXED(1067919793,32,FLEN)
NAN_BOXED(2101723488,32,FLEN)
NAN_BOXED(2111460076,32,FLEN)
NAN_BOXED(1067919793,32,FLEN)
NAN_BOXED(2101723488,32,FLEN)
NAN_BOXED(2134221905,32,FLEN)
NAN_BOXED(3213214733,32,FLEN)
NAN_BOXED(2126226918,32,FLEN)
NAN_BOXED(2134221905,32,FLEN)
NAN_BOXED(3213214733,32,FLEN)
NAN_BOXED(2126226918,32,FLEN)
NAN_BOXED(2134221905,32,FLEN)
NAN_BOXED(3213214733,32,FLEN)
NAN_BOXED(2126226918,32,FLEN)
NAN_BOXED(2134221905,32,FLEN)
NAN_BOXED(3213214733,32,FLEN)
NAN_BOXED(2126226918,32,FLEN)
NAN_BOXED(2134221905,32,FLEN)
NAN_BOXED(3213214733,32,FLEN)
NAN_BOXED(2126226918,32,FLEN)
NAN_BOXED(2115297598,32,FLEN)
NAN_BOXED(3222487660,32,FLEN)
NAN_BOXED(2134221816,32,FLEN)
NAN_BOXED(2115297598,32,FLEN)
NAN_BOXED(3222487660,32,FLEN)
NAN_BOXED(2134221816,32,FLEN)
NAN_BOXED(2115297598,32,FLEN)
NAN_BOXED(3222487660,32,FLEN)
NAN_BOXED(2134221816,32,FLEN)
NAN_BOXED(2115297598,32,FLEN)
NAN_BOXED(3222487660,32,FLEN)
NAN_BOXED(2134221816,32,FLEN)
NAN_BOXED(2115297598,32,FLEN)
NAN_BOXED(3222487660,32,FLEN)
NAN_BOXED(2134221816,32,FLEN)
NAN_BOXED(2128499265,32,FLEN)
NAN_BOXED(3225362226,32,FLEN)
NAN_BOXED(2131490029,32,FLEN)
NAN_BOXED(2128499265,32,FLEN)
NAN_BOXED(3225362226,32,FLEN)
NAN_BOXED(2131490029,32,FLEN)
NAN_BOXED(2128499265,32,FLEN)
NAN_BOXED(3225362226,32,FLEN)
NAN_BOXED(2131490029,32,FLEN)
NAN_BOXED(2128499265,32,FLEN)
NAN_BOXED(3225362226,32,FLEN)
NAN_BOXED(2131490029,32,FLEN)
NAN_BOXED(2128499265,32,FLEN)
NAN_BOXED(3225362226,32,FLEN)
NAN_BOXED(2131490029,32,FLEN)
NAN_BOXED(2133402861,32,FLEN)
NAN_BOXED(1062180197,32,FLEN)
NAN_BOXED(2119918005,32,FLEN)
NAN_BOXED(2133402861,32,FLEN)
NAN_BOXED(1062180197,32,FLEN)
NAN_BOXED(2119918005,32,FLEN)
NAN_BOXED(2133402861,32,FLEN)
NAN_BOXED(1062180197,32,FLEN)
NAN_BOXED(2119918005,32,FLEN)
NAN_BOXED(2133402861,32,FLEN)
NAN_BOXED(1062180197,32,FLEN)
NAN_BOXED(2119918005,32,FLEN)
NAN_BOXED(2133402861,32,FLEN)
NAN_BOXED(1062180197,32,FLEN)
NAN_BOXED(2119918005,32,FLEN)
NAN_BOXED(2122905782,32,FLEN)
NAN_BOXED(3238074717,32,FLEN)
NAN_BOXED(2133366582,32,FLEN)
NAN_BOXED(2122905782,32,FLEN)
NAN_BOXED(3238074717,32,FLEN)
NAN_BOXED(2133366582,32,FLEN)
NAN_BOXED(2122905782,32,FLEN)
NAN_BOXED(3238074717,32,FLEN)
NAN_BOXED(2133366582,32,FLEN)
NAN_BOXED(2122905782,32,FLEN)
NAN_BOXED(3238074717,32,FLEN)
NAN_BOXED(2133366582,32,FLEN)
NAN_BOXED(2122905782,32,FLEN)
NAN_BOXED(3238074717,32,FLEN)
NAN_BOXED(2133366582,32,FLEN)
NAN_BOXED(2110739101,32,FLEN)
NAN_BOXED(1091730159,32,FLEN)
NAN_BOXED(2131934884,32,FLEN)
NAN_BOXED(2110739101,32,FLEN)
NAN_BOXED(1091730159,32,FLEN)
NAN_BOXED(2131934884,32,FLEN)
NAN_BOXED(2110739101,32,FLEN)
NAN_BOXED(1091730159,32,FLEN)
NAN_BOXED(2131934884,32,FLEN)
NAN_BOXED(2110739101,32,FLEN)
NAN_BOXED(1091730159,32,FLEN)
NAN_BOXED(2131934884,32,FLEN)
NAN_BOXED(2110739101,32,FLEN)
NAN_BOXED(1091730159,32,FLEN)
NAN_BOXED(2131934884,32,FLEN)
NAN_BOXED(2106978397,32,FLEN)
NAN_BOXED(3258986533,32,FLEN)
NAN_BOXED(2131002313,32,FLEN)
NAN_BOXED(2106978397,32,FLEN)
NAN_BOXED(3258986533,32,FLEN)
NAN_BOXED(2131002313,32,FLEN)
NAN_BOXED(2106978397,32,FLEN)
NAN_BOXED(3258986533,32,FLEN)
NAN_BOXED(2131002313,32,FLEN)
NAN_BOXED(2106978397,32,FLEN)
NAN_BOXED(3258986533,32,FLEN)
NAN_BOXED(2131002313,32,FLEN)
NAN_BOXED(2106978397,32,FLEN)
NAN_BOXED(3258986533,32,FLEN)
NAN_BOXED(2131002313,32,FLEN)
NAN_BOXED(2131152857,32,FLEN)
NAN_BOXED(1082851495,32,FLEN)
NAN_BOXED(2134271586,32,FLEN)
NAN_BOXED(2131152857,32,FLEN)
NAN_BOXED(1082851495,32,FLEN)
NAN_BOXED(2134271586,32,FLEN)
NAN_BOXED(2131152857,32,FLEN)
NAN_BOXED(1082851495,32,FLEN)
NAN_BOXED(2134271586,32,FLEN)
NAN_BOXED(2131152857,32,FLEN)
NAN_BOXED(1082851495,32,FLEN)
NAN_BOXED(2134271586,32,FLEN)
NAN_BOXED(2131152857,32,FLEN)
NAN_BOXED(1082851495,32,FLEN)
NAN_BOXED(2134271586,32,FLEN)
NAN_BOXED(2132931421,32,FLEN)
NAN_BOXED(3240185233,32,FLEN)
NAN_BOXED(2126603263,32,FLEN)
NAN_BOXED(2132931421,32,FLEN)
NAN_BOXED(3240185233,32,FLEN)
NAN_BOXED(2126603263,32,FLEN)
NAN_BOXED(2132931421,32,FLEN)
NAN_BOXED(3240185233,32,FLEN)
NAN_BOXED(2126603263,32,FLEN)
NAN_BOXED(2132931421,32,FLEN)
NAN_BOXED(3240185233,32,FLEN)
NAN_BOXED(2126603263,32,FLEN)
NAN_BOXED(2132931421,32,FLEN)
NAN_BOXED(3240185233,32,FLEN)
NAN_BOXED(2126603263,32,FLEN)
NAN_BOXED(2115488564,32,FLEN)
NAN_BOXED(1109319019,32,FLEN)
NAN_BOXED(2112267586,32,FLEN)
NAN_BOXED(2115488564,32,FLEN)
NAN_BOXED(1109319019,32,FLEN)
NAN_BOXED(2112267586,32,FLEN)
NAN_BOXED(2115488564,32,FLEN)
NAN_BOXED(1109319019,32,FLEN)
NAN_BOXED(2112267586,32,FLEN)
NAN_BOXED(2115488564,32,FLEN)
NAN_BOXED(1109319019,32,FLEN)
NAN_BOXED(2112267586,32,FLEN)
NAN_BOXED(2115488564,32,FLEN)
NAN_BOXED(1109319019,32,FLEN)
NAN_BOXED(2112267586,32,FLEN)
NAN_BOXED(2116951087,32,FLEN)
NAN_BOXED(3238690226,32,FLEN)
NAN_BOXED(2134426297,32,FLEN)
NAN_BOXED(2116951087,32,FLEN)
NAN_BOXED(3238690226,32,FLEN)
NAN_BOXED(2134426297,32,FLEN)
NAN_BOXED(2116951087,32,FLEN)
NAN_BOXED(3238690226,32,FLEN)
NAN_BOXED(2134426297,32,FLEN)
NAN_BOXED(2109868884,32,FLEN)
NAN_BOXED(3243764458,32,FLEN)
NAN_BOXED(2131186472,32,FLEN)
NAN_BOXED(2109868884,32,FLEN)
NAN_BOXED(3243764458,32,FLEN)
NAN_BOXED(2131186472,32,FLEN)
NAN_BOXED(2109868884,32,FLEN)
NAN_BOXED(3243764458,32,FLEN)
NAN_BOXED(2131186472,32,FLEN)
NAN_BOXED(2109868884,32,FLEN)
NAN_BOXED(3243764458,32,FLEN)
NAN_BOXED(2131186472,32,FLEN)
NAN_BOXED(2105727029,32,FLEN)
NAN_BOXED(3244969278,32,FLEN)
NAN_BOXED(2117994720,32,FLEN)
NAN_BOXED(2115215902,32,FLEN)
NAN_BOXED(3239599161,32,FLEN)
NAN_BOXED(2132768199,32,FLEN)
NAN_BOXED(2115215902,32,FLEN)
NAN_BOXED(3239599161,32,FLEN)
NAN_BOXED(2132768199,32,FLEN)
NAN_BOXED(2106167970,32,FLEN)
NAN_BOXED(3244063090,32,FLEN)
NAN_BOXED(2117327421,32,FLEN)
NAN_BOXED(2106167970,32,FLEN)
NAN_BOXED(3244063090,32,FLEN)
NAN_BOXED(2117327421,32,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;



signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 48*((SIGALIGN)/4),4,0xdeadbeef


signature_x9_0:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;

mtrap_sigptr:
    .fill 64*XLEN/32,4,0xdeadbeef

tsig_end_canary:
CANARY;
#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif


sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
