
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.7.1
// timestamp : Fri Jun 17 14:18:09 2022 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /scratch/pawan/work/normalised/RV32F/fnmadd.s.cgf \
 \
//                  -- xlen 32  \
//                  --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fnmadd.s instruction of the RISC-V RV32F_Zicsr,RV32FD_Zicsr,RV64F_Zicsr,RV64FD_Zicsr extension for the fnmadd_b15 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*);def TEST_CASE_1=True;",fnmadd_b15)
RVTEST_CASE(1,"//check ISA:=regex(.*E.*F.*);def TEST_CASE_1=True;",fnmadd_b15)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_13056:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x09edf2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x12 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e89edf2; op2val:0x80000000;
op3val:0x89600000; valaddr_reg:x3; val_offset:39168*0 + 3*-1*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39168*0 + 3*0*FLEN/8, x4, x1, x2)

inst_13057:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x09edf2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x12 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e89edf2; op2val:0x80000000;
op3val:0x89700000; valaddr_reg:x3; val_offset:39171*0 + 3*0*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39171*0 + 3*1*FLEN/8, x4, x1, x2)

inst_13058:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x09edf2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x12 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e89edf2; op2val:0x80000000;
op3val:0x89780000; valaddr_reg:x3; val_offset:39174*0 + 3*1*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39174*0 + 3*2*FLEN/8, x4, x1, x2)

inst_13059:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x09edf2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x12 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e89edf2; op2val:0x80000000;
op3val:0x897c0000; valaddr_reg:x3; val_offset:39177*0 + 3*2*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39177*0 + 3*3*FLEN/8, x4, x1, x2)

inst_13060:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x09edf2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x12 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e89edf2; op2val:0x80000000;
op3val:0x897e0000; valaddr_reg:x3; val_offset:39180*0 + 3*3*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39180*0 + 3*4*FLEN/8, x4, x1, x2)

inst_13061:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x09edf2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x12 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e89edf2; op2val:0x80000000;
op3val:0x897f0000; valaddr_reg:x3; val_offset:39183*0 + 3*4*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39183*0 + 3*5*FLEN/8, x4, x1, x2)

inst_13062:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x09edf2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x12 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e89edf2; op2val:0x80000000;
op3val:0x897f8000; valaddr_reg:x3; val_offset:39186*0 + 3*5*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39186*0 + 3*6*FLEN/8, x4, x1, x2)

inst_13063:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x09edf2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x12 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e89edf2; op2val:0x80000000;
op3val:0x897fc000; valaddr_reg:x3; val_offset:39189*0 + 3*6*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39189*0 + 3*7*FLEN/8, x4, x1, x2)

inst_13064:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x09edf2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x12 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e89edf2; op2val:0x80000000;
op3val:0x897fe000; valaddr_reg:x3; val_offset:39192*0 + 3*7*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39192*0 + 3*8*FLEN/8, x4, x1, x2)

inst_13065:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x09edf2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x12 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e89edf2; op2val:0x80000000;
op3val:0x897ff000; valaddr_reg:x3; val_offset:39195*0 + 3*8*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39195*0 + 3*9*FLEN/8, x4, x1, x2)

inst_13066:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x09edf2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x12 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e89edf2; op2val:0x80000000;
op3val:0x897ff800; valaddr_reg:x3; val_offset:39198*0 + 3*9*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39198*0 + 3*10*FLEN/8, x4, x1, x2)

inst_13067:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x09edf2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x12 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e89edf2; op2val:0x80000000;
op3val:0x897ffc00; valaddr_reg:x3; val_offset:39201*0 + 3*10*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39201*0 + 3*11*FLEN/8, x4, x1, x2)

inst_13068:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x09edf2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x12 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e89edf2; op2val:0x80000000;
op3val:0x897ffe00; valaddr_reg:x3; val_offset:39204*0 + 3*11*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39204*0 + 3*12*FLEN/8, x4, x1, x2)

inst_13069:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x09edf2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x12 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e89edf2; op2val:0x80000000;
op3val:0x897fff00; valaddr_reg:x3; val_offset:39207*0 + 3*12*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39207*0 + 3*13*FLEN/8, x4, x1, x2)

inst_13070:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x09edf2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x12 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e89edf2; op2val:0x80000000;
op3val:0x897fff80; valaddr_reg:x3; val_offset:39210*0 + 3*13*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39210*0 + 3*14*FLEN/8, x4, x1, x2)

inst_13071:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x09edf2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x12 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e89edf2; op2val:0x80000000;
op3val:0x897fffc0; valaddr_reg:x3; val_offset:39213*0 + 3*14*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39213*0 + 3*15*FLEN/8, x4, x1, x2)

inst_13072:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x09edf2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x12 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e89edf2; op2val:0x80000000;
op3val:0x897fffe0; valaddr_reg:x3; val_offset:39216*0 + 3*15*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39216*0 + 3*16*FLEN/8, x4, x1, x2)

inst_13073:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x09edf2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x12 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e89edf2; op2val:0x80000000;
op3val:0x897ffff0; valaddr_reg:x3; val_offset:39219*0 + 3*16*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39219*0 + 3*17*FLEN/8, x4, x1, x2)

inst_13074:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x09edf2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x12 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e89edf2; op2val:0x80000000;
op3val:0x897ffff8; valaddr_reg:x3; val_offset:39222*0 + 3*17*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39222*0 + 3*18*FLEN/8, x4, x1, x2)

inst_13075:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x09edf2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x12 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e89edf2; op2val:0x80000000;
op3val:0x897ffffc; valaddr_reg:x3; val_offset:39225*0 + 3*18*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39225*0 + 3*19*FLEN/8, x4, x1, x2)

inst_13076:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x09edf2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x12 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e89edf2; op2val:0x80000000;
op3val:0x897ffffe; valaddr_reg:x3; val_offset:39228*0 + 3*19*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39228*0 + 3*20*FLEN/8, x4, x1, x2)

inst_13077:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x09edf2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x12 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e89edf2; op2val:0x80000000;
op3val:0x897fffff; valaddr_reg:x3; val_offset:39231*0 + 3*20*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39231*0 + 3*21*FLEN/8, x4, x1, x2)

inst_13078:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x71800000; valaddr_reg:x3; val_offset:39234*0 + 3*21*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39234*0 + 3*22*FLEN/8, x4, x1, x2)

inst_13079:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x71800001; valaddr_reg:x3; val_offset:39237*0 + 3*22*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39237*0 + 3*23*FLEN/8, x4, x1, x2)

inst_13080:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x71800003; valaddr_reg:x3; val_offset:39240*0 + 3*23*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39240*0 + 3*24*FLEN/8, x4, x1, x2)

inst_13081:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x71800007; valaddr_reg:x3; val_offset:39243*0 + 3*24*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39243*0 + 3*25*FLEN/8, x4, x1, x2)

inst_13082:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x7180000f; valaddr_reg:x3; val_offset:39246*0 + 3*25*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39246*0 + 3*26*FLEN/8, x4, x1, x2)

inst_13083:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x7180001f; valaddr_reg:x3; val_offset:39249*0 + 3*26*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39249*0 + 3*27*FLEN/8, x4, x1, x2)

inst_13084:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x7180003f; valaddr_reg:x3; val_offset:39252*0 + 3*27*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39252*0 + 3*28*FLEN/8, x4, x1, x2)

inst_13085:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x7180007f; valaddr_reg:x3; val_offset:39255*0 + 3*28*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39255*0 + 3*29*FLEN/8, x4, x1, x2)

inst_13086:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x718000ff; valaddr_reg:x3; val_offset:39258*0 + 3*29*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39258*0 + 3*30*FLEN/8, x4, x1, x2)

inst_13087:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x718001ff; valaddr_reg:x3; val_offset:39261*0 + 3*30*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39261*0 + 3*31*FLEN/8, x4, x1, x2)

inst_13088:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x718003ff; valaddr_reg:x3; val_offset:39264*0 + 3*31*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39264*0 + 3*32*FLEN/8, x4, x1, x2)

inst_13089:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x718007ff; valaddr_reg:x3; val_offset:39267*0 + 3*32*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39267*0 + 3*33*FLEN/8, x4, x1, x2)

inst_13090:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x71800fff; valaddr_reg:x3; val_offset:39270*0 + 3*33*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39270*0 + 3*34*FLEN/8, x4, x1, x2)

inst_13091:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x71801fff; valaddr_reg:x3; val_offset:39273*0 + 3*34*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39273*0 + 3*35*FLEN/8, x4, x1, x2)

inst_13092:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x71803fff; valaddr_reg:x3; val_offset:39276*0 + 3*35*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39276*0 + 3*36*FLEN/8, x4, x1, x2)

inst_13093:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x71807fff; valaddr_reg:x3; val_offset:39279*0 + 3*36*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39279*0 + 3*37*FLEN/8, x4, x1, x2)

inst_13094:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x7180ffff; valaddr_reg:x3; val_offset:39282*0 + 3*37*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39282*0 + 3*38*FLEN/8, x4, x1, x2)

inst_13095:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x7181ffff; valaddr_reg:x3; val_offset:39285*0 + 3*38*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39285*0 + 3*39*FLEN/8, x4, x1, x2)

inst_13096:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x7183ffff; valaddr_reg:x3; val_offset:39288*0 + 3*39*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39288*0 + 3*40*FLEN/8, x4, x1, x2)

inst_13097:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x7187ffff; valaddr_reg:x3; val_offset:39291*0 + 3*40*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39291*0 + 3*41*FLEN/8, x4, x1, x2)

inst_13098:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x718fffff; valaddr_reg:x3; val_offset:39294*0 + 3*41*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39294*0 + 3*42*FLEN/8, x4, x1, x2)

inst_13099:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x719fffff; valaddr_reg:x3; val_offset:39297*0 + 3*42*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39297*0 + 3*43*FLEN/8, x4, x1, x2)

inst_13100:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x71bfffff; valaddr_reg:x3; val_offset:39300*0 + 3*43*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39300*0 + 3*44*FLEN/8, x4, x1, x2)

inst_13101:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x71c00000; valaddr_reg:x3; val_offset:39303*0 + 3*44*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39303*0 + 3*45*FLEN/8, x4, x1, x2)

inst_13102:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x71e00000; valaddr_reg:x3; val_offset:39306*0 + 3*45*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39306*0 + 3*46*FLEN/8, x4, x1, x2)

inst_13103:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x71f00000; valaddr_reg:x3; val_offset:39309*0 + 3*46*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39309*0 + 3*47*FLEN/8, x4, x1, x2)

inst_13104:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x71f80000; valaddr_reg:x3; val_offset:39312*0 + 3*47*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39312*0 + 3*48*FLEN/8, x4, x1, x2)

inst_13105:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x71fc0000; valaddr_reg:x3; val_offset:39315*0 + 3*48*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39315*0 + 3*49*FLEN/8, x4, x1, x2)

inst_13106:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x71fe0000; valaddr_reg:x3; val_offset:39318*0 + 3*49*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39318*0 + 3*50*FLEN/8, x4, x1, x2)

inst_13107:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x71ff0000; valaddr_reg:x3; val_offset:39321*0 + 3*50*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39321*0 + 3*51*FLEN/8, x4, x1, x2)

inst_13108:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x71ff8000; valaddr_reg:x3; val_offset:39324*0 + 3*51*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39324*0 + 3*52*FLEN/8, x4, x1, x2)

inst_13109:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x71ffc000; valaddr_reg:x3; val_offset:39327*0 + 3*52*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39327*0 + 3*53*FLEN/8, x4, x1, x2)

inst_13110:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x71ffe000; valaddr_reg:x3; val_offset:39330*0 + 3*53*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39330*0 + 3*54*FLEN/8, x4, x1, x2)

inst_13111:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x71fff000; valaddr_reg:x3; val_offset:39333*0 + 3*54*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39333*0 + 3*55*FLEN/8, x4, x1, x2)

inst_13112:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x71fff800; valaddr_reg:x3; val_offset:39336*0 + 3*55*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39336*0 + 3*56*FLEN/8, x4, x1, x2)

inst_13113:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x71fffc00; valaddr_reg:x3; val_offset:39339*0 + 3*56*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39339*0 + 3*57*FLEN/8, x4, x1, x2)

inst_13114:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x71fffe00; valaddr_reg:x3; val_offset:39342*0 + 3*57*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39342*0 + 3*58*FLEN/8, x4, x1, x2)

inst_13115:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x71ffff00; valaddr_reg:x3; val_offset:39345*0 + 3*58*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39345*0 + 3*59*FLEN/8, x4, x1, x2)

inst_13116:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x71ffff80; valaddr_reg:x3; val_offset:39348*0 + 3*59*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39348*0 + 3*60*FLEN/8, x4, x1, x2)

inst_13117:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x71ffffc0; valaddr_reg:x3; val_offset:39351*0 + 3*60*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39351*0 + 3*61*FLEN/8, x4, x1, x2)

inst_13118:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x71ffffe0; valaddr_reg:x3; val_offset:39354*0 + 3*61*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39354*0 + 3*62*FLEN/8, x4, x1, x2)

inst_13119:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x71fffff0; valaddr_reg:x3; val_offset:39357*0 + 3*62*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39357*0 + 3*63*FLEN/8, x4, x1, x2)

inst_13120:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x71fffff8; valaddr_reg:x3; val_offset:39360*0 + 3*63*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39360*0 + 3*64*FLEN/8, x4, x1, x2)

inst_13121:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x71fffffc; valaddr_reg:x3; val_offset:39363*0 + 3*64*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39363*0 + 3*65*FLEN/8, x4, x1, x2)

inst_13122:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x71fffffe; valaddr_reg:x3; val_offset:39366*0 + 3*65*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39366*0 + 3*66*FLEN/8, x4, x1, x2)

inst_13123:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xe3 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x71ffffff; valaddr_reg:x3; val_offset:39369*0 + 3*66*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39369*0 + 3*67*FLEN/8, x4, x1, x2)

inst_13124:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x7f000001; valaddr_reg:x3; val_offset:39372*0 + 3*67*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39372*0 + 3*68*FLEN/8, x4, x1, x2)

inst_13125:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x7f000003; valaddr_reg:x3; val_offset:39375*0 + 3*68*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39375*0 + 3*69*FLEN/8, x4, x1, x2)

inst_13126:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x7f000007; valaddr_reg:x3; val_offset:39378*0 + 3*69*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39378*0 + 3*70*FLEN/8, x4, x1, x2)

inst_13127:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xfe and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x7f199999; valaddr_reg:x3; val_offset:39381*0 + 3*70*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39381*0 + 3*71*FLEN/8, x4, x1, x2)

inst_13128:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xfe and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x7f249249; valaddr_reg:x3; val_offset:39384*0 + 3*71*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39384*0 + 3*72*FLEN/8, x4, x1, x2)

inst_13129:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xfe and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x7f333333; valaddr_reg:x3; val_offset:39387*0 + 3*72*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39387*0 + 3*73*FLEN/8, x4, x1, x2)

inst_13130:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xfe and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x7f36db6d; valaddr_reg:x3; val_offset:39390*0 + 3*73*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39390*0 + 3*74*FLEN/8, x4, x1, x2)

inst_13131:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x7f3bbbbb; valaddr_reg:x3; val_offset:39393*0 + 3*74*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39393*0 + 3*75*FLEN/8, x4, x1, x2)

inst_13132:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xfe and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x7f444444; valaddr_reg:x3; val_offset:39396*0 + 3*75*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39396*0 + 3*76*FLEN/8, x4, x1, x2)

inst_13133:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xfe and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x7f4ccccc; valaddr_reg:x3; val_offset:39399*0 + 3*76*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39399*0 + 3*77*FLEN/8, x4, x1, x2)

inst_13134:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xfe and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x7f5b6db6; valaddr_reg:x3; val_offset:39402*0 + 3*77*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39402*0 + 3*78*FLEN/8, x4, x1, x2)

inst_13135:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xfe and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x7f666666; valaddr_reg:x3; val_offset:39405*0 + 3*78*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39405*0 + 3*79*FLEN/8, x4, x1, x2)

inst_13136:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xfe and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x7f6db6db; valaddr_reg:x3; val_offset:39408*0 + 3*79*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39408*0 + 3*80*FLEN/8, x4, x1, x2)

inst_13137:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x7f7ffff8; valaddr_reg:x3; val_offset:39411*0 + 3*80*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39411*0 + 3*81*FLEN/8, x4, x1, x2)

inst_13138:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x7f7ffffc; valaddr_reg:x3; val_offset:39414*0 + 3*81*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39414*0 + 3*82*FLEN/8, x4, x1, x2)

inst_13139:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0a049f and fs2 == 0 and fe2 == 0x80 and fm2 == 0x6d6b0f and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8a049f; op2val:0x406d6b0f;
op3val:0x7f7ffffe; valaddr_reg:x3; val_offset:39417*0 + 3*82*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39417*0 + 3*83*FLEN/8, x4, x1, x2)

inst_13140:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x59 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x2c800000; valaddr_reg:x3; val_offset:39420*0 + 3*83*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39420*0 + 3*84*FLEN/8, x4, x1, x2)

inst_13141:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x59 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x2c800001; valaddr_reg:x3; val_offset:39423*0 + 3*84*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39423*0 + 3*85*FLEN/8, x4, x1, x2)

inst_13142:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x59 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x2c800003; valaddr_reg:x3; val_offset:39426*0 + 3*85*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39426*0 + 3*86*FLEN/8, x4, x1, x2)

inst_13143:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x59 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x2c800007; valaddr_reg:x3; val_offset:39429*0 + 3*86*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39429*0 + 3*87*FLEN/8, x4, x1, x2)

inst_13144:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x59 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x2c80000f; valaddr_reg:x3; val_offset:39432*0 + 3*87*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39432*0 + 3*88*FLEN/8, x4, x1, x2)

inst_13145:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x59 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x2c80001f; valaddr_reg:x3; val_offset:39435*0 + 3*88*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39435*0 + 3*89*FLEN/8, x4, x1, x2)

inst_13146:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x59 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x2c80003f; valaddr_reg:x3; val_offset:39438*0 + 3*89*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39438*0 + 3*90*FLEN/8, x4, x1, x2)

inst_13147:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x59 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x2c80007f; valaddr_reg:x3; val_offset:39441*0 + 3*90*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39441*0 + 3*91*FLEN/8, x4, x1, x2)

inst_13148:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x59 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x2c8000ff; valaddr_reg:x3; val_offset:39444*0 + 3*91*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39444*0 + 3*92*FLEN/8, x4, x1, x2)

inst_13149:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x59 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x2c8001ff; valaddr_reg:x3; val_offset:39447*0 + 3*92*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39447*0 + 3*93*FLEN/8, x4, x1, x2)

inst_13150:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x59 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x2c8003ff; valaddr_reg:x3; val_offset:39450*0 + 3*93*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39450*0 + 3*94*FLEN/8, x4, x1, x2)

inst_13151:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x59 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x2c8007ff; valaddr_reg:x3; val_offset:39453*0 + 3*94*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39453*0 + 3*95*FLEN/8, x4, x1, x2)

inst_13152:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x59 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x2c800fff; valaddr_reg:x3; val_offset:39456*0 + 3*95*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39456*0 + 3*96*FLEN/8, x4, x1, x2)

inst_13153:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x59 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x2c801fff; valaddr_reg:x3; val_offset:39459*0 + 3*96*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39459*0 + 3*97*FLEN/8, x4, x1, x2)

inst_13154:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x59 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x2c803fff; valaddr_reg:x3; val_offset:39462*0 + 3*97*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39462*0 + 3*98*FLEN/8, x4, x1, x2)

inst_13155:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x59 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x2c807fff; valaddr_reg:x3; val_offset:39465*0 + 3*98*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39465*0 + 3*99*FLEN/8, x4, x1, x2)

inst_13156:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x59 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x2c80ffff; valaddr_reg:x3; val_offset:39468*0 + 3*99*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39468*0 + 3*100*FLEN/8, x4, x1, x2)

inst_13157:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x59 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x2c81ffff; valaddr_reg:x3; val_offset:39471*0 + 3*100*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39471*0 + 3*101*FLEN/8, x4, x1, x2)

inst_13158:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x59 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x2c83ffff; valaddr_reg:x3; val_offset:39474*0 + 3*101*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39474*0 + 3*102*FLEN/8, x4, x1, x2)

inst_13159:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x59 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x2c87ffff; valaddr_reg:x3; val_offset:39477*0 + 3*102*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39477*0 + 3*103*FLEN/8, x4, x1, x2)

inst_13160:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x59 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x2c8fffff; valaddr_reg:x3; val_offset:39480*0 + 3*103*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39480*0 + 3*104*FLEN/8, x4, x1, x2)

inst_13161:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x59 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x2c9fffff; valaddr_reg:x3; val_offset:39483*0 + 3*104*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39483*0 + 3*105*FLEN/8, x4, x1, x2)

inst_13162:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x59 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x2cbfffff; valaddr_reg:x3; val_offset:39486*0 + 3*105*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39486*0 + 3*106*FLEN/8, x4, x1, x2)

inst_13163:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x59 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x2cc00000; valaddr_reg:x3; val_offset:39489*0 + 3*106*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39489*0 + 3*107*FLEN/8, x4, x1, x2)

inst_13164:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x59 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x2ce00000; valaddr_reg:x3; val_offset:39492*0 + 3*107*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39492*0 + 3*108*FLEN/8, x4, x1, x2)

inst_13165:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x59 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x2cf00000; valaddr_reg:x3; val_offset:39495*0 + 3*108*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39495*0 + 3*109*FLEN/8, x4, x1, x2)

inst_13166:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x59 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x2cf80000; valaddr_reg:x3; val_offset:39498*0 + 3*109*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39498*0 + 3*110*FLEN/8, x4, x1, x2)

inst_13167:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x59 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x2cfc0000; valaddr_reg:x3; val_offset:39501*0 + 3*110*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39501*0 + 3*111*FLEN/8, x4, x1, x2)

inst_13168:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x59 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x2cfe0000; valaddr_reg:x3; val_offset:39504*0 + 3*111*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39504*0 + 3*112*FLEN/8, x4, x1, x2)

inst_13169:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x59 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x2cff0000; valaddr_reg:x3; val_offset:39507*0 + 3*112*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39507*0 + 3*113*FLEN/8, x4, x1, x2)

inst_13170:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x59 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x2cff8000; valaddr_reg:x3; val_offset:39510*0 + 3*113*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39510*0 + 3*114*FLEN/8, x4, x1, x2)

inst_13171:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x59 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x2cffc000; valaddr_reg:x3; val_offset:39513*0 + 3*114*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39513*0 + 3*115*FLEN/8, x4, x1, x2)

inst_13172:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x59 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x2cffe000; valaddr_reg:x3; val_offset:39516*0 + 3*115*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39516*0 + 3*116*FLEN/8, x4, x1, x2)

inst_13173:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x59 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x2cfff000; valaddr_reg:x3; val_offset:39519*0 + 3*116*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39519*0 + 3*117*FLEN/8, x4, x1, x2)

inst_13174:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x59 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x2cfff800; valaddr_reg:x3; val_offset:39522*0 + 3*117*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39522*0 + 3*118*FLEN/8, x4, x1, x2)

inst_13175:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x59 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x2cfffc00; valaddr_reg:x3; val_offset:39525*0 + 3*118*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39525*0 + 3*119*FLEN/8, x4, x1, x2)

inst_13176:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x59 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x2cfffe00; valaddr_reg:x3; val_offset:39528*0 + 3*119*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39528*0 + 3*120*FLEN/8, x4, x1, x2)

inst_13177:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x59 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x2cffff00; valaddr_reg:x3; val_offset:39531*0 + 3*120*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39531*0 + 3*121*FLEN/8, x4, x1, x2)

inst_13178:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x59 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x2cffff80; valaddr_reg:x3; val_offset:39534*0 + 3*121*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39534*0 + 3*122*FLEN/8, x4, x1, x2)

inst_13179:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x59 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x2cffffc0; valaddr_reg:x3; val_offset:39537*0 + 3*122*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39537*0 + 3*123*FLEN/8, x4, x1, x2)

inst_13180:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x59 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x2cffffe0; valaddr_reg:x3; val_offset:39540*0 + 3*123*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39540*0 + 3*124*FLEN/8, x4, x1, x2)

inst_13181:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x59 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x2cfffff0; valaddr_reg:x3; val_offset:39543*0 + 3*124*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39543*0 + 3*125*FLEN/8, x4, x1, x2)

inst_13182:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x59 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x2cfffff8; valaddr_reg:x3; val_offset:39546*0 + 3*125*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39546*0 + 3*126*FLEN/8, x4, x1, x2)

inst_13183:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x59 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x2cfffffc; valaddr_reg:x3; val_offset:39549*0 + 3*126*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39549*0 + 3*127*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_2)

inst_13184:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x59 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x2cfffffe; valaddr_reg:x3; val_offset:39552*0 + 3*127*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39552*0 + 3*128*FLEN/8, x4, x1, x2)

inst_13185:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x59 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x2cffffff; valaddr_reg:x3; val_offset:39555*0 + 3*128*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39555*0 + 3*129*FLEN/8, x4, x1, x2)

inst_13186:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x3f800001; valaddr_reg:x3; val_offset:39558*0 + 3*129*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39558*0 + 3*130*FLEN/8, x4, x1, x2)

inst_13187:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x3f800003; valaddr_reg:x3; val_offset:39561*0 + 3*130*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39561*0 + 3*131*FLEN/8, x4, x1, x2)

inst_13188:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x3f800007; valaddr_reg:x3; val_offset:39564*0 + 3*131*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39564*0 + 3*132*FLEN/8, x4, x1, x2)

inst_13189:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x3f999999; valaddr_reg:x3; val_offset:39567*0 + 3*132*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39567*0 + 3*133*FLEN/8, x4, x1, x2)

inst_13190:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x3fa49249; valaddr_reg:x3; val_offset:39570*0 + 3*133*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39570*0 + 3*134*FLEN/8, x4, x1, x2)

inst_13191:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x3fb33333; valaddr_reg:x3; val_offset:39573*0 + 3*134*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39573*0 + 3*135*FLEN/8, x4, x1, x2)

inst_13192:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x3fb6db6d; valaddr_reg:x3; val_offset:39576*0 + 3*135*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39576*0 + 3*136*FLEN/8, x4, x1, x2)

inst_13193:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x3fbbbbbb; valaddr_reg:x3; val_offset:39579*0 + 3*136*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39579*0 + 3*137*FLEN/8, x4, x1, x2)

inst_13194:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x3fc44444; valaddr_reg:x3; val_offset:39582*0 + 3*137*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39582*0 + 3*138*FLEN/8, x4, x1, x2)

inst_13195:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x3fcccccc; valaddr_reg:x3; val_offset:39585*0 + 3*138*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39585*0 + 3*139*FLEN/8, x4, x1, x2)

inst_13196:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x3fdb6db6; valaddr_reg:x3; val_offset:39588*0 + 3*139*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39588*0 + 3*140*FLEN/8, x4, x1, x2)

inst_13197:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x3fe66666; valaddr_reg:x3; val_offset:39591*0 + 3*140*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39591*0 + 3*141*FLEN/8, x4, x1, x2)

inst_13198:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x3fedb6db; valaddr_reg:x3; val_offset:39594*0 + 3*141*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39594*0 + 3*142*FLEN/8, x4, x1, x2)

inst_13199:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x3ffffff8; valaddr_reg:x3; val_offset:39597*0 + 3*142*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39597*0 + 3*143*FLEN/8, x4, x1, x2)

inst_13200:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x3ffffffc; valaddr_reg:x3; val_offset:39600*0 + 3*143*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39600*0 + 3*144*FLEN/8, x4, x1, x2)

inst_13201:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c0f02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x74fac5 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c0f02; op2val:0x74fac5;
op3val:0x3ffffffe; valaddr_reg:x3; val_offset:39603*0 + 3*144*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39603*0 + 3*145*FLEN/8, x4, x1, x2)

inst_13202:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xbf800001; valaddr_reg:x3; val_offset:39606*0 + 3*145*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39606*0 + 3*146*FLEN/8, x4, x1, x2)

inst_13203:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xbf800003; valaddr_reg:x3; val_offset:39609*0 + 3*146*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39609*0 + 3*147*FLEN/8, x4, x1, x2)

inst_13204:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xbf800007; valaddr_reg:x3; val_offset:39612*0 + 3*147*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39612*0 + 3*148*FLEN/8, x4, x1, x2)

inst_13205:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x7f and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xbf999999; valaddr_reg:x3; val_offset:39615*0 + 3*148*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39615*0 + 3*149*FLEN/8, x4, x1, x2)

inst_13206:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x7f and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xbfa49249; valaddr_reg:x3; val_offset:39618*0 + 3*149*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39618*0 + 3*150*FLEN/8, x4, x1, x2)

inst_13207:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x7f and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xbfb33333; valaddr_reg:x3; val_offset:39621*0 + 3*150*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39621*0 + 3*151*FLEN/8, x4, x1, x2)

inst_13208:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x7f and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xbfb6db6d; valaddr_reg:x3; val_offset:39624*0 + 3*151*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39624*0 + 3*152*FLEN/8, x4, x1, x2)

inst_13209:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x7f and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xbfbbbbbb; valaddr_reg:x3; val_offset:39627*0 + 3*152*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39627*0 + 3*153*FLEN/8, x4, x1, x2)

inst_13210:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x7f and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xbfc44444; valaddr_reg:x3; val_offset:39630*0 + 3*153*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39630*0 + 3*154*FLEN/8, x4, x1, x2)

inst_13211:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x7f and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xbfcccccc; valaddr_reg:x3; val_offset:39633*0 + 3*154*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39633*0 + 3*155*FLEN/8, x4, x1, x2)

inst_13212:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x7f and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xbfdb6db6; valaddr_reg:x3; val_offset:39636*0 + 3*155*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39636*0 + 3*156*FLEN/8, x4, x1, x2)

inst_13213:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x7f and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xbfe66666; valaddr_reg:x3; val_offset:39639*0 + 3*156*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39639*0 + 3*157*FLEN/8, x4, x1, x2)

inst_13214:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x7f and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xbfedb6db; valaddr_reg:x3; val_offset:39642*0 + 3*157*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39642*0 + 3*158*FLEN/8, x4, x1, x2)

inst_13215:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xbffffff8; valaddr_reg:x3; val_offset:39645*0 + 3*158*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39645*0 + 3*159*FLEN/8, x4, x1, x2)

inst_13216:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xbffffffc; valaddr_reg:x3; val_offset:39648*0 + 3*159*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39648*0 + 3*160*FLEN/8, x4, x1, x2)

inst_13217:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xbffffffe; valaddr_reg:x3; val_offset:39651*0 + 3*160*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39651*0 + 3*161*FLEN/8, x4, x1, x2)

inst_13218:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x88 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xc4000000; valaddr_reg:x3; val_offset:39654*0 + 3*161*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39654*0 + 3*162*FLEN/8, x4, x1, x2)

inst_13219:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x88 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xc4000001; valaddr_reg:x3; val_offset:39657*0 + 3*162*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39657*0 + 3*163*FLEN/8, x4, x1, x2)

inst_13220:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x88 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xc4000003; valaddr_reg:x3; val_offset:39660*0 + 3*163*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39660*0 + 3*164*FLEN/8, x4, x1, x2)

inst_13221:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x88 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xc4000007; valaddr_reg:x3; val_offset:39663*0 + 3*164*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39663*0 + 3*165*FLEN/8, x4, x1, x2)

inst_13222:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x88 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xc400000f; valaddr_reg:x3; val_offset:39666*0 + 3*165*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39666*0 + 3*166*FLEN/8, x4, x1, x2)

inst_13223:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x88 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xc400001f; valaddr_reg:x3; val_offset:39669*0 + 3*166*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39669*0 + 3*167*FLEN/8, x4, x1, x2)

inst_13224:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x88 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xc400003f; valaddr_reg:x3; val_offset:39672*0 + 3*167*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39672*0 + 3*168*FLEN/8, x4, x1, x2)

inst_13225:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x88 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xc400007f; valaddr_reg:x3; val_offset:39675*0 + 3*168*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39675*0 + 3*169*FLEN/8, x4, x1, x2)

inst_13226:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x88 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xc40000ff; valaddr_reg:x3; val_offset:39678*0 + 3*169*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39678*0 + 3*170*FLEN/8, x4, x1, x2)

inst_13227:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x88 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xc40001ff; valaddr_reg:x3; val_offset:39681*0 + 3*170*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39681*0 + 3*171*FLEN/8, x4, x1, x2)

inst_13228:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x88 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xc40003ff; valaddr_reg:x3; val_offset:39684*0 + 3*171*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39684*0 + 3*172*FLEN/8, x4, x1, x2)

inst_13229:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x88 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xc40007ff; valaddr_reg:x3; val_offset:39687*0 + 3*172*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39687*0 + 3*173*FLEN/8, x4, x1, x2)

inst_13230:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x88 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xc4000fff; valaddr_reg:x3; val_offset:39690*0 + 3*173*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39690*0 + 3*174*FLEN/8, x4, x1, x2)

inst_13231:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x88 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xc4001fff; valaddr_reg:x3; val_offset:39693*0 + 3*174*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39693*0 + 3*175*FLEN/8, x4, x1, x2)

inst_13232:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x88 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xc4003fff; valaddr_reg:x3; val_offset:39696*0 + 3*175*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39696*0 + 3*176*FLEN/8, x4, x1, x2)

inst_13233:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x88 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xc4007fff; valaddr_reg:x3; val_offset:39699*0 + 3*176*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39699*0 + 3*177*FLEN/8, x4, x1, x2)

inst_13234:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x88 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xc400ffff; valaddr_reg:x3; val_offset:39702*0 + 3*177*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39702*0 + 3*178*FLEN/8, x4, x1, x2)

inst_13235:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x88 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xc401ffff; valaddr_reg:x3; val_offset:39705*0 + 3*178*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39705*0 + 3*179*FLEN/8, x4, x1, x2)

inst_13236:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x88 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xc403ffff; valaddr_reg:x3; val_offset:39708*0 + 3*179*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39708*0 + 3*180*FLEN/8, x4, x1, x2)

inst_13237:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x88 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xc407ffff; valaddr_reg:x3; val_offset:39711*0 + 3*180*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39711*0 + 3*181*FLEN/8, x4, x1, x2)

inst_13238:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x88 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xc40fffff; valaddr_reg:x3; val_offset:39714*0 + 3*181*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39714*0 + 3*182*FLEN/8, x4, x1, x2)

inst_13239:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x88 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xc41fffff; valaddr_reg:x3; val_offset:39717*0 + 3*182*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39717*0 + 3*183*FLEN/8, x4, x1, x2)

inst_13240:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x88 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xc43fffff; valaddr_reg:x3; val_offset:39720*0 + 3*183*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39720*0 + 3*184*FLEN/8, x4, x1, x2)

inst_13241:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x88 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xc4400000; valaddr_reg:x3; val_offset:39723*0 + 3*184*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39723*0 + 3*185*FLEN/8, x4, x1, x2)

inst_13242:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x88 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xc4600000; valaddr_reg:x3; val_offset:39726*0 + 3*185*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39726*0 + 3*186*FLEN/8, x4, x1, x2)

inst_13243:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x88 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xc4700000; valaddr_reg:x3; val_offset:39729*0 + 3*186*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39729*0 + 3*187*FLEN/8, x4, x1, x2)

inst_13244:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x88 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xc4780000; valaddr_reg:x3; val_offset:39732*0 + 3*187*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39732*0 + 3*188*FLEN/8, x4, x1, x2)

inst_13245:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x88 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xc47c0000; valaddr_reg:x3; val_offset:39735*0 + 3*188*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39735*0 + 3*189*FLEN/8, x4, x1, x2)

inst_13246:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x88 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xc47e0000; valaddr_reg:x3; val_offset:39738*0 + 3*189*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39738*0 + 3*190*FLEN/8, x4, x1, x2)

inst_13247:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x88 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xc47f0000; valaddr_reg:x3; val_offset:39741*0 + 3*190*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39741*0 + 3*191*FLEN/8, x4, x1, x2)

inst_13248:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x88 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xc47f8000; valaddr_reg:x3; val_offset:39744*0 + 3*191*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39744*0 + 3*192*FLEN/8, x4, x1, x2)

inst_13249:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x88 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xc47fc000; valaddr_reg:x3; val_offset:39747*0 + 3*192*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39747*0 + 3*193*FLEN/8, x4, x1, x2)

inst_13250:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x88 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xc47fe000; valaddr_reg:x3; val_offset:39750*0 + 3*193*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39750*0 + 3*194*FLEN/8, x4, x1, x2)

inst_13251:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x88 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xc47ff000; valaddr_reg:x3; val_offset:39753*0 + 3*194*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39753*0 + 3*195*FLEN/8, x4, x1, x2)

inst_13252:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x88 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xc47ff800; valaddr_reg:x3; val_offset:39756*0 + 3*195*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39756*0 + 3*196*FLEN/8, x4, x1, x2)

inst_13253:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x88 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xc47ffc00; valaddr_reg:x3; val_offset:39759*0 + 3*196*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39759*0 + 3*197*FLEN/8, x4, x1, x2)

inst_13254:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x88 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xc47ffe00; valaddr_reg:x3; val_offset:39762*0 + 3*197*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39762*0 + 3*198*FLEN/8, x4, x1, x2)

inst_13255:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x88 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xc47fff00; valaddr_reg:x3; val_offset:39765*0 + 3*198*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39765*0 + 3*199*FLEN/8, x4, x1, x2)

inst_13256:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x88 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xc47fff80; valaddr_reg:x3; val_offset:39768*0 + 3*199*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39768*0 + 3*200*FLEN/8, x4, x1, x2)

inst_13257:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x88 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xc47fffc0; valaddr_reg:x3; val_offset:39771*0 + 3*200*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39771*0 + 3*201*FLEN/8, x4, x1, x2)

inst_13258:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x88 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xc47fffe0; valaddr_reg:x3; val_offset:39774*0 + 3*201*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39774*0 + 3*202*FLEN/8, x4, x1, x2)

inst_13259:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x88 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xc47ffff0; valaddr_reg:x3; val_offset:39777*0 + 3*202*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39777*0 + 3*203*FLEN/8, x4, x1, x2)

inst_13260:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x88 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xc47ffff8; valaddr_reg:x3; val_offset:39780*0 + 3*203*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39780*0 + 3*204*FLEN/8, x4, x1, x2)

inst_13261:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x88 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xc47ffffc; valaddr_reg:x3; val_offset:39783*0 + 3*204*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39783*0 + 3*205*FLEN/8, x4, x1, x2)

inst_13262:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x88 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xc47ffffe; valaddr_reg:x3; val_offset:39786*0 + 3*205*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39786*0 + 3*206*FLEN/8, x4, x1, x2)

inst_13263:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0c1e52 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x74edfd and fs3 == 1 and fe3 == 0x88 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8c1e52; op2val:0x8074edfd;
op3val:0xc47fffff; valaddr_reg:x3; val_offset:39789*0 + 3*206*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39789*0 + 3*207*FLEN/8, x4, x1, x2)

inst_13264:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x3; val_offset:39792*0 + 3*207*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39792*0 + 3*208*FLEN/8, x4, x1, x2)

inst_13265:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x80000003; valaddr_reg:x3; val_offset:39795*0 + 3*208*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39795*0 + 3*209*FLEN/8, x4, x1, x2)

inst_13266:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x80000007; valaddr_reg:x3; val_offset:39798*0 + 3*209*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39798*0 + 3*210*FLEN/8, x4, x1, x2)

inst_13267:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x80199999; valaddr_reg:x3; val_offset:39801*0 + 3*210*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39801*0 + 3*211*FLEN/8, x4, x1, x2)

inst_13268:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x80249249; valaddr_reg:x3; val_offset:39804*0 + 3*211*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39804*0 + 3*212*FLEN/8, x4, x1, x2)

inst_13269:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x80333333; valaddr_reg:x3; val_offset:39807*0 + 3*212*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39807*0 + 3*213*FLEN/8, x4, x1, x2)

inst_13270:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x8036db6d; valaddr_reg:x3; val_offset:39810*0 + 3*213*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39810*0 + 3*214*FLEN/8, x4, x1, x2)

inst_13271:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x803bbbbb; valaddr_reg:x3; val_offset:39813*0 + 3*214*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39813*0 + 3*215*FLEN/8, x4, x1, x2)

inst_13272:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x80444444; valaddr_reg:x3; val_offset:39816*0 + 3*215*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39816*0 + 3*216*FLEN/8, x4, x1, x2)

inst_13273:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x804ccccc; valaddr_reg:x3; val_offset:39819*0 + 3*216*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39819*0 + 3*217*FLEN/8, x4, x1, x2)

inst_13274:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x805b6db6; valaddr_reg:x3; val_offset:39822*0 + 3*217*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39822*0 + 3*218*FLEN/8, x4, x1, x2)

inst_13275:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x80666666; valaddr_reg:x3; val_offset:39825*0 + 3*218*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39825*0 + 3*219*FLEN/8, x4, x1, x2)

inst_13276:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x806db6db; valaddr_reg:x3; val_offset:39828*0 + 3*219*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39828*0 + 3*220*FLEN/8, x4, x1, x2)

inst_13277:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x807ffff8; valaddr_reg:x3; val_offset:39831*0 + 3*220*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39831*0 + 3*221*FLEN/8, x4, x1, x2)

inst_13278:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x807ffffc; valaddr_reg:x3; val_offset:39834*0 + 3*221*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39834*0 + 3*222*FLEN/8, x4, x1, x2)

inst_13279:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x3; val_offset:39837*0 + 3*222*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39837*0 + 3*223*FLEN/8, x4, x1, x2)

inst_13280:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x8b000000; valaddr_reg:x3; val_offset:39840*0 + 3*223*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39840*0 + 3*224*FLEN/8, x4, x1, x2)

inst_13281:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x8b000001; valaddr_reg:x3; val_offset:39843*0 + 3*224*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39843*0 + 3*225*FLEN/8, x4, x1, x2)

inst_13282:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x8b000003; valaddr_reg:x3; val_offset:39846*0 + 3*225*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39846*0 + 3*226*FLEN/8, x4, x1, x2)

inst_13283:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x8b000007; valaddr_reg:x3; val_offset:39849*0 + 3*226*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39849*0 + 3*227*FLEN/8, x4, x1, x2)

inst_13284:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x8b00000f; valaddr_reg:x3; val_offset:39852*0 + 3*227*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39852*0 + 3*228*FLEN/8, x4, x1, x2)

inst_13285:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x8b00001f; valaddr_reg:x3; val_offset:39855*0 + 3*228*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39855*0 + 3*229*FLEN/8, x4, x1, x2)

inst_13286:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x8b00003f; valaddr_reg:x3; val_offset:39858*0 + 3*229*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39858*0 + 3*230*FLEN/8, x4, x1, x2)

inst_13287:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x8b00007f; valaddr_reg:x3; val_offset:39861*0 + 3*230*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39861*0 + 3*231*FLEN/8, x4, x1, x2)

inst_13288:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x8b0000ff; valaddr_reg:x3; val_offset:39864*0 + 3*231*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39864*0 + 3*232*FLEN/8, x4, x1, x2)

inst_13289:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x8b0001ff; valaddr_reg:x3; val_offset:39867*0 + 3*232*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39867*0 + 3*233*FLEN/8, x4, x1, x2)

inst_13290:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x8b0003ff; valaddr_reg:x3; val_offset:39870*0 + 3*233*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39870*0 + 3*234*FLEN/8, x4, x1, x2)

inst_13291:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x8b0007ff; valaddr_reg:x3; val_offset:39873*0 + 3*234*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39873*0 + 3*235*FLEN/8, x4, x1, x2)

inst_13292:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x8b000fff; valaddr_reg:x3; val_offset:39876*0 + 3*235*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39876*0 + 3*236*FLEN/8, x4, x1, x2)

inst_13293:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x8b001fff; valaddr_reg:x3; val_offset:39879*0 + 3*236*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39879*0 + 3*237*FLEN/8, x4, x1, x2)

inst_13294:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x8b003fff; valaddr_reg:x3; val_offset:39882*0 + 3*237*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39882*0 + 3*238*FLEN/8, x4, x1, x2)

inst_13295:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x8b007fff; valaddr_reg:x3; val_offset:39885*0 + 3*238*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39885*0 + 3*239*FLEN/8, x4, x1, x2)

inst_13296:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x8b00ffff; valaddr_reg:x3; val_offset:39888*0 + 3*239*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39888*0 + 3*240*FLEN/8, x4, x1, x2)

inst_13297:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x8b01ffff; valaddr_reg:x3; val_offset:39891*0 + 3*240*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39891*0 + 3*241*FLEN/8, x4, x1, x2)

inst_13298:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x8b03ffff; valaddr_reg:x3; val_offset:39894*0 + 3*241*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39894*0 + 3*242*FLEN/8, x4, x1, x2)

inst_13299:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x8b07ffff; valaddr_reg:x3; val_offset:39897*0 + 3*242*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39897*0 + 3*243*FLEN/8, x4, x1, x2)

inst_13300:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x8b0fffff; valaddr_reg:x3; val_offset:39900*0 + 3*243*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39900*0 + 3*244*FLEN/8, x4, x1, x2)

inst_13301:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x8b1fffff; valaddr_reg:x3; val_offset:39903*0 + 3*244*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39903*0 + 3*245*FLEN/8, x4, x1, x2)

inst_13302:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x8b3fffff; valaddr_reg:x3; val_offset:39906*0 + 3*245*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39906*0 + 3*246*FLEN/8, x4, x1, x2)

inst_13303:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x8b400000; valaddr_reg:x3; val_offset:39909*0 + 3*246*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39909*0 + 3*247*FLEN/8, x4, x1, x2)

inst_13304:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x8b600000; valaddr_reg:x3; val_offset:39912*0 + 3*247*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39912*0 + 3*248*FLEN/8, x4, x1, x2)

inst_13305:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x8b700000; valaddr_reg:x3; val_offset:39915*0 + 3*248*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39915*0 + 3*249*FLEN/8, x4, x1, x2)

inst_13306:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x8b780000; valaddr_reg:x3; val_offset:39918*0 + 3*249*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39918*0 + 3*250*FLEN/8, x4, x1, x2)

inst_13307:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x8b7c0000; valaddr_reg:x3; val_offset:39921*0 + 3*250*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39921*0 + 3*251*FLEN/8, x4, x1, x2)

inst_13308:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x8b7e0000; valaddr_reg:x3; val_offset:39924*0 + 3*251*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39924*0 + 3*252*FLEN/8, x4, x1, x2)

inst_13309:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x8b7f0000; valaddr_reg:x3; val_offset:39927*0 + 3*252*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39927*0 + 3*253*FLEN/8, x4, x1, x2)

inst_13310:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x8b7f8000; valaddr_reg:x3; val_offset:39930*0 + 3*253*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39930*0 + 3*254*FLEN/8, x4, x1, x2)

inst_13311:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x8b7fc000; valaddr_reg:x3; val_offset:39933*0 + 3*254*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39933*0 + 3*255*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_3)

inst_13312:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x8b7fe000; valaddr_reg:x3; val_offset:39936*0 + 3*256*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39936*0 + 3*256*FLEN/8, x4, x1, x2)

inst_13313:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x8b7ff000; valaddr_reg:x3; val_offset:39939*0 + 3*257*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39939*0 + 3*257*FLEN/8, x4, x1, x2)

inst_13314:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x8b7ff800; valaddr_reg:x3; val_offset:39942*0 + 3*258*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39942*0 + 3*258*FLEN/8, x4, x1, x2)

inst_13315:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x8b7ffc00; valaddr_reg:x3; val_offset:39945*0 + 3*259*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39945*0 + 3*259*FLEN/8, x4, x1, x2)

inst_13316:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x8b7ffe00; valaddr_reg:x3; val_offset:39948*0 + 3*260*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39948*0 + 3*260*FLEN/8, x4, x1, x2)

inst_13317:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x8b7fff00; valaddr_reg:x3; val_offset:39951*0 + 3*261*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39951*0 + 3*261*FLEN/8, x4, x1, x2)

inst_13318:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x8b7fff80; valaddr_reg:x3; val_offset:39954*0 + 3*262*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39954*0 + 3*262*FLEN/8, x4, x1, x2)

inst_13319:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x8b7fffc0; valaddr_reg:x3; val_offset:39957*0 + 3*263*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39957*0 + 3*263*FLEN/8, x4, x1, x2)

inst_13320:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x8b7fffe0; valaddr_reg:x3; val_offset:39960*0 + 3*264*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39960*0 + 3*264*FLEN/8, x4, x1, x2)

inst_13321:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x8b7ffff0; valaddr_reg:x3; val_offset:39963*0 + 3*265*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39963*0 + 3*265*FLEN/8, x4, x1, x2)

inst_13322:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x8b7ffff8; valaddr_reg:x3; val_offset:39966*0 + 3*266*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39966*0 + 3*266*FLEN/8, x4, x1, x2)

inst_13323:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x8b7ffffc; valaddr_reg:x3; val_offset:39969*0 + 3*267*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39969*0 + 3*267*FLEN/8, x4, x1, x2)

inst_13324:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x8b7ffffe; valaddr_reg:x3; val_offset:39972*0 + 3*268*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39972*0 + 3*268*FLEN/8, x4, x1, x2)

inst_13325:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0cf9bd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8cf9bd; op2val:0x80000000;
op3val:0x8b7fffff; valaddr_reg:x3; val_offset:39975*0 + 3*269*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39975*0 + 3*269*FLEN/8, x4, x1, x2)

inst_13326:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x3; val_offset:39978*0 + 3*270*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39978*0 + 3*270*FLEN/8, x4, x1, x2)

inst_13327:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x80000003; valaddr_reg:x3; val_offset:39981*0 + 3*271*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39981*0 + 3*271*FLEN/8, x4, x1, x2)

inst_13328:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x80000007; valaddr_reg:x3; val_offset:39984*0 + 3*272*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39984*0 + 3*272*FLEN/8, x4, x1, x2)

inst_13329:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x80199999; valaddr_reg:x3; val_offset:39987*0 + 3*273*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39987*0 + 3*273*FLEN/8, x4, x1, x2)

inst_13330:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x80249249; valaddr_reg:x3; val_offset:39990*0 + 3*274*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39990*0 + 3*274*FLEN/8, x4, x1, x2)

inst_13331:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x80333333; valaddr_reg:x3; val_offset:39993*0 + 3*275*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39993*0 + 3*275*FLEN/8, x4, x1, x2)

inst_13332:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x8036db6d; valaddr_reg:x3; val_offset:39996*0 + 3*276*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39996*0 + 3*276*FLEN/8, x4, x1, x2)

inst_13333:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x803bbbbb; valaddr_reg:x3; val_offset:39999*0 + 3*277*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 39999*0 + 3*277*FLEN/8, x4, x1, x2)

inst_13334:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x80444444; valaddr_reg:x3; val_offset:40002*0 + 3*278*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40002*0 + 3*278*FLEN/8, x4, x1, x2)

inst_13335:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x804ccccc; valaddr_reg:x3; val_offset:40005*0 + 3*279*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40005*0 + 3*279*FLEN/8, x4, x1, x2)

inst_13336:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x805b6db6; valaddr_reg:x3; val_offset:40008*0 + 3*280*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40008*0 + 3*280*FLEN/8, x4, x1, x2)

inst_13337:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x80666666; valaddr_reg:x3; val_offset:40011*0 + 3*281*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40011*0 + 3*281*FLEN/8, x4, x1, x2)

inst_13338:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x806db6db; valaddr_reg:x3; val_offset:40014*0 + 3*282*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40014*0 + 3*282*FLEN/8, x4, x1, x2)

inst_13339:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x807ffff8; valaddr_reg:x3; val_offset:40017*0 + 3*283*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40017*0 + 3*283*FLEN/8, x4, x1, x2)

inst_13340:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x807ffffc; valaddr_reg:x3; val_offset:40020*0 + 3*284*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40020*0 + 3*284*FLEN/8, x4, x1, x2)

inst_13341:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x3; val_offset:40023*0 + 3*285*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40023*0 + 3*285*FLEN/8, x4, x1, x2)

inst_13342:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x8c800000; valaddr_reg:x3; val_offset:40026*0 + 3*286*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40026*0 + 3*286*FLEN/8, x4, x1, x2)

inst_13343:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x8c800001; valaddr_reg:x3; val_offset:40029*0 + 3*287*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40029*0 + 3*287*FLEN/8, x4, x1, x2)

inst_13344:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x8c800003; valaddr_reg:x3; val_offset:40032*0 + 3*288*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40032*0 + 3*288*FLEN/8, x4, x1, x2)

inst_13345:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x8c800007; valaddr_reg:x3; val_offset:40035*0 + 3*289*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40035*0 + 3*289*FLEN/8, x4, x1, x2)

inst_13346:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x8c80000f; valaddr_reg:x3; val_offset:40038*0 + 3*290*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40038*0 + 3*290*FLEN/8, x4, x1, x2)

inst_13347:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x8c80001f; valaddr_reg:x3; val_offset:40041*0 + 3*291*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40041*0 + 3*291*FLEN/8, x4, x1, x2)

inst_13348:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x8c80003f; valaddr_reg:x3; val_offset:40044*0 + 3*292*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40044*0 + 3*292*FLEN/8, x4, x1, x2)

inst_13349:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x8c80007f; valaddr_reg:x3; val_offset:40047*0 + 3*293*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40047*0 + 3*293*FLEN/8, x4, x1, x2)

inst_13350:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x8c8000ff; valaddr_reg:x3; val_offset:40050*0 + 3*294*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40050*0 + 3*294*FLEN/8, x4, x1, x2)

inst_13351:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x8c8001ff; valaddr_reg:x3; val_offset:40053*0 + 3*295*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40053*0 + 3*295*FLEN/8, x4, x1, x2)

inst_13352:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x8c8003ff; valaddr_reg:x3; val_offset:40056*0 + 3*296*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40056*0 + 3*296*FLEN/8, x4, x1, x2)

inst_13353:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x8c8007ff; valaddr_reg:x3; val_offset:40059*0 + 3*297*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40059*0 + 3*297*FLEN/8, x4, x1, x2)

inst_13354:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x8c800fff; valaddr_reg:x3; val_offset:40062*0 + 3*298*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40062*0 + 3*298*FLEN/8, x4, x1, x2)

inst_13355:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x8c801fff; valaddr_reg:x3; val_offset:40065*0 + 3*299*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40065*0 + 3*299*FLEN/8, x4, x1, x2)

inst_13356:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x8c803fff; valaddr_reg:x3; val_offset:40068*0 + 3*300*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40068*0 + 3*300*FLEN/8, x4, x1, x2)

inst_13357:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x8c807fff; valaddr_reg:x3; val_offset:40071*0 + 3*301*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40071*0 + 3*301*FLEN/8, x4, x1, x2)

inst_13358:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x8c80ffff; valaddr_reg:x3; val_offset:40074*0 + 3*302*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40074*0 + 3*302*FLEN/8, x4, x1, x2)

inst_13359:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x8c81ffff; valaddr_reg:x3; val_offset:40077*0 + 3*303*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40077*0 + 3*303*FLEN/8, x4, x1, x2)

inst_13360:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x8c83ffff; valaddr_reg:x3; val_offset:40080*0 + 3*304*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40080*0 + 3*304*FLEN/8, x4, x1, x2)

inst_13361:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x8c87ffff; valaddr_reg:x3; val_offset:40083*0 + 3*305*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40083*0 + 3*305*FLEN/8, x4, x1, x2)

inst_13362:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x8c8fffff; valaddr_reg:x3; val_offset:40086*0 + 3*306*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40086*0 + 3*306*FLEN/8, x4, x1, x2)

inst_13363:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x8c9fffff; valaddr_reg:x3; val_offset:40089*0 + 3*307*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40089*0 + 3*307*FLEN/8, x4, x1, x2)

inst_13364:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x8cbfffff; valaddr_reg:x3; val_offset:40092*0 + 3*308*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40092*0 + 3*308*FLEN/8, x4, x1, x2)

inst_13365:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x8cc00000; valaddr_reg:x3; val_offset:40095*0 + 3*309*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40095*0 + 3*309*FLEN/8, x4, x1, x2)

inst_13366:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x8ce00000; valaddr_reg:x3; val_offset:40098*0 + 3*310*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40098*0 + 3*310*FLEN/8, x4, x1, x2)

inst_13367:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x8cf00000; valaddr_reg:x3; val_offset:40101*0 + 3*311*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40101*0 + 3*311*FLEN/8, x4, x1, x2)

inst_13368:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x8cf80000; valaddr_reg:x3; val_offset:40104*0 + 3*312*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40104*0 + 3*312*FLEN/8, x4, x1, x2)

inst_13369:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x8cfc0000; valaddr_reg:x3; val_offset:40107*0 + 3*313*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40107*0 + 3*313*FLEN/8, x4, x1, x2)

inst_13370:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x8cfe0000; valaddr_reg:x3; val_offset:40110*0 + 3*314*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40110*0 + 3*314*FLEN/8, x4, x1, x2)

inst_13371:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x8cff0000; valaddr_reg:x3; val_offset:40113*0 + 3*315*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40113*0 + 3*315*FLEN/8, x4, x1, x2)

inst_13372:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x8cff8000; valaddr_reg:x3; val_offset:40116*0 + 3*316*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40116*0 + 3*316*FLEN/8, x4, x1, x2)

inst_13373:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x8cffc000; valaddr_reg:x3; val_offset:40119*0 + 3*317*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40119*0 + 3*317*FLEN/8, x4, x1, x2)

inst_13374:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x8cffe000; valaddr_reg:x3; val_offset:40122*0 + 3*318*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40122*0 + 3*318*FLEN/8, x4, x1, x2)

inst_13375:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x8cfff000; valaddr_reg:x3; val_offset:40125*0 + 3*319*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40125*0 + 3*319*FLEN/8, x4, x1, x2)

inst_13376:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x8cfff800; valaddr_reg:x3; val_offset:40128*0 + 3*320*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40128*0 + 3*320*FLEN/8, x4, x1, x2)

inst_13377:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x8cfffc00; valaddr_reg:x3; val_offset:40131*0 + 3*321*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40131*0 + 3*321*FLEN/8, x4, x1, x2)

inst_13378:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x8cfffe00; valaddr_reg:x3; val_offset:40134*0 + 3*322*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40134*0 + 3*322*FLEN/8, x4, x1, x2)

inst_13379:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x8cffff00; valaddr_reg:x3; val_offset:40137*0 + 3*323*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40137*0 + 3*323*FLEN/8, x4, x1, x2)

inst_13380:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x8cffff80; valaddr_reg:x3; val_offset:40140*0 + 3*324*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40140*0 + 3*324*FLEN/8, x4, x1, x2)

inst_13381:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x8cffffc0; valaddr_reg:x3; val_offset:40143*0 + 3*325*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40143*0 + 3*325*FLEN/8, x4, x1, x2)

inst_13382:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x8cffffe0; valaddr_reg:x3; val_offset:40146*0 + 3*326*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40146*0 + 3*326*FLEN/8, x4, x1, x2)

inst_13383:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x8cfffff0; valaddr_reg:x3; val_offset:40149*0 + 3*327*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40149*0 + 3*327*FLEN/8, x4, x1, x2)

inst_13384:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x8cfffff8; valaddr_reg:x3; val_offset:40152*0 + 3*328*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40152*0 + 3*328*FLEN/8, x4, x1, x2)

inst_13385:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x8cfffffc; valaddr_reg:x3; val_offset:40155*0 + 3*329*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40155*0 + 3*329*FLEN/8, x4, x1, x2)

inst_13386:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x8cfffffe; valaddr_reg:x3; val_offset:40158*0 + 3*330*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40158*0 + 3*330*FLEN/8, x4, x1, x2)

inst_13387:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0d93b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8d93b6; op2val:0x80000000;
op3val:0x8cffffff; valaddr_reg:x3; val_offset:40161*0 + 3*331*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40161*0 + 3*331*FLEN/8, x4, x1, x2)

inst_13388:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x3; val_offset:40164*0 + 3*332*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40164*0 + 3*332*FLEN/8, x4, x1, x2)

inst_13389:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x80000003; valaddr_reg:x3; val_offset:40167*0 + 3*333*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40167*0 + 3*333*FLEN/8, x4, x1, x2)

inst_13390:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x80000007; valaddr_reg:x3; val_offset:40170*0 + 3*334*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40170*0 + 3*334*FLEN/8, x4, x1, x2)

inst_13391:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x80199999; valaddr_reg:x3; val_offset:40173*0 + 3*335*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40173*0 + 3*335*FLEN/8, x4, x1, x2)

inst_13392:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x80249249; valaddr_reg:x3; val_offset:40176*0 + 3*336*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40176*0 + 3*336*FLEN/8, x4, x1, x2)

inst_13393:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x80333333; valaddr_reg:x3; val_offset:40179*0 + 3*337*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40179*0 + 3*337*FLEN/8, x4, x1, x2)

inst_13394:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8036db6d; valaddr_reg:x3; val_offset:40182*0 + 3*338*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40182*0 + 3*338*FLEN/8, x4, x1, x2)

inst_13395:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x803bbbbb; valaddr_reg:x3; val_offset:40185*0 + 3*339*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40185*0 + 3*339*FLEN/8, x4, x1, x2)

inst_13396:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x80444444; valaddr_reg:x3; val_offset:40188*0 + 3*340*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40188*0 + 3*340*FLEN/8, x4, x1, x2)

inst_13397:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x804ccccc; valaddr_reg:x3; val_offset:40191*0 + 3*341*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40191*0 + 3*341*FLEN/8, x4, x1, x2)

inst_13398:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x805b6db6; valaddr_reg:x3; val_offset:40194*0 + 3*342*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40194*0 + 3*342*FLEN/8, x4, x1, x2)

inst_13399:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x80666666; valaddr_reg:x3; val_offset:40197*0 + 3*343*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40197*0 + 3*343*FLEN/8, x4, x1, x2)

inst_13400:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x806db6db; valaddr_reg:x3; val_offset:40200*0 + 3*344*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40200*0 + 3*344*FLEN/8, x4, x1, x2)

inst_13401:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x807ffff8; valaddr_reg:x3; val_offset:40203*0 + 3*345*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40203*0 + 3*345*FLEN/8, x4, x1, x2)

inst_13402:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x807ffffc; valaddr_reg:x3; val_offset:40206*0 + 3*346*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40206*0 + 3*346*FLEN/8, x4, x1, x2)

inst_13403:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x3; val_offset:40209*0 + 3*347*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40209*0 + 3*347*FLEN/8, x4, x1, x2)

inst_13404:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8f800000; valaddr_reg:x3; val_offset:40212*0 + 3*348*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40212*0 + 3*348*FLEN/8, x4, x1, x2)

inst_13405:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8f800001; valaddr_reg:x3; val_offset:40215*0 + 3*349*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40215*0 + 3*349*FLEN/8, x4, x1, x2)

inst_13406:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8f800003; valaddr_reg:x3; val_offset:40218*0 + 3*350*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40218*0 + 3*350*FLEN/8, x4, x1, x2)

inst_13407:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8f800007; valaddr_reg:x3; val_offset:40221*0 + 3*351*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40221*0 + 3*351*FLEN/8, x4, x1, x2)

inst_13408:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8f80000f; valaddr_reg:x3; val_offset:40224*0 + 3*352*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40224*0 + 3*352*FLEN/8, x4, x1, x2)

inst_13409:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8f80001f; valaddr_reg:x3; val_offset:40227*0 + 3*353*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40227*0 + 3*353*FLEN/8, x4, x1, x2)

inst_13410:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8f80003f; valaddr_reg:x3; val_offset:40230*0 + 3*354*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40230*0 + 3*354*FLEN/8, x4, x1, x2)

inst_13411:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8f80007f; valaddr_reg:x3; val_offset:40233*0 + 3*355*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40233*0 + 3*355*FLEN/8, x4, x1, x2)

inst_13412:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8f8000ff; valaddr_reg:x3; val_offset:40236*0 + 3*356*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40236*0 + 3*356*FLEN/8, x4, x1, x2)

inst_13413:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8f8001ff; valaddr_reg:x3; val_offset:40239*0 + 3*357*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40239*0 + 3*357*FLEN/8, x4, x1, x2)

inst_13414:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8f8003ff; valaddr_reg:x3; val_offset:40242*0 + 3*358*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40242*0 + 3*358*FLEN/8, x4, x1, x2)

inst_13415:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8f8007ff; valaddr_reg:x3; val_offset:40245*0 + 3*359*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40245*0 + 3*359*FLEN/8, x4, x1, x2)

inst_13416:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8f800fff; valaddr_reg:x3; val_offset:40248*0 + 3*360*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40248*0 + 3*360*FLEN/8, x4, x1, x2)

inst_13417:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8f801fff; valaddr_reg:x3; val_offset:40251*0 + 3*361*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40251*0 + 3*361*FLEN/8, x4, x1, x2)

inst_13418:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8f803fff; valaddr_reg:x3; val_offset:40254*0 + 3*362*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40254*0 + 3*362*FLEN/8, x4, x1, x2)

inst_13419:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8f807fff; valaddr_reg:x3; val_offset:40257*0 + 3*363*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40257*0 + 3*363*FLEN/8, x4, x1, x2)

inst_13420:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8f80ffff; valaddr_reg:x3; val_offset:40260*0 + 3*364*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40260*0 + 3*364*FLEN/8, x4, x1, x2)

inst_13421:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8f81ffff; valaddr_reg:x3; val_offset:40263*0 + 3*365*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40263*0 + 3*365*FLEN/8, x4, x1, x2)

inst_13422:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8f83ffff; valaddr_reg:x3; val_offset:40266*0 + 3*366*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40266*0 + 3*366*FLEN/8, x4, x1, x2)

inst_13423:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8f87ffff; valaddr_reg:x3; val_offset:40269*0 + 3*367*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40269*0 + 3*367*FLEN/8, x4, x1, x2)

inst_13424:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8f8fffff; valaddr_reg:x3; val_offset:40272*0 + 3*368*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40272*0 + 3*368*FLEN/8, x4, x1, x2)

inst_13425:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8f9fffff; valaddr_reg:x3; val_offset:40275*0 + 3*369*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40275*0 + 3*369*FLEN/8, x4, x1, x2)

inst_13426:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8fbfffff; valaddr_reg:x3; val_offset:40278*0 + 3*370*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40278*0 + 3*370*FLEN/8, x4, x1, x2)

inst_13427:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8fc00000; valaddr_reg:x3; val_offset:40281*0 + 3*371*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40281*0 + 3*371*FLEN/8, x4, x1, x2)

inst_13428:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8fe00000; valaddr_reg:x3; val_offset:40284*0 + 3*372*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40284*0 + 3*372*FLEN/8, x4, x1, x2)

inst_13429:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8ff00000; valaddr_reg:x3; val_offset:40287*0 + 3*373*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40287*0 + 3*373*FLEN/8, x4, x1, x2)

inst_13430:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8ff80000; valaddr_reg:x3; val_offset:40290*0 + 3*374*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40290*0 + 3*374*FLEN/8, x4, x1, x2)

inst_13431:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8ffc0000; valaddr_reg:x3; val_offset:40293*0 + 3*375*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40293*0 + 3*375*FLEN/8, x4, x1, x2)

inst_13432:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8ffe0000; valaddr_reg:x3; val_offset:40296*0 + 3*376*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40296*0 + 3*376*FLEN/8, x4, x1, x2)

inst_13433:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8fff0000; valaddr_reg:x3; val_offset:40299*0 + 3*377*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40299*0 + 3*377*FLEN/8, x4, x1, x2)

inst_13434:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8fff8000; valaddr_reg:x3; val_offset:40302*0 + 3*378*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40302*0 + 3*378*FLEN/8, x4, x1, x2)

inst_13435:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8fffc000; valaddr_reg:x3; val_offset:40305*0 + 3*379*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40305*0 + 3*379*FLEN/8, x4, x1, x2)

inst_13436:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8fffe000; valaddr_reg:x3; val_offset:40308*0 + 3*380*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40308*0 + 3*380*FLEN/8, x4, x1, x2)

inst_13437:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8ffff000; valaddr_reg:x3; val_offset:40311*0 + 3*381*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40311*0 + 3*381*FLEN/8, x4, x1, x2)

inst_13438:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8ffff800; valaddr_reg:x3; val_offset:40314*0 + 3*382*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40314*0 + 3*382*FLEN/8, x4, x1, x2)

inst_13439:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8ffffc00; valaddr_reg:x3; val_offset:40317*0 + 3*383*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40317*0 + 3*383*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_4)

inst_13440:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8ffffe00; valaddr_reg:x3; val_offset:40320*0 + 3*384*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40320*0 + 3*384*FLEN/8, x4, x1, x2)

inst_13441:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8fffff00; valaddr_reg:x3; val_offset:40323*0 + 3*385*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40323*0 + 3*385*FLEN/8, x4, x1, x2)

inst_13442:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8fffff80; valaddr_reg:x3; val_offset:40326*0 + 3*386*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40326*0 + 3*386*FLEN/8, x4, x1, x2)

inst_13443:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8fffffc0; valaddr_reg:x3; val_offset:40329*0 + 3*387*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40329*0 + 3*387*FLEN/8, x4, x1, x2)

inst_13444:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8fffffe0; valaddr_reg:x3; val_offset:40332*0 + 3*388*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40332*0 + 3*388*FLEN/8, x4, x1, x2)

inst_13445:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8ffffff0; valaddr_reg:x3; val_offset:40335*0 + 3*389*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40335*0 + 3*389*FLEN/8, x4, x1, x2)

inst_13446:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8ffffff8; valaddr_reg:x3; val_offset:40338*0 + 3*390*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40338*0 + 3*390*FLEN/8, x4, x1, x2)

inst_13447:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8ffffffc; valaddr_reg:x3; val_offset:40341*0 + 3*391*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40341*0 + 3*391*FLEN/8, x4, x1, x2)

inst_13448:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8ffffffe; valaddr_reg:x3; val_offset:40344*0 + 3*392*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40344*0 + 3*392*FLEN/8, x4, x1, x2)

inst_13449:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x0e47db and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e8e47db; op2val:0x80000000;
op3val:0x8fffffff; valaddr_reg:x3; val_offset:40347*0 + 3*393*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40347*0 + 3*393*FLEN/8, x4, x1, x2)

inst_13450:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xd1 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x68800000; valaddr_reg:x3; val_offset:40350*0 + 3*394*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40350*0 + 3*394*FLEN/8, x4, x1, x2)

inst_13451:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xd1 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x68800001; valaddr_reg:x3; val_offset:40353*0 + 3*395*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40353*0 + 3*395*FLEN/8, x4, x1, x2)

inst_13452:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xd1 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x68800003; valaddr_reg:x3; val_offset:40356*0 + 3*396*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40356*0 + 3*396*FLEN/8, x4, x1, x2)

inst_13453:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xd1 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x68800007; valaddr_reg:x3; val_offset:40359*0 + 3*397*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40359*0 + 3*397*FLEN/8, x4, x1, x2)

inst_13454:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xd1 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x6880000f; valaddr_reg:x3; val_offset:40362*0 + 3*398*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40362*0 + 3*398*FLEN/8, x4, x1, x2)

inst_13455:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xd1 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x6880001f; valaddr_reg:x3; val_offset:40365*0 + 3*399*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40365*0 + 3*399*FLEN/8, x4, x1, x2)

inst_13456:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xd1 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x6880003f; valaddr_reg:x3; val_offset:40368*0 + 3*400*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40368*0 + 3*400*FLEN/8, x4, x1, x2)

inst_13457:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xd1 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x6880007f; valaddr_reg:x3; val_offset:40371*0 + 3*401*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40371*0 + 3*401*FLEN/8, x4, x1, x2)

inst_13458:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xd1 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x688000ff; valaddr_reg:x3; val_offset:40374*0 + 3*402*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40374*0 + 3*402*FLEN/8, x4, x1, x2)

inst_13459:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xd1 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x688001ff; valaddr_reg:x3; val_offset:40377*0 + 3*403*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40377*0 + 3*403*FLEN/8, x4, x1, x2)

inst_13460:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xd1 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x688003ff; valaddr_reg:x3; val_offset:40380*0 + 3*404*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40380*0 + 3*404*FLEN/8, x4, x1, x2)

inst_13461:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xd1 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x688007ff; valaddr_reg:x3; val_offset:40383*0 + 3*405*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40383*0 + 3*405*FLEN/8, x4, x1, x2)

inst_13462:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xd1 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x68800fff; valaddr_reg:x3; val_offset:40386*0 + 3*406*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40386*0 + 3*406*FLEN/8, x4, x1, x2)

inst_13463:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xd1 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x68801fff; valaddr_reg:x3; val_offset:40389*0 + 3*407*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40389*0 + 3*407*FLEN/8, x4, x1, x2)

inst_13464:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xd1 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x68803fff; valaddr_reg:x3; val_offset:40392*0 + 3*408*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40392*0 + 3*408*FLEN/8, x4, x1, x2)

inst_13465:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xd1 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x68807fff; valaddr_reg:x3; val_offset:40395*0 + 3*409*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40395*0 + 3*409*FLEN/8, x4, x1, x2)

inst_13466:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xd1 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x6880ffff; valaddr_reg:x3; val_offset:40398*0 + 3*410*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40398*0 + 3*410*FLEN/8, x4, x1, x2)

inst_13467:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xd1 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x6881ffff; valaddr_reg:x3; val_offset:40401*0 + 3*411*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40401*0 + 3*411*FLEN/8, x4, x1, x2)

inst_13468:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xd1 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x6883ffff; valaddr_reg:x3; val_offset:40404*0 + 3*412*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40404*0 + 3*412*FLEN/8, x4, x1, x2)

inst_13469:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xd1 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x6887ffff; valaddr_reg:x3; val_offset:40407*0 + 3*413*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40407*0 + 3*413*FLEN/8, x4, x1, x2)

inst_13470:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xd1 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x688fffff; valaddr_reg:x3; val_offset:40410*0 + 3*414*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40410*0 + 3*414*FLEN/8, x4, x1, x2)

inst_13471:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xd1 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x689fffff; valaddr_reg:x3; val_offset:40413*0 + 3*415*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40413*0 + 3*415*FLEN/8, x4, x1, x2)

inst_13472:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xd1 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x68bfffff; valaddr_reg:x3; val_offset:40416*0 + 3*416*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40416*0 + 3*416*FLEN/8, x4, x1, x2)

inst_13473:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xd1 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x68c00000; valaddr_reg:x3; val_offset:40419*0 + 3*417*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40419*0 + 3*417*FLEN/8, x4, x1, x2)

inst_13474:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xd1 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x68e00000; valaddr_reg:x3; val_offset:40422*0 + 3*418*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40422*0 + 3*418*FLEN/8, x4, x1, x2)

inst_13475:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xd1 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x68f00000; valaddr_reg:x3; val_offset:40425*0 + 3*419*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40425*0 + 3*419*FLEN/8, x4, x1, x2)

inst_13476:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xd1 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x68f80000; valaddr_reg:x3; val_offset:40428*0 + 3*420*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40428*0 + 3*420*FLEN/8, x4, x1, x2)

inst_13477:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xd1 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x68fc0000; valaddr_reg:x3; val_offset:40431*0 + 3*421*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40431*0 + 3*421*FLEN/8, x4, x1, x2)

inst_13478:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xd1 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x68fe0000; valaddr_reg:x3; val_offset:40434*0 + 3*422*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40434*0 + 3*422*FLEN/8, x4, x1, x2)

inst_13479:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xd1 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x68ff0000; valaddr_reg:x3; val_offset:40437*0 + 3*423*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40437*0 + 3*423*FLEN/8, x4, x1, x2)

inst_13480:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xd1 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x68ff8000; valaddr_reg:x3; val_offset:40440*0 + 3*424*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40440*0 + 3*424*FLEN/8, x4, x1, x2)

inst_13481:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xd1 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x68ffc000; valaddr_reg:x3; val_offset:40443*0 + 3*425*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40443*0 + 3*425*FLEN/8, x4, x1, x2)

inst_13482:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xd1 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x68ffe000; valaddr_reg:x3; val_offset:40446*0 + 3*426*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40446*0 + 3*426*FLEN/8, x4, x1, x2)

inst_13483:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xd1 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x68fff000; valaddr_reg:x3; val_offset:40449*0 + 3*427*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40449*0 + 3*427*FLEN/8, x4, x1, x2)

inst_13484:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xd1 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x68fff800; valaddr_reg:x3; val_offset:40452*0 + 3*428*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40452*0 + 3*428*FLEN/8, x4, x1, x2)

inst_13485:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xd1 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x68fffc00; valaddr_reg:x3; val_offset:40455*0 + 3*429*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40455*0 + 3*429*FLEN/8, x4, x1, x2)

inst_13486:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xd1 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x68fffe00; valaddr_reg:x3; val_offset:40458*0 + 3*430*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40458*0 + 3*430*FLEN/8, x4, x1, x2)

inst_13487:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xd1 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x68ffff00; valaddr_reg:x3; val_offset:40461*0 + 3*431*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40461*0 + 3*431*FLEN/8, x4, x1, x2)

inst_13488:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xd1 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x68ffff80; valaddr_reg:x3; val_offset:40464*0 + 3*432*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40464*0 + 3*432*FLEN/8, x4, x1, x2)

inst_13489:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xd1 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x68ffffc0; valaddr_reg:x3; val_offset:40467*0 + 3*433*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40467*0 + 3*433*FLEN/8, x4, x1, x2)

inst_13490:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xd1 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x68ffffe0; valaddr_reg:x3; val_offset:40470*0 + 3*434*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40470*0 + 3*434*FLEN/8, x4, x1, x2)

inst_13491:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xd1 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x68fffff0; valaddr_reg:x3; val_offset:40473*0 + 3*435*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40473*0 + 3*435*FLEN/8, x4, x1, x2)

inst_13492:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xd1 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x68fffff8; valaddr_reg:x3; val_offset:40476*0 + 3*436*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40476*0 + 3*436*FLEN/8, x4, x1, x2)

inst_13493:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xd1 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x68fffffc; valaddr_reg:x3; val_offset:40479*0 + 3*437*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40479*0 + 3*437*FLEN/8, x4, x1, x2)

inst_13494:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xd1 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x68fffffe; valaddr_reg:x3; val_offset:40482*0 + 3*438*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40482*0 + 3*438*FLEN/8, x4, x1, x2)

inst_13495:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xd1 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x68ffffff; valaddr_reg:x3; val_offset:40485*0 + 3*439*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40485*0 + 3*439*FLEN/8, x4, x1, x2)

inst_13496:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x7f000001; valaddr_reg:x3; val_offset:40488*0 + 3*440*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40488*0 + 3*440*FLEN/8, x4, x1, x2)

inst_13497:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x7f000003; valaddr_reg:x3; val_offset:40491*0 + 3*441*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40491*0 + 3*441*FLEN/8, x4, x1, x2)

inst_13498:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x7f000007; valaddr_reg:x3; val_offset:40494*0 + 3*442*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40494*0 + 3*442*FLEN/8, x4, x1, x2)

inst_13499:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x7f199999; valaddr_reg:x3; val_offset:40497*0 + 3*443*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40497*0 + 3*443*FLEN/8, x4, x1, x2)

inst_13500:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x7f249249; valaddr_reg:x3; val_offset:40500*0 + 3*444*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40500*0 + 3*444*FLEN/8, x4, x1, x2)

inst_13501:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x7f333333; valaddr_reg:x3; val_offset:40503*0 + 3*445*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40503*0 + 3*445*FLEN/8, x4, x1, x2)

inst_13502:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x7f36db6d; valaddr_reg:x3; val_offset:40506*0 + 3*446*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40506*0 + 3*446*FLEN/8, x4, x1, x2)

inst_13503:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x7f3bbbbb; valaddr_reg:x3; val_offset:40509*0 + 3*447*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40509*0 + 3*447*FLEN/8, x4, x1, x2)

inst_13504:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x7f444444; valaddr_reg:x3; val_offset:40512*0 + 3*448*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40512*0 + 3*448*FLEN/8, x4, x1, x2)

inst_13505:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x7f4ccccc; valaddr_reg:x3; val_offset:40515*0 + 3*449*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40515*0 + 3*449*FLEN/8, x4, x1, x2)

inst_13506:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x7f5b6db6; valaddr_reg:x3; val_offset:40518*0 + 3*450*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40518*0 + 3*450*FLEN/8, x4, x1, x2)

inst_13507:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x7f666666; valaddr_reg:x3; val_offset:40521*0 + 3*451*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40521*0 + 3*451*FLEN/8, x4, x1, x2)

inst_13508:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x7f6db6db; valaddr_reg:x3; val_offset:40524*0 + 3*452*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40524*0 + 3*452*FLEN/8, x4, x1, x2)

inst_13509:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x7f7ffff8; valaddr_reg:x3; val_offset:40527*0 + 3*453*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40527*0 + 3*453*FLEN/8, x4, x1, x2)

inst_13510:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x7f7ffffc; valaddr_reg:x3; val_offset:40530*0 + 3*454*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40530*0 + 3*454*FLEN/8, x4, x1, x2)

inst_13511:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x10fb7b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x620382 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e90fb7b; op2val:0x40620382;
op3val:0x7f7ffffe; valaddr_reg:x3; val_offset:40533*0 + 3*455*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40533*0 + 3*455*FLEN/8, x4, x1, x2)

inst_13512:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x80800001; valaddr_reg:x3; val_offset:40536*0 + 3*456*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40536*0 + 3*456*FLEN/8, x4, x1, x2)

inst_13513:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x80800003; valaddr_reg:x3; val_offset:40539*0 + 3*457*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40539*0 + 3*457*FLEN/8, x4, x1, x2)

inst_13514:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x80800007; valaddr_reg:x3; val_offset:40542*0 + 3*458*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40542*0 + 3*458*FLEN/8, x4, x1, x2)

inst_13515:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x80999999; valaddr_reg:x3; val_offset:40545*0 + 3*459*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40545*0 + 3*459*FLEN/8, x4, x1, x2)

inst_13516:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x80a49249; valaddr_reg:x3; val_offset:40548*0 + 3*460*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40548*0 + 3*460*FLEN/8, x4, x1, x2)

inst_13517:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x80b33333; valaddr_reg:x3; val_offset:40551*0 + 3*461*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40551*0 + 3*461*FLEN/8, x4, x1, x2)

inst_13518:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x80b6db6d; valaddr_reg:x3; val_offset:40554*0 + 3*462*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40554*0 + 3*462*FLEN/8, x4, x1, x2)

inst_13519:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x80bbbbbb; valaddr_reg:x3; val_offset:40557*0 + 3*463*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40557*0 + 3*463*FLEN/8, x4, x1, x2)

inst_13520:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x80c44444; valaddr_reg:x3; val_offset:40560*0 + 3*464*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40560*0 + 3*464*FLEN/8, x4, x1, x2)

inst_13521:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x80cccccc; valaddr_reg:x3; val_offset:40563*0 + 3*465*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40563*0 + 3*465*FLEN/8, x4, x1, x2)

inst_13522:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x80db6db6; valaddr_reg:x3; val_offset:40566*0 + 3*466*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40566*0 + 3*466*FLEN/8, x4, x1, x2)

inst_13523:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x80e66666; valaddr_reg:x3; val_offset:40569*0 + 3*467*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40569*0 + 3*467*FLEN/8, x4, x1, x2)

inst_13524:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x80edb6db; valaddr_reg:x3; val_offset:40572*0 + 3*468*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40572*0 + 3*468*FLEN/8, x4, x1, x2)

inst_13525:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x80fffff8; valaddr_reg:x3; val_offset:40575*0 + 3*469*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40575*0 + 3*469*FLEN/8, x4, x1, x2)

inst_13526:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x80fffffc; valaddr_reg:x3; val_offset:40578*0 + 3*470*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40578*0 + 3*470*FLEN/8, x4, x1, x2)

inst_13527:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x80fffffe; valaddr_reg:x3; val_offset:40581*0 + 3*471*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40581*0 + 3*471*FLEN/8, x4, x1, x2)

inst_13528:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x08 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x84000000; valaddr_reg:x3; val_offset:40584*0 + 3*472*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40584*0 + 3*472*FLEN/8, x4, x1, x2)

inst_13529:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x08 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x84000001; valaddr_reg:x3; val_offset:40587*0 + 3*473*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40587*0 + 3*473*FLEN/8, x4, x1, x2)

inst_13530:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x08 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x84000003; valaddr_reg:x3; val_offset:40590*0 + 3*474*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40590*0 + 3*474*FLEN/8, x4, x1, x2)

inst_13531:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x08 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x84000007; valaddr_reg:x3; val_offset:40593*0 + 3*475*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40593*0 + 3*475*FLEN/8, x4, x1, x2)

inst_13532:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x08 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x8400000f; valaddr_reg:x3; val_offset:40596*0 + 3*476*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40596*0 + 3*476*FLEN/8, x4, x1, x2)

inst_13533:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x08 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x8400001f; valaddr_reg:x3; val_offset:40599*0 + 3*477*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40599*0 + 3*477*FLEN/8, x4, x1, x2)

inst_13534:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x08 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x8400003f; valaddr_reg:x3; val_offset:40602*0 + 3*478*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40602*0 + 3*478*FLEN/8, x4, x1, x2)

inst_13535:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x08 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x8400007f; valaddr_reg:x3; val_offset:40605*0 + 3*479*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40605*0 + 3*479*FLEN/8, x4, x1, x2)

inst_13536:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x08 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x840000ff; valaddr_reg:x3; val_offset:40608*0 + 3*480*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40608*0 + 3*480*FLEN/8, x4, x1, x2)

inst_13537:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x08 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x840001ff; valaddr_reg:x3; val_offset:40611*0 + 3*481*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40611*0 + 3*481*FLEN/8, x4, x1, x2)

inst_13538:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x08 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x840003ff; valaddr_reg:x3; val_offset:40614*0 + 3*482*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40614*0 + 3*482*FLEN/8, x4, x1, x2)

inst_13539:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x08 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x840007ff; valaddr_reg:x3; val_offset:40617*0 + 3*483*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40617*0 + 3*483*FLEN/8, x4, x1, x2)

inst_13540:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x08 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x84000fff; valaddr_reg:x3; val_offset:40620*0 + 3*484*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40620*0 + 3*484*FLEN/8, x4, x1, x2)

inst_13541:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x08 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x84001fff; valaddr_reg:x3; val_offset:40623*0 + 3*485*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40623*0 + 3*485*FLEN/8, x4, x1, x2)

inst_13542:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x08 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x84003fff; valaddr_reg:x3; val_offset:40626*0 + 3*486*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40626*0 + 3*486*FLEN/8, x4, x1, x2)

inst_13543:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x08 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x84007fff; valaddr_reg:x3; val_offset:40629*0 + 3*487*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40629*0 + 3*487*FLEN/8, x4, x1, x2)

inst_13544:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x08 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x8400ffff; valaddr_reg:x3; val_offset:40632*0 + 3*488*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40632*0 + 3*488*FLEN/8, x4, x1, x2)

inst_13545:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x08 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x8401ffff; valaddr_reg:x3; val_offset:40635*0 + 3*489*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40635*0 + 3*489*FLEN/8, x4, x1, x2)

inst_13546:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x08 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x8403ffff; valaddr_reg:x3; val_offset:40638*0 + 3*490*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40638*0 + 3*490*FLEN/8, x4, x1, x2)

inst_13547:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x08 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x8407ffff; valaddr_reg:x3; val_offset:40641*0 + 3*491*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40641*0 + 3*491*FLEN/8, x4, x1, x2)

inst_13548:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x08 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x840fffff; valaddr_reg:x3; val_offset:40644*0 + 3*492*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40644*0 + 3*492*FLEN/8, x4, x1, x2)

inst_13549:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x08 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x841fffff; valaddr_reg:x3; val_offset:40647*0 + 3*493*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40647*0 + 3*493*FLEN/8, x4, x1, x2)

inst_13550:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x08 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x843fffff; valaddr_reg:x3; val_offset:40650*0 + 3*494*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40650*0 + 3*494*FLEN/8, x4, x1, x2)

inst_13551:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x08 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x84400000; valaddr_reg:x3; val_offset:40653*0 + 3*495*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40653*0 + 3*495*FLEN/8, x4, x1, x2)

inst_13552:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x08 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x84600000; valaddr_reg:x3; val_offset:40656*0 + 3*496*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40656*0 + 3*496*FLEN/8, x4, x1, x2)

inst_13553:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x08 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x84700000; valaddr_reg:x3; val_offset:40659*0 + 3*497*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40659*0 + 3*497*FLEN/8, x4, x1, x2)

inst_13554:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x08 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x84780000; valaddr_reg:x3; val_offset:40662*0 + 3*498*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40662*0 + 3*498*FLEN/8, x4, x1, x2)

inst_13555:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x08 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x847c0000; valaddr_reg:x3; val_offset:40665*0 + 3*499*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40665*0 + 3*499*FLEN/8, x4, x1, x2)

inst_13556:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x08 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x847e0000; valaddr_reg:x3; val_offset:40668*0 + 3*500*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40668*0 + 3*500*FLEN/8, x4, x1, x2)

inst_13557:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x08 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x847f0000; valaddr_reg:x3; val_offset:40671*0 + 3*501*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40671*0 + 3*501*FLEN/8, x4, x1, x2)

inst_13558:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x08 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x847f8000; valaddr_reg:x3; val_offset:40674*0 + 3*502*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40674*0 + 3*502*FLEN/8, x4, x1, x2)

inst_13559:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x08 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x847fc000; valaddr_reg:x3; val_offset:40677*0 + 3*503*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40677*0 + 3*503*FLEN/8, x4, x1, x2)

inst_13560:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x08 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x847fe000; valaddr_reg:x3; val_offset:40680*0 + 3*504*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40680*0 + 3*504*FLEN/8, x4, x1, x2)

inst_13561:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x08 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x847ff000; valaddr_reg:x3; val_offset:40683*0 + 3*505*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40683*0 + 3*505*FLEN/8, x4, x1, x2)

inst_13562:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x08 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x847ff800; valaddr_reg:x3; val_offset:40686*0 + 3*506*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40686*0 + 3*506*FLEN/8, x4, x1, x2)

inst_13563:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x08 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x847ffc00; valaddr_reg:x3; val_offset:40689*0 + 3*507*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40689*0 + 3*507*FLEN/8, x4, x1, x2)

inst_13564:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x08 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x847ffe00; valaddr_reg:x3; val_offset:40692*0 + 3*508*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40692*0 + 3*508*FLEN/8, x4, x1, x2)

inst_13565:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x08 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x847fff00; valaddr_reg:x3; val_offset:40695*0 + 3*509*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40695*0 + 3*509*FLEN/8, x4, x1, x2)

inst_13566:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x08 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x847fff80; valaddr_reg:x3; val_offset:40698*0 + 3*510*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40698*0 + 3*510*FLEN/8, x4, x1, x2)

inst_13567:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x08 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x847fffc0; valaddr_reg:x3; val_offset:40701*0 + 3*511*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40701*0 + 3*511*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_5)

inst_13568:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x08 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x847fffe0; valaddr_reg:x3; val_offset:40704*0 + 3*512*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40704*0 + 3*512*FLEN/8, x4, x1, x2)

inst_13569:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x08 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x847ffff0; valaddr_reg:x3; val_offset:40707*0 + 3*513*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40707*0 + 3*513*FLEN/8, x4, x1, x2)

inst_13570:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x08 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x847ffff8; valaddr_reg:x3; val_offset:40710*0 + 3*514*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40710*0 + 3*514*FLEN/8, x4, x1, x2)

inst_13571:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x08 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x847ffffc; valaddr_reg:x3; val_offset:40713*0 + 3*515*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40713*0 + 3*515*FLEN/8, x4, x1, x2)

inst_13572:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x08 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x847ffffe; valaddr_reg:x3; val_offset:40716*0 + 3*516*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40716*0 + 3*516*FLEN/8, x4, x1, x2)

inst_13573:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x117a6b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x08 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e917a6b; op2val:0x80000000;
op3val:0x847fffff; valaddr_reg:x3; val_offset:40719*0 + 3*517*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40719*0 + 3*517*FLEN/8, x4, x1, x2)

inst_13574:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x62 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xb1000000; valaddr_reg:x3; val_offset:40722*0 + 3*518*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40722*0 + 3*518*FLEN/8, x4, x1, x2)

inst_13575:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x62 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xb1000001; valaddr_reg:x3; val_offset:40725*0 + 3*519*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40725*0 + 3*519*FLEN/8, x4, x1, x2)

inst_13576:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x62 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xb1000003; valaddr_reg:x3; val_offset:40728*0 + 3*520*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40728*0 + 3*520*FLEN/8, x4, x1, x2)

inst_13577:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x62 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xb1000007; valaddr_reg:x3; val_offset:40731*0 + 3*521*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40731*0 + 3*521*FLEN/8, x4, x1, x2)

inst_13578:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x62 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xb100000f; valaddr_reg:x3; val_offset:40734*0 + 3*522*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40734*0 + 3*522*FLEN/8, x4, x1, x2)

inst_13579:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x62 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xb100001f; valaddr_reg:x3; val_offset:40737*0 + 3*523*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40737*0 + 3*523*FLEN/8, x4, x1, x2)

inst_13580:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x62 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xb100003f; valaddr_reg:x3; val_offset:40740*0 + 3*524*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40740*0 + 3*524*FLEN/8, x4, x1, x2)

inst_13581:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x62 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xb100007f; valaddr_reg:x3; val_offset:40743*0 + 3*525*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40743*0 + 3*525*FLEN/8, x4, x1, x2)

inst_13582:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x62 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xb10000ff; valaddr_reg:x3; val_offset:40746*0 + 3*526*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40746*0 + 3*526*FLEN/8, x4, x1, x2)

inst_13583:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x62 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xb10001ff; valaddr_reg:x3; val_offset:40749*0 + 3*527*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40749*0 + 3*527*FLEN/8, x4, x1, x2)

inst_13584:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x62 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xb10003ff; valaddr_reg:x3; val_offset:40752*0 + 3*528*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40752*0 + 3*528*FLEN/8, x4, x1, x2)

inst_13585:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x62 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xb10007ff; valaddr_reg:x3; val_offset:40755*0 + 3*529*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40755*0 + 3*529*FLEN/8, x4, x1, x2)

inst_13586:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x62 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xb1000fff; valaddr_reg:x3; val_offset:40758*0 + 3*530*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40758*0 + 3*530*FLEN/8, x4, x1, x2)

inst_13587:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x62 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xb1001fff; valaddr_reg:x3; val_offset:40761*0 + 3*531*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40761*0 + 3*531*FLEN/8, x4, x1, x2)

inst_13588:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x62 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xb1003fff; valaddr_reg:x3; val_offset:40764*0 + 3*532*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40764*0 + 3*532*FLEN/8, x4, x1, x2)

inst_13589:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x62 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xb1007fff; valaddr_reg:x3; val_offset:40767*0 + 3*533*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40767*0 + 3*533*FLEN/8, x4, x1, x2)

inst_13590:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x62 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xb100ffff; valaddr_reg:x3; val_offset:40770*0 + 3*534*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40770*0 + 3*534*FLEN/8, x4, x1, x2)

inst_13591:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x62 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xb101ffff; valaddr_reg:x3; val_offset:40773*0 + 3*535*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40773*0 + 3*535*FLEN/8, x4, x1, x2)

inst_13592:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x62 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xb103ffff; valaddr_reg:x3; val_offset:40776*0 + 3*536*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40776*0 + 3*536*FLEN/8, x4, x1, x2)

inst_13593:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x62 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xb107ffff; valaddr_reg:x3; val_offset:40779*0 + 3*537*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40779*0 + 3*537*FLEN/8, x4, x1, x2)

inst_13594:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x62 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xb10fffff; valaddr_reg:x3; val_offset:40782*0 + 3*538*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40782*0 + 3*538*FLEN/8, x4, x1, x2)

inst_13595:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x62 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xb11fffff; valaddr_reg:x3; val_offset:40785*0 + 3*539*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40785*0 + 3*539*FLEN/8, x4, x1, x2)

inst_13596:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x62 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xb13fffff; valaddr_reg:x3; val_offset:40788*0 + 3*540*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40788*0 + 3*540*FLEN/8, x4, x1, x2)

inst_13597:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x62 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xb1400000; valaddr_reg:x3; val_offset:40791*0 + 3*541*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40791*0 + 3*541*FLEN/8, x4, x1, x2)

inst_13598:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x62 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xb1600000; valaddr_reg:x3; val_offset:40794*0 + 3*542*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40794*0 + 3*542*FLEN/8, x4, x1, x2)

inst_13599:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x62 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xb1700000; valaddr_reg:x3; val_offset:40797*0 + 3*543*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40797*0 + 3*543*FLEN/8, x4, x1, x2)

inst_13600:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x62 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xb1780000; valaddr_reg:x3; val_offset:40800*0 + 3*544*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40800*0 + 3*544*FLEN/8, x4, x1, x2)

inst_13601:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x62 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xb17c0000; valaddr_reg:x3; val_offset:40803*0 + 3*545*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40803*0 + 3*545*FLEN/8, x4, x1, x2)

inst_13602:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x62 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xb17e0000; valaddr_reg:x3; val_offset:40806*0 + 3*546*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40806*0 + 3*546*FLEN/8, x4, x1, x2)

inst_13603:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x62 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xb17f0000; valaddr_reg:x3; val_offset:40809*0 + 3*547*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40809*0 + 3*547*FLEN/8, x4, x1, x2)

inst_13604:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x62 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xb17f8000; valaddr_reg:x3; val_offset:40812*0 + 3*548*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40812*0 + 3*548*FLEN/8, x4, x1, x2)

inst_13605:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x62 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xb17fc000; valaddr_reg:x3; val_offset:40815*0 + 3*549*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40815*0 + 3*549*FLEN/8, x4, x1, x2)

inst_13606:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x62 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xb17fe000; valaddr_reg:x3; val_offset:40818*0 + 3*550*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40818*0 + 3*550*FLEN/8, x4, x1, x2)

inst_13607:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x62 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xb17ff000; valaddr_reg:x3; val_offset:40821*0 + 3*551*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40821*0 + 3*551*FLEN/8, x4, x1, x2)

inst_13608:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x62 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xb17ff800; valaddr_reg:x3; val_offset:40824*0 + 3*552*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40824*0 + 3*552*FLEN/8, x4, x1, x2)

inst_13609:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x62 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xb17ffc00; valaddr_reg:x3; val_offset:40827*0 + 3*553*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40827*0 + 3*553*FLEN/8, x4, x1, x2)

inst_13610:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x62 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xb17ffe00; valaddr_reg:x3; val_offset:40830*0 + 3*554*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40830*0 + 3*554*FLEN/8, x4, x1, x2)

inst_13611:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x62 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xb17fff00; valaddr_reg:x3; val_offset:40833*0 + 3*555*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40833*0 + 3*555*FLEN/8, x4, x1, x2)

inst_13612:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x62 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xb17fff80; valaddr_reg:x3; val_offset:40836*0 + 3*556*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40836*0 + 3*556*FLEN/8, x4, x1, x2)

inst_13613:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x62 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xb17fffc0; valaddr_reg:x3; val_offset:40839*0 + 3*557*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40839*0 + 3*557*FLEN/8, x4, x1, x2)

inst_13614:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x62 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xb17fffe0; valaddr_reg:x3; val_offset:40842*0 + 3*558*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40842*0 + 3*558*FLEN/8, x4, x1, x2)

inst_13615:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x62 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xb17ffff0; valaddr_reg:x3; val_offset:40845*0 + 3*559*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40845*0 + 3*559*FLEN/8, x4, x1, x2)

inst_13616:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x62 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xb17ffff8; valaddr_reg:x3; val_offset:40848*0 + 3*560*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40848*0 + 3*560*FLEN/8, x4, x1, x2)

inst_13617:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x62 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xb17ffffc; valaddr_reg:x3; val_offset:40851*0 + 3*561*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40851*0 + 3*561*FLEN/8, x4, x1, x2)

inst_13618:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x62 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xb17ffffe; valaddr_reg:x3; val_offset:40854*0 + 3*562*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40854*0 + 3*562*FLEN/8, x4, x1, x2)

inst_13619:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x62 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xb17fffff; valaddr_reg:x3; val_offset:40857*0 + 3*563*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40857*0 + 3*563*FLEN/8, x4, x1, x2)

inst_13620:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xbf800001; valaddr_reg:x3; val_offset:40860*0 + 3*564*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40860*0 + 3*564*FLEN/8, x4, x1, x2)

inst_13621:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xbf800003; valaddr_reg:x3; val_offset:40863*0 + 3*565*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40863*0 + 3*565*FLEN/8, x4, x1, x2)

inst_13622:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xbf800007; valaddr_reg:x3; val_offset:40866*0 + 3*566*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40866*0 + 3*566*FLEN/8, x4, x1, x2)

inst_13623:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xbf999999; valaddr_reg:x3; val_offset:40869*0 + 3*567*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40869*0 + 3*567*FLEN/8, x4, x1, x2)

inst_13624:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xbfa49249; valaddr_reg:x3; val_offset:40872*0 + 3*568*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40872*0 + 3*568*FLEN/8, x4, x1, x2)

inst_13625:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xbfb33333; valaddr_reg:x3; val_offset:40875*0 + 3*569*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40875*0 + 3*569*FLEN/8, x4, x1, x2)

inst_13626:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xbfb6db6d; valaddr_reg:x3; val_offset:40878*0 + 3*570*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40878*0 + 3*570*FLEN/8, x4, x1, x2)

inst_13627:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xbfbbbbbb; valaddr_reg:x3; val_offset:40881*0 + 3*571*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40881*0 + 3*571*FLEN/8, x4, x1, x2)

inst_13628:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xbfc44444; valaddr_reg:x3; val_offset:40884*0 + 3*572*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40884*0 + 3*572*FLEN/8, x4, x1, x2)

inst_13629:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xbfcccccc; valaddr_reg:x3; val_offset:40887*0 + 3*573*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40887*0 + 3*573*FLEN/8, x4, x1, x2)

inst_13630:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xbfdb6db6; valaddr_reg:x3; val_offset:40890*0 + 3*574*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40890*0 + 3*574*FLEN/8, x4, x1, x2)

inst_13631:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xbfe66666; valaddr_reg:x3; val_offset:40893*0 + 3*575*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40893*0 + 3*575*FLEN/8, x4, x1, x2)

inst_13632:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xbfedb6db; valaddr_reg:x3; val_offset:40896*0 + 3*576*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40896*0 + 3*576*FLEN/8, x4, x1, x2)

inst_13633:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xbffffff8; valaddr_reg:x3; val_offset:40899*0 + 3*577*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40899*0 + 3*577*FLEN/8, x4, x1, x2)

inst_13634:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xbffffffc; valaddr_reg:x3; val_offset:40902*0 + 3*578*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40902*0 + 3*578*FLEN/8, x4, x1, x2)

inst_13635:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11a030 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7081f1 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91a030; op2val:0x807081f1;
op3val:0xbffffffe; valaddr_reg:x3; val_offset:40905*0 + 3*579*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40905*0 + 3*579*FLEN/8, x4, x1, x2)

inst_13636:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x1; valaddr_reg:x3; val_offset:40908*0 + 3*580*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40908*0 + 3*580*FLEN/8, x4, x1, x2)

inst_13637:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x3; valaddr_reg:x3; val_offset:40911*0 + 3*581*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40911*0 + 3*581*FLEN/8, x4, x1, x2)

inst_13638:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x7; valaddr_reg:x3; val_offset:40914*0 + 3*582*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40914*0 + 3*582*FLEN/8, x4, x1, x2)

inst_13639:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x199999; valaddr_reg:x3; val_offset:40917*0 + 3*583*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40917*0 + 3*583*FLEN/8, x4, x1, x2)

inst_13640:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x249249; valaddr_reg:x3; val_offset:40920*0 + 3*584*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40920*0 + 3*584*FLEN/8, x4, x1, x2)

inst_13641:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x333333; valaddr_reg:x3; val_offset:40923*0 + 3*585*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40923*0 + 3*585*FLEN/8, x4, x1, x2)

inst_13642:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x36db6d; valaddr_reg:x3; val_offset:40926*0 + 3*586*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40926*0 + 3*586*FLEN/8, x4, x1, x2)

inst_13643:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x3bbbbb; valaddr_reg:x3; val_offset:40929*0 + 3*587*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40929*0 + 3*587*FLEN/8, x4, x1, x2)

inst_13644:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x444444; valaddr_reg:x3; val_offset:40932*0 + 3*588*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40932*0 + 3*588*FLEN/8, x4, x1, x2)

inst_13645:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x4ccccc; valaddr_reg:x3; val_offset:40935*0 + 3*589*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40935*0 + 3*589*FLEN/8, x4, x1, x2)

inst_13646:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x5b6db6; valaddr_reg:x3; val_offset:40938*0 + 3*590*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40938*0 + 3*590*FLEN/8, x4, x1, x2)

inst_13647:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x666666; valaddr_reg:x3; val_offset:40941*0 + 3*591*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40941*0 + 3*591*FLEN/8, x4, x1, x2)

inst_13648:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x6db6db; valaddr_reg:x3; val_offset:40944*0 + 3*592*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40944*0 + 3*592*FLEN/8, x4, x1, x2)

inst_13649:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x7ffff8; valaddr_reg:x3; val_offset:40947*0 + 3*593*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40947*0 + 3*593*FLEN/8, x4, x1, x2)

inst_13650:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x7ffffc; valaddr_reg:x3; val_offset:40950*0 + 3*594*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40950*0 + 3*594*FLEN/8, x4, x1, x2)

inst_13651:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x7ffffe; valaddr_reg:x3; val_offset:40953*0 + 3*595*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40953*0 + 3*595*FLEN/8, x4, x1, x2)

inst_13652:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x2000000; valaddr_reg:x3; val_offset:40956*0 + 3*596*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40956*0 + 3*596*FLEN/8, x4, x1, x2)

inst_13653:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x2000001; valaddr_reg:x3; val_offset:40959*0 + 3*597*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40959*0 + 3*597*FLEN/8, x4, x1, x2)

inst_13654:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x2000003; valaddr_reg:x3; val_offset:40962*0 + 3*598*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40962*0 + 3*598*FLEN/8, x4, x1, x2)

inst_13655:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x2000007; valaddr_reg:x3; val_offset:40965*0 + 3*599*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40965*0 + 3*599*FLEN/8, x4, x1, x2)

inst_13656:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x200000f; valaddr_reg:x3; val_offset:40968*0 + 3*600*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40968*0 + 3*600*FLEN/8, x4, x1, x2)

inst_13657:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x200001f; valaddr_reg:x3; val_offset:40971*0 + 3*601*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40971*0 + 3*601*FLEN/8, x4, x1, x2)

inst_13658:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x200003f; valaddr_reg:x3; val_offset:40974*0 + 3*602*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40974*0 + 3*602*FLEN/8, x4, x1, x2)

inst_13659:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x200007f; valaddr_reg:x3; val_offset:40977*0 + 3*603*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40977*0 + 3*603*FLEN/8, x4, x1, x2)

inst_13660:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x20000ff; valaddr_reg:x3; val_offset:40980*0 + 3*604*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40980*0 + 3*604*FLEN/8, x4, x1, x2)

inst_13661:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x20001ff; valaddr_reg:x3; val_offset:40983*0 + 3*605*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40983*0 + 3*605*FLEN/8, x4, x1, x2)

inst_13662:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x20003ff; valaddr_reg:x3; val_offset:40986*0 + 3*606*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40986*0 + 3*606*FLEN/8, x4, x1, x2)

inst_13663:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x20007ff; valaddr_reg:x3; val_offset:40989*0 + 3*607*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40989*0 + 3*607*FLEN/8, x4, x1, x2)

inst_13664:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x2000fff; valaddr_reg:x3; val_offset:40992*0 + 3*608*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40992*0 + 3*608*FLEN/8, x4, x1, x2)

inst_13665:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x2001fff; valaddr_reg:x3; val_offset:40995*0 + 3*609*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40995*0 + 3*609*FLEN/8, x4, x1, x2)

inst_13666:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x2003fff; valaddr_reg:x3; val_offset:40998*0 + 3*610*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 40998*0 + 3*610*FLEN/8, x4, x1, x2)

inst_13667:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x2007fff; valaddr_reg:x3; val_offset:41001*0 + 3*611*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41001*0 + 3*611*FLEN/8, x4, x1, x2)

inst_13668:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x200ffff; valaddr_reg:x3; val_offset:41004*0 + 3*612*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41004*0 + 3*612*FLEN/8, x4, x1, x2)

inst_13669:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x201ffff; valaddr_reg:x3; val_offset:41007*0 + 3*613*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41007*0 + 3*613*FLEN/8, x4, x1, x2)

inst_13670:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x203ffff; valaddr_reg:x3; val_offset:41010*0 + 3*614*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41010*0 + 3*614*FLEN/8, x4, x1, x2)

inst_13671:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x207ffff; valaddr_reg:x3; val_offset:41013*0 + 3*615*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41013*0 + 3*615*FLEN/8, x4, x1, x2)

inst_13672:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x20fffff; valaddr_reg:x3; val_offset:41016*0 + 3*616*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41016*0 + 3*616*FLEN/8, x4, x1, x2)

inst_13673:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x21fffff; valaddr_reg:x3; val_offset:41019*0 + 3*617*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41019*0 + 3*617*FLEN/8, x4, x1, x2)

inst_13674:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x23fffff; valaddr_reg:x3; val_offset:41022*0 + 3*618*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41022*0 + 3*618*FLEN/8, x4, x1, x2)

inst_13675:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x2400000; valaddr_reg:x3; val_offset:41025*0 + 3*619*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41025*0 + 3*619*FLEN/8, x4, x1, x2)

inst_13676:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x2600000; valaddr_reg:x3; val_offset:41028*0 + 3*620*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41028*0 + 3*620*FLEN/8, x4, x1, x2)

inst_13677:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x2700000; valaddr_reg:x3; val_offset:41031*0 + 3*621*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41031*0 + 3*621*FLEN/8, x4, x1, x2)

inst_13678:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x2780000; valaddr_reg:x3; val_offset:41034*0 + 3*622*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41034*0 + 3*622*FLEN/8, x4, x1, x2)

inst_13679:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x27c0000; valaddr_reg:x3; val_offset:41037*0 + 3*623*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41037*0 + 3*623*FLEN/8, x4, x1, x2)

inst_13680:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x27e0000; valaddr_reg:x3; val_offset:41040*0 + 3*624*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41040*0 + 3*624*FLEN/8, x4, x1, x2)

inst_13681:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x27f0000; valaddr_reg:x3; val_offset:41043*0 + 3*625*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41043*0 + 3*625*FLEN/8, x4, x1, x2)

inst_13682:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x27f8000; valaddr_reg:x3; val_offset:41046*0 + 3*626*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41046*0 + 3*626*FLEN/8, x4, x1, x2)

inst_13683:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x27fc000; valaddr_reg:x3; val_offset:41049*0 + 3*627*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41049*0 + 3*627*FLEN/8, x4, x1, x2)

inst_13684:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x27fe000; valaddr_reg:x3; val_offset:41052*0 + 3*628*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41052*0 + 3*628*FLEN/8, x4, x1, x2)

inst_13685:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x27ff000; valaddr_reg:x3; val_offset:41055*0 + 3*629*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41055*0 + 3*629*FLEN/8, x4, x1, x2)

inst_13686:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x27ff800; valaddr_reg:x3; val_offset:41058*0 + 3*630*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41058*0 + 3*630*FLEN/8, x4, x1, x2)

inst_13687:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x27ffc00; valaddr_reg:x3; val_offset:41061*0 + 3*631*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41061*0 + 3*631*FLEN/8, x4, x1, x2)

inst_13688:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x27ffe00; valaddr_reg:x3; val_offset:41064*0 + 3*632*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41064*0 + 3*632*FLEN/8, x4, x1, x2)

inst_13689:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x27fff00; valaddr_reg:x3; val_offset:41067*0 + 3*633*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41067*0 + 3*633*FLEN/8, x4, x1, x2)

inst_13690:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x27fff80; valaddr_reg:x3; val_offset:41070*0 + 3*634*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41070*0 + 3*634*FLEN/8, x4, x1, x2)

inst_13691:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x27fffc0; valaddr_reg:x3; val_offset:41073*0 + 3*635*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41073*0 + 3*635*FLEN/8, x4, x1, x2)

inst_13692:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x27fffe0; valaddr_reg:x3; val_offset:41076*0 + 3*636*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41076*0 + 3*636*FLEN/8, x4, x1, x2)

inst_13693:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x27ffff0; valaddr_reg:x3; val_offset:41079*0 + 3*637*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41079*0 + 3*637*FLEN/8, x4, x1, x2)

inst_13694:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x27ffff8; valaddr_reg:x3; val_offset:41082*0 + 3*638*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41082*0 + 3*638*FLEN/8, x4, x1, x2)

inst_13695:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x27ffffc; valaddr_reg:x3; val_offset:41085*0 + 3*639*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41085*0 + 3*639*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_6)

inst_13696:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x27ffffe; valaddr_reg:x3; val_offset:41088*0 + 3*640*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41088*0 + 3*640*FLEN/8, x4, x1, x2)

inst_13697:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x11c5b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x04 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e91c5b1; op2val:0x0;
op3val:0x27fffff; valaddr_reg:x3; val_offset:41091*0 + 3*641*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41091*0 + 3*641*FLEN/8, x4, x1, x2)

inst_13698:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7d and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbe800000; valaddr_reg:x3; val_offset:41094*0 + 3*642*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41094*0 + 3*642*FLEN/8, x4, x1, x2)

inst_13699:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7d and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbe800001; valaddr_reg:x3; val_offset:41097*0 + 3*643*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41097*0 + 3*643*FLEN/8, x4, x1, x2)

inst_13700:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7d and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbe800003; valaddr_reg:x3; val_offset:41100*0 + 3*644*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41100*0 + 3*644*FLEN/8, x4, x1, x2)

inst_13701:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7d and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbe800007; valaddr_reg:x3; val_offset:41103*0 + 3*645*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41103*0 + 3*645*FLEN/8, x4, x1, x2)

inst_13702:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7d and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbe80000f; valaddr_reg:x3; val_offset:41106*0 + 3*646*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41106*0 + 3*646*FLEN/8, x4, x1, x2)

inst_13703:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7d and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbe80001f; valaddr_reg:x3; val_offset:41109*0 + 3*647*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41109*0 + 3*647*FLEN/8, x4, x1, x2)

inst_13704:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7d and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbe80003f; valaddr_reg:x3; val_offset:41112*0 + 3*648*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41112*0 + 3*648*FLEN/8, x4, x1, x2)

inst_13705:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7d and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbe80007f; valaddr_reg:x3; val_offset:41115*0 + 3*649*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41115*0 + 3*649*FLEN/8, x4, x1, x2)

inst_13706:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7d and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbe8000ff; valaddr_reg:x3; val_offset:41118*0 + 3*650*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41118*0 + 3*650*FLEN/8, x4, x1, x2)

inst_13707:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7d and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbe8001ff; valaddr_reg:x3; val_offset:41121*0 + 3*651*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41121*0 + 3*651*FLEN/8, x4, x1, x2)

inst_13708:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7d and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbe8003ff; valaddr_reg:x3; val_offset:41124*0 + 3*652*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41124*0 + 3*652*FLEN/8, x4, x1, x2)

inst_13709:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7d and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbe8007ff; valaddr_reg:x3; val_offset:41127*0 + 3*653*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41127*0 + 3*653*FLEN/8, x4, x1, x2)

inst_13710:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7d and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbe800fff; valaddr_reg:x3; val_offset:41130*0 + 3*654*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41130*0 + 3*654*FLEN/8, x4, x1, x2)

inst_13711:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7d and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbe801fff; valaddr_reg:x3; val_offset:41133*0 + 3*655*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41133*0 + 3*655*FLEN/8, x4, x1, x2)

inst_13712:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7d and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbe803fff; valaddr_reg:x3; val_offset:41136*0 + 3*656*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41136*0 + 3*656*FLEN/8, x4, x1, x2)

inst_13713:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7d and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbe807fff; valaddr_reg:x3; val_offset:41139*0 + 3*657*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41139*0 + 3*657*FLEN/8, x4, x1, x2)

inst_13714:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7d and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbe80ffff; valaddr_reg:x3; val_offset:41142*0 + 3*658*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41142*0 + 3*658*FLEN/8, x4, x1, x2)

inst_13715:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7d and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbe81ffff; valaddr_reg:x3; val_offset:41145*0 + 3*659*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41145*0 + 3*659*FLEN/8, x4, x1, x2)

inst_13716:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7d and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbe83ffff; valaddr_reg:x3; val_offset:41148*0 + 3*660*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41148*0 + 3*660*FLEN/8, x4, x1, x2)

inst_13717:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7d and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbe87ffff; valaddr_reg:x3; val_offset:41151*0 + 3*661*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41151*0 + 3*661*FLEN/8, x4, x1, x2)

inst_13718:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7d and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbe8fffff; valaddr_reg:x3; val_offset:41154*0 + 3*662*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41154*0 + 3*662*FLEN/8, x4, x1, x2)

inst_13719:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7d and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbe9fffff; valaddr_reg:x3; val_offset:41157*0 + 3*663*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41157*0 + 3*663*FLEN/8, x4, x1, x2)

inst_13720:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7d and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbebfffff; valaddr_reg:x3; val_offset:41160*0 + 3*664*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41160*0 + 3*664*FLEN/8, x4, x1, x2)

inst_13721:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7d and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbec00000; valaddr_reg:x3; val_offset:41163*0 + 3*665*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41163*0 + 3*665*FLEN/8, x4, x1, x2)

inst_13722:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7d and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbee00000; valaddr_reg:x3; val_offset:41166*0 + 3*666*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41166*0 + 3*666*FLEN/8, x4, x1, x2)

inst_13723:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7d and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbef00000; valaddr_reg:x3; val_offset:41169*0 + 3*667*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41169*0 + 3*667*FLEN/8, x4, x1, x2)

inst_13724:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7d and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbef80000; valaddr_reg:x3; val_offset:41172*0 + 3*668*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41172*0 + 3*668*FLEN/8, x4, x1, x2)

inst_13725:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7d and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbefc0000; valaddr_reg:x3; val_offset:41175*0 + 3*669*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41175*0 + 3*669*FLEN/8, x4, x1, x2)

inst_13726:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7d and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbefe0000; valaddr_reg:x3; val_offset:41178*0 + 3*670*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41178*0 + 3*670*FLEN/8, x4, x1, x2)

inst_13727:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7d and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbeff0000; valaddr_reg:x3; val_offset:41181*0 + 3*671*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41181*0 + 3*671*FLEN/8, x4, x1, x2)

inst_13728:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7d and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbeff8000; valaddr_reg:x3; val_offset:41184*0 + 3*672*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41184*0 + 3*672*FLEN/8, x4, x1, x2)

inst_13729:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7d and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbeffc000; valaddr_reg:x3; val_offset:41187*0 + 3*673*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41187*0 + 3*673*FLEN/8, x4, x1, x2)

inst_13730:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7d and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbeffe000; valaddr_reg:x3; val_offset:41190*0 + 3*674*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41190*0 + 3*674*FLEN/8, x4, x1, x2)

inst_13731:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7d and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbefff000; valaddr_reg:x3; val_offset:41193*0 + 3*675*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41193*0 + 3*675*FLEN/8, x4, x1, x2)

inst_13732:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7d and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbefff800; valaddr_reg:x3; val_offset:41196*0 + 3*676*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41196*0 + 3*676*FLEN/8, x4, x1, x2)

inst_13733:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7d and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbefffc00; valaddr_reg:x3; val_offset:41199*0 + 3*677*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41199*0 + 3*677*FLEN/8, x4, x1, x2)

inst_13734:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7d and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbefffe00; valaddr_reg:x3; val_offset:41202*0 + 3*678*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41202*0 + 3*678*FLEN/8, x4, x1, x2)

inst_13735:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7d and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbeffff00; valaddr_reg:x3; val_offset:41205*0 + 3*679*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41205*0 + 3*679*FLEN/8, x4, x1, x2)

inst_13736:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7d and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbeffff80; valaddr_reg:x3; val_offset:41208*0 + 3*680*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41208*0 + 3*680*FLEN/8, x4, x1, x2)

inst_13737:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7d and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbeffffc0; valaddr_reg:x3; val_offset:41211*0 + 3*681*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41211*0 + 3*681*FLEN/8, x4, x1, x2)

inst_13738:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7d and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbeffffe0; valaddr_reg:x3; val_offset:41214*0 + 3*682*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41214*0 + 3*682*FLEN/8, x4, x1, x2)

inst_13739:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7d and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbefffff0; valaddr_reg:x3; val_offset:41217*0 + 3*683*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41217*0 + 3*683*FLEN/8, x4, x1, x2)

inst_13740:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7d and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbefffff8; valaddr_reg:x3; val_offset:41220*0 + 3*684*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41220*0 + 3*684*FLEN/8, x4, x1, x2)

inst_13741:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7d and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbefffffc; valaddr_reg:x3; val_offset:41223*0 + 3*685*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41223*0 + 3*685*FLEN/8, x4, x1, x2)

inst_13742:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7d and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbefffffe; valaddr_reg:x3; val_offset:41226*0 + 3*686*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41226*0 + 3*686*FLEN/8, x4, x1, x2)

inst_13743:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7d and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbeffffff; valaddr_reg:x3; val_offset:41229*0 + 3*687*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41229*0 + 3*687*FLEN/8, x4, x1, x2)

inst_13744:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbf800001; valaddr_reg:x3; val_offset:41232*0 + 3*688*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41232*0 + 3*688*FLEN/8, x4, x1, x2)

inst_13745:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbf800003; valaddr_reg:x3; val_offset:41235*0 + 3*689*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41235*0 + 3*689*FLEN/8, x4, x1, x2)

inst_13746:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbf800007; valaddr_reg:x3; val_offset:41238*0 + 3*690*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41238*0 + 3*690*FLEN/8, x4, x1, x2)

inst_13747:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbf999999; valaddr_reg:x3; val_offset:41241*0 + 3*691*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41241*0 + 3*691*FLEN/8, x4, x1, x2)

inst_13748:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbfa49249; valaddr_reg:x3; val_offset:41244*0 + 3*692*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41244*0 + 3*692*FLEN/8, x4, x1, x2)

inst_13749:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbfb33333; valaddr_reg:x3; val_offset:41247*0 + 3*693*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41247*0 + 3*693*FLEN/8, x4, x1, x2)

inst_13750:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbfb6db6d; valaddr_reg:x3; val_offset:41250*0 + 3*694*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41250*0 + 3*694*FLEN/8, x4, x1, x2)

inst_13751:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbfbbbbbb; valaddr_reg:x3; val_offset:41253*0 + 3*695*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41253*0 + 3*695*FLEN/8, x4, x1, x2)

inst_13752:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbfc44444; valaddr_reg:x3; val_offset:41256*0 + 3*696*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41256*0 + 3*696*FLEN/8, x4, x1, x2)

inst_13753:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbfcccccc; valaddr_reg:x3; val_offset:41259*0 + 3*697*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41259*0 + 3*697*FLEN/8, x4, x1, x2)

inst_13754:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbfdb6db6; valaddr_reg:x3; val_offset:41262*0 + 3*698*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41262*0 + 3*698*FLEN/8, x4, x1, x2)

inst_13755:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbfe66666; valaddr_reg:x3; val_offset:41265*0 + 3*699*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41265*0 + 3*699*FLEN/8, x4, x1, x2)

inst_13756:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbfedb6db; valaddr_reg:x3; val_offset:41268*0 + 3*700*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41268*0 + 3*700*FLEN/8, x4, x1, x2)

inst_13757:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbffffff8; valaddr_reg:x3; val_offset:41271*0 + 3*701*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41271*0 + 3*701*FLEN/8, x4, x1, x2)

inst_13758:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbffffffc; valaddr_reg:x3; val_offset:41274*0 + 3*702*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41274*0 + 3*702*FLEN/8, x4, x1, x2)

inst_13759:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x120226 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x703674 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e920226; op2val:0x80703674;
op3val:0xbffffffe; valaddr_reg:x3; val_offset:41277*0 + 3*703*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41277*0 + 3*703*FLEN/8, x4, x1, x2)

inst_13760:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0x800001; valaddr_reg:x3; val_offset:41280*0 + 3*704*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41280*0 + 3*704*FLEN/8, x4, x1, x2)

inst_13761:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0x800003; valaddr_reg:x3; val_offset:41283*0 + 3*705*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41283*0 + 3*705*FLEN/8, x4, x1, x2)

inst_13762:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0x800007; valaddr_reg:x3; val_offset:41286*0 + 3*706*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41286*0 + 3*706*FLEN/8, x4, x1, x2)

inst_13763:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0x999999; valaddr_reg:x3; val_offset:41289*0 + 3*707*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41289*0 + 3*707*FLEN/8, x4, x1, x2)

inst_13764:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xa49249; valaddr_reg:x3; val_offset:41292*0 + 3*708*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41292*0 + 3*708*FLEN/8, x4, x1, x2)

inst_13765:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xb33333; valaddr_reg:x3; val_offset:41295*0 + 3*709*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41295*0 + 3*709*FLEN/8, x4, x1, x2)

inst_13766:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xb6db6d; valaddr_reg:x3; val_offset:41298*0 + 3*710*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41298*0 + 3*710*FLEN/8, x4, x1, x2)

inst_13767:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xbbbbbb; valaddr_reg:x3; val_offset:41301*0 + 3*711*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41301*0 + 3*711*FLEN/8, x4, x1, x2)

inst_13768:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xc44444; valaddr_reg:x3; val_offset:41304*0 + 3*712*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41304*0 + 3*712*FLEN/8, x4, x1, x2)

inst_13769:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xcccccc; valaddr_reg:x3; val_offset:41307*0 + 3*713*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41307*0 + 3*713*FLEN/8, x4, x1, x2)

inst_13770:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xdb6db6; valaddr_reg:x3; val_offset:41310*0 + 3*714*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41310*0 + 3*714*FLEN/8, x4, x1, x2)

inst_13771:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xe66666; valaddr_reg:x3; val_offset:41313*0 + 3*715*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41313*0 + 3*715*FLEN/8, x4, x1, x2)

inst_13772:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xedb6db; valaddr_reg:x3; val_offset:41316*0 + 3*716*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41316*0 + 3*716*FLEN/8, x4, x1, x2)

inst_13773:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xfffff8; valaddr_reg:x3; val_offset:41319*0 + 3*717*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41319*0 + 3*717*FLEN/8, x4, x1, x2)

inst_13774:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xfffffc; valaddr_reg:x3; val_offset:41322*0 + 3*718*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41322*0 + 3*718*FLEN/8, x4, x1, x2)

inst_13775:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xfffffe; valaddr_reg:x3; val_offset:41325*0 + 3*719*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41325*0 + 3*719*FLEN/8, x4, x1, x2)

inst_13776:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xf800000; valaddr_reg:x3; val_offset:41328*0 + 3*720*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41328*0 + 3*720*FLEN/8, x4, x1, x2)

inst_13777:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xf800001; valaddr_reg:x3; val_offset:41331*0 + 3*721*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41331*0 + 3*721*FLEN/8, x4, x1, x2)

inst_13778:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xf800003; valaddr_reg:x3; val_offset:41334*0 + 3*722*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41334*0 + 3*722*FLEN/8, x4, x1, x2)

inst_13779:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xf800007; valaddr_reg:x3; val_offset:41337*0 + 3*723*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41337*0 + 3*723*FLEN/8, x4, x1, x2)

inst_13780:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xf80000f; valaddr_reg:x3; val_offset:41340*0 + 3*724*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41340*0 + 3*724*FLEN/8, x4, x1, x2)

inst_13781:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xf80001f; valaddr_reg:x3; val_offset:41343*0 + 3*725*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41343*0 + 3*725*FLEN/8, x4, x1, x2)

inst_13782:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xf80003f; valaddr_reg:x3; val_offset:41346*0 + 3*726*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41346*0 + 3*726*FLEN/8, x4, x1, x2)

inst_13783:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xf80007f; valaddr_reg:x3; val_offset:41349*0 + 3*727*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41349*0 + 3*727*FLEN/8, x4, x1, x2)

inst_13784:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xf8000ff; valaddr_reg:x3; val_offset:41352*0 + 3*728*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41352*0 + 3*728*FLEN/8, x4, x1, x2)

inst_13785:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xf8001ff; valaddr_reg:x3; val_offset:41355*0 + 3*729*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41355*0 + 3*729*FLEN/8, x4, x1, x2)

inst_13786:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xf8003ff; valaddr_reg:x3; val_offset:41358*0 + 3*730*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41358*0 + 3*730*FLEN/8, x4, x1, x2)

inst_13787:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xf8007ff; valaddr_reg:x3; val_offset:41361*0 + 3*731*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41361*0 + 3*731*FLEN/8, x4, x1, x2)

inst_13788:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xf800fff; valaddr_reg:x3; val_offset:41364*0 + 3*732*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41364*0 + 3*732*FLEN/8, x4, x1, x2)

inst_13789:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xf801fff; valaddr_reg:x3; val_offset:41367*0 + 3*733*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41367*0 + 3*733*FLEN/8, x4, x1, x2)

inst_13790:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xf803fff; valaddr_reg:x3; val_offset:41370*0 + 3*734*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41370*0 + 3*734*FLEN/8, x4, x1, x2)

inst_13791:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xf807fff; valaddr_reg:x3; val_offset:41373*0 + 3*735*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41373*0 + 3*735*FLEN/8, x4, x1, x2)

inst_13792:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xf80ffff; valaddr_reg:x3; val_offset:41376*0 + 3*736*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41376*0 + 3*736*FLEN/8, x4, x1, x2)

inst_13793:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xf81ffff; valaddr_reg:x3; val_offset:41379*0 + 3*737*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41379*0 + 3*737*FLEN/8, x4, x1, x2)

inst_13794:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xf83ffff; valaddr_reg:x3; val_offset:41382*0 + 3*738*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41382*0 + 3*738*FLEN/8, x4, x1, x2)

inst_13795:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xf87ffff; valaddr_reg:x3; val_offset:41385*0 + 3*739*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41385*0 + 3*739*FLEN/8, x4, x1, x2)

inst_13796:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xf8fffff; valaddr_reg:x3; val_offset:41388*0 + 3*740*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41388*0 + 3*740*FLEN/8, x4, x1, x2)

inst_13797:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xf9fffff; valaddr_reg:x3; val_offset:41391*0 + 3*741*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41391*0 + 3*741*FLEN/8, x4, x1, x2)

inst_13798:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xfbfffff; valaddr_reg:x3; val_offset:41394*0 + 3*742*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41394*0 + 3*742*FLEN/8, x4, x1, x2)

inst_13799:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xfc00000; valaddr_reg:x3; val_offset:41397*0 + 3*743*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41397*0 + 3*743*FLEN/8, x4, x1, x2)

inst_13800:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xfe00000; valaddr_reg:x3; val_offset:41400*0 + 3*744*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41400*0 + 3*744*FLEN/8, x4, x1, x2)

inst_13801:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xff00000; valaddr_reg:x3; val_offset:41403*0 + 3*745*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41403*0 + 3*745*FLEN/8, x4, x1, x2)

inst_13802:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xff80000; valaddr_reg:x3; val_offset:41406*0 + 3*746*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41406*0 + 3*746*FLEN/8, x4, x1, x2)

inst_13803:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xffc0000; valaddr_reg:x3; val_offset:41409*0 + 3*747*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41409*0 + 3*747*FLEN/8, x4, x1, x2)

inst_13804:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xffe0000; valaddr_reg:x3; val_offset:41412*0 + 3*748*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41412*0 + 3*748*FLEN/8, x4, x1, x2)

inst_13805:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xfff0000; valaddr_reg:x3; val_offset:41415*0 + 3*749*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41415*0 + 3*749*FLEN/8, x4, x1, x2)

inst_13806:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xfff8000; valaddr_reg:x3; val_offset:41418*0 + 3*750*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41418*0 + 3*750*FLEN/8, x4, x1, x2)

inst_13807:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xfffc000; valaddr_reg:x3; val_offset:41421*0 + 3*751*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41421*0 + 3*751*FLEN/8, x4, x1, x2)

inst_13808:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xfffe000; valaddr_reg:x3; val_offset:41424*0 + 3*752*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41424*0 + 3*752*FLEN/8, x4, x1, x2)

inst_13809:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xffff000; valaddr_reg:x3; val_offset:41427*0 + 3*753*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41427*0 + 3*753*FLEN/8, x4, x1, x2)

inst_13810:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xffff800; valaddr_reg:x3; val_offset:41430*0 + 3*754*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41430*0 + 3*754*FLEN/8, x4, x1, x2)

inst_13811:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xffffc00; valaddr_reg:x3; val_offset:41433*0 + 3*755*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41433*0 + 3*755*FLEN/8, x4, x1, x2)

inst_13812:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xffffe00; valaddr_reg:x3; val_offset:41436*0 + 3*756*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41436*0 + 3*756*FLEN/8, x4, x1, x2)

inst_13813:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xfffff00; valaddr_reg:x3; val_offset:41439*0 + 3*757*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41439*0 + 3*757*FLEN/8, x4, x1, x2)

inst_13814:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xfffff80; valaddr_reg:x3; val_offset:41442*0 + 3*758*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41442*0 + 3*758*FLEN/8, x4, x1, x2)

inst_13815:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xfffffc0; valaddr_reg:x3; val_offset:41445*0 + 3*759*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41445*0 + 3*759*FLEN/8, x4, x1, x2)

inst_13816:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xfffffe0; valaddr_reg:x3; val_offset:41448*0 + 3*760*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41448*0 + 3*760*FLEN/8, x4, x1, x2)

inst_13817:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xffffff0; valaddr_reg:x3; val_offset:41451*0 + 3*761*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41451*0 + 3*761*FLEN/8, x4, x1, x2)

inst_13818:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xffffff8; valaddr_reg:x3; val_offset:41454*0 + 3*762*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41454*0 + 3*762*FLEN/8, x4, x1, x2)

inst_13819:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xffffffc; valaddr_reg:x3; val_offset:41457*0 + 3*763*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41457*0 + 3*763*FLEN/8, x4, x1, x2)

inst_13820:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xffffffe; valaddr_reg:x3; val_offset:41460*0 + 3*764*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41460*0 + 3*764*FLEN/8, x4, x1, x2)

inst_13821:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x12d2db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e92d2db; op2val:0x0;
op3val:0xfffffff; valaddr_reg:x3; val_offset:41463*0 + 3*765*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41463*0 + 3*765*FLEN/8, x4, x1, x2)

inst_13822:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x135639 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x6f3374 and fs3 == 0 and fe3 == 0x4f and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e935639; op2val:0x6f3374;
op3val:0x27800000; valaddr_reg:x3; val_offset:41466*0 + 3*766*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41466*0 + 3*766*FLEN/8, x4, x1, x2)

inst_13823:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x135639 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x6f3374 and fs3 == 0 and fe3 == 0x4f and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmadd.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e935639; op2val:0x6f3374;
op3val:0x27800001; valaddr_reg:x3; val_offset:41469*0 + 3*767*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.s, f31, f30, f29, f28, dyn, 0, 0, x3, 41469*0 + 3*767*FLEN/8, x4, x1, x2)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0x7e89edf2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89600000,32,FLEN)
NAN_BOXED(0x7e89edf2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89700000,32,FLEN)
NAN_BOXED(0x7e89edf2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x89780000,32,FLEN)
NAN_BOXED(0x7e89edf2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x897c0000,32,FLEN)
NAN_BOXED(0x7e89edf2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x897e0000,32,FLEN)
NAN_BOXED(0x7e89edf2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x897f0000,32,FLEN)
NAN_BOXED(0x7e89edf2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x897f8000,32,FLEN)
NAN_BOXED(0x7e89edf2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x897fc000,32,FLEN)
NAN_BOXED(0x7e89edf2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x897fe000,32,FLEN)
NAN_BOXED(0x7e89edf2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x897ff000,32,FLEN)
NAN_BOXED(0x7e89edf2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x897ff800,32,FLEN)
NAN_BOXED(0x7e89edf2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x897ffc00,32,FLEN)
NAN_BOXED(0x7e89edf2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x897ffe00,32,FLEN)
NAN_BOXED(0x7e89edf2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x897fff00,32,FLEN)
NAN_BOXED(0x7e89edf2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x897fff80,32,FLEN)
NAN_BOXED(0x7e89edf2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x897fffc0,32,FLEN)
NAN_BOXED(0x7e89edf2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x897fffe0,32,FLEN)
NAN_BOXED(0x7e89edf2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x897ffff0,32,FLEN)
NAN_BOXED(0x7e89edf2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x897ffff8,32,FLEN)
NAN_BOXED(0x7e89edf2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x897ffffc,32,FLEN)
NAN_BOXED(0x7e89edf2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x897ffffe,32,FLEN)
NAN_BOXED(0x7e89edf2,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x897fffff,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x71800000,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x71800001,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x71800003,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x71800007,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x7180000f,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x7180001f,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x7180003f,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x7180007f,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x718000ff,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x718001ff,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x718003ff,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x718007ff,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x71800fff,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x71801fff,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x71803fff,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x71807fff,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x7180ffff,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x7181ffff,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x7183ffff,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x7187ffff,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x718fffff,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x719fffff,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x71bfffff,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x71c00000,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x71e00000,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x71f00000,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x71f80000,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x71fc0000,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x71fe0000,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x71ff0000,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x71ff8000,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x71ffc000,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x71ffe000,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x71fff000,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x71fff800,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x71fffc00,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x71fffe00,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x71ffff00,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x71ffff80,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x71ffffc0,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x71ffffe0,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x71fffff0,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x71fffff8,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x71fffffc,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x71fffffe,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x71ffffff,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x7f000001,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x7f000003,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x7f000007,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x7f199999,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x7f249249,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x7f333333,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x7f36db6d,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x7f3bbbbb,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x7f444444,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x7f4ccccc,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x7f5b6db6,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x7f666666,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x7f6db6db,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x7f7ffff8,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x7f7ffffc,32,FLEN)
NAN_BOXED(0x7e8a049f,32,FLEN)
NAN_BOXED(0x406d6b0f,32,FLEN)
NAN_BOXED(0x7f7ffffe,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x2c800000,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x2c800001,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x2c800003,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x2c800007,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x2c80000f,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x2c80001f,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x2c80003f,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x2c80007f,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x2c8000ff,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x2c8001ff,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x2c8003ff,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x2c8007ff,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x2c800fff,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x2c801fff,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x2c803fff,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x2c807fff,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x2c80ffff,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x2c81ffff,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x2c83ffff,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x2c87ffff,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x2c8fffff,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x2c9fffff,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x2cbfffff,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x2cc00000,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x2ce00000,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x2cf00000,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x2cf80000,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x2cfc0000,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x2cfe0000,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x2cff0000,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x2cff8000,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x2cffc000,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x2cffe000,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x2cfff000,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x2cfff800,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x2cfffc00,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x2cfffe00,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x2cffff00,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x2cffff80,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x2cffffc0,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x2cffffe0,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x2cfffff0,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x2cfffff8,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x2cfffffc,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x2cfffffe,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x2cffffff,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x3f800001,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x3f800003,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x3f800007,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x3f999999,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x3fa49249,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x3fb33333,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x3fb6db6d,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x3fbbbbbb,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x3fc44444,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x3fcccccc,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x3fdb6db6,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x3fe66666,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x3fedb6db,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x3ffffff8,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x3ffffffc,32,FLEN)
NAN_BOXED(0x7e8c0f02,32,FLEN)
NAN_BOXED(0x74fac5,32,FLEN)
NAN_BOXED(0x3ffffffe,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xbf800001,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xbf800003,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xbf800007,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xbf999999,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xbfa49249,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xbfb33333,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xbfb6db6d,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xbfbbbbbb,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xbfc44444,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xbfcccccc,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xbfdb6db6,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xbfe66666,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xbfedb6db,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xbffffff8,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xbffffffc,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xbffffffe,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xc4000000,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xc4000001,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xc4000003,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xc4000007,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xc400000f,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xc400001f,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xc400003f,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xc400007f,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xc40000ff,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xc40001ff,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xc40003ff,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xc40007ff,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xc4000fff,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xc4001fff,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xc4003fff,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xc4007fff,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xc400ffff,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xc401ffff,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xc403ffff,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xc407ffff,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xc40fffff,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xc41fffff,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xc43fffff,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xc4400000,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xc4600000,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xc4700000,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xc4780000,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xc47c0000,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xc47e0000,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xc47f0000,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xc47f8000,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xc47fc000,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xc47fe000,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xc47ff000,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xc47ff800,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xc47ffc00,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xc47ffe00,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xc47fff00,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xc47fff80,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xc47fffc0,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xc47fffe0,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xc47ffff0,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xc47ffff8,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xc47ffffc,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xc47ffffe,32,FLEN)
NAN_BOXED(0x7e8c1e52,32,FLEN)
NAN_BOXED(0x8074edfd,32,FLEN)
NAN_BOXED(0xc47fffff,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000001,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000003,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000007,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80199999,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80249249,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80333333,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8036db6d,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x803bbbbb,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80444444,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x804ccccc,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x805b6db6,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80666666,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x806db6db,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffff8,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffc,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffe,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8b000000,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8b000001,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8b000003,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8b000007,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8b00000f,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8b00001f,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8b00003f,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8b00007f,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8b0000ff,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8b0001ff,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8b0003ff,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8b0007ff,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8b000fff,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8b001fff,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8b003fff,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8b007fff,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8b00ffff,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8b01ffff,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8b03ffff,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8b07ffff,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8b0fffff,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8b1fffff,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8b3fffff,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8b400000,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8b600000,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8b700000,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8b780000,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8b7c0000,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8b7e0000,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8b7f0000,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8b7f8000,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8b7fc000,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8b7fe000,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8b7ff000,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8b7ff800,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8b7ffc00,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8b7ffe00,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8b7fff00,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8b7fff80,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8b7fffc0,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8b7fffe0,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8b7ffff0,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8b7ffff8,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8b7ffffc,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8b7ffffe,32,FLEN)
NAN_BOXED(0x7e8cf9bd,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8b7fffff,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000001,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000003,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000007,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80199999,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80249249,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80333333,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8036db6d,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x803bbbbb,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80444444,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x804ccccc,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x805b6db6,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80666666,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x806db6db,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffff8,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffc,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffe,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c800000,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c800001,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c800003,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c800007,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c80000f,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c80001f,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c80003f,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c80007f,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c8000ff,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c8001ff,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c8003ff,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c8007ff,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c800fff,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c801fff,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c803fff,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c807fff,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c80ffff,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c81ffff,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c83ffff,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c87ffff,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c8fffff,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c9fffff,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8cbfffff,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8cc00000,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8ce00000,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8cf00000,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8cf80000,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8cfc0000,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8cfe0000,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8cff0000,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8cff8000,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8cffc000,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8cffe000,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8cfff000,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8cfff800,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8cfffc00,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8cfffe00,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8cffff00,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8cffff80,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8cffffc0,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8cffffe0,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8cfffff0,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8cfffff8,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8cfffffc,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8cfffffe,32,FLEN)
NAN_BOXED(0x7e8d93b6,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8cffffff,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000001,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000003,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000007,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80199999,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80249249,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80333333,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8036db6d,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x803bbbbb,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80444444,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x804ccccc,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x805b6db6,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80666666,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x806db6db,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffff8,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffc,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffe,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8f800000,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8f800001,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8f800003,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8f800007,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8f80000f,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8f80001f,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8f80003f,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8f80007f,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8f8000ff,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8f8001ff,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8f8003ff,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8f8007ff,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8f800fff,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8f801fff,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8f803fff,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8f807fff,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8f80ffff,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8f81ffff,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8f83ffff,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8f87ffff,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8f8fffff,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8f9fffff,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8fbfffff,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8fc00000,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8fe00000,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8ff00000,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8ff80000,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8ffc0000,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8ffe0000,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8fff0000,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8fff8000,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8fffc000,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8fffe000,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8ffff000,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8ffff800,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8ffffc00,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8ffffe00,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8fffff00,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8fffff80,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8fffffc0,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8fffffe0,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8ffffff0,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8ffffff8,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8ffffffc,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8ffffffe,32,FLEN)
NAN_BOXED(0x7e8e47db,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8fffffff,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x68800000,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x68800001,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x68800003,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x68800007,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x6880000f,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x6880001f,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x6880003f,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x6880007f,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x688000ff,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x688001ff,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x688003ff,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x688007ff,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x68800fff,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x68801fff,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x68803fff,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x68807fff,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x6880ffff,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x6881ffff,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x6883ffff,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x6887ffff,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x688fffff,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x689fffff,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x68bfffff,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x68c00000,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x68e00000,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x68f00000,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x68f80000,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x68fc0000,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x68fe0000,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x68ff0000,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x68ff8000,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x68ffc000,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x68ffe000,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x68fff000,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x68fff800,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x68fffc00,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x68fffe00,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x68ffff00,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x68ffff80,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x68ffffc0,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x68ffffe0,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x68fffff0,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x68fffff8,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x68fffffc,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x68fffffe,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x68ffffff,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x7f000001,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x7f000003,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x7f000007,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x7f199999,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x7f249249,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x7f333333,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x7f36db6d,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x7f3bbbbb,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x7f444444,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x7f4ccccc,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x7f5b6db6,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x7f666666,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x7f6db6db,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x7f7ffff8,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x7f7ffffc,32,FLEN)
NAN_BOXED(0x7e90fb7b,32,FLEN)
NAN_BOXED(0x40620382,32,FLEN)
NAN_BOXED(0x7f7ffffe,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80800001,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80800003,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80800007,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80999999,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80a49249,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80b33333,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80b6db6d,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80bbbbbb,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80c44444,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80cccccc,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80db6db6,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80e66666,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80edb6db,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80fffff8,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80fffffc,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80fffffe,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x84000000,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x84000001,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x84000003,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x84000007,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8400000f,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8400001f,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8400003f,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8400007f,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x840000ff,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x840001ff,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x840003ff,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x840007ff,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x84000fff,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x84001fff,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x84003fff,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x84007fff,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8400ffff,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8401ffff,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8403ffff,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8407ffff,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x840fffff,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x841fffff,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x843fffff,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x84400000,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x84600000,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x84700000,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x84780000,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x847c0000,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x847e0000,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x847f0000,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x847f8000,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x847fc000,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x847fe000,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x847ff000,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x847ff800,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x847ffc00,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x847ffe00,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x847fff00,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x847fff80,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x847fffc0,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x847fffe0,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x847ffff0,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x847ffff8,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x847ffffc,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x847ffffe,32,FLEN)
NAN_BOXED(0x7e917a6b,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x847fffff,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xb1000000,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xb1000001,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xb1000003,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xb1000007,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xb100000f,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xb100001f,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xb100003f,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xb100007f,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xb10000ff,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xb10001ff,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xb10003ff,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xb10007ff,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xb1000fff,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xb1001fff,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xb1003fff,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xb1007fff,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xb100ffff,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xb101ffff,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xb103ffff,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xb107ffff,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xb10fffff,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xb11fffff,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xb13fffff,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xb1400000,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xb1600000,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xb1700000,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xb1780000,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xb17c0000,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xb17e0000,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xb17f0000,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xb17f8000,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xb17fc000,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xb17fe000,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xb17ff000,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xb17ff800,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xb17ffc00,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xb17ffe00,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xb17fff00,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xb17fff80,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xb17fffc0,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xb17fffe0,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xb17ffff0,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xb17ffff8,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xb17ffffc,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xb17ffffe,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xb17fffff,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xbf800001,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xbf800003,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xbf800007,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xbf999999,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xbfa49249,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xbfb33333,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xbfb6db6d,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xbfbbbbbb,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xbfc44444,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xbfcccccc,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xbfdb6db6,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xbfe66666,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xbfedb6db,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xbffffff8,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xbffffffc,32,FLEN)
NAN_BOXED(0x7e91a030,32,FLEN)
NAN_BOXED(0x807081f1,32,FLEN)
NAN_BOXED(0xbffffffe,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x199999,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x249249,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x333333,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x36db6d,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3bbbbb,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x444444,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4ccccc,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5b6db6,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x666666,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6db6db,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffff8,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffc,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffe,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2000000,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2000001,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2000003,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2000007,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x200000f,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x200001f,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x200003f,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x200007f,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x20000ff,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x20001ff,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x20003ff,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x20007ff,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2000fff,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2001fff,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2003fff,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2007fff,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x200ffff,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x201ffff,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x203ffff,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x207ffff,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x20fffff,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x21fffff,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x23fffff,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2400000,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2600000,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2700000,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2780000,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x27c0000,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x27e0000,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x27f0000,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x27f8000,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x27fc000,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x27fe000,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x27ff000,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x27ff800,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x27ffc00,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x27ffe00,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x27fff00,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x27fff80,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x27fffc0,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x27fffe0,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x27ffff0,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x27ffff8,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x27ffffc,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x27ffffe,32,FLEN)
NAN_BOXED(0x7e91c5b1,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x27fffff,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbe800000,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbe800001,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbe800003,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbe800007,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbe80000f,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbe80001f,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbe80003f,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbe80007f,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbe8000ff,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbe8001ff,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbe8003ff,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbe8007ff,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbe800fff,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbe801fff,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbe803fff,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbe807fff,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbe80ffff,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbe81ffff,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbe83ffff,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbe87ffff,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbe8fffff,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbe9fffff,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbebfffff,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbec00000,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbee00000,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbef00000,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbef80000,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbefc0000,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbefe0000,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbeff0000,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbeff8000,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbeffc000,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbeffe000,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbefff000,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbefff800,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbefffc00,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbefffe00,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbeffff00,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbeffff80,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbeffffc0,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbeffffe0,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbefffff0,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbefffff8,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbefffffc,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbefffffe,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbeffffff,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbf800001,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbf800003,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbf800007,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbf999999,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbfa49249,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbfb33333,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbfb6db6d,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbfbbbbbb,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbfc44444,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbfcccccc,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbfdb6db6,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbfe66666,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbfedb6db,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbffffff8,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbffffffc,32,FLEN)
NAN_BOXED(0x7e920226,32,FLEN)
NAN_BOXED(0x80703674,32,FLEN)
NAN_BOXED(0xbffffffe,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800001,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800003,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800007,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x999999,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa49249,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb33333,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb6db6d,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbbbbbb,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xc44444,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xcccccc,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xdb6db6,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe66666,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xedb6db,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffff8,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffffc,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffffe,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf800000,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf800001,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf800003,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf800007,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf80000f,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf80001f,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf80003f,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf80007f,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf8000ff,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf8001ff,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf8003ff,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf8007ff,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf800fff,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf801fff,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf803fff,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf807fff,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf80ffff,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf81ffff,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf83ffff,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf87ffff,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf8fffff,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xf9fffff,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfbfffff,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfc00000,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfe00000,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xff00000,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xff80000,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xffc0000,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xffe0000,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfff0000,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfff8000,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffc000,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffe000,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xffff000,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xffff800,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xffffc00,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xffffe00,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffff00,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffff80,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffffc0,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffffe0,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xffffff0,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xffffff8,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xffffffc,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xffffffe,32,FLEN)
NAN_BOXED(0x7e92d2db,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffffff,32,FLEN)
NAN_BOXED(0x7e935639,32,FLEN)
NAN_BOXED(0x6f3374,32,FLEN)
NAN_BOXED(0x27800000,32,FLEN)
NAN_BOXED(0x7e935639,32,FLEN)
NAN_BOXED(0x6f3374,32,FLEN)
NAN_BOXED(0x27800001,32,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;


signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_2:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_3:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_4:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_5:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_6:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine

tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
    .fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;

#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif

sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
