
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.7.1
// timestamp : Fri Jun 17 14:18:08 2022 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /scratch/pawan/work/normalised/RV32F/fnmsub.s.cgf \
 \
//                  -- xlen 32  \
//                  --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fnmsub.s instruction of the RISC-V RV32F_Zicsr,RV32FD_Zicsr,RV64F_Zicsr,RV64FD_Zicsr extension for the fnmsub_b15 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*);def TEST_CASE_1=True;",fnmsub_b15)
RVTEST_CASE(1,"//check ISA:=regex(.*E.*F.*);def TEST_CASE_1=True;",fnmsub_b15)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_11520:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x71e169 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e71e169; op2val:0x0;
op3val:0x333333; valaddr_reg:x3; val_offset:34560*0 + 3*-1*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34560*0 + 3*0*FLEN/8, x4, x1, x2)

inst_11521:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x71e169 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e71e169; op2val:0x0;
op3val:0x36db6d; valaddr_reg:x3; val_offset:34563*0 + 3*0*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34563*0 + 3*1*FLEN/8, x4, x1, x2)

inst_11522:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x71e169 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e71e169; op2val:0x0;
op3val:0x3bbbbb; valaddr_reg:x3; val_offset:34566*0 + 3*1*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34566*0 + 3*2*FLEN/8, x4, x1, x2)

inst_11523:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x71e169 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e71e169; op2val:0x0;
op3val:0x3fffff; valaddr_reg:x3; val_offset:34569*0 + 3*2*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34569*0 + 3*3*FLEN/8, x4, x1, x2)

inst_11524:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x71e169 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e71e169; op2val:0x0;
op3val:0x400000; valaddr_reg:x3; val_offset:34572*0 + 3*3*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34572*0 + 3*4*FLEN/8, x4, x1, x2)

inst_11525:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x71e169 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e71e169; op2val:0x0;
op3val:0x444444; valaddr_reg:x3; val_offset:34575*0 + 3*4*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34575*0 + 3*5*FLEN/8, x4, x1, x2)

inst_11526:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x71e169 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e71e169; op2val:0x0;
op3val:0x4ccccc; valaddr_reg:x3; val_offset:34578*0 + 3*5*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34578*0 + 3*6*FLEN/8, x4, x1, x2)

inst_11527:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x71e169 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e71e169; op2val:0x0;
op3val:0x5b6db6; valaddr_reg:x3; val_offset:34581*0 + 3*6*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34581*0 + 3*7*FLEN/8, x4, x1, x2)

inst_11528:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x71e169 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e71e169; op2val:0x0;
op3val:0x600000; valaddr_reg:x3; val_offset:34584*0 + 3*7*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34584*0 + 3*8*FLEN/8, x4, x1, x2)

inst_11529:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x71e169 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e71e169; op2val:0x0;
op3val:0x666666; valaddr_reg:x3; val_offset:34587*0 + 3*8*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34587*0 + 3*9*FLEN/8, x4, x1, x2)

inst_11530:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x71e169 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e71e169; op2val:0x0;
op3val:0x6db6db; valaddr_reg:x3; val_offset:34590*0 + 3*9*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34590*0 + 3*10*FLEN/8, x4, x1, x2)

inst_11531:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x71e169 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e71e169; op2val:0x0;
op3val:0x700000; valaddr_reg:x3; val_offset:34593*0 + 3*10*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34593*0 + 3*11*FLEN/8, x4, x1, x2)

inst_11532:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x71e169 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e71e169; op2val:0x0;
op3val:0x780000; valaddr_reg:x3; val_offset:34596*0 + 3*11*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34596*0 + 3*12*FLEN/8, x4, x1, x2)

inst_11533:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x71e169 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e71e169; op2val:0x0;
op3val:0x7c0000; valaddr_reg:x3; val_offset:34599*0 + 3*12*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34599*0 + 3*13*FLEN/8, x4, x1, x2)

inst_11534:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x71e169 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e71e169; op2val:0x0;
op3val:0x7e0000; valaddr_reg:x3; val_offset:34602*0 + 3*13*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34602*0 + 3*14*FLEN/8, x4, x1, x2)

inst_11535:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x71e169 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e71e169; op2val:0x0;
op3val:0x7f0000; valaddr_reg:x3; val_offset:34605*0 + 3*14*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34605*0 + 3*15*FLEN/8, x4, x1, x2)

inst_11536:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x71e169 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e71e169; op2val:0x0;
op3val:0x7f8000; valaddr_reg:x3; val_offset:34608*0 + 3*15*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34608*0 + 3*16*FLEN/8, x4, x1, x2)

inst_11537:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x71e169 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e71e169; op2val:0x0;
op3val:0x7fc000; valaddr_reg:x3; val_offset:34611*0 + 3*16*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34611*0 + 3*17*FLEN/8, x4, x1, x2)

inst_11538:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x71e169 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e71e169; op2val:0x0;
op3val:0x7fe000; valaddr_reg:x3; val_offset:34614*0 + 3*17*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34614*0 + 3*18*FLEN/8, x4, x1, x2)

inst_11539:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x71e169 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e71e169; op2val:0x0;
op3val:0x7ff000; valaddr_reg:x3; val_offset:34617*0 + 3*18*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34617*0 + 3*19*FLEN/8, x4, x1, x2)

inst_11540:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x71e169 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e71e169; op2val:0x0;
op3val:0x7ff800; valaddr_reg:x3; val_offset:34620*0 + 3*19*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34620*0 + 3*20*FLEN/8, x4, x1, x2)

inst_11541:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x71e169 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e71e169; op2val:0x0;
op3val:0x7ffc00; valaddr_reg:x3; val_offset:34623*0 + 3*20*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34623*0 + 3*21*FLEN/8, x4, x1, x2)

inst_11542:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x71e169 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e71e169; op2val:0x0;
op3val:0x7ffe00; valaddr_reg:x3; val_offset:34626*0 + 3*21*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34626*0 + 3*22*FLEN/8, x4, x1, x2)

inst_11543:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x71e169 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e71e169; op2val:0x0;
op3val:0x7fff00; valaddr_reg:x3; val_offset:34629*0 + 3*22*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34629*0 + 3*23*FLEN/8, x4, x1, x2)

inst_11544:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x71e169 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e71e169; op2val:0x0;
op3val:0x7fff80; valaddr_reg:x3; val_offset:34632*0 + 3*23*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34632*0 + 3*24*FLEN/8, x4, x1, x2)

inst_11545:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x71e169 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e71e169; op2val:0x0;
op3val:0x7fffc0; valaddr_reg:x3; val_offset:34635*0 + 3*24*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34635*0 + 3*25*FLEN/8, x4, x1, x2)

inst_11546:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x71e169 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e71e169; op2val:0x0;
op3val:0x7fffe0; valaddr_reg:x3; val_offset:34638*0 + 3*25*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34638*0 + 3*26*FLEN/8, x4, x1, x2)

inst_11547:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x71e169 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e71e169; op2val:0x0;
op3val:0x7ffff0; valaddr_reg:x3; val_offset:34641*0 + 3*26*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34641*0 + 3*27*FLEN/8, x4, x1, x2)

inst_11548:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x71e169 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e71e169; op2val:0x0;
op3val:0x7ffff8; valaddr_reg:x3; val_offset:34644*0 + 3*27*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34644*0 + 3*28*FLEN/8, x4, x1, x2)

inst_11549:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x71e169 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e71e169; op2val:0x0;
op3val:0x7ffffc; valaddr_reg:x3; val_offset:34647*0 + 3*28*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34647*0 + 3*29*FLEN/8, x4, x1, x2)

inst_11550:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x71e169 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e71e169; op2val:0x0;
op3val:0x7ffffe; valaddr_reg:x3; val_offset:34650*0 + 3*29*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34650*0 + 3*30*FLEN/8, x4, x1, x2)

inst_11551:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x71e169 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e71e169; op2val:0x0;
op3val:0x7fffff; valaddr_reg:x3; val_offset:34653*0 + 3*30*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34653*0 + 3*31*FLEN/8, x4, x1, x2)

inst_11552:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xbf800001; valaddr_reg:x3; val_offset:34656*0 + 3*31*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34656*0 + 3*32*FLEN/8, x4, x1, x2)

inst_11553:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xbf800003; valaddr_reg:x3; val_offset:34659*0 + 3*32*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34659*0 + 3*33*FLEN/8, x4, x1, x2)

inst_11554:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xbf800007; valaddr_reg:x3; val_offset:34662*0 + 3*33*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34662*0 + 3*34*FLEN/8, x4, x1, x2)

inst_11555:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xbf999999; valaddr_reg:x3; val_offset:34665*0 + 3*34*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34665*0 + 3*35*FLEN/8, x4, x1, x2)

inst_11556:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xbfa49249; valaddr_reg:x3; val_offset:34668*0 + 3*35*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34668*0 + 3*36*FLEN/8, x4, x1, x2)

inst_11557:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xbfb33333; valaddr_reg:x3; val_offset:34671*0 + 3*36*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34671*0 + 3*37*FLEN/8, x4, x1, x2)

inst_11558:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xbfb6db6d; valaddr_reg:x3; val_offset:34674*0 + 3*37*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34674*0 + 3*38*FLEN/8, x4, x1, x2)

inst_11559:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xbfbbbbbb; valaddr_reg:x3; val_offset:34677*0 + 3*38*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34677*0 + 3*39*FLEN/8, x4, x1, x2)

inst_11560:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xbfc44444; valaddr_reg:x3; val_offset:34680*0 + 3*39*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34680*0 + 3*40*FLEN/8, x4, x1, x2)

inst_11561:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xbfcccccc; valaddr_reg:x3; val_offset:34683*0 + 3*40*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34683*0 + 3*41*FLEN/8, x4, x1, x2)

inst_11562:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xbfdb6db6; valaddr_reg:x3; val_offset:34686*0 + 3*41*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34686*0 + 3*42*FLEN/8, x4, x1, x2)

inst_11563:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xbfe66666; valaddr_reg:x3; val_offset:34689*0 + 3*42*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34689*0 + 3*43*FLEN/8, x4, x1, x2)

inst_11564:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xbfedb6db; valaddr_reg:x3; val_offset:34692*0 + 3*43*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34692*0 + 3*44*FLEN/8, x4, x1, x2)

inst_11565:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xbffffff8; valaddr_reg:x3; val_offset:34695*0 + 3*44*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34695*0 + 3*45*FLEN/8, x4, x1, x2)

inst_11566:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xbffffffc; valaddr_reg:x3; val_offset:34698*0 + 3*45*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34698*0 + 3*46*FLEN/8, x4, x1, x2)

inst_11567:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xbffffffe; valaddr_reg:x3; val_offset:34701*0 + 3*46*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34701*0 + 3*47*FLEN/8, x4, x1, x2)

inst_11568:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x8b and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xc5800000; valaddr_reg:x3; val_offset:34704*0 + 3*47*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34704*0 + 3*48*FLEN/8, x4, x1, x2)

inst_11569:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x8b and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xc5800001; valaddr_reg:x3; val_offset:34707*0 + 3*48*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34707*0 + 3*49*FLEN/8, x4, x1, x2)

inst_11570:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x8b and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xc5800003; valaddr_reg:x3; val_offset:34710*0 + 3*49*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34710*0 + 3*50*FLEN/8, x4, x1, x2)

inst_11571:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x8b and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xc5800007; valaddr_reg:x3; val_offset:34713*0 + 3*50*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34713*0 + 3*51*FLEN/8, x4, x1, x2)

inst_11572:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x8b and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xc580000f; valaddr_reg:x3; val_offset:34716*0 + 3*51*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34716*0 + 3*52*FLEN/8, x4, x1, x2)

inst_11573:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x8b and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xc580001f; valaddr_reg:x3; val_offset:34719*0 + 3*52*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34719*0 + 3*53*FLEN/8, x4, x1, x2)

inst_11574:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x8b and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xc580003f; valaddr_reg:x3; val_offset:34722*0 + 3*53*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34722*0 + 3*54*FLEN/8, x4, x1, x2)

inst_11575:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x8b and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xc580007f; valaddr_reg:x3; val_offset:34725*0 + 3*54*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34725*0 + 3*55*FLEN/8, x4, x1, x2)

inst_11576:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x8b and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xc58000ff; valaddr_reg:x3; val_offset:34728*0 + 3*55*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34728*0 + 3*56*FLEN/8, x4, x1, x2)

inst_11577:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x8b and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xc58001ff; valaddr_reg:x3; val_offset:34731*0 + 3*56*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34731*0 + 3*57*FLEN/8, x4, x1, x2)

inst_11578:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x8b and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xc58003ff; valaddr_reg:x3; val_offset:34734*0 + 3*57*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34734*0 + 3*58*FLEN/8, x4, x1, x2)

inst_11579:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x8b and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xc58007ff; valaddr_reg:x3; val_offset:34737*0 + 3*58*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34737*0 + 3*59*FLEN/8, x4, x1, x2)

inst_11580:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x8b and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xc5800fff; valaddr_reg:x3; val_offset:34740*0 + 3*59*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34740*0 + 3*60*FLEN/8, x4, x1, x2)

inst_11581:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x8b and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xc5801fff; valaddr_reg:x3; val_offset:34743*0 + 3*60*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34743*0 + 3*61*FLEN/8, x4, x1, x2)

inst_11582:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x8b and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xc5803fff; valaddr_reg:x3; val_offset:34746*0 + 3*61*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34746*0 + 3*62*FLEN/8, x4, x1, x2)

inst_11583:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x8b and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xc5807fff; valaddr_reg:x3; val_offset:34749*0 + 3*62*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34749*0 + 3*63*FLEN/8, x4, x1, x2)

inst_11584:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x8b and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xc580ffff; valaddr_reg:x3; val_offset:34752*0 + 3*63*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34752*0 + 3*64*FLEN/8, x4, x1, x2)

inst_11585:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x8b and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xc581ffff; valaddr_reg:x3; val_offset:34755*0 + 3*64*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34755*0 + 3*65*FLEN/8, x4, x1, x2)

inst_11586:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x8b and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xc583ffff; valaddr_reg:x3; val_offset:34758*0 + 3*65*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34758*0 + 3*66*FLEN/8, x4, x1, x2)

inst_11587:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x8b and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xc587ffff; valaddr_reg:x3; val_offset:34761*0 + 3*66*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34761*0 + 3*67*FLEN/8, x4, x1, x2)

inst_11588:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x8b and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xc58fffff; valaddr_reg:x3; val_offset:34764*0 + 3*67*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34764*0 + 3*68*FLEN/8, x4, x1, x2)

inst_11589:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x8b and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xc59fffff; valaddr_reg:x3; val_offset:34767*0 + 3*68*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34767*0 + 3*69*FLEN/8, x4, x1, x2)

inst_11590:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x8b and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xc5bfffff; valaddr_reg:x3; val_offset:34770*0 + 3*69*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34770*0 + 3*70*FLEN/8, x4, x1, x2)

inst_11591:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x8b and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xc5c00000; valaddr_reg:x3; val_offset:34773*0 + 3*70*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34773*0 + 3*71*FLEN/8, x4, x1, x2)

inst_11592:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x8b and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xc5e00000; valaddr_reg:x3; val_offset:34776*0 + 3*71*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34776*0 + 3*72*FLEN/8, x4, x1, x2)

inst_11593:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x8b and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xc5f00000; valaddr_reg:x3; val_offset:34779*0 + 3*72*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34779*0 + 3*73*FLEN/8, x4, x1, x2)

inst_11594:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x8b and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xc5f80000; valaddr_reg:x3; val_offset:34782*0 + 3*73*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34782*0 + 3*74*FLEN/8, x4, x1, x2)

inst_11595:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x8b and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xc5fc0000; valaddr_reg:x3; val_offset:34785*0 + 3*74*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34785*0 + 3*75*FLEN/8, x4, x1, x2)

inst_11596:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x8b and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xc5fe0000; valaddr_reg:x3; val_offset:34788*0 + 3*75*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34788*0 + 3*76*FLEN/8, x4, x1, x2)

inst_11597:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x8b and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xc5ff0000; valaddr_reg:x3; val_offset:34791*0 + 3*76*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34791*0 + 3*77*FLEN/8, x4, x1, x2)

inst_11598:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x8b and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xc5ff8000; valaddr_reg:x3; val_offset:34794*0 + 3*77*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34794*0 + 3*78*FLEN/8, x4, x1, x2)

inst_11599:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x8b and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xc5ffc000; valaddr_reg:x3; val_offset:34797*0 + 3*78*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34797*0 + 3*79*FLEN/8, x4, x1, x2)

inst_11600:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x8b and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xc5ffe000; valaddr_reg:x3; val_offset:34800*0 + 3*79*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34800*0 + 3*80*FLEN/8, x4, x1, x2)

inst_11601:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x8b and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xc5fff000; valaddr_reg:x3; val_offset:34803*0 + 3*80*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34803*0 + 3*81*FLEN/8, x4, x1, x2)

inst_11602:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x8b and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xc5fff800; valaddr_reg:x3; val_offset:34806*0 + 3*81*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34806*0 + 3*82*FLEN/8, x4, x1, x2)

inst_11603:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x8b and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xc5fffc00; valaddr_reg:x3; val_offset:34809*0 + 3*82*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34809*0 + 3*83*FLEN/8, x4, x1, x2)

inst_11604:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x8b and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xc5fffe00; valaddr_reg:x3; val_offset:34812*0 + 3*83*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34812*0 + 3*84*FLEN/8, x4, x1, x2)

inst_11605:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x8b and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xc5ffff00; valaddr_reg:x3; val_offset:34815*0 + 3*84*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34815*0 + 3*85*FLEN/8, x4, x1, x2)

inst_11606:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x8b and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xc5ffff80; valaddr_reg:x3; val_offset:34818*0 + 3*85*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34818*0 + 3*86*FLEN/8, x4, x1, x2)

inst_11607:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x8b and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xc5ffffc0; valaddr_reg:x3; val_offset:34821*0 + 3*86*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34821*0 + 3*87*FLEN/8, x4, x1, x2)

inst_11608:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x8b and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xc5ffffe0; valaddr_reg:x3; val_offset:34824*0 + 3*87*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34824*0 + 3*88*FLEN/8, x4, x1, x2)

inst_11609:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x8b and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xc5fffff0; valaddr_reg:x3; val_offset:34827*0 + 3*88*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34827*0 + 3*89*FLEN/8, x4, x1, x2)

inst_11610:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x8b and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xc5fffff8; valaddr_reg:x3; val_offset:34830*0 + 3*89*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34830*0 + 3*90*FLEN/8, x4, x1, x2)

inst_11611:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x8b and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xc5fffffc; valaddr_reg:x3; val_offset:34833*0 + 3*90*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34833*0 + 3*91*FLEN/8, x4, x1, x2)

inst_11612:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x8b and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xc5fffffe; valaddr_reg:x3; val_offset:34836*0 + 3*91*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34836*0 + 3*92*FLEN/8, x4, x1, x2)

inst_11613:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x729bb9 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x0710c1 and fs3 == 1 and fe3 == 0x8b and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e729bb9; op2val:0x808710c1;
op3val:0xc5ffffff; valaddr_reg:x3; val_offset:34839*0 + 3*92*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34839*0 + 3*93*FLEN/8, x4, x1, x2)

inst_11614:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xda and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x6d000000; valaddr_reg:x3; val_offset:34842*0 + 3*93*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34842*0 + 3*94*FLEN/8, x4, x1, x2)

inst_11615:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xda and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x6d000001; valaddr_reg:x3; val_offset:34845*0 + 3*94*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34845*0 + 3*95*FLEN/8, x4, x1, x2)

inst_11616:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xda and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x6d000003; valaddr_reg:x3; val_offset:34848*0 + 3*95*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34848*0 + 3*96*FLEN/8, x4, x1, x2)

inst_11617:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xda and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x6d000007; valaddr_reg:x3; val_offset:34851*0 + 3*96*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34851*0 + 3*97*FLEN/8, x4, x1, x2)

inst_11618:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xda and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x6d00000f; valaddr_reg:x3; val_offset:34854*0 + 3*97*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34854*0 + 3*98*FLEN/8, x4, x1, x2)

inst_11619:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xda and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x6d00001f; valaddr_reg:x3; val_offset:34857*0 + 3*98*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34857*0 + 3*99*FLEN/8, x4, x1, x2)

inst_11620:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xda and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x6d00003f; valaddr_reg:x3; val_offset:34860*0 + 3*99*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34860*0 + 3*100*FLEN/8, x4, x1, x2)

inst_11621:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xda and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x6d00007f; valaddr_reg:x3; val_offset:34863*0 + 3*100*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34863*0 + 3*101*FLEN/8, x4, x1, x2)

inst_11622:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xda and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x6d0000ff; valaddr_reg:x3; val_offset:34866*0 + 3*101*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34866*0 + 3*102*FLEN/8, x4, x1, x2)

inst_11623:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xda and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x6d0001ff; valaddr_reg:x3; val_offset:34869*0 + 3*102*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34869*0 + 3*103*FLEN/8, x4, x1, x2)

inst_11624:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xda and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x6d0003ff; valaddr_reg:x3; val_offset:34872*0 + 3*103*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34872*0 + 3*104*FLEN/8, x4, x1, x2)

inst_11625:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xda and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x6d0007ff; valaddr_reg:x3; val_offset:34875*0 + 3*104*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34875*0 + 3*105*FLEN/8, x4, x1, x2)

inst_11626:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xda and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x6d000fff; valaddr_reg:x3; val_offset:34878*0 + 3*105*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34878*0 + 3*106*FLEN/8, x4, x1, x2)

inst_11627:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xda and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x6d001fff; valaddr_reg:x3; val_offset:34881*0 + 3*106*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34881*0 + 3*107*FLEN/8, x4, x1, x2)

inst_11628:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xda and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x6d003fff; valaddr_reg:x3; val_offset:34884*0 + 3*107*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34884*0 + 3*108*FLEN/8, x4, x1, x2)

inst_11629:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xda and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x6d007fff; valaddr_reg:x3; val_offset:34887*0 + 3*108*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34887*0 + 3*109*FLEN/8, x4, x1, x2)

inst_11630:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xda and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x6d00ffff; valaddr_reg:x3; val_offset:34890*0 + 3*109*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34890*0 + 3*110*FLEN/8, x4, x1, x2)

inst_11631:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xda and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x6d01ffff; valaddr_reg:x3; val_offset:34893*0 + 3*110*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34893*0 + 3*111*FLEN/8, x4, x1, x2)

inst_11632:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xda and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x6d03ffff; valaddr_reg:x3; val_offset:34896*0 + 3*111*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34896*0 + 3*112*FLEN/8, x4, x1, x2)

inst_11633:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xda and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x6d07ffff; valaddr_reg:x3; val_offset:34899*0 + 3*112*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34899*0 + 3*113*FLEN/8, x4, x1, x2)

inst_11634:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xda and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x6d0fffff; valaddr_reg:x3; val_offset:34902*0 + 3*113*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34902*0 + 3*114*FLEN/8, x4, x1, x2)

inst_11635:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xda and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x6d1fffff; valaddr_reg:x3; val_offset:34905*0 + 3*114*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34905*0 + 3*115*FLEN/8, x4, x1, x2)

inst_11636:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xda and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x6d3fffff; valaddr_reg:x3; val_offset:34908*0 + 3*115*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34908*0 + 3*116*FLEN/8, x4, x1, x2)

inst_11637:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xda and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x6d400000; valaddr_reg:x3; val_offset:34911*0 + 3*116*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34911*0 + 3*117*FLEN/8, x4, x1, x2)

inst_11638:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xda and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x6d600000; valaddr_reg:x3; val_offset:34914*0 + 3*117*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34914*0 + 3*118*FLEN/8, x4, x1, x2)

inst_11639:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xda and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x6d700000; valaddr_reg:x3; val_offset:34917*0 + 3*118*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34917*0 + 3*119*FLEN/8, x4, x1, x2)

inst_11640:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xda and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x6d780000; valaddr_reg:x3; val_offset:34920*0 + 3*119*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34920*0 + 3*120*FLEN/8, x4, x1, x2)

inst_11641:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xda and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x6d7c0000; valaddr_reg:x3; val_offset:34923*0 + 3*120*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34923*0 + 3*121*FLEN/8, x4, x1, x2)

inst_11642:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xda and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x6d7e0000; valaddr_reg:x3; val_offset:34926*0 + 3*121*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34926*0 + 3*122*FLEN/8, x4, x1, x2)

inst_11643:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xda and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x6d7f0000; valaddr_reg:x3; val_offset:34929*0 + 3*122*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34929*0 + 3*123*FLEN/8, x4, x1, x2)

inst_11644:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xda and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x6d7f8000; valaddr_reg:x3; val_offset:34932*0 + 3*123*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34932*0 + 3*124*FLEN/8, x4, x1, x2)

inst_11645:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xda and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x6d7fc000; valaddr_reg:x3; val_offset:34935*0 + 3*124*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34935*0 + 3*125*FLEN/8, x4, x1, x2)

inst_11646:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xda and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x6d7fe000; valaddr_reg:x3; val_offset:34938*0 + 3*125*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34938*0 + 3*126*FLEN/8, x4, x1, x2)

inst_11647:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xda and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x6d7ff000; valaddr_reg:x3; val_offset:34941*0 + 3*126*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34941*0 + 3*127*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_2)

inst_11648:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xda and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x6d7ff800; valaddr_reg:x3; val_offset:34944*0 + 3*127*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34944*0 + 3*128*FLEN/8, x4, x1, x2)

inst_11649:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xda and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x6d7ffc00; valaddr_reg:x3; val_offset:34947*0 + 3*128*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34947*0 + 3*129*FLEN/8, x4, x1, x2)

inst_11650:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xda and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x6d7ffe00; valaddr_reg:x3; val_offset:34950*0 + 3*129*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34950*0 + 3*130*FLEN/8, x4, x1, x2)

inst_11651:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xda and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x6d7fff00; valaddr_reg:x3; val_offset:34953*0 + 3*130*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34953*0 + 3*131*FLEN/8, x4, x1, x2)

inst_11652:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xda and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x6d7fff80; valaddr_reg:x3; val_offset:34956*0 + 3*131*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34956*0 + 3*132*FLEN/8, x4, x1, x2)

inst_11653:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xda and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x6d7fffc0; valaddr_reg:x3; val_offset:34959*0 + 3*132*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34959*0 + 3*133*FLEN/8, x4, x1, x2)

inst_11654:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xda and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x6d7fffe0; valaddr_reg:x3; val_offset:34962*0 + 3*133*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34962*0 + 3*134*FLEN/8, x4, x1, x2)

inst_11655:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xda and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x6d7ffff0; valaddr_reg:x3; val_offset:34965*0 + 3*134*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34965*0 + 3*135*FLEN/8, x4, x1, x2)

inst_11656:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xda and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x6d7ffff8; valaddr_reg:x3; val_offset:34968*0 + 3*135*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34968*0 + 3*136*FLEN/8, x4, x1, x2)

inst_11657:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xda and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x6d7ffffc; valaddr_reg:x3; val_offset:34971*0 + 3*136*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34971*0 + 3*137*FLEN/8, x4, x1, x2)

inst_11658:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xda and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x6d7ffffe; valaddr_reg:x3; val_offset:34974*0 + 3*137*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34974*0 + 3*138*FLEN/8, x4, x1, x2)

inst_11659:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xda and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x6d7fffff; valaddr_reg:x3; val_offset:34977*0 + 3*138*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34977*0 + 3*139*FLEN/8, x4, x1, x2)

inst_11660:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x7f000001; valaddr_reg:x3; val_offset:34980*0 + 3*139*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34980*0 + 3*140*FLEN/8, x4, x1, x2)

inst_11661:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x7f000003; valaddr_reg:x3; val_offset:34983*0 + 3*140*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34983*0 + 3*141*FLEN/8, x4, x1, x2)

inst_11662:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x7f000007; valaddr_reg:x3; val_offset:34986*0 + 3*141*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34986*0 + 3*142*FLEN/8, x4, x1, x2)

inst_11663:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x7f199999; valaddr_reg:x3; val_offset:34989*0 + 3*142*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34989*0 + 3*143*FLEN/8, x4, x1, x2)

inst_11664:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x7f249249; valaddr_reg:x3; val_offset:34992*0 + 3*143*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34992*0 + 3*144*FLEN/8, x4, x1, x2)

inst_11665:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x7f333333; valaddr_reg:x3; val_offset:34995*0 + 3*144*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34995*0 + 3*145*FLEN/8, x4, x1, x2)

inst_11666:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x7f36db6d; valaddr_reg:x3; val_offset:34998*0 + 3*145*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 34998*0 + 3*146*FLEN/8, x4, x1, x2)

inst_11667:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x7f3bbbbb; valaddr_reg:x3; val_offset:35001*0 + 3*146*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35001*0 + 3*147*FLEN/8, x4, x1, x2)

inst_11668:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x7f444444; valaddr_reg:x3; val_offset:35004*0 + 3*147*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35004*0 + 3*148*FLEN/8, x4, x1, x2)

inst_11669:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x7f4ccccc; valaddr_reg:x3; val_offset:35007*0 + 3*148*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35007*0 + 3*149*FLEN/8, x4, x1, x2)

inst_11670:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x7f5b6db6; valaddr_reg:x3; val_offset:35010*0 + 3*149*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35010*0 + 3*150*FLEN/8, x4, x1, x2)

inst_11671:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x7f666666; valaddr_reg:x3; val_offset:35013*0 + 3*150*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35013*0 + 3*151*FLEN/8, x4, x1, x2)

inst_11672:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x7f6db6db; valaddr_reg:x3; val_offset:35016*0 + 3*151*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35016*0 + 3*152*FLEN/8, x4, x1, x2)

inst_11673:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x7f7ffff8; valaddr_reg:x3; val_offset:35019*0 + 3*152*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35019*0 + 3*153*FLEN/8, x4, x1, x2)

inst_11674:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x7f7ffffc; valaddr_reg:x3; val_offset:35022*0 + 3*153*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35022*0 + 3*154*FLEN/8, x4, x1, x2)

inst_11675:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x72a5cd and fs2 == 0 and fe2 == 0x81 and fm2 == 0x070b24 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e72a5cd; op2val:0x40870b24;
op3val:0x7f7ffffe; valaddr_reg:x3; val_offset:35025*0 + 3*154*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35025*0 + 3*155*FLEN/8, x4, x1, x2)

inst_11676:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0x1; valaddr_reg:x3; val_offset:35028*0 + 3*155*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35028*0 + 3*156*FLEN/8, x4, x1, x2)

inst_11677:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0x3; valaddr_reg:x3; val_offset:35031*0 + 3*156*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35031*0 + 3*157*FLEN/8, x4, x1, x2)

inst_11678:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0x7; valaddr_reg:x3; val_offset:35034*0 + 3*157*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35034*0 + 3*158*FLEN/8, x4, x1, x2)

inst_11679:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0x199999; valaddr_reg:x3; val_offset:35037*0 + 3*158*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35037*0 + 3*159*FLEN/8, x4, x1, x2)

inst_11680:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0x249249; valaddr_reg:x3; val_offset:35040*0 + 3*159*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35040*0 + 3*160*FLEN/8, x4, x1, x2)

inst_11681:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0x333333; valaddr_reg:x3; val_offset:35043*0 + 3*160*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35043*0 + 3*161*FLEN/8, x4, x1, x2)

inst_11682:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0x36db6d; valaddr_reg:x3; val_offset:35046*0 + 3*161*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35046*0 + 3*162*FLEN/8, x4, x1, x2)

inst_11683:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0x3bbbbb; valaddr_reg:x3; val_offset:35049*0 + 3*162*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35049*0 + 3*163*FLEN/8, x4, x1, x2)

inst_11684:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0x444444; valaddr_reg:x3; val_offset:35052*0 + 3*163*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35052*0 + 3*164*FLEN/8, x4, x1, x2)

inst_11685:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0x4ccccc; valaddr_reg:x3; val_offset:35055*0 + 3*164*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35055*0 + 3*165*FLEN/8, x4, x1, x2)

inst_11686:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0x5b6db6; valaddr_reg:x3; val_offset:35058*0 + 3*165*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35058*0 + 3*166*FLEN/8, x4, x1, x2)

inst_11687:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0x666666; valaddr_reg:x3; val_offset:35061*0 + 3*166*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35061*0 + 3*167*FLEN/8, x4, x1, x2)

inst_11688:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0x6db6db; valaddr_reg:x3; val_offset:35064*0 + 3*167*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35064*0 + 3*168*FLEN/8, x4, x1, x2)

inst_11689:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0x7ffff8; valaddr_reg:x3; val_offset:35067*0 + 3*168*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35067*0 + 3*169*FLEN/8, x4, x1, x2)

inst_11690:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0x7ffffc; valaddr_reg:x3; val_offset:35070*0 + 3*169*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35070*0 + 3*170*FLEN/8, x4, x1, x2)

inst_11691:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0x7ffffe; valaddr_reg:x3; val_offset:35073*0 + 3*170*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35073*0 + 3*171*FLEN/8, x4, x1, x2)

inst_11692:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0xb800000; valaddr_reg:x3; val_offset:35076*0 + 3*171*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35076*0 + 3*172*FLEN/8, x4, x1, x2)

inst_11693:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0xb800001; valaddr_reg:x3; val_offset:35079*0 + 3*172*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35079*0 + 3*173*FLEN/8, x4, x1, x2)

inst_11694:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0xb800003; valaddr_reg:x3; val_offset:35082*0 + 3*173*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35082*0 + 3*174*FLEN/8, x4, x1, x2)

inst_11695:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0xb800007; valaddr_reg:x3; val_offset:35085*0 + 3*174*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35085*0 + 3*175*FLEN/8, x4, x1, x2)

inst_11696:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0xb80000f; valaddr_reg:x3; val_offset:35088*0 + 3*175*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35088*0 + 3*176*FLEN/8, x4, x1, x2)

inst_11697:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0xb80001f; valaddr_reg:x3; val_offset:35091*0 + 3*176*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35091*0 + 3*177*FLEN/8, x4, x1, x2)

inst_11698:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0xb80003f; valaddr_reg:x3; val_offset:35094*0 + 3*177*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35094*0 + 3*178*FLEN/8, x4, x1, x2)

inst_11699:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0xb80007f; valaddr_reg:x3; val_offset:35097*0 + 3*178*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35097*0 + 3*179*FLEN/8, x4, x1, x2)

inst_11700:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0xb8000ff; valaddr_reg:x3; val_offset:35100*0 + 3*179*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35100*0 + 3*180*FLEN/8, x4, x1, x2)

inst_11701:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0xb8001ff; valaddr_reg:x3; val_offset:35103*0 + 3*180*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35103*0 + 3*181*FLEN/8, x4, x1, x2)

inst_11702:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0xb8003ff; valaddr_reg:x3; val_offset:35106*0 + 3*181*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35106*0 + 3*182*FLEN/8, x4, x1, x2)

inst_11703:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0xb8007ff; valaddr_reg:x3; val_offset:35109*0 + 3*182*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35109*0 + 3*183*FLEN/8, x4, x1, x2)

inst_11704:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0xb800fff; valaddr_reg:x3; val_offset:35112*0 + 3*183*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35112*0 + 3*184*FLEN/8, x4, x1, x2)

inst_11705:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0xb801fff; valaddr_reg:x3; val_offset:35115*0 + 3*184*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35115*0 + 3*185*FLEN/8, x4, x1, x2)

inst_11706:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0xb803fff; valaddr_reg:x3; val_offset:35118*0 + 3*185*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35118*0 + 3*186*FLEN/8, x4, x1, x2)

inst_11707:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0xb807fff; valaddr_reg:x3; val_offset:35121*0 + 3*186*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35121*0 + 3*187*FLEN/8, x4, x1, x2)

inst_11708:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0xb80ffff; valaddr_reg:x3; val_offset:35124*0 + 3*187*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35124*0 + 3*188*FLEN/8, x4, x1, x2)

inst_11709:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0xb81ffff; valaddr_reg:x3; val_offset:35127*0 + 3*188*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35127*0 + 3*189*FLEN/8, x4, x1, x2)

inst_11710:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0xb83ffff; valaddr_reg:x3; val_offset:35130*0 + 3*189*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35130*0 + 3*190*FLEN/8, x4, x1, x2)

inst_11711:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0xb87ffff; valaddr_reg:x3; val_offset:35133*0 + 3*190*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35133*0 + 3*191*FLEN/8, x4, x1, x2)

inst_11712:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0xb8fffff; valaddr_reg:x3; val_offset:35136*0 + 3*191*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35136*0 + 3*192*FLEN/8, x4, x1, x2)

inst_11713:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0xb9fffff; valaddr_reg:x3; val_offset:35139*0 + 3*192*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35139*0 + 3*193*FLEN/8, x4, x1, x2)

inst_11714:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0xbbfffff; valaddr_reg:x3; val_offset:35142*0 + 3*193*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35142*0 + 3*194*FLEN/8, x4, x1, x2)

inst_11715:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0xbc00000; valaddr_reg:x3; val_offset:35145*0 + 3*194*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35145*0 + 3*195*FLEN/8, x4, x1, x2)

inst_11716:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0xbe00000; valaddr_reg:x3; val_offset:35148*0 + 3*195*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35148*0 + 3*196*FLEN/8, x4, x1, x2)

inst_11717:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0xbf00000; valaddr_reg:x3; val_offset:35151*0 + 3*196*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35151*0 + 3*197*FLEN/8, x4, x1, x2)

inst_11718:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0xbf80000; valaddr_reg:x3; val_offset:35154*0 + 3*197*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35154*0 + 3*198*FLEN/8, x4, x1, x2)

inst_11719:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0xbfc0000; valaddr_reg:x3; val_offset:35157*0 + 3*198*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35157*0 + 3*199*FLEN/8, x4, x1, x2)

inst_11720:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0xbfe0000; valaddr_reg:x3; val_offset:35160*0 + 3*199*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35160*0 + 3*200*FLEN/8, x4, x1, x2)

inst_11721:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0xbff0000; valaddr_reg:x3; val_offset:35163*0 + 3*200*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35163*0 + 3*201*FLEN/8, x4, x1, x2)

inst_11722:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0xbff8000; valaddr_reg:x3; val_offset:35166*0 + 3*201*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35166*0 + 3*202*FLEN/8, x4, x1, x2)

inst_11723:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0xbffc000; valaddr_reg:x3; val_offset:35169*0 + 3*202*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35169*0 + 3*203*FLEN/8, x4, x1, x2)

inst_11724:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0xbffe000; valaddr_reg:x3; val_offset:35172*0 + 3*203*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35172*0 + 3*204*FLEN/8, x4, x1, x2)

inst_11725:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0xbfff000; valaddr_reg:x3; val_offset:35175*0 + 3*204*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35175*0 + 3*205*FLEN/8, x4, x1, x2)

inst_11726:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0xbfff800; valaddr_reg:x3; val_offset:35178*0 + 3*205*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35178*0 + 3*206*FLEN/8, x4, x1, x2)

inst_11727:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0xbfffc00; valaddr_reg:x3; val_offset:35181*0 + 3*206*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35181*0 + 3*207*FLEN/8, x4, x1, x2)

inst_11728:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0xbfffe00; valaddr_reg:x3; val_offset:35184*0 + 3*207*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35184*0 + 3*208*FLEN/8, x4, x1, x2)

inst_11729:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0xbffff00; valaddr_reg:x3; val_offset:35187*0 + 3*208*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35187*0 + 3*209*FLEN/8, x4, x1, x2)

inst_11730:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0xbffff80; valaddr_reg:x3; val_offset:35190*0 + 3*209*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35190*0 + 3*210*FLEN/8, x4, x1, x2)

inst_11731:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0xbffffc0; valaddr_reg:x3; val_offset:35193*0 + 3*210*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35193*0 + 3*211*FLEN/8, x4, x1, x2)

inst_11732:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0xbffffe0; valaddr_reg:x3; val_offset:35196*0 + 3*211*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35196*0 + 3*212*FLEN/8, x4, x1, x2)

inst_11733:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0xbfffff0; valaddr_reg:x3; val_offset:35199*0 + 3*212*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35199*0 + 3*213*FLEN/8, x4, x1, x2)

inst_11734:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0xbfffff8; valaddr_reg:x3; val_offset:35202*0 + 3*213*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35202*0 + 3*214*FLEN/8, x4, x1, x2)

inst_11735:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0xbfffffc; valaddr_reg:x3; val_offset:35205*0 + 3*214*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35205*0 + 3*215*FLEN/8, x4, x1, x2)

inst_11736:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0xbfffffe; valaddr_reg:x3; val_offset:35208*0 + 3*215*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35208*0 + 3*216*FLEN/8, x4, x1, x2)

inst_11737:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x748605 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e748605; op2val:0x0;
op3val:0xbffffff; valaddr_reg:x3; val_offset:35211*0 + 3*216*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35211*0 + 3*217*FLEN/8, x4, x1, x2)

inst_11738:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0x800001; valaddr_reg:x3; val_offset:35214*0 + 3*217*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35214*0 + 3*218*FLEN/8, x4, x1, x2)

inst_11739:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0x800003; valaddr_reg:x3; val_offset:35217*0 + 3*218*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35217*0 + 3*219*FLEN/8, x4, x1, x2)

inst_11740:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0x800007; valaddr_reg:x3; val_offset:35220*0 + 3*219*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35220*0 + 3*220*FLEN/8, x4, x1, x2)

inst_11741:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0x999999; valaddr_reg:x3; val_offset:35223*0 + 3*220*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35223*0 + 3*221*FLEN/8, x4, x1, x2)

inst_11742:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0xa49249; valaddr_reg:x3; val_offset:35226*0 + 3*221*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35226*0 + 3*222*FLEN/8, x4, x1, x2)

inst_11743:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0xb33333; valaddr_reg:x3; val_offset:35229*0 + 3*222*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35229*0 + 3*223*FLEN/8, x4, x1, x2)

inst_11744:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0xb6db6d; valaddr_reg:x3; val_offset:35232*0 + 3*223*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35232*0 + 3*224*FLEN/8, x4, x1, x2)

inst_11745:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0xbbbbbb; valaddr_reg:x3; val_offset:35235*0 + 3*224*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35235*0 + 3*225*FLEN/8, x4, x1, x2)

inst_11746:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0xc44444; valaddr_reg:x3; val_offset:35238*0 + 3*225*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35238*0 + 3*226*FLEN/8, x4, x1, x2)

inst_11747:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0xcccccc; valaddr_reg:x3; val_offset:35241*0 + 3*226*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35241*0 + 3*227*FLEN/8, x4, x1, x2)

inst_11748:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0xdb6db6; valaddr_reg:x3; val_offset:35244*0 + 3*227*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35244*0 + 3*228*FLEN/8, x4, x1, x2)

inst_11749:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0xe66666; valaddr_reg:x3; val_offset:35247*0 + 3*228*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35247*0 + 3*229*FLEN/8, x4, x1, x2)

inst_11750:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0xedb6db; valaddr_reg:x3; val_offset:35250*0 + 3*229*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35250*0 + 3*230*FLEN/8, x4, x1, x2)

inst_11751:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0xfffff8; valaddr_reg:x3; val_offset:35253*0 + 3*230*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35253*0 + 3*231*FLEN/8, x4, x1, x2)

inst_11752:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0xfffffc; valaddr_reg:x3; val_offset:35256*0 + 3*231*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35256*0 + 3*232*FLEN/8, x4, x1, x2)

inst_11753:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0xfffffe; valaddr_reg:x3; val_offset:35259*0 + 3*232*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35259*0 + 3*233*FLEN/8, x4, x1, x2)

inst_11754:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0x6800000; valaddr_reg:x3; val_offset:35262*0 + 3*233*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35262*0 + 3*234*FLEN/8, x4, x1, x2)

inst_11755:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0x6800001; valaddr_reg:x3; val_offset:35265*0 + 3*234*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35265*0 + 3*235*FLEN/8, x4, x1, x2)

inst_11756:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0x6800003; valaddr_reg:x3; val_offset:35268*0 + 3*235*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35268*0 + 3*236*FLEN/8, x4, x1, x2)

inst_11757:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0x6800007; valaddr_reg:x3; val_offset:35271*0 + 3*236*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35271*0 + 3*237*FLEN/8, x4, x1, x2)

inst_11758:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0x680000f; valaddr_reg:x3; val_offset:35274*0 + 3*237*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35274*0 + 3*238*FLEN/8, x4, x1, x2)

inst_11759:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0x680001f; valaddr_reg:x3; val_offset:35277*0 + 3*238*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35277*0 + 3*239*FLEN/8, x4, x1, x2)

inst_11760:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0x680003f; valaddr_reg:x3; val_offset:35280*0 + 3*239*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35280*0 + 3*240*FLEN/8, x4, x1, x2)

inst_11761:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0x680007f; valaddr_reg:x3; val_offset:35283*0 + 3*240*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35283*0 + 3*241*FLEN/8, x4, x1, x2)

inst_11762:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0x68000ff; valaddr_reg:x3; val_offset:35286*0 + 3*241*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35286*0 + 3*242*FLEN/8, x4, x1, x2)

inst_11763:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0x68001ff; valaddr_reg:x3; val_offset:35289*0 + 3*242*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35289*0 + 3*243*FLEN/8, x4, x1, x2)

inst_11764:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0x68003ff; valaddr_reg:x3; val_offset:35292*0 + 3*243*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35292*0 + 3*244*FLEN/8, x4, x1, x2)

inst_11765:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0x68007ff; valaddr_reg:x3; val_offset:35295*0 + 3*244*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35295*0 + 3*245*FLEN/8, x4, x1, x2)

inst_11766:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0x6800fff; valaddr_reg:x3; val_offset:35298*0 + 3*245*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35298*0 + 3*246*FLEN/8, x4, x1, x2)

inst_11767:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0x6801fff; valaddr_reg:x3; val_offset:35301*0 + 3*246*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35301*0 + 3*247*FLEN/8, x4, x1, x2)

inst_11768:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0x6803fff; valaddr_reg:x3; val_offset:35304*0 + 3*247*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35304*0 + 3*248*FLEN/8, x4, x1, x2)

inst_11769:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0x6807fff; valaddr_reg:x3; val_offset:35307*0 + 3*248*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35307*0 + 3*249*FLEN/8, x4, x1, x2)

inst_11770:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0x680ffff; valaddr_reg:x3; val_offset:35310*0 + 3*249*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35310*0 + 3*250*FLEN/8, x4, x1, x2)

inst_11771:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0x681ffff; valaddr_reg:x3; val_offset:35313*0 + 3*250*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35313*0 + 3*251*FLEN/8, x4, x1, x2)

inst_11772:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0x683ffff; valaddr_reg:x3; val_offset:35316*0 + 3*251*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35316*0 + 3*252*FLEN/8, x4, x1, x2)

inst_11773:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0x687ffff; valaddr_reg:x3; val_offset:35319*0 + 3*252*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35319*0 + 3*253*FLEN/8, x4, x1, x2)

inst_11774:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0x68fffff; valaddr_reg:x3; val_offset:35322*0 + 3*253*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35322*0 + 3*254*FLEN/8, x4, x1, x2)

inst_11775:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0x69fffff; valaddr_reg:x3; val_offset:35325*0 + 3*254*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35325*0 + 3*255*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_3)

inst_11776:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0x6bfffff; valaddr_reg:x3; val_offset:35328*0 + 3*256*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35328*0 + 3*256*FLEN/8, x4, x1, x2)

inst_11777:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0x6c00000; valaddr_reg:x3; val_offset:35331*0 + 3*257*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35331*0 + 3*257*FLEN/8, x4, x1, x2)

inst_11778:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0x6e00000; valaddr_reg:x3; val_offset:35334*0 + 3*258*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35334*0 + 3*258*FLEN/8, x4, x1, x2)

inst_11779:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0x6f00000; valaddr_reg:x3; val_offset:35337*0 + 3*259*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35337*0 + 3*259*FLEN/8, x4, x1, x2)

inst_11780:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0x6f80000; valaddr_reg:x3; val_offset:35340*0 + 3*260*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35340*0 + 3*260*FLEN/8, x4, x1, x2)

inst_11781:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0x6fc0000; valaddr_reg:x3; val_offset:35343*0 + 3*261*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35343*0 + 3*261*FLEN/8, x4, x1, x2)

inst_11782:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0x6fe0000; valaddr_reg:x3; val_offset:35346*0 + 3*262*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35346*0 + 3*262*FLEN/8, x4, x1, x2)

inst_11783:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0x6ff0000; valaddr_reg:x3; val_offset:35349*0 + 3*263*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35349*0 + 3*263*FLEN/8, x4, x1, x2)

inst_11784:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0x6ff8000; valaddr_reg:x3; val_offset:35352*0 + 3*264*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35352*0 + 3*264*FLEN/8, x4, x1, x2)

inst_11785:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0x6ffc000; valaddr_reg:x3; val_offset:35355*0 + 3*265*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35355*0 + 3*265*FLEN/8, x4, x1, x2)

inst_11786:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0x6ffe000; valaddr_reg:x3; val_offset:35358*0 + 3*266*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35358*0 + 3*266*FLEN/8, x4, x1, x2)

inst_11787:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0x6fff000; valaddr_reg:x3; val_offset:35361*0 + 3*267*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35361*0 + 3*267*FLEN/8, x4, x1, x2)

inst_11788:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0x6fff800; valaddr_reg:x3; val_offset:35364*0 + 3*268*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35364*0 + 3*268*FLEN/8, x4, x1, x2)

inst_11789:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0x6fffc00; valaddr_reg:x3; val_offset:35367*0 + 3*269*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35367*0 + 3*269*FLEN/8, x4, x1, x2)

inst_11790:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0x6fffe00; valaddr_reg:x3; val_offset:35370*0 + 3*270*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35370*0 + 3*270*FLEN/8, x4, x1, x2)

inst_11791:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0x6ffff00; valaddr_reg:x3; val_offset:35373*0 + 3*271*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35373*0 + 3*271*FLEN/8, x4, x1, x2)

inst_11792:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0x6ffff80; valaddr_reg:x3; val_offset:35376*0 + 3*272*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35376*0 + 3*272*FLEN/8, x4, x1, x2)

inst_11793:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0x6ffffc0; valaddr_reg:x3; val_offset:35379*0 + 3*273*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35379*0 + 3*273*FLEN/8, x4, x1, x2)

inst_11794:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0x6ffffe0; valaddr_reg:x3; val_offset:35382*0 + 3*274*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35382*0 + 3*274*FLEN/8, x4, x1, x2)

inst_11795:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0x6fffff0; valaddr_reg:x3; val_offset:35385*0 + 3*275*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35385*0 + 3*275*FLEN/8, x4, x1, x2)

inst_11796:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0x6fffff8; valaddr_reg:x3; val_offset:35388*0 + 3*276*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35388*0 + 3*276*FLEN/8, x4, x1, x2)

inst_11797:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0x6fffffc; valaddr_reg:x3; val_offset:35391*0 + 3*277*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35391*0 + 3*277*FLEN/8, x4, x1, x2)

inst_11798:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0x6fffffe; valaddr_reg:x3; val_offset:35394*0 + 3*278*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35394*0 + 3*278*FLEN/8, x4, x1, x2)

inst_11799:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x74d94c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0d and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e74d94c; op2val:0x0;
op3val:0x6ffffff; valaddr_reg:x3; val_offset:35397*0 + 3*279*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35397*0 + 3*279*FLEN/8, x4, x1, x2)

inst_11800:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3c800000; valaddr_reg:x3; val_offset:35400*0 + 3*280*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35400*0 + 3*280*FLEN/8, x4, x1, x2)

inst_11801:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3c800001; valaddr_reg:x3; val_offset:35403*0 + 3*281*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35403*0 + 3*281*FLEN/8, x4, x1, x2)

inst_11802:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3c800003; valaddr_reg:x3; val_offset:35406*0 + 3*282*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35406*0 + 3*282*FLEN/8, x4, x1, x2)

inst_11803:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3c800007; valaddr_reg:x3; val_offset:35409*0 + 3*283*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35409*0 + 3*283*FLEN/8, x4, x1, x2)

inst_11804:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3c80000f; valaddr_reg:x3; val_offset:35412*0 + 3*284*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35412*0 + 3*284*FLEN/8, x4, x1, x2)

inst_11805:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3c80001f; valaddr_reg:x3; val_offset:35415*0 + 3*285*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35415*0 + 3*285*FLEN/8, x4, x1, x2)

inst_11806:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3c80003f; valaddr_reg:x3; val_offset:35418*0 + 3*286*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35418*0 + 3*286*FLEN/8, x4, x1, x2)

inst_11807:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3c80007f; valaddr_reg:x3; val_offset:35421*0 + 3*287*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35421*0 + 3*287*FLEN/8, x4, x1, x2)

inst_11808:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3c8000ff; valaddr_reg:x3; val_offset:35424*0 + 3*288*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35424*0 + 3*288*FLEN/8, x4, x1, x2)

inst_11809:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3c8001ff; valaddr_reg:x3; val_offset:35427*0 + 3*289*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35427*0 + 3*289*FLEN/8, x4, x1, x2)

inst_11810:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3c8003ff; valaddr_reg:x3; val_offset:35430*0 + 3*290*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35430*0 + 3*290*FLEN/8, x4, x1, x2)

inst_11811:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3c8007ff; valaddr_reg:x3; val_offset:35433*0 + 3*291*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35433*0 + 3*291*FLEN/8, x4, x1, x2)

inst_11812:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3c800fff; valaddr_reg:x3; val_offset:35436*0 + 3*292*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35436*0 + 3*292*FLEN/8, x4, x1, x2)

inst_11813:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3c801fff; valaddr_reg:x3; val_offset:35439*0 + 3*293*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35439*0 + 3*293*FLEN/8, x4, x1, x2)

inst_11814:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3c803fff; valaddr_reg:x3; val_offset:35442*0 + 3*294*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35442*0 + 3*294*FLEN/8, x4, x1, x2)

inst_11815:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3c807fff; valaddr_reg:x3; val_offset:35445*0 + 3*295*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35445*0 + 3*295*FLEN/8, x4, x1, x2)

inst_11816:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3c80ffff; valaddr_reg:x3; val_offset:35448*0 + 3*296*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35448*0 + 3*296*FLEN/8, x4, x1, x2)

inst_11817:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3c81ffff; valaddr_reg:x3; val_offset:35451*0 + 3*297*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35451*0 + 3*297*FLEN/8, x4, x1, x2)

inst_11818:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3c83ffff; valaddr_reg:x3; val_offset:35454*0 + 3*298*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35454*0 + 3*298*FLEN/8, x4, x1, x2)

inst_11819:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3c87ffff; valaddr_reg:x3; val_offset:35457*0 + 3*299*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35457*0 + 3*299*FLEN/8, x4, x1, x2)

inst_11820:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3c8fffff; valaddr_reg:x3; val_offset:35460*0 + 3*300*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35460*0 + 3*300*FLEN/8, x4, x1, x2)

inst_11821:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3c9fffff; valaddr_reg:x3; val_offset:35463*0 + 3*301*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35463*0 + 3*301*FLEN/8, x4, x1, x2)

inst_11822:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3cbfffff; valaddr_reg:x3; val_offset:35466*0 + 3*302*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35466*0 + 3*302*FLEN/8, x4, x1, x2)

inst_11823:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3cc00000; valaddr_reg:x3; val_offset:35469*0 + 3*303*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35469*0 + 3*303*FLEN/8, x4, x1, x2)

inst_11824:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3ce00000; valaddr_reg:x3; val_offset:35472*0 + 3*304*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35472*0 + 3*304*FLEN/8, x4, x1, x2)

inst_11825:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3cf00000; valaddr_reg:x3; val_offset:35475*0 + 3*305*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35475*0 + 3*305*FLEN/8, x4, x1, x2)

inst_11826:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3cf80000; valaddr_reg:x3; val_offset:35478*0 + 3*306*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35478*0 + 3*306*FLEN/8, x4, x1, x2)

inst_11827:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3cfc0000; valaddr_reg:x3; val_offset:35481*0 + 3*307*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35481*0 + 3*307*FLEN/8, x4, x1, x2)

inst_11828:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3cfe0000; valaddr_reg:x3; val_offset:35484*0 + 3*308*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35484*0 + 3*308*FLEN/8, x4, x1, x2)

inst_11829:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3cff0000; valaddr_reg:x3; val_offset:35487*0 + 3*309*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35487*0 + 3*309*FLEN/8, x4, x1, x2)

inst_11830:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3cff8000; valaddr_reg:x3; val_offset:35490*0 + 3*310*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35490*0 + 3*310*FLEN/8, x4, x1, x2)

inst_11831:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3cffc000; valaddr_reg:x3; val_offset:35493*0 + 3*311*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35493*0 + 3*311*FLEN/8, x4, x1, x2)

inst_11832:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3cffe000; valaddr_reg:x3; val_offset:35496*0 + 3*312*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35496*0 + 3*312*FLEN/8, x4, x1, x2)

inst_11833:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3cfff000; valaddr_reg:x3; val_offset:35499*0 + 3*313*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35499*0 + 3*313*FLEN/8, x4, x1, x2)

inst_11834:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3cfff800; valaddr_reg:x3; val_offset:35502*0 + 3*314*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35502*0 + 3*314*FLEN/8, x4, x1, x2)

inst_11835:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3cfffc00; valaddr_reg:x3; val_offset:35505*0 + 3*315*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35505*0 + 3*315*FLEN/8, x4, x1, x2)

inst_11836:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3cfffe00; valaddr_reg:x3; val_offset:35508*0 + 3*316*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35508*0 + 3*316*FLEN/8, x4, x1, x2)

inst_11837:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3cffff00; valaddr_reg:x3; val_offset:35511*0 + 3*317*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35511*0 + 3*317*FLEN/8, x4, x1, x2)

inst_11838:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3cffff80; valaddr_reg:x3; val_offset:35514*0 + 3*318*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35514*0 + 3*318*FLEN/8, x4, x1, x2)

inst_11839:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3cffffc0; valaddr_reg:x3; val_offset:35517*0 + 3*319*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35517*0 + 3*319*FLEN/8, x4, x1, x2)

inst_11840:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3cffffe0; valaddr_reg:x3; val_offset:35520*0 + 3*320*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35520*0 + 3*320*FLEN/8, x4, x1, x2)

inst_11841:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3cfffff0; valaddr_reg:x3; val_offset:35523*0 + 3*321*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35523*0 + 3*321*FLEN/8, x4, x1, x2)

inst_11842:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3cfffff8; valaddr_reg:x3; val_offset:35526*0 + 3*322*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35526*0 + 3*322*FLEN/8, x4, x1, x2)

inst_11843:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3cfffffc; valaddr_reg:x3; val_offset:35529*0 + 3*323*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35529*0 + 3*323*FLEN/8, x4, x1, x2)

inst_11844:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3cfffffe; valaddr_reg:x3; val_offset:35532*0 + 3*324*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35532*0 + 3*324*FLEN/8, x4, x1, x2)

inst_11845:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x79 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3cffffff; valaddr_reg:x3; val_offset:35535*0 + 3*325*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35535*0 + 3*325*FLEN/8, x4, x1, x2)

inst_11846:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3f800001; valaddr_reg:x3; val_offset:35538*0 + 3*326*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35538*0 + 3*326*FLEN/8, x4, x1, x2)

inst_11847:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3f800003; valaddr_reg:x3; val_offset:35541*0 + 3*327*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35541*0 + 3*327*FLEN/8, x4, x1, x2)

inst_11848:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3f800007; valaddr_reg:x3; val_offset:35544*0 + 3*328*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35544*0 + 3*328*FLEN/8, x4, x1, x2)

inst_11849:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3f999999; valaddr_reg:x3; val_offset:35547*0 + 3*329*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35547*0 + 3*329*FLEN/8, x4, x1, x2)

inst_11850:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3fa49249; valaddr_reg:x3; val_offset:35550*0 + 3*330*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35550*0 + 3*330*FLEN/8, x4, x1, x2)

inst_11851:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3fb33333; valaddr_reg:x3; val_offset:35553*0 + 3*331*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35553*0 + 3*331*FLEN/8, x4, x1, x2)

inst_11852:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3fb6db6d; valaddr_reg:x3; val_offset:35556*0 + 3*332*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35556*0 + 3*332*FLEN/8, x4, x1, x2)

inst_11853:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3fbbbbbb; valaddr_reg:x3; val_offset:35559*0 + 3*333*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35559*0 + 3*333*FLEN/8, x4, x1, x2)

inst_11854:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3fc44444; valaddr_reg:x3; val_offset:35562*0 + 3*334*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35562*0 + 3*334*FLEN/8, x4, x1, x2)

inst_11855:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3fcccccc; valaddr_reg:x3; val_offset:35565*0 + 3*335*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35565*0 + 3*335*FLEN/8, x4, x1, x2)

inst_11856:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3fdb6db6; valaddr_reg:x3; val_offset:35568*0 + 3*336*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35568*0 + 3*336*FLEN/8, x4, x1, x2)

inst_11857:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3fe66666; valaddr_reg:x3; val_offset:35571*0 + 3*337*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35571*0 + 3*337*FLEN/8, x4, x1, x2)

inst_11858:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3fedb6db; valaddr_reg:x3; val_offset:35574*0 + 3*338*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35574*0 + 3*338*FLEN/8, x4, x1, x2)

inst_11859:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3ffffff8; valaddr_reg:x3; val_offset:35577*0 + 3*339*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35577*0 + 3*339*FLEN/8, x4, x1, x2)

inst_11860:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3ffffffc; valaddr_reg:x3; val_offset:35580*0 + 3*340*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35580*0 + 3*340*FLEN/8, x4, x1, x2)

inst_11861:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x75c78c and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0552a0 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e75c78c; op2val:0x8552a0;
op3val:0x3ffffffe; valaddr_reg:x3; val_offset:35583*0 + 3*341*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35583*0 + 3*341*FLEN/8, x4, x1, x2)

inst_11862:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x3f800001; valaddr_reg:x3; val_offset:35586*0 + 3*342*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35586*0 + 3*342*FLEN/8, x4, x1, x2)

inst_11863:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x3f800003; valaddr_reg:x3; val_offset:35589*0 + 3*343*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35589*0 + 3*343*FLEN/8, x4, x1, x2)

inst_11864:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x3f800007; valaddr_reg:x3; val_offset:35592*0 + 3*344*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35592*0 + 3*344*FLEN/8, x4, x1, x2)

inst_11865:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x3f999999; valaddr_reg:x3; val_offset:35595*0 + 3*345*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35595*0 + 3*345*FLEN/8, x4, x1, x2)

inst_11866:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x3fa49249; valaddr_reg:x3; val_offset:35598*0 + 3*346*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35598*0 + 3*346*FLEN/8, x4, x1, x2)

inst_11867:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x3fb33333; valaddr_reg:x3; val_offset:35601*0 + 3*347*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35601*0 + 3*347*FLEN/8, x4, x1, x2)

inst_11868:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x3fb6db6d; valaddr_reg:x3; val_offset:35604*0 + 3*348*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35604*0 + 3*348*FLEN/8, x4, x1, x2)

inst_11869:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x3fbbbbbb; valaddr_reg:x3; val_offset:35607*0 + 3*349*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35607*0 + 3*349*FLEN/8, x4, x1, x2)

inst_11870:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x3fc44444; valaddr_reg:x3; val_offset:35610*0 + 3*350*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35610*0 + 3*350*FLEN/8, x4, x1, x2)

inst_11871:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x3fcccccc; valaddr_reg:x3; val_offset:35613*0 + 3*351*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35613*0 + 3*351*FLEN/8, x4, x1, x2)

inst_11872:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x3fdb6db6; valaddr_reg:x3; val_offset:35616*0 + 3*352*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35616*0 + 3*352*FLEN/8, x4, x1, x2)

inst_11873:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x3fe66666; valaddr_reg:x3; val_offset:35619*0 + 3*353*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35619*0 + 3*353*FLEN/8, x4, x1, x2)

inst_11874:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x3fedb6db; valaddr_reg:x3; val_offset:35622*0 + 3*354*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35622*0 + 3*354*FLEN/8, x4, x1, x2)

inst_11875:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x3ffffff8; valaddr_reg:x3; val_offset:35625*0 + 3*355*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35625*0 + 3*355*FLEN/8, x4, x1, x2)

inst_11876:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x3ffffffc; valaddr_reg:x3; val_offset:35628*0 + 3*356*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35628*0 + 3*356*FLEN/8, x4, x1, x2)

inst_11877:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x3ffffffe; valaddr_reg:x3; val_offset:35631*0 + 3*357*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35631*0 + 3*357*FLEN/8, x4, x1, x2)

inst_11878:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x8c and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x46000000; valaddr_reg:x3; val_offset:35634*0 + 3*358*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35634*0 + 3*358*FLEN/8, x4, x1, x2)

inst_11879:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x8c and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x46000001; valaddr_reg:x3; val_offset:35637*0 + 3*359*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35637*0 + 3*359*FLEN/8, x4, x1, x2)

inst_11880:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x8c and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x46000003; valaddr_reg:x3; val_offset:35640*0 + 3*360*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35640*0 + 3*360*FLEN/8, x4, x1, x2)

inst_11881:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x8c and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x46000007; valaddr_reg:x3; val_offset:35643*0 + 3*361*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35643*0 + 3*361*FLEN/8, x4, x1, x2)

inst_11882:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x8c and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x4600000f; valaddr_reg:x3; val_offset:35646*0 + 3*362*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35646*0 + 3*362*FLEN/8, x4, x1, x2)

inst_11883:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x8c and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x4600001f; valaddr_reg:x3; val_offset:35649*0 + 3*363*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35649*0 + 3*363*FLEN/8, x4, x1, x2)

inst_11884:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x8c and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x4600003f; valaddr_reg:x3; val_offset:35652*0 + 3*364*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35652*0 + 3*364*FLEN/8, x4, x1, x2)

inst_11885:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x8c and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x4600007f; valaddr_reg:x3; val_offset:35655*0 + 3*365*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35655*0 + 3*365*FLEN/8, x4, x1, x2)

inst_11886:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x8c and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x460000ff; valaddr_reg:x3; val_offset:35658*0 + 3*366*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35658*0 + 3*366*FLEN/8, x4, x1, x2)

inst_11887:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x8c and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x460001ff; valaddr_reg:x3; val_offset:35661*0 + 3*367*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35661*0 + 3*367*FLEN/8, x4, x1, x2)

inst_11888:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x8c and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x460003ff; valaddr_reg:x3; val_offset:35664*0 + 3*368*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35664*0 + 3*368*FLEN/8, x4, x1, x2)

inst_11889:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x8c and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x460007ff; valaddr_reg:x3; val_offset:35667*0 + 3*369*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35667*0 + 3*369*FLEN/8, x4, x1, x2)

inst_11890:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x8c and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x46000fff; valaddr_reg:x3; val_offset:35670*0 + 3*370*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35670*0 + 3*370*FLEN/8, x4, x1, x2)

inst_11891:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x8c and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x46001fff; valaddr_reg:x3; val_offset:35673*0 + 3*371*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35673*0 + 3*371*FLEN/8, x4, x1, x2)

inst_11892:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x8c and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x46003fff; valaddr_reg:x3; val_offset:35676*0 + 3*372*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35676*0 + 3*372*FLEN/8, x4, x1, x2)

inst_11893:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x8c and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x46007fff; valaddr_reg:x3; val_offset:35679*0 + 3*373*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35679*0 + 3*373*FLEN/8, x4, x1, x2)

inst_11894:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x8c and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x4600ffff; valaddr_reg:x3; val_offset:35682*0 + 3*374*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35682*0 + 3*374*FLEN/8, x4, x1, x2)

inst_11895:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x8c and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x4601ffff; valaddr_reg:x3; val_offset:35685*0 + 3*375*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35685*0 + 3*375*FLEN/8, x4, x1, x2)

inst_11896:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x8c and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x4603ffff; valaddr_reg:x3; val_offset:35688*0 + 3*376*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35688*0 + 3*376*FLEN/8, x4, x1, x2)

inst_11897:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x8c and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x4607ffff; valaddr_reg:x3; val_offset:35691*0 + 3*377*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35691*0 + 3*377*FLEN/8, x4, x1, x2)

inst_11898:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x8c and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x460fffff; valaddr_reg:x3; val_offset:35694*0 + 3*378*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35694*0 + 3*378*FLEN/8, x4, x1, x2)

inst_11899:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x8c and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x461fffff; valaddr_reg:x3; val_offset:35697*0 + 3*379*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35697*0 + 3*379*FLEN/8, x4, x1, x2)

inst_11900:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x8c and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x463fffff; valaddr_reg:x3; val_offset:35700*0 + 3*380*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35700*0 + 3*380*FLEN/8, x4, x1, x2)

inst_11901:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x8c and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x46400000; valaddr_reg:x3; val_offset:35703*0 + 3*381*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35703*0 + 3*381*FLEN/8, x4, x1, x2)

inst_11902:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x8c and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x46600000; valaddr_reg:x3; val_offset:35706*0 + 3*382*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35706*0 + 3*382*FLEN/8, x4, x1, x2)

inst_11903:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x8c and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x46700000; valaddr_reg:x3; val_offset:35709*0 + 3*383*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35709*0 + 3*383*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_4)

inst_11904:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x8c and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x46780000; valaddr_reg:x3; val_offset:35712*0 + 3*384*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35712*0 + 3*384*FLEN/8, x4, x1, x2)

inst_11905:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x8c and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x467c0000; valaddr_reg:x3; val_offset:35715*0 + 3*385*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35715*0 + 3*385*FLEN/8, x4, x1, x2)

inst_11906:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x8c and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x467e0000; valaddr_reg:x3; val_offset:35718*0 + 3*386*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35718*0 + 3*386*FLEN/8, x4, x1, x2)

inst_11907:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x8c and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x467f0000; valaddr_reg:x3; val_offset:35721*0 + 3*387*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35721*0 + 3*387*FLEN/8, x4, x1, x2)

inst_11908:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x8c and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x467f8000; valaddr_reg:x3; val_offset:35724*0 + 3*388*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35724*0 + 3*388*FLEN/8, x4, x1, x2)

inst_11909:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x8c and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x467fc000; valaddr_reg:x3; val_offset:35727*0 + 3*389*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35727*0 + 3*389*FLEN/8, x4, x1, x2)

inst_11910:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x8c and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x467fe000; valaddr_reg:x3; val_offset:35730*0 + 3*390*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35730*0 + 3*390*FLEN/8, x4, x1, x2)

inst_11911:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x8c and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x467ff000; valaddr_reg:x3; val_offset:35733*0 + 3*391*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35733*0 + 3*391*FLEN/8, x4, x1, x2)

inst_11912:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x8c and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x467ff800; valaddr_reg:x3; val_offset:35736*0 + 3*392*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35736*0 + 3*392*FLEN/8, x4, x1, x2)

inst_11913:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x8c and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x467ffc00; valaddr_reg:x3; val_offset:35739*0 + 3*393*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35739*0 + 3*393*FLEN/8, x4, x1, x2)

inst_11914:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x8c and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x467ffe00; valaddr_reg:x3; val_offset:35742*0 + 3*394*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35742*0 + 3*394*FLEN/8, x4, x1, x2)

inst_11915:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x8c and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x467fff00; valaddr_reg:x3; val_offset:35745*0 + 3*395*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35745*0 + 3*395*FLEN/8, x4, x1, x2)

inst_11916:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x8c and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x467fff80; valaddr_reg:x3; val_offset:35748*0 + 3*396*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35748*0 + 3*396*FLEN/8, x4, x1, x2)

inst_11917:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x8c and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x467fffc0; valaddr_reg:x3; val_offset:35751*0 + 3*397*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35751*0 + 3*397*FLEN/8, x4, x1, x2)

inst_11918:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x8c and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x467fffe0; valaddr_reg:x3; val_offset:35754*0 + 3*398*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35754*0 + 3*398*FLEN/8, x4, x1, x2)

inst_11919:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x8c and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x467ffff0; valaddr_reg:x3; val_offset:35757*0 + 3*399*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35757*0 + 3*399*FLEN/8, x4, x1, x2)

inst_11920:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x8c and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x467ffff8; valaddr_reg:x3; val_offset:35760*0 + 3*400*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35760*0 + 3*400*FLEN/8, x4, x1, x2)

inst_11921:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x8c and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x467ffffc; valaddr_reg:x3; val_offset:35763*0 + 3*401*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35763*0 + 3*401*FLEN/8, x4, x1, x2)

inst_11922:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x8c and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x467ffffe; valaddr_reg:x3; val_offset:35766*0 + 3*402*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35766*0 + 3*402*FLEN/8, x4, x1, x2)

inst_11923:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x774515 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x0484e8 and fs3 == 0 and fe3 == 0x8c and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e774515; op2val:0x8484e8;
op3val:0x467fffff; valaddr_reg:x3; val_offset:35769*0 + 3*403*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35769*0 + 3*403*FLEN/8, x4, x1, x2)

inst_11924:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x3; val_offset:35772*0 + 3*404*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35772*0 + 3*404*FLEN/8, x4, x1, x2)

inst_11925:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x80000003; valaddr_reg:x3; val_offset:35775*0 + 3*405*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35775*0 + 3*405*FLEN/8, x4, x1, x2)

inst_11926:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x80000007; valaddr_reg:x3; val_offset:35778*0 + 3*406*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35778*0 + 3*406*FLEN/8, x4, x1, x2)

inst_11927:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x80199999; valaddr_reg:x3; val_offset:35781*0 + 3*407*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35781*0 + 3*407*FLEN/8, x4, x1, x2)

inst_11928:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x80249249; valaddr_reg:x3; val_offset:35784*0 + 3*408*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35784*0 + 3*408*FLEN/8, x4, x1, x2)

inst_11929:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x80333333; valaddr_reg:x3; val_offset:35787*0 + 3*409*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35787*0 + 3*409*FLEN/8, x4, x1, x2)

inst_11930:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x8036db6d; valaddr_reg:x3; val_offset:35790*0 + 3*410*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35790*0 + 3*410*FLEN/8, x4, x1, x2)

inst_11931:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x803bbbbb; valaddr_reg:x3; val_offset:35793*0 + 3*411*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35793*0 + 3*411*FLEN/8, x4, x1, x2)

inst_11932:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x80444444; valaddr_reg:x3; val_offset:35796*0 + 3*412*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35796*0 + 3*412*FLEN/8, x4, x1, x2)

inst_11933:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x804ccccc; valaddr_reg:x3; val_offset:35799*0 + 3*413*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35799*0 + 3*413*FLEN/8, x4, x1, x2)

inst_11934:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x805b6db6; valaddr_reg:x3; val_offset:35802*0 + 3*414*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35802*0 + 3*414*FLEN/8, x4, x1, x2)

inst_11935:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x80666666; valaddr_reg:x3; val_offset:35805*0 + 3*415*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35805*0 + 3*415*FLEN/8, x4, x1, x2)

inst_11936:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x806db6db; valaddr_reg:x3; val_offset:35808*0 + 3*416*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35808*0 + 3*416*FLEN/8, x4, x1, x2)

inst_11937:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x807ffff8; valaddr_reg:x3; val_offset:35811*0 + 3*417*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35811*0 + 3*417*FLEN/8, x4, x1, x2)

inst_11938:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x807ffffc; valaddr_reg:x3; val_offset:35814*0 + 3*418*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35814*0 + 3*418*FLEN/8, x4, x1, x2)

inst_11939:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x3; val_offset:35817*0 + 3*419*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35817*0 + 3*419*FLEN/8, x4, x1, x2)

inst_11940:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x10 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x88000000; valaddr_reg:x3; val_offset:35820*0 + 3*420*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35820*0 + 3*420*FLEN/8, x4, x1, x2)

inst_11941:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x10 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x88000001; valaddr_reg:x3; val_offset:35823*0 + 3*421*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35823*0 + 3*421*FLEN/8, x4, x1, x2)

inst_11942:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x10 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x88000003; valaddr_reg:x3; val_offset:35826*0 + 3*422*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35826*0 + 3*422*FLEN/8, x4, x1, x2)

inst_11943:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x10 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x88000007; valaddr_reg:x3; val_offset:35829*0 + 3*423*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35829*0 + 3*423*FLEN/8, x4, x1, x2)

inst_11944:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x10 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x8800000f; valaddr_reg:x3; val_offset:35832*0 + 3*424*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35832*0 + 3*424*FLEN/8, x4, x1, x2)

inst_11945:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x10 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x8800001f; valaddr_reg:x3; val_offset:35835*0 + 3*425*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35835*0 + 3*425*FLEN/8, x4, x1, x2)

inst_11946:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x10 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x8800003f; valaddr_reg:x3; val_offset:35838*0 + 3*426*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35838*0 + 3*426*FLEN/8, x4, x1, x2)

inst_11947:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x10 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x8800007f; valaddr_reg:x3; val_offset:35841*0 + 3*427*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35841*0 + 3*427*FLEN/8, x4, x1, x2)

inst_11948:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x10 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x880000ff; valaddr_reg:x3; val_offset:35844*0 + 3*428*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35844*0 + 3*428*FLEN/8, x4, x1, x2)

inst_11949:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x10 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x880001ff; valaddr_reg:x3; val_offset:35847*0 + 3*429*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35847*0 + 3*429*FLEN/8, x4, x1, x2)

inst_11950:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x10 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x880003ff; valaddr_reg:x3; val_offset:35850*0 + 3*430*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35850*0 + 3*430*FLEN/8, x4, x1, x2)

inst_11951:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x10 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x880007ff; valaddr_reg:x3; val_offset:35853*0 + 3*431*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35853*0 + 3*431*FLEN/8, x4, x1, x2)

inst_11952:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x10 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x88000fff; valaddr_reg:x3; val_offset:35856*0 + 3*432*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35856*0 + 3*432*FLEN/8, x4, x1, x2)

inst_11953:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x10 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x88001fff; valaddr_reg:x3; val_offset:35859*0 + 3*433*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35859*0 + 3*433*FLEN/8, x4, x1, x2)

inst_11954:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x10 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x88003fff; valaddr_reg:x3; val_offset:35862*0 + 3*434*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35862*0 + 3*434*FLEN/8, x4, x1, x2)

inst_11955:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x10 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x88007fff; valaddr_reg:x3; val_offset:35865*0 + 3*435*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35865*0 + 3*435*FLEN/8, x4, x1, x2)

inst_11956:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x10 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x8800ffff; valaddr_reg:x3; val_offset:35868*0 + 3*436*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35868*0 + 3*436*FLEN/8, x4, x1, x2)

inst_11957:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x10 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x8801ffff; valaddr_reg:x3; val_offset:35871*0 + 3*437*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35871*0 + 3*437*FLEN/8, x4, x1, x2)

inst_11958:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x10 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x8803ffff; valaddr_reg:x3; val_offset:35874*0 + 3*438*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35874*0 + 3*438*FLEN/8, x4, x1, x2)

inst_11959:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x10 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x8807ffff; valaddr_reg:x3; val_offset:35877*0 + 3*439*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35877*0 + 3*439*FLEN/8, x4, x1, x2)

inst_11960:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x10 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x880fffff; valaddr_reg:x3; val_offset:35880*0 + 3*440*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35880*0 + 3*440*FLEN/8, x4, x1, x2)

inst_11961:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x10 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x881fffff; valaddr_reg:x3; val_offset:35883*0 + 3*441*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35883*0 + 3*441*FLEN/8, x4, x1, x2)

inst_11962:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x10 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x883fffff; valaddr_reg:x3; val_offset:35886*0 + 3*442*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35886*0 + 3*442*FLEN/8, x4, x1, x2)

inst_11963:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x10 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x88400000; valaddr_reg:x3; val_offset:35889*0 + 3*443*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35889*0 + 3*443*FLEN/8, x4, x1, x2)

inst_11964:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x10 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x88600000; valaddr_reg:x3; val_offset:35892*0 + 3*444*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35892*0 + 3*444*FLEN/8, x4, x1, x2)

inst_11965:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x10 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x88700000; valaddr_reg:x3; val_offset:35895*0 + 3*445*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35895*0 + 3*445*FLEN/8, x4, x1, x2)

inst_11966:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x10 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x88780000; valaddr_reg:x3; val_offset:35898*0 + 3*446*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35898*0 + 3*446*FLEN/8, x4, x1, x2)

inst_11967:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x10 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x887c0000; valaddr_reg:x3; val_offset:35901*0 + 3*447*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35901*0 + 3*447*FLEN/8, x4, x1, x2)

inst_11968:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x10 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x887e0000; valaddr_reg:x3; val_offset:35904*0 + 3*448*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35904*0 + 3*448*FLEN/8, x4, x1, x2)

inst_11969:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x10 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x887f0000; valaddr_reg:x3; val_offset:35907*0 + 3*449*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35907*0 + 3*449*FLEN/8, x4, x1, x2)

inst_11970:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x10 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x887f8000; valaddr_reg:x3; val_offset:35910*0 + 3*450*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35910*0 + 3*450*FLEN/8, x4, x1, x2)

inst_11971:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x10 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x887fc000; valaddr_reg:x3; val_offset:35913*0 + 3*451*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35913*0 + 3*451*FLEN/8, x4, x1, x2)

inst_11972:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x10 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x887fe000; valaddr_reg:x3; val_offset:35916*0 + 3*452*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35916*0 + 3*452*FLEN/8, x4, x1, x2)

inst_11973:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x10 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x887ff000; valaddr_reg:x3; val_offset:35919*0 + 3*453*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35919*0 + 3*453*FLEN/8, x4, x1, x2)

inst_11974:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x10 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x887ff800; valaddr_reg:x3; val_offset:35922*0 + 3*454*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35922*0 + 3*454*FLEN/8, x4, x1, x2)

inst_11975:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x10 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x887ffc00; valaddr_reg:x3; val_offset:35925*0 + 3*455*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35925*0 + 3*455*FLEN/8, x4, x1, x2)

inst_11976:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x10 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x887ffe00; valaddr_reg:x3; val_offset:35928*0 + 3*456*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35928*0 + 3*456*FLEN/8, x4, x1, x2)

inst_11977:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x10 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x887fff00; valaddr_reg:x3; val_offset:35931*0 + 3*457*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35931*0 + 3*457*FLEN/8, x4, x1, x2)

inst_11978:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x10 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x887fff80; valaddr_reg:x3; val_offset:35934*0 + 3*458*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35934*0 + 3*458*FLEN/8, x4, x1, x2)

inst_11979:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x10 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x887fffc0; valaddr_reg:x3; val_offset:35937*0 + 3*459*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35937*0 + 3*459*FLEN/8, x4, x1, x2)

inst_11980:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x10 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x887fffe0; valaddr_reg:x3; val_offset:35940*0 + 3*460*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35940*0 + 3*460*FLEN/8, x4, x1, x2)

inst_11981:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x10 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x887ffff0; valaddr_reg:x3; val_offset:35943*0 + 3*461*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35943*0 + 3*461*FLEN/8, x4, x1, x2)

inst_11982:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x10 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x887ffff8; valaddr_reg:x3; val_offset:35946*0 + 3*462*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35946*0 + 3*462*FLEN/8, x4, x1, x2)

inst_11983:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x10 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x887ffffc; valaddr_reg:x3; val_offset:35949*0 + 3*463*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35949*0 + 3*463*FLEN/8, x4, x1, x2)

inst_11984:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x10 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x887ffffe; valaddr_reg:x3; val_offset:35952*0 + 3*464*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35952*0 + 3*464*FLEN/8, x4, x1, x2)

inst_11985:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x790586 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x10 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e790586; op2val:0x80000000;
op3val:0x887fffff; valaddr_reg:x3; val_offset:35955*0 + 3*465*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35955*0 + 3*465*FLEN/8, x4, x1, x2)

inst_11986:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x1; valaddr_reg:x3; val_offset:35958*0 + 3*466*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35958*0 + 3*466*FLEN/8, x4, x1, x2)

inst_11987:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x3; valaddr_reg:x3; val_offset:35961*0 + 3*467*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35961*0 + 3*467*FLEN/8, x4, x1, x2)

inst_11988:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x7; valaddr_reg:x3; val_offset:35964*0 + 3*468*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35964*0 + 3*468*FLEN/8, x4, x1, x2)

inst_11989:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x199999; valaddr_reg:x3; val_offset:35967*0 + 3*469*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35967*0 + 3*469*FLEN/8, x4, x1, x2)

inst_11990:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x249249; valaddr_reg:x3; val_offset:35970*0 + 3*470*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35970*0 + 3*470*FLEN/8, x4, x1, x2)

inst_11991:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x333333; valaddr_reg:x3; val_offset:35973*0 + 3*471*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35973*0 + 3*471*FLEN/8, x4, x1, x2)

inst_11992:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x36db6d; valaddr_reg:x3; val_offset:35976*0 + 3*472*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35976*0 + 3*472*FLEN/8, x4, x1, x2)

inst_11993:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x3bbbbb; valaddr_reg:x3; val_offset:35979*0 + 3*473*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35979*0 + 3*473*FLEN/8, x4, x1, x2)

inst_11994:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x444444; valaddr_reg:x3; val_offset:35982*0 + 3*474*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35982*0 + 3*474*FLEN/8, x4, x1, x2)

inst_11995:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x4ccccc; valaddr_reg:x3; val_offset:35985*0 + 3*475*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35985*0 + 3*475*FLEN/8, x4, x1, x2)

inst_11996:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x5b6db6; valaddr_reg:x3; val_offset:35988*0 + 3*476*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35988*0 + 3*476*FLEN/8, x4, x1, x2)

inst_11997:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x666666; valaddr_reg:x3; val_offset:35991*0 + 3*477*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35991*0 + 3*477*FLEN/8, x4, x1, x2)

inst_11998:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x6db6db; valaddr_reg:x3; val_offset:35994*0 + 3*478*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35994*0 + 3*478*FLEN/8, x4, x1, x2)

inst_11999:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x7ffff8; valaddr_reg:x3; val_offset:35997*0 + 3*479*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 35997*0 + 3*479*FLEN/8, x4, x1, x2)

inst_12000:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x7ffffc; valaddr_reg:x3; val_offset:36000*0 + 3*480*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36000*0 + 3*480*FLEN/8, x4, x1, x2)

inst_12001:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x7ffffe; valaddr_reg:x3; val_offset:36003*0 + 3*481*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36003*0 + 3*481*FLEN/8, x4, x1, x2)

inst_12002:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x5800000; valaddr_reg:x3; val_offset:36006*0 + 3*482*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36006*0 + 3*482*FLEN/8, x4, x1, x2)

inst_12003:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x5800001; valaddr_reg:x3; val_offset:36009*0 + 3*483*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36009*0 + 3*483*FLEN/8, x4, x1, x2)

inst_12004:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x5800003; valaddr_reg:x3; val_offset:36012*0 + 3*484*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36012*0 + 3*484*FLEN/8, x4, x1, x2)

inst_12005:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x5800007; valaddr_reg:x3; val_offset:36015*0 + 3*485*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36015*0 + 3*485*FLEN/8, x4, x1, x2)

inst_12006:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x580000f; valaddr_reg:x3; val_offset:36018*0 + 3*486*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36018*0 + 3*486*FLEN/8, x4, x1, x2)

inst_12007:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x580001f; valaddr_reg:x3; val_offset:36021*0 + 3*487*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36021*0 + 3*487*FLEN/8, x4, x1, x2)

inst_12008:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x580003f; valaddr_reg:x3; val_offset:36024*0 + 3*488*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36024*0 + 3*488*FLEN/8, x4, x1, x2)

inst_12009:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x580007f; valaddr_reg:x3; val_offset:36027*0 + 3*489*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36027*0 + 3*489*FLEN/8, x4, x1, x2)

inst_12010:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x58000ff; valaddr_reg:x3; val_offset:36030*0 + 3*490*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36030*0 + 3*490*FLEN/8, x4, x1, x2)

inst_12011:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x58001ff; valaddr_reg:x3; val_offset:36033*0 + 3*491*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36033*0 + 3*491*FLEN/8, x4, x1, x2)

inst_12012:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x58003ff; valaddr_reg:x3; val_offset:36036*0 + 3*492*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36036*0 + 3*492*FLEN/8, x4, x1, x2)

inst_12013:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x58007ff; valaddr_reg:x3; val_offset:36039*0 + 3*493*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36039*0 + 3*493*FLEN/8, x4, x1, x2)

inst_12014:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x5800fff; valaddr_reg:x3; val_offset:36042*0 + 3*494*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36042*0 + 3*494*FLEN/8, x4, x1, x2)

inst_12015:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x5801fff; valaddr_reg:x3; val_offset:36045*0 + 3*495*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36045*0 + 3*495*FLEN/8, x4, x1, x2)

inst_12016:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x5803fff; valaddr_reg:x3; val_offset:36048*0 + 3*496*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36048*0 + 3*496*FLEN/8, x4, x1, x2)

inst_12017:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x5807fff; valaddr_reg:x3; val_offset:36051*0 + 3*497*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36051*0 + 3*497*FLEN/8, x4, x1, x2)

inst_12018:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x580ffff; valaddr_reg:x3; val_offset:36054*0 + 3*498*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36054*0 + 3*498*FLEN/8, x4, x1, x2)

inst_12019:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x581ffff; valaddr_reg:x3; val_offset:36057*0 + 3*499*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36057*0 + 3*499*FLEN/8, x4, x1, x2)

inst_12020:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x583ffff; valaddr_reg:x3; val_offset:36060*0 + 3*500*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36060*0 + 3*500*FLEN/8, x4, x1, x2)

inst_12021:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x587ffff; valaddr_reg:x3; val_offset:36063*0 + 3*501*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36063*0 + 3*501*FLEN/8, x4, x1, x2)

inst_12022:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x58fffff; valaddr_reg:x3; val_offset:36066*0 + 3*502*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36066*0 + 3*502*FLEN/8, x4, x1, x2)

inst_12023:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x59fffff; valaddr_reg:x3; val_offset:36069*0 + 3*503*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36069*0 + 3*503*FLEN/8, x4, x1, x2)

inst_12024:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x5bfffff; valaddr_reg:x3; val_offset:36072*0 + 3*504*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36072*0 + 3*504*FLEN/8, x4, x1, x2)

inst_12025:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x5c00000; valaddr_reg:x3; val_offset:36075*0 + 3*505*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36075*0 + 3*505*FLEN/8, x4, x1, x2)

inst_12026:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x5e00000; valaddr_reg:x3; val_offset:36078*0 + 3*506*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36078*0 + 3*506*FLEN/8, x4, x1, x2)

inst_12027:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x5f00000; valaddr_reg:x3; val_offset:36081*0 + 3*507*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36081*0 + 3*507*FLEN/8, x4, x1, x2)

inst_12028:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x5f80000; valaddr_reg:x3; val_offset:36084*0 + 3*508*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36084*0 + 3*508*FLEN/8, x4, x1, x2)

inst_12029:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x5fc0000; valaddr_reg:x3; val_offset:36087*0 + 3*509*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36087*0 + 3*509*FLEN/8, x4, x1, x2)

inst_12030:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x5fe0000; valaddr_reg:x3; val_offset:36090*0 + 3*510*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36090*0 + 3*510*FLEN/8, x4, x1, x2)

inst_12031:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x5ff0000; valaddr_reg:x3; val_offset:36093*0 + 3*511*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36093*0 + 3*511*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_5)

inst_12032:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x5ff8000; valaddr_reg:x3; val_offset:36096*0 + 3*512*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36096*0 + 3*512*FLEN/8, x4, x1, x2)

inst_12033:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x5ffc000; valaddr_reg:x3; val_offset:36099*0 + 3*513*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36099*0 + 3*513*FLEN/8, x4, x1, x2)

inst_12034:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x5ffe000; valaddr_reg:x3; val_offset:36102*0 + 3*514*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36102*0 + 3*514*FLEN/8, x4, x1, x2)

inst_12035:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x5fff000; valaddr_reg:x3; val_offset:36105*0 + 3*515*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36105*0 + 3*515*FLEN/8, x4, x1, x2)

inst_12036:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x5fff800; valaddr_reg:x3; val_offset:36108*0 + 3*516*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36108*0 + 3*516*FLEN/8, x4, x1, x2)

inst_12037:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x5fffc00; valaddr_reg:x3; val_offset:36111*0 + 3*517*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36111*0 + 3*517*FLEN/8, x4, x1, x2)

inst_12038:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x5fffe00; valaddr_reg:x3; val_offset:36114*0 + 3*518*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36114*0 + 3*518*FLEN/8, x4, x1, x2)

inst_12039:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x5ffff00; valaddr_reg:x3; val_offset:36117*0 + 3*519*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36117*0 + 3*519*FLEN/8, x4, x1, x2)

inst_12040:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x5ffff80; valaddr_reg:x3; val_offset:36120*0 + 3*520*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36120*0 + 3*520*FLEN/8, x4, x1, x2)

inst_12041:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x5ffffc0; valaddr_reg:x3; val_offset:36123*0 + 3*521*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36123*0 + 3*521*FLEN/8, x4, x1, x2)

inst_12042:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x5ffffe0; valaddr_reg:x3; val_offset:36126*0 + 3*522*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36126*0 + 3*522*FLEN/8, x4, x1, x2)

inst_12043:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x5fffff0; valaddr_reg:x3; val_offset:36129*0 + 3*523*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36129*0 + 3*523*FLEN/8, x4, x1, x2)

inst_12044:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x5fffff8; valaddr_reg:x3; val_offset:36132*0 + 3*524*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36132*0 + 3*524*FLEN/8, x4, x1, x2)

inst_12045:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x5fffffc; valaddr_reg:x3; val_offset:36135*0 + 3*525*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36135*0 + 3*525*FLEN/8, x4, x1, x2)

inst_12046:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x5fffffe; valaddr_reg:x3; val_offset:36138*0 + 3*526*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36138*0 + 3*526*FLEN/8, x4, x1, x2)

inst_12047:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7a08a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7a08a9; op2val:0x0;
op3val:0x5ffffff; valaddr_reg:x3; val_offset:36141*0 + 3*527*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36141*0 + 3*527*FLEN/8, x4, x1, x2)

inst_12048:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7e800000; valaddr_reg:x3; val_offset:36144*0 + 3*528*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36144*0 + 3*528*FLEN/8, x4, x1, x2)

inst_12049:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7e800001; valaddr_reg:x3; val_offset:36147*0 + 3*529*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36147*0 + 3*529*FLEN/8, x4, x1, x2)

inst_12050:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7e800003; valaddr_reg:x3; val_offset:36150*0 + 3*530*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36150*0 + 3*530*FLEN/8, x4, x1, x2)

inst_12051:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7e800007; valaddr_reg:x3; val_offset:36153*0 + 3*531*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36153*0 + 3*531*FLEN/8, x4, x1, x2)

inst_12052:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7e80000f; valaddr_reg:x3; val_offset:36156*0 + 3*532*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36156*0 + 3*532*FLEN/8, x4, x1, x2)

inst_12053:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7e80001f; valaddr_reg:x3; val_offset:36159*0 + 3*533*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36159*0 + 3*533*FLEN/8, x4, x1, x2)

inst_12054:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7e80003f; valaddr_reg:x3; val_offset:36162*0 + 3*534*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36162*0 + 3*534*FLEN/8, x4, x1, x2)

inst_12055:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7e80007f; valaddr_reg:x3; val_offset:36165*0 + 3*535*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36165*0 + 3*535*FLEN/8, x4, x1, x2)

inst_12056:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7e8000ff; valaddr_reg:x3; val_offset:36168*0 + 3*536*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36168*0 + 3*536*FLEN/8, x4, x1, x2)

inst_12057:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7e8001ff; valaddr_reg:x3; val_offset:36171*0 + 3*537*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36171*0 + 3*537*FLEN/8, x4, x1, x2)

inst_12058:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7e8003ff; valaddr_reg:x3; val_offset:36174*0 + 3*538*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36174*0 + 3*538*FLEN/8, x4, x1, x2)

inst_12059:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7e8007ff; valaddr_reg:x3; val_offset:36177*0 + 3*539*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36177*0 + 3*539*FLEN/8, x4, x1, x2)

inst_12060:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7e800fff; valaddr_reg:x3; val_offset:36180*0 + 3*540*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36180*0 + 3*540*FLEN/8, x4, x1, x2)

inst_12061:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7e801fff; valaddr_reg:x3; val_offset:36183*0 + 3*541*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36183*0 + 3*541*FLEN/8, x4, x1, x2)

inst_12062:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7e803fff; valaddr_reg:x3; val_offset:36186*0 + 3*542*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36186*0 + 3*542*FLEN/8, x4, x1, x2)

inst_12063:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7e807fff; valaddr_reg:x3; val_offset:36189*0 + 3*543*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36189*0 + 3*543*FLEN/8, x4, x1, x2)

inst_12064:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7e80ffff; valaddr_reg:x3; val_offset:36192*0 + 3*544*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36192*0 + 3*544*FLEN/8, x4, x1, x2)

inst_12065:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7e81ffff; valaddr_reg:x3; val_offset:36195*0 + 3*545*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36195*0 + 3*545*FLEN/8, x4, x1, x2)

inst_12066:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7e83ffff; valaddr_reg:x3; val_offset:36198*0 + 3*546*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36198*0 + 3*546*FLEN/8, x4, x1, x2)

inst_12067:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7e87ffff; valaddr_reg:x3; val_offset:36201*0 + 3*547*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36201*0 + 3*547*FLEN/8, x4, x1, x2)

inst_12068:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7e8fffff; valaddr_reg:x3; val_offset:36204*0 + 3*548*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36204*0 + 3*548*FLEN/8, x4, x1, x2)

inst_12069:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7e9fffff; valaddr_reg:x3; val_offset:36207*0 + 3*549*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36207*0 + 3*549*FLEN/8, x4, x1, x2)

inst_12070:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7ebfffff; valaddr_reg:x3; val_offset:36210*0 + 3*550*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36210*0 + 3*550*FLEN/8, x4, x1, x2)

inst_12071:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7ec00000; valaddr_reg:x3; val_offset:36213*0 + 3*551*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36213*0 + 3*551*FLEN/8, x4, x1, x2)

inst_12072:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7ee00000; valaddr_reg:x3; val_offset:36216*0 + 3*552*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36216*0 + 3*552*FLEN/8, x4, x1, x2)

inst_12073:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7ef00000; valaddr_reg:x3; val_offset:36219*0 + 3*553*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36219*0 + 3*553*FLEN/8, x4, x1, x2)

inst_12074:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7ef80000; valaddr_reg:x3; val_offset:36222*0 + 3*554*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36222*0 + 3*554*FLEN/8, x4, x1, x2)

inst_12075:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7efc0000; valaddr_reg:x3; val_offset:36225*0 + 3*555*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36225*0 + 3*555*FLEN/8, x4, x1, x2)

inst_12076:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7efe0000; valaddr_reg:x3; val_offset:36228*0 + 3*556*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36228*0 + 3*556*FLEN/8, x4, x1, x2)

inst_12077:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7eff0000; valaddr_reg:x3; val_offset:36231*0 + 3*557*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36231*0 + 3*557*FLEN/8, x4, x1, x2)

inst_12078:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7eff8000; valaddr_reg:x3; val_offset:36234*0 + 3*558*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36234*0 + 3*558*FLEN/8, x4, x1, x2)

inst_12079:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7effc000; valaddr_reg:x3; val_offset:36237*0 + 3*559*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36237*0 + 3*559*FLEN/8, x4, x1, x2)

inst_12080:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7effe000; valaddr_reg:x3; val_offset:36240*0 + 3*560*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36240*0 + 3*560*FLEN/8, x4, x1, x2)

inst_12081:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7efff000; valaddr_reg:x3; val_offset:36243*0 + 3*561*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36243*0 + 3*561*FLEN/8, x4, x1, x2)

inst_12082:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7efff800; valaddr_reg:x3; val_offset:36246*0 + 3*562*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36246*0 + 3*562*FLEN/8, x4, x1, x2)

inst_12083:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7efffc00; valaddr_reg:x3; val_offset:36249*0 + 3*563*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36249*0 + 3*563*FLEN/8, x4, x1, x2)

inst_12084:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7efffe00; valaddr_reg:x3; val_offset:36252*0 + 3*564*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36252*0 + 3*564*FLEN/8, x4, x1, x2)

inst_12085:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7effff00; valaddr_reg:x3; val_offset:36255*0 + 3*565*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36255*0 + 3*565*FLEN/8, x4, x1, x2)

inst_12086:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7effff80; valaddr_reg:x3; val_offset:36258*0 + 3*566*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36258*0 + 3*566*FLEN/8, x4, x1, x2)

inst_12087:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7effffc0; valaddr_reg:x3; val_offset:36261*0 + 3*567*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36261*0 + 3*567*FLEN/8, x4, x1, x2)

inst_12088:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7effffe0; valaddr_reg:x3; val_offset:36264*0 + 3*568*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36264*0 + 3*568*FLEN/8, x4, x1, x2)

inst_12089:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7efffff0; valaddr_reg:x3; val_offset:36267*0 + 3*569*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36267*0 + 3*569*FLEN/8, x4, x1, x2)

inst_12090:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7efffff8; valaddr_reg:x3; val_offset:36270*0 + 3*570*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36270*0 + 3*570*FLEN/8, x4, x1, x2)

inst_12091:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7efffffc; valaddr_reg:x3; val_offset:36273*0 + 3*571*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36273*0 + 3*571*FLEN/8, x4, x1, x2)

inst_12092:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7efffffe; valaddr_reg:x3; val_offset:36276*0 + 3*572*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36276*0 + 3*572*FLEN/8, x4, x1, x2)

inst_12093:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfd and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7effffff; valaddr_reg:x3; val_offset:36279*0 + 3*573*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36279*0 + 3*573*FLEN/8, x4, x1, x2)

inst_12094:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7f000001; valaddr_reg:x3; val_offset:36282*0 + 3*574*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36282*0 + 3*574*FLEN/8, x4, x1, x2)

inst_12095:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7f000003; valaddr_reg:x3; val_offset:36285*0 + 3*575*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36285*0 + 3*575*FLEN/8, x4, x1, x2)

inst_12096:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7f000007; valaddr_reg:x3; val_offset:36288*0 + 3*576*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36288*0 + 3*576*FLEN/8, x4, x1, x2)

inst_12097:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7f199999; valaddr_reg:x3; val_offset:36291*0 + 3*577*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36291*0 + 3*577*FLEN/8, x4, x1, x2)

inst_12098:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7f249249; valaddr_reg:x3; val_offset:36294*0 + 3*578*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36294*0 + 3*578*FLEN/8, x4, x1, x2)

inst_12099:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7f333333; valaddr_reg:x3; val_offset:36297*0 + 3*579*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36297*0 + 3*579*FLEN/8, x4, x1, x2)

inst_12100:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7f36db6d; valaddr_reg:x3; val_offset:36300*0 + 3*580*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36300*0 + 3*580*FLEN/8, x4, x1, x2)

inst_12101:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7f3bbbbb; valaddr_reg:x3; val_offset:36303*0 + 3*581*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36303*0 + 3*581*FLEN/8, x4, x1, x2)

inst_12102:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7f444444; valaddr_reg:x3; val_offset:36306*0 + 3*582*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36306*0 + 3*582*FLEN/8, x4, x1, x2)

inst_12103:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7f4ccccc; valaddr_reg:x3; val_offset:36309*0 + 3*583*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36309*0 + 3*583*FLEN/8, x4, x1, x2)

inst_12104:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7f5b6db6; valaddr_reg:x3; val_offset:36312*0 + 3*584*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36312*0 + 3*584*FLEN/8, x4, x1, x2)

inst_12105:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7f666666; valaddr_reg:x3; val_offset:36315*0 + 3*585*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36315*0 + 3*585*FLEN/8, x4, x1, x2)

inst_12106:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7f6db6db; valaddr_reg:x3; val_offset:36318*0 + 3*586*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36318*0 + 3*586*FLEN/8, x4, x1, x2)

inst_12107:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7f7ffff8; valaddr_reg:x3; val_offset:36321*0 + 3*587*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36321*0 + 3*587*FLEN/8, x4, x1, x2)

inst_12108:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7f7ffffc; valaddr_reg:x3; val_offset:36324*0 + 3*588*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36324*0 + 3*588*FLEN/8, x4, x1, x2)

inst_12109:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c2bb2 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x01f197 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c2bb2; op2val:0x4081f197;
op3val:0x7f7ffffe; valaddr_reg:x3; val_offset:36327*0 + 3*589*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36327*0 + 3*589*FLEN/8, x4, x1, x2)

inst_12110:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xbf800001; valaddr_reg:x3; val_offset:36330*0 + 3*590*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36330*0 + 3*590*FLEN/8, x4, x1, x2)

inst_12111:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xbf800003; valaddr_reg:x3; val_offset:36333*0 + 3*591*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36333*0 + 3*591*FLEN/8, x4, x1, x2)

inst_12112:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x7f and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xbf800007; valaddr_reg:x3; val_offset:36336*0 + 3*592*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36336*0 + 3*592*FLEN/8, x4, x1, x2)

inst_12113:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x7f and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xbf999999; valaddr_reg:x3; val_offset:36339*0 + 3*593*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36339*0 + 3*593*FLEN/8, x4, x1, x2)

inst_12114:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x7f and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xbfa49249; valaddr_reg:x3; val_offset:36342*0 + 3*594*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36342*0 + 3*594*FLEN/8, x4, x1, x2)

inst_12115:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x7f and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xbfb33333; valaddr_reg:x3; val_offset:36345*0 + 3*595*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36345*0 + 3*595*FLEN/8, x4, x1, x2)

inst_12116:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x7f and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xbfb6db6d; valaddr_reg:x3; val_offset:36348*0 + 3*596*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36348*0 + 3*596*FLEN/8, x4, x1, x2)

inst_12117:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x7f and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xbfbbbbbb; valaddr_reg:x3; val_offset:36351*0 + 3*597*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36351*0 + 3*597*FLEN/8, x4, x1, x2)

inst_12118:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x7f and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xbfc44444; valaddr_reg:x3; val_offset:36354*0 + 3*598*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36354*0 + 3*598*FLEN/8, x4, x1, x2)

inst_12119:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x7f and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xbfcccccc; valaddr_reg:x3; val_offset:36357*0 + 3*599*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36357*0 + 3*599*FLEN/8, x4, x1, x2)

inst_12120:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x7f and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xbfdb6db6; valaddr_reg:x3; val_offset:36360*0 + 3*600*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36360*0 + 3*600*FLEN/8, x4, x1, x2)

inst_12121:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x7f and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xbfe66666; valaddr_reg:x3; val_offset:36363*0 + 3*601*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36363*0 + 3*601*FLEN/8, x4, x1, x2)

inst_12122:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x7f and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xbfedb6db; valaddr_reg:x3; val_offset:36366*0 + 3*602*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36366*0 + 3*602*FLEN/8, x4, x1, x2)

inst_12123:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xbffffff8; valaddr_reg:x3; val_offset:36369*0 + 3*603*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36369*0 + 3*603*FLEN/8, x4, x1, x2)

inst_12124:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xbffffffc; valaddr_reg:x3; val_offset:36372*0 + 3*604*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36372*0 + 3*604*FLEN/8, x4, x1, x2)

inst_12125:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x7f and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xbffffffe; valaddr_reg:x3; val_offset:36375*0 + 3*605*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36375*0 + 3*605*FLEN/8, x4, x1, x2)

inst_12126:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x92 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xc9000000; valaddr_reg:x3; val_offset:36378*0 + 3*606*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36378*0 + 3*606*FLEN/8, x4, x1, x2)

inst_12127:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x92 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xc9000001; valaddr_reg:x3; val_offset:36381*0 + 3*607*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36381*0 + 3*607*FLEN/8, x4, x1, x2)

inst_12128:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x92 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xc9000003; valaddr_reg:x3; val_offset:36384*0 + 3*608*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36384*0 + 3*608*FLEN/8, x4, x1, x2)

inst_12129:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x92 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xc9000007; valaddr_reg:x3; val_offset:36387*0 + 3*609*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36387*0 + 3*609*FLEN/8, x4, x1, x2)

inst_12130:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x92 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xc900000f; valaddr_reg:x3; val_offset:36390*0 + 3*610*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36390*0 + 3*610*FLEN/8, x4, x1, x2)

inst_12131:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x92 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xc900001f; valaddr_reg:x3; val_offset:36393*0 + 3*611*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36393*0 + 3*611*FLEN/8, x4, x1, x2)

inst_12132:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x92 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xc900003f; valaddr_reg:x3; val_offset:36396*0 + 3*612*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36396*0 + 3*612*FLEN/8, x4, x1, x2)

inst_12133:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x92 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xc900007f; valaddr_reg:x3; val_offset:36399*0 + 3*613*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36399*0 + 3*613*FLEN/8, x4, x1, x2)

inst_12134:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x92 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xc90000ff; valaddr_reg:x3; val_offset:36402*0 + 3*614*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36402*0 + 3*614*FLEN/8, x4, x1, x2)

inst_12135:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x92 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xc90001ff; valaddr_reg:x3; val_offset:36405*0 + 3*615*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36405*0 + 3*615*FLEN/8, x4, x1, x2)

inst_12136:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x92 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xc90003ff; valaddr_reg:x3; val_offset:36408*0 + 3*616*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36408*0 + 3*616*FLEN/8, x4, x1, x2)

inst_12137:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x92 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xc90007ff; valaddr_reg:x3; val_offset:36411*0 + 3*617*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36411*0 + 3*617*FLEN/8, x4, x1, x2)

inst_12138:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x92 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xc9000fff; valaddr_reg:x3; val_offset:36414*0 + 3*618*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36414*0 + 3*618*FLEN/8, x4, x1, x2)

inst_12139:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x92 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xc9001fff; valaddr_reg:x3; val_offset:36417*0 + 3*619*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36417*0 + 3*619*FLEN/8, x4, x1, x2)

inst_12140:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x92 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xc9003fff; valaddr_reg:x3; val_offset:36420*0 + 3*620*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36420*0 + 3*620*FLEN/8, x4, x1, x2)

inst_12141:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x92 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xc9007fff; valaddr_reg:x3; val_offset:36423*0 + 3*621*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36423*0 + 3*621*FLEN/8, x4, x1, x2)

inst_12142:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x92 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xc900ffff; valaddr_reg:x3; val_offset:36426*0 + 3*622*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36426*0 + 3*622*FLEN/8, x4, x1, x2)

inst_12143:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x92 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xc901ffff; valaddr_reg:x3; val_offset:36429*0 + 3*623*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36429*0 + 3*623*FLEN/8, x4, x1, x2)

inst_12144:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x92 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xc903ffff; valaddr_reg:x3; val_offset:36432*0 + 3*624*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36432*0 + 3*624*FLEN/8, x4, x1, x2)

inst_12145:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x92 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xc907ffff; valaddr_reg:x3; val_offset:36435*0 + 3*625*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36435*0 + 3*625*FLEN/8, x4, x1, x2)

inst_12146:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x92 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xc90fffff; valaddr_reg:x3; val_offset:36438*0 + 3*626*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36438*0 + 3*626*FLEN/8, x4, x1, x2)

inst_12147:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x92 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xc91fffff; valaddr_reg:x3; val_offset:36441*0 + 3*627*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36441*0 + 3*627*FLEN/8, x4, x1, x2)

inst_12148:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x92 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xc93fffff; valaddr_reg:x3; val_offset:36444*0 + 3*628*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36444*0 + 3*628*FLEN/8, x4, x1, x2)

inst_12149:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x92 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xc9400000; valaddr_reg:x3; val_offset:36447*0 + 3*629*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36447*0 + 3*629*FLEN/8, x4, x1, x2)

inst_12150:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x92 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xc9600000; valaddr_reg:x3; val_offset:36450*0 + 3*630*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36450*0 + 3*630*FLEN/8, x4, x1, x2)

inst_12151:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x92 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xc9700000; valaddr_reg:x3; val_offset:36453*0 + 3*631*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36453*0 + 3*631*FLEN/8, x4, x1, x2)

inst_12152:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x92 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xc9780000; valaddr_reg:x3; val_offset:36456*0 + 3*632*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36456*0 + 3*632*FLEN/8, x4, x1, x2)

inst_12153:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x92 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xc97c0000; valaddr_reg:x3; val_offset:36459*0 + 3*633*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36459*0 + 3*633*FLEN/8, x4, x1, x2)

inst_12154:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x92 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xc97e0000; valaddr_reg:x3; val_offset:36462*0 + 3*634*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36462*0 + 3*634*FLEN/8, x4, x1, x2)

inst_12155:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x92 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xc97f0000; valaddr_reg:x3; val_offset:36465*0 + 3*635*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36465*0 + 3*635*FLEN/8, x4, x1, x2)

inst_12156:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x92 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xc97f8000; valaddr_reg:x3; val_offset:36468*0 + 3*636*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36468*0 + 3*636*FLEN/8, x4, x1, x2)

inst_12157:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x92 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xc97fc000; valaddr_reg:x3; val_offset:36471*0 + 3*637*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36471*0 + 3*637*FLEN/8, x4, x1, x2)

inst_12158:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x92 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xc97fe000; valaddr_reg:x3; val_offset:36474*0 + 3*638*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36474*0 + 3*638*FLEN/8, x4, x1, x2)

inst_12159:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x92 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xc97ff000; valaddr_reg:x3; val_offset:36477*0 + 3*639*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36477*0 + 3*639*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_6)

inst_12160:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x92 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xc97ff800; valaddr_reg:x3; val_offset:36480*0 + 3*640*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36480*0 + 3*640*FLEN/8, x4, x1, x2)

inst_12161:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x92 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xc97ffc00; valaddr_reg:x3; val_offset:36483*0 + 3*641*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36483*0 + 3*641*FLEN/8, x4, x1, x2)

inst_12162:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x92 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xc97ffe00; valaddr_reg:x3; val_offset:36486*0 + 3*642*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36486*0 + 3*642*FLEN/8, x4, x1, x2)

inst_12163:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x92 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xc97fff00; valaddr_reg:x3; val_offset:36489*0 + 3*643*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36489*0 + 3*643*FLEN/8, x4, x1, x2)

inst_12164:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x92 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xc97fff80; valaddr_reg:x3; val_offset:36492*0 + 3*644*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36492*0 + 3*644*FLEN/8, x4, x1, x2)

inst_12165:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x92 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xc97fffc0; valaddr_reg:x3; val_offset:36495*0 + 3*645*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36495*0 + 3*645*FLEN/8, x4, x1, x2)

inst_12166:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x92 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xc97fffe0; valaddr_reg:x3; val_offset:36498*0 + 3*646*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36498*0 + 3*646*FLEN/8, x4, x1, x2)

inst_12167:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x92 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xc97ffff0; valaddr_reg:x3; val_offset:36501*0 + 3*647*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36501*0 + 3*647*FLEN/8, x4, x1, x2)

inst_12168:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x92 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xc97ffff8; valaddr_reg:x3; val_offset:36504*0 + 3*648*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36504*0 + 3*648*FLEN/8, x4, x1, x2)

inst_12169:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x92 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xc97ffffc; valaddr_reg:x3; val_offset:36507*0 + 3*649*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36507*0 + 3*649*FLEN/8, x4, x1, x2)

inst_12170:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x92 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xc97ffffe; valaddr_reg:x3; val_offset:36510*0 + 3*650*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36510*0 + 3*650*FLEN/8, x4, x1, x2)

inst_12171:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7c800c and fs2 == 1 and fe2 == 0x01 and fm2 == 0x01c62f and fs3 == 1 and fe3 == 0x92 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7c800c; op2val:0x8081c62f;
op3val:0xc97fffff; valaddr_reg:x3; val_offset:36513*0 + 3*651*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36513*0 + 3*651*FLEN/8, x4, x1, x2)

inst_12172:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x21800000; valaddr_reg:x3; val_offset:36516*0 + 3*652*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36516*0 + 3*652*FLEN/8, x4, x1, x2)

inst_12173:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x21800001; valaddr_reg:x3; val_offset:36519*0 + 3*653*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36519*0 + 3*653*FLEN/8, x4, x1, x2)

inst_12174:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x21800003; valaddr_reg:x3; val_offset:36522*0 + 3*654*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36522*0 + 3*654*FLEN/8, x4, x1, x2)

inst_12175:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x21800007; valaddr_reg:x3; val_offset:36525*0 + 3*655*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36525*0 + 3*655*FLEN/8, x4, x1, x2)

inst_12176:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x2180000f; valaddr_reg:x3; val_offset:36528*0 + 3*656*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36528*0 + 3*656*FLEN/8, x4, x1, x2)

inst_12177:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x2180001f; valaddr_reg:x3; val_offset:36531*0 + 3*657*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36531*0 + 3*657*FLEN/8, x4, x1, x2)

inst_12178:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x2180003f; valaddr_reg:x3; val_offset:36534*0 + 3*658*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36534*0 + 3*658*FLEN/8, x4, x1, x2)

inst_12179:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x2180007f; valaddr_reg:x3; val_offset:36537*0 + 3*659*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36537*0 + 3*659*FLEN/8, x4, x1, x2)

inst_12180:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x218000ff; valaddr_reg:x3; val_offset:36540*0 + 3*660*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36540*0 + 3*660*FLEN/8, x4, x1, x2)

inst_12181:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x218001ff; valaddr_reg:x3; val_offset:36543*0 + 3*661*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36543*0 + 3*661*FLEN/8, x4, x1, x2)

inst_12182:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x218003ff; valaddr_reg:x3; val_offset:36546*0 + 3*662*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36546*0 + 3*662*FLEN/8, x4, x1, x2)

inst_12183:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x218007ff; valaddr_reg:x3; val_offset:36549*0 + 3*663*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36549*0 + 3*663*FLEN/8, x4, x1, x2)

inst_12184:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x21800fff; valaddr_reg:x3; val_offset:36552*0 + 3*664*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36552*0 + 3*664*FLEN/8, x4, x1, x2)

inst_12185:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x21801fff; valaddr_reg:x3; val_offset:36555*0 + 3*665*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36555*0 + 3*665*FLEN/8, x4, x1, x2)

inst_12186:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x21803fff; valaddr_reg:x3; val_offset:36558*0 + 3*666*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36558*0 + 3*666*FLEN/8, x4, x1, x2)

inst_12187:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x21807fff; valaddr_reg:x3; val_offset:36561*0 + 3*667*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36561*0 + 3*667*FLEN/8, x4, x1, x2)

inst_12188:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x2180ffff; valaddr_reg:x3; val_offset:36564*0 + 3*668*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36564*0 + 3*668*FLEN/8, x4, x1, x2)

inst_12189:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x2181ffff; valaddr_reg:x3; val_offset:36567*0 + 3*669*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36567*0 + 3*669*FLEN/8, x4, x1, x2)

inst_12190:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x2183ffff; valaddr_reg:x3; val_offset:36570*0 + 3*670*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36570*0 + 3*670*FLEN/8, x4, x1, x2)

inst_12191:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x2187ffff; valaddr_reg:x3; val_offset:36573*0 + 3*671*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36573*0 + 3*671*FLEN/8, x4, x1, x2)

inst_12192:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x218fffff; valaddr_reg:x3; val_offset:36576*0 + 3*672*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36576*0 + 3*672*FLEN/8, x4, x1, x2)

inst_12193:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x219fffff; valaddr_reg:x3; val_offset:36579*0 + 3*673*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36579*0 + 3*673*FLEN/8, x4, x1, x2)

inst_12194:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x21bfffff; valaddr_reg:x3; val_offset:36582*0 + 3*674*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36582*0 + 3*674*FLEN/8, x4, x1, x2)

inst_12195:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x21c00000; valaddr_reg:x3; val_offset:36585*0 + 3*675*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36585*0 + 3*675*FLEN/8, x4, x1, x2)

inst_12196:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x21e00000; valaddr_reg:x3; val_offset:36588*0 + 3*676*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36588*0 + 3*676*FLEN/8, x4, x1, x2)

inst_12197:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x21f00000; valaddr_reg:x3; val_offset:36591*0 + 3*677*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36591*0 + 3*677*FLEN/8, x4, x1, x2)

inst_12198:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x21f80000; valaddr_reg:x3; val_offset:36594*0 + 3*678*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36594*0 + 3*678*FLEN/8, x4, x1, x2)

inst_12199:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x21fc0000; valaddr_reg:x3; val_offset:36597*0 + 3*679*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36597*0 + 3*679*FLEN/8, x4, x1, x2)

inst_12200:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x21fe0000; valaddr_reg:x3; val_offset:36600*0 + 3*680*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36600*0 + 3*680*FLEN/8, x4, x1, x2)

inst_12201:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x21ff0000; valaddr_reg:x3; val_offset:36603*0 + 3*681*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36603*0 + 3*681*FLEN/8, x4, x1, x2)

inst_12202:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x21ff8000; valaddr_reg:x3; val_offset:36606*0 + 3*682*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36606*0 + 3*682*FLEN/8, x4, x1, x2)

inst_12203:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x21ffc000; valaddr_reg:x3; val_offset:36609*0 + 3*683*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36609*0 + 3*683*FLEN/8, x4, x1, x2)

inst_12204:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x21ffe000; valaddr_reg:x3; val_offset:36612*0 + 3*684*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36612*0 + 3*684*FLEN/8, x4, x1, x2)

inst_12205:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x21fff000; valaddr_reg:x3; val_offset:36615*0 + 3*685*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36615*0 + 3*685*FLEN/8, x4, x1, x2)

inst_12206:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x21fff800; valaddr_reg:x3; val_offset:36618*0 + 3*686*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36618*0 + 3*686*FLEN/8, x4, x1, x2)

inst_12207:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x21fffc00; valaddr_reg:x3; val_offset:36621*0 + 3*687*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36621*0 + 3*687*FLEN/8, x4, x1, x2)

inst_12208:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x21fffe00; valaddr_reg:x3; val_offset:36624*0 + 3*688*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36624*0 + 3*688*FLEN/8, x4, x1, x2)

inst_12209:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x21ffff00; valaddr_reg:x3; val_offset:36627*0 + 3*689*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36627*0 + 3*689*FLEN/8, x4, x1, x2)

inst_12210:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x21ffff80; valaddr_reg:x3; val_offset:36630*0 + 3*690*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36630*0 + 3*690*FLEN/8, x4, x1, x2)

inst_12211:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x21ffffc0; valaddr_reg:x3; val_offset:36633*0 + 3*691*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36633*0 + 3*691*FLEN/8, x4, x1, x2)

inst_12212:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x21ffffe0; valaddr_reg:x3; val_offset:36636*0 + 3*692*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36636*0 + 3*692*FLEN/8, x4, x1, x2)

inst_12213:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x21fffff0; valaddr_reg:x3; val_offset:36639*0 + 3*693*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36639*0 + 3*693*FLEN/8, x4, x1, x2)

inst_12214:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x21fffff8; valaddr_reg:x3; val_offset:36642*0 + 3*694*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36642*0 + 3*694*FLEN/8, x4, x1, x2)

inst_12215:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x21fffffc; valaddr_reg:x3; val_offset:36645*0 + 3*695*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36645*0 + 3*695*FLEN/8, x4, x1, x2)

inst_12216:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x21fffffe; valaddr_reg:x3; val_offset:36648*0 + 3*696*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36648*0 + 3*696*FLEN/8, x4, x1, x2)

inst_12217:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x43 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x21ffffff; valaddr_reg:x3; val_offset:36651*0 + 3*697*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36651*0 + 3*697*FLEN/8, x4, x1, x2)

inst_12218:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x3f800001; valaddr_reg:x3; val_offset:36654*0 + 3*698*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36654*0 + 3*698*FLEN/8, x4, x1, x2)

inst_12219:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x3f800003; valaddr_reg:x3; val_offset:36657*0 + 3*699*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36657*0 + 3*699*FLEN/8, x4, x1, x2)

inst_12220:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x3f800007; valaddr_reg:x3; val_offset:36660*0 + 3*700*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36660*0 + 3*700*FLEN/8, x4, x1, x2)

inst_12221:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x3f999999; valaddr_reg:x3; val_offset:36663*0 + 3*701*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36663*0 + 3*701*FLEN/8, x4, x1, x2)

inst_12222:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x3fa49249; valaddr_reg:x3; val_offset:36666*0 + 3*702*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36666*0 + 3*702*FLEN/8, x4, x1, x2)

inst_12223:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x3fb33333; valaddr_reg:x3; val_offset:36669*0 + 3*703*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36669*0 + 3*703*FLEN/8, x4, x1, x2)

inst_12224:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x3fb6db6d; valaddr_reg:x3; val_offset:36672*0 + 3*704*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36672*0 + 3*704*FLEN/8, x4, x1, x2)

inst_12225:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x3fbbbbbb; valaddr_reg:x3; val_offset:36675*0 + 3*705*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36675*0 + 3*705*FLEN/8, x4, x1, x2)

inst_12226:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x3fc44444; valaddr_reg:x3; val_offset:36678*0 + 3*706*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36678*0 + 3*706*FLEN/8, x4, x1, x2)

inst_12227:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x3fcccccc; valaddr_reg:x3; val_offset:36681*0 + 3*707*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36681*0 + 3*707*FLEN/8, x4, x1, x2)

inst_12228:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x3fdb6db6; valaddr_reg:x3; val_offset:36684*0 + 3*708*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36684*0 + 3*708*FLEN/8, x4, x1, x2)

inst_12229:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x3fe66666; valaddr_reg:x3; val_offset:36687*0 + 3*709*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36687*0 + 3*709*FLEN/8, x4, x1, x2)

inst_12230:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x3fedb6db; valaddr_reg:x3; val_offset:36690*0 + 3*710*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36690*0 + 3*710*FLEN/8, x4, x1, x2)

inst_12231:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x3ffffff8; valaddr_reg:x3; val_offset:36693*0 + 3*711*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36693*0 + 3*711*FLEN/8, x4, x1, x2)

inst_12232:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x3ffffffc; valaddr_reg:x3; val_offset:36696*0 + 3*712*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36696*0 + 3*712*FLEN/8, x4, x1, x2)

inst_12233:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e2c3a and fs2 == 0 and fe2 == 0x01 and fm2 == 0x00eb90 and fs3 == 0 and fe3 == 0x7f and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e2c3a; op2val:0x80eb90;
op3val:0x3ffffffe; valaddr_reg:x3; val_offset:36699*0 + 3*713*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36699*0 + 3*713*FLEN/8, x4, x1, x2)

inst_12234:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0x800001; valaddr_reg:x3; val_offset:36702*0 + 3*714*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36702*0 + 3*714*FLEN/8, x4, x1, x2)

inst_12235:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0x800003; valaddr_reg:x3; val_offset:36705*0 + 3*715*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36705*0 + 3*715*FLEN/8, x4, x1, x2)

inst_12236:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0x800007; valaddr_reg:x3; val_offset:36708*0 + 3*716*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36708*0 + 3*716*FLEN/8, x4, x1, x2)

inst_12237:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0x999999; valaddr_reg:x3; val_offset:36711*0 + 3*717*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36711*0 + 3*717*FLEN/8, x4, x1, x2)

inst_12238:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0xa49249; valaddr_reg:x3; val_offset:36714*0 + 3*718*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36714*0 + 3*718*FLEN/8, x4, x1, x2)

inst_12239:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0xb33333; valaddr_reg:x3; val_offset:36717*0 + 3*719*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36717*0 + 3*719*FLEN/8, x4, x1, x2)

inst_12240:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0xb6db6d; valaddr_reg:x3; val_offset:36720*0 + 3*720*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36720*0 + 3*720*FLEN/8, x4, x1, x2)

inst_12241:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0xbbbbbb; valaddr_reg:x3; val_offset:36723*0 + 3*721*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36723*0 + 3*721*FLEN/8, x4, x1, x2)

inst_12242:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0xc44444; valaddr_reg:x3; val_offset:36726*0 + 3*722*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36726*0 + 3*722*FLEN/8, x4, x1, x2)

inst_12243:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0xcccccc; valaddr_reg:x3; val_offset:36729*0 + 3*723*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36729*0 + 3*723*FLEN/8, x4, x1, x2)

inst_12244:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0xdb6db6; valaddr_reg:x3; val_offset:36732*0 + 3*724*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36732*0 + 3*724*FLEN/8, x4, x1, x2)

inst_12245:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0xe66666; valaddr_reg:x3; val_offset:36735*0 + 3*725*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36735*0 + 3*725*FLEN/8, x4, x1, x2)

inst_12246:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0xedb6db; valaddr_reg:x3; val_offset:36738*0 + 3*726*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36738*0 + 3*726*FLEN/8, x4, x1, x2)

inst_12247:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0xfffff8; valaddr_reg:x3; val_offset:36741*0 + 3*727*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36741*0 + 3*727*FLEN/8, x4, x1, x2)

inst_12248:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0xfffffc; valaddr_reg:x3; val_offset:36744*0 + 3*728*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36744*0 + 3*728*FLEN/8, x4, x1, x2)

inst_12249:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0xfffffe; valaddr_reg:x3; val_offset:36747*0 + 3*729*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36747*0 + 3*729*FLEN/8, x4, x1, x2)

inst_12250:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0x3000000; valaddr_reg:x3; val_offset:36750*0 + 3*730*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36750*0 + 3*730*FLEN/8, x4, x1, x2)

inst_12251:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0x3000001; valaddr_reg:x3; val_offset:36753*0 + 3*731*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36753*0 + 3*731*FLEN/8, x4, x1, x2)

inst_12252:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0x3000003; valaddr_reg:x3; val_offset:36756*0 + 3*732*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36756*0 + 3*732*FLEN/8, x4, x1, x2)

inst_12253:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0x3000007; valaddr_reg:x3; val_offset:36759*0 + 3*733*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36759*0 + 3*733*FLEN/8, x4, x1, x2)

inst_12254:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0x300000f; valaddr_reg:x3; val_offset:36762*0 + 3*734*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36762*0 + 3*734*FLEN/8, x4, x1, x2)

inst_12255:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0x300001f; valaddr_reg:x3; val_offset:36765*0 + 3*735*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36765*0 + 3*735*FLEN/8, x4, x1, x2)

inst_12256:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0x300003f; valaddr_reg:x3; val_offset:36768*0 + 3*736*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36768*0 + 3*736*FLEN/8, x4, x1, x2)

inst_12257:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0x300007f; valaddr_reg:x3; val_offset:36771*0 + 3*737*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36771*0 + 3*737*FLEN/8, x4, x1, x2)

inst_12258:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0x30000ff; valaddr_reg:x3; val_offset:36774*0 + 3*738*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36774*0 + 3*738*FLEN/8, x4, x1, x2)

inst_12259:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0x30001ff; valaddr_reg:x3; val_offset:36777*0 + 3*739*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36777*0 + 3*739*FLEN/8, x4, x1, x2)

inst_12260:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0x30003ff; valaddr_reg:x3; val_offset:36780*0 + 3*740*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36780*0 + 3*740*FLEN/8, x4, x1, x2)

inst_12261:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0x30007ff; valaddr_reg:x3; val_offset:36783*0 + 3*741*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36783*0 + 3*741*FLEN/8, x4, x1, x2)

inst_12262:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0x3000fff; valaddr_reg:x3; val_offset:36786*0 + 3*742*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36786*0 + 3*742*FLEN/8, x4, x1, x2)

inst_12263:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0x3001fff; valaddr_reg:x3; val_offset:36789*0 + 3*743*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36789*0 + 3*743*FLEN/8, x4, x1, x2)

inst_12264:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0x3003fff; valaddr_reg:x3; val_offset:36792*0 + 3*744*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36792*0 + 3*744*FLEN/8, x4, x1, x2)

inst_12265:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0x3007fff; valaddr_reg:x3; val_offset:36795*0 + 3*745*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36795*0 + 3*745*FLEN/8, x4, x1, x2)

inst_12266:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0x300ffff; valaddr_reg:x3; val_offset:36798*0 + 3*746*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36798*0 + 3*746*FLEN/8, x4, x1, x2)

inst_12267:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0x301ffff; valaddr_reg:x3; val_offset:36801*0 + 3*747*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36801*0 + 3*747*FLEN/8, x4, x1, x2)

inst_12268:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0x303ffff; valaddr_reg:x3; val_offset:36804*0 + 3*748*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36804*0 + 3*748*FLEN/8, x4, x1, x2)

inst_12269:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0x307ffff; valaddr_reg:x3; val_offset:36807*0 + 3*749*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36807*0 + 3*749*FLEN/8, x4, x1, x2)

inst_12270:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0x30fffff; valaddr_reg:x3; val_offset:36810*0 + 3*750*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36810*0 + 3*750*FLEN/8, x4, x1, x2)

inst_12271:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0x31fffff; valaddr_reg:x3; val_offset:36813*0 + 3*751*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36813*0 + 3*751*FLEN/8, x4, x1, x2)

inst_12272:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0x33fffff; valaddr_reg:x3; val_offset:36816*0 + 3*752*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36816*0 + 3*752*FLEN/8, x4, x1, x2)

inst_12273:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0x3400000; valaddr_reg:x3; val_offset:36819*0 + 3*753*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36819*0 + 3*753*FLEN/8, x4, x1, x2)

inst_12274:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0x3600000; valaddr_reg:x3; val_offset:36822*0 + 3*754*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36822*0 + 3*754*FLEN/8, x4, x1, x2)

inst_12275:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0x3700000; valaddr_reg:x3; val_offset:36825*0 + 3*755*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36825*0 + 3*755*FLEN/8, x4, x1, x2)

inst_12276:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0x3780000; valaddr_reg:x3; val_offset:36828*0 + 3*756*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36828*0 + 3*756*FLEN/8, x4, x1, x2)

inst_12277:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0x37c0000; valaddr_reg:x3; val_offset:36831*0 + 3*757*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36831*0 + 3*757*FLEN/8, x4, x1, x2)

inst_12278:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0x37e0000; valaddr_reg:x3; val_offset:36834*0 + 3*758*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36834*0 + 3*758*FLEN/8, x4, x1, x2)

inst_12279:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0x37f0000; valaddr_reg:x3; val_offset:36837*0 + 3*759*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36837*0 + 3*759*FLEN/8, x4, x1, x2)

inst_12280:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0x37f8000; valaddr_reg:x3; val_offset:36840*0 + 3*760*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36840*0 + 3*760*FLEN/8, x4, x1, x2)

inst_12281:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0x37fc000; valaddr_reg:x3; val_offset:36843*0 + 3*761*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36843*0 + 3*761*FLEN/8, x4, x1, x2)

inst_12282:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0x37fe000; valaddr_reg:x3; val_offset:36846*0 + 3*762*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36846*0 + 3*762*FLEN/8, x4, x1, x2)

inst_12283:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0x37ff000; valaddr_reg:x3; val_offset:36849*0 + 3*763*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36849*0 + 3*763*FLEN/8, x4, x1, x2)

inst_12284:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0x37ff800; valaddr_reg:x3; val_offset:36852*0 + 3*764*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36852*0 + 3*764*FLEN/8, x4, x1, x2)

inst_12285:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0x37ffc00; valaddr_reg:x3; val_offset:36855*0 + 3*765*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36855*0 + 3*765*FLEN/8, x4, x1, x2)

inst_12286:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0x37ffe00; valaddr_reg:x3; val_offset:36858*0 + 3*766*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36858*0 + 3*766*FLEN/8, x4, x1, x2)

inst_12287:
// fs1 == 0 and fe1 == 0xfc and fm1 == 0x7e9193 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x06 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e7e9193; op2val:0x0;
op3val:0x37fff00; valaddr_reg:x3; val_offset:36861*0 + 3*767*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 36861*0 + 3*767*FLEN/8, x4, x1, x2)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0x7e71e169,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x333333,32,FLEN)
NAN_BOXED(0x7e71e169,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x36db6d,32,FLEN)
NAN_BOXED(0x7e71e169,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3bbbbb,32,FLEN)
NAN_BOXED(0x7e71e169,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3fffff,32,FLEN)
NAN_BOXED(0x7e71e169,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x400000,32,FLEN)
NAN_BOXED(0x7e71e169,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x444444,32,FLEN)
NAN_BOXED(0x7e71e169,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4ccccc,32,FLEN)
NAN_BOXED(0x7e71e169,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5b6db6,32,FLEN)
NAN_BOXED(0x7e71e169,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x600000,32,FLEN)
NAN_BOXED(0x7e71e169,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x666666,32,FLEN)
NAN_BOXED(0x7e71e169,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6db6db,32,FLEN)
NAN_BOXED(0x7e71e169,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x700000,32,FLEN)
NAN_BOXED(0x7e71e169,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x780000,32,FLEN)
NAN_BOXED(0x7e71e169,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7c0000,32,FLEN)
NAN_BOXED(0x7e71e169,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7e0000,32,FLEN)
NAN_BOXED(0x7e71e169,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7f0000,32,FLEN)
NAN_BOXED(0x7e71e169,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7f8000,32,FLEN)
NAN_BOXED(0x7e71e169,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fc000,32,FLEN)
NAN_BOXED(0x7e71e169,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fe000,32,FLEN)
NAN_BOXED(0x7e71e169,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ff000,32,FLEN)
NAN_BOXED(0x7e71e169,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ff800,32,FLEN)
NAN_BOXED(0x7e71e169,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffc00,32,FLEN)
NAN_BOXED(0x7e71e169,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffe00,32,FLEN)
NAN_BOXED(0x7e71e169,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fff00,32,FLEN)
NAN_BOXED(0x7e71e169,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fff80,32,FLEN)
NAN_BOXED(0x7e71e169,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fffc0,32,FLEN)
NAN_BOXED(0x7e71e169,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fffe0,32,FLEN)
NAN_BOXED(0x7e71e169,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffff0,32,FLEN)
NAN_BOXED(0x7e71e169,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffff8,32,FLEN)
NAN_BOXED(0x7e71e169,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffc,32,FLEN)
NAN_BOXED(0x7e71e169,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffe,32,FLEN)
NAN_BOXED(0x7e71e169,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7fffff,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xbf800001,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xbf800003,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xbf800007,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xbf999999,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xbfa49249,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xbfb33333,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xbfb6db6d,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xbfbbbbbb,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xbfc44444,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xbfcccccc,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xbfdb6db6,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xbfe66666,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xbfedb6db,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xbffffff8,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xbffffffc,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xbffffffe,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xc5800000,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xc5800001,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xc5800003,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xc5800007,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xc580000f,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xc580001f,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xc580003f,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xc580007f,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xc58000ff,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xc58001ff,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xc58003ff,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xc58007ff,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xc5800fff,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xc5801fff,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xc5803fff,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xc5807fff,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xc580ffff,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xc581ffff,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xc583ffff,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xc587ffff,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xc58fffff,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xc59fffff,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xc5bfffff,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xc5c00000,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xc5e00000,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xc5f00000,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xc5f80000,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xc5fc0000,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xc5fe0000,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xc5ff0000,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xc5ff8000,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xc5ffc000,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xc5ffe000,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xc5fff000,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xc5fff800,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xc5fffc00,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xc5fffe00,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xc5ffff00,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xc5ffff80,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xc5ffffc0,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xc5ffffe0,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xc5fffff0,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xc5fffff8,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xc5fffffc,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xc5fffffe,32,FLEN)
NAN_BOXED(0x7e729bb9,32,FLEN)
NAN_BOXED(0x808710c1,32,FLEN)
NAN_BOXED(0xc5ffffff,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x6d000000,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x6d000001,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x6d000003,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x6d000007,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x6d00000f,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x6d00001f,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x6d00003f,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x6d00007f,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x6d0000ff,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x6d0001ff,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x6d0003ff,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x6d0007ff,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x6d000fff,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x6d001fff,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x6d003fff,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x6d007fff,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x6d00ffff,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x6d01ffff,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x6d03ffff,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x6d07ffff,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x6d0fffff,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x6d1fffff,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x6d3fffff,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x6d400000,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x6d600000,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x6d700000,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x6d780000,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x6d7c0000,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x6d7e0000,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x6d7f0000,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x6d7f8000,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x6d7fc000,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x6d7fe000,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x6d7ff000,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x6d7ff800,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x6d7ffc00,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x6d7ffe00,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x6d7fff00,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x6d7fff80,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x6d7fffc0,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x6d7fffe0,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x6d7ffff0,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x6d7ffff8,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x6d7ffffc,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x6d7ffffe,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x6d7fffff,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x7f000001,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x7f000003,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x7f000007,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x7f199999,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x7f249249,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x7f333333,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x7f36db6d,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x7f3bbbbb,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x7f444444,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x7f4ccccc,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x7f5b6db6,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x7f666666,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x7f6db6db,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x7f7ffff8,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x7f7ffffc,32,FLEN)
NAN_BOXED(0x7e72a5cd,32,FLEN)
NAN_BOXED(0x40870b24,32,FLEN)
NAN_BOXED(0x7f7ffffe,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x199999,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x249249,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x333333,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x36db6d,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3bbbbb,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x444444,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4ccccc,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5b6db6,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x666666,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6db6db,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffff8,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffc,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffe,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb800000,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb800001,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb800003,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb800007,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb80000f,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb80001f,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb80003f,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb80007f,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb8000ff,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb8001ff,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb8003ff,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb8007ff,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb800fff,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb801fff,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb803fff,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb807fff,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb80ffff,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb81ffff,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb83ffff,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb87ffff,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb8fffff,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb9fffff,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbbfffff,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbc00000,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbe00000,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbf00000,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbf80000,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbfc0000,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbfe0000,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbff0000,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbff8000,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbffc000,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbffe000,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbfff000,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbfff800,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbfffc00,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbfffe00,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbffff00,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbffff80,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbffffc0,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbffffe0,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbfffff0,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbfffff8,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbfffffc,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbfffffe,32,FLEN)
NAN_BOXED(0x7e748605,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbffffff,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800001,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800003,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800007,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x999999,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa49249,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb33333,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb6db6d,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbbbbbb,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xc44444,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xcccccc,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xdb6db6,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe66666,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xedb6db,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffff8,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffffc,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffffe,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6800000,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6800001,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6800003,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6800007,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x680000f,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x680001f,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x680003f,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x680007f,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x68000ff,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x68001ff,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x68003ff,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x68007ff,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6800fff,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6801fff,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6803fff,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6807fff,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x680ffff,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x681ffff,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x683ffff,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x687ffff,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x68fffff,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x69fffff,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6bfffff,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6c00000,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6e00000,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6f00000,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6f80000,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6fc0000,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6fe0000,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6ff0000,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6ff8000,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6ffc000,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6ffe000,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6fff000,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6fff800,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6fffc00,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6fffe00,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6ffff00,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6ffff80,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6ffffc0,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6ffffe0,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6fffff0,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6fffff8,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6fffffc,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6fffffe,32,FLEN)
NAN_BOXED(0x7e74d94c,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6ffffff,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3c800000,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3c800001,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3c800003,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3c800007,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3c80000f,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3c80001f,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3c80003f,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3c80007f,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3c8000ff,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3c8001ff,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3c8003ff,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3c8007ff,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3c800fff,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3c801fff,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3c803fff,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3c807fff,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3c80ffff,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3c81ffff,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3c83ffff,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3c87ffff,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3c8fffff,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3c9fffff,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3cbfffff,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3cc00000,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3ce00000,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3cf00000,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3cf80000,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3cfc0000,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3cfe0000,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3cff0000,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3cff8000,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3cffc000,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3cffe000,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3cfff000,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3cfff800,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3cfffc00,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3cfffe00,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3cffff00,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3cffff80,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3cffffc0,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3cffffe0,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3cfffff0,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3cfffff8,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3cfffffc,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3cfffffe,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3cffffff,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3f800001,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3f800003,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3f800007,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3f999999,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3fa49249,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3fb33333,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3fb6db6d,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3fbbbbbb,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3fc44444,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3fcccccc,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3fdb6db6,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3fe66666,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3fedb6db,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3ffffff8,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3ffffffc,32,FLEN)
NAN_BOXED(0x7e75c78c,32,FLEN)
NAN_BOXED(0x8552a0,32,FLEN)
NAN_BOXED(0x3ffffffe,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x3f800001,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x3f800003,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x3f800007,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x3f999999,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x3fa49249,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x3fb33333,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x3fb6db6d,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x3fbbbbbb,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x3fc44444,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x3fcccccc,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x3fdb6db6,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x3fe66666,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x3fedb6db,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x3ffffff8,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x3ffffffc,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x3ffffffe,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x46000000,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x46000001,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x46000003,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x46000007,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x4600000f,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x4600001f,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x4600003f,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x4600007f,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x460000ff,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x460001ff,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x460003ff,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x460007ff,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x46000fff,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x46001fff,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x46003fff,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x46007fff,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x4600ffff,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x4601ffff,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x4603ffff,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x4607ffff,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x460fffff,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x461fffff,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x463fffff,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x46400000,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x46600000,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x46700000,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x46780000,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x467c0000,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x467e0000,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x467f0000,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x467f8000,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x467fc000,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x467fe000,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x467ff000,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x467ff800,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x467ffc00,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x467ffe00,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x467fff00,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x467fff80,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x467fffc0,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x467fffe0,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x467ffff0,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x467ffff8,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x467ffffc,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x467ffffe,32,FLEN)
NAN_BOXED(0x7e774515,32,FLEN)
NAN_BOXED(0x8484e8,32,FLEN)
NAN_BOXED(0x467fffff,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000001,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000003,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000007,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80199999,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80249249,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80333333,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8036db6d,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x803bbbbb,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80444444,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x804ccccc,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x805b6db6,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80666666,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x806db6db,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffff8,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffc,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffe,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x88000000,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x88000001,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x88000003,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x88000007,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8800000f,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8800001f,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8800003f,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8800007f,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x880000ff,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x880001ff,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x880003ff,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x880007ff,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x88000fff,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x88001fff,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x88003fff,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x88007fff,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8800ffff,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8801ffff,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8803ffff,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8807ffff,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x880fffff,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x881fffff,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x883fffff,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x88400000,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x88600000,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x88700000,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x88780000,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x887c0000,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x887e0000,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x887f0000,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x887f8000,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x887fc000,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x887fe000,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x887ff000,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x887ff800,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x887ffc00,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x887ffe00,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x887fff00,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x887fff80,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x887fffc0,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x887fffe0,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x887ffff0,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x887ffff8,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x887ffffc,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x887ffffe,32,FLEN)
NAN_BOXED(0x7e790586,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x887fffff,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x199999,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x249249,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x333333,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x36db6d,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3bbbbb,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x444444,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4ccccc,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5b6db6,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x666666,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6db6db,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffff8,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffc,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffe,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5800000,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5800001,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5800003,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5800007,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x580000f,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x580001f,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x580003f,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x580007f,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x58000ff,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x58001ff,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x58003ff,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x58007ff,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5800fff,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5801fff,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5803fff,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5807fff,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x580ffff,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x581ffff,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x583ffff,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x587ffff,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x58fffff,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x59fffff,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5bfffff,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5c00000,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5e00000,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5f00000,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5f80000,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5fc0000,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5fe0000,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5ff0000,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5ff8000,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5ffc000,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5ffe000,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5fff000,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5fff800,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5fffc00,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5fffe00,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5ffff00,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5ffff80,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5ffffc0,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5ffffe0,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5fffff0,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5fffff8,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5fffffc,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5fffffe,32,FLEN)
NAN_BOXED(0x7e7a08a9,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5ffffff,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7e800000,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7e800001,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7e800003,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7e800007,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7e80000f,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7e80001f,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7e80003f,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7e80007f,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7e8000ff,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7e8001ff,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7e8003ff,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7e8007ff,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7e800fff,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7e801fff,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7e803fff,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7e807fff,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7e80ffff,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7e81ffff,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7e83ffff,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7e87ffff,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7e8fffff,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7e9fffff,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7ebfffff,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7ec00000,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7ee00000,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7ef00000,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7ef80000,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7efc0000,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7efe0000,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7eff0000,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7eff8000,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7effc000,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7effe000,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7efff000,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7efff800,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7efffc00,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7efffe00,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7effff00,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7effff80,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7effffc0,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7effffe0,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7efffff0,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7efffff8,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7efffffc,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7efffffe,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7effffff,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7f000001,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7f000003,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7f000007,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7f199999,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7f249249,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7f333333,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7f36db6d,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7f3bbbbb,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7f444444,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7f4ccccc,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7f5b6db6,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7f666666,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7f6db6db,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7f7ffff8,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7f7ffffc,32,FLEN)
NAN_BOXED(0x7e7c2bb2,32,FLEN)
NAN_BOXED(0x4081f197,32,FLEN)
NAN_BOXED(0x7f7ffffe,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xbf800001,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xbf800003,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xbf800007,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xbf999999,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xbfa49249,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xbfb33333,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xbfb6db6d,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xbfbbbbbb,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xbfc44444,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xbfcccccc,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xbfdb6db6,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xbfe66666,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xbfedb6db,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xbffffff8,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xbffffffc,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xbffffffe,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xc9000000,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xc9000001,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xc9000003,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xc9000007,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xc900000f,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xc900001f,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xc900003f,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xc900007f,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xc90000ff,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xc90001ff,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xc90003ff,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xc90007ff,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xc9000fff,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xc9001fff,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xc9003fff,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xc9007fff,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xc900ffff,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xc901ffff,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xc903ffff,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xc907ffff,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xc90fffff,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xc91fffff,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xc93fffff,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xc9400000,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xc9600000,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xc9700000,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xc9780000,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xc97c0000,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xc97e0000,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xc97f0000,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xc97f8000,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xc97fc000,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xc97fe000,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xc97ff000,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xc97ff800,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xc97ffc00,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xc97ffe00,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xc97fff00,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xc97fff80,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xc97fffc0,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xc97fffe0,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xc97ffff0,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xc97ffff8,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xc97ffffc,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xc97ffffe,32,FLEN)
NAN_BOXED(0x7e7c800c,32,FLEN)
NAN_BOXED(0x8081c62f,32,FLEN)
NAN_BOXED(0xc97fffff,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x21800000,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x21800001,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x21800003,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x21800007,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x2180000f,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x2180001f,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x2180003f,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x2180007f,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x218000ff,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x218001ff,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x218003ff,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x218007ff,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x21800fff,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x21801fff,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x21803fff,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x21807fff,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x2180ffff,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x2181ffff,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x2183ffff,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x2187ffff,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x218fffff,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x219fffff,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x21bfffff,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x21c00000,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x21e00000,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x21f00000,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x21f80000,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x21fc0000,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x21fe0000,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x21ff0000,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x21ff8000,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x21ffc000,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x21ffe000,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x21fff000,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x21fff800,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x21fffc00,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x21fffe00,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x21ffff00,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x21ffff80,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x21ffffc0,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x21ffffe0,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x21fffff0,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x21fffff8,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x21fffffc,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x21fffffe,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x21ffffff,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x3f800001,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x3f800003,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x3f800007,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x3f999999,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x3fa49249,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x3fb33333,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x3fb6db6d,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x3fbbbbbb,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x3fc44444,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x3fcccccc,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x3fdb6db6,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x3fe66666,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x3fedb6db,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x3ffffff8,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x3ffffffc,32,FLEN)
NAN_BOXED(0x7e7e2c3a,32,FLEN)
NAN_BOXED(0x80eb90,32,FLEN)
NAN_BOXED(0x3ffffffe,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800001,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800003,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800007,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x999999,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xa49249,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb33333,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xb6db6d,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xbbbbbb,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xc44444,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xcccccc,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xdb6db6,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe66666,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xedb6db,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffff8,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffffc,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xfffffe,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3000000,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3000001,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3000003,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3000007,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x300000f,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x300001f,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x300003f,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x300007f,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x30000ff,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x30001ff,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x30003ff,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x30007ff,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3000fff,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3001fff,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3003fff,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3007fff,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x300ffff,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x301ffff,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x303ffff,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x307ffff,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x30fffff,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x31fffff,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x33fffff,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3400000,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3600000,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3700000,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3780000,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x37c0000,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x37e0000,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x37f0000,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x37f8000,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x37fc000,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x37fe000,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x37ff000,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x37ff800,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x37ffc00,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x37ffe00,32,FLEN)
NAN_BOXED(0x7e7e9193,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x37fff00,32,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;


signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_2:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_3:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_4:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_5:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_6:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine

tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
    .fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;

#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif

sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
