
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.11.0
// timestamp : Wed Feb  7 04:34:04 2024 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/rv32h_fnmadd.cgf \
 \
//                  -- xlen 32  \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fnmadd.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV32FD_Zicsr,RV64F_Zicsr_Zfh,RV64FD_Zicsr extension for the fnmadd_b15 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV32IFD_Zicsr,RV64IF_Zicsr_Zfh,RV64IFD_Zicsr")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fnmadd_b15)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_9204:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x205 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x14f and fs3 == 1 and fe3 == 0x14 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a05; op2val:0xbd4f;
op3val:0xd000; valaddr_reg:x3; val_offset:27612*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27612*FLEN/8, x4, x1, x2)

inst_9205:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x205 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x14f and fs3 == 1 and fe3 == 0x14 and fm3 == 0x1ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a05; op2val:0xbd4f;
op3val:0xd1ff; valaddr_reg:x3; val_offset:27615*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27615*FLEN/8, x4, x1, x2)

inst_9206:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x205 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x14f and fs3 == 1 and fe3 == 0x14 and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a05; op2val:0xbd4f;
op3val:0xd200; valaddr_reg:x3; val_offset:27618*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27618*FLEN/8, x4, x1, x2)

inst_9207:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x205 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x14f and fs3 == 1 and fe3 == 0x14 and fm3 == 0x0ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a05; op2val:0xbd4f;
op3val:0xd0ff; valaddr_reg:x3; val_offset:27621*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27621*FLEN/8, x4, x1, x2)

inst_9208:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x205 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x14f and fs3 == 1 and fe3 == 0x14 and fm3 == 0x300 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a05; op2val:0xbd4f;
op3val:0xd300; valaddr_reg:x3; val_offset:27624*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27624*FLEN/8, x4, x1, x2)

inst_9209:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x205 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x14f and fs3 == 1 and fe3 == 0x14 and fm3 == 0x07f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a05; op2val:0xbd4f;
op3val:0xd07f; valaddr_reg:x3; val_offset:27627*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27627*FLEN/8, x4, x1, x2)

inst_9210:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x205 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x14f and fs3 == 1 and fe3 == 0x14 and fm3 == 0x380 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a05; op2val:0xbd4f;
op3val:0xd380; valaddr_reg:x3; val_offset:27630*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27630*FLEN/8, x4, x1, x2)

inst_9211:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x205 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x14f and fs3 == 1 and fe3 == 0x14 and fm3 == 0x03f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a05; op2val:0xbd4f;
op3val:0xd03f; valaddr_reg:x3; val_offset:27633*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27633*FLEN/8, x4, x1, x2)

inst_9212:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x205 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x14f and fs3 == 1 and fe3 == 0x14 and fm3 == 0x3c0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a05; op2val:0xbd4f;
op3val:0xd3c0; valaddr_reg:x3; val_offset:27636*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27636*FLEN/8, x4, x1, x2)

inst_9213:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x205 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x14f and fs3 == 1 and fe3 == 0x14 and fm3 == 0x01f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a05; op2val:0xbd4f;
op3val:0xd01f; valaddr_reg:x3; val_offset:27639*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27639*FLEN/8, x4, x1, x2)

inst_9214:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x205 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x14f and fs3 == 1 and fe3 == 0x14 and fm3 == 0x3e0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a05; op2val:0xbd4f;
op3val:0xd3e0; valaddr_reg:x3; val_offset:27642*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27642*FLEN/8, x4, x1, x2)

inst_9215:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x205 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x14f and fs3 == 1 and fe3 == 0x14 and fm3 == 0x00f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a05; op2val:0xbd4f;
op3val:0xd00f; valaddr_reg:x3; val_offset:27645*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27645*FLEN/8, x4, x1, x2)

RVTEST_SIGBASE(x1,signature_x1_73)
inst_9216:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x205 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x14f and fs3 == 1 and fe3 == 0x14 and fm3 == 0x3f0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a05; op2val:0xbd4f;
op3val:0xd3f0; valaddr_reg:x3; val_offset:27648*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27648*FLEN/8, x4, x1, x2)

inst_9217:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x205 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x14f and fs3 == 1 and fe3 == 0x14 and fm3 == 0x007 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a05; op2val:0xbd4f;
op3val:0xd007; valaddr_reg:x3; val_offset:27651*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27651*FLEN/8, x4, x1, x2)

inst_9218:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x205 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x14f and fs3 == 1 and fe3 == 0x14 and fm3 == 0x3f8 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a05; op2val:0xbd4f;
op3val:0xd3f8; valaddr_reg:x3; val_offset:27654*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27654*FLEN/8, x4, x1, x2)

inst_9219:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x205 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x14f and fs3 == 1 and fe3 == 0x14 and fm3 == 0x003 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a05; op2val:0xbd4f;
op3val:0xd003; valaddr_reg:x3; val_offset:27657*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27657*FLEN/8, x4, x1, x2)

inst_9220:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x205 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x14f and fs3 == 1 and fe3 == 0x14 and fm3 == 0x3fc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a05; op2val:0xbd4f;
op3val:0xd3fc; valaddr_reg:x3; val_offset:27660*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27660*FLEN/8, x4, x1, x2)

inst_9221:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x205 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x14f and fs3 == 1 and fe3 == 0x14 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a05; op2val:0xbd4f;
op3val:0xd001; valaddr_reg:x3; val_offset:27663*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27663*FLEN/8, x4, x1, x2)

inst_9222:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x205 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x14f and fs3 == 1 and fe3 == 0x14 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a05; op2val:0xbd4f;
op3val:0xd3fe; valaddr_reg:x3; val_offset:27666*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27666*FLEN/8, x4, x1, x2)

inst_9223:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x205 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x14f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a05; op2val:0xbd4f;
op3val:0xfbfe; valaddr_reg:x3; val_offset:27669*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27669*FLEN/8, x4, x1, x2)

inst_9224:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x205 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x14f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a05; op2val:0xbd4f;
op3val:0xf801; valaddr_reg:x3; val_offset:27672*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27672*FLEN/8, x4, x1, x2)

inst_9225:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x205 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x14f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1b6 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a05; op2val:0xbd4f;
op3val:0xf9b6; valaddr_reg:x3; val_offset:27675*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27675*FLEN/8, x4, x1, x2)

inst_9226:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x205 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x14f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x36d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a05; op2val:0xbd4f;
op3val:0xfb6d; valaddr_reg:x3; val_offset:27678*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27678*FLEN/8, x4, x1, x2)

inst_9227:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x205 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x14f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x0cc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a05; op2val:0xbd4f;
op3val:0xf8cc; valaddr_reg:x3; val_offset:27681*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27681*FLEN/8, x4, x1, x2)

inst_9228:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x205 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x14f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x333 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a05; op2val:0xbd4f;
op3val:0xfb33; valaddr_reg:x3; val_offset:27684*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27684*FLEN/8, x4, x1, x2)

inst_9229:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x205 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x14f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1dd and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a05; op2val:0xbd4f;
op3val:0xf9dd; valaddr_reg:x3; val_offset:27687*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27687*FLEN/8, x4, x1, x2)

inst_9230:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x205 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x14f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x222 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a05; op2val:0xbd4f;
op3val:0xfa22; valaddr_reg:x3; val_offset:27690*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27690*FLEN/8, x4, x1, x2)

inst_9231:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x205 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x14f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x124 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a05; op2val:0xbd4f;
op3val:0xf924; valaddr_reg:x3; val_offset:27693*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27693*FLEN/8, x4, x1, x2)

inst_9232:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x205 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x14f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x2db and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a05; op2val:0xbd4f;
op3val:0xfadb; valaddr_reg:x3; val_offset:27696*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27696*FLEN/8, x4, x1, x2)

inst_9233:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x205 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x14f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x199 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a05; op2val:0xbd4f;
op3val:0xf999; valaddr_reg:x3; val_offset:27699*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27699*FLEN/8, x4, x1, x2)

inst_9234:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x205 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x14f and fs3 == 1 and fe3 == 0x1e and fm3 == 0x266 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a05; op2val:0xbd4f;
op3val:0xfa66; valaddr_reg:x3; val_offset:27702*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27702*FLEN/8, x4, x1, x2)

inst_9235:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ca and fs2 == 1 and fe2 == 0x12 and fm2 == 0x186 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6dca; op2val:0xc986;
op3val:0xd7ff; valaddr_reg:x3; val_offset:27705*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27705*FLEN/8, x4, x1, x2)

inst_9236:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ca and fs2 == 1 and fe2 == 0x12 and fm2 == 0x186 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6dca; op2val:0xc986;
op3val:0xd400; valaddr_reg:x3; val_offset:27708*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27708*FLEN/8, x4, x1, x2)

inst_9237:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ca and fs2 == 1 and fe2 == 0x12 and fm2 == 0x186 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x1ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6dca; op2val:0xc986;
op3val:0xd5ff; valaddr_reg:x3; val_offset:27711*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27711*FLEN/8, x4, x1, x2)

inst_9238:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ca and fs2 == 1 and fe2 == 0x12 and fm2 == 0x186 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6dca; op2val:0xc986;
op3val:0xd600; valaddr_reg:x3; val_offset:27714*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27714*FLEN/8, x4, x1, x2)

inst_9239:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ca and fs2 == 1 and fe2 == 0x12 and fm2 == 0x186 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x0ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6dca; op2val:0xc986;
op3val:0xd4ff; valaddr_reg:x3; val_offset:27717*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27717*FLEN/8, x4, x1, x2)

inst_9240:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ca and fs2 == 1 and fe2 == 0x12 and fm2 == 0x186 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x300 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6dca; op2val:0xc986;
op3val:0xd700; valaddr_reg:x3; val_offset:27720*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27720*FLEN/8, x4, x1, x2)

inst_9241:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ca and fs2 == 1 and fe2 == 0x12 and fm2 == 0x186 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x07f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6dca; op2val:0xc986;
op3val:0xd47f; valaddr_reg:x3; val_offset:27723*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27723*FLEN/8, x4, x1, x2)

inst_9242:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ca and fs2 == 1 and fe2 == 0x12 and fm2 == 0x186 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x380 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6dca; op2val:0xc986;
op3val:0xd780; valaddr_reg:x3; val_offset:27726*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27726*FLEN/8, x4, x1, x2)

inst_9243:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ca and fs2 == 1 and fe2 == 0x12 and fm2 == 0x186 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x03f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6dca; op2val:0xc986;
op3val:0xd43f; valaddr_reg:x3; val_offset:27729*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27729*FLEN/8, x4, x1, x2)

inst_9244:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ca and fs2 == 1 and fe2 == 0x12 and fm2 == 0x186 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x3c0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6dca; op2val:0xc986;
op3val:0xd7c0; valaddr_reg:x3; val_offset:27732*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27732*FLEN/8, x4, x1, x2)

inst_9245:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ca and fs2 == 1 and fe2 == 0x12 and fm2 == 0x186 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x01f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6dca; op2val:0xc986;
op3val:0xd41f; valaddr_reg:x3; val_offset:27735*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27735*FLEN/8, x4, x1, x2)

inst_9246:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ca and fs2 == 1 and fe2 == 0x12 and fm2 == 0x186 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x3e0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6dca; op2val:0xc986;
op3val:0xd7e0; valaddr_reg:x3; val_offset:27738*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27738*FLEN/8, x4, x1, x2)

inst_9247:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ca and fs2 == 1 and fe2 == 0x12 and fm2 == 0x186 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x00f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6dca; op2val:0xc986;
op3val:0xd40f; valaddr_reg:x3; val_offset:27741*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27741*FLEN/8, x4, x1, x2)

inst_9248:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ca and fs2 == 1 and fe2 == 0x12 and fm2 == 0x186 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x3f0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6dca; op2val:0xc986;
op3val:0xd7f0; valaddr_reg:x3; val_offset:27744*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27744*FLEN/8, x4, x1, x2)

inst_9249:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ca and fs2 == 1 and fe2 == 0x12 and fm2 == 0x186 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x007 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6dca; op2val:0xc986;
op3val:0xd407; valaddr_reg:x3; val_offset:27747*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27747*FLEN/8, x4, x1, x2)

inst_9250:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ca and fs2 == 1 and fe2 == 0x12 and fm2 == 0x186 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x3f8 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6dca; op2val:0xc986;
op3val:0xd7f8; valaddr_reg:x3; val_offset:27750*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27750*FLEN/8, x4, x1, x2)

inst_9251:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ca and fs2 == 1 and fe2 == 0x12 and fm2 == 0x186 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x003 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6dca; op2val:0xc986;
op3val:0xd403; valaddr_reg:x3; val_offset:27753*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27753*FLEN/8, x4, x1, x2)

inst_9252:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ca and fs2 == 1 and fe2 == 0x12 and fm2 == 0x186 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x3fc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6dca; op2val:0xc986;
op3val:0xd7fc; valaddr_reg:x3; val_offset:27756*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27756*FLEN/8, x4, x1, x2)

inst_9253:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ca and fs2 == 1 and fe2 == 0x12 and fm2 == 0x186 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6dca; op2val:0xc986;
op3val:0xd401; valaddr_reg:x3; val_offset:27759*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27759*FLEN/8, x4, x1, x2)

inst_9254:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ca and fs2 == 1 and fe2 == 0x12 and fm2 == 0x186 and fs3 == 1 and fe3 == 0x15 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6dca; op2val:0xc986;
op3val:0xd7fe; valaddr_reg:x3; val_offset:27762*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27762*FLEN/8, x4, x1, x2)

inst_9255:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ca and fs2 == 1 and fe2 == 0x12 and fm2 == 0x186 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6dca; op2val:0xc986;
op3val:0xfbfe; valaddr_reg:x3; val_offset:27765*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27765*FLEN/8, x4, x1, x2)

inst_9256:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ca and fs2 == 1 and fe2 == 0x12 and fm2 == 0x186 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6dca; op2val:0xc986;
op3val:0xf801; valaddr_reg:x3; val_offset:27768*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27768*FLEN/8, x4, x1, x2)

inst_9257:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ca and fs2 == 1 and fe2 == 0x12 and fm2 == 0x186 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1b6 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6dca; op2val:0xc986;
op3val:0xf9b6; valaddr_reg:x3; val_offset:27771*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27771*FLEN/8, x4, x1, x2)

inst_9258:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ca and fs2 == 1 and fe2 == 0x12 and fm2 == 0x186 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x36d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6dca; op2val:0xc986;
op3val:0xfb6d; valaddr_reg:x3; val_offset:27774*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27774*FLEN/8, x4, x1, x2)

inst_9259:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ca and fs2 == 1 and fe2 == 0x12 and fm2 == 0x186 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x0cc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6dca; op2val:0xc986;
op3val:0xf8cc; valaddr_reg:x3; val_offset:27777*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27777*FLEN/8, x4, x1, x2)

inst_9260:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ca and fs2 == 1 and fe2 == 0x12 and fm2 == 0x186 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x333 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6dca; op2val:0xc986;
op3val:0xfb33; valaddr_reg:x3; val_offset:27780*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27780*FLEN/8, x4, x1, x2)

inst_9261:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ca and fs2 == 1 and fe2 == 0x12 and fm2 == 0x186 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1dd and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6dca; op2val:0xc986;
op3val:0xf9dd; valaddr_reg:x3; val_offset:27783*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27783*FLEN/8, x4, x1, x2)

inst_9262:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ca and fs2 == 1 and fe2 == 0x12 and fm2 == 0x186 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x222 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6dca; op2val:0xc986;
op3val:0xfa22; valaddr_reg:x3; val_offset:27786*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27786*FLEN/8, x4, x1, x2)

inst_9263:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ca and fs2 == 1 and fe2 == 0x12 and fm2 == 0x186 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x124 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6dca; op2val:0xc986;
op3val:0xf924; valaddr_reg:x3; val_offset:27789*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27789*FLEN/8, x4, x1, x2)

inst_9264:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ca and fs2 == 1 and fe2 == 0x12 and fm2 == 0x186 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x2db and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6dca; op2val:0xc986;
op3val:0xfadb; valaddr_reg:x3; val_offset:27792*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27792*FLEN/8, x4, x1, x2)

inst_9265:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ca and fs2 == 1 and fe2 == 0x12 and fm2 == 0x186 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x199 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6dca; op2val:0xc986;
op3val:0xf999; valaddr_reg:x3; val_offset:27795*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27795*FLEN/8, x4, x1, x2)

inst_9266:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1ca and fs2 == 1 and fe2 == 0x12 and fm2 == 0x186 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x266 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6dca; op2val:0xc986;
op3val:0xfa66; valaddr_reg:x3; val_offset:27798*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27798*FLEN/8, x4, x1, x2)

inst_9267:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x097 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2f6 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7897; op2val:0xbef6;
op3val:0xdbff; valaddr_reg:x3; val_offset:27801*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27801*FLEN/8, x4, x1, x2)

inst_9268:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x097 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2f6 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7897; op2val:0xbef6;
op3val:0xd800; valaddr_reg:x3; val_offset:27804*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27804*FLEN/8, x4, x1, x2)

inst_9269:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x097 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2f6 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x1ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7897; op2val:0xbef6;
op3val:0xd9ff; valaddr_reg:x3; val_offset:27807*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27807*FLEN/8, x4, x1, x2)

inst_9270:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x097 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2f6 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7897; op2val:0xbef6;
op3val:0xda00; valaddr_reg:x3; val_offset:27810*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27810*FLEN/8, x4, x1, x2)

inst_9271:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x097 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2f6 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x0ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7897; op2val:0xbef6;
op3val:0xd8ff; valaddr_reg:x3; val_offset:27813*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27813*FLEN/8, x4, x1, x2)

inst_9272:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x097 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2f6 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x300 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7897; op2val:0xbef6;
op3val:0xdb00; valaddr_reg:x3; val_offset:27816*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27816*FLEN/8, x4, x1, x2)

inst_9273:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x097 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2f6 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x07f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7897; op2val:0xbef6;
op3val:0xd87f; valaddr_reg:x3; val_offset:27819*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27819*FLEN/8, x4, x1, x2)

inst_9274:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x097 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2f6 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x380 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7897; op2val:0xbef6;
op3val:0xdb80; valaddr_reg:x3; val_offset:27822*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27822*FLEN/8, x4, x1, x2)

inst_9275:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x097 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2f6 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x03f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7897; op2val:0xbef6;
op3val:0xd83f; valaddr_reg:x3; val_offset:27825*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27825*FLEN/8, x4, x1, x2)

inst_9276:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x097 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2f6 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x3c0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7897; op2val:0xbef6;
op3val:0xdbc0; valaddr_reg:x3; val_offset:27828*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27828*FLEN/8, x4, x1, x2)

inst_9277:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x097 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2f6 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x01f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7897; op2val:0xbef6;
op3val:0xd81f; valaddr_reg:x3; val_offset:27831*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27831*FLEN/8, x4, x1, x2)

inst_9278:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x097 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2f6 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x3e0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7897; op2val:0xbef6;
op3val:0xdbe0; valaddr_reg:x3; val_offset:27834*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27834*FLEN/8, x4, x1, x2)

inst_9279:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x097 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2f6 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x00f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7897; op2val:0xbef6;
op3val:0xd80f; valaddr_reg:x3; val_offset:27837*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27837*FLEN/8, x4, x1, x2)

inst_9280:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x097 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2f6 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x3f0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7897; op2val:0xbef6;
op3val:0xdbf0; valaddr_reg:x3; val_offset:27840*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27840*FLEN/8, x4, x1, x2)

inst_9281:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x097 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2f6 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x007 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7897; op2val:0xbef6;
op3val:0xd807; valaddr_reg:x3; val_offset:27843*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27843*FLEN/8, x4, x1, x2)

inst_9282:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x097 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2f6 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x3f8 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7897; op2val:0xbef6;
op3val:0xdbf8; valaddr_reg:x3; val_offset:27846*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27846*FLEN/8, x4, x1, x2)

inst_9283:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x097 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2f6 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x003 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7897; op2val:0xbef6;
op3val:0xd803; valaddr_reg:x3; val_offset:27849*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27849*FLEN/8, x4, x1, x2)

inst_9284:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x097 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2f6 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x3fc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7897; op2val:0xbef6;
op3val:0xdbfc; valaddr_reg:x3; val_offset:27852*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27852*FLEN/8, x4, x1, x2)

inst_9285:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x097 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2f6 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7897; op2val:0xbef6;
op3val:0xd801; valaddr_reg:x3; val_offset:27855*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27855*FLEN/8, x4, x1, x2)

inst_9286:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x097 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2f6 and fs3 == 1 and fe3 == 0x16 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7897; op2val:0xbef6;
op3val:0xdbfe; valaddr_reg:x3; val_offset:27858*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27858*FLEN/8, x4, x1, x2)

inst_9287:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x097 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2f6 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7897; op2val:0xbef6;
op3val:0xfbfe; valaddr_reg:x3; val_offset:27861*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27861*FLEN/8, x4, x1, x2)

inst_9288:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x097 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2f6 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7897; op2val:0xbef6;
op3val:0xf801; valaddr_reg:x3; val_offset:27864*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27864*FLEN/8, x4, x1, x2)

inst_9289:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x097 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2f6 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1b6 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7897; op2val:0xbef6;
op3val:0xf9b6; valaddr_reg:x3; val_offset:27867*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27867*FLEN/8, x4, x1, x2)

inst_9290:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x097 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2f6 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x36d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7897; op2val:0xbef6;
op3val:0xfb6d; valaddr_reg:x3; val_offset:27870*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27870*FLEN/8, x4, x1, x2)

inst_9291:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x097 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2f6 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x0cc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7897; op2val:0xbef6;
op3val:0xf8cc; valaddr_reg:x3; val_offset:27873*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27873*FLEN/8, x4, x1, x2)

inst_9292:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x097 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2f6 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x333 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7897; op2val:0xbef6;
op3val:0xfb33; valaddr_reg:x3; val_offset:27876*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27876*FLEN/8, x4, x1, x2)

inst_9293:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x097 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2f6 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1dd and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7897; op2val:0xbef6;
op3val:0xf9dd; valaddr_reg:x3; val_offset:27879*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27879*FLEN/8, x4, x1, x2)

inst_9294:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x097 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2f6 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x222 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7897; op2val:0xbef6;
op3val:0xfa22; valaddr_reg:x3; val_offset:27882*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27882*FLEN/8, x4, x1, x2)

inst_9295:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x097 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2f6 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x124 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7897; op2val:0xbef6;
op3val:0xf924; valaddr_reg:x3; val_offset:27885*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27885*FLEN/8, x4, x1, x2)

inst_9296:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x097 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2f6 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x2db and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7897; op2val:0xbef6;
op3val:0xfadb; valaddr_reg:x3; val_offset:27888*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27888*FLEN/8, x4, x1, x2)

inst_9297:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x097 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2f6 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x199 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7897; op2val:0xbef6;
op3val:0xf999; valaddr_reg:x3; val_offset:27891*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27891*FLEN/8, x4, x1, x2)

inst_9298:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x097 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2f6 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x266 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7897; op2val:0xbef6;
op3val:0xfa66; valaddr_reg:x3; val_offset:27894*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27894*FLEN/8, x4, x1, x2)

inst_9299:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e6 and fs3 == 1 and fe3 == 0x17 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x756b; op2val:0xc1e6;
op3val:0xdfff; valaddr_reg:x3; val_offset:27897*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27897*FLEN/8, x4, x1, x2)

inst_9300:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e6 and fs3 == 1 and fe3 == 0x17 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x756b; op2val:0xc1e6;
op3val:0xdc00; valaddr_reg:x3; val_offset:27900*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27900*FLEN/8, x4, x1, x2)

inst_9301:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e6 and fs3 == 1 and fe3 == 0x17 and fm3 == 0x1ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x756b; op2val:0xc1e6;
op3val:0xddff; valaddr_reg:x3; val_offset:27903*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27903*FLEN/8, x4, x1, x2)

inst_9302:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e6 and fs3 == 1 and fe3 == 0x17 and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x756b; op2val:0xc1e6;
op3val:0xde00; valaddr_reg:x3; val_offset:27906*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27906*FLEN/8, x4, x1, x2)

inst_9303:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e6 and fs3 == 1 and fe3 == 0x17 and fm3 == 0x0ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x756b; op2val:0xc1e6;
op3val:0xdcff; valaddr_reg:x3; val_offset:27909*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27909*FLEN/8, x4, x1, x2)

inst_9304:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e6 and fs3 == 1 and fe3 == 0x17 and fm3 == 0x300 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x756b; op2val:0xc1e6;
op3val:0xdf00; valaddr_reg:x3; val_offset:27912*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27912*FLEN/8, x4, x1, x2)

inst_9305:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e6 and fs3 == 1 and fe3 == 0x17 and fm3 == 0x07f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x756b; op2val:0xc1e6;
op3val:0xdc7f; valaddr_reg:x3; val_offset:27915*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27915*FLEN/8, x4, x1, x2)

inst_9306:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e6 and fs3 == 1 and fe3 == 0x17 and fm3 == 0x380 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x756b; op2val:0xc1e6;
op3val:0xdf80; valaddr_reg:x3; val_offset:27918*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27918*FLEN/8, x4, x1, x2)

inst_9307:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e6 and fs3 == 1 and fe3 == 0x17 and fm3 == 0x03f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x756b; op2val:0xc1e6;
op3val:0xdc3f; valaddr_reg:x3; val_offset:27921*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27921*FLEN/8, x4, x1, x2)

inst_9308:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e6 and fs3 == 1 and fe3 == 0x17 and fm3 == 0x3c0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x756b; op2val:0xc1e6;
op3val:0xdfc0; valaddr_reg:x3; val_offset:27924*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27924*FLEN/8, x4, x1, x2)

inst_9309:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e6 and fs3 == 1 and fe3 == 0x17 and fm3 == 0x01f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x756b; op2val:0xc1e6;
op3val:0xdc1f; valaddr_reg:x3; val_offset:27927*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27927*FLEN/8, x4, x1, x2)

inst_9310:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e6 and fs3 == 1 and fe3 == 0x17 and fm3 == 0x3e0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x756b; op2val:0xc1e6;
op3val:0xdfe0; valaddr_reg:x3; val_offset:27930*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27930*FLEN/8, x4, x1, x2)

inst_9311:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e6 and fs3 == 1 and fe3 == 0x17 and fm3 == 0x00f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x756b; op2val:0xc1e6;
op3val:0xdc0f; valaddr_reg:x3; val_offset:27933*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27933*FLEN/8, x4, x1, x2)

inst_9312:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e6 and fs3 == 1 and fe3 == 0x17 and fm3 == 0x3f0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x756b; op2val:0xc1e6;
op3val:0xdff0; valaddr_reg:x3; val_offset:27936*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27936*FLEN/8, x4, x1, x2)

inst_9313:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e6 and fs3 == 1 and fe3 == 0x17 and fm3 == 0x007 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x756b; op2val:0xc1e6;
op3val:0xdc07; valaddr_reg:x3; val_offset:27939*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27939*FLEN/8, x4, x1, x2)

inst_9314:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e6 and fs3 == 1 and fe3 == 0x17 and fm3 == 0x3f8 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x756b; op2val:0xc1e6;
op3val:0xdff8; valaddr_reg:x3; val_offset:27942*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27942*FLEN/8, x4, x1, x2)

inst_9315:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e6 and fs3 == 1 and fe3 == 0x17 and fm3 == 0x003 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x756b; op2val:0xc1e6;
op3val:0xdc03; valaddr_reg:x3; val_offset:27945*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27945*FLEN/8, x4, x1, x2)

inst_9316:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e6 and fs3 == 1 and fe3 == 0x17 and fm3 == 0x3fc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x756b; op2val:0xc1e6;
op3val:0xdffc; valaddr_reg:x3; val_offset:27948*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27948*FLEN/8, x4, x1, x2)

inst_9317:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e6 and fs3 == 1 and fe3 == 0x17 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x756b; op2val:0xc1e6;
op3val:0xdc01; valaddr_reg:x3; val_offset:27951*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27951*FLEN/8, x4, x1, x2)

inst_9318:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e6 and fs3 == 1 and fe3 == 0x17 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x756b; op2val:0xc1e6;
op3val:0xdffe; valaddr_reg:x3; val_offset:27954*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27954*FLEN/8, x4, x1, x2)

inst_9319:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e6 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x756b; op2val:0xc1e6;
op3val:0xfbfe; valaddr_reg:x3; val_offset:27957*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27957*FLEN/8, x4, x1, x2)

inst_9320:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e6 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x756b; op2val:0xc1e6;
op3val:0xf801; valaddr_reg:x3; val_offset:27960*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27960*FLEN/8, x4, x1, x2)

inst_9321:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e6 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1b6 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x756b; op2val:0xc1e6;
op3val:0xf9b6; valaddr_reg:x3; val_offset:27963*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27963*FLEN/8, x4, x1, x2)

inst_9322:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e6 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x36d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x756b; op2val:0xc1e6;
op3val:0xfb6d; valaddr_reg:x3; val_offset:27966*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27966*FLEN/8, x4, x1, x2)

inst_9323:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e6 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x0cc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x756b; op2val:0xc1e6;
op3val:0xf8cc; valaddr_reg:x3; val_offset:27969*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27969*FLEN/8, x4, x1, x2)

inst_9324:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e6 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x333 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x756b; op2val:0xc1e6;
op3val:0xfb33; valaddr_reg:x3; val_offset:27972*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27972*FLEN/8, x4, x1, x2)

inst_9325:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e6 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1dd and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x756b; op2val:0xc1e6;
op3val:0xf9dd; valaddr_reg:x3; val_offset:27975*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27975*FLEN/8, x4, x1, x2)

inst_9326:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e6 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x222 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x756b; op2val:0xc1e6;
op3val:0xfa22; valaddr_reg:x3; val_offset:27978*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27978*FLEN/8, x4, x1, x2)

inst_9327:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e6 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x124 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x756b; op2val:0xc1e6;
op3val:0xf924; valaddr_reg:x3; val_offset:27981*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27981*FLEN/8, x4, x1, x2)

inst_9328:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e6 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x2db and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x756b; op2val:0xc1e6;
op3val:0xfadb; valaddr_reg:x3; val_offset:27984*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27984*FLEN/8, x4, x1, x2)

inst_9329:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e6 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x199 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x756b; op2val:0xc1e6;
op3val:0xf999; valaddr_reg:x3; val_offset:27987*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27987*FLEN/8, x4, x1, x2)

inst_9330:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16b and fs2 == 1 and fe2 == 0x10 and fm2 == 0x1e6 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x266 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x756b; op2val:0xc1e6;
op3val:0xfa66; valaddr_reg:x3; val_offset:27990*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27990*FLEN/8, x4, x1, x2)

inst_9331:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x346 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x065 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7346; op2val:0xc465;
op3val:0xe3ff; valaddr_reg:x3; val_offset:27993*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27993*FLEN/8, x4, x1, x2)

inst_9332:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x346 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x065 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7346; op2val:0xc465;
op3val:0xe000; valaddr_reg:x3; val_offset:27996*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27996*FLEN/8, x4, x1, x2)

inst_9333:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x346 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x065 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x1ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7346; op2val:0xc465;
op3val:0xe1ff; valaddr_reg:x3; val_offset:27999*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 27999*FLEN/8, x4, x1, x2)

inst_9334:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x346 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x065 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7346; op2val:0xc465;
op3val:0xe200; valaddr_reg:x3; val_offset:28002*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28002*FLEN/8, x4, x1, x2)

inst_9335:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x346 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x065 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x0ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7346; op2val:0xc465;
op3val:0xe0ff; valaddr_reg:x3; val_offset:28005*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28005*FLEN/8, x4, x1, x2)

inst_9336:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x346 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x065 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x300 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7346; op2val:0xc465;
op3val:0xe300; valaddr_reg:x3; val_offset:28008*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28008*FLEN/8, x4, x1, x2)

inst_9337:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x346 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x065 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x07f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7346; op2val:0xc465;
op3val:0xe07f; valaddr_reg:x3; val_offset:28011*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28011*FLEN/8, x4, x1, x2)

inst_9338:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x346 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x065 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x380 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7346; op2val:0xc465;
op3val:0xe380; valaddr_reg:x3; val_offset:28014*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28014*FLEN/8, x4, x1, x2)

inst_9339:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x346 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x065 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x03f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7346; op2val:0xc465;
op3val:0xe03f; valaddr_reg:x3; val_offset:28017*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28017*FLEN/8, x4, x1, x2)

inst_9340:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x346 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x065 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x3c0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7346; op2val:0xc465;
op3val:0xe3c0; valaddr_reg:x3; val_offset:28020*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28020*FLEN/8, x4, x1, x2)

inst_9341:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x346 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x065 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x01f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7346; op2val:0xc465;
op3val:0xe01f; valaddr_reg:x3; val_offset:28023*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28023*FLEN/8, x4, x1, x2)

inst_9342:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x346 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x065 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x3e0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7346; op2val:0xc465;
op3val:0xe3e0; valaddr_reg:x3; val_offset:28026*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28026*FLEN/8, x4, x1, x2)

inst_9343:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x346 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x065 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x00f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7346; op2val:0xc465;
op3val:0xe00f; valaddr_reg:x3; val_offset:28029*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28029*FLEN/8, x4, x1, x2)

RVTEST_SIGBASE(x1,signature_x1_74)
inst_9344:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x346 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x065 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x3f0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7346; op2val:0xc465;
op3val:0xe3f0; valaddr_reg:x3; val_offset:28032*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28032*FLEN/8, x4, x1, x2)

inst_9345:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x346 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x065 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x007 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7346; op2val:0xc465;
op3val:0xe007; valaddr_reg:x3; val_offset:28035*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28035*FLEN/8, x4, x1, x2)

inst_9346:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x346 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x065 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x3f8 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7346; op2val:0xc465;
op3val:0xe3f8; valaddr_reg:x3; val_offset:28038*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28038*FLEN/8, x4, x1, x2)

inst_9347:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x346 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x065 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x003 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7346; op2val:0xc465;
op3val:0xe003; valaddr_reg:x3; val_offset:28041*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28041*FLEN/8, x4, x1, x2)

inst_9348:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x346 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x065 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x3fc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7346; op2val:0xc465;
op3val:0xe3fc; valaddr_reg:x3; val_offset:28044*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28044*FLEN/8, x4, x1, x2)

inst_9349:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x346 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x065 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7346; op2val:0xc465;
op3val:0xe001; valaddr_reg:x3; val_offset:28047*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28047*FLEN/8, x4, x1, x2)

inst_9350:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x346 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x065 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7346; op2val:0xc465;
op3val:0xe3fe; valaddr_reg:x3; val_offset:28050*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28050*FLEN/8, x4, x1, x2)

inst_9351:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x346 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x065 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7346; op2val:0xc465;
op3val:0xfbfe; valaddr_reg:x3; val_offset:28053*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28053*FLEN/8, x4, x1, x2)

inst_9352:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x346 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x065 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7346; op2val:0xc465;
op3val:0xf801; valaddr_reg:x3; val_offset:28056*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28056*FLEN/8, x4, x1, x2)

inst_9353:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x346 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x065 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1b6 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7346; op2val:0xc465;
op3val:0xf9b6; valaddr_reg:x3; val_offset:28059*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28059*FLEN/8, x4, x1, x2)

inst_9354:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x346 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x065 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x36d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7346; op2val:0xc465;
op3val:0xfb6d; valaddr_reg:x3; val_offset:28062*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28062*FLEN/8, x4, x1, x2)

inst_9355:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x346 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x065 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x0cc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7346; op2val:0xc465;
op3val:0xf8cc; valaddr_reg:x3; val_offset:28065*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28065*FLEN/8, x4, x1, x2)

inst_9356:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x346 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x065 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x333 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7346; op2val:0xc465;
op3val:0xfb33; valaddr_reg:x3; val_offset:28068*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28068*FLEN/8, x4, x1, x2)

inst_9357:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x346 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x065 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1dd and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7346; op2val:0xc465;
op3val:0xf9dd; valaddr_reg:x3; val_offset:28071*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28071*FLEN/8, x4, x1, x2)

inst_9358:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x346 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x065 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x222 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7346; op2val:0xc465;
op3val:0xfa22; valaddr_reg:x3; val_offset:28074*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28074*FLEN/8, x4, x1, x2)

inst_9359:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x346 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x065 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x124 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7346; op2val:0xc465;
op3val:0xf924; valaddr_reg:x3; val_offset:28077*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28077*FLEN/8, x4, x1, x2)

inst_9360:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x346 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x065 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x2db and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7346; op2val:0xc465;
op3val:0xfadb; valaddr_reg:x3; val_offset:28080*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28080*FLEN/8, x4, x1, x2)

inst_9361:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x346 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x065 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x199 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7346; op2val:0xc465;
op3val:0xf999; valaddr_reg:x3; val_offset:28083*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28083*FLEN/8, x4, x1, x2)

inst_9362:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x346 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x065 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x266 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7346; op2val:0xc465;
op3val:0xfa66; valaddr_reg:x3; val_offset:28086*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28086*FLEN/8, x4, x1, x2)

inst_9363:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ba and fs2 == 1 and fe2 == 0x0f and fm2 == 0x023 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bba; op2val:0xbc23;
op3val:0xe7ff; valaddr_reg:x3; val_offset:28089*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28089*FLEN/8, x4, x1, x2)

inst_9364:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ba and fs2 == 1 and fe2 == 0x0f and fm2 == 0x023 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bba; op2val:0xbc23;
op3val:0xe400; valaddr_reg:x3; val_offset:28092*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28092*FLEN/8, x4, x1, x2)

inst_9365:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ba and fs2 == 1 and fe2 == 0x0f and fm2 == 0x023 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x1ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bba; op2val:0xbc23;
op3val:0xe5ff; valaddr_reg:x3; val_offset:28095*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28095*FLEN/8, x4, x1, x2)

inst_9366:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ba and fs2 == 1 and fe2 == 0x0f and fm2 == 0x023 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bba; op2val:0xbc23;
op3val:0xe600; valaddr_reg:x3; val_offset:28098*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28098*FLEN/8, x4, x1, x2)

inst_9367:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ba and fs2 == 1 and fe2 == 0x0f and fm2 == 0x023 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x0ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bba; op2val:0xbc23;
op3val:0xe4ff; valaddr_reg:x3; val_offset:28101*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28101*FLEN/8, x4, x1, x2)

inst_9368:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ba and fs2 == 1 and fe2 == 0x0f and fm2 == 0x023 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x300 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bba; op2val:0xbc23;
op3val:0xe700; valaddr_reg:x3; val_offset:28104*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28104*FLEN/8, x4, x1, x2)

inst_9369:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ba and fs2 == 1 and fe2 == 0x0f and fm2 == 0x023 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x07f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bba; op2val:0xbc23;
op3val:0xe47f; valaddr_reg:x3; val_offset:28107*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28107*FLEN/8, x4, x1, x2)

inst_9370:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ba and fs2 == 1 and fe2 == 0x0f and fm2 == 0x023 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x380 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bba; op2val:0xbc23;
op3val:0xe780; valaddr_reg:x3; val_offset:28110*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28110*FLEN/8, x4, x1, x2)

inst_9371:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ba and fs2 == 1 and fe2 == 0x0f and fm2 == 0x023 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x03f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bba; op2val:0xbc23;
op3val:0xe43f; valaddr_reg:x3; val_offset:28113*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28113*FLEN/8, x4, x1, x2)

inst_9372:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ba and fs2 == 1 and fe2 == 0x0f and fm2 == 0x023 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x3c0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bba; op2val:0xbc23;
op3val:0xe7c0; valaddr_reg:x3; val_offset:28116*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28116*FLEN/8, x4, x1, x2)

inst_9373:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ba and fs2 == 1 and fe2 == 0x0f and fm2 == 0x023 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x01f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bba; op2val:0xbc23;
op3val:0xe41f; valaddr_reg:x3; val_offset:28119*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28119*FLEN/8, x4, x1, x2)

inst_9374:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ba and fs2 == 1 and fe2 == 0x0f and fm2 == 0x023 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x3e0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bba; op2val:0xbc23;
op3val:0xe7e0; valaddr_reg:x3; val_offset:28122*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28122*FLEN/8, x4, x1, x2)

inst_9375:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ba and fs2 == 1 and fe2 == 0x0f and fm2 == 0x023 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x00f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bba; op2val:0xbc23;
op3val:0xe40f; valaddr_reg:x3; val_offset:28125*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28125*FLEN/8, x4, x1, x2)

inst_9376:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ba and fs2 == 1 and fe2 == 0x0f and fm2 == 0x023 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x3f0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bba; op2val:0xbc23;
op3val:0xe7f0; valaddr_reg:x3; val_offset:28128*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28128*FLEN/8, x4, x1, x2)

inst_9377:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ba and fs2 == 1 and fe2 == 0x0f and fm2 == 0x023 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x007 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bba; op2val:0xbc23;
op3val:0xe407; valaddr_reg:x3; val_offset:28131*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28131*FLEN/8, x4, x1, x2)

inst_9378:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ba and fs2 == 1 and fe2 == 0x0f and fm2 == 0x023 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x3f8 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bba; op2val:0xbc23;
op3val:0xe7f8; valaddr_reg:x3; val_offset:28134*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28134*FLEN/8, x4, x1, x2)

inst_9379:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ba and fs2 == 1 and fe2 == 0x0f and fm2 == 0x023 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x003 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bba; op2val:0xbc23;
op3val:0xe403; valaddr_reg:x3; val_offset:28137*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28137*FLEN/8, x4, x1, x2)

inst_9380:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ba and fs2 == 1 and fe2 == 0x0f and fm2 == 0x023 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x3fc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bba; op2val:0xbc23;
op3val:0xe7fc; valaddr_reg:x3; val_offset:28140*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28140*FLEN/8, x4, x1, x2)

inst_9381:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ba and fs2 == 1 and fe2 == 0x0f and fm2 == 0x023 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bba; op2val:0xbc23;
op3val:0xe401; valaddr_reg:x3; val_offset:28143*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28143*FLEN/8, x4, x1, x2)

inst_9382:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ba and fs2 == 1 and fe2 == 0x0f and fm2 == 0x023 and fs3 == 1 and fe3 == 0x19 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bba; op2val:0xbc23;
op3val:0xe7fe; valaddr_reg:x3; val_offset:28146*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28146*FLEN/8, x4, x1, x2)

inst_9383:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ba and fs2 == 1 and fe2 == 0x0f and fm2 == 0x023 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bba; op2val:0xbc23;
op3val:0xfbfe; valaddr_reg:x3; val_offset:28149*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28149*FLEN/8, x4, x1, x2)

inst_9384:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ba and fs2 == 1 and fe2 == 0x0f and fm2 == 0x023 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bba; op2val:0xbc23;
op3val:0xf801; valaddr_reg:x3; val_offset:28152*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28152*FLEN/8, x4, x1, x2)

inst_9385:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ba and fs2 == 1 and fe2 == 0x0f and fm2 == 0x023 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1b6 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bba; op2val:0xbc23;
op3val:0xf9b6; valaddr_reg:x3; val_offset:28155*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28155*FLEN/8, x4, x1, x2)

inst_9386:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ba and fs2 == 1 and fe2 == 0x0f and fm2 == 0x023 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x36d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bba; op2val:0xbc23;
op3val:0xfb6d; valaddr_reg:x3; val_offset:28158*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28158*FLEN/8, x4, x1, x2)

inst_9387:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ba and fs2 == 1 and fe2 == 0x0f and fm2 == 0x023 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x0cc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bba; op2val:0xbc23;
op3val:0xf8cc; valaddr_reg:x3; val_offset:28161*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28161*FLEN/8, x4, x1, x2)

inst_9388:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ba and fs2 == 1 and fe2 == 0x0f and fm2 == 0x023 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x333 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bba; op2val:0xbc23;
op3val:0xfb33; valaddr_reg:x3; val_offset:28164*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28164*FLEN/8, x4, x1, x2)

inst_9389:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ba and fs2 == 1 and fe2 == 0x0f and fm2 == 0x023 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1dd and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bba; op2val:0xbc23;
op3val:0xf9dd; valaddr_reg:x3; val_offset:28167*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28167*FLEN/8, x4, x1, x2)

inst_9390:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ba and fs2 == 1 and fe2 == 0x0f and fm2 == 0x023 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x222 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bba; op2val:0xbc23;
op3val:0xfa22; valaddr_reg:x3; val_offset:28170*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28170*FLEN/8, x4, x1, x2)

inst_9391:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ba and fs2 == 1 and fe2 == 0x0f and fm2 == 0x023 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x124 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bba; op2val:0xbc23;
op3val:0xf924; valaddr_reg:x3; val_offset:28173*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28173*FLEN/8, x4, x1, x2)

inst_9392:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ba and fs2 == 1 and fe2 == 0x0f and fm2 == 0x023 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x2db and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bba; op2val:0xbc23;
op3val:0xfadb; valaddr_reg:x3; val_offset:28176*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28176*FLEN/8, x4, x1, x2)

inst_9393:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ba and fs2 == 1 and fe2 == 0x0f and fm2 == 0x023 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x199 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bba; op2val:0xbc23;
op3val:0xf999; valaddr_reg:x3; val_offset:28179*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28179*FLEN/8, x4, x1, x2)

inst_9394:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ba and fs2 == 1 and fe2 == 0x0f and fm2 == 0x023 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x266 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bba; op2val:0xbc23;
op3val:0xfa66; valaddr_reg:x3; val_offset:28182*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28182*FLEN/8, x4, x1, x2)

inst_9395:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x141 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x216 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6941; op2val:0xce16;
op3val:0xebff; valaddr_reg:x3; val_offset:28185*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28185*FLEN/8, x4, x1, x2)

inst_9396:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x141 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x216 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6941; op2val:0xce16;
op3val:0xe800; valaddr_reg:x3; val_offset:28188*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28188*FLEN/8, x4, x1, x2)

inst_9397:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x141 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x216 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x1ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6941; op2val:0xce16;
op3val:0xe9ff; valaddr_reg:x3; val_offset:28191*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28191*FLEN/8, x4, x1, x2)

inst_9398:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x141 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x216 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6941; op2val:0xce16;
op3val:0xea00; valaddr_reg:x3; val_offset:28194*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28194*FLEN/8, x4, x1, x2)

inst_9399:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x141 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x216 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x0ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6941; op2val:0xce16;
op3val:0xe8ff; valaddr_reg:x3; val_offset:28197*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28197*FLEN/8, x4, x1, x2)

inst_9400:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x141 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x216 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x300 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6941; op2val:0xce16;
op3val:0xeb00; valaddr_reg:x3; val_offset:28200*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28200*FLEN/8, x4, x1, x2)

inst_9401:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x141 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x216 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x07f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6941; op2val:0xce16;
op3val:0xe87f; valaddr_reg:x3; val_offset:28203*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28203*FLEN/8, x4, x1, x2)

inst_9402:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x141 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x216 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x380 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6941; op2val:0xce16;
op3val:0xeb80; valaddr_reg:x3; val_offset:28206*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28206*FLEN/8, x4, x1, x2)

inst_9403:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x141 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x216 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x03f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6941; op2val:0xce16;
op3val:0xe83f; valaddr_reg:x3; val_offset:28209*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28209*FLEN/8, x4, x1, x2)

inst_9404:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x141 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x216 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x3c0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6941; op2val:0xce16;
op3val:0xebc0; valaddr_reg:x3; val_offset:28212*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28212*FLEN/8, x4, x1, x2)

inst_9405:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x141 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x216 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x01f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6941; op2val:0xce16;
op3val:0xe81f; valaddr_reg:x3; val_offset:28215*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28215*FLEN/8, x4, x1, x2)

inst_9406:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x141 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x216 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x3e0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6941; op2val:0xce16;
op3val:0xebe0; valaddr_reg:x3; val_offset:28218*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28218*FLEN/8, x4, x1, x2)

inst_9407:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x141 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x216 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x00f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6941; op2val:0xce16;
op3val:0xe80f; valaddr_reg:x3; val_offset:28221*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28221*FLEN/8, x4, x1, x2)

inst_9408:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x141 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x216 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x3f0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6941; op2val:0xce16;
op3val:0xebf0; valaddr_reg:x3; val_offset:28224*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28224*FLEN/8, x4, x1, x2)

inst_9409:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x141 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x216 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x007 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6941; op2val:0xce16;
op3val:0xe807; valaddr_reg:x3; val_offset:28227*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28227*FLEN/8, x4, x1, x2)

inst_9410:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x141 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x216 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x3f8 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6941; op2val:0xce16;
op3val:0xebf8; valaddr_reg:x3; val_offset:28230*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28230*FLEN/8, x4, x1, x2)

inst_9411:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x141 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x216 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x003 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6941; op2val:0xce16;
op3val:0xe803; valaddr_reg:x3; val_offset:28233*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28233*FLEN/8, x4, x1, x2)

inst_9412:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x141 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x216 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x3fc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6941; op2val:0xce16;
op3val:0xebfc; valaddr_reg:x3; val_offset:28236*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28236*FLEN/8, x4, x1, x2)

inst_9413:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x141 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x216 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6941; op2val:0xce16;
op3val:0xe801; valaddr_reg:x3; val_offset:28239*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28239*FLEN/8, x4, x1, x2)

inst_9414:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x141 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x216 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6941; op2val:0xce16;
op3val:0xebfe; valaddr_reg:x3; val_offset:28242*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28242*FLEN/8, x4, x1, x2)

inst_9415:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x141 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x216 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6941; op2val:0xce16;
op3val:0xfbfe; valaddr_reg:x3; val_offset:28245*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28245*FLEN/8, x4, x1, x2)

inst_9416:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x141 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x216 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6941; op2val:0xce16;
op3val:0xf801; valaddr_reg:x3; val_offset:28248*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28248*FLEN/8, x4, x1, x2)

inst_9417:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x141 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x216 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1b6 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6941; op2val:0xce16;
op3val:0xf9b6; valaddr_reg:x3; val_offset:28251*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28251*FLEN/8, x4, x1, x2)

inst_9418:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x141 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x216 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x36d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6941; op2val:0xce16;
op3val:0xfb6d; valaddr_reg:x3; val_offset:28254*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28254*FLEN/8, x4, x1, x2)

inst_9419:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x141 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x216 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x0cc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6941; op2val:0xce16;
op3val:0xf8cc; valaddr_reg:x3; val_offset:28257*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28257*FLEN/8, x4, x1, x2)

inst_9420:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x141 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x216 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x333 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6941; op2val:0xce16;
op3val:0xfb33; valaddr_reg:x3; val_offset:28260*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28260*FLEN/8, x4, x1, x2)

inst_9421:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x141 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x216 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1dd and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6941; op2val:0xce16;
op3val:0xf9dd; valaddr_reg:x3; val_offset:28263*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28263*FLEN/8, x4, x1, x2)

inst_9422:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x141 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x216 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x222 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6941; op2val:0xce16;
op3val:0xfa22; valaddr_reg:x3; val_offset:28266*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28266*FLEN/8, x4, x1, x2)

inst_9423:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x141 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x216 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x124 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6941; op2val:0xce16;
op3val:0xf924; valaddr_reg:x3; val_offset:28269*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28269*FLEN/8, x4, x1, x2)

inst_9424:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x141 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x216 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x2db and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6941; op2val:0xce16;
op3val:0xfadb; valaddr_reg:x3; val_offset:28272*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28272*FLEN/8, x4, x1, x2)

inst_9425:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x141 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x216 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x199 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6941; op2val:0xce16;
op3val:0xf999; valaddr_reg:x3; val_offset:28275*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28275*FLEN/8, x4, x1, x2)

inst_9426:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x141 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x216 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x266 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6941; op2val:0xce16;
op3val:0xfa66; valaddr_reg:x3; val_offset:28278*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28278*FLEN/8, x4, x1, x2)

inst_9427:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x15a and fs3 == 1 and fe3 == 0x1b and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71f9; op2val:0xc55a;
op3val:0xefff; valaddr_reg:x3; val_offset:28281*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28281*FLEN/8, x4, x1, x2)

inst_9428:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x15a and fs3 == 1 and fe3 == 0x1b and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71f9; op2val:0xc55a;
op3val:0xec00; valaddr_reg:x3; val_offset:28284*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28284*FLEN/8, x4, x1, x2)

inst_9429:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x15a and fs3 == 1 and fe3 == 0x1b and fm3 == 0x1ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71f9; op2val:0xc55a;
op3val:0xedff; valaddr_reg:x3; val_offset:28287*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28287*FLEN/8, x4, x1, x2)

inst_9430:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x15a and fs3 == 1 and fe3 == 0x1b and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71f9; op2val:0xc55a;
op3val:0xee00; valaddr_reg:x3; val_offset:28290*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28290*FLEN/8, x4, x1, x2)

inst_9431:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x15a and fs3 == 1 and fe3 == 0x1b and fm3 == 0x0ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71f9; op2val:0xc55a;
op3val:0xecff; valaddr_reg:x3; val_offset:28293*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28293*FLEN/8, x4, x1, x2)

inst_9432:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x15a and fs3 == 1 and fe3 == 0x1b and fm3 == 0x300 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71f9; op2val:0xc55a;
op3val:0xef00; valaddr_reg:x3; val_offset:28296*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28296*FLEN/8, x4, x1, x2)

inst_9433:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x15a and fs3 == 1 and fe3 == 0x1b and fm3 == 0x07f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71f9; op2val:0xc55a;
op3val:0xec7f; valaddr_reg:x3; val_offset:28299*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28299*FLEN/8, x4, x1, x2)

inst_9434:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x15a and fs3 == 1 and fe3 == 0x1b and fm3 == 0x380 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71f9; op2val:0xc55a;
op3val:0xef80; valaddr_reg:x3; val_offset:28302*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28302*FLEN/8, x4, x1, x2)

inst_9435:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x15a and fs3 == 1 and fe3 == 0x1b and fm3 == 0x03f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71f9; op2val:0xc55a;
op3val:0xec3f; valaddr_reg:x3; val_offset:28305*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28305*FLEN/8, x4, x1, x2)

inst_9436:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x15a and fs3 == 1 and fe3 == 0x1b and fm3 == 0x3c0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71f9; op2val:0xc55a;
op3val:0xefc0; valaddr_reg:x3; val_offset:28308*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28308*FLEN/8, x4, x1, x2)

inst_9437:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x15a and fs3 == 1 and fe3 == 0x1b and fm3 == 0x01f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71f9; op2val:0xc55a;
op3val:0xec1f; valaddr_reg:x3; val_offset:28311*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28311*FLEN/8, x4, x1, x2)

inst_9438:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x15a and fs3 == 1 and fe3 == 0x1b and fm3 == 0x3e0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71f9; op2val:0xc55a;
op3val:0xefe0; valaddr_reg:x3; val_offset:28314*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28314*FLEN/8, x4, x1, x2)

inst_9439:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x15a and fs3 == 1 and fe3 == 0x1b and fm3 == 0x00f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71f9; op2val:0xc55a;
op3val:0xec0f; valaddr_reg:x3; val_offset:28317*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28317*FLEN/8, x4, x1, x2)

inst_9440:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x15a and fs3 == 1 and fe3 == 0x1b and fm3 == 0x3f0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71f9; op2val:0xc55a;
op3val:0xeff0; valaddr_reg:x3; val_offset:28320*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28320*FLEN/8, x4, x1, x2)

inst_9441:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x15a and fs3 == 1 and fe3 == 0x1b and fm3 == 0x007 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71f9; op2val:0xc55a;
op3val:0xec07; valaddr_reg:x3; val_offset:28323*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28323*FLEN/8, x4, x1, x2)

inst_9442:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x15a and fs3 == 1 and fe3 == 0x1b and fm3 == 0x3f8 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71f9; op2val:0xc55a;
op3val:0xeff8; valaddr_reg:x3; val_offset:28326*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28326*FLEN/8, x4, x1, x2)

inst_9443:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x15a and fs3 == 1 and fe3 == 0x1b and fm3 == 0x003 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71f9; op2val:0xc55a;
op3val:0xec03; valaddr_reg:x3; val_offset:28329*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28329*FLEN/8, x4, x1, x2)

inst_9444:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x15a and fs3 == 1 and fe3 == 0x1b and fm3 == 0x3fc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71f9; op2val:0xc55a;
op3val:0xeffc; valaddr_reg:x3; val_offset:28332*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28332*FLEN/8, x4, x1, x2)

inst_9445:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x15a and fs3 == 1 and fe3 == 0x1b and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71f9; op2val:0xc55a;
op3val:0xec01; valaddr_reg:x3; val_offset:28335*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28335*FLEN/8, x4, x1, x2)

inst_9446:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x15a and fs3 == 1 and fe3 == 0x1b and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71f9; op2val:0xc55a;
op3val:0xeffe; valaddr_reg:x3; val_offset:28338*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28338*FLEN/8, x4, x1, x2)

inst_9447:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x15a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71f9; op2val:0xc55a;
op3val:0xfbfe; valaddr_reg:x3; val_offset:28341*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28341*FLEN/8, x4, x1, x2)

inst_9448:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x15a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71f9; op2val:0xc55a;
op3val:0xf801; valaddr_reg:x3; val_offset:28344*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28344*FLEN/8, x4, x1, x2)

inst_9449:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x15a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1b6 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71f9; op2val:0xc55a;
op3val:0xf9b6; valaddr_reg:x3; val_offset:28347*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28347*FLEN/8, x4, x1, x2)

inst_9450:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x15a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x36d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71f9; op2val:0xc55a;
op3val:0xfb6d; valaddr_reg:x3; val_offset:28350*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28350*FLEN/8, x4, x1, x2)

inst_9451:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x15a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x0cc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71f9; op2val:0xc55a;
op3val:0xf8cc; valaddr_reg:x3; val_offset:28353*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28353*FLEN/8, x4, x1, x2)

inst_9452:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x15a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x333 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71f9; op2val:0xc55a;
op3val:0xfb33; valaddr_reg:x3; val_offset:28356*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28356*FLEN/8, x4, x1, x2)

inst_9453:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x15a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1dd and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71f9; op2val:0xc55a;
op3val:0xf9dd; valaddr_reg:x3; val_offset:28359*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28359*FLEN/8, x4, x1, x2)

inst_9454:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x15a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x222 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71f9; op2val:0xc55a;
op3val:0xfa22; valaddr_reg:x3; val_offset:28362*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28362*FLEN/8, x4, x1, x2)

inst_9455:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x15a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x124 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71f9; op2val:0xc55a;
op3val:0xf924; valaddr_reg:x3; val_offset:28365*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28365*FLEN/8, x4, x1, x2)

inst_9456:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x15a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x2db and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71f9; op2val:0xc55a;
op3val:0xfadb; valaddr_reg:x3; val_offset:28368*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28368*FLEN/8, x4, x1, x2)

inst_9457:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x15a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x199 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71f9; op2val:0xc55a;
op3val:0xf999; valaddr_reg:x3; val_offset:28371*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28371*FLEN/8, x4, x1, x2)

inst_9458:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1f9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x15a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x266 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71f9; op2val:0xc55a;
op3val:0xfa66; valaddr_reg:x3; val_offset:28374*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28374*FLEN/8, x4, x1, x2)

inst_9459:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x256 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x10b and fs3 == 1 and fe3 == 0x1c and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a56; op2val:0xbd0b;
op3val:0xf3ff; valaddr_reg:x3; val_offset:28377*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28377*FLEN/8, x4, x1, x2)

inst_9460:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x256 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x10b and fs3 == 1 and fe3 == 0x1c and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a56; op2val:0xbd0b;
op3val:0xf000; valaddr_reg:x3; val_offset:28380*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28380*FLEN/8, x4, x1, x2)

inst_9461:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x256 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x10b and fs3 == 1 and fe3 == 0x1c and fm3 == 0x1ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a56; op2val:0xbd0b;
op3val:0xf1ff; valaddr_reg:x3; val_offset:28383*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28383*FLEN/8, x4, x1, x2)

inst_9462:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x256 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x10b and fs3 == 1 and fe3 == 0x1c and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a56; op2val:0xbd0b;
op3val:0xf200; valaddr_reg:x3; val_offset:28386*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28386*FLEN/8, x4, x1, x2)

inst_9463:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x256 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x10b and fs3 == 1 and fe3 == 0x1c and fm3 == 0x0ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a56; op2val:0xbd0b;
op3val:0xf0ff; valaddr_reg:x3; val_offset:28389*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28389*FLEN/8, x4, x1, x2)

inst_9464:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x256 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x10b and fs3 == 1 and fe3 == 0x1c and fm3 == 0x300 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a56; op2val:0xbd0b;
op3val:0xf300; valaddr_reg:x3; val_offset:28392*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28392*FLEN/8, x4, x1, x2)

inst_9465:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x256 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x10b and fs3 == 1 and fe3 == 0x1c and fm3 == 0x07f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a56; op2val:0xbd0b;
op3val:0xf07f; valaddr_reg:x3; val_offset:28395*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28395*FLEN/8, x4, x1, x2)

inst_9466:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x256 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x10b and fs3 == 1 and fe3 == 0x1c and fm3 == 0x380 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a56; op2val:0xbd0b;
op3val:0xf380; valaddr_reg:x3; val_offset:28398*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28398*FLEN/8, x4, x1, x2)

inst_9467:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x256 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x10b and fs3 == 1 and fe3 == 0x1c and fm3 == 0x03f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a56; op2val:0xbd0b;
op3val:0xf03f; valaddr_reg:x3; val_offset:28401*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28401*FLEN/8, x4, x1, x2)

inst_9468:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x256 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x10b and fs3 == 1 and fe3 == 0x1c and fm3 == 0x3c0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a56; op2val:0xbd0b;
op3val:0xf3c0; valaddr_reg:x3; val_offset:28404*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28404*FLEN/8, x4, x1, x2)

inst_9469:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x256 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x10b and fs3 == 1 and fe3 == 0x1c and fm3 == 0x01f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a56; op2val:0xbd0b;
op3val:0xf01f; valaddr_reg:x3; val_offset:28407*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28407*FLEN/8, x4, x1, x2)

inst_9470:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x256 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x10b and fs3 == 1 and fe3 == 0x1c and fm3 == 0x3e0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a56; op2val:0xbd0b;
op3val:0xf3e0; valaddr_reg:x3; val_offset:28410*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28410*FLEN/8, x4, x1, x2)

inst_9471:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x256 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x10b and fs3 == 1 and fe3 == 0x1c and fm3 == 0x00f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a56; op2val:0xbd0b;
op3val:0xf00f; valaddr_reg:x3; val_offset:28413*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28413*FLEN/8, x4, x1, x2)

RVTEST_SIGBASE(x1,signature_x1_75)
inst_9472:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x256 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x10b and fs3 == 1 and fe3 == 0x1c and fm3 == 0x3f0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a56; op2val:0xbd0b;
op3val:0xf3f0; valaddr_reg:x3; val_offset:28416*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28416*FLEN/8, x4, x1, x2)

inst_9473:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x256 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x10b and fs3 == 1 and fe3 == 0x1c and fm3 == 0x007 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a56; op2val:0xbd0b;
op3val:0xf007; valaddr_reg:x3; val_offset:28419*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28419*FLEN/8, x4, x1, x2)

inst_9474:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x256 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x10b and fs3 == 1 and fe3 == 0x1c and fm3 == 0x3f8 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a56; op2val:0xbd0b;
op3val:0xf3f8; valaddr_reg:x3; val_offset:28422*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28422*FLEN/8, x4, x1, x2)

inst_9475:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x256 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x10b and fs3 == 1 and fe3 == 0x1c and fm3 == 0x003 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a56; op2val:0xbd0b;
op3val:0xf003; valaddr_reg:x3; val_offset:28425*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28425*FLEN/8, x4, x1, x2)

inst_9476:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x256 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x10b and fs3 == 1 and fe3 == 0x1c and fm3 == 0x3fc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a56; op2val:0xbd0b;
op3val:0xf3fc; valaddr_reg:x3; val_offset:28428*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28428*FLEN/8, x4, x1, x2)

inst_9477:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x256 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x10b and fs3 == 1 and fe3 == 0x1c and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a56; op2val:0xbd0b;
op3val:0xf001; valaddr_reg:x3; val_offset:28431*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28431*FLEN/8, x4, x1, x2)

inst_9478:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x256 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x10b and fs3 == 1 and fe3 == 0x1c and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a56; op2val:0xbd0b;
op3val:0xf3fe; valaddr_reg:x3; val_offset:28434*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28434*FLEN/8, x4, x1, x2)

inst_9479:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x256 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x10b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a56; op2val:0xbd0b;
op3val:0xfbfe; valaddr_reg:x3; val_offset:28437*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28437*FLEN/8, x4, x1, x2)

inst_9480:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x256 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x10b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a56; op2val:0xbd0b;
op3val:0xf801; valaddr_reg:x3; val_offset:28440*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28440*FLEN/8, x4, x1, x2)

inst_9481:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x256 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x10b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1b6 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a56; op2val:0xbd0b;
op3val:0xf9b6; valaddr_reg:x3; val_offset:28443*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28443*FLEN/8, x4, x1, x2)

inst_9482:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x256 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x10b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x36d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a56; op2val:0xbd0b;
op3val:0xfb6d; valaddr_reg:x3; val_offset:28446*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28446*FLEN/8, x4, x1, x2)

inst_9483:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x256 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x10b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x0cc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a56; op2val:0xbd0b;
op3val:0xf8cc; valaddr_reg:x3; val_offset:28449*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28449*FLEN/8, x4, x1, x2)

inst_9484:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x256 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x10b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x333 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a56; op2val:0xbd0b;
op3val:0xfb33; valaddr_reg:x3; val_offset:28452*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28452*FLEN/8, x4, x1, x2)

inst_9485:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x256 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x10b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1dd and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a56; op2val:0xbd0b;
op3val:0xf9dd; valaddr_reg:x3; val_offset:28455*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28455*FLEN/8, x4, x1, x2)

inst_9486:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x256 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x10b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x222 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a56; op2val:0xbd0b;
op3val:0xfa22; valaddr_reg:x3; val_offset:28458*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28458*FLEN/8, x4, x1, x2)

inst_9487:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x256 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x10b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x124 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a56; op2val:0xbd0b;
op3val:0xf924; valaddr_reg:x3; val_offset:28461*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28461*FLEN/8, x4, x1, x2)

inst_9488:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x256 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x10b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x2db and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a56; op2val:0xbd0b;
op3val:0xfadb; valaddr_reg:x3; val_offset:28464*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28464*FLEN/8, x4, x1, x2)

inst_9489:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x256 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x10b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x199 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a56; op2val:0xbd0b;
op3val:0xf999; valaddr_reg:x3; val_offset:28467*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28467*FLEN/8, x4, x1, x2)

inst_9490:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x256 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x10b and fs3 == 1 and fe3 == 0x1e and fm3 == 0x266 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a56; op2val:0xbd0b;
op3val:0xfa66; valaddr_reg:x3; val_offset:28470*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28470*FLEN/8, x4, x1, x2)

inst_9491:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2e8 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78a1; op2val:0xbee8;
op3val:0xf7ff; valaddr_reg:x3; val_offset:28473*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28473*FLEN/8, x4, x1, x2)

inst_9492:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2e8 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78a1; op2val:0xbee8;
op3val:0xf400; valaddr_reg:x3; val_offset:28476*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28476*FLEN/8, x4, x1, x2)

inst_9493:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2e8 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x1ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78a1; op2val:0xbee8;
op3val:0xf5ff; valaddr_reg:x3; val_offset:28479*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28479*FLEN/8, x4, x1, x2)

inst_9494:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2e8 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78a1; op2val:0xbee8;
op3val:0xf600; valaddr_reg:x3; val_offset:28482*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28482*FLEN/8, x4, x1, x2)

inst_9495:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2e8 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x0ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78a1; op2val:0xbee8;
op3val:0xf4ff; valaddr_reg:x3; val_offset:28485*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28485*FLEN/8, x4, x1, x2)

inst_9496:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2e8 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x300 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78a1; op2val:0xbee8;
op3val:0xf700; valaddr_reg:x3; val_offset:28488*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28488*FLEN/8, x4, x1, x2)

inst_9497:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2e8 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x07f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78a1; op2val:0xbee8;
op3val:0xf47f; valaddr_reg:x3; val_offset:28491*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28491*FLEN/8, x4, x1, x2)

inst_9498:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2e8 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x380 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78a1; op2val:0xbee8;
op3val:0xf780; valaddr_reg:x3; val_offset:28494*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28494*FLEN/8, x4, x1, x2)

inst_9499:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2e8 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x03f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78a1; op2val:0xbee8;
op3val:0xf43f; valaddr_reg:x3; val_offset:28497*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28497*FLEN/8, x4, x1, x2)

inst_9500:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2e8 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x3c0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78a1; op2val:0xbee8;
op3val:0xf7c0; valaddr_reg:x3; val_offset:28500*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28500*FLEN/8, x4, x1, x2)

inst_9501:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2e8 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x01f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78a1; op2val:0xbee8;
op3val:0xf41f; valaddr_reg:x3; val_offset:28503*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28503*FLEN/8, x4, x1, x2)

inst_9502:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2e8 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x3e0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78a1; op2val:0xbee8;
op3val:0xf7e0; valaddr_reg:x3; val_offset:28506*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28506*FLEN/8, x4, x1, x2)

inst_9503:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2e8 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x00f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78a1; op2val:0xbee8;
op3val:0xf40f; valaddr_reg:x3; val_offset:28509*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28509*FLEN/8, x4, x1, x2)

inst_9504:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2e8 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x3f0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78a1; op2val:0xbee8;
op3val:0xf7f0; valaddr_reg:x3; val_offset:28512*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28512*FLEN/8, x4, x1, x2)

inst_9505:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2e8 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x007 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78a1; op2val:0xbee8;
op3val:0xf407; valaddr_reg:x3; val_offset:28515*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28515*FLEN/8, x4, x1, x2)

inst_9506:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2e8 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x3f8 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78a1; op2val:0xbee8;
op3val:0xf7f8; valaddr_reg:x3; val_offset:28518*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28518*FLEN/8, x4, x1, x2)

inst_9507:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2e8 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x003 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78a1; op2val:0xbee8;
op3val:0xf403; valaddr_reg:x3; val_offset:28521*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28521*FLEN/8, x4, x1, x2)

inst_9508:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2e8 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x3fc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78a1; op2val:0xbee8;
op3val:0xf7fc; valaddr_reg:x3; val_offset:28524*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28524*FLEN/8, x4, x1, x2)

inst_9509:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2e8 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78a1; op2val:0xbee8;
op3val:0xf401; valaddr_reg:x3; val_offset:28527*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28527*FLEN/8, x4, x1, x2)

inst_9510:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2e8 and fs3 == 1 and fe3 == 0x1d and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78a1; op2val:0xbee8;
op3val:0xf7fe; valaddr_reg:x3; val_offset:28530*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28530*FLEN/8, x4, x1, x2)

inst_9511:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2e8 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78a1; op2val:0xbee8;
op3val:0xfbfe; valaddr_reg:x3; val_offset:28533*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28533*FLEN/8, x4, x1, x2)

inst_9512:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2e8 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78a1; op2val:0xbee8;
op3val:0xf801; valaddr_reg:x3; val_offset:28536*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28536*FLEN/8, x4, x1, x2)

inst_9513:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2e8 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1b6 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78a1; op2val:0xbee8;
op3val:0xf9b6; valaddr_reg:x3; val_offset:28539*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28539*FLEN/8, x4, x1, x2)

inst_9514:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2e8 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x36d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78a1; op2val:0xbee8;
op3val:0xfb6d; valaddr_reg:x3; val_offset:28542*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28542*FLEN/8, x4, x1, x2)

inst_9515:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2e8 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x0cc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78a1; op2val:0xbee8;
op3val:0xf8cc; valaddr_reg:x3; val_offset:28545*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28545*FLEN/8, x4, x1, x2)

inst_9516:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2e8 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x333 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78a1; op2val:0xbee8;
op3val:0xfb33; valaddr_reg:x3; val_offset:28548*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28548*FLEN/8, x4, x1, x2)

inst_9517:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2e8 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1dd and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78a1; op2val:0xbee8;
op3val:0xf9dd; valaddr_reg:x3; val_offset:28551*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28551*FLEN/8, x4, x1, x2)

inst_9518:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2e8 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x222 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78a1; op2val:0xbee8;
op3val:0xfa22; valaddr_reg:x3; val_offset:28554*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28554*FLEN/8, x4, x1, x2)

inst_9519:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2e8 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x124 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78a1; op2val:0xbee8;
op3val:0xf924; valaddr_reg:x3; val_offset:28557*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28557*FLEN/8, x4, x1, x2)

inst_9520:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2e8 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x2db and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78a1; op2val:0xbee8;
op3val:0xfadb; valaddr_reg:x3; val_offset:28560*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28560*FLEN/8, x4, x1, x2)

inst_9521:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2e8 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x199 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78a1; op2val:0xbee8;
op3val:0xf999; valaddr_reg:x3; val_offset:28563*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28563*FLEN/8, x4, x1, x2)

inst_9522:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x2e8 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x266 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78a1; op2val:0xbee8;
op3val:0xfa66; valaddr_reg:x3; val_offset:28566*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28566*FLEN/8, x4, x1, x2)

inst_9523:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x057 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b5e; op2val:0xbc57;
op3val:0xfbff; valaddr_reg:x3; val_offset:28569*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28569*FLEN/8, x4, x1, x2)

inst_9524:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x057 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b5e; op2val:0xbc57;
op3val:0xf800; valaddr_reg:x3; val_offset:28572*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28572*FLEN/8, x4, x1, x2)

inst_9525:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x057 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b5e; op2val:0xbc57;
op3val:0xf9ff; valaddr_reg:x3; val_offset:28575*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28575*FLEN/8, x4, x1, x2)

inst_9526:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x057 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b5e; op2val:0xbc57;
op3val:0xfa00; valaddr_reg:x3; val_offset:28578*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28578*FLEN/8, x4, x1, x2)

inst_9527:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x057 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x0ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b5e; op2val:0xbc57;
op3val:0xf8ff; valaddr_reg:x3; val_offset:28581*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28581*FLEN/8, x4, x1, x2)

inst_9528:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x057 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x300 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b5e; op2val:0xbc57;
op3val:0xfb00; valaddr_reg:x3; val_offset:28584*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28584*FLEN/8, x4, x1, x2)

inst_9529:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x057 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x07f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b5e; op2val:0xbc57;
op3val:0xf87f; valaddr_reg:x3; val_offset:28587*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28587*FLEN/8, x4, x1, x2)

inst_9530:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x057 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x380 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b5e; op2val:0xbc57;
op3val:0xfb80; valaddr_reg:x3; val_offset:28590*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28590*FLEN/8, x4, x1, x2)

inst_9531:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x057 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x03f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b5e; op2val:0xbc57;
op3val:0xf83f; valaddr_reg:x3; val_offset:28593*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28593*FLEN/8, x4, x1, x2)

inst_9532:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x057 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3c0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b5e; op2val:0xbc57;
op3val:0xfbc0; valaddr_reg:x3; val_offset:28596*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28596*FLEN/8, x4, x1, x2)

inst_9533:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x057 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x01f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b5e; op2val:0xbc57;
op3val:0xf81f; valaddr_reg:x3; val_offset:28599*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28599*FLEN/8, x4, x1, x2)

inst_9534:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x057 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3e0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b5e; op2val:0xbc57;
op3val:0xfbe0; valaddr_reg:x3; val_offset:28602*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28602*FLEN/8, x4, x1, x2)

inst_9535:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x057 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x00f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b5e; op2val:0xbc57;
op3val:0xf80f; valaddr_reg:x3; val_offset:28605*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28605*FLEN/8, x4, x1, x2)

inst_9536:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x057 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3f0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b5e; op2val:0xbc57;
op3val:0xfbf0; valaddr_reg:x3; val_offset:28608*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28608*FLEN/8, x4, x1, x2)

inst_9537:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x057 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x007 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b5e; op2val:0xbc57;
op3val:0xf807; valaddr_reg:x3; val_offset:28611*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28611*FLEN/8, x4, x1, x2)

inst_9538:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x057 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3f8 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b5e; op2val:0xbc57;
op3val:0xfbf8; valaddr_reg:x3; val_offset:28614*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28614*FLEN/8, x4, x1, x2)

inst_9539:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x057 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x003 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b5e; op2val:0xbc57;
op3val:0xf803; valaddr_reg:x3; val_offset:28617*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28617*FLEN/8, x4, x1, x2)

inst_9540:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x057 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3fc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b5e; op2val:0xbc57;
op3val:0xfbfc; valaddr_reg:x3; val_offset:28620*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28620*FLEN/8, x4, x1, x2)

inst_9541:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x057 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b5e; op2val:0xbc57;
op3val:0xf801; valaddr_reg:x3; val_offset:28623*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28623*FLEN/8, x4, x1, x2)

inst_9542:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x057 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b5e; op2val:0xbc57;
op3val:0xfbfe; valaddr_reg:x3; val_offset:28626*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28626*FLEN/8, x4, x1, x2)

inst_9543:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x057 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1b6 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b5e; op2val:0xbc57;
op3val:0xf9b6; valaddr_reg:x3; val_offset:28629*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28629*FLEN/8, x4, x1, x2)

inst_9544:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x057 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x36d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b5e; op2val:0xbc57;
op3val:0xfb6d; valaddr_reg:x3; val_offset:28632*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28632*FLEN/8, x4, x1, x2)

inst_9545:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x057 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x0cc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b5e; op2val:0xbc57;
op3val:0xf8cc; valaddr_reg:x3; val_offset:28635*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28635*FLEN/8, x4, x1, x2)

inst_9546:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x057 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x333 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b5e; op2val:0xbc57;
op3val:0xfb33; valaddr_reg:x3; val_offset:28638*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28638*FLEN/8, x4, x1, x2)

inst_9547:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x057 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1dd and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b5e; op2val:0xbc57;
op3val:0xf9dd; valaddr_reg:x3; val_offset:28641*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28641*FLEN/8, x4, x1, x2)

inst_9548:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x057 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x222 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b5e; op2val:0xbc57;
op3val:0xfa22; valaddr_reg:x3; val_offset:28644*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28644*FLEN/8, x4, x1, x2)

inst_9549:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x057 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x124 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b5e; op2val:0xbc57;
op3val:0xf924; valaddr_reg:x3; val_offset:28647*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28647*FLEN/8, x4, x1, x2)

inst_9550:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x057 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x2db and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b5e; op2val:0xbc57;
op3val:0xfadb; valaddr_reg:x3; val_offset:28650*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28650*FLEN/8, x4, x1, x2)

inst_9551:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x057 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x199 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b5e; op2val:0xbc57;
op3val:0xf999; valaddr_reg:x3; val_offset:28653*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28653*FLEN/8, x4, x1, x2)

inst_9552:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x35e and fs2 == 1 and fe2 == 0x0f and fm2 == 0x057 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x266 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b5e; op2val:0xbc57;
op3val:0xfa66; valaddr_reg:x3; val_offset:28656*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28656*FLEN/8, x4, x1, x2)

inst_9553:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3dd and fs2 == 1 and fe2 == 0x11 and fm2 == 0x011 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x73dd; op2val:0xc411;
op3val:0xfbff; valaddr_reg:x3; val_offset:28659*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28659*FLEN/8, x4, x1, x2)

inst_9554:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3dd and fs2 == 1 and fe2 == 0x11 and fm2 == 0x011 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x73dd; op2val:0xc411;
op3val:0xfbfe; valaddr_reg:x3; val_offset:28662*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28662*FLEN/8, x4, x1, x2)

inst_9555:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3dd and fs2 == 1 and fe2 == 0x11 and fm2 == 0x011 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x73dd; op2val:0xc411;
op3val:0xf801; valaddr_reg:x3; val_offset:28665*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28665*FLEN/8, x4, x1, x2)

inst_9556:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3dd and fs2 == 1 and fe2 == 0x11 and fm2 == 0x011 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1b6 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x73dd; op2val:0xc411;
op3val:0xf9b6; valaddr_reg:x3; val_offset:28668*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28668*FLEN/8, x4, x1, x2)

inst_9557:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3dd and fs2 == 1 and fe2 == 0x11 and fm2 == 0x011 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x36d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x73dd; op2val:0xc411;
op3val:0xfb6d; valaddr_reg:x3; val_offset:28671*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28671*FLEN/8, x4, x1, x2)

inst_9558:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3dd and fs2 == 1 and fe2 == 0x11 and fm2 == 0x011 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x0cc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x73dd; op2val:0xc411;
op3val:0xf8cc; valaddr_reg:x3; val_offset:28674*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28674*FLEN/8, x4, x1, x2)

inst_9559:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3dd and fs2 == 1 and fe2 == 0x11 and fm2 == 0x011 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x333 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x73dd; op2val:0xc411;
op3val:0xfb33; valaddr_reg:x3; val_offset:28677*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28677*FLEN/8, x4, x1, x2)

inst_9560:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3dd and fs2 == 1 and fe2 == 0x11 and fm2 == 0x011 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1dd and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x73dd; op2val:0xc411;
op3val:0xf9dd; valaddr_reg:x3; val_offset:28680*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28680*FLEN/8, x4, x1, x2)

inst_9561:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3dd and fs2 == 1 and fe2 == 0x11 and fm2 == 0x011 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x222 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x73dd; op2val:0xc411;
op3val:0xfa22; valaddr_reg:x3; val_offset:28683*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28683*FLEN/8, x4, x1, x2)

inst_9562:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3dd and fs2 == 1 and fe2 == 0x11 and fm2 == 0x011 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x124 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x73dd; op2val:0xc411;
op3val:0xf924; valaddr_reg:x3; val_offset:28686*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28686*FLEN/8, x4, x1, x2)

inst_9563:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3dd and fs2 == 1 and fe2 == 0x11 and fm2 == 0x011 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x2db and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x73dd; op2val:0xc411;
op3val:0xfadb; valaddr_reg:x3; val_offset:28689*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28689*FLEN/8, x4, x1, x2)

inst_9564:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3dd and fs2 == 1 and fe2 == 0x11 and fm2 == 0x011 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x199 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x73dd; op2val:0xc411;
op3val:0xf999; valaddr_reg:x3; val_offset:28692*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28692*FLEN/8, x4, x1, x2)

inst_9565:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3dd and fs2 == 1 and fe2 == 0x11 and fm2 == 0x011 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x266 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x73dd; op2val:0xc411;
op3val:0xfa66; valaddr_reg:x3; val_offset:28695*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28695*FLEN/8, x4, x1, x2)

inst_9566:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x275 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0f3 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6e75; op2val:0xc8f3;
op3val:0x83ff; valaddr_reg:x3; val_offset:28698*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28698*FLEN/8, x4, x1, x2)

inst_9567:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x275 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0f3 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6e75; op2val:0xc8f3;
op3val:0x8001; valaddr_reg:x3; val_offset:28701*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28701*FLEN/8, x4, x1, x2)

inst_9568:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x275 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0f3 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x1ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6e75; op2val:0xc8f3;
op3val:0x81ff; valaddr_reg:x3; val_offset:28704*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28704*FLEN/8, x4, x1, x2)

inst_9569:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x275 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0f3 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6e75; op2val:0xc8f3;
op3val:0x8200; valaddr_reg:x3; val_offset:28707*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28707*FLEN/8, x4, x1, x2)

inst_9570:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x275 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0f3 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x0ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6e75; op2val:0xc8f3;
op3val:0x80ff; valaddr_reg:x3; val_offset:28710*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28710*FLEN/8, x4, x1, x2)

inst_9571:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x275 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0f3 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x300 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6e75; op2val:0xc8f3;
op3val:0x8300; valaddr_reg:x3; val_offset:28713*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28713*FLEN/8, x4, x1, x2)

inst_9572:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x275 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0f3 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x07f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6e75; op2val:0xc8f3;
op3val:0x807f; valaddr_reg:x3; val_offset:28716*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28716*FLEN/8, x4, x1, x2)

inst_9573:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x275 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0f3 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x380 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6e75; op2val:0xc8f3;
op3val:0x8380; valaddr_reg:x3; val_offset:28719*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28719*FLEN/8, x4, x1, x2)

inst_9574:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x275 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0f3 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x03f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6e75; op2val:0xc8f3;
op3val:0x803f; valaddr_reg:x3; val_offset:28722*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28722*FLEN/8, x4, x1, x2)

inst_9575:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x275 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0f3 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3c0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6e75; op2val:0xc8f3;
op3val:0x83c0; valaddr_reg:x3; val_offset:28725*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28725*FLEN/8, x4, x1, x2)

inst_9576:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x275 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0f3 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x01f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6e75; op2val:0xc8f3;
op3val:0x801f; valaddr_reg:x3; val_offset:28728*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28728*FLEN/8, x4, x1, x2)

inst_9577:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x275 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0f3 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3e0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6e75; op2val:0xc8f3;
op3val:0x83e0; valaddr_reg:x3; val_offset:28731*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28731*FLEN/8, x4, x1, x2)

inst_9578:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x275 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0f3 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x00f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6e75; op2val:0xc8f3;
op3val:0x800f; valaddr_reg:x3; val_offset:28734*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28734*FLEN/8, x4, x1, x2)

inst_9579:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x275 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0f3 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3f0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6e75; op2val:0xc8f3;
op3val:0x83f0; valaddr_reg:x3; val_offset:28737*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28737*FLEN/8, x4, x1, x2)

inst_9580:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x275 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0f3 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x007 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6e75; op2val:0xc8f3;
op3val:0x8007; valaddr_reg:x3; val_offset:28740*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28740*FLEN/8, x4, x1, x2)

inst_9581:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x275 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0f3 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3f8 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6e75; op2val:0xc8f3;
op3val:0x83f8; valaddr_reg:x3; val_offset:28743*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28743*FLEN/8, x4, x1, x2)

inst_9582:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x275 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0f3 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x003 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6e75; op2val:0xc8f3;
op3val:0x8003; valaddr_reg:x3; val_offset:28746*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28746*FLEN/8, x4, x1, x2)

inst_9583:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x275 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0f3 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6e75; op2val:0xc8f3;
op3val:0x83fc; valaddr_reg:x3; val_offset:28749*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28749*FLEN/8, x4, x1, x2)

inst_9584:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x275 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0f3 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6e75; op2val:0xc8f3;
op3val:0x83fe; valaddr_reg:x3; val_offset:28752*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28752*FLEN/8, x4, x1, x2)

inst_9585:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x275 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0f3 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6e75; op2val:0xc8f3;
op3val:0xfbfe; valaddr_reg:x3; val_offset:28755*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28755*FLEN/8, x4, x1, x2)

inst_9586:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x275 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0f3 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6e75; op2val:0xc8f3;
op3val:0xf801; valaddr_reg:x3; val_offset:28758*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28758*FLEN/8, x4, x1, x2)

inst_9587:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x275 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0f3 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1b6 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6e75; op2val:0xc8f3;
op3val:0xf9b6; valaddr_reg:x3; val_offset:28761*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28761*FLEN/8, x4, x1, x2)

inst_9588:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x275 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0f3 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x36d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6e75; op2val:0xc8f3;
op3val:0xfb6d; valaddr_reg:x3; val_offset:28764*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28764*FLEN/8, x4, x1, x2)

inst_9589:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x275 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0f3 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x0cc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6e75; op2val:0xc8f3;
op3val:0xf8cc; valaddr_reg:x3; val_offset:28767*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28767*FLEN/8, x4, x1, x2)

inst_9590:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x275 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0f3 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x333 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6e75; op2val:0xc8f3;
op3val:0xfb33; valaddr_reg:x3; val_offset:28770*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28770*FLEN/8, x4, x1, x2)

inst_9591:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x275 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0f3 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1dd and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6e75; op2val:0xc8f3;
op3val:0xf9dd; valaddr_reg:x3; val_offset:28773*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28773*FLEN/8, x4, x1, x2)

inst_9592:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x275 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0f3 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x222 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6e75; op2val:0xc8f3;
op3val:0xfa22; valaddr_reg:x3; val_offset:28776*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28776*FLEN/8, x4, x1, x2)

inst_9593:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x275 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0f3 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x124 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6e75; op2val:0xc8f3;
op3val:0xf924; valaddr_reg:x3; val_offset:28779*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28779*FLEN/8, x4, x1, x2)

inst_9594:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x275 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0f3 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x2db and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6e75; op2val:0xc8f3;
op3val:0xfadb; valaddr_reg:x3; val_offset:28782*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28782*FLEN/8, x4, x1, x2)

inst_9595:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x275 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0f3 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x199 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6e75; op2val:0xc8f3;
op3val:0xf999; valaddr_reg:x3; val_offset:28785*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28785*FLEN/8, x4, x1, x2)

inst_9596:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x275 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x0f3 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x266 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6e75; op2val:0xc8f3;
op3val:0xfa66; valaddr_reg:x3; val_offset:28788*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28788*FLEN/8, x4, x1, x2)

inst_9597:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x28a and fs3 == 1 and fe3 == 0x01 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78e3; op2val:0xbe8a;
op3val:0x87ff; valaddr_reg:x3; val_offset:28791*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28791*FLEN/8, x4, x1, x2)

inst_9598:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x28a and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78e3; op2val:0xbe8a;
op3val:0x8400; valaddr_reg:x3; val_offset:28794*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28794*FLEN/8, x4, x1, x2)

inst_9599:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x28a and fs3 == 1 and fe3 == 0x01 and fm3 == 0x1ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78e3; op2val:0xbe8a;
op3val:0x85ff; valaddr_reg:x3; val_offset:28797*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28797*FLEN/8, x4, x1, x2)

RVTEST_SIGBASE(x1,signature_x1_76)
inst_9600:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x28a and fs3 == 1 and fe3 == 0x01 and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78e3; op2val:0xbe8a;
op3val:0x8600; valaddr_reg:x3; val_offset:28800*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28800*FLEN/8, x4, x1, x2)

inst_9601:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x28a and fs3 == 1 and fe3 == 0x01 and fm3 == 0x0ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78e3; op2val:0xbe8a;
op3val:0x84ff; valaddr_reg:x3; val_offset:28803*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28803*FLEN/8, x4, x1, x2)

inst_9602:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x28a and fs3 == 1 and fe3 == 0x01 and fm3 == 0x300 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78e3; op2val:0xbe8a;
op3val:0x8700; valaddr_reg:x3; val_offset:28806*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28806*FLEN/8, x4, x1, x2)

inst_9603:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x28a and fs3 == 1 and fe3 == 0x01 and fm3 == 0x07f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78e3; op2val:0xbe8a;
op3val:0x847f; valaddr_reg:x3; val_offset:28809*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28809*FLEN/8, x4, x1, x2)

inst_9604:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x28a and fs3 == 1 and fe3 == 0x01 and fm3 == 0x380 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78e3; op2val:0xbe8a;
op3val:0x8780; valaddr_reg:x3; val_offset:28812*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28812*FLEN/8, x4, x1, x2)

inst_9605:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x28a and fs3 == 1 and fe3 == 0x01 and fm3 == 0x03f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78e3; op2val:0xbe8a;
op3val:0x843f; valaddr_reg:x3; val_offset:28815*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28815*FLEN/8, x4, x1, x2)

inst_9606:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x28a and fs3 == 1 and fe3 == 0x01 and fm3 == 0x3c0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78e3; op2val:0xbe8a;
op3val:0x87c0; valaddr_reg:x3; val_offset:28818*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28818*FLEN/8, x4, x1, x2)

inst_9607:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x28a and fs3 == 1 and fe3 == 0x01 and fm3 == 0x01f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78e3; op2val:0xbe8a;
op3val:0x841f; valaddr_reg:x3; val_offset:28821*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28821*FLEN/8, x4, x1, x2)

inst_9608:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x28a and fs3 == 1 and fe3 == 0x01 and fm3 == 0x3e0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78e3; op2val:0xbe8a;
op3val:0x87e0; valaddr_reg:x3; val_offset:28824*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28824*FLEN/8, x4, x1, x2)

inst_9609:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x28a and fs3 == 1 and fe3 == 0x01 and fm3 == 0x00f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78e3; op2val:0xbe8a;
op3val:0x840f; valaddr_reg:x3; val_offset:28827*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28827*FLEN/8, x4, x1, x2)

inst_9610:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x28a and fs3 == 1 and fe3 == 0x01 and fm3 == 0x3f0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78e3; op2val:0xbe8a;
op3val:0x87f0; valaddr_reg:x3; val_offset:28830*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28830*FLEN/8, x4, x1, x2)

inst_9611:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x28a and fs3 == 1 and fe3 == 0x01 and fm3 == 0x007 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78e3; op2val:0xbe8a;
op3val:0x8407; valaddr_reg:x3; val_offset:28833*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28833*FLEN/8, x4, x1, x2)

inst_9612:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x28a and fs3 == 1 and fe3 == 0x01 and fm3 == 0x3f8 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78e3; op2val:0xbe8a;
op3val:0x87f8; valaddr_reg:x3; val_offset:28836*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28836*FLEN/8, x4, x1, x2)

inst_9613:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x28a and fs3 == 1 and fe3 == 0x01 and fm3 == 0x003 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78e3; op2val:0xbe8a;
op3val:0x8403; valaddr_reg:x3; val_offset:28839*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28839*FLEN/8, x4, x1, x2)

inst_9614:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x28a and fs3 == 1 and fe3 == 0x01 and fm3 == 0x3fc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78e3; op2val:0xbe8a;
op3val:0x87fc; valaddr_reg:x3; val_offset:28842*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28842*FLEN/8, x4, x1, x2)

inst_9615:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x28a and fs3 == 1 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78e3; op2val:0xbe8a;
op3val:0x8401; valaddr_reg:x3; val_offset:28845*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28845*FLEN/8, x4, x1, x2)

inst_9616:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x28a and fs3 == 1 and fe3 == 0x01 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78e3; op2val:0xbe8a;
op3val:0x87fe; valaddr_reg:x3; val_offset:28848*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28848*FLEN/8, x4, x1, x2)

inst_9617:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x28a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78e3; op2val:0xbe8a;
op3val:0xfbfe; valaddr_reg:x3; val_offset:28851*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28851*FLEN/8, x4, x1, x2)

inst_9618:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x28a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78e3; op2val:0xbe8a;
op3val:0xf801; valaddr_reg:x3; val_offset:28854*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28854*FLEN/8, x4, x1, x2)

inst_9619:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x28a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1b6 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78e3; op2val:0xbe8a;
op3val:0xf9b6; valaddr_reg:x3; val_offset:28857*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28857*FLEN/8, x4, x1, x2)

inst_9620:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x28a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x36d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78e3; op2val:0xbe8a;
op3val:0xfb6d; valaddr_reg:x3; val_offset:28860*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28860*FLEN/8, x4, x1, x2)

inst_9621:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x28a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x0cc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78e3; op2val:0xbe8a;
op3val:0xf8cc; valaddr_reg:x3; val_offset:28863*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28863*FLEN/8, x4, x1, x2)

inst_9622:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x28a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x333 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78e3; op2val:0xbe8a;
op3val:0xfb33; valaddr_reg:x3; val_offset:28866*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28866*FLEN/8, x4, x1, x2)

inst_9623:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x28a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1dd and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78e3; op2val:0xbe8a;
op3val:0xf9dd; valaddr_reg:x3; val_offset:28869*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28869*FLEN/8, x4, x1, x2)

inst_9624:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x28a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x222 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78e3; op2val:0xbe8a;
op3val:0xfa22; valaddr_reg:x3; val_offset:28872*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28872*FLEN/8, x4, x1, x2)

inst_9625:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x28a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x124 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78e3; op2val:0xbe8a;
op3val:0xf924; valaddr_reg:x3; val_offset:28875*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28875*FLEN/8, x4, x1, x2)

inst_9626:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x28a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x2db and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78e3; op2val:0xbe8a;
op3val:0xfadb; valaddr_reg:x3; val_offset:28878*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28878*FLEN/8, x4, x1, x2)

inst_9627:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x28a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x199 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78e3; op2val:0xbe8a;
op3val:0xf999; valaddr_reg:x3; val_offset:28881*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28881*FLEN/8, x4, x1, x2)

inst_9628:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x28a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x266 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78e3; op2val:0xbe8a;
op3val:0xfa66; valaddr_reg:x3; val_offset:28884*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28884*FLEN/8, x4, x1, x2)

inst_9629:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x275 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f4 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a75; op2val:0xbcf4;
op3val:0x8bff; valaddr_reg:x3; val_offset:28887*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28887*FLEN/8, x4, x1, x2)

inst_9630:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x275 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f4 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a75; op2val:0xbcf4;
op3val:0x8800; valaddr_reg:x3; val_offset:28890*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28890*FLEN/8, x4, x1, x2)

inst_9631:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x275 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f4 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x1ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a75; op2val:0xbcf4;
op3val:0x89ff; valaddr_reg:x3; val_offset:28893*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28893*FLEN/8, x4, x1, x2)

inst_9632:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x275 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f4 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a75; op2val:0xbcf4;
op3val:0x8a00; valaddr_reg:x3; val_offset:28896*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28896*FLEN/8, x4, x1, x2)

inst_9633:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x275 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f4 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x0ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a75; op2val:0xbcf4;
op3val:0x88ff; valaddr_reg:x3; val_offset:28899*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28899*FLEN/8, x4, x1, x2)

inst_9634:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x275 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f4 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x300 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a75; op2val:0xbcf4;
op3val:0x8b00; valaddr_reg:x3; val_offset:28902*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28902*FLEN/8, x4, x1, x2)

inst_9635:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x275 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f4 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x07f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a75; op2val:0xbcf4;
op3val:0x887f; valaddr_reg:x3; val_offset:28905*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28905*FLEN/8, x4, x1, x2)

inst_9636:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x275 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f4 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x380 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a75; op2val:0xbcf4;
op3val:0x8b80; valaddr_reg:x3; val_offset:28908*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28908*FLEN/8, x4, x1, x2)

inst_9637:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x275 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f4 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x03f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a75; op2val:0xbcf4;
op3val:0x883f; valaddr_reg:x3; val_offset:28911*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28911*FLEN/8, x4, x1, x2)

inst_9638:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x275 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f4 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x3c0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a75; op2val:0xbcf4;
op3val:0x8bc0; valaddr_reg:x3; val_offset:28914*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28914*FLEN/8, x4, x1, x2)

inst_9639:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x275 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f4 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x01f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a75; op2val:0xbcf4;
op3val:0x881f; valaddr_reg:x3; val_offset:28917*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28917*FLEN/8, x4, x1, x2)

inst_9640:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x275 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f4 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x3e0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a75; op2val:0xbcf4;
op3val:0x8be0; valaddr_reg:x3; val_offset:28920*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28920*FLEN/8, x4, x1, x2)

inst_9641:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x275 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f4 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x00f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a75; op2val:0xbcf4;
op3val:0x880f; valaddr_reg:x3; val_offset:28923*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28923*FLEN/8, x4, x1, x2)

inst_9642:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x275 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f4 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x3f0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a75; op2val:0xbcf4;
op3val:0x8bf0; valaddr_reg:x3; val_offset:28926*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28926*FLEN/8, x4, x1, x2)

inst_9643:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x275 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f4 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x007 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a75; op2val:0xbcf4;
op3val:0x8807; valaddr_reg:x3; val_offset:28929*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28929*FLEN/8, x4, x1, x2)

inst_9644:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x275 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f4 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x3f8 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a75; op2val:0xbcf4;
op3val:0x8bf8; valaddr_reg:x3; val_offset:28932*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28932*FLEN/8, x4, x1, x2)

inst_9645:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x275 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f4 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x003 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a75; op2val:0xbcf4;
op3val:0x8803; valaddr_reg:x3; val_offset:28935*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28935*FLEN/8, x4, x1, x2)

inst_9646:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x275 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f4 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x3fc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a75; op2val:0xbcf4;
op3val:0x8bfc; valaddr_reg:x3; val_offset:28938*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28938*FLEN/8, x4, x1, x2)

inst_9647:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x275 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f4 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a75; op2val:0xbcf4;
op3val:0x8801; valaddr_reg:x3; val_offset:28941*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28941*FLEN/8, x4, x1, x2)

inst_9648:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x275 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f4 and fs3 == 1 and fe3 == 0x02 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a75; op2val:0xbcf4;
op3val:0x8bfe; valaddr_reg:x3; val_offset:28944*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28944*FLEN/8, x4, x1, x2)

inst_9649:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x275 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f4 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a75; op2val:0xbcf4;
op3val:0xfbfe; valaddr_reg:x3; val_offset:28947*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28947*FLEN/8, x4, x1, x2)

inst_9650:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x275 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f4 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a75; op2val:0xbcf4;
op3val:0xf801; valaddr_reg:x3; val_offset:28950*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28950*FLEN/8, x4, x1, x2)

inst_9651:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x275 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f4 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1b6 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a75; op2val:0xbcf4;
op3val:0xf9b6; valaddr_reg:x3; val_offset:28953*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28953*FLEN/8, x4, x1, x2)

inst_9652:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x275 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f4 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x36d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a75; op2val:0xbcf4;
op3val:0xfb6d; valaddr_reg:x3; val_offset:28956*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28956*FLEN/8, x4, x1, x2)

inst_9653:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x275 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f4 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x0cc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a75; op2val:0xbcf4;
op3val:0xf8cc; valaddr_reg:x3; val_offset:28959*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28959*FLEN/8, x4, x1, x2)

inst_9654:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x275 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f4 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x333 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a75; op2val:0xbcf4;
op3val:0xfb33; valaddr_reg:x3; val_offset:28962*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28962*FLEN/8, x4, x1, x2)

inst_9655:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x275 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f4 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1dd and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a75; op2val:0xbcf4;
op3val:0xf9dd; valaddr_reg:x3; val_offset:28965*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28965*FLEN/8, x4, x1, x2)

inst_9656:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x275 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f4 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x222 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a75; op2val:0xbcf4;
op3val:0xfa22; valaddr_reg:x3; val_offset:28968*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28968*FLEN/8, x4, x1, x2)

inst_9657:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x275 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f4 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x124 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a75; op2val:0xbcf4;
op3val:0xf924; valaddr_reg:x3; val_offset:28971*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28971*FLEN/8, x4, x1, x2)

inst_9658:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x275 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f4 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x2db and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a75; op2val:0xbcf4;
op3val:0xfadb; valaddr_reg:x3; val_offset:28974*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28974*FLEN/8, x4, x1, x2)

inst_9659:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x275 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f4 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x199 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a75; op2val:0xbcf4;
op3val:0xf999; valaddr_reg:x3; val_offset:28977*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28977*FLEN/8, x4, x1, x2)

inst_9660:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x275 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f4 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x266 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a75; op2val:0xbcf4;
op3val:0xfa66; valaddr_reg:x3; val_offset:28980*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28980*FLEN/8, x4, x1, x2)

inst_9661:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1e3 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x16e and fs3 == 1 and fe3 == 0x03 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6de3; op2val:0xc96e;
op3val:0x8fff; valaddr_reg:x3; val_offset:28983*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28983*FLEN/8, x4, x1, x2)

inst_9662:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1e3 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x16e and fs3 == 1 and fe3 == 0x03 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6de3; op2val:0xc96e;
op3val:0x8c00; valaddr_reg:x3; val_offset:28986*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28986*FLEN/8, x4, x1, x2)

inst_9663:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1e3 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x16e and fs3 == 1 and fe3 == 0x03 and fm3 == 0x1ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6de3; op2val:0xc96e;
op3val:0x8dff; valaddr_reg:x3; val_offset:28989*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28989*FLEN/8, x4, x1, x2)

inst_9664:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1e3 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x16e and fs3 == 1 and fe3 == 0x03 and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6de3; op2val:0xc96e;
op3val:0x8e00; valaddr_reg:x3; val_offset:28992*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28992*FLEN/8, x4, x1, x2)

inst_9665:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1e3 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x16e and fs3 == 1 and fe3 == 0x03 and fm3 == 0x0ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6de3; op2val:0xc96e;
op3val:0x8cff; valaddr_reg:x3; val_offset:28995*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28995*FLEN/8, x4, x1, x2)

inst_9666:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1e3 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x16e and fs3 == 1 and fe3 == 0x03 and fm3 == 0x300 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6de3; op2val:0xc96e;
op3val:0x8f00; valaddr_reg:x3; val_offset:28998*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 28998*FLEN/8, x4, x1, x2)

inst_9667:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1e3 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x16e and fs3 == 1 and fe3 == 0x03 and fm3 == 0x07f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6de3; op2val:0xc96e;
op3val:0x8c7f; valaddr_reg:x3; val_offset:29001*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29001*FLEN/8, x4, x1, x2)

inst_9668:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1e3 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x16e and fs3 == 1 and fe3 == 0x03 and fm3 == 0x380 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6de3; op2val:0xc96e;
op3val:0x8f80; valaddr_reg:x3; val_offset:29004*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29004*FLEN/8, x4, x1, x2)

inst_9669:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1e3 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x16e and fs3 == 1 and fe3 == 0x03 and fm3 == 0x03f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6de3; op2val:0xc96e;
op3val:0x8c3f; valaddr_reg:x3; val_offset:29007*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29007*FLEN/8, x4, x1, x2)

inst_9670:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1e3 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x16e and fs3 == 1 and fe3 == 0x03 and fm3 == 0x3c0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6de3; op2val:0xc96e;
op3val:0x8fc0; valaddr_reg:x3; val_offset:29010*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29010*FLEN/8, x4, x1, x2)

inst_9671:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1e3 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x16e and fs3 == 1 and fe3 == 0x03 and fm3 == 0x01f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6de3; op2val:0xc96e;
op3val:0x8c1f; valaddr_reg:x3; val_offset:29013*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29013*FLEN/8, x4, x1, x2)

inst_9672:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1e3 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x16e and fs3 == 1 and fe3 == 0x03 and fm3 == 0x3e0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6de3; op2val:0xc96e;
op3val:0x8fe0; valaddr_reg:x3; val_offset:29016*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29016*FLEN/8, x4, x1, x2)

inst_9673:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1e3 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x16e and fs3 == 1 and fe3 == 0x03 and fm3 == 0x00f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6de3; op2val:0xc96e;
op3val:0x8c0f; valaddr_reg:x3; val_offset:29019*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29019*FLEN/8, x4, x1, x2)

inst_9674:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1e3 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x16e and fs3 == 1 and fe3 == 0x03 and fm3 == 0x3f0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6de3; op2val:0xc96e;
op3val:0x8ff0; valaddr_reg:x3; val_offset:29022*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29022*FLEN/8, x4, x1, x2)

inst_9675:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1e3 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x16e and fs3 == 1 and fe3 == 0x03 and fm3 == 0x007 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6de3; op2val:0xc96e;
op3val:0x8c07; valaddr_reg:x3; val_offset:29025*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29025*FLEN/8, x4, x1, x2)

inst_9676:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1e3 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x16e and fs3 == 1 and fe3 == 0x03 and fm3 == 0x3f8 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6de3; op2val:0xc96e;
op3val:0x8ff8; valaddr_reg:x3; val_offset:29028*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29028*FLEN/8, x4, x1, x2)

inst_9677:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1e3 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x16e and fs3 == 1 and fe3 == 0x03 and fm3 == 0x003 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6de3; op2val:0xc96e;
op3val:0x8c03; valaddr_reg:x3; val_offset:29031*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29031*FLEN/8, x4, x1, x2)

inst_9678:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1e3 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x16e and fs3 == 1 and fe3 == 0x03 and fm3 == 0x3fc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6de3; op2val:0xc96e;
op3val:0x8ffc; valaddr_reg:x3; val_offset:29034*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29034*FLEN/8, x4, x1, x2)

inst_9679:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1e3 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x16e and fs3 == 1 and fe3 == 0x03 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6de3; op2val:0xc96e;
op3val:0x8c01; valaddr_reg:x3; val_offset:29037*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29037*FLEN/8, x4, x1, x2)

inst_9680:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1e3 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x16e and fs3 == 1 and fe3 == 0x03 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6de3; op2val:0xc96e;
op3val:0x8ffe; valaddr_reg:x3; val_offset:29040*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29040*FLEN/8, x4, x1, x2)

inst_9681:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1e3 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x16e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6de3; op2val:0xc96e;
op3val:0xfbfe; valaddr_reg:x3; val_offset:29043*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29043*FLEN/8, x4, x1, x2)

inst_9682:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1e3 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x16e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6de3; op2val:0xc96e;
op3val:0xf801; valaddr_reg:x3; val_offset:29046*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29046*FLEN/8, x4, x1, x2)

inst_9683:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1e3 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x16e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1b6 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6de3; op2val:0xc96e;
op3val:0xf9b6; valaddr_reg:x3; val_offset:29049*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29049*FLEN/8, x4, x1, x2)

inst_9684:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1e3 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x16e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x36d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6de3; op2val:0xc96e;
op3val:0xfb6d; valaddr_reg:x3; val_offset:29052*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29052*FLEN/8, x4, x1, x2)

inst_9685:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1e3 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x16e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x0cc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6de3; op2val:0xc96e;
op3val:0xf8cc; valaddr_reg:x3; val_offset:29055*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29055*FLEN/8, x4, x1, x2)

inst_9686:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1e3 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x16e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x333 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6de3; op2val:0xc96e;
op3val:0xfb33; valaddr_reg:x3; val_offset:29058*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29058*FLEN/8, x4, x1, x2)

inst_9687:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1e3 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x16e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1dd and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6de3; op2val:0xc96e;
op3val:0xf9dd; valaddr_reg:x3; val_offset:29061*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29061*FLEN/8, x4, x1, x2)

inst_9688:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1e3 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x16e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x222 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6de3; op2val:0xc96e;
op3val:0xfa22; valaddr_reg:x3; val_offset:29064*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29064*FLEN/8, x4, x1, x2)

inst_9689:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1e3 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x16e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x124 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6de3; op2val:0xc96e;
op3val:0xf924; valaddr_reg:x3; val_offset:29067*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29067*FLEN/8, x4, x1, x2)

inst_9690:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1e3 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x16e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x2db and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6de3; op2val:0xc96e;
op3val:0xfadb; valaddr_reg:x3; val_offset:29070*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29070*FLEN/8, x4, x1, x2)

inst_9691:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1e3 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x16e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x199 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6de3; op2val:0xc96e;
op3val:0xf999; valaddr_reg:x3; val_offset:29073*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29073*FLEN/8, x4, x1, x2)

inst_9692:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1e3 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x16e and fs3 == 1 and fe3 == 0x1e and fm3 == 0x266 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6de3; op2val:0xc96e;
op3val:0xfa66; valaddr_reg:x3; val_offset:29076*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29076*FLEN/8, x4, x1, x2)

inst_9693:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x08a and fs3 == 1 and fe3 == 0x04 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x730a; op2val:0xc48a;
op3val:0x93ff; valaddr_reg:x3; val_offset:29079*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29079*FLEN/8, x4, x1, x2)

inst_9694:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x08a and fs3 == 1 and fe3 == 0x04 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x730a; op2val:0xc48a;
op3val:0x9000; valaddr_reg:x3; val_offset:29082*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29082*FLEN/8, x4, x1, x2)

inst_9695:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x08a and fs3 == 1 and fe3 == 0x04 and fm3 == 0x1ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x730a; op2val:0xc48a;
op3val:0x91ff; valaddr_reg:x3; val_offset:29085*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29085*FLEN/8, x4, x1, x2)

inst_9696:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x08a and fs3 == 1 and fe3 == 0x04 and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x730a; op2val:0xc48a;
op3val:0x9200; valaddr_reg:x3; val_offset:29088*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29088*FLEN/8, x4, x1, x2)

inst_9697:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x08a and fs3 == 1 and fe3 == 0x04 and fm3 == 0x0ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x730a; op2val:0xc48a;
op3val:0x90ff; valaddr_reg:x3; val_offset:29091*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29091*FLEN/8, x4, x1, x2)

inst_9698:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x08a and fs3 == 1 and fe3 == 0x04 and fm3 == 0x300 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x730a; op2val:0xc48a;
op3val:0x9300; valaddr_reg:x3; val_offset:29094*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29094*FLEN/8, x4, x1, x2)

inst_9699:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x08a and fs3 == 1 and fe3 == 0x04 and fm3 == 0x07f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x730a; op2val:0xc48a;
op3val:0x907f; valaddr_reg:x3; val_offset:29097*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29097*FLEN/8, x4, x1, x2)

inst_9700:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x08a and fs3 == 1 and fe3 == 0x04 and fm3 == 0x380 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x730a; op2val:0xc48a;
op3val:0x9380; valaddr_reg:x3; val_offset:29100*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29100*FLEN/8, x4, x1, x2)

inst_9701:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x08a and fs3 == 1 and fe3 == 0x04 and fm3 == 0x03f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x730a; op2val:0xc48a;
op3val:0x903f; valaddr_reg:x3; val_offset:29103*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29103*FLEN/8, x4, x1, x2)

inst_9702:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x08a and fs3 == 1 and fe3 == 0x04 and fm3 == 0x3c0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x730a; op2val:0xc48a;
op3val:0x93c0; valaddr_reg:x3; val_offset:29106*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29106*FLEN/8, x4, x1, x2)

inst_9703:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x08a and fs3 == 1 and fe3 == 0x04 and fm3 == 0x01f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x730a; op2val:0xc48a;
op3val:0x901f; valaddr_reg:x3; val_offset:29109*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29109*FLEN/8, x4, x1, x2)

inst_9704:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x08a and fs3 == 1 and fe3 == 0x04 and fm3 == 0x3e0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x730a; op2val:0xc48a;
op3val:0x93e0; valaddr_reg:x3; val_offset:29112*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29112*FLEN/8, x4, x1, x2)

inst_9705:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x08a and fs3 == 1 and fe3 == 0x04 and fm3 == 0x00f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x730a; op2val:0xc48a;
op3val:0x900f; valaddr_reg:x3; val_offset:29115*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29115*FLEN/8, x4, x1, x2)

inst_9706:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x08a and fs3 == 1 and fe3 == 0x04 and fm3 == 0x3f0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x730a; op2val:0xc48a;
op3val:0x93f0; valaddr_reg:x3; val_offset:29118*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29118*FLEN/8, x4, x1, x2)

inst_9707:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x08a and fs3 == 1 and fe3 == 0x04 and fm3 == 0x007 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x730a; op2val:0xc48a;
op3val:0x9007; valaddr_reg:x3; val_offset:29121*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29121*FLEN/8, x4, x1, x2)

inst_9708:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x08a and fs3 == 1 and fe3 == 0x04 and fm3 == 0x3f8 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x730a; op2val:0xc48a;
op3val:0x93f8; valaddr_reg:x3; val_offset:29124*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29124*FLEN/8, x4, x1, x2)

inst_9709:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x08a and fs3 == 1 and fe3 == 0x04 and fm3 == 0x003 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x730a; op2val:0xc48a;
op3val:0x9003; valaddr_reg:x3; val_offset:29127*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29127*FLEN/8, x4, x1, x2)

inst_9710:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x08a and fs3 == 1 and fe3 == 0x04 and fm3 == 0x3fc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x730a; op2val:0xc48a;
op3val:0x93fc; valaddr_reg:x3; val_offset:29130*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29130*FLEN/8, x4, x1, x2)

inst_9711:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x08a and fs3 == 1 and fe3 == 0x04 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x730a; op2val:0xc48a;
op3val:0x9001; valaddr_reg:x3; val_offset:29133*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29133*FLEN/8, x4, x1, x2)

inst_9712:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x08a and fs3 == 1 and fe3 == 0x04 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x730a; op2val:0xc48a;
op3val:0x93fe; valaddr_reg:x3; val_offset:29136*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29136*FLEN/8, x4, x1, x2)

inst_9713:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x08a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x730a; op2val:0xc48a;
op3val:0xfbfe; valaddr_reg:x3; val_offset:29139*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29139*FLEN/8, x4, x1, x2)

inst_9714:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x08a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x730a; op2val:0xc48a;
op3val:0xf801; valaddr_reg:x3; val_offset:29142*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29142*FLEN/8, x4, x1, x2)

inst_9715:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x08a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1b6 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x730a; op2val:0xc48a;
op3val:0xf9b6; valaddr_reg:x3; val_offset:29145*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29145*FLEN/8, x4, x1, x2)

inst_9716:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x08a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x36d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x730a; op2val:0xc48a;
op3val:0xfb6d; valaddr_reg:x3; val_offset:29148*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29148*FLEN/8, x4, x1, x2)

inst_9717:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x08a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x0cc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x730a; op2val:0xc48a;
op3val:0xf8cc; valaddr_reg:x3; val_offset:29151*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29151*FLEN/8, x4, x1, x2)

inst_9718:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x08a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x333 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x730a; op2val:0xc48a;
op3val:0xfb33; valaddr_reg:x3; val_offset:29154*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29154*FLEN/8, x4, x1, x2)

inst_9719:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x08a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1dd and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x730a; op2val:0xc48a;
op3val:0xf9dd; valaddr_reg:x3; val_offset:29157*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29157*FLEN/8, x4, x1, x2)

inst_9720:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x08a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x222 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x730a; op2val:0xc48a;
op3val:0xfa22; valaddr_reg:x3; val_offset:29160*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29160*FLEN/8, x4, x1, x2)

inst_9721:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x08a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x124 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x730a; op2val:0xc48a;
op3val:0xf924; valaddr_reg:x3; val_offset:29163*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29163*FLEN/8, x4, x1, x2)

inst_9722:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x08a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x2db and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x730a; op2val:0xc48a;
op3val:0xfadb; valaddr_reg:x3; val_offset:29166*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29166*FLEN/8, x4, x1, x2)

inst_9723:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x08a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x199 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x730a; op2val:0xc48a;
op3val:0xf999; valaddr_reg:x3; val_offset:29169*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29169*FLEN/8, x4, x1, x2)

inst_9724:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30a and fs2 == 1 and fe2 == 0x11 and fm2 == 0x08a and fs3 == 1 and fe3 == 0x1e and fm3 == 0x266 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x730a; op2val:0xc48a;
op3val:0xfa66; valaddr_reg:x3; val_offset:29172*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29172*FLEN/8, x4, x1, x2)

inst_9725:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f2 and fs3 == 1 and fe3 == 0x05 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a76; op2val:0xbcf2;
op3val:0x97ff; valaddr_reg:x3; val_offset:29175*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29175*FLEN/8, x4, x1, x2)

inst_9726:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f2 and fs3 == 1 and fe3 == 0x05 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a76; op2val:0xbcf2;
op3val:0x9400; valaddr_reg:x3; val_offset:29178*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29178*FLEN/8, x4, x1, x2)

inst_9727:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f2 and fs3 == 1 and fe3 == 0x05 and fm3 == 0x1ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a76; op2val:0xbcf2;
op3val:0x95ff; valaddr_reg:x3; val_offset:29181*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29181*FLEN/8, x4, x1, x2)

RVTEST_SIGBASE(x1,signature_x1_77)
inst_9728:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f2 and fs3 == 1 and fe3 == 0x05 and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a76; op2val:0xbcf2;
op3val:0x9600; valaddr_reg:x3; val_offset:29184*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29184*FLEN/8, x4, x1, x2)

inst_9729:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f2 and fs3 == 1 and fe3 == 0x05 and fm3 == 0x0ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a76; op2val:0xbcf2;
op3val:0x94ff; valaddr_reg:x3; val_offset:29187*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29187*FLEN/8, x4, x1, x2)

inst_9730:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f2 and fs3 == 1 and fe3 == 0x05 and fm3 == 0x300 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a76; op2val:0xbcf2;
op3val:0x9700; valaddr_reg:x3; val_offset:29190*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29190*FLEN/8, x4, x1, x2)

inst_9731:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f2 and fs3 == 1 and fe3 == 0x05 and fm3 == 0x07f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a76; op2val:0xbcf2;
op3val:0x947f; valaddr_reg:x3; val_offset:29193*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29193*FLEN/8, x4, x1, x2)

inst_9732:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f2 and fs3 == 1 and fe3 == 0x05 and fm3 == 0x380 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a76; op2val:0xbcf2;
op3val:0x9780; valaddr_reg:x3; val_offset:29196*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29196*FLEN/8, x4, x1, x2)

inst_9733:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f2 and fs3 == 1 and fe3 == 0x05 and fm3 == 0x03f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a76; op2val:0xbcf2;
op3val:0x943f; valaddr_reg:x3; val_offset:29199*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29199*FLEN/8, x4, x1, x2)

inst_9734:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f2 and fs3 == 1 and fe3 == 0x05 and fm3 == 0x3c0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a76; op2val:0xbcf2;
op3val:0x97c0; valaddr_reg:x3; val_offset:29202*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29202*FLEN/8, x4, x1, x2)

inst_9735:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f2 and fs3 == 1 and fe3 == 0x05 and fm3 == 0x01f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a76; op2val:0xbcf2;
op3val:0x941f; valaddr_reg:x3; val_offset:29205*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29205*FLEN/8, x4, x1, x2)

inst_9736:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f2 and fs3 == 1 and fe3 == 0x05 and fm3 == 0x3e0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a76; op2val:0xbcf2;
op3val:0x97e0; valaddr_reg:x3; val_offset:29208*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29208*FLEN/8, x4, x1, x2)

inst_9737:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f2 and fs3 == 1 and fe3 == 0x05 and fm3 == 0x00f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a76; op2val:0xbcf2;
op3val:0x940f; valaddr_reg:x3; val_offset:29211*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29211*FLEN/8, x4, x1, x2)

inst_9738:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f2 and fs3 == 1 and fe3 == 0x05 and fm3 == 0x3f0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a76; op2val:0xbcf2;
op3val:0x97f0; valaddr_reg:x3; val_offset:29214*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29214*FLEN/8, x4, x1, x2)

inst_9739:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f2 and fs3 == 1 and fe3 == 0x05 and fm3 == 0x007 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a76; op2val:0xbcf2;
op3val:0x9407; valaddr_reg:x3; val_offset:29217*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29217*FLEN/8, x4, x1, x2)

inst_9740:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f2 and fs3 == 1 and fe3 == 0x05 and fm3 == 0x3f8 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a76; op2val:0xbcf2;
op3val:0x97f8; valaddr_reg:x3; val_offset:29220*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29220*FLEN/8, x4, x1, x2)

inst_9741:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f2 and fs3 == 1 and fe3 == 0x05 and fm3 == 0x003 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a76; op2val:0xbcf2;
op3val:0x9403; valaddr_reg:x3; val_offset:29223*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29223*FLEN/8, x4, x1, x2)

inst_9742:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f2 and fs3 == 1 and fe3 == 0x05 and fm3 == 0x3fc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a76; op2val:0xbcf2;
op3val:0x97fc; valaddr_reg:x3; val_offset:29226*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29226*FLEN/8, x4, x1, x2)

inst_9743:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f2 and fs3 == 1 and fe3 == 0x05 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a76; op2val:0xbcf2;
op3val:0x9401; valaddr_reg:x3; val_offset:29229*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29229*FLEN/8, x4, x1, x2)

inst_9744:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f2 and fs3 == 1 and fe3 == 0x05 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a76; op2val:0xbcf2;
op3val:0x97fe; valaddr_reg:x3; val_offset:29232*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29232*FLEN/8, x4, x1, x2)

inst_9745:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f2 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a76; op2val:0xbcf2;
op3val:0xfbfe; valaddr_reg:x3; val_offset:29235*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29235*FLEN/8, x4, x1, x2)

inst_9746:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f2 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a76; op2val:0xbcf2;
op3val:0xf801; valaddr_reg:x3; val_offset:29238*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29238*FLEN/8, x4, x1, x2)

inst_9747:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f2 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1b6 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a76; op2val:0xbcf2;
op3val:0xf9b6; valaddr_reg:x3; val_offset:29241*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29241*FLEN/8, x4, x1, x2)

inst_9748:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f2 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x36d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a76; op2val:0xbcf2;
op3val:0xfb6d; valaddr_reg:x3; val_offset:29244*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29244*FLEN/8, x4, x1, x2)

inst_9749:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f2 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x0cc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a76; op2val:0xbcf2;
op3val:0xf8cc; valaddr_reg:x3; val_offset:29247*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29247*FLEN/8, x4, x1, x2)

inst_9750:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f2 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x333 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a76; op2val:0xbcf2;
op3val:0xfb33; valaddr_reg:x3; val_offset:29250*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29250*FLEN/8, x4, x1, x2)

inst_9751:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f2 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1dd and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a76; op2val:0xbcf2;
op3val:0xf9dd; valaddr_reg:x3; val_offset:29253*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29253*FLEN/8, x4, x1, x2)

inst_9752:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f2 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x222 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a76; op2val:0xbcf2;
op3val:0xfa22; valaddr_reg:x3; val_offset:29256*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29256*FLEN/8, x4, x1, x2)

inst_9753:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f2 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x124 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a76; op2val:0xbcf2;
op3val:0xf924; valaddr_reg:x3; val_offset:29259*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29259*FLEN/8, x4, x1, x2)

inst_9754:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f2 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x2db and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a76; op2val:0xbcf2;
op3val:0xfadb; valaddr_reg:x3; val_offset:29262*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29262*FLEN/8, x4, x1, x2)

inst_9755:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f2 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x199 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a76; op2val:0xbcf2;
op3val:0xf999; valaddr_reg:x3; val_offset:29265*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29265*FLEN/8, x4, x1, x2)

inst_9756:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x276 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0f2 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x266 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a76; op2val:0xbcf2;
op3val:0xfa66; valaddr_reg:x3; val_offset:29268*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29268*FLEN/8, x4, x1, x2)

inst_9757:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0fa and fs3 == 1 and fe3 == 0x06 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x766c; op2val:0xc0fa;
op3val:0x9bff; valaddr_reg:x3; val_offset:29271*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29271*FLEN/8, x4, x1, x2)

inst_9758:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0fa and fs3 == 1 and fe3 == 0x06 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x766c; op2val:0xc0fa;
op3val:0x9800; valaddr_reg:x3; val_offset:29274*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29274*FLEN/8, x4, x1, x2)

inst_9759:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0fa and fs3 == 1 and fe3 == 0x06 and fm3 == 0x1ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x766c; op2val:0xc0fa;
op3val:0x99ff; valaddr_reg:x3; val_offset:29277*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29277*FLEN/8, x4, x1, x2)

inst_9760:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0fa and fs3 == 1 and fe3 == 0x06 and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x766c; op2val:0xc0fa;
op3val:0x9a00; valaddr_reg:x3; val_offset:29280*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29280*FLEN/8, x4, x1, x2)

inst_9761:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0fa and fs3 == 1 and fe3 == 0x06 and fm3 == 0x0ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x766c; op2val:0xc0fa;
op3val:0x98ff; valaddr_reg:x3; val_offset:29283*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29283*FLEN/8, x4, x1, x2)

inst_9762:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0fa and fs3 == 1 and fe3 == 0x06 and fm3 == 0x300 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x766c; op2val:0xc0fa;
op3val:0x9b00; valaddr_reg:x3; val_offset:29286*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29286*FLEN/8, x4, x1, x2)

inst_9763:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0fa and fs3 == 1 and fe3 == 0x06 and fm3 == 0x07f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x766c; op2val:0xc0fa;
op3val:0x987f; valaddr_reg:x3; val_offset:29289*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29289*FLEN/8, x4, x1, x2)

inst_9764:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0fa and fs3 == 1 and fe3 == 0x06 and fm3 == 0x380 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x766c; op2val:0xc0fa;
op3val:0x9b80; valaddr_reg:x3; val_offset:29292*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29292*FLEN/8, x4, x1, x2)

inst_9765:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0fa and fs3 == 1 and fe3 == 0x06 and fm3 == 0x03f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x766c; op2val:0xc0fa;
op3val:0x983f; valaddr_reg:x3; val_offset:29295*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29295*FLEN/8, x4, x1, x2)

inst_9766:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0fa and fs3 == 1 and fe3 == 0x06 and fm3 == 0x3c0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x766c; op2val:0xc0fa;
op3val:0x9bc0; valaddr_reg:x3; val_offset:29298*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29298*FLEN/8, x4, x1, x2)

inst_9767:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0fa and fs3 == 1 and fe3 == 0x06 and fm3 == 0x01f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x766c; op2val:0xc0fa;
op3val:0x981f; valaddr_reg:x3; val_offset:29301*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29301*FLEN/8, x4, x1, x2)

inst_9768:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0fa and fs3 == 1 and fe3 == 0x06 and fm3 == 0x3e0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x766c; op2val:0xc0fa;
op3val:0x9be0; valaddr_reg:x3; val_offset:29304*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29304*FLEN/8, x4, x1, x2)

inst_9769:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0fa and fs3 == 1 and fe3 == 0x06 and fm3 == 0x00f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x766c; op2val:0xc0fa;
op3val:0x980f; valaddr_reg:x3; val_offset:29307*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29307*FLEN/8, x4, x1, x2)

inst_9770:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0fa and fs3 == 1 and fe3 == 0x06 and fm3 == 0x3f0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x766c; op2val:0xc0fa;
op3val:0x9bf0; valaddr_reg:x3; val_offset:29310*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29310*FLEN/8, x4, x1, x2)

inst_9771:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0fa and fs3 == 1 and fe3 == 0x06 and fm3 == 0x007 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x766c; op2val:0xc0fa;
op3val:0x9807; valaddr_reg:x3; val_offset:29313*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29313*FLEN/8, x4, x1, x2)

inst_9772:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0fa and fs3 == 1 and fe3 == 0x06 and fm3 == 0x3f8 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x766c; op2val:0xc0fa;
op3val:0x9bf8; valaddr_reg:x3; val_offset:29316*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29316*FLEN/8, x4, x1, x2)

inst_9773:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0fa and fs3 == 1 and fe3 == 0x06 and fm3 == 0x003 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x766c; op2val:0xc0fa;
op3val:0x9803; valaddr_reg:x3; val_offset:29319*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29319*FLEN/8, x4, x1, x2)

inst_9774:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0fa and fs3 == 1 and fe3 == 0x06 and fm3 == 0x3fc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x766c; op2val:0xc0fa;
op3val:0x9bfc; valaddr_reg:x3; val_offset:29322*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29322*FLEN/8, x4, x1, x2)

inst_9775:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0fa and fs3 == 1 and fe3 == 0x06 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x766c; op2val:0xc0fa;
op3val:0x9801; valaddr_reg:x3; val_offset:29325*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29325*FLEN/8, x4, x1, x2)

inst_9776:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0fa and fs3 == 1 and fe3 == 0x06 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x766c; op2val:0xc0fa;
op3val:0x9bfe; valaddr_reg:x3; val_offset:29328*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29328*FLEN/8, x4, x1, x2)

inst_9777:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0fa and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x766c; op2val:0xc0fa;
op3val:0xfbfe; valaddr_reg:x3; val_offset:29331*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29331*FLEN/8, x4, x1, x2)

inst_9778:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0fa and fs3 == 1 and fe3 == 0x1e and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x766c; op2val:0xc0fa;
op3val:0xf801; valaddr_reg:x3; val_offset:29334*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29334*FLEN/8, x4, x1, x2)

inst_9779:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0fa and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1b6 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x766c; op2val:0xc0fa;
op3val:0xf9b6; valaddr_reg:x3; val_offset:29337*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29337*FLEN/8, x4, x1, x2)

inst_9780:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0fa and fs3 == 1 and fe3 == 0x1e and fm3 == 0x36d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x766c; op2val:0xc0fa;
op3val:0xfb6d; valaddr_reg:x3; val_offset:29340*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29340*FLEN/8, x4, x1, x2)

inst_9781:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0fa and fs3 == 1 and fe3 == 0x1e and fm3 == 0x0cc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x766c; op2val:0xc0fa;
op3val:0xf8cc; valaddr_reg:x3; val_offset:29343*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29343*FLEN/8, x4, x1, x2)

inst_9782:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0fa and fs3 == 1 and fe3 == 0x1e and fm3 == 0x333 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x766c; op2val:0xc0fa;
op3val:0xfb33; valaddr_reg:x3; val_offset:29346*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29346*FLEN/8, x4, x1, x2)

inst_9783:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0fa and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1dd and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x766c; op2val:0xc0fa;
op3val:0xf9dd; valaddr_reg:x3; val_offset:29349*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29349*FLEN/8, x4, x1, x2)

inst_9784:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0fa and fs3 == 1 and fe3 == 0x1e and fm3 == 0x222 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x766c; op2val:0xc0fa;
op3val:0xfa22; valaddr_reg:x3; val_offset:29352*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29352*FLEN/8, x4, x1, x2)

inst_9785:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0fa and fs3 == 1 and fe3 == 0x1e and fm3 == 0x124 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x766c; op2val:0xc0fa;
op3val:0xf924; valaddr_reg:x3; val_offset:29355*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29355*FLEN/8, x4, x1, x2)

inst_9786:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0fa and fs3 == 1 and fe3 == 0x1e and fm3 == 0x2db and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x766c; op2val:0xc0fa;
op3val:0xfadb; valaddr_reg:x3; val_offset:29358*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29358*FLEN/8, x4, x1, x2)

inst_9787:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0fa and fs3 == 1 and fe3 == 0x1e and fm3 == 0x199 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x766c; op2val:0xc0fa;
op3val:0xf999; valaddr_reg:x3; val_offset:29361*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29361*FLEN/8, x4, x1, x2)

inst_9788:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26c and fs2 == 1 and fe2 == 0x10 and fm2 == 0x0fa and fs3 == 1 and fe3 == 0x1e and fm3 == 0x266 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x766c; op2val:0xc0fa;
op3val:0xfa66; valaddr_reg:x3; val_offset:29364*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29364*FLEN/8, x4, x1, x2)

inst_9789:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x049 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x375 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7449; op2val:0xc375;
op3val:0x9fff; valaddr_reg:x3; val_offset:29367*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29367*FLEN/8, x4, x1, x2)

inst_9790:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x049 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x375 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7449; op2val:0xc375;
op3val:0x9c00; valaddr_reg:x3; val_offset:29370*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29370*FLEN/8, x4, x1, x2)

inst_9791:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x049 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x375 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x1ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7449; op2val:0xc375;
op3val:0x9dff; valaddr_reg:x3; val_offset:29373*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29373*FLEN/8, x4, x1, x2)

inst_9792:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x049 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x375 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7449; op2val:0xc375;
op3val:0x9e00; valaddr_reg:x3; val_offset:29376*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29376*FLEN/8, x4, x1, x2)

inst_9793:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x049 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x375 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x0ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7449; op2val:0xc375;
op3val:0x9cff; valaddr_reg:x3; val_offset:29379*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29379*FLEN/8, x4, x1, x2)

inst_9794:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x049 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x375 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x300 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7449; op2val:0xc375;
op3val:0x9f00; valaddr_reg:x3; val_offset:29382*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29382*FLEN/8, x4, x1, x2)

inst_9795:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x049 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x375 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x07f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7449; op2val:0xc375;
op3val:0x9c7f; valaddr_reg:x3; val_offset:29385*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29385*FLEN/8, x4, x1, x2)

inst_9796:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x049 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x375 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x380 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7449; op2val:0xc375;
op3val:0x9f80; valaddr_reg:x3; val_offset:29388*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29388*FLEN/8, x4, x1, x2)

inst_9797:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x049 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x375 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x03f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7449; op2val:0xc375;
op3val:0x9c3f; valaddr_reg:x3; val_offset:29391*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29391*FLEN/8, x4, x1, x2)

inst_9798:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x049 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x375 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x3c0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7449; op2val:0xc375;
op3val:0x9fc0; valaddr_reg:x3; val_offset:29394*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29394*FLEN/8, x4, x1, x2)

inst_9799:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x049 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x375 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x01f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7449; op2val:0xc375;
op3val:0x9c1f; valaddr_reg:x3; val_offset:29397*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29397*FLEN/8, x4, x1, x2)

inst_9800:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x049 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x375 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x3e0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7449; op2val:0xc375;
op3val:0x9fe0; valaddr_reg:x3; val_offset:29400*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29400*FLEN/8, x4, x1, x2)

inst_9801:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x049 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x375 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x00f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7449; op2val:0xc375;
op3val:0x9c0f; valaddr_reg:x3; val_offset:29403*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29403*FLEN/8, x4, x1, x2)

inst_9802:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x049 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x375 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x3f0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7449; op2val:0xc375;
op3val:0x9ff0; valaddr_reg:x3; val_offset:29406*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29406*FLEN/8, x4, x1, x2)

inst_9803:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x049 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x375 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x007 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7449; op2val:0xc375;
op3val:0x9c07; valaddr_reg:x3; val_offset:29409*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29409*FLEN/8, x4, x1, x2)

inst_9804:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x049 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x375 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x3f8 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7449; op2val:0xc375;
op3val:0x9ff8; valaddr_reg:x3; val_offset:29412*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29412*FLEN/8, x4, x1, x2)

inst_9805:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x049 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x375 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x003 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7449; op2val:0xc375;
op3val:0x9c03; valaddr_reg:x3; val_offset:29415*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29415*FLEN/8, x4, x1, x2)

inst_9806:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x049 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x375 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x3fc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7449; op2val:0xc375;
op3val:0x9ffc; valaddr_reg:x3; val_offset:29418*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29418*FLEN/8, x4, x1, x2)

inst_9807:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x049 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x375 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7449; op2val:0xc375;
op3val:0x9c01; valaddr_reg:x3; val_offset:29421*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29421*FLEN/8, x4, x1, x2)

inst_9808:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x049 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x375 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7449; op2val:0xc375;
op3val:0x9ffe; valaddr_reg:x3; val_offset:29424*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29424*FLEN/8, x4, x1, x2)

inst_9809:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x049 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x375 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7449; op2val:0xc375;
op3val:0xfbfe; valaddr_reg:x3; val_offset:29427*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29427*FLEN/8, x4, x1, x2)

inst_9810:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x049 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x375 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7449; op2val:0xc375;
op3val:0xf801; valaddr_reg:x3; val_offset:29430*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29430*FLEN/8, x4, x1, x2)

inst_9811:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x049 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x375 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1b6 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7449; op2val:0xc375;
op3val:0xf9b6; valaddr_reg:x3; val_offset:29433*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29433*FLEN/8, x4, x1, x2)

inst_9812:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x049 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x375 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x36d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7449; op2val:0xc375;
op3val:0xfb6d; valaddr_reg:x3; val_offset:29436*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29436*FLEN/8, x4, x1, x2)

inst_9813:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x049 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x375 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x0cc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7449; op2val:0xc375;
op3val:0xf8cc; valaddr_reg:x3; val_offset:29439*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29439*FLEN/8, x4, x1, x2)

inst_9814:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x049 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x375 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x333 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7449; op2val:0xc375;
op3val:0xfb33; valaddr_reg:x3; val_offset:29442*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29442*FLEN/8, x4, x1, x2)

inst_9815:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x049 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x375 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1dd and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7449; op2val:0xc375;
op3val:0xf9dd; valaddr_reg:x3; val_offset:29445*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29445*FLEN/8, x4, x1, x2)

inst_9816:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x049 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x375 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x222 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7449; op2val:0xc375;
op3val:0xfa22; valaddr_reg:x3; val_offset:29448*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29448*FLEN/8, x4, x1, x2)

inst_9817:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x049 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x375 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x124 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7449; op2val:0xc375;
op3val:0xf924; valaddr_reg:x3; val_offset:29451*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29451*FLEN/8, x4, x1, x2)

inst_9818:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x049 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x375 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x2db and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7449; op2val:0xc375;
op3val:0xfadb; valaddr_reg:x3; val_offset:29454*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29454*FLEN/8, x4, x1, x2)

inst_9819:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x049 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x375 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x199 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7449; op2val:0xc375;
op3val:0xf999; valaddr_reg:x3; val_offset:29457*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29457*FLEN/8, x4, x1, x2)

inst_9820:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x049 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x375 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x266 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7449; op2val:0xc375;
op3val:0xfa66; valaddr_reg:x3; val_offset:29460*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29460*FLEN/8, x4, x1, x2)

inst_9821:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x0f and fm2 == 0x09c and fs3 == 1 and fe3 == 0x08 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7aef; op2val:0xbc9c;
op3val:0xa3ff; valaddr_reg:x3; val_offset:29463*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29463*FLEN/8, x4, x1, x2)

inst_9822:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x0f and fm2 == 0x09c and fs3 == 1 and fe3 == 0x08 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7aef; op2val:0xbc9c;
op3val:0xa000; valaddr_reg:x3; val_offset:29466*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29466*FLEN/8, x4, x1, x2)

inst_9823:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x0f and fm2 == 0x09c and fs3 == 1 and fe3 == 0x08 and fm3 == 0x1ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7aef; op2val:0xbc9c;
op3val:0xa1ff; valaddr_reg:x3; val_offset:29469*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29469*FLEN/8, x4, x1, x2)

inst_9824:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x0f and fm2 == 0x09c and fs3 == 1 and fe3 == 0x08 and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7aef; op2val:0xbc9c;
op3val:0xa200; valaddr_reg:x3; val_offset:29472*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29472*FLEN/8, x4, x1, x2)

inst_9825:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x0f and fm2 == 0x09c and fs3 == 1 and fe3 == 0x08 and fm3 == 0x0ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7aef; op2val:0xbc9c;
op3val:0xa0ff; valaddr_reg:x3; val_offset:29475*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29475*FLEN/8, x4, x1, x2)

inst_9826:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x0f and fm2 == 0x09c and fs3 == 1 and fe3 == 0x08 and fm3 == 0x300 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7aef; op2val:0xbc9c;
op3val:0xa300; valaddr_reg:x3; val_offset:29478*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29478*FLEN/8, x4, x1, x2)

inst_9827:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x0f and fm2 == 0x09c and fs3 == 1 and fe3 == 0x08 and fm3 == 0x07f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7aef; op2val:0xbc9c;
op3val:0xa07f; valaddr_reg:x3; val_offset:29481*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29481*FLEN/8, x4, x1, x2)

inst_9828:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x0f and fm2 == 0x09c and fs3 == 1 and fe3 == 0x08 and fm3 == 0x380 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7aef; op2val:0xbc9c;
op3val:0xa380; valaddr_reg:x3; val_offset:29484*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29484*FLEN/8, x4, x1, x2)

inst_9829:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x0f and fm2 == 0x09c and fs3 == 1 and fe3 == 0x08 and fm3 == 0x03f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7aef; op2val:0xbc9c;
op3val:0xa03f; valaddr_reg:x3; val_offset:29487*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29487*FLEN/8, x4, x1, x2)

inst_9830:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x0f and fm2 == 0x09c and fs3 == 1 and fe3 == 0x08 and fm3 == 0x3c0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7aef; op2val:0xbc9c;
op3val:0xa3c0; valaddr_reg:x3; val_offset:29490*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29490*FLEN/8, x4, x1, x2)

inst_9831:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x0f and fm2 == 0x09c and fs3 == 1 and fe3 == 0x08 and fm3 == 0x01f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7aef; op2val:0xbc9c;
op3val:0xa01f; valaddr_reg:x3; val_offset:29493*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29493*FLEN/8, x4, x1, x2)

inst_9832:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x0f and fm2 == 0x09c and fs3 == 1 and fe3 == 0x08 and fm3 == 0x3e0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7aef; op2val:0xbc9c;
op3val:0xa3e0; valaddr_reg:x3; val_offset:29496*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29496*FLEN/8, x4, x1, x2)

inst_9833:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x0f and fm2 == 0x09c and fs3 == 1 and fe3 == 0x08 and fm3 == 0x00f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7aef; op2val:0xbc9c;
op3val:0xa00f; valaddr_reg:x3; val_offset:29499*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29499*FLEN/8, x4, x1, x2)

inst_9834:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x0f and fm2 == 0x09c and fs3 == 1 and fe3 == 0x08 and fm3 == 0x3f0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7aef; op2val:0xbc9c;
op3val:0xa3f0; valaddr_reg:x3; val_offset:29502*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29502*FLEN/8, x4, x1, x2)

inst_9835:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x0f and fm2 == 0x09c and fs3 == 1 and fe3 == 0x08 and fm3 == 0x007 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7aef; op2val:0xbc9c;
op3val:0xa007; valaddr_reg:x3; val_offset:29505*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29505*FLEN/8, x4, x1, x2)

inst_9836:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x0f and fm2 == 0x09c and fs3 == 1 and fe3 == 0x08 and fm3 == 0x3f8 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7aef; op2val:0xbc9c;
op3val:0xa3f8; valaddr_reg:x3; val_offset:29508*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29508*FLEN/8, x4, x1, x2)

inst_9837:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x0f and fm2 == 0x09c and fs3 == 1 and fe3 == 0x08 and fm3 == 0x003 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7aef; op2val:0xbc9c;
op3val:0xa003; valaddr_reg:x3; val_offset:29511*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29511*FLEN/8, x4, x1, x2)

inst_9838:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x0f and fm2 == 0x09c and fs3 == 1 and fe3 == 0x08 and fm3 == 0x3fc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7aef; op2val:0xbc9c;
op3val:0xa3fc; valaddr_reg:x3; val_offset:29514*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29514*FLEN/8, x4, x1, x2)

inst_9839:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x0f and fm2 == 0x09c and fs3 == 1 and fe3 == 0x08 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7aef; op2val:0xbc9c;
op3val:0xa001; valaddr_reg:x3; val_offset:29517*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29517*FLEN/8, x4, x1, x2)

inst_9840:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x0f and fm2 == 0x09c and fs3 == 1 and fe3 == 0x08 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7aef; op2val:0xbc9c;
op3val:0xa3fe; valaddr_reg:x3; val_offset:29520*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29520*FLEN/8, x4, x1, x2)

inst_9841:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x0f and fm2 == 0x09c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7aef; op2val:0xbc9c;
op3val:0xfbfe; valaddr_reg:x3; val_offset:29523*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29523*FLEN/8, x4, x1, x2)

inst_9842:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x0f and fm2 == 0x09c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7aef; op2val:0xbc9c;
op3val:0xf801; valaddr_reg:x3; val_offset:29526*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29526*FLEN/8, x4, x1, x2)

inst_9843:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x0f and fm2 == 0x09c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1b6 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7aef; op2val:0xbc9c;
op3val:0xf9b6; valaddr_reg:x3; val_offset:29529*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29529*FLEN/8, x4, x1, x2)

inst_9844:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x0f and fm2 == 0x09c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x36d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7aef; op2val:0xbc9c;
op3val:0xfb6d; valaddr_reg:x3; val_offset:29532*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29532*FLEN/8, x4, x1, x2)

inst_9845:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x0f and fm2 == 0x09c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x0cc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7aef; op2val:0xbc9c;
op3val:0xf8cc; valaddr_reg:x3; val_offset:29535*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29535*FLEN/8, x4, x1, x2)

inst_9846:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x0f and fm2 == 0x09c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x333 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7aef; op2val:0xbc9c;
op3val:0xfb33; valaddr_reg:x3; val_offset:29538*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29538*FLEN/8, x4, x1, x2)

inst_9847:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x0f and fm2 == 0x09c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1dd and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7aef; op2val:0xbc9c;
op3val:0xf9dd; valaddr_reg:x3; val_offset:29541*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29541*FLEN/8, x4, x1, x2)

inst_9848:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x0f and fm2 == 0x09c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x222 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7aef; op2val:0xbc9c;
op3val:0xfa22; valaddr_reg:x3; val_offset:29544*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29544*FLEN/8, x4, x1, x2)

inst_9849:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x0f and fm2 == 0x09c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x124 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7aef; op2val:0xbc9c;
op3val:0xf924; valaddr_reg:x3; val_offset:29547*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29547*FLEN/8, x4, x1, x2)

inst_9850:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x0f and fm2 == 0x09c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x2db and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7aef; op2val:0xbc9c;
op3val:0xfadb; valaddr_reg:x3; val_offset:29550*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29550*FLEN/8, x4, x1, x2)

inst_9851:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x0f and fm2 == 0x09c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x199 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7aef; op2val:0xbc9c;
op3val:0xf999; valaddr_reg:x3; val_offset:29553*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29553*FLEN/8, x4, x1, x2)

inst_9852:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x0f and fm2 == 0x09c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x266 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7aef; op2val:0xbc9c;
op3val:0xfa66; valaddr_reg:x3; val_offset:29556*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29556*FLEN/8, x4, x1, x2)

inst_9853:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x17c and fs3 == 1 and fe3 == 0x09 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79d4; op2val:0xbd7c;
op3val:0xa7ff; valaddr_reg:x3; val_offset:29559*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29559*FLEN/8, x4, x1, x2)

inst_9854:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x17c and fs3 == 1 and fe3 == 0x09 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79d4; op2val:0xbd7c;
op3val:0xa400; valaddr_reg:x3; val_offset:29562*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29562*FLEN/8, x4, x1, x2)

inst_9855:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x17c and fs3 == 1 and fe3 == 0x09 and fm3 == 0x1ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79d4; op2val:0xbd7c;
op3val:0xa5ff; valaddr_reg:x3; val_offset:29565*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29565*FLEN/8, x4, x1, x2)

RVTEST_SIGBASE(x1,signature_x1_78)
inst_9856:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x17c and fs3 == 1 and fe3 == 0x09 and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79d4; op2val:0xbd7c;
op3val:0xa600; valaddr_reg:x3; val_offset:29568*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29568*FLEN/8, x4, x1, x2)

inst_9857:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x17c and fs3 == 1 and fe3 == 0x09 and fm3 == 0x0ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79d4; op2val:0xbd7c;
op3val:0xa4ff; valaddr_reg:x3; val_offset:29571*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29571*FLEN/8, x4, x1, x2)

inst_9858:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x17c and fs3 == 1 and fe3 == 0x09 and fm3 == 0x300 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79d4; op2val:0xbd7c;
op3val:0xa700; valaddr_reg:x3; val_offset:29574*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29574*FLEN/8, x4, x1, x2)

inst_9859:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x17c and fs3 == 1 and fe3 == 0x09 and fm3 == 0x07f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79d4; op2val:0xbd7c;
op3val:0xa47f; valaddr_reg:x3; val_offset:29577*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29577*FLEN/8, x4, x1, x2)

inst_9860:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x17c and fs3 == 1 and fe3 == 0x09 and fm3 == 0x380 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79d4; op2val:0xbd7c;
op3val:0xa780; valaddr_reg:x3; val_offset:29580*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29580*FLEN/8, x4, x1, x2)

inst_9861:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x17c and fs3 == 1 and fe3 == 0x09 and fm3 == 0x03f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79d4; op2val:0xbd7c;
op3val:0xa43f; valaddr_reg:x3; val_offset:29583*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29583*FLEN/8, x4, x1, x2)

inst_9862:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x17c and fs3 == 1 and fe3 == 0x09 and fm3 == 0x3c0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79d4; op2val:0xbd7c;
op3val:0xa7c0; valaddr_reg:x3; val_offset:29586*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29586*FLEN/8, x4, x1, x2)

inst_9863:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x17c and fs3 == 1 and fe3 == 0x09 and fm3 == 0x01f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79d4; op2val:0xbd7c;
op3val:0xa41f; valaddr_reg:x3; val_offset:29589*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29589*FLEN/8, x4, x1, x2)

inst_9864:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x17c and fs3 == 1 and fe3 == 0x09 and fm3 == 0x3e0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79d4; op2val:0xbd7c;
op3val:0xa7e0; valaddr_reg:x3; val_offset:29592*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29592*FLEN/8, x4, x1, x2)

inst_9865:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x17c and fs3 == 1 and fe3 == 0x09 and fm3 == 0x00f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79d4; op2val:0xbd7c;
op3val:0xa40f; valaddr_reg:x3; val_offset:29595*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29595*FLEN/8, x4, x1, x2)

inst_9866:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x17c and fs3 == 1 and fe3 == 0x09 and fm3 == 0x3f0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79d4; op2val:0xbd7c;
op3val:0xa7f0; valaddr_reg:x3; val_offset:29598*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29598*FLEN/8, x4, x1, x2)

inst_9867:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x17c and fs3 == 1 and fe3 == 0x09 and fm3 == 0x007 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79d4; op2val:0xbd7c;
op3val:0xa407; valaddr_reg:x3; val_offset:29601*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29601*FLEN/8, x4, x1, x2)

inst_9868:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x17c and fs3 == 1 and fe3 == 0x09 and fm3 == 0x3f8 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79d4; op2val:0xbd7c;
op3val:0xa7f8; valaddr_reg:x3; val_offset:29604*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29604*FLEN/8, x4, x1, x2)

inst_9869:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x17c and fs3 == 1 and fe3 == 0x09 and fm3 == 0x003 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79d4; op2val:0xbd7c;
op3val:0xa403; valaddr_reg:x3; val_offset:29607*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29607*FLEN/8, x4, x1, x2)

inst_9870:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x17c and fs3 == 1 and fe3 == 0x09 and fm3 == 0x3fc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79d4; op2val:0xbd7c;
op3val:0xa7fc; valaddr_reg:x3; val_offset:29610*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29610*FLEN/8, x4, x1, x2)

inst_9871:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x17c and fs3 == 1 and fe3 == 0x09 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79d4; op2val:0xbd7c;
op3val:0xa401; valaddr_reg:x3; val_offset:29613*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29613*FLEN/8, x4, x1, x2)

inst_9872:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x17c and fs3 == 1 and fe3 == 0x09 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79d4; op2val:0xbd7c;
op3val:0xa7fe; valaddr_reg:x3; val_offset:29616*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29616*FLEN/8, x4, x1, x2)

inst_9873:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x17c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79d4; op2val:0xbd7c;
op3val:0xfbfe; valaddr_reg:x3; val_offset:29619*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29619*FLEN/8, x4, x1, x2)

inst_9874:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x17c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79d4; op2val:0xbd7c;
op3val:0xf801; valaddr_reg:x3; val_offset:29622*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29622*FLEN/8, x4, x1, x2)

inst_9875:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x17c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1b6 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79d4; op2val:0xbd7c;
op3val:0xf9b6; valaddr_reg:x3; val_offset:29625*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29625*FLEN/8, x4, x1, x2)

inst_9876:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x17c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x36d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79d4; op2val:0xbd7c;
op3val:0xfb6d; valaddr_reg:x3; val_offset:29628*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29628*FLEN/8, x4, x1, x2)

inst_9877:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x17c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x0cc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79d4; op2val:0xbd7c;
op3val:0xf8cc; valaddr_reg:x3; val_offset:29631*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29631*FLEN/8, x4, x1, x2)

inst_9878:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x17c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x333 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79d4; op2val:0xbd7c;
op3val:0xfb33; valaddr_reg:x3; val_offset:29634*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29634*FLEN/8, x4, x1, x2)

inst_9879:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x17c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1dd and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79d4; op2val:0xbd7c;
op3val:0xf9dd; valaddr_reg:x3; val_offset:29637*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29637*FLEN/8, x4, x1, x2)

inst_9880:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x17c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x222 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79d4; op2val:0xbd7c;
op3val:0xfa22; valaddr_reg:x3; val_offset:29640*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29640*FLEN/8, x4, x1, x2)

inst_9881:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x17c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x124 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79d4; op2val:0xbd7c;
op3val:0xf924; valaddr_reg:x3; val_offset:29643*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29643*FLEN/8, x4, x1, x2)

inst_9882:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x17c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x2db and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79d4; op2val:0xbd7c;
op3val:0xfadb; valaddr_reg:x3; val_offset:29646*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29646*FLEN/8, x4, x1, x2)

inst_9883:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x17c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x199 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79d4; op2val:0xbd7c;
op3val:0xf999; valaddr_reg:x3; val_offset:29649*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29649*FLEN/8, x4, x1, x2)

inst_9884:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d4 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x17c and fs3 == 1 and fe3 == 0x1e and fm3 == 0x266 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79d4; op2val:0xbd7c;
op3val:0xfa66; valaddr_reg:x3; val_offset:29652*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29652*FLEN/8, x4, x1, x2)

inst_9885:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x182 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1ce and fs3 == 1 and fe3 == 0x0a and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6582; op2val:0xd1ce;
op3val:0xabff; valaddr_reg:x3; val_offset:29655*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29655*FLEN/8, x4, x1, x2)

inst_9886:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x182 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1ce and fs3 == 1 and fe3 == 0x0a and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6582; op2val:0xd1ce;
op3val:0xa800; valaddr_reg:x3; val_offset:29658*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29658*FLEN/8, x4, x1, x2)

inst_9887:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x182 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1ce and fs3 == 1 and fe3 == 0x0a and fm3 == 0x1ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6582; op2val:0xd1ce;
op3val:0xa9ff; valaddr_reg:x3; val_offset:29661*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29661*FLEN/8, x4, x1, x2)

inst_9888:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x182 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1ce and fs3 == 1 and fe3 == 0x0a and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6582; op2val:0xd1ce;
op3val:0xaa00; valaddr_reg:x3; val_offset:29664*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29664*FLEN/8, x4, x1, x2)

inst_9889:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x182 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1ce and fs3 == 1 and fe3 == 0x0a and fm3 == 0x0ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6582; op2val:0xd1ce;
op3val:0xa8ff; valaddr_reg:x3; val_offset:29667*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29667*FLEN/8, x4, x1, x2)

inst_9890:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x182 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1ce and fs3 == 1 and fe3 == 0x0a and fm3 == 0x300 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6582; op2val:0xd1ce;
op3val:0xab00; valaddr_reg:x3; val_offset:29670*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29670*FLEN/8, x4, x1, x2)

inst_9891:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x182 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1ce and fs3 == 1 and fe3 == 0x0a and fm3 == 0x07f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6582; op2val:0xd1ce;
op3val:0xa87f; valaddr_reg:x3; val_offset:29673*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29673*FLEN/8, x4, x1, x2)

inst_9892:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x182 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1ce and fs3 == 1 and fe3 == 0x0a and fm3 == 0x380 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6582; op2val:0xd1ce;
op3val:0xab80; valaddr_reg:x3; val_offset:29676*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29676*FLEN/8, x4, x1, x2)

inst_9893:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x182 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1ce and fs3 == 1 and fe3 == 0x0a and fm3 == 0x03f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6582; op2val:0xd1ce;
op3val:0xa83f; valaddr_reg:x3; val_offset:29679*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29679*FLEN/8, x4, x1, x2)

inst_9894:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x182 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1ce and fs3 == 1 and fe3 == 0x0a and fm3 == 0x3c0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6582; op2val:0xd1ce;
op3val:0xabc0; valaddr_reg:x3; val_offset:29682*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29682*FLEN/8, x4, x1, x2)

inst_9895:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x182 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1ce and fs3 == 1 and fe3 == 0x0a and fm3 == 0x01f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6582; op2val:0xd1ce;
op3val:0xa81f; valaddr_reg:x3; val_offset:29685*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29685*FLEN/8, x4, x1, x2)

inst_9896:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x182 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1ce and fs3 == 1 and fe3 == 0x0a and fm3 == 0x3e0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6582; op2val:0xd1ce;
op3val:0xabe0; valaddr_reg:x3; val_offset:29688*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29688*FLEN/8, x4, x1, x2)

inst_9897:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x182 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1ce and fs3 == 1 and fe3 == 0x0a and fm3 == 0x00f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6582; op2val:0xd1ce;
op3val:0xa80f; valaddr_reg:x3; val_offset:29691*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29691*FLEN/8, x4, x1, x2)

inst_9898:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x182 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1ce and fs3 == 1 and fe3 == 0x0a and fm3 == 0x3f0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6582; op2val:0xd1ce;
op3val:0xabf0; valaddr_reg:x3; val_offset:29694*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29694*FLEN/8, x4, x1, x2)

inst_9899:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x182 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1ce and fs3 == 1 and fe3 == 0x0a and fm3 == 0x007 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6582; op2val:0xd1ce;
op3val:0xa807; valaddr_reg:x3; val_offset:29697*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29697*FLEN/8, x4, x1, x2)

inst_9900:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x182 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1ce and fs3 == 1 and fe3 == 0x0a and fm3 == 0x3f8 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6582; op2val:0xd1ce;
op3val:0xabf8; valaddr_reg:x3; val_offset:29700*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29700*FLEN/8, x4, x1, x2)

inst_9901:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x182 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1ce and fs3 == 1 and fe3 == 0x0a and fm3 == 0x003 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6582; op2val:0xd1ce;
op3val:0xa803; valaddr_reg:x3; val_offset:29703*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29703*FLEN/8, x4, x1, x2)

inst_9902:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x182 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1ce and fs3 == 1 and fe3 == 0x0a and fm3 == 0x3fc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6582; op2val:0xd1ce;
op3val:0xabfc; valaddr_reg:x3; val_offset:29706*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29706*FLEN/8, x4, x1, x2)

inst_9903:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x182 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1ce and fs3 == 1 and fe3 == 0x0a and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6582; op2val:0xd1ce;
op3val:0xa801; valaddr_reg:x3; val_offset:29709*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29709*FLEN/8, x4, x1, x2)

inst_9904:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x182 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1ce and fs3 == 1 and fe3 == 0x0a and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6582; op2val:0xd1ce;
op3val:0xabfe; valaddr_reg:x3; val_offset:29712*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29712*FLEN/8, x4, x1, x2)

inst_9905:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x182 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1ce and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6582; op2val:0xd1ce;
op3val:0xfbfe; valaddr_reg:x3; val_offset:29715*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29715*FLEN/8, x4, x1, x2)

inst_9906:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x182 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1ce and fs3 == 1 and fe3 == 0x1e and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6582; op2val:0xd1ce;
op3val:0xf801; valaddr_reg:x3; val_offset:29718*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29718*FLEN/8, x4, x1, x2)

inst_9907:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x182 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1ce and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1b6 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6582; op2val:0xd1ce;
op3val:0xf9b6; valaddr_reg:x3; val_offset:29721*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29721*FLEN/8, x4, x1, x2)

inst_9908:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x182 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1ce and fs3 == 1 and fe3 == 0x1e and fm3 == 0x36d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6582; op2val:0xd1ce;
op3val:0xfb6d; valaddr_reg:x3; val_offset:29724*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29724*FLEN/8, x4, x1, x2)

inst_9909:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x182 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1ce and fs3 == 1 and fe3 == 0x1e and fm3 == 0x0cc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6582; op2val:0xd1ce;
op3val:0xf8cc; valaddr_reg:x3; val_offset:29727*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29727*FLEN/8, x4, x1, x2)

inst_9910:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x182 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1ce and fs3 == 1 and fe3 == 0x1e and fm3 == 0x333 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6582; op2val:0xd1ce;
op3val:0xfb33; valaddr_reg:x3; val_offset:29730*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29730*FLEN/8, x4, x1, x2)

inst_9911:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x182 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1ce and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1dd and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6582; op2val:0xd1ce;
op3val:0xf9dd; valaddr_reg:x3; val_offset:29733*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29733*FLEN/8, x4, x1, x2)

inst_9912:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x182 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1ce and fs3 == 1 and fe3 == 0x1e and fm3 == 0x222 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6582; op2val:0xd1ce;
op3val:0xfa22; valaddr_reg:x3; val_offset:29736*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29736*FLEN/8, x4, x1, x2)

inst_9913:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x182 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1ce and fs3 == 1 and fe3 == 0x1e and fm3 == 0x124 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6582; op2val:0xd1ce;
op3val:0xf924; valaddr_reg:x3; val_offset:29739*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29739*FLEN/8, x4, x1, x2)

inst_9914:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x182 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1ce and fs3 == 1 and fe3 == 0x1e and fm3 == 0x2db and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6582; op2val:0xd1ce;
op3val:0xfadb; valaddr_reg:x3; val_offset:29742*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29742*FLEN/8, x4, x1, x2)

inst_9915:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x182 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1ce and fs3 == 1 and fe3 == 0x1e and fm3 == 0x199 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6582; op2val:0xd1ce;
op3val:0xf999; valaddr_reg:x3; val_offset:29745*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29745*FLEN/8, x4, x1, x2)

inst_9916:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x182 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x1ce and fs3 == 1 and fe3 == 0x1e and fm3 == 0x266 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6582; op2val:0xd1ce;
op3val:0xfa66; valaddr_reg:x3; val_offset:29748*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29748*FLEN/8, x4, x1, x2)

inst_9917:
// fs1 == 0 and fe1 == 0x18 and fm1 == 0x115 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x24a and fs3 == 1 and fe3 == 0x0b and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6115; op2val:0xd64a;
op3val:0xafff; valaddr_reg:x3; val_offset:29751*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29751*FLEN/8, x4, x1, x2)

inst_9918:
// fs1 == 0 and fe1 == 0x18 and fm1 == 0x115 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x24a and fs3 == 1 and fe3 == 0x0b and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6115; op2val:0xd64a;
op3val:0xac00; valaddr_reg:x3; val_offset:29754*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29754*FLEN/8, x4, x1, x2)

inst_9919:
// fs1 == 0 and fe1 == 0x18 and fm1 == 0x115 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x24a and fs3 == 1 and fe3 == 0x0b and fm3 == 0x1ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6115; op2val:0xd64a;
op3val:0xadff; valaddr_reg:x3; val_offset:29757*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29757*FLEN/8, x4, x1, x2)

inst_9920:
// fs1 == 0 and fe1 == 0x18 and fm1 == 0x115 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x24a and fs3 == 1 and fe3 == 0x0b and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6115; op2val:0xd64a;
op3val:0xae00; valaddr_reg:x3; val_offset:29760*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29760*FLEN/8, x4, x1, x2)

inst_9921:
// fs1 == 0 and fe1 == 0x18 and fm1 == 0x115 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x24a and fs3 == 1 and fe3 == 0x0b and fm3 == 0x0ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6115; op2val:0xd64a;
op3val:0xacff; valaddr_reg:x3; val_offset:29763*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29763*FLEN/8, x4, x1, x2)

inst_9922:
// fs1 == 0 and fe1 == 0x18 and fm1 == 0x115 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x24a and fs3 == 1 and fe3 == 0x0b and fm3 == 0x300 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6115; op2val:0xd64a;
op3val:0xaf00; valaddr_reg:x3; val_offset:29766*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29766*FLEN/8, x4, x1, x2)

inst_9923:
// fs1 == 0 and fe1 == 0x18 and fm1 == 0x115 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x24a and fs3 == 1 and fe3 == 0x0b and fm3 == 0x07f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6115; op2val:0xd64a;
op3val:0xac7f; valaddr_reg:x3; val_offset:29769*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29769*FLEN/8, x4, x1, x2)

inst_9924:
// fs1 == 0 and fe1 == 0x18 and fm1 == 0x115 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x24a and fs3 == 1 and fe3 == 0x0b and fm3 == 0x380 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6115; op2val:0xd64a;
op3val:0xaf80; valaddr_reg:x3; val_offset:29772*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29772*FLEN/8, x4, x1, x2)

inst_9925:
// fs1 == 0 and fe1 == 0x18 and fm1 == 0x115 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x24a and fs3 == 1 and fe3 == 0x0b and fm3 == 0x03f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6115; op2val:0xd64a;
op3val:0xac3f; valaddr_reg:x3; val_offset:29775*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29775*FLEN/8, x4, x1, x2)

inst_9926:
// fs1 == 0 and fe1 == 0x18 and fm1 == 0x115 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x24a and fs3 == 1 and fe3 == 0x0b and fm3 == 0x3c0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6115; op2val:0xd64a;
op3val:0xafc0; valaddr_reg:x3; val_offset:29778*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29778*FLEN/8, x4, x1, x2)

inst_9927:
// fs1 == 0 and fe1 == 0x18 and fm1 == 0x115 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x24a and fs3 == 1 and fe3 == 0x0b and fm3 == 0x01f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6115; op2val:0xd64a;
op3val:0xac1f; valaddr_reg:x3; val_offset:29781*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29781*FLEN/8, x4, x1, x2)

inst_9928:
// fs1 == 0 and fe1 == 0x18 and fm1 == 0x115 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x24a and fs3 == 1 and fe3 == 0x0b and fm3 == 0x3e0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6115; op2val:0xd64a;
op3val:0xafe0; valaddr_reg:x3; val_offset:29784*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29784*FLEN/8, x4, x1, x2)

inst_9929:
// fs1 == 0 and fe1 == 0x18 and fm1 == 0x115 and fs2 == 1 and fe2 == 0x15 and fm2 == 0x24a and fs3 == 1 and fe3 == 0x0b and fm3 == 0x00f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6115; op2val:0xd64a;
op3val:0xac0f; valaddr_reg:x3; val_offset:29787*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29787*FLEN/8, x4, x1, x2)

inst_9971:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x154 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1b6 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a00; op2val:0xbd54;
op3val:0xf9b6; valaddr_reg:x3; val_offset:29913*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29913*FLEN/8, x4, x1, x2)

inst_9972:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x154 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x36d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a00; op2val:0xbd54;
op3val:0xfb6d; valaddr_reg:x3; val_offset:29916*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29916*FLEN/8, x4, x1, x2)

inst_9973:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x154 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x0cc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a00; op2val:0xbd54;
op3val:0xf8cc; valaddr_reg:x3; val_offset:29919*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29919*FLEN/8, x4, x1, x2)

inst_9974:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x154 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x333 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a00; op2val:0xbd54;
op3val:0xfb33; valaddr_reg:x3; val_offset:29922*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29922*FLEN/8, x4, x1, x2)

inst_9975:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x154 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1dd and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a00; op2val:0xbd54;
op3val:0xf9dd; valaddr_reg:x3; val_offset:29925*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29925*FLEN/8, x4, x1, x2)

inst_9976:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x154 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x222 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a00; op2val:0xbd54;
op3val:0xfa22; valaddr_reg:x3; val_offset:29928*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29928*FLEN/8, x4, x1, x2)

inst_9977:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x154 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x124 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a00; op2val:0xbd54;
op3val:0xf924; valaddr_reg:x3; val_offset:29931*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29931*FLEN/8, x4, x1, x2)

inst_9978:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x154 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x2db and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a00; op2val:0xbd54;
op3val:0xfadb; valaddr_reg:x3; val_offset:29934*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29934*FLEN/8, x4, x1, x2)

inst_9979:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x154 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x199 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a00; op2val:0xbd54;
op3val:0xf999; valaddr_reg:x3; val_offset:29937*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29937*FLEN/8, x4, x1, x2)

inst_9980:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x200 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x154 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x266 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a00; op2val:0xbd54;
op3val:0xfa66; valaddr_reg:x3; val_offset:29940*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29940*FLEN/8, x4, x1, x2)

inst_9981:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1be and fs2 == 1 and fe2 == 0x10 and fm2 == 0x191 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75be; op2val:0xc191;
op3val:0xb7ff; valaddr_reg:x3; val_offset:29943*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29943*FLEN/8, x4, x1, x2)

inst_9982:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1be and fs2 == 1 and fe2 == 0x10 and fm2 == 0x191 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75be; op2val:0xc191;
op3val:0xb400; valaddr_reg:x3; val_offset:29946*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29946*FLEN/8, x4, x1, x2)

inst_9983:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1be and fs2 == 1 and fe2 == 0x10 and fm2 == 0x191 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x1ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75be; op2val:0xc191;
op3val:0xb5ff; valaddr_reg:x3; val_offset:29949*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29949*FLEN/8, x4, x1, x2)

RVTEST_SIGBASE(x1,signature_x1_79)
inst_9984:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1be and fs2 == 1 and fe2 == 0x10 and fm2 == 0x191 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75be; op2val:0xc191;
op3val:0xb600; valaddr_reg:x3; val_offset:29952*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29952*FLEN/8, x4, x1, x2)

inst_9985:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1be and fs2 == 1 and fe2 == 0x10 and fm2 == 0x191 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x0ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75be; op2val:0xc191;
op3val:0xb4ff; valaddr_reg:x3; val_offset:29955*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29955*FLEN/8, x4, x1, x2)

inst_9986:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1be and fs2 == 1 and fe2 == 0x10 and fm2 == 0x191 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x300 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75be; op2val:0xc191;
op3val:0xb700; valaddr_reg:x3; val_offset:29958*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29958*FLEN/8, x4, x1, x2)

inst_9987:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1be and fs2 == 1 and fe2 == 0x10 and fm2 == 0x191 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x07f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75be; op2val:0xc191;
op3val:0xb47f; valaddr_reg:x3; val_offset:29961*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29961*FLEN/8, x4, x1, x2)

inst_9988:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1be and fs2 == 1 and fe2 == 0x10 and fm2 == 0x191 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x380 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75be; op2val:0xc191;
op3val:0xb780; valaddr_reg:x3; val_offset:29964*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29964*FLEN/8, x4, x1, x2)

inst_9989:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1be and fs2 == 1 and fe2 == 0x10 and fm2 == 0x191 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x03f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75be; op2val:0xc191;
op3val:0xb43f; valaddr_reg:x3; val_offset:29967*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29967*FLEN/8, x4, x1, x2)

inst_9990:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1be and fs2 == 1 and fe2 == 0x10 and fm2 == 0x191 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x3c0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75be; op2val:0xc191;
op3val:0xb7c0; valaddr_reg:x3; val_offset:29970*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29970*FLEN/8, x4, x1, x2)

inst_9991:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1be and fs2 == 1 and fe2 == 0x10 and fm2 == 0x191 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x01f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75be; op2val:0xc191;
op3val:0xb41f; valaddr_reg:x3; val_offset:29973*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29973*FLEN/8, x4, x1, x2)

inst_9992:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1be and fs2 == 1 and fe2 == 0x10 and fm2 == 0x191 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x3e0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75be; op2val:0xc191;
op3val:0xb7e0; valaddr_reg:x3; val_offset:29976*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29976*FLEN/8, x4, x1, x2)

inst_9993:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1be and fs2 == 1 and fe2 == 0x10 and fm2 == 0x191 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x00f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75be; op2val:0xc191;
op3val:0xb40f; valaddr_reg:x3; val_offset:29979*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29979*FLEN/8, x4, x1, x2)

inst_9994:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1be and fs2 == 1 and fe2 == 0x10 and fm2 == 0x191 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x3f0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75be; op2val:0xc191;
op3val:0xb7f0; valaddr_reg:x3; val_offset:29982*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29982*FLEN/8, x4, x1, x2)

inst_9995:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1be and fs2 == 1 and fe2 == 0x10 and fm2 == 0x191 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x007 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75be; op2val:0xc191;
op3val:0xb407; valaddr_reg:x3; val_offset:29985*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29985*FLEN/8, x4, x1, x2)

inst_9996:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1be and fs2 == 1 and fe2 == 0x10 and fm2 == 0x191 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x3f8 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75be; op2val:0xc191;
op3val:0xb7f8; valaddr_reg:x3; val_offset:29988*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29988*FLEN/8, x4, x1, x2)

inst_9997:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1be and fs2 == 1 and fe2 == 0x10 and fm2 == 0x191 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x003 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75be; op2val:0xc191;
op3val:0xb403; valaddr_reg:x3; val_offset:29991*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29991*FLEN/8, x4, x1, x2)

inst_9998:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1be and fs2 == 1 and fe2 == 0x10 and fm2 == 0x191 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x3fc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75be; op2val:0xc191;
op3val:0xb7fc; valaddr_reg:x3; val_offset:29994*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29994*FLEN/8, x4, x1, x2)

inst_9999:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1be and fs2 == 1 and fe2 == 0x10 and fm2 == 0x191 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75be; op2val:0xc191;
op3val:0xb401; valaddr_reg:x3; val_offset:29997*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 29997*FLEN/8, x4, x1, x2)

inst_10000:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1be and fs2 == 1 and fe2 == 0x10 and fm2 == 0x191 and fs3 == 1 and fe3 == 0x0d and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75be; op2val:0xc191;
op3val:0xb7fe; valaddr_reg:x3; val_offset:30000*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30000*FLEN/8, x4, x1, x2)

inst_10001:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1be and fs2 == 1 and fe2 == 0x10 and fm2 == 0x191 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75be; op2val:0xc191;
op3val:0xfbfe; valaddr_reg:x3; val_offset:30003*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30003*FLEN/8, x4, x1, x2)

inst_10002:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1be and fs2 == 1 and fe2 == 0x10 and fm2 == 0x191 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75be; op2val:0xc191;
op3val:0xf801; valaddr_reg:x3; val_offset:30006*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30006*FLEN/8, x4, x1, x2)

inst_10003:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1be and fs2 == 1 and fe2 == 0x10 and fm2 == 0x191 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1b6 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75be; op2val:0xc191;
op3val:0xf9b6; valaddr_reg:x3; val_offset:30009*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30009*FLEN/8, x4, x1, x2)

inst_10004:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1be and fs2 == 1 and fe2 == 0x10 and fm2 == 0x191 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x36d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75be; op2val:0xc191;
op3val:0xfb6d; valaddr_reg:x3; val_offset:30012*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30012*FLEN/8, x4, x1, x2)

inst_10005:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1be and fs2 == 1 and fe2 == 0x10 and fm2 == 0x191 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x0cc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75be; op2val:0xc191;
op3val:0xf8cc; valaddr_reg:x3; val_offset:30015*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30015*FLEN/8, x4, x1, x2)

inst_10006:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1be and fs2 == 1 and fe2 == 0x10 and fm2 == 0x191 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x333 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75be; op2val:0xc191;
op3val:0xfb33; valaddr_reg:x3; val_offset:30018*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30018*FLEN/8, x4, x1, x2)

inst_10007:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1be and fs2 == 1 and fe2 == 0x10 and fm2 == 0x191 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1dd and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75be; op2val:0xc191;
op3val:0xf9dd; valaddr_reg:x3; val_offset:30021*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30021*FLEN/8, x4, x1, x2)

inst_10008:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1be and fs2 == 1 and fe2 == 0x10 and fm2 == 0x191 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x222 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75be; op2val:0xc191;
op3val:0xfa22; valaddr_reg:x3; val_offset:30024*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30024*FLEN/8, x4, x1, x2)

inst_10009:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1be and fs2 == 1 and fe2 == 0x10 and fm2 == 0x191 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x124 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75be; op2val:0xc191;
op3val:0xf924; valaddr_reg:x3; val_offset:30027*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30027*FLEN/8, x4, x1, x2)

inst_10010:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1be and fs2 == 1 and fe2 == 0x10 and fm2 == 0x191 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x2db and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75be; op2val:0xc191;
op3val:0xfadb; valaddr_reg:x3; val_offset:30030*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30030*FLEN/8, x4, x1, x2)

inst_10011:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1be and fs2 == 1 and fe2 == 0x10 and fm2 == 0x191 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x199 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75be; op2val:0xc191;
op3val:0xf999; valaddr_reg:x3; val_offset:30033*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30033*FLEN/8, x4, x1, x2)

inst_10012:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1be and fs2 == 1 and fe2 == 0x10 and fm2 == 0x191 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x266 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75be; op2val:0xc191;
op3val:0xfa66; valaddr_reg:x3; val_offset:30036*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30036*FLEN/8, x4, x1, x2)

inst_10013:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x37f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x044 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x777f; op2val:0xc044;
op3val:0xbbff; valaddr_reg:x3; val_offset:30039*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30039*FLEN/8, x4, x1, x2)

inst_10014:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x37f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x044 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x777f; op2val:0xc044;
op3val:0xb800; valaddr_reg:x3; val_offset:30042*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30042*FLEN/8, x4, x1, x2)

inst_10015:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x37f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x044 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x1ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x777f; op2val:0xc044;
op3val:0xb9ff; valaddr_reg:x3; val_offset:30045*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30045*FLEN/8, x4, x1, x2)

inst_10016:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x37f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x044 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x777f; op2val:0xc044;
op3val:0xba00; valaddr_reg:x3; val_offset:30048*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30048*FLEN/8, x4, x1, x2)

inst_10017:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x37f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x044 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x0ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x777f; op2val:0xc044;
op3val:0xb8ff; valaddr_reg:x3; val_offset:30051*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30051*FLEN/8, x4, x1, x2)

inst_10018:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x37f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x044 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x300 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x777f; op2val:0xc044;
op3val:0xbb00; valaddr_reg:x3; val_offset:30054*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30054*FLEN/8, x4, x1, x2)

inst_10019:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x37f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x044 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x07f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x777f; op2val:0xc044;
op3val:0xb87f; valaddr_reg:x3; val_offset:30057*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30057*FLEN/8, x4, x1, x2)

inst_10020:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x37f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x044 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x380 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x777f; op2val:0xc044;
op3val:0xbb80; valaddr_reg:x3; val_offset:30060*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30060*FLEN/8, x4, x1, x2)

inst_10021:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x37f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x044 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x03f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x777f; op2val:0xc044;
op3val:0xb83f; valaddr_reg:x3; val_offset:30063*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30063*FLEN/8, x4, x1, x2)

inst_10022:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x37f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x044 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x3c0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x777f; op2val:0xc044;
op3val:0xbbc0; valaddr_reg:x3; val_offset:30066*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30066*FLEN/8, x4, x1, x2)

inst_10023:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x37f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x044 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x01f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x777f; op2val:0xc044;
op3val:0xb81f; valaddr_reg:x3; val_offset:30069*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30069*FLEN/8, x4, x1, x2)

inst_10024:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x37f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x044 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x3e0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x777f; op2val:0xc044;
op3val:0xbbe0; valaddr_reg:x3; val_offset:30072*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30072*FLEN/8, x4, x1, x2)

inst_10025:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x37f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x044 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x00f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x777f; op2val:0xc044;
op3val:0xb80f; valaddr_reg:x3; val_offset:30075*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30075*FLEN/8, x4, x1, x2)

inst_10026:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x37f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x044 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x3f0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x777f; op2val:0xc044;
op3val:0xbbf0; valaddr_reg:x3; val_offset:30078*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30078*FLEN/8, x4, x1, x2)

inst_10027:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x37f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x044 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x007 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x777f; op2val:0xc044;
op3val:0xb807; valaddr_reg:x3; val_offset:30081*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30081*FLEN/8, x4, x1, x2)

inst_10028:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x37f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x044 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x3f8 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x777f; op2val:0xc044;
op3val:0xbbf8; valaddr_reg:x3; val_offset:30084*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30084*FLEN/8, x4, x1, x2)

inst_10029:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x37f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x044 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x003 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x777f; op2val:0xc044;
op3val:0xb803; valaddr_reg:x3; val_offset:30087*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30087*FLEN/8, x4, x1, x2)

inst_10030:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x37f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x044 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x3fc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x777f; op2val:0xc044;
op3val:0xbbfc; valaddr_reg:x3; val_offset:30090*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30090*FLEN/8, x4, x1, x2)

inst_10031:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x37f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x044 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x777f; op2val:0xc044;
op3val:0xb801; valaddr_reg:x3; val_offset:30093*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30093*FLEN/8, x4, x1, x2)

inst_10032:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x37f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x044 and fs3 == 1 and fe3 == 0x0e and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x777f; op2val:0xc044;
op3val:0xbbfe; valaddr_reg:x3; val_offset:30096*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30096*FLEN/8, x4, x1, x2)

inst_10033:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x37f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x044 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x777f; op2val:0xc044;
op3val:0xfbfe; valaddr_reg:x3; val_offset:30099*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30099*FLEN/8, x4, x1, x2)

inst_10034:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x37f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x044 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x777f; op2val:0xc044;
op3val:0xf801; valaddr_reg:x3; val_offset:30102*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30102*FLEN/8, x4, x1, x2)

inst_10035:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x37f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x044 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1b6 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x777f; op2val:0xc044;
op3val:0xf9b6; valaddr_reg:x3; val_offset:30105*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30105*FLEN/8, x4, x1, x2)

inst_10036:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x37f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x044 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x36d and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x777f; op2val:0xc044;
op3val:0xfb6d; valaddr_reg:x3; val_offset:30108*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30108*FLEN/8, x4, x1, x2)

inst_10037:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x37f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x044 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x0cc and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x777f; op2val:0xc044;
op3val:0xf8cc; valaddr_reg:x3; val_offset:30111*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30111*FLEN/8, x4, x1, x2)

inst_10038:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x37f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x044 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x333 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x777f; op2val:0xc044;
op3val:0xfb33; valaddr_reg:x3; val_offset:30114*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30114*FLEN/8, x4, x1, x2)

inst_10039:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x37f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x044 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x1dd and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x777f; op2val:0xc044;
op3val:0xf9dd; valaddr_reg:x3; val_offset:30117*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30117*FLEN/8, x4, x1, x2)

inst_10040:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x37f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x044 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x222 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x777f; op2val:0xc044;
op3val:0xfa22; valaddr_reg:x3; val_offset:30120*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30120*FLEN/8, x4, x1, x2)

inst_10041:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x37f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x044 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x124 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x777f; op2val:0xc044;
op3val:0xf924; valaddr_reg:x3; val_offset:30123*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30123*FLEN/8, x4, x1, x2)

inst_10042:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x37f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x044 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x2db and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x777f; op2val:0xc044;
op3val:0xfadb; valaddr_reg:x3; val_offset:30126*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30126*FLEN/8, x4, x1, x2)

inst_10043:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x37f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x044 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x199 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x777f; op2val:0xc044;
op3val:0xf999; valaddr_reg:x3; val_offset:30129*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30129*FLEN/8, x4, x1, x2)

inst_10044:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x37f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x044 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x266 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x777f; op2val:0xc044;
op3val:0xfa66; valaddr_reg:x3; val_offset:30132*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30132*FLEN/8, x4, x1, x2)

inst_10045:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x704c; op2val:0x0;
op3val:0x1; valaddr_reg:x3; val_offset:30135*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30135*FLEN/8, x4, x1, x2)

inst_10046:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x1ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x704c; op2val:0x0;
op3val:0x1ff; valaddr_reg:x3; val_offset:30138*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30138*FLEN/8, x4, x1, x2)

inst_10047:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x0ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x704c; op2val:0x0;
op3val:0xff; valaddr_reg:x3; val_offset:30141*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30141*FLEN/8, x4, x1, x2)

inst_10048:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x07f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x704c; op2val:0x0;
op3val:0x7f; valaddr_reg:x3; val_offset:30144*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30144*FLEN/8, x4, x1, x2)

inst_10049:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3c0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x704c; op2val:0x0;
op3val:0x3c0; valaddr_reg:x3; val_offset:30147*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30147*FLEN/8, x4, x1, x2)

inst_10050:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x03f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x704c; op2val:0x0;
op3val:0x3f; valaddr_reg:x3; val_offset:30150*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30150*FLEN/8, x4, x1, x2)

inst_10051:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3e0 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x704c; op2val:0x0;
op3val:0x3e0; valaddr_reg:x3; val_offset:30153*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30153*FLEN/8, x4, x1, x2)

inst_10052:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x01f and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x704c; op2val:0x0;
op3val:0x1f; valaddr_reg:x3; val_offset:30156*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 30156*FLEN/8, x4, x1, x2)


#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(31237,16,FLEN)
NAN_BOXED(48463,16,FLEN)
NAN_BOXED(54208,16,FLEN)
NAN_BOXED(31237,16,FLEN)
NAN_BOXED(48463,16,FLEN)
NAN_BOXED(53279,16,FLEN)
NAN_BOXED(31237,16,FLEN)
NAN_BOXED(48463,16,FLEN)
NAN_BOXED(54240,16,FLEN)
NAN_BOXED(31237,16,FLEN)
NAN_BOXED(48463,16,FLEN)
NAN_BOXED(53263,16,FLEN)
NAN_BOXED(31237,16,FLEN)
NAN_BOXED(48463,16,FLEN)
NAN_BOXED(54256,16,FLEN)
NAN_BOXED(31237,16,FLEN)
NAN_BOXED(48463,16,FLEN)
NAN_BOXED(53255,16,FLEN)
NAN_BOXED(31237,16,FLEN)
NAN_BOXED(48463,16,FLEN)
NAN_BOXED(54264,16,FLEN)
NAN_BOXED(31237,16,FLEN)
NAN_BOXED(48463,16,FLEN)
NAN_BOXED(53251,16,FLEN)
NAN_BOXED(31237,16,FLEN)
NAN_BOXED(48463,16,FLEN)
NAN_BOXED(54268,16,FLEN)
NAN_BOXED(31237,16,FLEN)
NAN_BOXED(48463,16,FLEN)
NAN_BOXED(53249,16,FLEN)
NAN_BOXED(31237,16,FLEN)
NAN_BOXED(48463,16,FLEN)
NAN_BOXED(54270,16,FLEN)
NAN_BOXED(31237,16,FLEN)
NAN_BOXED(48463,16,FLEN)
NAN_BOXED(64510,16,FLEN)
NAN_BOXED(31237,16,FLEN)
NAN_BOXED(48463,16,FLEN)
NAN_BOXED(63489,16,FLEN)
NAN_BOXED(31237,16,FLEN)
NAN_BOXED(48463,16,FLEN)
NAN_BOXED(63926,16,FLEN)
NAN_BOXED(31237,16,FLEN)
NAN_BOXED(48463,16,FLEN)
NAN_BOXED(64365,16,FLEN)
NAN_BOXED(31237,16,FLEN)
NAN_BOXED(48463,16,FLEN)
NAN_BOXED(63692,16,FLEN)
NAN_BOXED(31237,16,FLEN)
NAN_BOXED(48463,16,FLEN)
NAN_BOXED(64307,16,FLEN)
NAN_BOXED(31237,16,FLEN)
NAN_BOXED(48463,16,FLEN)
NAN_BOXED(63965,16,FLEN)
NAN_BOXED(31237,16,FLEN)
NAN_BOXED(48463,16,FLEN)
NAN_BOXED(64034,16,FLEN)
NAN_BOXED(31237,16,FLEN)
NAN_BOXED(48463,16,FLEN)
NAN_BOXED(63780,16,FLEN)
NAN_BOXED(31237,16,FLEN)
NAN_BOXED(48463,16,FLEN)
NAN_BOXED(64219,16,FLEN)
NAN_BOXED(31237,16,FLEN)
NAN_BOXED(48463,16,FLEN)
NAN_BOXED(63897,16,FLEN)
NAN_BOXED(31237,16,FLEN)
NAN_BOXED(48463,16,FLEN)
NAN_BOXED(64102,16,FLEN)
NAN_BOXED(28106,16,FLEN)
NAN_BOXED(51590,16,FLEN)
NAN_BOXED(55295,16,FLEN)
NAN_BOXED(28106,16,FLEN)
NAN_BOXED(51590,16,FLEN)
NAN_BOXED(54272,16,FLEN)
NAN_BOXED(28106,16,FLEN)
NAN_BOXED(51590,16,FLEN)
NAN_BOXED(54783,16,FLEN)
NAN_BOXED(28106,16,FLEN)
NAN_BOXED(51590,16,FLEN)
NAN_BOXED(54784,16,FLEN)
NAN_BOXED(28106,16,FLEN)
NAN_BOXED(51590,16,FLEN)
NAN_BOXED(54527,16,FLEN)
NAN_BOXED(28106,16,FLEN)
NAN_BOXED(51590,16,FLEN)
NAN_BOXED(55040,16,FLEN)
NAN_BOXED(28106,16,FLEN)
NAN_BOXED(51590,16,FLEN)
NAN_BOXED(54399,16,FLEN)
NAN_BOXED(28106,16,FLEN)
NAN_BOXED(51590,16,FLEN)
NAN_BOXED(55168,16,FLEN)
NAN_BOXED(28106,16,FLEN)
NAN_BOXED(51590,16,FLEN)
NAN_BOXED(54335,16,FLEN)
NAN_BOXED(28106,16,FLEN)
NAN_BOXED(51590,16,FLEN)
NAN_BOXED(55232,16,FLEN)
NAN_BOXED(28106,16,FLEN)
NAN_BOXED(51590,16,FLEN)
NAN_BOXED(54303,16,FLEN)
NAN_BOXED(28106,16,FLEN)
NAN_BOXED(51590,16,FLEN)
NAN_BOXED(55264,16,FLEN)
NAN_BOXED(28106,16,FLEN)
NAN_BOXED(51590,16,FLEN)
NAN_BOXED(54287,16,FLEN)
NAN_BOXED(28106,16,FLEN)
NAN_BOXED(51590,16,FLEN)
NAN_BOXED(55280,16,FLEN)
NAN_BOXED(28106,16,FLEN)
NAN_BOXED(51590,16,FLEN)
NAN_BOXED(54279,16,FLEN)
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NAN_BOXED(24853,16,FLEN)
NAN_BOXED(54858,16,FLEN)
NAN_BOXED(45024,16,FLEN)
NAN_BOXED(24853,16,FLEN)
NAN_BOXED(54858,16,FLEN)
NAN_BOXED(44047,16,FLEN)
NAN_BOXED(24853,16,FLEN)
NAN_BOXED(54858,16,FLEN)
NAN_BOXED(45040,16,FLEN)
NAN_BOXED(24853,16,FLEN)
NAN_BOXED(54858,16,FLEN)
NAN_BOXED(44039,16,FLEN)
NAN_BOXED(24853,16,FLEN)
NAN_BOXED(54858,16,FLEN)
NAN_BOXED(45048,16,FLEN)
NAN_BOXED(24853,16,FLEN)
NAN_BOXED(54858,16,FLEN)
NAN_BOXED(44035,16,FLEN)
NAN_BOXED(24853,16,FLEN)
NAN_BOXED(54858,16,FLEN)
NAN_BOXED(45052,16,FLEN)
NAN_BOXED(24853,16,FLEN)
NAN_BOXED(54858,16,FLEN)
NAN_BOXED(44033,16,FLEN)
NAN_BOXED(24853,16,FLEN)
NAN_BOXED(54858,16,FLEN)
NAN_BOXED(45054,16,FLEN)
NAN_BOXED(24853,16,FLEN)
NAN_BOXED(54858,16,FLEN)
NAN_BOXED(64510,16,FLEN)
NAN_BOXED(24853,16,FLEN)
NAN_BOXED(54858,16,FLEN)
NAN_BOXED(63489,16,FLEN)
NAN_BOXED(24853,16,FLEN)
NAN_BOXED(54858,16,FLEN)
NAN_BOXED(63926,16,FLEN)
NAN_BOXED(24853,16,FLEN)
NAN_BOXED(54858,16,FLEN)
NAN_BOXED(64365,16,FLEN)
NAN_BOXED(24853,16,FLEN)
NAN_BOXED(54858,16,FLEN)
NAN_BOXED(63692,16,FLEN)
NAN_BOXED(24853,16,FLEN)
NAN_BOXED(54858,16,FLEN)
NAN_BOXED(64307,16,FLEN)
NAN_BOXED(24853,16,FLEN)
NAN_BOXED(54858,16,FLEN)
NAN_BOXED(63965,16,FLEN)
NAN_BOXED(24853,16,FLEN)
NAN_BOXED(54858,16,FLEN)
NAN_BOXED(64034,16,FLEN)
NAN_BOXED(24853,16,FLEN)
NAN_BOXED(54858,16,FLEN)
NAN_BOXED(63780,16,FLEN)
NAN_BOXED(24853,16,FLEN)
NAN_BOXED(54858,16,FLEN)
NAN_BOXED(64219,16,FLEN)
NAN_BOXED(24853,16,FLEN)
NAN_BOXED(54858,16,FLEN)
NAN_BOXED(63897,16,FLEN)
NAN_BOXED(24853,16,FLEN)
NAN_BOXED(54858,16,FLEN)
NAN_BOXED(64102,16,FLEN)
NAN_BOXED(31232,16,FLEN)
NAN_BOXED(48468,16,FLEN)
NAN_BOXED(46079,16,FLEN)
NAN_BOXED(31232,16,FLEN)
NAN_BOXED(48468,16,FLEN)
NAN_BOXED(45056,16,FLEN)
NAN_BOXED(31232,16,FLEN)
NAN_BOXED(48468,16,FLEN)
NAN_BOXED(45567,16,FLEN)
NAN_BOXED(31232,16,FLEN)
NAN_BOXED(48468,16,FLEN)
NAN_BOXED(45568,16,FLEN)
NAN_BOXED(31232,16,FLEN)
NAN_BOXED(48468,16,FLEN)
NAN_BOXED(45311,16,FLEN)
NAN_BOXED(31232,16,FLEN)
NAN_BOXED(48468,16,FLEN)
NAN_BOXED(45824,16,FLEN)
NAN_BOXED(31232,16,FLEN)
NAN_BOXED(48468,16,FLEN)
NAN_BOXED(45183,16,FLEN)
NAN_BOXED(31232,16,FLEN)
NAN_BOXED(48468,16,FLEN)
NAN_BOXED(45952,16,FLEN)
NAN_BOXED(31232,16,FLEN)
NAN_BOXED(48468,16,FLEN)
NAN_BOXED(45119,16,FLEN)
NAN_BOXED(31232,16,FLEN)
NAN_BOXED(48468,16,FLEN)
NAN_BOXED(46016,16,FLEN)
NAN_BOXED(31232,16,FLEN)
NAN_BOXED(48468,16,FLEN)
NAN_BOXED(45087,16,FLEN)
NAN_BOXED(31232,16,FLEN)
NAN_BOXED(48468,16,FLEN)
NAN_BOXED(46048,16,FLEN)
NAN_BOXED(31232,16,FLEN)
NAN_BOXED(48468,16,FLEN)
NAN_BOXED(45071,16,FLEN)
NAN_BOXED(31232,16,FLEN)
NAN_BOXED(48468,16,FLEN)
NAN_BOXED(46064,16,FLEN)
NAN_BOXED(31232,16,FLEN)
NAN_BOXED(48468,16,FLEN)
NAN_BOXED(45063,16,FLEN)
NAN_BOXED(31232,16,FLEN)
NAN_BOXED(48468,16,FLEN)
NAN_BOXED(46072,16,FLEN)
NAN_BOXED(31232,16,FLEN)
NAN_BOXED(48468,16,FLEN)
NAN_BOXED(45059,16,FLEN)
NAN_BOXED(31232,16,FLEN)
NAN_BOXED(48468,16,FLEN)
NAN_BOXED(46076,16,FLEN)
NAN_BOXED(31232,16,FLEN)
NAN_BOXED(48468,16,FLEN)
NAN_BOXED(45057,16,FLEN)
NAN_BOXED(31232,16,FLEN)
NAN_BOXED(48468,16,FLEN)
NAN_BOXED(46078,16,FLEN)
NAN_BOXED(31232,16,FLEN)
NAN_BOXED(48468,16,FLEN)
NAN_BOXED(64510,16,FLEN)
NAN_BOXED(31232,16,FLEN)
NAN_BOXED(48468,16,FLEN)
NAN_BOXED(63489,16,FLEN)
NAN_BOXED(31232,16,FLEN)
NAN_BOXED(48468,16,FLEN)
NAN_BOXED(63926,16,FLEN)
NAN_BOXED(31232,16,FLEN)
NAN_BOXED(48468,16,FLEN)
NAN_BOXED(64365,16,FLEN)
NAN_BOXED(31232,16,FLEN)
NAN_BOXED(48468,16,FLEN)
NAN_BOXED(63692,16,FLEN)
NAN_BOXED(31232,16,FLEN)
NAN_BOXED(48468,16,FLEN)
NAN_BOXED(64307,16,FLEN)
NAN_BOXED(31232,16,FLEN)
NAN_BOXED(48468,16,FLEN)
NAN_BOXED(63965,16,FLEN)
NAN_BOXED(31232,16,FLEN)
NAN_BOXED(48468,16,FLEN)
NAN_BOXED(64034,16,FLEN)
NAN_BOXED(31232,16,FLEN)
NAN_BOXED(48468,16,FLEN)
NAN_BOXED(63780,16,FLEN)
NAN_BOXED(31232,16,FLEN)
NAN_BOXED(48468,16,FLEN)
NAN_BOXED(64219,16,FLEN)
NAN_BOXED(31232,16,FLEN)
NAN_BOXED(48468,16,FLEN)
NAN_BOXED(63897,16,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;



signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_2:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_3:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_4:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_5:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_6:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_7:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_8:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_9:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_10:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_11:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_12:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_13:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_14:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_15:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_16:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_17:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_18:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_19:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_20:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_21:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_22:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_23:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_24:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_25:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_26:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_27:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_28:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_29:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_30:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_31:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_32:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_33:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_34:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_35:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_36:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_37:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_38:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_39:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_40:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_41:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_42:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_43:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_44:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_45:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_46:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_47:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_48:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_49:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_50:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_51:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_52:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_53:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_54:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_55:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_56:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_57:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_58:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_59:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_60:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_61:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_62:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_63:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_64:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_65:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_66:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_67:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_68:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_69:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_70:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_71:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_72:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_73:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_74:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_75:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_76:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_77:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_78:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_79:
    .fill 138*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;

mtrap_sigptr:
    .fill 64*XLEN/32,4,0xdeadbeef

tsig_end_canary:
CANARY;
#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif


sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
