
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.7.1
// timestamp : Fri Jun 17 14:18:08 2022 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /scratch/pawan/work/normalised/RV32F/fnmsub.s.cgf \
 \
//                  -- xlen 32  \
//                  --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fnmsub.s instruction of the RISC-V RV32F_Zicsr,RV32FD_Zicsr,RV64F_Zicsr,RV64FD_Zicsr extension for the fnmsub_b15 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr,RV32IFD_Zicsr,RV64IF_Zicsr,RV64IFD_Zicsr,RV32EF_Zicsr,RV32EFD_Zicsr,RV64EF_Zicsr,RV64EFD_Zicsr")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*);def TEST_CASE_1=True;",fnmsub_b15)
RVTEST_CASE(1,"//check ISA:=regex(.*E.*F.*);def TEST_CASE_1=True;",fnmsub_b15)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_14592:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1337c1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9337c1; op2val:0x80000000;
op3val:0x8d8003ff; valaddr_reg:x3; val_offset:43776*0 + 3*-1*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43776*0 + 3*0*FLEN/8, x4, x1, x2)

inst_14593:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1337c1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9337c1; op2val:0x80000000;
op3val:0x8d8007ff; valaddr_reg:x3; val_offset:43779*0 + 3*0*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43779*0 + 3*1*FLEN/8, x4, x1, x2)

inst_14594:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1337c1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9337c1; op2val:0x80000000;
op3val:0x8d800fff; valaddr_reg:x3; val_offset:43782*0 + 3*1*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43782*0 + 3*2*FLEN/8, x4, x1, x2)

inst_14595:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1337c1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9337c1; op2val:0x80000000;
op3val:0x8d801fff; valaddr_reg:x3; val_offset:43785*0 + 3*2*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43785*0 + 3*3*FLEN/8, x4, x1, x2)

inst_14596:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1337c1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9337c1; op2val:0x80000000;
op3val:0x8d803fff; valaddr_reg:x3; val_offset:43788*0 + 3*3*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43788*0 + 3*4*FLEN/8, x4, x1, x2)

inst_14597:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1337c1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9337c1; op2val:0x80000000;
op3val:0x8d807fff; valaddr_reg:x3; val_offset:43791*0 + 3*4*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43791*0 + 3*5*FLEN/8, x4, x1, x2)

inst_14598:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1337c1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9337c1; op2val:0x80000000;
op3val:0x8d80ffff; valaddr_reg:x3; val_offset:43794*0 + 3*5*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43794*0 + 3*6*FLEN/8, x4, x1, x2)

inst_14599:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1337c1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9337c1; op2val:0x80000000;
op3val:0x8d81ffff; valaddr_reg:x3; val_offset:43797*0 + 3*6*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43797*0 + 3*7*FLEN/8, x4, x1, x2)

inst_14600:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1337c1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9337c1; op2val:0x80000000;
op3val:0x8d83ffff; valaddr_reg:x3; val_offset:43800*0 + 3*7*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43800*0 + 3*8*FLEN/8, x4, x1, x2)

inst_14601:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1337c1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9337c1; op2val:0x80000000;
op3val:0x8d87ffff; valaddr_reg:x3; val_offset:43803*0 + 3*8*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43803*0 + 3*9*FLEN/8, x4, x1, x2)

inst_14602:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1337c1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9337c1; op2val:0x80000000;
op3val:0x8d8fffff; valaddr_reg:x3; val_offset:43806*0 + 3*9*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43806*0 + 3*10*FLEN/8, x4, x1, x2)

inst_14603:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1337c1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9337c1; op2val:0x80000000;
op3val:0x8d9fffff; valaddr_reg:x3; val_offset:43809*0 + 3*10*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43809*0 + 3*11*FLEN/8, x4, x1, x2)

inst_14604:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1337c1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9337c1; op2val:0x80000000;
op3val:0x8dbfffff; valaddr_reg:x3; val_offset:43812*0 + 3*11*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43812*0 + 3*12*FLEN/8, x4, x1, x2)

inst_14605:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1337c1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9337c1; op2val:0x80000000;
op3val:0x8dc00000; valaddr_reg:x3; val_offset:43815*0 + 3*12*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43815*0 + 3*13*FLEN/8, x4, x1, x2)

inst_14606:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1337c1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9337c1; op2val:0x80000000;
op3val:0x8de00000; valaddr_reg:x3; val_offset:43818*0 + 3*13*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43818*0 + 3*14*FLEN/8, x4, x1, x2)

inst_14607:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1337c1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9337c1; op2val:0x80000000;
op3val:0x8df00000; valaddr_reg:x3; val_offset:43821*0 + 3*14*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43821*0 + 3*15*FLEN/8, x4, x1, x2)

inst_14608:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1337c1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9337c1; op2val:0x80000000;
op3val:0x8df80000; valaddr_reg:x3; val_offset:43824*0 + 3*15*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43824*0 + 3*16*FLEN/8, x4, x1, x2)

inst_14609:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1337c1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9337c1; op2val:0x80000000;
op3val:0x8dfc0000; valaddr_reg:x3; val_offset:43827*0 + 3*16*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43827*0 + 3*17*FLEN/8, x4, x1, x2)

inst_14610:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1337c1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9337c1; op2val:0x80000000;
op3val:0x8dfe0000; valaddr_reg:x3; val_offset:43830*0 + 3*17*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43830*0 + 3*18*FLEN/8, x4, x1, x2)

inst_14611:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1337c1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9337c1; op2val:0x80000000;
op3val:0x8dff0000; valaddr_reg:x3; val_offset:43833*0 + 3*18*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43833*0 + 3*19*FLEN/8, x4, x1, x2)

inst_14612:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1337c1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9337c1; op2val:0x80000000;
op3val:0x8dff8000; valaddr_reg:x3; val_offset:43836*0 + 3*19*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43836*0 + 3*20*FLEN/8, x4, x1, x2)

inst_14613:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1337c1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9337c1; op2val:0x80000000;
op3val:0x8dffc000; valaddr_reg:x3; val_offset:43839*0 + 3*20*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43839*0 + 3*21*FLEN/8, x4, x1, x2)

inst_14614:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1337c1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9337c1; op2val:0x80000000;
op3val:0x8dffe000; valaddr_reg:x3; val_offset:43842*0 + 3*21*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43842*0 + 3*22*FLEN/8, x4, x1, x2)

inst_14615:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1337c1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9337c1; op2val:0x80000000;
op3val:0x8dfff000; valaddr_reg:x3; val_offset:43845*0 + 3*22*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43845*0 + 3*23*FLEN/8, x4, x1, x2)

inst_14616:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1337c1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9337c1; op2val:0x80000000;
op3val:0x8dfff800; valaddr_reg:x3; val_offset:43848*0 + 3*23*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43848*0 + 3*24*FLEN/8, x4, x1, x2)

inst_14617:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1337c1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9337c1; op2val:0x80000000;
op3val:0x8dfffc00; valaddr_reg:x3; val_offset:43851*0 + 3*24*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43851*0 + 3*25*FLEN/8, x4, x1, x2)

inst_14618:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1337c1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9337c1; op2val:0x80000000;
op3val:0x8dfffe00; valaddr_reg:x3; val_offset:43854*0 + 3*25*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43854*0 + 3*26*FLEN/8, x4, x1, x2)

inst_14619:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1337c1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9337c1; op2val:0x80000000;
op3val:0x8dffff00; valaddr_reg:x3; val_offset:43857*0 + 3*26*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43857*0 + 3*27*FLEN/8, x4, x1, x2)

inst_14620:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1337c1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9337c1; op2val:0x80000000;
op3val:0x8dffff80; valaddr_reg:x3; val_offset:43860*0 + 3*27*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43860*0 + 3*28*FLEN/8, x4, x1, x2)

inst_14621:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1337c1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9337c1; op2val:0x80000000;
op3val:0x8dffffc0; valaddr_reg:x3; val_offset:43863*0 + 3*28*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43863*0 + 3*29*FLEN/8, x4, x1, x2)

inst_14622:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1337c1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9337c1; op2val:0x80000000;
op3val:0x8dffffe0; valaddr_reg:x3; val_offset:43866*0 + 3*29*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43866*0 + 3*30*FLEN/8, x4, x1, x2)

inst_14623:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1337c1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9337c1; op2val:0x80000000;
op3val:0x8dfffff0; valaddr_reg:x3; val_offset:43869*0 + 3*30*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43869*0 + 3*31*FLEN/8, x4, x1, x2)

inst_14624:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1337c1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9337c1; op2val:0x80000000;
op3val:0x8dfffff8; valaddr_reg:x3; val_offset:43872*0 + 3*31*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43872*0 + 3*32*FLEN/8, x4, x1, x2)

inst_14625:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1337c1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9337c1; op2val:0x80000000;
op3val:0x8dfffffc; valaddr_reg:x3; val_offset:43875*0 + 3*32*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43875*0 + 3*33*FLEN/8, x4, x1, x2)

inst_14626:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1337c1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9337c1; op2val:0x80000000;
op3val:0x8dfffffe; valaddr_reg:x3; val_offset:43878*0 + 3*33*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43878*0 + 3*34*FLEN/8, x4, x1, x2)

inst_14627:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1337c1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1b and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9337c1; op2val:0x80000000;
op3val:0x8dffffff; valaddr_reg:x3; val_offset:43881*0 + 3*34*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43881*0 + 3*35*FLEN/8, x4, x1, x2)

inst_14628:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x3; val_offset:43884*0 + 3*35*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43884*0 + 3*36*FLEN/8, x4, x1, x2)

inst_14629:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x80000003; valaddr_reg:x3; val_offset:43887*0 + 3*36*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43887*0 + 3*37*FLEN/8, x4, x1, x2)

inst_14630:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x80000007; valaddr_reg:x3; val_offset:43890*0 + 3*37*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43890*0 + 3*38*FLEN/8, x4, x1, x2)

inst_14631:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x80199999; valaddr_reg:x3; val_offset:43893*0 + 3*38*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43893*0 + 3*39*FLEN/8, x4, x1, x2)

inst_14632:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x80249249; valaddr_reg:x3; val_offset:43896*0 + 3*39*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43896*0 + 3*40*FLEN/8, x4, x1, x2)

inst_14633:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x80333333; valaddr_reg:x3; val_offset:43899*0 + 3*40*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43899*0 + 3*41*FLEN/8, x4, x1, x2)

inst_14634:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x8036db6d; valaddr_reg:x3; val_offset:43902*0 + 3*41*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43902*0 + 3*42*FLEN/8, x4, x1, x2)

inst_14635:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x803bbbbb; valaddr_reg:x3; val_offset:43905*0 + 3*42*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43905*0 + 3*43*FLEN/8, x4, x1, x2)

inst_14636:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x80444444; valaddr_reg:x3; val_offset:43908*0 + 3*43*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43908*0 + 3*44*FLEN/8, x4, x1, x2)

inst_14637:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x804ccccc; valaddr_reg:x3; val_offset:43911*0 + 3*44*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43911*0 + 3*45*FLEN/8, x4, x1, x2)

inst_14638:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x805b6db6; valaddr_reg:x3; val_offset:43914*0 + 3*45*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43914*0 + 3*46*FLEN/8, x4, x1, x2)

inst_14639:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x80666666; valaddr_reg:x3; val_offset:43917*0 + 3*46*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43917*0 + 3*47*FLEN/8, x4, x1, x2)

inst_14640:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x806db6db; valaddr_reg:x3; val_offset:43920*0 + 3*47*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43920*0 + 3*48*FLEN/8, x4, x1, x2)

inst_14641:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x807ffff8; valaddr_reg:x3; val_offset:43923*0 + 3*48*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43923*0 + 3*49*FLEN/8, x4, x1, x2)

inst_14642:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x807ffffc; valaddr_reg:x3; val_offset:43926*0 + 3*49*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43926*0 + 3*50*FLEN/8, x4, x1, x2)

inst_14643:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x3; val_offset:43929*0 + 3*50*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43929*0 + 3*51*FLEN/8, x4, x1, x2)

inst_14644:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x83800000; valaddr_reg:x3; val_offset:43932*0 + 3*51*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43932*0 + 3*52*FLEN/8, x4, x1, x2)

inst_14645:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x83800001; valaddr_reg:x3; val_offset:43935*0 + 3*52*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43935*0 + 3*53*FLEN/8, x4, x1, x2)

inst_14646:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x83800003; valaddr_reg:x3; val_offset:43938*0 + 3*53*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43938*0 + 3*54*FLEN/8, x4, x1, x2)

inst_14647:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x83800007; valaddr_reg:x3; val_offset:43941*0 + 3*54*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43941*0 + 3*55*FLEN/8, x4, x1, x2)

inst_14648:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x8380000f; valaddr_reg:x3; val_offset:43944*0 + 3*55*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43944*0 + 3*56*FLEN/8, x4, x1, x2)

inst_14649:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x8380001f; valaddr_reg:x3; val_offset:43947*0 + 3*56*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43947*0 + 3*57*FLEN/8, x4, x1, x2)

inst_14650:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x8380003f; valaddr_reg:x3; val_offset:43950*0 + 3*57*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43950*0 + 3*58*FLEN/8, x4, x1, x2)

inst_14651:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x8380007f; valaddr_reg:x3; val_offset:43953*0 + 3*58*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43953*0 + 3*59*FLEN/8, x4, x1, x2)

inst_14652:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x838000ff; valaddr_reg:x3; val_offset:43956*0 + 3*59*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43956*0 + 3*60*FLEN/8, x4, x1, x2)

inst_14653:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x838001ff; valaddr_reg:x3; val_offset:43959*0 + 3*60*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43959*0 + 3*61*FLEN/8, x4, x1, x2)

inst_14654:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x838003ff; valaddr_reg:x3; val_offset:43962*0 + 3*61*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43962*0 + 3*62*FLEN/8, x4, x1, x2)

inst_14655:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x838007ff; valaddr_reg:x3; val_offset:43965*0 + 3*62*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43965*0 + 3*63*FLEN/8, x4, x1, x2)

inst_14656:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x83800fff; valaddr_reg:x3; val_offset:43968*0 + 3*63*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43968*0 + 3*64*FLEN/8, x4, x1, x2)

inst_14657:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x83801fff; valaddr_reg:x3; val_offset:43971*0 + 3*64*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43971*0 + 3*65*FLEN/8, x4, x1, x2)

inst_14658:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x83803fff; valaddr_reg:x3; val_offset:43974*0 + 3*65*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43974*0 + 3*66*FLEN/8, x4, x1, x2)

inst_14659:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x83807fff; valaddr_reg:x3; val_offset:43977*0 + 3*66*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43977*0 + 3*67*FLEN/8, x4, x1, x2)

inst_14660:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x8380ffff; valaddr_reg:x3; val_offset:43980*0 + 3*67*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43980*0 + 3*68*FLEN/8, x4, x1, x2)

inst_14661:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x8381ffff; valaddr_reg:x3; val_offset:43983*0 + 3*68*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43983*0 + 3*69*FLEN/8, x4, x1, x2)

inst_14662:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x8383ffff; valaddr_reg:x3; val_offset:43986*0 + 3*69*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43986*0 + 3*70*FLEN/8, x4, x1, x2)

inst_14663:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x8387ffff; valaddr_reg:x3; val_offset:43989*0 + 3*70*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43989*0 + 3*71*FLEN/8, x4, x1, x2)

inst_14664:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x838fffff; valaddr_reg:x3; val_offset:43992*0 + 3*71*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43992*0 + 3*72*FLEN/8, x4, x1, x2)

inst_14665:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x839fffff; valaddr_reg:x3; val_offset:43995*0 + 3*72*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43995*0 + 3*73*FLEN/8, x4, x1, x2)

inst_14666:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x83bfffff; valaddr_reg:x3; val_offset:43998*0 + 3*73*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 43998*0 + 3*74*FLEN/8, x4, x1, x2)

inst_14667:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x83c00000; valaddr_reg:x3; val_offset:44001*0 + 3*74*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44001*0 + 3*75*FLEN/8, x4, x1, x2)

inst_14668:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x83e00000; valaddr_reg:x3; val_offset:44004*0 + 3*75*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44004*0 + 3*76*FLEN/8, x4, x1, x2)

inst_14669:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x83f00000; valaddr_reg:x3; val_offset:44007*0 + 3*76*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44007*0 + 3*77*FLEN/8, x4, x1, x2)

inst_14670:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x83f80000; valaddr_reg:x3; val_offset:44010*0 + 3*77*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44010*0 + 3*78*FLEN/8, x4, x1, x2)

inst_14671:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x83fc0000; valaddr_reg:x3; val_offset:44013*0 + 3*78*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44013*0 + 3*79*FLEN/8, x4, x1, x2)

inst_14672:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x83fe0000; valaddr_reg:x3; val_offset:44016*0 + 3*79*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44016*0 + 3*80*FLEN/8, x4, x1, x2)

inst_14673:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x83ff0000; valaddr_reg:x3; val_offset:44019*0 + 3*80*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44019*0 + 3*81*FLEN/8, x4, x1, x2)

inst_14674:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x83ff8000; valaddr_reg:x3; val_offset:44022*0 + 3*81*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44022*0 + 3*82*FLEN/8, x4, x1, x2)

inst_14675:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x83ffc000; valaddr_reg:x3; val_offset:44025*0 + 3*82*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44025*0 + 3*83*FLEN/8, x4, x1, x2)

inst_14676:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x83ffe000; valaddr_reg:x3; val_offset:44028*0 + 3*83*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44028*0 + 3*84*FLEN/8, x4, x1, x2)

inst_14677:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x83fff000; valaddr_reg:x3; val_offset:44031*0 + 3*84*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44031*0 + 3*85*FLEN/8, x4, x1, x2)

inst_14678:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x83fff800; valaddr_reg:x3; val_offset:44034*0 + 3*85*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44034*0 + 3*86*FLEN/8, x4, x1, x2)

inst_14679:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x83fffc00; valaddr_reg:x3; val_offset:44037*0 + 3*86*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44037*0 + 3*87*FLEN/8, x4, x1, x2)

inst_14680:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x83fffe00; valaddr_reg:x3; val_offset:44040*0 + 3*87*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44040*0 + 3*88*FLEN/8, x4, x1, x2)

inst_14681:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x83ffff00; valaddr_reg:x3; val_offset:44043*0 + 3*88*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44043*0 + 3*89*FLEN/8, x4, x1, x2)

inst_14682:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x83ffff80; valaddr_reg:x3; val_offset:44046*0 + 3*89*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44046*0 + 3*90*FLEN/8, x4, x1, x2)

inst_14683:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x83ffffc0; valaddr_reg:x3; val_offset:44049*0 + 3*90*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44049*0 + 3*91*FLEN/8, x4, x1, x2)

inst_14684:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x83ffffe0; valaddr_reg:x3; val_offset:44052*0 + 3*91*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44052*0 + 3*92*FLEN/8, x4, x1, x2)

inst_14685:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x83fffff0; valaddr_reg:x3; val_offset:44055*0 + 3*92*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44055*0 + 3*93*FLEN/8, x4, x1, x2)

inst_14686:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x83fffff8; valaddr_reg:x3; val_offset:44058*0 + 3*93*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44058*0 + 3*94*FLEN/8, x4, x1, x2)

inst_14687:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x83fffffc; valaddr_reg:x3; val_offset:44061*0 + 3*94*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44061*0 + 3*95*FLEN/8, x4, x1, x2)

inst_14688:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x83fffffe; valaddr_reg:x3; val_offset:44064*0 + 3*95*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44064*0 + 3*96*FLEN/8, x4, x1, x2)

inst_14689:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x142c31 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x07 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e942c31; op2val:0x80000000;
op3val:0x83ffffff; valaddr_reg:x3; val_offset:44067*0 + 3*96*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44067*0 + 3*97*FLEN/8, x4, x1, x2)

inst_14690:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0x1; valaddr_reg:x3; val_offset:44070*0 + 3*97*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44070*0 + 3*98*FLEN/8, x4, x1, x2)

inst_14691:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0x3; valaddr_reg:x3; val_offset:44073*0 + 3*98*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44073*0 + 3*99*FLEN/8, x4, x1, x2)

inst_14692:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0x7; valaddr_reg:x3; val_offset:44076*0 + 3*99*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44076*0 + 3*100*FLEN/8, x4, x1, x2)

inst_14693:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0x199999; valaddr_reg:x3; val_offset:44079*0 + 3*100*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44079*0 + 3*101*FLEN/8, x4, x1, x2)

inst_14694:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0x249249; valaddr_reg:x3; val_offset:44082*0 + 3*101*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44082*0 + 3*102*FLEN/8, x4, x1, x2)

inst_14695:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0x333333; valaddr_reg:x3; val_offset:44085*0 + 3*102*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44085*0 + 3*103*FLEN/8, x4, x1, x2)

inst_14696:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0x36db6d; valaddr_reg:x3; val_offset:44088*0 + 3*103*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44088*0 + 3*104*FLEN/8, x4, x1, x2)

inst_14697:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0x3bbbbb; valaddr_reg:x3; val_offset:44091*0 + 3*104*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44091*0 + 3*105*FLEN/8, x4, x1, x2)

inst_14698:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0x444444; valaddr_reg:x3; val_offset:44094*0 + 3*105*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44094*0 + 3*106*FLEN/8, x4, x1, x2)

inst_14699:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0x4ccccc; valaddr_reg:x3; val_offset:44097*0 + 3*106*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44097*0 + 3*107*FLEN/8, x4, x1, x2)

inst_14700:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0x5b6db6; valaddr_reg:x3; val_offset:44100*0 + 3*107*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44100*0 + 3*108*FLEN/8, x4, x1, x2)

inst_14701:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0x666666; valaddr_reg:x3; val_offset:44103*0 + 3*108*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44103*0 + 3*109*FLEN/8, x4, x1, x2)

inst_14702:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0x6db6db; valaddr_reg:x3; val_offset:44106*0 + 3*109*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44106*0 + 3*110*FLEN/8, x4, x1, x2)

inst_14703:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0x7ffff8; valaddr_reg:x3; val_offset:44109*0 + 3*110*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44109*0 + 3*111*FLEN/8, x4, x1, x2)

inst_14704:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0x7ffffc; valaddr_reg:x3; val_offset:44112*0 + 3*111*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44112*0 + 3*112*FLEN/8, x4, x1, x2)

inst_14705:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0x7ffffe; valaddr_reg:x3; val_offset:44115*0 + 3*112*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44115*0 + 3*113*FLEN/8, x4, x1, x2)

inst_14706:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0xd800000; valaddr_reg:x3; val_offset:44118*0 + 3*113*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44118*0 + 3*114*FLEN/8, x4, x1, x2)

inst_14707:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0xd800001; valaddr_reg:x3; val_offset:44121*0 + 3*114*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44121*0 + 3*115*FLEN/8, x4, x1, x2)

inst_14708:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0xd800003; valaddr_reg:x3; val_offset:44124*0 + 3*115*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44124*0 + 3*116*FLEN/8, x4, x1, x2)

inst_14709:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0xd800007; valaddr_reg:x3; val_offset:44127*0 + 3*116*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44127*0 + 3*117*FLEN/8, x4, x1, x2)

inst_14710:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0xd80000f; valaddr_reg:x3; val_offset:44130*0 + 3*117*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44130*0 + 3*118*FLEN/8, x4, x1, x2)

inst_14711:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0xd80001f; valaddr_reg:x3; val_offset:44133*0 + 3*118*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44133*0 + 3*119*FLEN/8, x4, x1, x2)

inst_14712:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0xd80003f; valaddr_reg:x3; val_offset:44136*0 + 3*119*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44136*0 + 3*120*FLEN/8, x4, x1, x2)

inst_14713:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0xd80007f; valaddr_reg:x3; val_offset:44139*0 + 3*120*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44139*0 + 3*121*FLEN/8, x4, x1, x2)

inst_14714:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0xd8000ff; valaddr_reg:x3; val_offset:44142*0 + 3*121*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44142*0 + 3*122*FLEN/8, x4, x1, x2)

inst_14715:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0xd8001ff; valaddr_reg:x3; val_offset:44145*0 + 3*122*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44145*0 + 3*123*FLEN/8, x4, x1, x2)

inst_14716:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0xd8003ff; valaddr_reg:x3; val_offset:44148*0 + 3*123*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44148*0 + 3*124*FLEN/8, x4, x1, x2)

inst_14717:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0xd8007ff; valaddr_reg:x3; val_offset:44151*0 + 3*124*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44151*0 + 3*125*FLEN/8, x4, x1, x2)

inst_14718:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0xd800fff; valaddr_reg:x3; val_offset:44154*0 + 3*125*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44154*0 + 3*126*FLEN/8, x4, x1, x2)

inst_14719:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0xd801fff; valaddr_reg:x3; val_offset:44157*0 + 3*126*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44157*0 + 3*127*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_2)

inst_14720:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0xd803fff; valaddr_reg:x3; val_offset:44160*0 + 3*127*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44160*0 + 3*128*FLEN/8, x4, x1, x2)

inst_14721:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0xd807fff; valaddr_reg:x3; val_offset:44163*0 + 3*128*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44163*0 + 3*129*FLEN/8, x4, x1, x2)

inst_14722:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0xd80ffff; valaddr_reg:x3; val_offset:44166*0 + 3*129*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44166*0 + 3*130*FLEN/8, x4, x1, x2)

inst_14723:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0xd81ffff; valaddr_reg:x3; val_offset:44169*0 + 3*130*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44169*0 + 3*131*FLEN/8, x4, x1, x2)

inst_14724:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0xd83ffff; valaddr_reg:x3; val_offset:44172*0 + 3*131*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44172*0 + 3*132*FLEN/8, x4, x1, x2)

inst_14725:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0xd87ffff; valaddr_reg:x3; val_offset:44175*0 + 3*132*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44175*0 + 3*133*FLEN/8, x4, x1, x2)

inst_14726:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0xd8fffff; valaddr_reg:x3; val_offset:44178*0 + 3*133*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44178*0 + 3*134*FLEN/8, x4, x1, x2)

inst_14727:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0xd9fffff; valaddr_reg:x3; val_offset:44181*0 + 3*134*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44181*0 + 3*135*FLEN/8, x4, x1, x2)

inst_14728:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0xdbfffff; valaddr_reg:x3; val_offset:44184*0 + 3*135*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44184*0 + 3*136*FLEN/8, x4, x1, x2)

inst_14729:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0xdc00000; valaddr_reg:x3; val_offset:44187*0 + 3*136*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44187*0 + 3*137*FLEN/8, x4, x1, x2)

inst_14730:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0xde00000; valaddr_reg:x3; val_offset:44190*0 + 3*137*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44190*0 + 3*138*FLEN/8, x4, x1, x2)

inst_14731:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0xdf00000; valaddr_reg:x3; val_offset:44193*0 + 3*138*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44193*0 + 3*139*FLEN/8, x4, x1, x2)

inst_14732:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0xdf80000; valaddr_reg:x3; val_offset:44196*0 + 3*139*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44196*0 + 3*140*FLEN/8, x4, x1, x2)

inst_14733:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0xdfc0000; valaddr_reg:x3; val_offset:44199*0 + 3*140*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44199*0 + 3*141*FLEN/8, x4, x1, x2)

inst_14734:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0xdfe0000; valaddr_reg:x3; val_offset:44202*0 + 3*141*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44202*0 + 3*142*FLEN/8, x4, x1, x2)

inst_14735:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0xdff0000; valaddr_reg:x3; val_offset:44205*0 + 3*142*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44205*0 + 3*143*FLEN/8, x4, x1, x2)

inst_14736:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0xdff8000; valaddr_reg:x3; val_offset:44208*0 + 3*143*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44208*0 + 3*144*FLEN/8, x4, x1, x2)

inst_14737:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0xdffc000; valaddr_reg:x3; val_offset:44211*0 + 3*144*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44211*0 + 3*145*FLEN/8, x4, x1, x2)

inst_14738:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0xdffe000; valaddr_reg:x3; val_offset:44214*0 + 3*145*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44214*0 + 3*146*FLEN/8, x4, x1, x2)

inst_14739:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0xdfff000; valaddr_reg:x3; val_offset:44217*0 + 3*146*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44217*0 + 3*147*FLEN/8, x4, x1, x2)

inst_14740:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0xdfff800; valaddr_reg:x3; val_offset:44220*0 + 3*147*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44220*0 + 3*148*FLEN/8, x4, x1, x2)

inst_14741:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0xdfffc00; valaddr_reg:x3; val_offset:44223*0 + 3*148*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44223*0 + 3*149*FLEN/8, x4, x1, x2)

inst_14742:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0xdfffe00; valaddr_reg:x3; val_offset:44226*0 + 3*149*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44226*0 + 3*150*FLEN/8, x4, x1, x2)

inst_14743:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0xdffff00; valaddr_reg:x3; val_offset:44229*0 + 3*150*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44229*0 + 3*151*FLEN/8, x4, x1, x2)

inst_14744:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0xdffff80; valaddr_reg:x3; val_offset:44232*0 + 3*151*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44232*0 + 3*152*FLEN/8, x4, x1, x2)

inst_14745:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0xdffffc0; valaddr_reg:x3; val_offset:44235*0 + 3*152*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44235*0 + 3*153*FLEN/8, x4, x1, x2)

inst_14746:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0xdffffe0; valaddr_reg:x3; val_offset:44238*0 + 3*153*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44238*0 + 3*154*FLEN/8, x4, x1, x2)

inst_14747:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0xdfffff0; valaddr_reg:x3; val_offset:44241*0 + 3*154*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44241*0 + 3*155*FLEN/8, x4, x1, x2)

inst_14748:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0xdfffff8; valaddr_reg:x3; val_offset:44244*0 + 3*155*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44244*0 + 3*156*FLEN/8, x4, x1, x2)

inst_14749:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0xdfffffc; valaddr_reg:x3; val_offset:44247*0 + 3*156*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44247*0 + 3*157*FLEN/8, x4, x1, x2)

inst_14750:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0xdfffffe; valaddr_reg:x3; val_offset:44250*0 + 3*157*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44250*0 + 3*158*FLEN/8, x4, x1, x2)

inst_14751:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x14d779 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e94d779; op2val:0x0;
op3val:0xdffffff; valaddr_reg:x3; val_offset:44253*0 + 3*158*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44253*0 + 3*159*FLEN/8, x4, x1, x2)

inst_14752:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0x1; valaddr_reg:x3; val_offset:44256*0 + 3*159*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44256*0 + 3*160*FLEN/8, x4, x1, x2)

inst_14753:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0x3; valaddr_reg:x3; val_offset:44259*0 + 3*160*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44259*0 + 3*161*FLEN/8, x4, x1, x2)

inst_14754:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0x7; valaddr_reg:x3; val_offset:44262*0 + 3*161*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44262*0 + 3*162*FLEN/8, x4, x1, x2)

inst_14755:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0x199999; valaddr_reg:x3; val_offset:44265*0 + 3*162*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44265*0 + 3*163*FLEN/8, x4, x1, x2)

inst_14756:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0x249249; valaddr_reg:x3; val_offset:44268*0 + 3*163*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44268*0 + 3*164*FLEN/8, x4, x1, x2)

inst_14757:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0x333333; valaddr_reg:x3; val_offset:44271*0 + 3*164*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44271*0 + 3*165*FLEN/8, x4, x1, x2)

inst_14758:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0x36db6d; valaddr_reg:x3; val_offset:44274*0 + 3*165*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44274*0 + 3*166*FLEN/8, x4, x1, x2)

inst_14759:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0x3bbbbb; valaddr_reg:x3; val_offset:44277*0 + 3*166*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44277*0 + 3*167*FLEN/8, x4, x1, x2)

inst_14760:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0x444444; valaddr_reg:x3; val_offset:44280*0 + 3*167*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44280*0 + 3*168*FLEN/8, x4, x1, x2)

inst_14761:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0x4ccccc; valaddr_reg:x3; val_offset:44283*0 + 3*168*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44283*0 + 3*169*FLEN/8, x4, x1, x2)

inst_14762:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0x5b6db6; valaddr_reg:x3; val_offset:44286*0 + 3*169*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44286*0 + 3*170*FLEN/8, x4, x1, x2)

inst_14763:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0x666666; valaddr_reg:x3; val_offset:44289*0 + 3*170*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44289*0 + 3*171*FLEN/8, x4, x1, x2)

inst_14764:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0x6db6db; valaddr_reg:x3; val_offset:44292*0 + 3*171*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44292*0 + 3*172*FLEN/8, x4, x1, x2)

inst_14765:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0x7ffff8; valaddr_reg:x3; val_offset:44295*0 + 3*172*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44295*0 + 3*173*FLEN/8, x4, x1, x2)

inst_14766:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0x7ffffc; valaddr_reg:x3; val_offset:44298*0 + 3*173*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44298*0 + 3*174*FLEN/8, x4, x1, x2)

inst_14767:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0x7ffffe; valaddr_reg:x3; val_offset:44301*0 + 3*174*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44301*0 + 3*175*FLEN/8, x4, x1, x2)

inst_14768:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0xe800000; valaddr_reg:x3; val_offset:44304*0 + 3*175*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44304*0 + 3*176*FLEN/8, x4, x1, x2)

inst_14769:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0xe800001; valaddr_reg:x3; val_offset:44307*0 + 3*176*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44307*0 + 3*177*FLEN/8, x4, x1, x2)

inst_14770:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0xe800003; valaddr_reg:x3; val_offset:44310*0 + 3*177*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44310*0 + 3*178*FLEN/8, x4, x1, x2)

inst_14771:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0xe800007; valaddr_reg:x3; val_offset:44313*0 + 3*178*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44313*0 + 3*179*FLEN/8, x4, x1, x2)

inst_14772:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0xe80000f; valaddr_reg:x3; val_offset:44316*0 + 3*179*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44316*0 + 3*180*FLEN/8, x4, x1, x2)

inst_14773:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0xe80001f; valaddr_reg:x3; val_offset:44319*0 + 3*180*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44319*0 + 3*181*FLEN/8, x4, x1, x2)

inst_14774:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0xe80003f; valaddr_reg:x3; val_offset:44322*0 + 3*181*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44322*0 + 3*182*FLEN/8, x4, x1, x2)

inst_14775:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0xe80007f; valaddr_reg:x3; val_offset:44325*0 + 3*182*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44325*0 + 3*183*FLEN/8, x4, x1, x2)

inst_14776:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0xe8000ff; valaddr_reg:x3; val_offset:44328*0 + 3*183*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44328*0 + 3*184*FLEN/8, x4, x1, x2)

inst_14777:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0xe8001ff; valaddr_reg:x3; val_offset:44331*0 + 3*184*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44331*0 + 3*185*FLEN/8, x4, x1, x2)

inst_14778:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0xe8003ff; valaddr_reg:x3; val_offset:44334*0 + 3*185*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44334*0 + 3*186*FLEN/8, x4, x1, x2)

inst_14779:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0xe8007ff; valaddr_reg:x3; val_offset:44337*0 + 3*186*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44337*0 + 3*187*FLEN/8, x4, x1, x2)

inst_14780:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0xe800fff; valaddr_reg:x3; val_offset:44340*0 + 3*187*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44340*0 + 3*188*FLEN/8, x4, x1, x2)

inst_14781:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0xe801fff; valaddr_reg:x3; val_offset:44343*0 + 3*188*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44343*0 + 3*189*FLEN/8, x4, x1, x2)

inst_14782:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0xe803fff; valaddr_reg:x3; val_offset:44346*0 + 3*189*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44346*0 + 3*190*FLEN/8, x4, x1, x2)

inst_14783:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0xe807fff; valaddr_reg:x3; val_offset:44349*0 + 3*190*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44349*0 + 3*191*FLEN/8, x4, x1, x2)

inst_14784:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0xe80ffff; valaddr_reg:x3; val_offset:44352*0 + 3*191*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44352*0 + 3*192*FLEN/8, x4, x1, x2)

inst_14785:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0xe81ffff; valaddr_reg:x3; val_offset:44355*0 + 3*192*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44355*0 + 3*193*FLEN/8, x4, x1, x2)

inst_14786:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0xe83ffff; valaddr_reg:x3; val_offset:44358*0 + 3*193*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44358*0 + 3*194*FLEN/8, x4, x1, x2)

inst_14787:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0xe87ffff; valaddr_reg:x3; val_offset:44361*0 + 3*194*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44361*0 + 3*195*FLEN/8, x4, x1, x2)

inst_14788:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0xe8fffff; valaddr_reg:x3; val_offset:44364*0 + 3*195*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44364*0 + 3*196*FLEN/8, x4, x1, x2)

inst_14789:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0xe9fffff; valaddr_reg:x3; val_offset:44367*0 + 3*196*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44367*0 + 3*197*FLEN/8, x4, x1, x2)

inst_14790:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0xebfffff; valaddr_reg:x3; val_offset:44370*0 + 3*197*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44370*0 + 3*198*FLEN/8, x4, x1, x2)

inst_14791:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0xec00000; valaddr_reg:x3; val_offset:44373*0 + 3*198*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44373*0 + 3*199*FLEN/8, x4, x1, x2)

inst_14792:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0xee00000; valaddr_reg:x3; val_offset:44376*0 + 3*199*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44376*0 + 3*200*FLEN/8, x4, x1, x2)

inst_14793:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0xef00000; valaddr_reg:x3; val_offset:44379*0 + 3*200*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44379*0 + 3*201*FLEN/8, x4, x1, x2)

inst_14794:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0xef80000; valaddr_reg:x3; val_offset:44382*0 + 3*201*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44382*0 + 3*202*FLEN/8, x4, x1, x2)

inst_14795:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0xefc0000; valaddr_reg:x3; val_offset:44385*0 + 3*202*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44385*0 + 3*203*FLEN/8, x4, x1, x2)

inst_14796:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0xefe0000; valaddr_reg:x3; val_offset:44388*0 + 3*203*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44388*0 + 3*204*FLEN/8, x4, x1, x2)

inst_14797:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0xeff0000; valaddr_reg:x3; val_offset:44391*0 + 3*204*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44391*0 + 3*205*FLEN/8, x4, x1, x2)

inst_14798:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0xeff8000; valaddr_reg:x3; val_offset:44394*0 + 3*205*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44394*0 + 3*206*FLEN/8, x4, x1, x2)

inst_14799:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0xeffc000; valaddr_reg:x3; val_offset:44397*0 + 3*206*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44397*0 + 3*207*FLEN/8, x4, x1, x2)

inst_14800:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0xeffe000; valaddr_reg:x3; val_offset:44400*0 + 3*207*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44400*0 + 3*208*FLEN/8, x4, x1, x2)

inst_14801:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0xefff000; valaddr_reg:x3; val_offset:44403*0 + 3*208*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44403*0 + 3*209*FLEN/8, x4, x1, x2)

inst_14802:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0xefff800; valaddr_reg:x3; val_offset:44406*0 + 3*209*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44406*0 + 3*210*FLEN/8, x4, x1, x2)

inst_14803:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0xefffc00; valaddr_reg:x3; val_offset:44409*0 + 3*210*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44409*0 + 3*211*FLEN/8, x4, x1, x2)

inst_14804:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0xefffe00; valaddr_reg:x3; val_offset:44412*0 + 3*211*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44412*0 + 3*212*FLEN/8, x4, x1, x2)

inst_14805:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0xeffff00; valaddr_reg:x3; val_offset:44415*0 + 3*212*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44415*0 + 3*213*FLEN/8, x4, x1, x2)

inst_14806:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0xeffff80; valaddr_reg:x3; val_offset:44418*0 + 3*213*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44418*0 + 3*214*FLEN/8, x4, x1, x2)

inst_14807:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0xeffffc0; valaddr_reg:x3; val_offset:44421*0 + 3*214*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44421*0 + 3*215*FLEN/8, x4, x1, x2)

inst_14808:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0xeffffe0; valaddr_reg:x3; val_offset:44424*0 + 3*215*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44424*0 + 3*216*FLEN/8, x4, x1, x2)

inst_14809:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0xefffff0; valaddr_reg:x3; val_offset:44427*0 + 3*216*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44427*0 + 3*217*FLEN/8, x4, x1, x2)

inst_14810:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0xefffff8; valaddr_reg:x3; val_offset:44430*0 + 3*217*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44430*0 + 3*218*FLEN/8, x4, x1, x2)

inst_14811:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0xefffffc; valaddr_reg:x3; val_offset:44433*0 + 3*218*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44433*0 + 3*219*FLEN/8, x4, x1, x2)

inst_14812:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0xefffffe; valaddr_reg:x3; val_offset:44436*0 + 3*219*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44436*0 + 3*220*FLEN/8, x4, x1, x2)

inst_14813:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x154029 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e954029; op2val:0x0;
op3val:0xeffffff; valaddr_reg:x3; val_offset:44439*0 + 3*220*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44439*0 + 3*221*FLEN/8, x4, x1, x2)

inst_14814:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x1; valaddr_reg:x3; val_offset:44442*0 + 3*221*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44442*0 + 3*222*FLEN/8, x4, x1, x2)

inst_14815:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x3; valaddr_reg:x3; val_offset:44445*0 + 3*222*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44445*0 + 3*223*FLEN/8, x4, x1, x2)

inst_14816:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x7; valaddr_reg:x3; val_offset:44448*0 + 3*223*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44448*0 + 3*224*FLEN/8, x4, x1, x2)

inst_14817:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x199999; valaddr_reg:x3; val_offset:44451*0 + 3*224*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44451*0 + 3*225*FLEN/8, x4, x1, x2)

inst_14818:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x249249; valaddr_reg:x3; val_offset:44454*0 + 3*225*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44454*0 + 3*226*FLEN/8, x4, x1, x2)

inst_14819:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x333333; valaddr_reg:x3; val_offset:44457*0 + 3*226*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44457*0 + 3*227*FLEN/8, x4, x1, x2)

inst_14820:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x36db6d; valaddr_reg:x3; val_offset:44460*0 + 3*227*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44460*0 + 3*228*FLEN/8, x4, x1, x2)

inst_14821:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x3bbbbb; valaddr_reg:x3; val_offset:44463*0 + 3*228*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44463*0 + 3*229*FLEN/8, x4, x1, x2)

inst_14822:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x444444; valaddr_reg:x3; val_offset:44466*0 + 3*229*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44466*0 + 3*230*FLEN/8, x4, x1, x2)

inst_14823:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x4ccccc; valaddr_reg:x3; val_offset:44469*0 + 3*230*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44469*0 + 3*231*FLEN/8, x4, x1, x2)

inst_14824:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x5b6db6; valaddr_reg:x3; val_offset:44472*0 + 3*231*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44472*0 + 3*232*FLEN/8, x4, x1, x2)

inst_14825:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x666666; valaddr_reg:x3; val_offset:44475*0 + 3*232*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44475*0 + 3*233*FLEN/8, x4, x1, x2)

inst_14826:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x6db6db; valaddr_reg:x3; val_offset:44478*0 + 3*233*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44478*0 + 3*234*FLEN/8, x4, x1, x2)

inst_14827:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x7ffff8; valaddr_reg:x3; val_offset:44481*0 + 3*234*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44481*0 + 3*235*FLEN/8, x4, x1, x2)

inst_14828:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x7ffffc; valaddr_reg:x3; val_offset:44484*0 + 3*235*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44484*0 + 3*236*FLEN/8, x4, x1, x2)

inst_14829:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x7ffffe; valaddr_reg:x3; val_offset:44487*0 + 3*236*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44487*0 + 3*237*FLEN/8, x4, x1, x2)

inst_14830:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x8000000; valaddr_reg:x3; val_offset:44490*0 + 3*237*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44490*0 + 3*238*FLEN/8, x4, x1, x2)

inst_14831:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x8000001; valaddr_reg:x3; val_offset:44493*0 + 3*238*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44493*0 + 3*239*FLEN/8, x4, x1, x2)

inst_14832:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x8000003; valaddr_reg:x3; val_offset:44496*0 + 3*239*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44496*0 + 3*240*FLEN/8, x4, x1, x2)

inst_14833:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x8000007; valaddr_reg:x3; val_offset:44499*0 + 3*240*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44499*0 + 3*241*FLEN/8, x4, x1, x2)

inst_14834:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x800000f; valaddr_reg:x3; val_offset:44502*0 + 3*241*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44502*0 + 3*242*FLEN/8, x4, x1, x2)

inst_14835:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x800001f; valaddr_reg:x3; val_offset:44505*0 + 3*242*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44505*0 + 3*243*FLEN/8, x4, x1, x2)

inst_14836:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x800003f; valaddr_reg:x3; val_offset:44508*0 + 3*243*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44508*0 + 3*244*FLEN/8, x4, x1, x2)

inst_14837:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x800007f; valaddr_reg:x3; val_offset:44511*0 + 3*244*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44511*0 + 3*245*FLEN/8, x4, x1, x2)

inst_14838:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x80000ff; valaddr_reg:x3; val_offset:44514*0 + 3*245*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44514*0 + 3*246*FLEN/8, x4, x1, x2)

inst_14839:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x80001ff; valaddr_reg:x3; val_offset:44517*0 + 3*246*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44517*0 + 3*247*FLEN/8, x4, x1, x2)

inst_14840:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x80003ff; valaddr_reg:x3; val_offset:44520*0 + 3*247*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44520*0 + 3*248*FLEN/8, x4, x1, x2)

inst_14841:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x80007ff; valaddr_reg:x3; val_offset:44523*0 + 3*248*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44523*0 + 3*249*FLEN/8, x4, x1, x2)

inst_14842:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x8000fff; valaddr_reg:x3; val_offset:44526*0 + 3*249*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44526*0 + 3*250*FLEN/8, x4, x1, x2)

inst_14843:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x8001fff; valaddr_reg:x3; val_offset:44529*0 + 3*250*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44529*0 + 3*251*FLEN/8, x4, x1, x2)

inst_14844:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x8003fff; valaddr_reg:x3; val_offset:44532*0 + 3*251*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44532*0 + 3*252*FLEN/8, x4, x1, x2)

inst_14845:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x8007fff; valaddr_reg:x3; val_offset:44535*0 + 3*252*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44535*0 + 3*253*FLEN/8, x4, x1, x2)

inst_14846:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x800ffff; valaddr_reg:x3; val_offset:44538*0 + 3*253*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44538*0 + 3*254*FLEN/8, x4, x1, x2)

inst_14847:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x801ffff; valaddr_reg:x3; val_offset:44541*0 + 3*254*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44541*0 + 3*255*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_3)

inst_14848:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x803ffff; valaddr_reg:x3; val_offset:44544*0 + 3*256*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44544*0 + 3*256*FLEN/8, x4, x1, x2)

inst_14849:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x807ffff; valaddr_reg:x3; val_offset:44547*0 + 3*257*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44547*0 + 3*257*FLEN/8, x4, x1, x2)

inst_14850:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x80fffff; valaddr_reg:x3; val_offset:44550*0 + 3*258*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44550*0 + 3*258*FLEN/8, x4, x1, x2)

inst_14851:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x81fffff; valaddr_reg:x3; val_offset:44553*0 + 3*259*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44553*0 + 3*259*FLEN/8, x4, x1, x2)

inst_14852:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x83fffff; valaddr_reg:x3; val_offset:44556*0 + 3*260*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44556*0 + 3*260*FLEN/8, x4, x1, x2)

inst_14853:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x8400000; valaddr_reg:x3; val_offset:44559*0 + 3*261*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44559*0 + 3*261*FLEN/8, x4, x1, x2)

inst_14854:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x8600000; valaddr_reg:x3; val_offset:44562*0 + 3*262*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44562*0 + 3*262*FLEN/8, x4, x1, x2)

inst_14855:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x8700000; valaddr_reg:x3; val_offset:44565*0 + 3*263*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44565*0 + 3*263*FLEN/8, x4, x1, x2)

inst_14856:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x8780000; valaddr_reg:x3; val_offset:44568*0 + 3*264*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44568*0 + 3*264*FLEN/8, x4, x1, x2)

inst_14857:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x87c0000; valaddr_reg:x3; val_offset:44571*0 + 3*265*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44571*0 + 3*265*FLEN/8, x4, x1, x2)

inst_14858:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x87e0000; valaddr_reg:x3; val_offset:44574*0 + 3*266*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44574*0 + 3*266*FLEN/8, x4, x1, x2)

inst_14859:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x87f0000; valaddr_reg:x3; val_offset:44577*0 + 3*267*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44577*0 + 3*267*FLEN/8, x4, x1, x2)

inst_14860:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x87f8000; valaddr_reg:x3; val_offset:44580*0 + 3*268*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44580*0 + 3*268*FLEN/8, x4, x1, x2)

inst_14861:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x87fc000; valaddr_reg:x3; val_offset:44583*0 + 3*269*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44583*0 + 3*269*FLEN/8, x4, x1, x2)

inst_14862:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x87fe000; valaddr_reg:x3; val_offset:44586*0 + 3*270*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44586*0 + 3*270*FLEN/8, x4, x1, x2)

inst_14863:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x87ff000; valaddr_reg:x3; val_offset:44589*0 + 3*271*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44589*0 + 3*271*FLEN/8, x4, x1, x2)

inst_14864:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x87ff800; valaddr_reg:x3; val_offset:44592*0 + 3*272*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44592*0 + 3*272*FLEN/8, x4, x1, x2)

inst_14865:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x87ffc00; valaddr_reg:x3; val_offset:44595*0 + 3*273*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44595*0 + 3*273*FLEN/8, x4, x1, x2)

inst_14866:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x87ffe00; valaddr_reg:x3; val_offset:44598*0 + 3*274*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44598*0 + 3*274*FLEN/8, x4, x1, x2)

inst_14867:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x87fff00; valaddr_reg:x3; val_offset:44601*0 + 3*275*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44601*0 + 3*275*FLEN/8, x4, x1, x2)

inst_14868:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x87fff80; valaddr_reg:x3; val_offset:44604*0 + 3*276*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44604*0 + 3*276*FLEN/8, x4, x1, x2)

inst_14869:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x87fffc0; valaddr_reg:x3; val_offset:44607*0 + 3*277*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44607*0 + 3*277*FLEN/8, x4, x1, x2)

inst_14870:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x87fffe0; valaddr_reg:x3; val_offset:44610*0 + 3*278*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44610*0 + 3*278*FLEN/8, x4, x1, x2)

inst_14871:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x87ffff0; valaddr_reg:x3; val_offset:44613*0 + 3*279*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44613*0 + 3*279*FLEN/8, x4, x1, x2)

inst_14872:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x87ffff8; valaddr_reg:x3; val_offset:44616*0 + 3*280*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44616*0 + 3*280*FLEN/8, x4, x1, x2)

inst_14873:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x87ffffc; valaddr_reg:x3; val_offset:44619*0 + 3*281*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44619*0 + 3*281*FLEN/8, x4, x1, x2)

inst_14874:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x87ffffe; valaddr_reg:x3; val_offset:44622*0 + 3*282*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44622*0 + 3*282*FLEN/8, x4, x1, x2)

inst_14875:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x15bc56 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e95bc56; op2val:0x0;
op3val:0x87fffff; valaddr_reg:x3; val_offset:44625*0 + 3*283*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44625*0 + 3*283*FLEN/8, x4, x1, x2)

inst_14876:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xca and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x65000000; valaddr_reg:x3; val_offset:44628*0 + 3*284*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44628*0 + 3*284*FLEN/8, x4, x1, x2)

inst_14877:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xca and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x65000001; valaddr_reg:x3; val_offset:44631*0 + 3*285*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44631*0 + 3*285*FLEN/8, x4, x1, x2)

inst_14878:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xca and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x65000003; valaddr_reg:x3; val_offset:44634*0 + 3*286*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44634*0 + 3*286*FLEN/8, x4, x1, x2)

inst_14879:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xca and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x65000007; valaddr_reg:x3; val_offset:44637*0 + 3*287*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44637*0 + 3*287*FLEN/8, x4, x1, x2)

inst_14880:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xca and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x6500000f; valaddr_reg:x3; val_offset:44640*0 + 3*288*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44640*0 + 3*288*FLEN/8, x4, x1, x2)

inst_14881:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xca and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x6500001f; valaddr_reg:x3; val_offset:44643*0 + 3*289*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44643*0 + 3*289*FLEN/8, x4, x1, x2)

inst_14882:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xca and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x6500003f; valaddr_reg:x3; val_offset:44646*0 + 3*290*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44646*0 + 3*290*FLEN/8, x4, x1, x2)

inst_14883:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xca and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x6500007f; valaddr_reg:x3; val_offset:44649*0 + 3*291*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44649*0 + 3*291*FLEN/8, x4, x1, x2)

inst_14884:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xca and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x650000ff; valaddr_reg:x3; val_offset:44652*0 + 3*292*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44652*0 + 3*292*FLEN/8, x4, x1, x2)

inst_14885:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xca and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x650001ff; valaddr_reg:x3; val_offset:44655*0 + 3*293*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44655*0 + 3*293*FLEN/8, x4, x1, x2)

inst_14886:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xca and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x650003ff; valaddr_reg:x3; val_offset:44658*0 + 3*294*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44658*0 + 3*294*FLEN/8, x4, x1, x2)

inst_14887:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xca and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x650007ff; valaddr_reg:x3; val_offset:44661*0 + 3*295*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44661*0 + 3*295*FLEN/8, x4, x1, x2)

inst_14888:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xca and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x65000fff; valaddr_reg:x3; val_offset:44664*0 + 3*296*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44664*0 + 3*296*FLEN/8, x4, x1, x2)

inst_14889:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xca and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x65001fff; valaddr_reg:x3; val_offset:44667*0 + 3*297*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44667*0 + 3*297*FLEN/8, x4, x1, x2)

inst_14890:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xca and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x65003fff; valaddr_reg:x3; val_offset:44670*0 + 3*298*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44670*0 + 3*298*FLEN/8, x4, x1, x2)

inst_14891:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xca and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x65007fff; valaddr_reg:x3; val_offset:44673*0 + 3*299*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44673*0 + 3*299*FLEN/8, x4, x1, x2)

inst_14892:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xca and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x6500ffff; valaddr_reg:x3; val_offset:44676*0 + 3*300*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44676*0 + 3*300*FLEN/8, x4, x1, x2)

inst_14893:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xca and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x6501ffff; valaddr_reg:x3; val_offset:44679*0 + 3*301*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44679*0 + 3*301*FLEN/8, x4, x1, x2)

inst_14894:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xca and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x6503ffff; valaddr_reg:x3; val_offset:44682*0 + 3*302*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44682*0 + 3*302*FLEN/8, x4, x1, x2)

inst_14895:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xca and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x6507ffff; valaddr_reg:x3; val_offset:44685*0 + 3*303*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44685*0 + 3*303*FLEN/8, x4, x1, x2)

inst_14896:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xca and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x650fffff; valaddr_reg:x3; val_offset:44688*0 + 3*304*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44688*0 + 3*304*FLEN/8, x4, x1, x2)

inst_14897:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xca and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x651fffff; valaddr_reg:x3; val_offset:44691*0 + 3*305*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44691*0 + 3*305*FLEN/8, x4, x1, x2)

inst_14898:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xca and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x653fffff; valaddr_reg:x3; val_offset:44694*0 + 3*306*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44694*0 + 3*306*FLEN/8, x4, x1, x2)

inst_14899:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xca and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x65400000; valaddr_reg:x3; val_offset:44697*0 + 3*307*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44697*0 + 3*307*FLEN/8, x4, x1, x2)

inst_14900:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xca and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x65600000; valaddr_reg:x3; val_offset:44700*0 + 3*308*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44700*0 + 3*308*FLEN/8, x4, x1, x2)

inst_14901:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xca and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x65700000; valaddr_reg:x3; val_offset:44703*0 + 3*309*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44703*0 + 3*309*FLEN/8, x4, x1, x2)

inst_14902:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xca and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x65780000; valaddr_reg:x3; val_offset:44706*0 + 3*310*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44706*0 + 3*310*FLEN/8, x4, x1, x2)

inst_14903:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xca and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x657c0000; valaddr_reg:x3; val_offset:44709*0 + 3*311*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44709*0 + 3*311*FLEN/8, x4, x1, x2)

inst_14904:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xca and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x657e0000; valaddr_reg:x3; val_offset:44712*0 + 3*312*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44712*0 + 3*312*FLEN/8, x4, x1, x2)

inst_14905:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xca and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x657f0000; valaddr_reg:x3; val_offset:44715*0 + 3*313*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44715*0 + 3*313*FLEN/8, x4, x1, x2)

inst_14906:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xca and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x657f8000; valaddr_reg:x3; val_offset:44718*0 + 3*314*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44718*0 + 3*314*FLEN/8, x4, x1, x2)

inst_14907:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xca and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x657fc000; valaddr_reg:x3; val_offset:44721*0 + 3*315*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44721*0 + 3*315*FLEN/8, x4, x1, x2)

inst_14908:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xca and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x657fe000; valaddr_reg:x3; val_offset:44724*0 + 3*316*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44724*0 + 3*316*FLEN/8, x4, x1, x2)

inst_14909:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xca and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x657ff000; valaddr_reg:x3; val_offset:44727*0 + 3*317*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44727*0 + 3*317*FLEN/8, x4, x1, x2)

inst_14910:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xca and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x657ff800; valaddr_reg:x3; val_offset:44730*0 + 3*318*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44730*0 + 3*318*FLEN/8, x4, x1, x2)

inst_14911:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xca and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x657ffc00; valaddr_reg:x3; val_offset:44733*0 + 3*319*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44733*0 + 3*319*FLEN/8, x4, x1, x2)

inst_14912:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xca and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x657ffe00; valaddr_reg:x3; val_offset:44736*0 + 3*320*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44736*0 + 3*320*FLEN/8, x4, x1, x2)

inst_14913:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xca and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x657fff00; valaddr_reg:x3; val_offset:44739*0 + 3*321*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44739*0 + 3*321*FLEN/8, x4, x1, x2)

inst_14914:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xca and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x657fff80; valaddr_reg:x3; val_offset:44742*0 + 3*322*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44742*0 + 3*322*FLEN/8, x4, x1, x2)

inst_14915:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xca and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x657fffc0; valaddr_reg:x3; val_offset:44745*0 + 3*323*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44745*0 + 3*323*FLEN/8, x4, x1, x2)

inst_14916:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xca and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x657fffe0; valaddr_reg:x3; val_offset:44748*0 + 3*324*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44748*0 + 3*324*FLEN/8, x4, x1, x2)

inst_14917:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xca and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x657ffff0; valaddr_reg:x3; val_offset:44751*0 + 3*325*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44751*0 + 3*325*FLEN/8, x4, x1, x2)

inst_14918:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xca and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x657ffff8; valaddr_reg:x3; val_offset:44754*0 + 3*326*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44754*0 + 3*326*FLEN/8, x4, x1, x2)

inst_14919:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xca and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x657ffffc; valaddr_reg:x3; val_offset:44757*0 + 3*327*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44757*0 + 3*327*FLEN/8, x4, x1, x2)

inst_14920:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xca and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x657ffffe; valaddr_reg:x3; val_offset:44760*0 + 3*328*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44760*0 + 3*328*FLEN/8, x4, x1, x2)

inst_14921:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xca and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x657fffff; valaddr_reg:x3; val_offset:44763*0 + 3*329*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44763*0 + 3*329*FLEN/8, x4, x1, x2)

inst_14922:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x7f000001; valaddr_reg:x3; val_offset:44766*0 + 3*330*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44766*0 + 3*330*FLEN/8, x4, x1, x2)

inst_14923:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x7f000003; valaddr_reg:x3; val_offset:44769*0 + 3*331*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44769*0 + 3*331*FLEN/8, x4, x1, x2)

inst_14924:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x7f000007; valaddr_reg:x3; val_offset:44772*0 + 3*332*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44772*0 + 3*332*FLEN/8, x4, x1, x2)

inst_14925:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x7f199999; valaddr_reg:x3; val_offset:44775*0 + 3*333*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44775*0 + 3*333*FLEN/8, x4, x1, x2)

inst_14926:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x7f249249; valaddr_reg:x3; val_offset:44778*0 + 3*334*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44778*0 + 3*334*FLEN/8, x4, x1, x2)

inst_14927:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x7f333333; valaddr_reg:x3; val_offset:44781*0 + 3*335*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44781*0 + 3*335*FLEN/8, x4, x1, x2)

inst_14928:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x7f36db6d; valaddr_reg:x3; val_offset:44784*0 + 3*336*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44784*0 + 3*336*FLEN/8, x4, x1, x2)

inst_14929:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x7f3bbbbb; valaddr_reg:x3; val_offset:44787*0 + 3*337*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44787*0 + 3*337*FLEN/8, x4, x1, x2)

inst_14930:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x7f444444; valaddr_reg:x3; val_offset:44790*0 + 3*338*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44790*0 + 3*338*FLEN/8, x4, x1, x2)

inst_14931:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x7f4ccccc; valaddr_reg:x3; val_offset:44793*0 + 3*339*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44793*0 + 3*339*FLEN/8, x4, x1, x2)

inst_14932:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x7f5b6db6; valaddr_reg:x3; val_offset:44796*0 + 3*340*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44796*0 + 3*340*FLEN/8, x4, x1, x2)

inst_14933:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x7f666666; valaddr_reg:x3; val_offset:44799*0 + 3*341*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44799*0 + 3*341*FLEN/8, x4, x1, x2)

inst_14934:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x7f6db6db; valaddr_reg:x3; val_offset:44802*0 + 3*342*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44802*0 + 3*342*FLEN/8, x4, x1, x2)

inst_14935:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x7f7ffff8; valaddr_reg:x3; val_offset:44805*0 + 3*343*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44805*0 + 3*343*FLEN/8, x4, x1, x2)

inst_14936:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x7f7ffffc; valaddr_reg:x3; val_offset:44808*0 + 3*344*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44808*0 + 3*344*FLEN/8, x4, x1, x2)

inst_14937:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x163706 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a2407 and fs3 == 0 and fe3 == 0xfe and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e963706; op2val:0x405a2407;
op3val:0x7f7ffffe; valaddr_reg:x3; val_offset:44811*0 + 3*345*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44811*0 + 3*345*FLEN/8, x4, x1, x2)

inst_14938:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x3; val_offset:44814*0 + 3*346*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44814*0 + 3*346*FLEN/8, x4, x1, x2)

inst_14939:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x80000003; valaddr_reg:x3; val_offset:44817*0 + 3*347*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44817*0 + 3*347*FLEN/8, x4, x1, x2)

inst_14940:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x80000007; valaddr_reg:x3; val_offset:44820*0 + 3*348*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44820*0 + 3*348*FLEN/8, x4, x1, x2)

inst_14941:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x80199999; valaddr_reg:x3; val_offset:44823*0 + 3*349*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44823*0 + 3*349*FLEN/8, x4, x1, x2)

inst_14942:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x80249249; valaddr_reg:x3; val_offset:44826*0 + 3*350*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44826*0 + 3*350*FLEN/8, x4, x1, x2)

inst_14943:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x80333333; valaddr_reg:x3; val_offset:44829*0 + 3*351*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44829*0 + 3*351*FLEN/8, x4, x1, x2)

inst_14944:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x8036db6d; valaddr_reg:x3; val_offset:44832*0 + 3*352*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44832*0 + 3*352*FLEN/8, x4, x1, x2)

inst_14945:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x803bbbbb; valaddr_reg:x3; val_offset:44835*0 + 3*353*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44835*0 + 3*353*FLEN/8, x4, x1, x2)

inst_14946:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x80444444; valaddr_reg:x3; val_offset:44838*0 + 3*354*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44838*0 + 3*354*FLEN/8, x4, x1, x2)

inst_14947:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x804ccccc; valaddr_reg:x3; val_offset:44841*0 + 3*355*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44841*0 + 3*355*FLEN/8, x4, x1, x2)

inst_14948:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x805b6db6; valaddr_reg:x3; val_offset:44844*0 + 3*356*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44844*0 + 3*356*FLEN/8, x4, x1, x2)

inst_14949:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x80666666; valaddr_reg:x3; val_offset:44847*0 + 3*357*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44847*0 + 3*357*FLEN/8, x4, x1, x2)

inst_14950:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x806db6db; valaddr_reg:x3; val_offset:44850*0 + 3*358*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44850*0 + 3*358*FLEN/8, x4, x1, x2)

inst_14951:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x807ffff8; valaddr_reg:x3; val_offset:44853*0 + 3*359*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44853*0 + 3*359*FLEN/8, x4, x1, x2)

inst_14952:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x807ffffc; valaddr_reg:x3; val_offset:44856*0 + 3*360*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44856*0 + 3*360*FLEN/8, x4, x1, x2)

inst_14953:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x3; val_offset:44859*0 + 3*361*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44859*0 + 3*361*FLEN/8, x4, x1, x2)

inst_14954:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x8c000000; valaddr_reg:x3; val_offset:44862*0 + 3*362*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44862*0 + 3*362*FLEN/8, x4, x1, x2)

inst_14955:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x8c000001; valaddr_reg:x3; val_offset:44865*0 + 3*363*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44865*0 + 3*363*FLEN/8, x4, x1, x2)

inst_14956:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x8c000003; valaddr_reg:x3; val_offset:44868*0 + 3*364*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44868*0 + 3*364*FLEN/8, x4, x1, x2)

inst_14957:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x8c000007; valaddr_reg:x3; val_offset:44871*0 + 3*365*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44871*0 + 3*365*FLEN/8, x4, x1, x2)

inst_14958:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x8c00000f; valaddr_reg:x3; val_offset:44874*0 + 3*366*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44874*0 + 3*366*FLEN/8, x4, x1, x2)

inst_14959:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x8c00001f; valaddr_reg:x3; val_offset:44877*0 + 3*367*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44877*0 + 3*367*FLEN/8, x4, x1, x2)

inst_14960:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x8c00003f; valaddr_reg:x3; val_offset:44880*0 + 3*368*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44880*0 + 3*368*FLEN/8, x4, x1, x2)

inst_14961:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x8c00007f; valaddr_reg:x3; val_offset:44883*0 + 3*369*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44883*0 + 3*369*FLEN/8, x4, x1, x2)

inst_14962:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x8c0000ff; valaddr_reg:x3; val_offset:44886*0 + 3*370*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44886*0 + 3*370*FLEN/8, x4, x1, x2)

inst_14963:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x8c0001ff; valaddr_reg:x3; val_offset:44889*0 + 3*371*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44889*0 + 3*371*FLEN/8, x4, x1, x2)

inst_14964:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x8c0003ff; valaddr_reg:x3; val_offset:44892*0 + 3*372*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44892*0 + 3*372*FLEN/8, x4, x1, x2)

inst_14965:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x8c0007ff; valaddr_reg:x3; val_offset:44895*0 + 3*373*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44895*0 + 3*373*FLEN/8, x4, x1, x2)

inst_14966:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x8c000fff; valaddr_reg:x3; val_offset:44898*0 + 3*374*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44898*0 + 3*374*FLEN/8, x4, x1, x2)

inst_14967:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x8c001fff; valaddr_reg:x3; val_offset:44901*0 + 3*375*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44901*0 + 3*375*FLEN/8, x4, x1, x2)

inst_14968:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x8c003fff; valaddr_reg:x3; val_offset:44904*0 + 3*376*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44904*0 + 3*376*FLEN/8, x4, x1, x2)

inst_14969:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x8c007fff; valaddr_reg:x3; val_offset:44907*0 + 3*377*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44907*0 + 3*377*FLEN/8, x4, x1, x2)

inst_14970:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x8c00ffff; valaddr_reg:x3; val_offset:44910*0 + 3*378*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44910*0 + 3*378*FLEN/8, x4, x1, x2)

inst_14971:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x8c01ffff; valaddr_reg:x3; val_offset:44913*0 + 3*379*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44913*0 + 3*379*FLEN/8, x4, x1, x2)

inst_14972:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x8c03ffff; valaddr_reg:x3; val_offset:44916*0 + 3*380*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44916*0 + 3*380*FLEN/8, x4, x1, x2)

inst_14973:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x8c07ffff; valaddr_reg:x3; val_offset:44919*0 + 3*381*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44919*0 + 3*381*FLEN/8, x4, x1, x2)

inst_14974:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x8c0fffff; valaddr_reg:x3; val_offset:44922*0 + 3*382*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44922*0 + 3*382*FLEN/8, x4, x1, x2)

inst_14975:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x8c1fffff; valaddr_reg:x3; val_offset:44925*0 + 3*383*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44925*0 + 3*383*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_4)

inst_14976:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x8c3fffff; valaddr_reg:x3; val_offset:44928*0 + 3*384*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44928*0 + 3*384*FLEN/8, x4, x1, x2)

inst_14977:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x8c400000; valaddr_reg:x3; val_offset:44931*0 + 3*385*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44931*0 + 3*385*FLEN/8, x4, x1, x2)

inst_14978:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x8c600000; valaddr_reg:x3; val_offset:44934*0 + 3*386*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44934*0 + 3*386*FLEN/8, x4, x1, x2)

inst_14979:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x8c700000; valaddr_reg:x3; val_offset:44937*0 + 3*387*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44937*0 + 3*387*FLEN/8, x4, x1, x2)

inst_14980:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x8c780000; valaddr_reg:x3; val_offset:44940*0 + 3*388*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44940*0 + 3*388*FLEN/8, x4, x1, x2)

inst_14981:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x8c7c0000; valaddr_reg:x3; val_offset:44943*0 + 3*389*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44943*0 + 3*389*FLEN/8, x4, x1, x2)

inst_14982:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x8c7e0000; valaddr_reg:x3; val_offset:44946*0 + 3*390*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44946*0 + 3*390*FLEN/8, x4, x1, x2)

inst_14983:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x8c7f0000; valaddr_reg:x3; val_offset:44949*0 + 3*391*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44949*0 + 3*391*FLEN/8, x4, x1, x2)

inst_14984:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x8c7f8000; valaddr_reg:x3; val_offset:44952*0 + 3*392*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44952*0 + 3*392*FLEN/8, x4, x1, x2)

inst_14985:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x8c7fc000; valaddr_reg:x3; val_offset:44955*0 + 3*393*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44955*0 + 3*393*FLEN/8, x4, x1, x2)

inst_14986:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x8c7fe000; valaddr_reg:x3; val_offset:44958*0 + 3*394*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44958*0 + 3*394*FLEN/8, x4, x1, x2)

inst_14987:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x8c7ff000; valaddr_reg:x3; val_offset:44961*0 + 3*395*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44961*0 + 3*395*FLEN/8, x4, x1, x2)

inst_14988:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x8c7ff800; valaddr_reg:x3; val_offset:44964*0 + 3*396*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44964*0 + 3*396*FLEN/8, x4, x1, x2)

inst_14989:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x8c7ffc00; valaddr_reg:x3; val_offset:44967*0 + 3*397*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44967*0 + 3*397*FLEN/8, x4, x1, x2)

inst_14990:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x8c7ffe00; valaddr_reg:x3; val_offset:44970*0 + 3*398*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44970*0 + 3*398*FLEN/8, x4, x1, x2)

inst_14991:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x8c7fff00; valaddr_reg:x3; val_offset:44973*0 + 3*399*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44973*0 + 3*399*FLEN/8, x4, x1, x2)

inst_14992:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x8c7fff80; valaddr_reg:x3; val_offset:44976*0 + 3*400*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44976*0 + 3*400*FLEN/8, x4, x1, x2)

inst_14993:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x8c7fffc0; valaddr_reg:x3; val_offset:44979*0 + 3*401*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44979*0 + 3*401*FLEN/8, x4, x1, x2)

inst_14994:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x8c7fffe0; valaddr_reg:x3; val_offset:44982*0 + 3*402*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44982*0 + 3*402*FLEN/8, x4, x1, x2)

inst_14995:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x8c7ffff0; valaddr_reg:x3; val_offset:44985*0 + 3*403*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44985*0 + 3*403*FLEN/8, x4, x1, x2)

inst_14996:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x8c7ffff8; valaddr_reg:x3; val_offset:44988*0 + 3*404*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44988*0 + 3*404*FLEN/8, x4, x1, x2)

inst_14997:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x8c7ffffc; valaddr_reg:x3; val_offset:44991*0 + 3*405*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44991*0 + 3*405*FLEN/8, x4, x1, x2)

inst_14998:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x8c7ffffe; valaddr_reg:x3; val_offset:44994*0 + 3*406*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44994*0 + 3*406*FLEN/8, x4, x1, x2)

inst_14999:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x17313a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x18 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e97313a; op2val:0x80000000;
op3val:0x8c7fffff; valaddr_reg:x3; val_offset:44997*0 + 3*407*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 44997*0 + 3*407*FLEN/8, x4, x1, x2)

inst_15000:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xf3 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xf9800000; valaddr_reg:x3; val_offset:45000*0 + 3*408*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45000*0 + 3*408*FLEN/8, x4, x1, x2)

inst_15001:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xf3 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xf9800001; valaddr_reg:x3; val_offset:45003*0 + 3*409*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45003*0 + 3*409*FLEN/8, x4, x1, x2)

inst_15002:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xf3 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xf9800003; valaddr_reg:x3; val_offset:45006*0 + 3*410*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45006*0 + 3*410*FLEN/8, x4, x1, x2)

inst_15003:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xf3 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xf9800007; valaddr_reg:x3; val_offset:45009*0 + 3*411*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45009*0 + 3*411*FLEN/8, x4, x1, x2)

inst_15004:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xf3 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xf980000f; valaddr_reg:x3; val_offset:45012*0 + 3*412*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45012*0 + 3*412*FLEN/8, x4, x1, x2)

inst_15005:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xf3 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xf980001f; valaddr_reg:x3; val_offset:45015*0 + 3*413*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45015*0 + 3*413*FLEN/8, x4, x1, x2)

inst_15006:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xf3 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xf980003f; valaddr_reg:x3; val_offset:45018*0 + 3*414*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45018*0 + 3*414*FLEN/8, x4, x1, x2)

inst_15007:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xf3 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xf980007f; valaddr_reg:x3; val_offset:45021*0 + 3*415*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45021*0 + 3*415*FLEN/8, x4, x1, x2)

inst_15008:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xf3 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xf98000ff; valaddr_reg:x3; val_offset:45024*0 + 3*416*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45024*0 + 3*416*FLEN/8, x4, x1, x2)

inst_15009:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xf3 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xf98001ff; valaddr_reg:x3; val_offset:45027*0 + 3*417*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45027*0 + 3*417*FLEN/8, x4, x1, x2)

inst_15010:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xf3 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xf98003ff; valaddr_reg:x3; val_offset:45030*0 + 3*418*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45030*0 + 3*418*FLEN/8, x4, x1, x2)

inst_15011:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xf3 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xf98007ff; valaddr_reg:x3; val_offset:45033*0 + 3*419*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45033*0 + 3*419*FLEN/8, x4, x1, x2)

inst_15012:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xf3 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xf9800fff; valaddr_reg:x3; val_offset:45036*0 + 3*420*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45036*0 + 3*420*FLEN/8, x4, x1, x2)

inst_15013:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xf3 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xf9801fff; valaddr_reg:x3; val_offset:45039*0 + 3*421*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45039*0 + 3*421*FLEN/8, x4, x1, x2)

inst_15014:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xf3 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xf9803fff; valaddr_reg:x3; val_offset:45042*0 + 3*422*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45042*0 + 3*422*FLEN/8, x4, x1, x2)

inst_15015:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xf3 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xf9807fff; valaddr_reg:x3; val_offset:45045*0 + 3*423*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45045*0 + 3*423*FLEN/8, x4, x1, x2)

inst_15016:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xf3 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xf980ffff; valaddr_reg:x3; val_offset:45048*0 + 3*424*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45048*0 + 3*424*FLEN/8, x4, x1, x2)

inst_15017:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xf3 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xf981ffff; valaddr_reg:x3; val_offset:45051*0 + 3*425*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45051*0 + 3*425*FLEN/8, x4, x1, x2)

inst_15018:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xf3 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xf983ffff; valaddr_reg:x3; val_offset:45054*0 + 3*426*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45054*0 + 3*426*FLEN/8, x4, x1, x2)

inst_15019:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xf3 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xf987ffff; valaddr_reg:x3; val_offset:45057*0 + 3*427*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45057*0 + 3*427*FLEN/8, x4, x1, x2)

inst_15020:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xf3 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xf98fffff; valaddr_reg:x3; val_offset:45060*0 + 3*428*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45060*0 + 3*428*FLEN/8, x4, x1, x2)

inst_15021:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xf3 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xf99fffff; valaddr_reg:x3; val_offset:45063*0 + 3*429*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45063*0 + 3*429*FLEN/8, x4, x1, x2)

inst_15022:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xf3 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xf9bfffff; valaddr_reg:x3; val_offset:45066*0 + 3*430*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45066*0 + 3*430*FLEN/8, x4, x1, x2)

inst_15023:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xf3 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xf9c00000; valaddr_reg:x3; val_offset:45069*0 + 3*431*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45069*0 + 3*431*FLEN/8, x4, x1, x2)

inst_15024:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xf3 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xf9e00000; valaddr_reg:x3; val_offset:45072*0 + 3*432*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45072*0 + 3*432*FLEN/8, x4, x1, x2)

inst_15025:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xf3 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xf9f00000; valaddr_reg:x3; val_offset:45075*0 + 3*433*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45075*0 + 3*433*FLEN/8, x4, x1, x2)

inst_15026:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xf3 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xf9f80000; valaddr_reg:x3; val_offset:45078*0 + 3*434*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45078*0 + 3*434*FLEN/8, x4, x1, x2)

inst_15027:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xf3 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xf9fc0000; valaddr_reg:x3; val_offset:45081*0 + 3*435*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45081*0 + 3*435*FLEN/8, x4, x1, x2)

inst_15028:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xf3 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xf9fe0000; valaddr_reg:x3; val_offset:45084*0 + 3*436*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45084*0 + 3*436*FLEN/8, x4, x1, x2)

inst_15029:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xf3 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xf9ff0000; valaddr_reg:x3; val_offset:45087*0 + 3*437*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45087*0 + 3*437*FLEN/8, x4, x1, x2)

inst_15030:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xf3 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xf9ff8000; valaddr_reg:x3; val_offset:45090*0 + 3*438*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45090*0 + 3*438*FLEN/8, x4, x1, x2)

inst_15031:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xf3 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xf9ffc000; valaddr_reg:x3; val_offset:45093*0 + 3*439*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45093*0 + 3*439*FLEN/8, x4, x1, x2)

inst_15032:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xf3 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xf9ffe000; valaddr_reg:x3; val_offset:45096*0 + 3*440*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45096*0 + 3*440*FLEN/8, x4, x1, x2)

inst_15033:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xf3 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xf9fff000; valaddr_reg:x3; val_offset:45099*0 + 3*441*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45099*0 + 3*441*FLEN/8, x4, x1, x2)

inst_15034:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xf3 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xf9fff800; valaddr_reg:x3; val_offset:45102*0 + 3*442*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45102*0 + 3*442*FLEN/8, x4, x1, x2)

inst_15035:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xf3 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xf9fffc00; valaddr_reg:x3; val_offset:45105*0 + 3*443*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45105*0 + 3*443*FLEN/8, x4, x1, x2)

inst_15036:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xf3 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xf9fffe00; valaddr_reg:x3; val_offset:45108*0 + 3*444*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45108*0 + 3*444*FLEN/8, x4, x1, x2)

inst_15037:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xf3 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xf9ffff00; valaddr_reg:x3; val_offset:45111*0 + 3*445*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45111*0 + 3*445*FLEN/8, x4, x1, x2)

inst_15038:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xf3 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xf9ffff80; valaddr_reg:x3; val_offset:45114*0 + 3*446*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45114*0 + 3*446*FLEN/8, x4, x1, x2)

inst_15039:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xf3 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xf9ffffc0; valaddr_reg:x3; val_offset:45117*0 + 3*447*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45117*0 + 3*447*FLEN/8, x4, x1, x2)

inst_15040:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xf3 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xf9ffffe0; valaddr_reg:x3; val_offset:45120*0 + 3*448*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45120*0 + 3*448*FLEN/8, x4, x1, x2)

inst_15041:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xf3 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xf9fffff0; valaddr_reg:x3; val_offset:45123*0 + 3*449*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45123*0 + 3*449*FLEN/8, x4, x1, x2)

inst_15042:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xf3 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xf9fffff8; valaddr_reg:x3; val_offset:45126*0 + 3*450*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45126*0 + 3*450*FLEN/8, x4, x1, x2)

inst_15043:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xf3 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xf9fffffc; valaddr_reg:x3; val_offset:45129*0 + 3*451*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45129*0 + 3*451*FLEN/8, x4, x1, x2)

inst_15044:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xf3 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xf9fffffe; valaddr_reg:x3; val_offset:45132*0 + 3*452*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45132*0 + 3*452*FLEN/8, x4, x1, x2)

inst_15045:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xf3 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xf9ffffff; valaddr_reg:x3; val_offset:45135*0 + 3*453*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45135*0 + 3*453*FLEN/8, x4, x1, x2)

inst_15046:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xfe and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xff000001; valaddr_reg:x3; val_offset:45138*0 + 3*454*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45138*0 + 3*454*FLEN/8, x4, x1, x2)

inst_15047:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xfe and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xff000003; valaddr_reg:x3; val_offset:45141*0 + 3*455*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45141*0 + 3*455*FLEN/8, x4, x1, x2)

inst_15048:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xfe and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xff000007; valaddr_reg:x3; val_offset:45144*0 + 3*456*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45144*0 + 3*456*FLEN/8, x4, x1, x2)

inst_15049:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xfe and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xff199999; valaddr_reg:x3; val_offset:45147*0 + 3*457*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45147*0 + 3*457*FLEN/8, x4, x1, x2)

inst_15050:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xfe and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xff249249; valaddr_reg:x3; val_offset:45150*0 + 3*458*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45150*0 + 3*458*FLEN/8, x4, x1, x2)

inst_15051:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xfe and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xff333333; valaddr_reg:x3; val_offset:45153*0 + 3*459*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45153*0 + 3*459*FLEN/8, x4, x1, x2)

inst_15052:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xfe and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xff36db6d; valaddr_reg:x3; val_offset:45156*0 + 3*460*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45156*0 + 3*460*FLEN/8, x4, x1, x2)

inst_15053:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xfe and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xff3bbbbb; valaddr_reg:x3; val_offset:45159*0 + 3*461*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45159*0 + 3*461*FLEN/8, x4, x1, x2)

inst_15054:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xfe and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xff444444; valaddr_reg:x3; val_offset:45162*0 + 3*462*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45162*0 + 3*462*FLEN/8, x4, x1, x2)

inst_15055:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xfe and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xff4ccccc; valaddr_reg:x3; val_offset:45165*0 + 3*463*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45165*0 + 3*463*FLEN/8, x4, x1, x2)

inst_15056:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xfe and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xff5b6db6; valaddr_reg:x3; val_offset:45168*0 + 3*464*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45168*0 + 3*464*FLEN/8, x4, x1, x2)

inst_15057:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xfe and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xff666666; valaddr_reg:x3; val_offset:45171*0 + 3*465*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45171*0 + 3*465*FLEN/8, x4, x1, x2)

inst_15058:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xfe and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xff6db6db; valaddr_reg:x3; val_offset:45174*0 + 3*466*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45174*0 + 3*466*FLEN/8, x4, x1, x2)

inst_15059:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xff7ffff8; valaddr_reg:x3; val_offset:45177*0 + 3*467*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45177*0 + 3*467*FLEN/8, x4, x1, x2)

inst_15060:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xff7ffffc; valaddr_reg:x3; val_offset:45180*0 + 3*468*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45180*0 + 3*468*FLEN/8, x4, x1, x2)

inst_15061:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184c3b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x57284c and fs3 == 1 and fe3 == 0xfe and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984c3b; op2val:0xc057284c;
op3val:0xff7ffffe; valaddr_reg:x3; val_offset:45183*0 + 3*469*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45183*0 + 3*469*FLEN/8, x4, x1, x2)

inst_15062:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x3; val_offset:45186*0 + 3*470*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45186*0 + 3*470*FLEN/8, x4, x1, x2)

inst_15063:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x80000003; valaddr_reg:x3; val_offset:45189*0 + 3*471*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45189*0 + 3*471*FLEN/8, x4, x1, x2)

inst_15064:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x80000007; valaddr_reg:x3; val_offset:45192*0 + 3*472*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45192*0 + 3*472*FLEN/8, x4, x1, x2)

inst_15065:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x80199999; valaddr_reg:x3; val_offset:45195*0 + 3*473*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45195*0 + 3*473*FLEN/8, x4, x1, x2)

inst_15066:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x80249249; valaddr_reg:x3; val_offset:45198*0 + 3*474*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45198*0 + 3*474*FLEN/8, x4, x1, x2)

inst_15067:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x80333333; valaddr_reg:x3; val_offset:45201*0 + 3*475*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45201*0 + 3*475*FLEN/8, x4, x1, x2)

inst_15068:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x8036db6d; valaddr_reg:x3; val_offset:45204*0 + 3*476*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45204*0 + 3*476*FLEN/8, x4, x1, x2)

inst_15069:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x803bbbbb; valaddr_reg:x3; val_offset:45207*0 + 3*477*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45207*0 + 3*477*FLEN/8, x4, x1, x2)

inst_15070:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x80444444; valaddr_reg:x3; val_offset:45210*0 + 3*478*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45210*0 + 3*478*FLEN/8, x4, x1, x2)

inst_15071:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x804ccccc; valaddr_reg:x3; val_offset:45213*0 + 3*479*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45213*0 + 3*479*FLEN/8, x4, x1, x2)

inst_15072:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x805b6db6; valaddr_reg:x3; val_offset:45216*0 + 3*480*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45216*0 + 3*480*FLEN/8, x4, x1, x2)

inst_15073:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x80666666; valaddr_reg:x3; val_offset:45219*0 + 3*481*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45219*0 + 3*481*FLEN/8, x4, x1, x2)

inst_15074:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x806db6db; valaddr_reg:x3; val_offset:45222*0 + 3*482*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45222*0 + 3*482*FLEN/8, x4, x1, x2)

inst_15075:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x807ffff8; valaddr_reg:x3; val_offset:45225*0 + 3*483*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45225*0 + 3*483*FLEN/8, x4, x1, x2)

inst_15076:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x807ffffc; valaddr_reg:x3; val_offset:45228*0 + 3*484*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45228*0 + 3*484*FLEN/8, x4, x1, x2)

inst_15077:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x3; val_offset:45231*0 + 3*485*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45231*0 + 3*485*FLEN/8, x4, x1, x2)

inst_15078:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x8d000000; valaddr_reg:x3; val_offset:45234*0 + 3*486*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45234*0 + 3*486*FLEN/8, x4, x1, x2)

inst_15079:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x8d000001; valaddr_reg:x3; val_offset:45237*0 + 3*487*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45237*0 + 3*487*FLEN/8, x4, x1, x2)

inst_15080:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x8d000003; valaddr_reg:x3; val_offset:45240*0 + 3*488*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45240*0 + 3*488*FLEN/8, x4, x1, x2)

inst_15081:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x8d000007; valaddr_reg:x3; val_offset:45243*0 + 3*489*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45243*0 + 3*489*FLEN/8, x4, x1, x2)

inst_15082:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x8d00000f; valaddr_reg:x3; val_offset:45246*0 + 3*490*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45246*0 + 3*490*FLEN/8, x4, x1, x2)

inst_15083:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x8d00001f; valaddr_reg:x3; val_offset:45249*0 + 3*491*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45249*0 + 3*491*FLEN/8, x4, x1, x2)

inst_15084:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x8d00003f; valaddr_reg:x3; val_offset:45252*0 + 3*492*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45252*0 + 3*492*FLEN/8, x4, x1, x2)

inst_15085:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x8d00007f; valaddr_reg:x3; val_offset:45255*0 + 3*493*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45255*0 + 3*493*FLEN/8, x4, x1, x2)

inst_15086:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x8d0000ff; valaddr_reg:x3; val_offset:45258*0 + 3*494*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45258*0 + 3*494*FLEN/8, x4, x1, x2)

inst_15087:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x8d0001ff; valaddr_reg:x3; val_offset:45261*0 + 3*495*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45261*0 + 3*495*FLEN/8, x4, x1, x2)

inst_15088:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x8d0003ff; valaddr_reg:x3; val_offset:45264*0 + 3*496*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45264*0 + 3*496*FLEN/8, x4, x1, x2)

inst_15089:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x8d0007ff; valaddr_reg:x3; val_offset:45267*0 + 3*497*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45267*0 + 3*497*FLEN/8, x4, x1, x2)

inst_15090:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x8d000fff; valaddr_reg:x3; val_offset:45270*0 + 3*498*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45270*0 + 3*498*FLEN/8, x4, x1, x2)

inst_15091:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x8d001fff; valaddr_reg:x3; val_offset:45273*0 + 3*499*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45273*0 + 3*499*FLEN/8, x4, x1, x2)

inst_15092:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x8d003fff; valaddr_reg:x3; val_offset:45276*0 + 3*500*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45276*0 + 3*500*FLEN/8, x4, x1, x2)

inst_15093:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x8d007fff; valaddr_reg:x3; val_offset:45279*0 + 3*501*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45279*0 + 3*501*FLEN/8, x4, x1, x2)

inst_15094:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x8d00ffff; valaddr_reg:x3; val_offset:45282*0 + 3*502*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45282*0 + 3*502*FLEN/8, x4, x1, x2)

inst_15095:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x8d01ffff; valaddr_reg:x3; val_offset:45285*0 + 3*503*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45285*0 + 3*503*FLEN/8, x4, x1, x2)

inst_15096:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x8d03ffff; valaddr_reg:x3; val_offset:45288*0 + 3*504*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45288*0 + 3*504*FLEN/8, x4, x1, x2)

inst_15097:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x8d07ffff; valaddr_reg:x3; val_offset:45291*0 + 3*505*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45291*0 + 3*505*FLEN/8, x4, x1, x2)

inst_15098:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x8d0fffff; valaddr_reg:x3; val_offset:45294*0 + 3*506*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45294*0 + 3*506*FLEN/8, x4, x1, x2)

inst_15099:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x8d1fffff; valaddr_reg:x3; val_offset:45297*0 + 3*507*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45297*0 + 3*507*FLEN/8, x4, x1, x2)

inst_15100:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x8d3fffff; valaddr_reg:x3; val_offset:45300*0 + 3*508*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45300*0 + 3*508*FLEN/8, x4, x1, x2)

inst_15101:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x8d400000; valaddr_reg:x3; val_offset:45303*0 + 3*509*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45303*0 + 3*509*FLEN/8, x4, x1, x2)

inst_15102:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x8d600000; valaddr_reg:x3; val_offset:45306*0 + 3*510*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45306*0 + 3*510*FLEN/8, x4, x1, x2)

inst_15103:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x8d700000; valaddr_reg:x3; val_offset:45309*0 + 3*511*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45309*0 + 3*511*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_5)

inst_15104:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x8d780000; valaddr_reg:x3; val_offset:45312*0 + 3*512*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45312*0 + 3*512*FLEN/8, x4, x1, x2)

inst_15105:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x8d7c0000; valaddr_reg:x3; val_offset:45315*0 + 3*513*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45315*0 + 3*513*FLEN/8, x4, x1, x2)

inst_15106:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x8d7e0000; valaddr_reg:x3; val_offset:45318*0 + 3*514*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45318*0 + 3*514*FLEN/8, x4, x1, x2)

inst_15107:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x8d7f0000; valaddr_reg:x3; val_offset:45321*0 + 3*515*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45321*0 + 3*515*FLEN/8, x4, x1, x2)

inst_15108:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x8d7f8000; valaddr_reg:x3; val_offset:45324*0 + 3*516*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45324*0 + 3*516*FLEN/8, x4, x1, x2)

inst_15109:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x8d7fc000; valaddr_reg:x3; val_offset:45327*0 + 3*517*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45327*0 + 3*517*FLEN/8, x4, x1, x2)

inst_15110:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x8d7fe000; valaddr_reg:x3; val_offset:45330*0 + 3*518*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45330*0 + 3*518*FLEN/8, x4, x1, x2)

inst_15111:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x8d7ff000; valaddr_reg:x3; val_offset:45333*0 + 3*519*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45333*0 + 3*519*FLEN/8, x4, x1, x2)

inst_15112:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x8d7ff800; valaddr_reg:x3; val_offset:45336*0 + 3*520*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45336*0 + 3*520*FLEN/8, x4, x1, x2)

inst_15113:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x8d7ffc00; valaddr_reg:x3; val_offset:45339*0 + 3*521*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45339*0 + 3*521*FLEN/8, x4, x1, x2)

inst_15114:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x8d7ffe00; valaddr_reg:x3; val_offset:45342*0 + 3*522*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45342*0 + 3*522*FLEN/8, x4, x1, x2)

inst_15115:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x8d7fff00; valaddr_reg:x3; val_offset:45345*0 + 3*523*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45345*0 + 3*523*FLEN/8, x4, x1, x2)

inst_15116:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x8d7fff80; valaddr_reg:x3; val_offset:45348*0 + 3*524*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45348*0 + 3*524*FLEN/8, x4, x1, x2)

inst_15117:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x8d7fffc0; valaddr_reg:x3; val_offset:45351*0 + 3*525*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45351*0 + 3*525*FLEN/8, x4, x1, x2)

inst_15118:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x8d7fffe0; valaddr_reg:x3; val_offset:45354*0 + 3*526*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45354*0 + 3*526*FLEN/8, x4, x1, x2)

inst_15119:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x8d7ffff0; valaddr_reg:x3; val_offset:45357*0 + 3*527*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45357*0 + 3*527*FLEN/8, x4, x1, x2)

inst_15120:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x8d7ffff8; valaddr_reg:x3; val_offset:45360*0 + 3*528*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45360*0 + 3*528*FLEN/8, x4, x1, x2)

inst_15121:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x8d7ffffc; valaddr_reg:x3; val_offset:45363*0 + 3*529*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45363*0 + 3*529*FLEN/8, x4, x1, x2)

inst_15122:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x8d7ffffe; valaddr_reg:x3; val_offset:45366*0 + 3*530*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45366*0 + 3*530*FLEN/8, x4, x1, x2)

inst_15123:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x184f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x1a and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e984f43; op2val:0x80000000;
op3val:0x8d7fffff; valaddr_reg:x3; val_offset:45369*0 + 3*531*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45369*0 + 3*531*FLEN/8, x4, x1, x2)

inst_15124:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x1; valaddr_reg:x3; val_offset:45372*0 + 3*532*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45372*0 + 3*532*FLEN/8, x4, x1, x2)

inst_15125:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x3; valaddr_reg:x3; val_offset:45375*0 + 3*533*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45375*0 + 3*533*FLEN/8, x4, x1, x2)

inst_15126:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x7; valaddr_reg:x3; val_offset:45378*0 + 3*534*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45378*0 + 3*534*FLEN/8, x4, x1, x2)

inst_15127:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x199999; valaddr_reg:x3; val_offset:45381*0 + 3*535*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45381*0 + 3*535*FLEN/8, x4, x1, x2)

inst_15128:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x249249; valaddr_reg:x3; val_offset:45384*0 + 3*536*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45384*0 + 3*536*FLEN/8, x4, x1, x2)

inst_15129:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x333333; valaddr_reg:x3; val_offset:45387*0 + 3*537*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45387*0 + 3*537*FLEN/8, x4, x1, x2)

inst_15130:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x36db6d; valaddr_reg:x3; val_offset:45390*0 + 3*538*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45390*0 + 3*538*FLEN/8, x4, x1, x2)

inst_15131:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x3bbbbb; valaddr_reg:x3; val_offset:45393*0 + 3*539*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45393*0 + 3*539*FLEN/8, x4, x1, x2)

inst_15132:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x444444; valaddr_reg:x3; val_offset:45396*0 + 3*540*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45396*0 + 3*540*FLEN/8, x4, x1, x2)

inst_15133:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x4ccccc; valaddr_reg:x3; val_offset:45399*0 + 3*541*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45399*0 + 3*541*FLEN/8, x4, x1, x2)

inst_15134:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x5b6db6; valaddr_reg:x3; val_offset:45402*0 + 3*542*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45402*0 + 3*542*FLEN/8, x4, x1, x2)

inst_15135:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x666666; valaddr_reg:x3; val_offset:45405*0 + 3*543*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45405*0 + 3*543*FLEN/8, x4, x1, x2)

inst_15136:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x6db6db; valaddr_reg:x3; val_offset:45408*0 + 3*544*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45408*0 + 3*544*FLEN/8, x4, x1, x2)

inst_15137:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x7ffff8; valaddr_reg:x3; val_offset:45411*0 + 3*545*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45411*0 + 3*545*FLEN/8, x4, x1, x2)

inst_15138:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x7ffffc; valaddr_reg:x3; val_offset:45414*0 + 3*546*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45414*0 + 3*546*FLEN/8, x4, x1, x2)

inst_15139:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x7ffffe; valaddr_reg:x3; val_offset:45417*0 + 3*547*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45417*0 + 3*547*FLEN/8, x4, x1, x2)

inst_15140:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x5800000; valaddr_reg:x3; val_offset:45420*0 + 3*548*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45420*0 + 3*548*FLEN/8, x4, x1, x2)

inst_15141:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x5800001; valaddr_reg:x3; val_offset:45423*0 + 3*549*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45423*0 + 3*549*FLEN/8, x4, x1, x2)

inst_15142:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x5800003; valaddr_reg:x3; val_offset:45426*0 + 3*550*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45426*0 + 3*550*FLEN/8, x4, x1, x2)

inst_15143:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x5800007; valaddr_reg:x3; val_offset:45429*0 + 3*551*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45429*0 + 3*551*FLEN/8, x4, x1, x2)

inst_15144:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x580000f; valaddr_reg:x3; val_offset:45432*0 + 3*552*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45432*0 + 3*552*FLEN/8, x4, x1, x2)

inst_15145:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x580001f; valaddr_reg:x3; val_offset:45435*0 + 3*553*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45435*0 + 3*553*FLEN/8, x4, x1, x2)

inst_15146:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x580003f; valaddr_reg:x3; val_offset:45438*0 + 3*554*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45438*0 + 3*554*FLEN/8, x4, x1, x2)

inst_15147:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x580007f; valaddr_reg:x3; val_offset:45441*0 + 3*555*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45441*0 + 3*555*FLEN/8, x4, x1, x2)

inst_15148:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x58000ff; valaddr_reg:x3; val_offset:45444*0 + 3*556*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45444*0 + 3*556*FLEN/8, x4, x1, x2)

inst_15149:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x58001ff; valaddr_reg:x3; val_offset:45447*0 + 3*557*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45447*0 + 3*557*FLEN/8, x4, x1, x2)

inst_15150:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x58003ff; valaddr_reg:x3; val_offset:45450*0 + 3*558*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45450*0 + 3*558*FLEN/8, x4, x1, x2)

inst_15151:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x58007ff; valaddr_reg:x3; val_offset:45453*0 + 3*559*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45453*0 + 3*559*FLEN/8, x4, x1, x2)

inst_15152:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x5800fff; valaddr_reg:x3; val_offset:45456*0 + 3*560*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45456*0 + 3*560*FLEN/8, x4, x1, x2)

inst_15153:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x5801fff; valaddr_reg:x3; val_offset:45459*0 + 3*561*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45459*0 + 3*561*FLEN/8, x4, x1, x2)

inst_15154:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x5803fff; valaddr_reg:x3; val_offset:45462*0 + 3*562*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45462*0 + 3*562*FLEN/8, x4, x1, x2)

inst_15155:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x5807fff; valaddr_reg:x3; val_offset:45465*0 + 3*563*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45465*0 + 3*563*FLEN/8, x4, x1, x2)

inst_15156:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x580ffff; valaddr_reg:x3; val_offset:45468*0 + 3*564*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45468*0 + 3*564*FLEN/8, x4, x1, x2)

inst_15157:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x581ffff; valaddr_reg:x3; val_offset:45471*0 + 3*565*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45471*0 + 3*565*FLEN/8, x4, x1, x2)

inst_15158:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x583ffff; valaddr_reg:x3; val_offset:45474*0 + 3*566*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45474*0 + 3*566*FLEN/8, x4, x1, x2)

inst_15159:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x587ffff; valaddr_reg:x3; val_offset:45477*0 + 3*567*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45477*0 + 3*567*FLEN/8, x4, x1, x2)

inst_15160:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x58fffff; valaddr_reg:x3; val_offset:45480*0 + 3*568*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45480*0 + 3*568*FLEN/8, x4, x1, x2)

inst_15161:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x59fffff; valaddr_reg:x3; val_offset:45483*0 + 3*569*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45483*0 + 3*569*FLEN/8, x4, x1, x2)

inst_15162:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x5bfffff; valaddr_reg:x3; val_offset:45486*0 + 3*570*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45486*0 + 3*570*FLEN/8, x4, x1, x2)

inst_15163:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x5c00000; valaddr_reg:x3; val_offset:45489*0 + 3*571*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45489*0 + 3*571*FLEN/8, x4, x1, x2)

inst_15164:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x5e00000; valaddr_reg:x3; val_offset:45492*0 + 3*572*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45492*0 + 3*572*FLEN/8, x4, x1, x2)

inst_15165:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x5f00000; valaddr_reg:x3; val_offset:45495*0 + 3*573*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45495*0 + 3*573*FLEN/8, x4, x1, x2)

inst_15166:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x5f80000; valaddr_reg:x3; val_offset:45498*0 + 3*574*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45498*0 + 3*574*FLEN/8, x4, x1, x2)

inst_15167:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x5fc0000; valaddr_reg:x3; val_offset:45501*0 + 3*575*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45501*0 + 3*575*FLEN/8, x4, x1, x2)

inst_15168:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x5fe0000; valaddr_reg:x3; val_offset:45504*0 + 3*576*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45504*0 + 3*576*FLEN/8, x4, x1, x2)

inst_15169:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x5ff0000; valaddr_reg:x3; val_offset:45507*0 + 3*577*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45507*0 + 3*577*FLEN/8, x4, x1, x2)

inst_15170:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x5ff8000; valaddr_reg:x3; val_offset:45510*0 + 3*578*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45510*0 + 3*578*FLEN/8, x4, x1, x2)

inst_15171:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x5ffc000; valaddr_reg:x3; val_offset:45513*0 + 3*579*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45513*0 + 3*579*FLEN/8, x4, x1, x2)

inst_15172:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x5ffe000; valaddr_reg:x3; val_offset:45516*0 + 3*580*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45516*0 + 3*580*FLEN/8, x4, x1, x2)

inst_15173:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x5fff000; valaddr_reg:x3; val_offset:45519*0 + 3*581*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45519*0 + 3*581*FLEN/8, x4, x1, x2)

inst_15174:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x5fff800; valaddr_reg:x3; val_offset:45522*0 + 3*582*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45522*0 + 3*582*FLEN/8, x4, x1, x2)

inst_15175:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x5fffc00; valaddr_reg:x3; val_offset:45525*0 + 3*583*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45525*0 + 3*583*FLEN/8, x4, x1, x2)

inst_15176:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x5fffe00; valaddr_reg:x3; val_offset:45528*0 + 3*584*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45528*0 + 3*584*FLEN/8, x4, x1, x2)

inst_15177:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x5ffff00; valaddr_reg:x3; val_offset:45531*0 + 3*585*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45531*0 + 3*585*FLEN/8, x4, x1, x2)

inst_15178:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x5ffff80; valaddr_reg:x3; val_offset:45534*0 + 3*586*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45534*0 + 3*586*FLEN/8, x4, x1, x2)

inst_15179:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x5ffffc0; valaddr_reg:x3; val_offset:45537*0 + 3*587*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45537*0 + 3*587*FLEN/8, x4, x1, x2)

inst_15180:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x5ffffe0; valaddr_reg:x3; val_offset:45540*0 + 3*588*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45540*0 + 3*588*FLEN/8, x4, x1, x2)

inst_15181:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x5fffff0; valaddr_reg:x3; val_offset:45543*0 + 3*589*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45543*0 + 3*589*FLEN/8, x4, x1, x2)

inst_15182:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x5fffff8; valaddr_reg:x3; val_offset:45546*0 + 3*590*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45546*0 + 3*590*FLEN/8, x4, x1, x2)

inst_15183:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x5fffffc; valaddr_reg:x3; val_offset:45549*0 + 3*591*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45549*0 + 3*591*FLEN/8, x4, x1, x2)

inst_15184:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x5fffffe; valaddr_reg:x3; val_offset:45552*0 + 3*592*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45552*0 + 3*592*FLEN/8, x4, x1, x2)

inst_15185:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x187fea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x0b and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e987fea; op2val:0x0;
op3val:0x5ffffff; valaddr_reg:x3; val_offset:45555*0 + 3*593*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45555*0 + 3*593*FLEN/8, x4, x1, x2)

inst_15186:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x80000001; valaddr_reg:x3; val_offset:45558*0 + 3*594*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45558*0 + 3*594*FLEN/8, x4, x1, x2)

inst_15187:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x80000003; valaddr_reg:x3; val_offset:45561*0 + 3*595*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45561*0 + 3*595*FLEN/8, x4, x1, x2)

inst_15188:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x80000007; valaddr_reg:x3; val_offset:45564*0 + 3*596*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45564*0 + 3*596*FLEN/8, x4, x1, x2)

inst_15189:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x80199999; valaddr_reg:x3; val_offset:45567*0 + 3*597*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45567*0 + 3*597*FLEN/8, x4, x1, x2)

inst_15190:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x80249249; valaddr_reg:x3; val_offset:45570*0 + 3*598*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45570*0 + 3*598*FLEN/8, x4, x1, x2)

inst_15191:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x80333333; valaddr_reg:x3; val_offset:45573*0 + 3*599*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45573*0 + 3*599*FLEN/8, x4, x1, x2)

inst_15192:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x8036db6d; valaddr_reg:x3; val_offset:45576*0 + 3*600*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45576*0 + 3*600*FLEN/8, x4, x1, x2)

inst_15193:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x803bbbbb; valaddr_reg:x3; val_offset:45579*0 + 3*601*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45579*0 + 3*601*FLEN/8, x4, x1, x2)

inst_15194:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x80444444; valaddr_reg:x3; val_offset:45582*0 + 3*602*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45582*0 + 3*602*FLEN/8, x4, x1, x2)

inst_15195:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x804ccccc; valaddr_reg:x3; val_offset:45585*0 + 3*603*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45585*0 + 3*603*FLEN/8, x4, x1, x2)

inst_15196:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x805b6db6; valaddr_reg:x3; val_offset:45588*0 + 3*604*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45588*0 + 3*604*FLEN/8, x4, x1, x2)

inst_15197:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x80666666; valaddr_reg:x3; val_offset:45591*0 + 3*605*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45591*0 + 3*605*FLEN/8, x4, x1, x2)

inst_15198:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x806db6db; valaddr_reg:x3; val_offset:45594*0 + 3*606*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45594*0 + 3*606*FLEN/8, x4, x1, x2)

inst_15199:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x807ffff8; valaddr_reg:x3; val_offset:45597*0 + 3*607*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45597*0 + 3*607*FLEN/8, x4, x1, x2)

inst_15200:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x807ffffc; valaddr_reg:x3; val_offset:45600*0 + 3*608*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45600*0 + 3*608*FLEN/8, x4, x1, x2)

inst_15201:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x807ffffe; valaddr_reg:x3; val_offset:45603*0 + 3*609*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45603*0 + 3*609*FLEN/8, x4, x1, x2)

inst_15202:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0b and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x85800000; valaddr_reg:x3; val_offset:45606*0 + 3*610*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45606*0 + 3*610*FLEN/8, x4, x1, x2)

inst_15203:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0b and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x85800001; valaddr_reg:x3; val_offset:45609*0 + 3*611*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45609*0 + 3*611*FLEN/8, x4, x1, x2)

inst_15204:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0b and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x85800003; valaddr_reg:x3; val_offset:45612*0 + 3*612*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45612*0 + 3*612*FLEN/8, x4, x1, x2)

inst_15205:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0b and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x85800007; valaddr_reg:x3; val_offset:45615*0 + 3*613*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45615*0 + 3*613*FLEN/8, x4, x1, x2)

inst_15206:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0b and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x8580000f; valaddr_reg:x3; val_offset:45618*0 + 3*614*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45618*0 + 3*614*FLEN/8, x4, x1, x2)

inst_15207:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0b and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x8580001f; valaddr_reg:x3; val_offset:45621*0 + 3*615*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45621*0 + 3*615*FLEN/8, x4, x1, x2)

inst_15208:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0b and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x8580003f; valaddr_reg:x3; val_offset:45624*0 + 3*616*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45624*0 + 3*616*FLEN/8, x4, x1, x2)

inst_15209:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0b and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x8580007f; valaddr_reg:x3; val_offset:45627*0 + 3*617*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45627*0 + 3*617*FLEN/8, x4, x1, x2)

inst_15210:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0b and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x858000ff; valaddr_reg:x3; val_offset:45630*0 + 3*618*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45630*0 + 3*618*FLEN/8, x4, x1, x2)

inst_15211:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0b and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x858001ff; valaddr_reg:x3; val_offset:45633*0 + 3*619*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45633*0 + 3*619*FLEN/8, x4, x1, x2)

inst_15212:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0b and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x858003ff; valaddr_reg:x3; val_offset:45636*0 + 3*620*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45636*0 + 3*620*FLEN/8, x4, x1, x2)

inst_15213:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0b and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x858007ff; valaddr_reg:x3; val_offset:45639*0 + 3*621*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45639*0 + 3*621*FLEN/8, x4, x1, x2)

inst_15214:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0b and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x85800fff; valaddr_reg:x3; val_offset:45642*0 + 3*622*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45642*0 + 3*622*FLEN/8, x4, x1, x2)

inst_15215:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0b and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x85801fff; valaddr_reg:x3; val_offset:45645*0 + 3*623*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45645*0 + 3*623*FLEN/8, x4, x1, x2)

inst_15216:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0b and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x85803fff; valaddr_reg:x3; val_offset:45648*0 + 3*624*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45648*0 + 3*624*FLEN/8, x4, x1, x2)

inst_15217:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0b and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x85807fff; valaddr_reg:x3; val_offset:45651*0 + 3*625*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45651*0 + 3*625*FLEN/8, x4, x1, x2)

inst_15218:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0b and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x8580ffff; valaddr_reg:x3; val_offset:45654*0 + 3*626*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45654*0 + 3*626*FLEN/8, x4, x1, x2)

inst_15219:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0b and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x8581ffff; valaddr_reg:x3; val_offset:45657*0 + 3*627*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45657*0 + 3*627*FLEN/8, x4, x1, x2)

inst_15220:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0b and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x8583ffff; valaddr_reg:x3; val_offset:45660*0 + 3*628*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45660*0 + 3*628*FLEN/8, x4, x1, x2)

inst_15221:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0b and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x8587ffff; valaddr_reg:x3; val_offset:45663*0 + 3*629*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45663*0 + 3*629*FLEN/8, x4, x1, x2)

inst_15222:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0b and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x858fffff; valaddr_reg:x3; val_offset:45666*0 + 3*630*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45666*0 + 3*630*FLEN/8, x4, x1, x2)

inst_15223:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0b and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x859fffff; valaddr_reg:x3; val_offset:45669*0 + 3*631*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45669*0 + 3*631*FLEN/8, x4, x1, x2)

inst_15224:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0b and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x85bfffff; valaddr_reg:x3; val_offset:45672*0 + 3*632*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45672*0 + 3*632*FLEN/8, x4, x1, x2)

inst_15225:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0b and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x85c00000; valaddr_reg:x3; val_offset:45675*0 + 3*633*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45675*0 + 3*633*FLEN/8, x4, x1, x2)

inst_15226:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0b and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x85e00000; valaddr_reg:x3; val_offset:45678*0 + 3*634*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45678*0 + 3*634*FLEN/8, x4, x1, x2)

inst_15227:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0b and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x85f00000; valaddr_reg:x3; val_offset:45681*0 + 3*635*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45681*0 + 3*635*FLEN/8, x4, x1, x2)

inst_15228:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0b and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x85f80000; valaddr_reg:x3; val_offset:45684*0 + 3*636*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45684*0 + 3*636*FLEN/8, x4, x1, x2)

inst_15229:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0b and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x85fc0000; valaddr_reg:x3; val_offset:45687*0 + 3*637*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45687*0 + 3*637*FLEN/8, x4, x1, x2)

inst_15230:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0b and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x85fe0000; valaddr_reg:x3; val_offset:45690*0 + 3*638*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45690*0 + 3*638*FLEN/8, x4, x1, x2)

inst_15231:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0b and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x85ff0000; valaddr_reg:x3; val_offset:45693*0 + 3*639*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45693*0 + 3*639*FLEN/8, x4, x1, x2)
RVTEST_SIGBASE(x1,signature_x1_6)

inst_15232:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0b and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x85ff8000; valaddr_reg:x3; val_offset:45696*0 + 3*640*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45696*0 + 3*640*FLEN/8, x4, x1, x2)

inst_15233:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0b and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x85ffc000; valaddr_reg:x3; val_offset:45699*0 + 3*641*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45699*0 + 3*641*FLEN/8, x4, x1, x2)

inst_15234:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0b and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x85ffe000; valaddr_reg:x3; val_offset:45702*0 + 3*642*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45702*0 + 3*642*FLEN/8, x4, x1, x2)

inst_15235:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0b and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x85fff000; valaddr_reg:x3; val_offset:45705*0 + 3*643*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45705*0 + 3*643*FLEN/8, x4, x1, x2)

inst_15236:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0b and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x85fff800; valaddr_reg:x3; val_offset:45708*0 + 3*644*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45708*0 + 3*644*FLEN/8, x4, x1, x2)

inst_15237:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0b and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x85fffc00; valaddr_reg:x3; val_offset:45711*0 + 3*645*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45711*0 + 3*645*FLEN/8, x4, x1, x2)

inst_15238:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0b and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x85fffe00; valaddr_reg:x3; val_offset:45714*0 + 3*646*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45714*0 + 3*646*FLEN/8, x4, x1, x2)

inst_15239:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0b and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x85ffff00; valaddr_reg:x3; val_offset:45717*0 + 3*647*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45717*0 + 3*647*FLEN/8, x4, x1, x2)

inst_15240:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0b and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x85ffff80; valaddr_reg:x3; val_offset:45720*0 + 3*648*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45720*0 + 3*648*FLEN/8, x4, x1, x2)

inst_15241:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0b and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x85ffffc0; valaddr_reg:x3; val_offset:45723*0 + 3*649*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45723*0 + 3*649*FLEN/8, x4, x1, x2)

inst_15242:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0b and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x85ffffe0; valaddr_reg:x3; val_offset:45726*0 + 3*650*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45726*0 + 3*650*FLEN/8, x4, x1, x2)

inst_15243:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0b and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x85fffff0; valaddr_reg:x3; val_offset:45729*0 + 3*651*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45729*0 + 3*651*FLEN/8, x4, x1, x2)

inst_15244:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0b and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x85fffff8; valaddr_reg:x3; val_offset:45732*0 + 3*652*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45732*0 + 3*652*FLEN/8, x4, x1, x2)

inst_15245:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0b and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x85fffffc; valaddr_reg:x3; val_offset:45735*0 + 3*653*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45735*0 + 3*653*FLEN/8, x4, x1, x2)

inst_15246:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0b and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x85fffffe; valaddr_reg:x3; val_offset:45738*0 + 3*654*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45738*0 + 3*654*FLEN/8, x4, x1, x2)

inst_15247:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x19b362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 1 and fe3 == 0x0b and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e99b362; op2val:0x80000000;
op3val:0x85ffffff; valaddr_reg:x3; val_offset:45741*0 + 3*655*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45741*0 + 3*655*FLEN/8, x4, x1, x2)

inst_15248:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x1; valaddr_reg:x3; val_offset:45744*0 + 3*656*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45744*0 + 3*656*FLEN/8, x4, x1, x2)

inst_15249:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x3; valaddr_reg:x3; val_offset:45747*0 + 3*657*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45747*0 + 3*657*FLEN/8, x4, x1, x2)

inst_15250:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x7; valaddr_reg:x3; val_offset:45750*0 + 3*658*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45750*0 + 3*658*FLEN/8, x4, x1, x2)

inst_15251:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x199999; valaddr_reg:x3; val_offset:45753*0 + 3*659*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45753*0 + 3*659*FLEN/8, x4, x1, x2)

inst_15252:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x249249 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x249249; valaddr_reg:x3; val_offset:45756*0 + 3*660*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45756*0 + 3*660*FLEN/8, x4, x1, x2)

inst_15253:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x333333 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x333333; valaddr_reg:x3; val_offset:45759*0 + 3*661*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45759*0 + 3*661*FLEN/8, x4, x1, x2)

inst_15254:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x36db6d and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x36db6d; valaddr_reg:x3; val_offset:45762*0 + 3*662*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45762*0 + 3*662*FLEN/8, x4, x1, x2)

inst_15255:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3bbbbb and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x3bbbbb; valaddr_reg:x3; val_offset:45765*0 + 3*663*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45765*0 + 3*663*FLEN/8, x4, x1, x2)

inst_15256:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x444444 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x444444; valaddr_reg:x3; val_offset:45768*0 + 3*664*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45768*0 + 3*664*FLEN/8, x4, x1, x2)

inst_15257:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x4ccccc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x4ccccc; valaddr_reg:x3; val_offset:45771*0 + 3*665*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45771*0 + 3*665*FLEN/8, x4, x1, x2)

inst_15258:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x5b6db6 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x5b6db6; valaddr_reg:x3; val_offset:45774*0 + 3*666*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45774*0 + 3*666*FLEN/8, x4, x1, x2)

inst_15259:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x666666 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x666666; valaddr_reg:x3; val_offset:45777*0 + 3*667*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45777*0 + 3*667*FLEN/8, x4, x1, x2)

inst_15260:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x6db6db and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x6db6db; valaddr_reg:x3; val_offset:45780*0 + 3*668*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45780*0 + 3*668*FLEN/8, x4, x1, x2)

inst_15261:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x7ffff8; valaddr_reg:x3; val_offset:45783*0 + 3*669*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45783*0 + 3*669*FLEN/8, x4, x1, x2)

inst_15262:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x7ffffc; valaddr_reg:x3; val_offset:45786*0 + 3*670*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45786*0 + 3*670*FLEN/8, x4, x1, x2)

inst_15263:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x7ffffe; valaddr_reg:x3; val_offset:45789*0 + 3*671*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45789*0 + 3*671*FLEN/8, x4, x1, x2)

inst_15264:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x05 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x2800000; valaddr_reg:x3; val_offset:45792*0 + 3*672*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45792*0 + 3*672*FLEN/8, x4, x1, x2)

inst_15265:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x05 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x2800001; valaddr_reg:x3; val_offset:45795*0 + 3*673*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45795*0 + 3*673*FLEN/8, x4, x1, x2)

inst_15266:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x05 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x2800003; valaddr_reg:x3; val_offset:45798*0 + 3*674*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45798*0 + 3*674*FLEN/8, x4, x1, x2)

inst_15267:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x05 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x2800007; valaddr_reg:x3; val_offset:45801*0 + 3*675*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45801*0 + 3*675*FLEN/8, x4, x1, x2)

inst_15268:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x05 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x280000f; valaddr_reg:x3; val_offset:45804*0 + 3*676*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45804*0 + 3*676*FLEN/8, x4, x1, x2)

inst_15269:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x05 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x280001f; valaddr_reg:x3; val_offset:45807*0 + 3*677*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45807*0 + 3*677*FLEN/8, x4, x1, x2)

inst_15270:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x05 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x280003f; valaddr_reg:x3; val_offset:45810*0 + 3*678*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45810*0 + 3*678*FLEN/8, x4, x1, x2)

inst_15271:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x05 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x280007f; valaddr_reg:x3; val_offset:45813*0 + 3*679*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45813*0 + 3*679*FLEN/8, x4, x1, x2)

inst_15272:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x05 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x28000ff; valaddr_reg:x3; val_offset:45816*0 + 3*680*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45816*0 + 3*680*FLEN/8, x4, x1, x2)

inst_15273:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x05 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x28001ff; valaddr_reg:x3; val_offset:45819*0 + 3*681*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45819*0 + 3*681*FLEN/8, x4, x1, x2)

inst_15274:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x05 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x28003ff; valaddr_reg:x3; val_offset:45822*0 + 3*682*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45822*0 + 3*682*FLEN/8, x4, x1, x2)

inst_15275:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x05 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x28007ff; valaddr_reg:x3; val_offset:45825*0 + 3*683*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45825*0 + 3*683*FLEN/8, x4, x1, x2)

inst_15276:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x05 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x2800fff; valaddr_reg:x3; val_offset:45828*0 + 3*684*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45828*0 + 3*684*FLEN/8, x4, x1, x2)

inst_15277:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x05 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x2801fff; valaddr_reg:x3; val_offset:45831*0 + 3*685*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45831*0 + 3*685*FLEN/8, x4, x1, x2)

inst_15278:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x05 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x2803fff; valaddr_reg:x3; val_offset:45834*0 + 3*686*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45834*0 + 3*686*FLEN/8, x4, x1, x2)

inst_15279:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x05 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x2807fff; valaddr_reg:x3; val_offset:45837*0 + 3*687*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45837*0 + 3*687*FLEN/8, x4, x1, x2)

inst_15280:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x05 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x280ffff; valaddr_reg:x3; val_offset:45840*0 + 3*688*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45840*0 + 3*688*FLEN/8, x4, x1, x2)

inst_15281:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x05 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x281ffff; valaddr_reg:x3; val_offset:45843*0 + 3*689*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45843*0 + 3*689*FLEN/8, x4, x1, x2)

inst_15282:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x05 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x283ffff; valaddr_reg:x3; val_offset:45846*0 + 3*690*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45846*0 + 3*690*FLEN/8, x4, x1, x2)

inst_15283:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x05 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x287ffff; valaddr_reg:x3; val_offset:45849*0 + 3*691*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45849*0 + 3*691*FLEN/8, x4, x1, x2)

inst_15284:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x05 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x28fffff; valaddr_reg:x3; val_offset:45852*0 + 3*692*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45852*0 + 3*692*FLEN/8, x4, x1, x2)

inst_15285:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x05 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x29fffff; valaddr_reg:x3; val_offset:45855*0 + 3*693*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45855*0 + 3*693*FLEN/8, x4, x1, x2)

inst_15286:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x05 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x2bfffff; valaddr_reg:x3; val_offset:45858*0 + 3*694*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45858*0 + 3*694*FLEN/8, x4, x1, x2)

inst_15287:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x05 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x2c00000; valaddr_reg:x3; val_offset:45861*0 + 3*695*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45861*0 + 3*695*FLEN/8, x4, x1, x2)

inst_15288:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x05 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x2e00000; valaddr_reg:x3; val_offset:45864*0 + 3*696*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45864*0 + 3*696*FLEN/8, x4, x1, x2)

inst_15289:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x05 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x2f00000; valaddr_reg:x3; val_offset:45867*0 + 3*697*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45867*0 + 3*697*FLEN/8, x4, x1, x2)

inst_15290:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x05 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x2f80000; valaddr_reg:x3; val_offset:45870*0 + 3*698*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45870*0 + 3*698*FLEN/8, x4, x1, x2)

inst_15291:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x05 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x2fc0000; valaddr_reg:x3; val_offset:45873*0 + 3*699*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45873*0 + 3*699*FLEN/8, x4, x1, x2)

inst_15292:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x05 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x2fe0000; valaddr_reg:x3; val_offset:45876*0 + 3*700*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45876*0 + 3*700*FLEN/8, x4, x1, x2)

inst_15293:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x05 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x2ff0000; valaddr_reg:x3; val_offset:45879*0 + 3*701*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45879*0 + 3*701*FLEN/8, x4, x1, x2)

inst_15294:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x05 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x2ff8000; valaddr_reg:x3; val_offset:45882*0 + 3*702*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45882*0 + 3*702*FLEN/8, x4, x1, x2)

inst_15295:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x05 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x2ffc000; valaddr_reg:x3; val_offset:45885*0 + 3*703*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45885*0 + 3*703*FLEN/8, x4, x1, x2)

inst_15296:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x05 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x2ffe000; valaddr_reg:x3; val_offset:45888*0 + 3*704*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45888*0 + 3*704*FLEN/8, x4, x1, x2)

inst_15297:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x05 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x2fff000; valaddr_reg:x3; val_offset:45891*0 + 3*705*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45891*0 + 3*705*FLEN/8, x4, x1, x2)

inst_15298:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x05 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x2fff800; valaddr_reg:x3; val_offset:45894*0 + 3*706*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45894*0 + 3*706*FLEN/8, x4, x1, x2)

inst_15299:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x05 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x2fffc00; valaddr_reg:x3; val_offset:45897*0 + 3*707*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45897*0 + 3*707*FLEN/8, x4, x1, x2)

inst_15300:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x05 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x2fffe00; valaddr_reg:x3; val_offset:45900*0 + 3*708*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45900*0 + 3*708*FLEN/8, x4, x1, x2)

inst_15301:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x05 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x2ffff00; valaddr_reg:x3; val_offset:45903*0 + 3*709*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45903*0 + 3*709*FLEN/8, x4, x1, x2)

inst_15302:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x05 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x2ffff80; valaddr_reg:x3; val_offset:45906*0 + 3*710*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45906*0 + 3*710*FLEN/8, x4, x1, x2)

inst_15303:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x05 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x2ffffc0; valaddr_reg:x3; val_offset:45909*0 + 3*711*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45909*0 + 3*711*FLEN/8, x4, x1, x2)

inst_15304:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x05 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x2ffffe0; valaddr_reg:x3; val_offset:45912*0 + 3*712*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45912*0 + 3*712*FLEN/8, x4, x1, x2)

inst_15305:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x05 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x2fffff0; valaddr_reg:x3; val_offset:45915*0 + 3*713*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45915*0 + 3*713*FLEN/8, x4, x1, x2)

inst_15306:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x05 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x2fffff8; valaddr_reg:x3; val_offset:45918*0 + 3*714*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45918*0 + 3*714*FLEN/8, x4, x1, x2)

inst_15307:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x05 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x2fffffc; valaddr_reg:x3; val_offset:45921*0 + 3*715*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45921*0 + 3*715*FLEN/8, x4, x1, x2)

inst_15308:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x05 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x2fffffe; valaddr_reg:x3; val_offset:45924*0 + 3*716*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45924*0 + 3*716*FLEN/8, x4, x1, x2)

inst_15309:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a0102 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fs3 == 0 and fe3 == 0x05 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a0102; op2val:0x0;
op3val:0x2ffffff; valaddr_reg:x3; val_offset:45927*0 + 3*717*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45927*0 + 3*717*FLEN/8, x4, x1, x2)

inst_15310:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a28e8 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x548f03 and fs3 == 1 and fe3 == 0xd5 and fm3 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a28e8; op2val:0xc0548f03;
op3val:0xea800000; valaddr_reg:x3; val_offset:45930*0 + 3*718*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45930*0 + 3*718*FLEN/8, x4, x1, x2)

inst_15311:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a28e8 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x548f03 and fs3 == 1 and fe3 == 0xd5 and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a28e8; op2val:0xc0548f03;
op3val:0xea800001; valaddr_reg:x3; val_offset:45933*0 + 3*719*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45933*0 + 3*719*FLEN/8, x4, x1, x2)

inst_15312:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a28e8 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x548f03 and fs3 == 1 and fe3 == 0xd5 and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a28e8; op2val:0xc0548f03;
op3val:0xea800003; valaddr_reg:x3; val_offset:45936*0 + 3*720*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45936*0 + 3*720*FLEN/8, x4, x1, x2)

inst_15313:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a28e8 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x548f03 and fs3 == 1 and fe3 == 0xd5 and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a28e8; op2val:0xc0548f03;
op3val:0xea800007; valaddr_reg:x3; val_offset:45939*0 + 3*721*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45939*0 + 3*721*FLEN/8, x4, x1, x2)

inst_15314:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a28e8 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x548f03 and fs3 == 1 and fe3 == 0xd5 and fm3 == 0x00000f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a28e8; op2val:0xc0548f03;
op3val:0xea80000f; valaddr_reg:x3; val_offset:45942*0 + 3*722*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45942*0 + 3*722*FLEN/8, x4, x1, x2)

inst_15315:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a28e8 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x548f03 and fs3 == 1 and fe3 == 0xd5 and fm3 == 0x00001f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a28e8; op2val:0xc0548f03;
op3val:0xea80001f; valaddr_reg:x3; val_offset:45945*0 + 3*723*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45945*0 + 3*723*FLEN/8, x4, x1, x2)

inst_15316:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a28e8 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x548f03 and fs3 == 1 and fe3 == 0xd5 and fm3 == 0x00003f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a28e8; op2val:0xc0548f03;
op3val:0xea80003f; valaddr_reg:x3; val_offset:45948*0 + 3*724*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45948*0 + 3*724*FLEN/8, x4, x1, x2)

inst_15317:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a28e8 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x548f03 and fs3 == 1 and fe3 == 0xd5 and fm3 == 0x00007f and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a28e8; op2val:0xc0548f03;
op3val:0xea80007f; valaddr_reg:x3; val_offset:45951*0 + 3*725*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45951*0 + 3*725*FLEN/8, x4, x1, x2)

inst_15318:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a28e8 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x548f03 and fs3 == 1 and fe3 == 0xd5 and fm3 == 0x0000ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a28e8; op2val:0xc0548f03;
op3val:0xea8000ff; valaddr_reg:x3; val_offset:45954*0 + 3*726*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45954*0 + 3*726*FLEN/8, x4, x1, x2)

inst_15319:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a28e8 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x548f03 and fs3 == 1 and fe3 == 0xd5 and fm3 == 0x0001ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a28e8; op2val:0xc0548f03;
op3val:0xea8001ff; valaddr_reg:x3; val_offset:45957*0 + 3*727*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45957*0 + 3*727*FLEN/8, x4, x1, x2)

inst_15320:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a28e8 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x548f03 and fs3 == 1 and fe3 == 0xd5 and fm3 == 0x0003ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a28e8; op2val:0xc0548f03;
op3val:0xea8003ff; valaddr_reg:x3; val_offset:45960*0 + 3*728*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45960*0 + 3*728*FLEN/8, x4, x1, x2)

inst_15321:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a28e8 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x548f03 and fs3 == 1 and fe3 == 0xd5 and fm3 == 0x0007ff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a28e8; op2val:0xc0548f03;
op3val:0xea8007ff; valaddr_reg:x3; val_offset:45963*0 + 3*729*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45963*0 + 3*729*FLEN/8, x4, x1, x2)

inst_15322:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a28e8 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x548f03 and fs3 == 1 and fe3 == 0xd5 and fm3 == 0x000fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a28e8; op2val:0xc0548f03;
op3val:0xea800fff; valaddr_reg:x3; val_offset:45966*0 + 3*730*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45966*0 + 3*730*FLEN/8, x4, x1, x2)

inst_15323:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a28e8 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x548f03 and fs3 == 1 and fe3 == 0xd5 and fm3 == 0x001fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a28e8; op2val:0xc0548f03;
op3val:0xea801fff; valaddr_reg:x3; val_offset:45969*0 + 3*731*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45969*0 + 3*731*FLEN/8, x4, x1, x2)

inst_15324:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a28e8 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x548f03 and fs3 == 1 and fe3 == 0xd5 and fm3 == 0x003fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a28e8; op2val:0xc0548f03;
op3val:0xea803fff; valaddr_reg:x3; val_offset:45972*0 + 3*732*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45972*0 + 3*732*FLEN/8, x4, x1, x2)

inst_15325:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a28e8 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x548f03 and fs3 == 1 and fe3 == 0xd5 and fm3 == 0x007fff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a28e8; op2val:0xc0548f03;
op3val:0xea807fff; valaddr_reg:x3; val_offset:45975*0 + 3*733*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45975*0 + 3*733*FLEN/8, x4, x1, x2)

inst_15326:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a28e8 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x548f03 and fs3 == 1 and fe3 == 0xd5 and fm3 == 0x00ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a28e8; op2val:0xc0548f03;
op3val:0xea80ffff; valaddr_reg:x3; val_offset:45978*0 + 3*734*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45978*0 + 3*734*FLEN/8, x4, x1, x2)

inst_15327:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a28e8 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x548f03 and fs3 == 1 and fe3 == 0xd5 and fm3 == 0x01ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a28e8; op2val:0xc0548f03;
op3val:0xea81ffff; valaddr_reg:x3; val_offset:45981*0 + 3*735*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45981*0 + 3*735*FLEN/8, x4, x1, x2)

inst_15328:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a28e8 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x548f03 and fs3 == 1 and fe3 == 0xd5 and fm3 == 0x03ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a28e8; op2val:0xc0548f03;
op3val:0xea83ffff; valaddr_reg:x3; val_offset:45984*0 + 3*736*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45984*0 + 3*736*FLEN/8, x4, x1, x2)

inst_15329:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a28e8 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x548f03 and fs3 == 1 and fe3 == 0xd5 and fm3 == 0x07ffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a28e8; op2val:0xc0548f03;
op3val:0xea87ffff; valaddr_reg:x3; val_offset:45987*0 + 3*737*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45987*0 + 3*737*FLEN/8, x4, x1, x2)

inst_15330:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a28e8 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x548f03 and fs3 == 1 and fe3 == 0xd5 and fm3 == 0x0fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a28e8; op2val:0xc0548f03;
op3val:0xea8fffff; valaddr_reg:x3; val_offset:45990*0 + 3*738*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45990*0 + 3*738*FLEN/8, x4, x1, x2)

inst_15331:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a28e8 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x548f03 and fs3 == 1 and fe3 == 0xd5 and fm3 == 0x1fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a28e8; op2val:0xc0548f03;
op3val:0xea9fffff; valaddr_reg:x3; val_offset:45993*0 + 3*739*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45993*0 + 3*739*FLEN/8, x4, x1, x2)

inst_15332:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a28e8 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x548f03 and fs3 == 1 and fe3 == 0xd5 and fm3 == 0x3fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a28e8; op2val:0xc0548f03;
op3val:0xeabfffff; valaddr_reg:x3; val_offset:45996*0 + 3*740*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45996*0 + 3*740*FLEN/8, x4, x1, x2)

inst_15333:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a28e8 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x548f03 and fs3 == 1 and fe3 == 0xd5 and fm3 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a28e8; op2val:0xc0548f03;
op3val:0xeac00000; valaddr_reg:x3; val_offset:45999*0 + 3*741*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 45999*0 + 3*741*FLEN/8, x4, x1, x2)

inst_15334:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a28e8 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x548f03 and fs3 == 1 and fe3 == 0xd5 and fm3 == 0x600000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a28e8; op2val:0xc0548f03;
op3val:0xeae00000; valaddr_reg:x3; val_offset:46002*0 + 3*742*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46002*0 + 3*742*FLEN/8, x4, x1, x2)

inst_15335:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a28e8 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x548f03 and fs3 == 1 and fe3 == 0xd5 and fm3 == 0x700000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a28e8; op2val:0xc0548f03;
op3val:0xeaf00000; valaddr_reg:x3; val_offset:46005*0 + 3*743*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46005*0 + 3*743*FLEN/8, x4, x1, x2)

inst_15336:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a28e8 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x548f03 and fs3 == 1 and fe3 == 0xd5 and fm3 == 0x780000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a28e8; op2val:0xc0548f03;
op3val:0xeaf80000; valaddr_reg:x3; val_offset:46008*0 + 3*744*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46008*0 + 3*744*FLEN/8, x4, x1, x2)

inst_15337:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a28e8 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x548f03 and fs3 == 1 and fe3 == 0xd5 and fm3 == 0x7c0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a28e8; op2val:0xc0548f03;
op3val:0xeafc0000; valaddr_reg:x3; val_offset:46011*0 + 3*745*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46011*0 + 3*745*FLEN/8, x4, x1, x2)

inst_15338:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a28e8 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x548f03 and fs3 == 1 and fe3 == 0xd5 and fm3 == 0x7e0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a28e8; op2val:0xc0548f03;
op3val:0xeafe0000; valaddr_reg:x3; val_offset:46014*0 + 3*746*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46014*0 + 3*746*FLEN/8, x4, x1, x2)

inst_15339:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a28e8 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x548f03 and fs3 == 1 and fe3 == 0xd5 and fm3 == 0x7f0000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a28e8; op2val:0xc0548f03;
op3val:0xeaff0000; valaddr_reg:x3; val_offset:46017*0 + 3*747*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46017*0 + 3*747*FLEN/8, x4, x1, x2)

inst_15340:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a28e8 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x548f03 and fs3 == 1 and fe3 == 0xd5 and fm3 == 0x7f8000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a28e8; op2val:0xc0548f03;
op3val:0xeaff8000; valaddr_reg:x3; val_offset:46020*0 + 3*748*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46020*0 + 3*748*FLEN/8, x4, x1, x2)

inst_15341:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a28e8 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x548f03 and fs3 == 1 and fe3 == 0xd5 and fm3 == 0x7fc000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a28e8; op2val:0xc0548f03;
op3val:0xeaffc000; valaddr_reg:x3; val_offset:46023*0 + 3*749*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46023*0 + 3*749*FLEN/8, x4, x1, x2)

inst_15342:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a28e8 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x548f03 and fs3 == 1 and fe3 == 0xd5 and fm3 == 0x7fe000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a28e8; op2val:0xc0548f03;
op3val:0xeaffe000; valaddr_reg:x3; val_offset:46026*0 + 3*750*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46026*0 + 3*750*FLEN/8, x4, x1, x2)

inst_15343:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a28e8 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x548f03 and fs3 == 1 and fe3 == 0xd5 and fm3 == 0x7ff000 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a28e8; op2val:0xc0548f03;
op3val:0xeafff000; valaddr_reg:x3; val_offset:46029*0 + 3*751*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46029*0 + 3*751*FLEN/8, x4, x1, x2)

inst_15344:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a28e8 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x548f03 and fs3 == 1 and fe3 == 0xd5 and fm3 == 0x7ff800 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a28e8; op2val:0xc0548f03;
op3val:0xeafff800; valaddr_reg:x3; val_offset:46032*0 + 3*752*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46032*0 + 3*752*FLEN/8, x4, x1, x2)

inst_15345:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a28e8 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x548f03 and fs3 == 1 and fe3 == 0xd5 and fm3 == 0x7ffc00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a28e8; op2val:0xc0548f03;
op3val:0xeafffc00; valaddr_reg:x3; val_offset:46035*0 + 3*753*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46035*0 + 3*753*FLEN/8, x4, x1, x2)

inst_15346:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a28e8 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x548f03 and fs3 == 1 and fe3 == 0xd5 and fm3 == 0x7ffe00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a28e8; op2val:0xc0548f03;
op3val:0xeafffe00; valaddr_reg:x3; val_offset:46038*0 + 3*754*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46038*0 + 3*754*FLEN/8, x4, x1, x2)

inst_15347:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a28e8 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x548f03 and fs3 == 1 and fe3 == 0xd5 and fm3 == 0x7fff00 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a28e8; op2val:0xc0548f03;
op3val:0xeaffff00; valaddr_reg:x3; val_offset:46041*0 + 3*755*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46041*0 + 3*755*FLEN/8, x4, x1, x2)

inst_15348:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a28e8 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x548f03 and fs3 == 1 and fe3 == 0xd5 and fm3 == 0x7fff80 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a28e8; op2val:0xc0548f03;
op3val:0xeaffff80; valaddr_reg:x3; val_offset:46044*0 + 3*756*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46044*0 + 3*756*FLEN/8, x4, x1, x2)

inst_15349:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a28e8 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x548f03 and fs3 == 1 and fe3 == 0xd5 and fm3 == 0x7fffc0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a28e8; op2val:0xc0548f03;
op3val:0xeaffffc0; valaddr_reg:x3; val_offset:46047*0 + 3*757*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46047*0 + 3*757*FLEN/8, x4, x1, x2)

inst_15350:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a28e8 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x548f03 and fs3 == 1 and fe3 == 0xd5 and fm3 == 0x7fffe0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a28e8; op2val:0xc0548f03;
op3val:0xeaffffe0; valaddr_reg:x3; val_offset:46050*0 + 3*758*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46050*0 + 3*758*FLEN/8, x4, x1, x2)

inst_15351:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a28e8 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x548f03 and fs3 == 1 and fe3 == 0xd5 and fm3 == 0x7ffff0 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a28e8; op2val:0xc0548f03;
op3val:0xeafffff0; valaddr_reg:x3; val_offset:46053*0 + 3*759*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46053*0 + 3*759*FLEN/8, x4, x1, x2)

inst_15352:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a28e8 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x548f03 and fs3 == 1 and fe3 == 0xd5 and fm3 == 0x7ffff8 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a28e8; op2val:0xc0548f03;
op3val:0xeafffff8; valaddr_reg:x3; val_offset:46056*0 + 3*760*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46056*0 + 3*760*FLEN/8, x4, x1, x2)

inst_15353:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a28e8 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x548f03 and fs3 == 1 and fe3 == 0xd5 and fm3 == 0x7ffffc and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a28e8; op2val:0xc0548f03;
op3val:0xeafffffc; valaddr_reg:x3; val_offset:46059*0 + 3*761*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46059*0 + 3*761*FLEN/8, x4, x1, x2)

inst_15354:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a28e8 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x548f03 and fs3 == 1 and fe3 == 0xd5 and fm3 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a28e8; op2val:0xc0548f03;
op3val:0xeafffffe; valaddr_reg:x3; val_offset:46062*0 + 3*762*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46062*0 + 3*762*FLEN/8, x4, x1, x2)

inst_15355:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a28e8 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x548f03 and fs3 == 1 and fe3 == 0xd5 and fm3 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a28e8; op2val:0xc0548f03;
op3val:0xeaffffff; valaddr_reg:x3; val_offset:46065*0 + 3*763*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46065*0 + 3*763*FLEN/8, x4, x1, x2)

inst_15356:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a28e8 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x548f03 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a28e8; op2val:0xc0548f03;
op3val:0xff000001; valaddr_reg:x3; val_offset:46068*0 + 3*764*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46068*0 + 3*764*FLEN/8, x4, x1, x2)

inst_15357:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a28e8 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x548f03 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x000003 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a28e8; op2val:0xc0548f03;
op3val:0xff000003; valaddr_reg:x3; val_offset:46071*0 + 3*765*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46071*0 + 3*765*FLEN/8, x4, x1, x2)

inst_15358:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a28e8 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x548f03 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x000007 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a28e8; op2val:0xc0548f03;
op3val:0xff000007; valaddr_reg:x3; val_offset:46074*0 + 3*766*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46074*0 + 3*766*FLEN/8, x4, x1, x2)

inst_15359:
// fs1 == 0 and fe1 == 0xfd and fm1 == 0x1a28e8 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x548f03 and fs3 == 1 and fe3 == 0xfe and fm3 == 0x199999 and  fcsr == 0x0 and rm_val == 7   
/* opcode: fnmsub.s ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7e9a28e8; op2val:0xc0548f03;
op3val:0xff199999; valaddr_reg:x3; val_offset:46077*0 + 3*767*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.s, f31, f30, f29, f28, dyn, 0, 0, x3, 46077*0 + 3*767*FLEN/8, x4, x1, x2)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0x7e9337c1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d8003ff,32,FLEN)
NAN_BOXED(0x7e9337c1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d8007ff,32,FLEN)
NAN_BOXED(0x7e9337c1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d800fff,32,FLEN)
NAN_BOXED(0x7e9337c1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d801fff,32,FLEN)
NAN_BOXED(0x7e9337c1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d803fff,32,FLEN)
NAN_BOXED(0x7e9337c1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d807fff,32,FLEN)
NAN_BOXED(0x7e9337c1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d80ffff,32,FLEN)
NAN_BOXED(0x7e9337c1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d81ffff,32,FLEN)
NAN_BOXED(0x7e9337c1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d83ffff,32,FLEN)
NAN_BOXED(0x7e9337c1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d87ffff,32,FLEN)
NAN_BOXED(0x7e9337c1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d8fffff,32,FLEN)
NAN_BOXED(0x7e9337c1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d9fffff,32,FLEN)
NAN_BOXED(0x7e9337c1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8dbfffff,32,FLEN)
NAN_BOXED(0x7e9337c1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8dc00000,32,FLEN)
NAN_BOXED(0x7e9337c1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8de00000,32,FLEN)
NAN_BOXED(0x7e9337c1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8df00000,32,FLEN)
NAN_BOXED(0x7e9337c1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8df80000,32,FLEN)
NAN_BOXED(0x7e9337c1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8dfc0000,32,FLEN)
NAN_BOXED(0x7e9337c1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8dfe0000,32,FLEN)
NAN_BOXED(0x7e9337c1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8dff0000,32,FLEN)
NAN_BOXED(0x7e9337c1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8dff8000,32,FLEN)
NAN_BOXED(0x7e9337c1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8dffc000,32,FLEN)
NAN_BOXED(0x7e9337c1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8dffe000,32,FLEN)
NAN_BOXED(0x7e9337c1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8dfff000,32,FLEN)
NAN_BOXED(0x7e9337c1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8dfff800,32,FLEN)
NAN_BOXED(0x7e9337c1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8dfffc00,32,FLEN)
NAN_BOXED(0x7e9337c1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8dfffe00,32,FLEN)
NAN_BOXED(0x7e9337c1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8dffff00,32,FLEN)
NAN_BOXED(0x7e9337c1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8dffff80,32,FLEN)
NAN_BOXED(0x7e9337c1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8dffffc0,32,FLEN)
NAN_BOXED(0x7e9337c1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8dffffe0,32,FLEN)
NAN_BOXED(0x7e9337c1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8dfffff0,32,FLEN)
NAN_BOXED(0x7e9337c1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8dfffff8,32,FLEN)
NAN_BOXED(0x7e9337c1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8dfffffc,32,FLEN)
NAN_BOXED(0x7e9337c1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8dfffffe,32,FLEN)
NAN_BOXED(0x7e9337c1,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8dffffff,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000001,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000003,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000007,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80199999,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80249249,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80333333,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8036db6d,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x803bbbbb,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80444444,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x804ccccc,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x805b6db6,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80666666,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x806db6db,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffff8,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffc,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffe,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83800000,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83800001,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83800003,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83800007,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8380000f,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8380001f,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8380003f,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8380007f,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x838000ff,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x838001ff,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x838003ff,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x838007ff,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83800fff,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83801fff,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83803fff,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83807fff,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8380ffff,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8381ffff,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8383ffff,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8387ffff,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x838fffff,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x839fffff,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83bfffff,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83c00000,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83e00000,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83f00000,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83f80000,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83fc0000,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83fe0000,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83ff0000,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83ff8000,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83ffc000,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83ffe000,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83fff000,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83fff800,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83fffc00,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83fffe00,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83ffff00,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83ffff80,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83ffffc0,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83ffffe0,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83fffff0,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83fffff8,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83fffffc,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83fffffe,32,FLEN)
NAN_BOXED(0x7e942c31,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x83ffffff,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x199999,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x249249,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x333333,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x36db6d,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3bbbbb,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x444444,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4ccccc,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5b6db6,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x666666,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6db6db,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffff8,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffc,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffe,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd800000,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd800001,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd800003,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd800007,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd80000f,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd80001f,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd80003f,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd80007f,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd8000ff,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd8001ff,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd8003ff,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd8007ff,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd800fff,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd801fff,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd803fff,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd807fff,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd80ffff,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd81ffff,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd83ffff,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd87ffff,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd8fffff,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xd9fffff,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xdbfffff,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xdc00000,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xde00000,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xdf00000,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xdf80000,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xdfc0000,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xdfe0000,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xdff0000,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xdff8000,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xdffc000,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xdffe000,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xdfff000,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xdfff800,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xdfffc00,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xdfffe00,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xdffff00,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xdffff80,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xdffffc0,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xdffffe0,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xdfffff0,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xdfffff8,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xdfffffc,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xdfffffe,32,FLEN)
NAN_BOXED(0x7e94d779,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xdffffff,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x199999,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x249249,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x333333,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x36db6d,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3bbbbb,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x444444,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4ccccc,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5b6db6,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x666666,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6db6db,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffff8,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffc,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffe,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe800000,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe800001,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe800003,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe800007,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe80000f,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe80001f,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe80003f,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe80007f,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe8000ff,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe8001ff,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe8003ff,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe8007ff,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe800fff,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe801fff,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe803fff,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe807fff,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe80ffff,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe81ffff,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe83ffff,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe87ffff,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe8fffff,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xe9fffff,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xebfffff,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xec00000,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xee00000,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xef00000,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xef80000,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xefc0000,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xefe0000,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xeff0000,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xeff8000,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xeffc000,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xeffe000,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xefff000,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xefff800,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xefffc00,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xefffe00,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xeffff00,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xeffff80,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xeffffc0,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xeffffe0,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xefffff0,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xefffff8,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xefffffc,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xefffffe,32,FLEN)
NAN_BOXED(0x7e954029,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0xeffffff,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x199999,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x249249,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x333333,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x36db6d,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3bbbbb,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x444444,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4ccccc,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5b6db6,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x666666,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6db6db,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffff8,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffc,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffe,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8000000,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8000001,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8000003,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8000007,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800000f,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800001f,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800003f,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800007f,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x80000ff,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x80001ff,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x80003ff,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x80007ff,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8000fff,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8001fff,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8003fff,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8007fff,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x800ffff,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x801ffff,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x803ffff,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x807ffff,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x80fffff,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x81fffff,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x83fffff,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8400000,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8600000,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8700000,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x8780000,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87c0000,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87e0000,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87f0000,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87f8000,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87fc000,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87fe000,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87ff000,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87ff800,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87ffc00,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87ffe00,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87fff00,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87fff80,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87fffc0,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87fffe0,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87ffff0,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87ffff8,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87ffffc,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87ffffe,32,FLEN)
NAN_BOXED(0x7e95bc56,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x87fffff,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x65000000,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x65000001,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x65000003,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x65000007,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x6500000f,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x6500001f,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x6500003f,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x6500007f,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x650000ff,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x650001ff,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x650003ff,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x650007ff,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x65000fff,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x65001fff,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x65003fff,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x65007fff,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x6500ffff,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x6501ffff,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x6503ffff,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x6507ffff,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x650fffff,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x651fffff,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x653fffff,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x65400000,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x65600000,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x65700000,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x65780000,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x657c0000,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x657e0000,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x657f0000,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x657f8000,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x657fc000,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x657fe000,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x657ff000,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x657ff800,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x657ffc00,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x657ffe00,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x657fff00,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x657fff80,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x657fffc0,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x657fffe0,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x657ffff0,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x657ffff8,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x657ffffc,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x657ffffe,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x657fffff,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x7f000001,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x7f000003,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x7f000007,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x7f199999,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x7f249249,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x7f333333,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x7f36db6d,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x7f3bbbbb,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x7f444444,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x7f4ccccc,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x7f5b6db6,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x7f666666,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x7f6db6db,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x7f7ffff8,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x7f7ffffc,32,FLEN)
NAN_BOXED(0x7e963706,32,FLEN)
NAN_BOXED(0x405a2407,32,FLEN)
NAN_BOXED(0x7f7ffffe,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000001,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000003,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000007,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80199999,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80249249,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80333333,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8036db6d,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x803bbbbb,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80444444,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x804ccccc,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x805b6db6,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80666666,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x806db6db,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffff8,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffc,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffe,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c000000,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c000001,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c000003,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c000007,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c00000f,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c00001f,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c00003f,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c00007f,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c0000ff,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c0001ff,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c0003ff,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c0007ff,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c000fff,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c001fff,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c003fff,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c007fff,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c00ffff,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c01ffff,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c03ffff,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c07ffff,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c0fffff,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c1fffff,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c3fffff,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c400000,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c600000,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c700000,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c780000,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c7c0000,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c7e0000,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c7f0000,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c7f8000,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c7fc000,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c7fe000,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c7ff000,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c7ff800,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c7ffc00,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c7ffe00,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c7fff00,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c7fff80,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c7fffc0,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c7fffe0,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c7ffff0,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c7ffff8,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c7ffffc,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c7ffffe,32,FLEN)
NAN_BOXED(0x7e97313a,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8c7fffff,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xf9800000,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xf9800001,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xf9800003,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xf9800007,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xf980000f,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xf980001f,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xf980003f,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xf980007f,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xf98000ff,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xf98001ff,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xf98003ff,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xf98007ff,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xf9800fff,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xf9801fff,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xf9803fff,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xf9807fff,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xf980ffff,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xf981ffff,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xf983ffff,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xf987ffff,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xf98fffff,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xf99fffff,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xf9bfffff,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xf9c00000,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xf9e00000,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xf9f00000,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xf9f80000,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xf9fc0000,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xf9fe0000,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xf9ff0000,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xf9ff8000,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xf9ffc000,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xf9ffe000,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xf9fff000,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xf9fff800,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xf9fffc00,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xf9fffe00,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xf9ffff00,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xf9ffff80,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xf9ffffc0,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xf9ffffe0,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xf9fffff0,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xf9fffff8,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xf9fffffc,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xf9fffffe,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xf9ffffff,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xff000001,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xff000003,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xff000007,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xff199999,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xff249249,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xff333333,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xff36db6d,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xff3bbbbb,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xff444444,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xff4ccccc,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xff5b6db6,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xff666666,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xff6db6db,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xff7ffff8,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xff7ffffc,32,FLEN)
NAN_BOXED(0x7e984c3b,32,FLEN)
NAN_BOXED(0xc057284c,32,FLEN)
NAN_BOXED(0xff7ffffe,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000001,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000003,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000007,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80199999,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80249249,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80333333,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8036db6d,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x803bbbbb,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80444444,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x804ccccc,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x805b6db6,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80666666,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x806db6db,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffff8,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffc,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffe,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d000000,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d000001,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d000003,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d000007,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d00000f,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d00001f,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d00003f,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d00007f,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d0000ff,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d0001ff,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d0003ff,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d0007ff,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d000fff,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d001fff,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d003fff,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d007fff,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d00ffff,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d01ffff,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d03ffff,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d07ffff,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d0fffff,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d1fffff,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d3fffff,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d400000,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d600000,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d700000,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d780000,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d7c0000,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d7e0000,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d7f0000,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d7f8000,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d7fc000,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d7fe000,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d7ff000,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d7ff800,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d7ffc00,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d7ffe00,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d7fff00,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d7fff80,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d7fffc0,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d7fffe0,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d7ffff0,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d7ffff8,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d7ffffc,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d7ffffe,32,FLEN)
NAN_BOXED(0x7e984f43,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8d7fffff,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x199999,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x249249,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x333333,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x36db6d,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3bbbbb,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x444444,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4ccccc,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5b6db6,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x666666,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6db6db,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffff8,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffc,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffe,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5800000,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5800001,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5800003,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5800007,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x580000f,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x580001f,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x580003f,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x580007f,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x58000ff,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x58001ff,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x58003ff,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x58007ff,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5800fff,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5801fff,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5803fff,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5807fff,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x580ffff,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x581ffff,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x583ffff,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x587ffff,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x58fffff,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x59fffff,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5bfffff,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5c00000,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5e00000,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5f00000,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5f80000,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5fc0000,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5fe0000,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5ff0000,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5ff8000,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5ffc000,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5ffe000,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5fff000,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5fff800,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5fffc00,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5fffe00,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5ffff00,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5ffff80,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5ffffc0,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5ffffe0,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5fffff0,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5fffff8,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5fffffc,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5fffffe,32,FLEN)
NAN_BOXED(0x7e987fea,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5ffffff,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000001,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000003,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80000007,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80199999,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80249249,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80333333,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8036db6d,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x803bbbbb,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80444444,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x804ccccc,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x805b6db6,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x80666666,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x806db6db,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffff8,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffc,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x807ffffe,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x85800000,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x85800001,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x85800003,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x85800007,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8580000f,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8580001f,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8580003f,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8580007f,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x858000ff,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x858001ff,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x858003ff,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x858007ff,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x85800fff,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x85801fff,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x85803fff,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x85807fff,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8580ffff,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8581ffff,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8583ffff,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x8587ffff,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x858fffff,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x859fffff,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x85bfffff,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x85c00000,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x85e00000,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x85f00000,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x85f80000,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x85fc0000,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x85fe0000,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x85ff0000,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x85ff8000,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x85ffc000,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x85ffe000,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x85fff000,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x85fff800,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x85fffc00,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x85fffe00,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x85ffff00,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x85ffff80,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x85ffffc0,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x85ffffe0,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x85fffff0,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x85fffff8,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x85fffffc,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x85fffffe,32,FLEN)
NAN_BOXED(0x7e99b362,32,FLEN)
NAN_BOXED(0x80000000,32,FLEN)
NAN_BOXED(0x85ffffff,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x1,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x199999,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x249249,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x333333,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x36db6d,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x3bbbbb,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x444444,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x4ccccc,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x5b6db6,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x666666,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x6db6db,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffff8,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffc,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x7ffffe,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2800000,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2800001,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2800003,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2800007,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x280000f,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x280001f,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x280003f,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x280007f,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x28000ff,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x28001ff,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x28003ff,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x28007ff,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2800fff,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2801fff,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2803fff,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2807fff,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x280ffff,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x281ffff,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x283ffff,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x287ffff,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x28fffff,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x29fffff,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2bfffff,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2c00000,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2e00000,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2f00000,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2f80000,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2fc0000,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2fe0000,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2ff0000,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2ff8000,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2ffc000,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2ffe000,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2fff000,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2fff800,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2fffc00,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2fffe00,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2ffff00,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2ffff80,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2ffffc0,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2ffffe0,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2fffff0,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2fffff8,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2fffffc,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2fffffe,32,FLEN)
NAN_BOXED(0x7e9a0102,32,FLEN)
NAN_BOXED(0x0,32,FLEN)
NAN_BOXED(0x2ffffff,32,FLEN)
NAN_BOXED(0x7e9a28e8,32,FLEN)
NAN_BOXED(0xc0548f03,32,FLEN)
NAN_BOXED(0xea800000,32,FLEN)
NAN_BOXED(0x7e9a28e8,32,FLEN)
NAN_BOXED(0xc0548f03,32,FLEN)
NAN_BOXED(0xea800001,32,FLEN)
NAN_BOXED(0x7e9a28e8,32,FLEN)
NAN_BOXED(0xc0548f03,32,FLEN)
NAN_BOXED(0xea800003,32,FLEN)
NAN_BOXED(0x7e9a28e8,32,FLEN)
NAN_BOXED(0xc0548f03,32,FLEN)
NAN_BOXED(0xea800007,32,FLEN)
NAN_BOXED(0x7e9a28e8,32,FLEN)
NAN_BOXED(0xc0548f03,32,FLEN)
NAN_BOXED(0xea80000f,32,FLEN)
NAN_BOXED(0x7e9a28e8,32,FLEN)
NAN_BOXED(0xc0548f03,32,FLEN)
NAN_BOXED(0xea80001f,32,FLEN)
NAN_BOXED(0x7e9a28e8,32,FLEN)
NAN_BOXED(0xc0548f03,32,FLEN)
NAN_BOXED(0xea80003f,32,FLEN)
NAN_BOXED(0x7e9a28e8,32,FLEN)
NAN_BOXED(0xc0548f03,32,FLEN)
NAN_BOXED(0xea80007f,32,FLEN)
NAN_BOXED(0x7e9a28e8,32,FLEN)
NAN_BOXED(0xc0548f03,32,FLEN)
NAN_BOXED(0xea8000ff,32,FLEN)
NAN_BOXED(0x7e9a28e8,32,FLEN)
NAN_BOXED(0xc0548f03,32,FLEN)
NAN_BOXED(0xea8001ff,32,FLEN)
NAN_BOXED(0x7e9a28e8,32,FLEN)
NAN_BOXED(0xc0548f03,32,FLEN)
NAN_BOXED(0xea8003ff,32,FLEN)
NAN_BOXED(0x7e9a28e8,32,FLEN)
NAN_BOXED(0xc0548f03,32,FLEN)
NAN_BOXED(0xea8007ff,32,FLEN)
NAN_BOXED(0x7e9a28e8,32,FLEN)
NAN_BOXED(0xc0548f03,32,FLEN)
NAN_BOXED(0xea800fff,32,FLEN)
NAN_BOXED(0x7e9a28e8,32,FLEN)
NAN_BOXED(0xc0548f03,32,FLEN)
NAN_BOXED(0xea801fff,32,FLEN)
NAN_BOXED(0x7e9a28e8,32,FLEN)
NAN_BOXED(0xc0548f03,32,FLEN)
NAN_BOXED(0xea803fff,32,FLEN)
NAN_BOXED(0x7e9a28e8,32,FLEN)
NAN_BOXED(0xc0548f03,32,FLEN)
NAN_BOXED(0xea807fff,32,FLEN)
NAN_BOXED(0x7e9a28e8,32,FLEN)
NAN_BOXED(0xc0548f03,32,FLEN)
NAN_BOXED(0xea80ffff,32,FLEN)
NAN_BOXED(0x7e9a28e8,32,FLEN)
NAN_BOXED(0xc0548f03,32,FLEN)
NAN_BOXED(0xea81ffff,32,FLEN)
NAN_BOXED(0x7e9a28e8,32,FLEN)
NAN_BOXED(0xc0548f03,32,FLEN)
NAN_BOXED(0xea83ffff,32,FLEN)
NAN_BOXED(0x7e9a28e8,32,FLEN)
NAN_BOXED(0xc0548f03,32,FLEN)
NAN_BOXED(0xea87ffff,32,FLEN)
NAN_BOXED(0x7e9a28e8,32,FLEN)
NAN_BOXED(0xc0548f03,32,FLEN)
NAN_BOXED(0xea8fffff,32,FLEN)
NAN_BOXED(0x7e9a28e8,32,FLEN)
NAN_BOXED(0xc0548f03,32,FLEN)
NAN_BOXED(0xea9fffff,32,FLEN)
NAN_BOXED(0x7e9a28e8,32,FLEN)
NAN_BOXED(0xc0548f03,32,FLEN)
NAN_BOXED(0xeabfffff,32,FLEN)
NAN_BOXED(0x7e9a28e8,32,FLEN)
NAN_BOXED(0xc0548f03,32,FLEN)
NAN_BOXED(0xeac00000,32,FLEN)
NAN_BOXED(0x7e9a28e8,32,FLEN)
NAN_BOXED(0xc0548f03,32,FLEN)
NAN_BOXED(0xeae00000,32,FLEN)
NAN_BOXED(0x7e9a28e8,32,FLEN)
NAN_BOXED(0xc0548f03,32,FLEN)
NAN_BOXED(0xeaf00000,32,FLEN)
NAN_BOXED(0x7e9a28e8,32,FLEN)
NAN_BOXED(0xc0548f03,32,FLEN)
NAN_BOXED(0xeaf80000,32,FLEN)
NAN_BOXED(0x7e9a28e8,32,FLEN)
NAN_BOXED(0xc0548f03,32,FLEN)
NAN_BOXED(0xeafc0000,32,FLEN)
NAN_BOXED(0x7e9a28e8,32,FLEN)
NAN_BOXED(0xc0548f03,32,FLEN)
NAN_BOXED(0xeafe0000,32,FLEN)
NAN_BOXED(0x7e9a28e8,32,FLEN)
NAN_BOXED(0xc0548f03,32,FLEN)
NAN_BOXED(0xeaff0000,32,FLEN)
NAN_BOXED(0x7e9a28e8,32,FLEN)
NAN_BOXED(0xc0548f03,32,FLEN)
NAN_BOXED(0xeaff8000,32,FLEN)
NAN_BOXED(0x7e9a28e8,32,FLEN)
NAN_BOXED(0xc0548f03,32,FLEN)
NAN_BOXED(0xeaffc000,32,FLEN)
NAN_BOXED(0x7e9a28e8,32,FLEN)
NAN_BOXED(0xc0548f03,32,FLEN)
NAN_BOXED(0xeaffe000,32,FLEN)
NAN_BOXED(0x7e9a28e8,32,FLEN)
NAN_BOXED(0xc0548f03,32,FLEN)
NAN_BOXED(0xeafff000,32,FLEN)
NAN_BOXED(0x7e9a28e8,32,FLEN)
NAN_BOXED(0xc0548f03,32,FLEN)
NAN_BOXED(0xeafff800,32,FLEN)
NAN_BOXED(0x7e9a28e8,32,FLEN)
NAN_BOXED(0xc0548f03,32,FLEN)
NAN_BOXED(0xeafffc00,32,FLEN)
NAN_BOXED(0x7e9a28e8,32,FLEN)
NAN_BOXED(0xc0548f03,32,FLEN)
NAN_BOXED(0xeafffe00,32,FLEN)
NAN_BOXED(0x7e9a28e8,32,FLEN)
NAN_BOXED(0xc0548f03,32,FLEN)
NAN_BOXED(0xeaffff00,32,FLEN)
NAN_BOXED(0x7e9a28e8,32,FLEN)
NAN_BOXED(0xc0548f03,32,FLEN)
NAN_BOXED(0xeaffff80,32,FLEN)
NAN_BOXED(0x7e9a28e8,32,FLEN)
NAN_BOXED(0xc0548f03,32,FLEN)
NAN_BOXED(0xeaffffc0,32,FLEN)
NAN_BOXED(0x7e9a28e8,32,FLEN)
NAN_BOXED(0xc0548f03,32,FLEN)
NAN_BOXED(0xeaffffe0,32,FLEN)
NAN_BOXED(0x7e9a28e8,32,FLEN)
NAN_BOXED(0xc0548f03,32,FLEN)
NAN_BOXED(0xeafffff0,32,FLEN)
NAN_BOXED(0x7e9a28e8,32,FLEN)
NAN_BOXED(0xc0548f03,32,FLEN)
NAN_BOXED(0xeafffff8,32,FLEN)
NAN_BOXED(0x7e9a28e8,32,FLEN)
NAN_BOXED(0xc0548f03,32,FLEN)
NAN_BOXED(0xeafffffc,32,FLEN)
NAN_BOXED(0x7e9a28e8,32,FLEN)
NAN_BOXED(0xc0548f03,32,FLEN)
NAN_BOXED(0xeafffffe,32,FLEN)
NAN_BOXED(0x7e9a28e8,32,FLEN)
NAN_BOXED(0xc0548f03,32,FLEN)
NAN_BOXED(0xeaffffff,32,FLEN)
NAN_BOXED(0x7e9a28e8,32,FLEN)
NAN_BOXED(0xc0548f03,32,FLEN)
NAN_BOXED(0xff000001,32,FLEN)
NAN_BOXED(0x7e9a28e8,32,FLEN)
NAN_BOXED(0xc0548f03,32,FLEN)
NAN_BOXED(0xff000003,32,FLEN)
NAN_BOXED(0x7e9a28e8,32,FLEN)
NAN_BOXED(0xc0548f03,32,FLEN)
NAN_BOXED(0xff000007,32,FLEN)
NAN_BOXED(0x7e9a28e8,32,FLEN)
NAN_BOXED(0xc0548f03,32,FLEN)
NAN_BOXED(0xff199999,32,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;


signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_2:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_3:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_4:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_5:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_6:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine

tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
    .fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;

#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif

sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
