
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.12.2
// timestamp : Wed Sep 25 06:02:02 2024 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/riscv/testing/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zhinx/rv32h_fsub.cgf \
 \
//                  -- xlen 32  \
//                  --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fsub.h instruction of the RISC-V RV32_Zfinx_Zhinx,RV64_Zfinx_Zhinx extension for the fsub_b3 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32I_Zfinx_Zhinx,RV64I_Zfinx_Zhinx")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zfinx.*Zhinx.*);def TEST_CASE_1=True;",fsub_b3)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x9,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_0:
// rs1 == rs2 == rd, rs1==x23, rs2==x23, rd==x23,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x23; op2:x23; dest:x23; op1val:0x704c; op2val:0x704c;
   valaddr_reg:x9; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x4*/
TEST_FPRR_OP(fsub.h, x23, x23, x23, dyn, 0, 0, x9, 0*FLEN/8, x20, x1, x4)

inst_1:
// rs2 == rd != rs1, rs1==x15, rs2==x7, rd==x7,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x15; op2:x7; dest:x7; op1val:0x704c; op2val:0x704c;
   valaddr_reg:x9; val_offset:2*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x4*/
TEST_FPRR_OP(fsub.h, x7, x15, x7, dyn, 32, 0, x9, 2*FLEN/8, x20, x1, x4)

inst_2:
// rs1 == rd != rs2, rs1==x6, rs2==x10, rd==x6,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x6; op2:x10; dest:x6; op1val:0x704c; op2val:0x704c;
   valaddr_reg:x9; val_offset:4*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x4*/
TEST_FPRR_OP(fsub.h, x6, x6, x10, dyn, 64, 0, x9, 4*FLEN/8, x20, x1, x4)

inst_3:
// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==x28, rs2==x2, rd==x29,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x28; op2:x2; dest:x29; op1val:0x704c; op2val:0x704c;
   valaddr_reg:x9; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x4*/
TEST_FPRR_OP(fsub.h, x29, x28, x2, dyn, 96, 0, x9, 6*FLEN/8, x20, x1, x4)

inst_4:
// rs1 == rs2 != rd, rs1==x0, rs2==x0, rd==x17,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x0; op2:x0; dest:x17; op1val:0x0; op2val:0x0;
   valaddr_reg:x9; val_offset:8*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x4*/
TEST_FPRR_OP(fsub.h, x17, x0, x0, dyn, 128, 0, x9, 8*FLEN/8, x20, x1, x4)

inst_5:
// rs1==x31, rs2==x6, rd==x11,fs1 == 0 and fe1 == 0x1e and fm1 == 0x21b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x21b and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x31; op2:x6; dest:x11; op1val:0x7a1b; op2val:0x7a1b;
   valaddr_reg:x9; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x4*/
TEST_FPRR_OP(fsub.h, x11, x31, x6, dyn, 0, 0, x9, 10*FLEN/8, x20, x1, x4)

inst_6:
// rs1==x11, rs2==x12, rd==x30,fs1 == 0 and fe1 == 0x1e and fm1 == 0x21b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x21b and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x11; op2:x12; dest:x30; op1val:0x7a1b; op2val:0x7a1b;
   valaddr_reg:x9; val_offset:12*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x4*/
TEST_FPRR_OP(fsub.h, x30, x11, x12, dyn, 32, 0, x9, 12*FLEN/8, x20, x1, x4)

inst_7:
// rs1==x5, rs2==x8, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x21b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x21b and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x5; op2:x8; dest:x19; op1val:0x7a1b; op2val:0x7a1b;
   valaddr_reg:x9; val_offset:14*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x4*/
TEST_FPRR_OP(fsub.h, x19, x5, x8, dyn, 64, 0, x9, 14*FLEN/8, x20, x1, x4)

inst_8:
// rs1==x18, rs2==x19, rd==x16,fs1 == 0 and fe1 == 0x1e and fm1 == 0x21b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x21b and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x18; op2:x19; dest:x16; op1val:0x7a1b; op2val:0x7a1b;
   valaddr_reg:x9; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x4*/
TEST_FPRR_OP(fsub.h, x16, x18, x19, dyn, 96, 0, x9, 16*FLEN/8, x20, x1, x4)

inst_9:
// rs1==x12, rs2==x24, rd==x10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x21b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x21b and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x12; op2:x24; dest:x10; op1val:0x7a1b; op2val:0x7a1b;
   valaddr_reg:x9; val_offset:18*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x4*/
TEST_FPRR_OP(fsub.h, x10, x12, x24, dyn, 128, 0, x9, 18*FLEN/8, x20, x1, x4)

inst_10:
// rs1==x14, rs2==x26, rd==x3,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x14; op2:x26; dest:x3; op1val:0x77ec; op2val:0x77ec;
   valaddr_reg:x9; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x4*/
TEST_FPRR_OP(fsub.h, x3, x14, x26, dyn, 0, 0, x9, 20*FLEN/8, x20, x1, x4)

inst_11:
// rs1==x13, rs2==x22, rd==x12,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x13; op2:x22; dest:x12; op1val:0x77ec; op2val:0x77ec;
   valaddr_reg:x9; val_offset:22*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x4*/
TEST_FPRR_OP(fsub.h, x12, x13, x22, dyn, 32, 0, x9, 22*FLEN/8, x20, x1, x4)
RVTEST_VALBASEUPD(x5,test_dataset_1)

inst_12:
// rs1==x27, rs2==x9, rd==x22,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x27; op2:x9; dest:x22; op1val:0x77ec; op2val:0x77ec;
   valaddr_reg:x5; val_offset:0*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x4*/
TEST_FPRR_OP(fsub.h, x22, x27, x9, dyn, 64, 0, x5, 0*FLEN/8, x12, x1, x4)
RVTEST_SIGBASE(x6,signature_x6_0)

inst_13:
// rs1==x22, rs2==x13, rd==x20,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x22; op2:x13; dest:x20; op1val:0x77ec; op2val:0x77ec;
   valaddr_reg:x5; val_offset:2*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x10*/
TEST_FPRR_OP(fsub.h, x20, x22, x13, dyn, 96, 0, x5, 2*FLEN/8, x12, x6, x10)

inst_14:
// rs1==x2, rs2==x11, rd==x24,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ec and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3ec and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x2; op2:x11; dest:x24; op1val:0x77ec; op2val:0x77ec;
   valaddr_reg:x5; val_offset:4*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x10*/
TEST_FPRR_OP(fsub.h, x24, x2, x11, dyn, 128, 0, x5, 4*FLEN/8, x12, x6, x10)

inst_15:
// rs1==x16, rs2==x21, rd==x15,fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x135 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x16; op2:x21; dest:x15; op1val:0x7935; op2val:0x7935;
   valaddr_reg:x5; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x10*/
TEST_FPRR_OP(fsub.h, x15, x16, x21, dyn, 0, 0, x5, 6*FLEN/8, x12, x6, x10)

inst_16:
// rs1==x3, rs2==x31, rd==x1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x135 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x3; op2:x31; dest:x1; op1val:0x7935; op2val:0x7935;
   valaddr_reg:x5; val_offset:8*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x10*/
TEST_FPRR_OP(fsub.h, x1, x3, x31, dyn, 32, 0, x5, 8*FLEN/8, x12, x6, x10)

inst_17:
// rs1==x7, rs2==x29, rd==x27,fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x135 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x7; op2:x29; dest:x27; op1val:0x7935; op2val:0x7935;
   valaddr_reg:x5; val_offset:10*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x10*/
TEST_FPRR_OP(fsub.h, x27, x7, x29, dyn, 64, 0, x5, 10*FLEN/8, x12, x6, x10)

inst_18:
// rs1==x21, rs2==x17, rd==x25,fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x135 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x21; op2:x17; dest:x25; op1val:0x7935; op2val:0x7935;
   valaddr_reg:x5; val_offset:12*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x10*/
TEST_FPRR_OP(fsub.h, x25, x21, x17, dyn, 96, 0, x5, 12*FLEN/8, x12, x6, x10)

inst_19:
// rs1==x29, rs2==x16, rd==x28,fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x135 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x29; op2:x16; dest:x28; op1val:0x7935; op2val:0x7935;
   valaddr_reg:x5; val_offset:14*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x10*/
TEST_FPRR_OP(fsub.h, x28, x29, x16, dyn, 128, 0, x5, 14*FLEN/8, x12, x6, x10)

inst_20:
// rs1==x26, rs2==x20, rd==x18,fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x26; op2:x20; dest:x18; op1val:0x6e01; op2val:0x6e01;
   valaddr_reg:x5; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x10*/
TEST_FPRR_OP(fsub.h, x18, x26, x20, dyn, 0, 0, x5, 16*FLEN/8, x12, x6, x10)

inst_21:
// rs1==x1, rs2==x15, rd==x4,fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x1; op2:x15; dest:x4; op1val:0x6e01; op2val:0x6e01;
   valaddr_reg:x5; val_offset:18*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x10*/
TEST_FPRR_OP(fsub.h, x4, x1, x15, dyn, 32, 0, x5, 18*FLEN/8, x12, x6, x10)

inst_22:
// rs1==x20, rs2==x18, rd==x9,fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x20; op2:x18; dest:x9; op1val:0x6e01; op2val:0x6e01;
   valaddr_reg:x5; val_offset:20*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x10*/
TEST_FPRR_OP(fsub.h, x9, x20, x18, dyn, 64, 0, x5, 20*FLEN/8, x12, x6, x10)

inst_23:
// rs1==x25, rs2==x27, rd==x8,fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x25; op2:x27; dest:x8; op1val:0x6e01; op2val:0x6e01;
   valaddr_reg:x5; val_offset:22*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x10*/
TEST_FPRR_OP(fsub.h, x8, x25, x27, dyn, 96, 0, x5, 22*FLEN/8, x12, x6, x10)
RVTEST_VALBASEUPD(x7,test_dataset_2)

inst_24:
// rs1==x4, rs2==x1, rd==x31,fs1 == 0 and fe1 == 0x1b and fm1 == 0x201 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x201 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x4; op2:x1; dest:x31; op1val:0x6e01; op2val:0x6e01;
   valaddr_reg:x7; val_offset:0*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x10*/
TEST_FPRR_OP(fsub.h, x31, x4, x1, dyn, 128, 0, x7, 0*FLEN/8, x11, x6, x10)

inst_25:
// rs1==x30, rs2==x14, rd==x5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x14; dest:x5; op1val:0x7aae; op2val:0x7aae;
   valaddr_reg:x7; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x10*/
TEST_FPRR_OP(fsub.h, x5, x30, x14, dyn, 0, 0, x7, 2*FLEN/8, x11, x6, x10)
RVTEST_SIGBASE(x1,signature_x1_2)

inst_26:
// rs1==x24, rs2==x30, rd==x2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x24; op2:x30; dest:x2; op1val:0x7aae; op2val:0x7aae;
   valaddr_reg:x7; val_offset:4*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x2, x24, x30, dyn, 32, 0, x7, 4*FLEN/8, x11, x1, x6)

inst_27:
// rs1==x8, rs2==x28, rd==x0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x8; op2:x28; dest:x0; op1val:0x7aae; op2val:0x7aae;
   valaddr_reg:x7; val_offset:6*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x0, x8, x28, dyn, 64, 0, x7, 6*FLEN/8, x11, x1, x6)

inst_28:
// rs1==x17, rs2==x3, rd==x26,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x17; op2:x3; dest:x26; op1val:0x7aae; op2val:0x7aae;
   valaddr_reg:x7; val_offset:8*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x26, x17, x3, dyn, 96, 0, x7, 8*FLEN/8, x11, x1, x6)

inst_29:
// rs1==x19, rs2==x25, rd==x13,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x19; op2:x25; dest:x13; op1val:0x7aae; op2val:0x7aae;
   valaddr_reg:x7; val_offset:10*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x13, x19, x25, dyn, 128, 0, x7, 10*FLEN/8, x11, x1, x6)

inst_30:
// rs1==x10, rs2==x4, rd==x21,fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x10; op2:x4; dest:x21; op1val:0x7a18; op2val:0x7a18;
   valaddr_reg:x7; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x21, x10, x4, dyn, 0, 0, x7, 12*FLEN/8, x11, x1, x6)

inst_31:
// rs1==x9, rs2==x5, rd==x14,fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x9; op2:x5; dest:x14; op1val:0x7a18; op2val:0x7a18;
   valaddr_reg:x7; val_offset:14*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x14, x9, x5, dyn, 32, 0, x7, 14*FLEN/8, x11, x1, x6)

inst_32:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a18; op2val:0x7a18;
   valaddr_reg:x7; val_offset:16*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 16*FLEN/8, x11, x1, x6)

inst_33:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a18; op2val:0x7a18;
   valaddr_reg:x7; val_offset:18*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 18*FLEN/8, x11, x1, x6)

inst_34:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x218 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x218 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a18; op2val:0x7a18;
   valaddr_reg:x7; val_offset:20*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 20*FLEN/8, x11, x1, x6)

inst_35:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31f and fs2 == 0 and fe2 == 0x1d and fm2 == 0x31f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x771f; op2val:0x771f;
   valaddr_reg:x7; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 22*FLEN/8, x11, x1, x6)

inst_36:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31f and fs2 == 0 and fe2 == 0x1d and fm2 == 0x31f and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x771f; op2val:0x771f;
   valaddr_reg:x7; val_offset:24*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 24*FLEN/8, x11, x1, x6)

inst_37:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31f and fs2 == 0 and fe2 == 0x1d and fm2 == 0x31f and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x771f; op2val:0x771f;
   valaddr_reg:x7; val_offset:26*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 26*FLEN/8, x11, x1, x6)

inst_38:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31f and fs2 == 0 and fe2 == 0x1d and fm2 == 0x31f and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x771f; op2val:0x771f;
   valaddr_reg:x7; val_offset:28*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 28*FLEN/8, x11, x1, x6)

inst_39:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31f and fs2 == 0 and fe2 == 0x1d and fm2 == 0x31f and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x771f; op2val:0x771f;
   valaddr_reg:x7; val_offset:30*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 30*FLEN/8, x11, x1, x6)

inst_40:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7351; op2val:0x7351;
   valaddr_reg:x7; val_offset:32*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 32*FLEN/8, x11, x1, x6)

inst_41:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7351; op2val:0x7351;
   valaddr_reg:x7; val_offset:34*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 34*FLEN/8, x11, x1, x6)

inst_42:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7351; op2val:0x7351;
   valaddr_reg:x7; val_offset:36*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 36*FLEN/8, x11, x1, x6)

inst_43:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7351; op2val:0x7351;
   valaddr_reg:x7; val_offset:38*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 38*FLEN/8, x11, x1, x6)

inst_44:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x351 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x351 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7351; op2val:0x7351;
   valaddr_reg:x7; val_offset:40*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 40*FLEN/8, x11, x1, x6)

inst_45:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x335 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x335 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b35; op2val:0x7b35;
   valaddr_reg:x7; val_offset:42*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 42*FLEN/8, x11, x1, x6)

inst_46:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x335 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x335 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b35; op2val:0x7b35;
   valaddr_reg:x7; val_offset:44*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 44*FLEN/8, x11, x1, x6)

inst_47:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x335 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x335 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b35; op2val:0x7b35;
   valaddr_reg:x7; val_offset:46*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 46*FLEN/8, x11, x1, x6)

inst_48:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x335 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x335 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b35; op2val:0x7b35;
   valaddr_reg:x7; val_offset:48*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 48*FLEN/8, x11, x1, x6)

inst_49:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x335 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x335 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b35; op2val:0x7b35;
   valaddr_reg:x7; val_offset:50*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 50*FLEN/8, x11, x1, x6)

inst_50:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x283 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x283 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6683; op2val:0x6683;
   valaddr_reg:x7; val_offset:52*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 52*FLEN/8, x11, x1, x6)

inst_51:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x283 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x283 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6683; op2val:0x6683;
   valaddr_reg:x7; val_offset:54*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 54*FLEN/8, x11, x1, x6)

inst_52:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x283 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x283 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6683; op2val:0x6683;
   valaddr_reg:x7; val_offset:56*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 56*FLEN/8, x11, x1, x6)

inst_53:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x283 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x283 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6683; op2val:0x6683;
   valaddr_reg:x7; val_offset:58*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 58*FLEN/8, x11, x1, x6)

inst_54:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x283 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x283 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6683; op2val:0x6683;
   valaddr_reg:x7; val_offset:60*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 60*FLEN/8, x11, x1, x6)

inst_55:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x382 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x382 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b82; op2val:0x7b82;
   valaddr_reg:x7; val_offset:62*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 62*FLEN/8, x11, x1, x6)

inst_56:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x382 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x382 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b82; op2val:0x7b82;
   valaddr_reg:x7; val_offset:64*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 64*FLEN/8, x11, x1, x6)

inst_57:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x382 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x382 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b82; op2val:0x7b82;
   valaddr_reg:x7; val_offset:66*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 66*FLEN/8, x11, x1, x6)

inst_58:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x382 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x382 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b82; op2val:0x7b82;
   valaddr_reg:x7; val_offset:68*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 68*FLEN/8, x11, x1, x6)

inst_59:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x382 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x382 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b82; op2val:0x7b82;
   valaddr_reg:x7; val_offset:70*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 70*FLEN/8, x11, x1, x6)

inst_60:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ed and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2ed and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72ed; op2val:0x72ed;
   valaddr_reg:x7; val_offset:72*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 72*FLEN/8, x11, x1, x6)

inst_61:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ed and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2ed and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72ed; op2val:0x72ed;
   valaddr_reg:x7; val_offset:74*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 74*FLEN/8, x11, x1, x6)

inst_62:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ed and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2ed and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72ed; op2val:0x72ed;
   valaddr_reg:x7; val_offset:76*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 76*FLEN/8, x11, x1, x6)

inst_63:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ed and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2ed and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72ed; op2val:0x72ed;
   valaddr_reg:x7; val_offset:78*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 78*FLEN/8, x11, x1, x6)

inst_64:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ed and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2ed and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72ed; op2val:0x72ed;
   valaddr_reg:x7; val_offset:80*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 80*FLEN/8, x11, x1, x6)

inst_65:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x36f and fs2 == 0 and fe2 == 0x19 and fm2 == 0x36f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x676f; op2val:0x676f;
   valaddr_reg:x7; val_offset:82*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 82*FLEN/8, x11, x1, x6)

inst_66:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x36f and fs2 == 0 and fe2 == 0x19 and fm2 == 0x36f and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x676f; op2val:0x676f;
   valaddr_reg:x7; val_offset:84*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 84*FLEN/8, x11, x1, x6)

inst_67:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x36f and fs2 == 0 and fe2 == 0x19 and fm2 == 0x36f and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x676f; op2val:0x676f;
   valaddr_reg:x7; val_offset:86*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 86*FLEN/8, x11, x1, x6)

inst_68:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x36f and fs2 == 0 and fe2 == 0x19 and fm2 == 0x36f and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x676f; op2val:0x676f;
   valaddr_reg:x7; val_offset:88*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 88*FLEN/8, x11, x1, x6)

inst_69:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x36f and fs2 == 0 and fe2 == 0x19 and fm2 == 0x36f and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x676f; op2val:0x676f;
   valaddr_reg:x7; val_offset:90*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 90*FLEN/8, x11, x1, x6)

inst_70:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x300 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7700; op2val:0x7700;
   valaddr_reg:x7; val_offset:92*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 92*FLEN/8, x11, x1, x6)

inst_71:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x300 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7700; op2val:0x7700;
   valaddr_reg:x7; val_offset:94*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 94*FLEN/8, x11, x1, x6)

inst_72:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x300 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7700; op2val:0x7700;
   valaddr_reg:x7; val_offset:96*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 96*FLEN/8, x11, x1, x6)

inst_73:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x300 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7700; op2val:0x7700;
   valaddr_reg:x7; val_offset:98*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 98*FLEN/8, x11, x1, x6)

inst_74:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x300 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x300 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7700; op2val:0x7700;
   valaddr_reg:x7; val_offset:100*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 100*FLEN/8, x11, x1, x6)

inst_75:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x374 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x374 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7374; op2val:0x7374;
   valaddr_reg:x7; val_offset:102*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 102*FLEN/8, x11, x1, x6)

inst_76:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x374 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x374 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7374; op2val:0x7374;
   valaddr_reg:x7; val_offset:104*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 104*FLEN/8, x11, x1, x6)

inst_77:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x374 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x374 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7374; op2val:0x7374;
   valaddr_reg:x7; val_offset:106*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 106*FLEN/8, x11, x1, x6)

inst_78:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x374 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x374 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7374; op2val:0x7374;
   valaddr_reg:x7; val_offset:108*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 108*FLEN/8, x11, x1, x6)

inst_79:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x374 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x374 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7374; op2val:0x7374;
   valaddr_reg:x7; val_offset:110*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 110*FLEN/8, x11, x1, x6)

inst_80:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2ff and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72ff; op2val:0x72ff;
   valaddr_reg:x7; val_offset:112*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 112*FLEN/8, x11, x1, x6)

inst_81:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2ff and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72ff; op2val:0x72ff;
   valaddr_reg:x7; val_offset:114*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 114*FLEN/8, x11, x1, x6)

inst_82:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2ff and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72ff; op2val:0x72ff;
   valaddr_reg:x7; val_offset:116*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 116*FLEN/8, x11, x1, x6)

inst_83:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2ff and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72ff; op2val:0x72ff;
   valaddr_reg:x7; val_offset:118*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 118*FLEN/8, x11, x1, x6)

inst_84:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2ff and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2ff and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72ff; op2val:0x72ff;
   valaddr_reg:x7; val_offset:120*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 120*FLEN/8, x11, x1, x6)

inst_85:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0a2 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74a2; op2val:0x74a2;
   valaddr_reg:x7; val_offset:122*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 122*FLEN/8, x11, x1, x6)

inst_86:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0a2 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74a2; op2val:0x74a2;
   valaddr_reg:x7; val_offset:124*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 124*FLEN/8, x11, x1, x6)

inst_87:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0a2 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74a2; op2val:0x74a2;
   valaddr_reg:x7; val_offset:126*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 126*FLEN/8, x11, x1, x6)

inst_88:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0a2 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74a2; op2val:0x74a2;
   valaddr_reg:x7; val_offset:128*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 128*FLEN/8, x11, x1, x6)

inst_89:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a2 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0a2 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74a2; op2val:0x74a2;
   valaddr_reg:x7; val_offset:130*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 130*FLEN/8, x11, x1, x6)

inst_90:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b2 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab2; op2val:0x7ab2;
   valaddr_reg:x7; val_offset:132*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 132*FLEN/8, x11, x1, x6)

inst_91:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b2 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab2; op2val:0x7ab2;
   valaddr_reg:x7; val_offset:134*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 134*FLEN/8, x11, x1, x6)

inst_92:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b2 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab2; op2val:0x7ab2;
   valaddr_reg:x7; val_offset:136*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 136*FLEN/8, x11, x1, x6)

inst_93:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b2 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab2; op2val:0x7ab2;
   valaddr_reg:x7; val_offset:138*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 138*FLEN/8, x11, x1, x6)

inst_94:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b2 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab2; op2val:0x7ab2;
   valaddr_reg:x7; val_offset:140*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 140*FLEN/8, x11, x1, x6)

inst_95:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x122 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x122 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7922; op2val:0x7922;
   valaddr_reg:x7; val_offset:142*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 142*FLEN/8, x11, x1, x6)

inst_96:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x122 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x122 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7922; op2val:0x7922;
   valaddr_reg:x7; val_offset:144*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 144*FLEN/8, x11, x1, x6)

inst_97:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x122 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x122 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7922; op2val:0x7922;
   valaddr_reg:x7; val_offset:146*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 146*FLEN/8, x11, x1, x6)

inst_98:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x122 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x122 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7922; op2val:0x7922;
   valaddr_reg:x7; val_offset:148*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 148*FLEN/8, x11, x1, x6)

inst_99:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x122 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x122 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7922; op2val:0x7922;
   valaddr_reg:x7; val_offset:150*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 150*FLEN/8, x11, x1, x6)

inst_100:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ef and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ef and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bef; op2val:0x7bef;
   valaddr_reg:x7; val_offset:152*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 152*FLEN/8, x11, x1, x6)

inst_101:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ef and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ef and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bef; op2val:0x7bef;
   valaddr_reg:x7; val_offset:154*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 154*FLEN/8, x11, x1, x6)

inst_102:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ef and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ef and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bef; op2val:0x7bef;
   valaddr_reg:x7; val_offset:156*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 156*FLEN/8, x11, x1, x6)

inst_103:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ef and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ef and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bef; op2val:0x7bef;
   valaddr_reg:x7; val_offset:158*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 158*FLEN/8, x11, x1, x6)

inst_104:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ef and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ef and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bef; op2val:0x7bef;
   valaddr_reg:x7; val_offset:160*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 160*FLEN/8, x11, x1, x6)

inst_105:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3bb and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3bb and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fbb; op2val:0x6fbb;
   valaddr_reg:x7; val_offset:162*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 162*FLEN/8, x11, x1, x6)

inst_106:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3bb and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3bb and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fbb; op2val:0x6fbb;
   valaddr_reg:x7; val_offset:164*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 164*FLEN/8, x11, x1, x6)

inst_107:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3bb and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3bb and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fbb; op2val:0x6fbb;
   valaddr_reg:x7; val_offset:166*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 166*FLEN/8, x11, x1, x6)

inst_108:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3bb and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3bb and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fbb; op2val:0x6fbb;
   valaddr_reg:x7; val_offset:168*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 168*FLEN/8, x11, x1, x6)

inst_109:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3bb and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3bb and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6fbb; op2val:0x6fbb;
   valaddr_reg:x7; val_offset:170*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 170*FLEN/8, x11, x1, x6)

inst_110:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1c4 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c4; op2val:0x79c4;
   valaddr_reg:x7; val_offset:172*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 172*FLEN/8, x11, x1, x6)

inst_111:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1c4 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c4; op2val:0x79c4;
   valaddr_reg:x7; val_offset:174*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 174*FLEN/8, x11, x1, x6)

inst_112:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1c4 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c4; op2val:0x79c4;
   valaddr_reg:x7; val_offset:176*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 176*FLEN/8, x11, x1, x6)

inst_113:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1c4 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c4; op2val:0x79c4;
   valaddr_reg:x7; val_offset:178*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 178*FLEN/8, x11, x1, x6)

inst_114:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1c4 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79c4; op2val:0x79c4;
   valaddr_reg:x7; val_offset:180*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 180*FLEN/8, x11, x1, x6)

inst_115:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x37c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b7c; op2val:0x7b7c;
   valaddr_reg:x7; val_offset:182*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 182*FLEN/8, x11, x1, x6)

inst_116:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x37c and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b7c; op2val:0x7b7c;
   valaddr_reg:x7; val_offset:184*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 184*FLEN/8, x11, x1, x6)

inst_117:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x37c and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b7c; op2val:0x7b7c;
   valaddr_reg:x7; val_offset:186*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 186*FLEN/8, x11, x1, x6)

inst_118:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x37c and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b7c; op2val:0x7b7c;
   valaddr_reg:x7; val_offset:188*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 188*FLEN/8, x11, x1, x6)

inst_119:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x37c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x37c and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b7c; op2val:0x7b7c;
   valaddr_reg:x7; val_offset:190*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 190*FLEN/8, x11, x1, x6)

inst_120:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2a3 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aa3; op2val:0x7aa3;
   valaddr_reg:x7; val_offset:192*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 192*FLEN/8, x11, x1, x6)

inst_121:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2a3 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aa3; op2val:0x7aa3;
   valaddr_reg:x7; val_offset:194*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 194*FLEN/8, x11, x1, x6)

inst_122:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2a3 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aa3; op2val:0x7aa3;
   valaddr_reg:x7; val_offset:196*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 196*FLEN/8, x11, x1, x6)

inst_123:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2a3 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aa3; op2val:0x7aa3;
   valaddr_reg:x7; val_offset:198*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 198*FLEN/8, x11, x1, x6)

inst_124:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2a3 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aa3; op2val:0x7aa3;
   valaddr_reg:x7; val_offset:200*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 200*FLEN/8, x11, x1, x6)

inst_125:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0da and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0da and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74da; op2val:0x74da;
   valaddr_reg:x7; val_offset:202*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 202*FLEN/8, x11, x1, x6)

inst_126:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0da and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0da and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74da; op2val:0x74da;
   valaddr_reg:x7; val_offset:204*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 204*FLEN/8, x11, x1, x6)

inst_127:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0da and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0da and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74da; op2val:0x74da;
   valaddr_reg:x7; val_offset:206*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 206*FLEN/8, x11, x1, x6)

inst_128:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0da and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0da and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74da; op2val:0x74da;
   valaddr_reg:x7; val_offset:208*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 208*FLEN/8, x11, x1, x6)

inst_129:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0da and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0da and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74da; op2val:0x74da;
   valaddr_reg:x7; val_offset:210*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 210*FLEN/8, x11, x1, x6)

inst_130:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x30e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b0e; op2val:0x7b0e;
   valaddr_reg:x7; val_offset:212*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 212*FLEN/8, x11, x1, x6)

inst_131:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x30e and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b0e; op2val:0x7b0e;
   valaddr_reg:x7; val_offset:214*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 214*FLEN/8, x11, x1, x6)

inst_132:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x30e and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b0e; op2val:0x7b0e;
   valaddr_reg:x7; val_offset:216*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 216*FLEN/8, x11, x1, x6)

inst_133:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x30e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b0e; op2val:0x7b0e;
   valaddr_reg:x7; val_offset:218*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 218*FLEN/8, x11, x1, x6)

inst_134:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x30e and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b0e; op2val:0x7b0e;
   valaddr_reg:x7; val_offset:220*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 220*FLEN/8, x11, x1, x6)

inst_135:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x00a and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x780a; op2val:0x780a;
   valaddr_reg:x7; val_offset:222*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 222*FLEN/8, x11, x1, x6)

inst_136:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x00a and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x780a; op2val:0x780a;
   valaddr_reg:x7; val_offset:224*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 224*FLEN/8, x11, x1, x6)

inst_137:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x00a and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x780a; op2val:0x780a;
   valaddr_reg:x7; val_offset:226*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 226*FLEN/8, x11, x1, x6)

inst_138:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x00a and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x780a; op2val:0x780a;
   valaddr_reg:x7; val_offset:228*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 228*FLEN/8, x11, x1, x6)

inst_139:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x00a and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x780a; op2val:0x780a;
   valaddr_reg:x7; val_offset:230*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 230*FLEN/8, x11, x1, x6)

inst_140:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x06b and fs2 == 0 and fe2 == 0x1a and fm2 == 0x06b and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x686b; op2val:0x686b;
   valaddr_reg:x7; val_offset:232*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 232*FLEN/8, x11, x1, x6)

inst_141:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x06b and fs2 == 0 and fe2 == 0x1a and fm2 == 0x06b and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x686b; op2val:0x686b;
   valaddr_reg:x7; val_offset:234*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 234*FLEN/8, x11, x1, x6)

inst_142:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x06b and fs2 == 0 and fe2 == 0x1a and fm2 == 0x06b and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x686b; op2val:0x686b;
   valaddr_reg:x7; val_offset:236*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 236*FLEN/8, x11, x1, x6)

inst_143:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x06b and fs2 == 0 and fe2 == 0x1a and fm2 == 0x06b and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x686b; op2val:0x686b;
   valaddr_reg:x7; val_offset:238*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 238*FLEN/8, x11, x1, x6)

inst_144:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x06b and fs2 == 0 and fe2 == 0x1a and fm2 == 0x06b and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x686b; op2val:0x686b;
   valaddr_reg:x7; val_offset:240*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 240*FLEN/8, x11, x1, x6)

inst_145:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x260 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x260 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a60; op2val:0x7a60;
   valaddr_reg:x7; val_offset:242*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 242*FLEN/8, x11, x1, x6)

inst_146:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x260 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x260 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a60; op2val:0x7a60;
   valaddr_reg:x7; val_offset:244*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 244*FLEN/8, x11, x1, x6)

inst_147:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x260 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x260 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a60; op2val:0x7a60;
   valaddr_reg:x7; val_offset:246*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 246*FLEN/8, x11, x1, x6)

inst_148:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x260 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x260 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a60; op2val:0x7a60;
   valaddr_reg:x7; val_offset:248*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 248*FLEN/8, x11, x1, x6)

inst_149:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x260 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x260 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a60; op2val:0x7a60;
   valaddr_reg:x7; val_offset:250*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 250*FLEN/8, x11, x1, x6)

inst_150:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x188 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x188 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7188; op2val:0x7188;
   valaddr_reg:x7; val_offset:252*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 252*FLEN/8, x11, x1, x6)

inst_151:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x188 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x188 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7188; op2val:0x7188;
   valaddr_reg:x7; val_offset:254*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 254*FLEN/8, x11, x1, x6)

inst_152:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x188 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x188 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7188; op2val:0x7188;
   valaddr_reg:x7; val_offset:256*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 256*FLEN/8, x11, x1, x6)

inst_153:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x188 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x188 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7188; op2val:0x7188;
   valaddr_reg:x7; val_offset:258*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 258*FLEN/8, x11, x1, x6)
RVTEST_SIGBASE(x1,signature_x1_3)

inst_154:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x188 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x188 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7188; op2val:0x7188;
   valaddr_reg:x7; val_offset:260*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 260*FLEN/8, x11, x1, x6)

inst_155:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x19f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x799f; op2val:0x799f;
   valaddr_reg:x7; val_offset:262*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 262*FLEN/8, x11, x1, x6)

inst_156:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x19f and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x799f; op2val:0x799f;
   valaddr_reg:x7; val_offset:264*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 264*FLEN/8, x11, x1, x6)

inst_157:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x19f and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x799f; op2val:0x799f;
   valaddr_reg:x7; val_offset:266*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 266*FLEN/8, x11, x1, x6)

inst_158:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x19f and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x799f; op2val:0x799f;
   valaddr_reg:x7; val_offset:268*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 268*FLEN/8, x11, x1, x6)

inst_159:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x19f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x19f and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x799f; op2val:0x799f;
   valaddr_reg:x7; val_offset:270*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 270*FLEN/8, x11, x1, x6)

inst_160:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1fe and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75fe; op2val:0x75fe;
   valaddr_reg:x7; val_offset:272*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 272*FLEN/8, x11, x1, x6)

inst_161:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1fe and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75fe; op2val:0x75fe;
   valaddr_reg:x7; val_offset:274*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 274*FLEN/8, x11, x1, x6)

inst_162:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1fe and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75fe; op2val:0x75fe;
   valaddr_reg:x7; val_offset:276*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 276*FLEN/8, x11, x1, x6)

inst_163:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1fe and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75fe; op2val:0x75fe;
   valaddr_reg:x7; val_offset:278*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 278*FLEN/8, x11, x1, x6)

inst_164:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1fe and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1fe and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75fe; op2val:0x75fe;
   valaddr_reg:x7; val_offset:280*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 280*FLEN/8, x11, x1, x6)

inst_165:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x010 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x010 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7810; op2val:0x7810;
   valaddr_reg:x7; val_offset:282*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 282*FLEN/8, x11, x1, x6)

inst_166:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x010 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x010 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7810; op2val:0x7810;
   valaddr_reg:x7; val_offset:284*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 284*FLEN/8, x11, x1, x6)

inst_167:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x010 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x010 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7810; op2val:0x7810;
   valaddr_reg:x7; val_offset:286*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 286*FLEN/8, x11, x1, x6)

inst_168:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x010 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x010 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7810; op2val:0x7810;
   valaddr_reg:x7; val_offset:288*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 288*FLEN/8, x11, x1, x6)

inst_169:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x010 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x010 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7810; op2val:0x7810;
   valaddr_reg:x7; val_offset:290*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 290*FLEN/8, x11, x1, x6)

inst_170:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x02a and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x782a; op2val:0x782a;
   valaddr_reg:x7; val_offset:292*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 292*FLEN/8, x11, x1, x6)

inst_171:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x02a and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x782a; op2val:0x782a;
   valaddr_reg:x7; val_offset:294*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 294*FLEN/8, x11, x1, x6)

inst_172:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x02a and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x782a; op2val:0x782a;
   valaddr_reg:x7; val_offset:296*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 296*FLEN/8, x11, x1, x6)

inst_173:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x02a and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x782a; op2val:0x782a;
   valaddr_reg:x7; val_offset:298*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 298*FLEN/8, x11, x1, x6)

inst_174:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x02a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x02a and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x782a; op2val:0x782a;
   valaddr_reg:x7; val_offset:300*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 300*FLEN/8, x11, x1, x6)

inst_175:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3d4 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d4; op2val:0x77d4;
   valaddr_reg:x7; val_offset:302*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 302*FLEN/8, x11, x1, x6)

inst_176:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3d4 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d4; op2val:0x77d4;
   valaddr_reg:x7; val_offset:304*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 304*FLEN/8, x11, x1, x6)

inst_177:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3d4 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d4; op2val:0x77d4;
   valaddr_reg:x7; val_offset:306*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 306*FLEN/8, x11, x1, x6)

inst_178:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3d4 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d4; op2val:0x77d4;
   valaddr_reg:x7; val_offset:308*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 308*FLEN/8, x11, x1, x6)

inst_179:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3d4 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77d4; op2val:0x77d4;
   valaddr_reg:x7; val_offset:310*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 310*FLEN/8, x11, x1, x6)

inst_180:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x190 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x190 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6990; op2val:0x6990;
   valaddr_reg:x7; val_offset:312*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 312*FLEN/8, x11, x1, x6)

inst_181:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x190 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x190 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6990; op2val:0x6990;
   valaddr_reg:x7; val_offset:314*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 314*FLEN/8, x11, x1, x6)

inst_182:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x190 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x190 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6990; op2val:0x6990;
   valaddr_reg:x7; val_offset:316*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 316*FLEN/8, x11, x1, x6)

inst_183:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x190 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x190 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6990; op2val:0x6990;
   valaddr_reg:x7; val_offset:318*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 318*FLEN/8, x11, x1, x6)

inst_184:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x190 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x190 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6990; op2val:0x6990;
   valaddr_reg:x7; val_offset:320*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 320*FLEN/8, x11, x1, x6)

inst_185:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3dc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3dc and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bdc; op2val:0x7bdc;
   valaddr_reg:x7; val_offset:322*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 322*FLEN/8, x11, x1, x6)

inst_186:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3dc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3dc and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bdc; op2val:0x7bdc;
   valaddr_reg:x7; val_offset:324*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 324*FLEN/8, x11, x1, x6)

inst_187:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3dc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3dc and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bdc; op2val:0x7bdc;
   valaddr_reg:x7; val_offset:326*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 326*FLEN/8, x11, x1, x6)

inst_188:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3dc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3dc and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bdc; op2val:0x7bdc;
   valaddr_reg:x7; val_offset:328*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 328*FLEN/8, x11, x1, x6)

inst_189:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3dc and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3dc and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bdc; op2val:0x7bdc;
   valaddr_reg:x7; val_offset:330*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 330*FLEN/8, x11, x1, x6)

inst_190:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x24b and fs2 == 0 and fe2 == 0x1d and fm2 == 0x24b and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x764b; op2val:0x764b;
   valaddr_reg:x7; val_offset:332*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 332*FLEN/8, x11, x1, x6)

inst_191:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x24b and fs2 == 0 and fe2 == 0x1d and fm2 == 0x24b and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x764b; op2val:0x764b;
   valaddr_reg:x7; val_offset:334*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 334*FLEN/8, x11, x1, x6)

inst_192:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x24b and fs2 == 0 and fe2 == 0x1d and fm2 == 0x24b and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x764b; op2val:0x764b;
   valaddr_reg:x7; val_offset:336*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 336*FLEN/8, x11, x1, x6)

inst_193:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x24b and fs2 == 0 and fe2 == 0x1d and fm2 == 0x24b and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x764b; op2val:0x764b;
   valaddr_reg:x7; val_offset:338*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 338*FLEN/8, x11, x1, x6)

inst_194:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x24b and fs2 == 0 and fe2 == 0x1d and fm2 == 0x24b and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x764b; op2val:0x764b;
   valaddr_reg:x7; val_offset:340*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 340*FLEN/8, x11, x1, x6)

inst_195:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x004 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7804; op2val:0x7804;
   valaddr_reg:x7; val_offset:342*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 342*FLEN/8, x11, x1, x6)

inst_196:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x004 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7804; op2val:0x7804;
   valaddr_reg:x7; val_offset:344*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 344*FLEN/8, x11, x1, x6)

inst_197:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x004 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7804; op2val:0x7804;
   valaddr_reg:x7; val_offset:346*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 346*FLEN/8, x11, x1, x6)

inst_198:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x004 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7804; op2val:0x7804;
   valaddr_reg:x7; val_offset:348*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 348*FLEN/8, x11, x1, x6)

inst_199:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x004 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7804; op2val:0x7804;
   valaddr_reg:x7; val_offset:350*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 350*FLEN/8, x11, x1, x6)

inst_200:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x229 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x229 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a29; op2val:0x7a29;
   valaddr_reg:x7; val_offset:352*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 352*FLEN/8, x11, x1, x6)

inst_201:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x229 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x229 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a29; op2val:0x7a29;
   valaddr_reg:x7; val_offset:354*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 354*FLEN/8, x11, x1, x6)

inst_202:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x229 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x229 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a29; op2val:0x7a29;
   valaddr_reg:x7; val_offset:356*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 356*FLEN/8, x11, x1, x6)

inst_203:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x229 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x229 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a29; op2val:0x7a29;
   valaddr_reg:x7; val_offset:358*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 358*FLEN/8, x11, x1, x6)

inst_204:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x229 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x229 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a29; op2val:0x7a29;
   valaddr_reg:x7; val_offset:360*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 360*FLEN/8, x11, x1, x6)

inst_205:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e1 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ae1; op2val:0x7ae1;
   valaddr_reg:x7; val_offset:362*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 362*FLEN/8, x11, x1, x6)

inst_206:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e1 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ae1; op2val:0x7ae1;
   valaddr_reg:x7; val_offset:364*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 364*FLEN/8, x11, x1, x6)

inst_207:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e1 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ae1; op2val:0x7ae1;
   valaddr_reg:x7; val_offset:366*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 366*FLEN/8, x11, x1, x6)

inst_208:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e1 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ae1; op2val:0x7ae1;
   valaddr_reg:x7; val_offset:368*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 368*FLEN/8, x11, x1, x6)

inst_209:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e1 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ae1; op2val:0x7ae1;
   valaddr_reg:x7; val_offset:370*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 370*FLEN/8, x11, x1, x6)

inst_210:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x01b and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x781b; op2val:0x781b;
   valaddr_reg:x7; val_offset:372*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 372*FLEN/8, x11, x1, x6)

inst_211:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x01b and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x781b; op2val:0x781b;
   valaddr_reg:x7; val_offset:374*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 374*FLEN/8, x11, x1, x6)

inst_212:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x01b and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x781b; op2val:0x781b;
   valaddr_reg:x7; val_offset:376*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 376*FLEN/8, x11, x1, x6)

inst_213:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x01b and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x781b; op2val:0x781b;
   valaddr_reg:x7; val_offset:378*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 378*FLEN/8, x11, x1, x6)

inst_214:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x01b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x01b and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x781b; op2val:0x781b;
   valaddr_reg:x7; val_offset:380*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 380*FLEN/8, x11, x1, x6)

inst_215:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x09e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x789e; op2val:0x789e;
   valaddr_reg:x7; val_offset:382*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 382*FLEN/8, x11, x1, x6)

inst_216:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x09e and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x789e; op2val:0x789e;
   valaddr_reg:x7; val_offset:384*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 384*FLEN/8, x11, x1, x6)

inst_217:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x09e and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x789e; op2val:0x789e;
   valaddr_reg:x7; val_offset:386*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 386*FLEN/8, x11, x1, x6)

inst_218:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x09e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x789e; op2val:0x789e;
   valaddr_reg:x7; val_offset:388*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 388*FLEN/8, x11, x1, x6)

inst_219:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x09e and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x789e; op2val:0x789e;
   valaddr_reg:x7; val_offset:390*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 390*FLEN/8, x11, x1, x6)

inst_220:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x04e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x04e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x744e; op2val:0x744e;
   valaddr_reg:x7; val_offset:392*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 392*FLEN/8, x11, x1, x6)

inst_221:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x04e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x04e and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x744e; op2val:0x744e;
   valaddr_reg:x7; val_offset:394*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 394*FLEN/8, x11, x1, x6)

inst_222:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x04e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x04e and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x744e; op2val:0x744e;
   valaddr_reg:x7; val_offset:396*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 396*FLEN/8, x11, x1, x6)

inst_223:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x04e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x04e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x744e; op2val:0x744e;
   valaddr_reg:x7; val_offset:398*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 398*FLEN/8, x11, x1, x6)

inst_224:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x04e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x04e and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x744e; op2val:0x744e;
   valaddr_reg:x7; val_offset:400*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 400*FLEN/8, x11, x1, x6)

inst_225:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a7 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba7; op2val:0x7ba7;
   valaddr_reg:x7; val_offset:402*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 402*FLEN/8, x11, x1, x6)

inst_226:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a7 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba7; op2val:0x7ba7;
   valaddr_reg:x7; val_offset:404*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 404*FLEN/8, x11, x1, x6)

inst_227:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a7 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba7; op2val:0x7ba7;
   valaddr_reg:x7; val_offset:406*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 406*FLEN/8, x11, x1, x6)

inst_228:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a7 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba7; op2val:0x7ba7;
   valaddr_reg:x7; val_offset:408*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 408*FLEN/8, x11, x1, x6)

inst_229:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a7 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba7; op2val:0x7ba7;
   valaddr_reg:x7; val_offset:410*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 410*FLEN/8, x11, x1, x6)

inst_230:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x244 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a44; op2val:0x7a44;
   valaddr_reg:x7; val_offset:412*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 412*FLEN/8, x11, x1, x6)

inst_231:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x244 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a44; op2val:0x7a44;
   valaddr_reg:x7; val_offset:414*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 414*FLEN/8, x11, x1, x6)

inst_232:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x244 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a44; op2val:0x7a44;
   valaddr_reg:x7; val_offset:416*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 416*FLEN/8, x11, x1, x6)

inst_233:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x244 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a44; op2val:0x7a44;
   valaddr_reg:x7; val_offset:418*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 418*FLEN/8, x11, x1, x6)

inst_234:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x244 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a44; op2val:0x7a44;
   valaddr_reg:x7; val_offset:420*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 420*FLEN/8, x11, x1, x6)

inst_235:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x316 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x316 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b16; op2val:0x7b16;
   valaddr_reg:x7; val_offset:422*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 422*FLEN/8, x11, x1, x6)

inst_236:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x316 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x316 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b16; op2val:0x7b16;
   valaddr_reg:x7; val_offset:424*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 424*FLEN/8, x11, x1, x6)

inst_237:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x316 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x316 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b16; op2val:0x7b16;
   valaddr_reg:x7; val_offset:426*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 426*FLEN/8, x11, x1, x6)

inst_238:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x316 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x316 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b16; op2val:0x7b16;
   valaddr_reg:x7; val_offset:428*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 428*FLEN/8, x11, x1, x6)

inst_239:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x316 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x316 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b16; op2val:0x7b16;
   valaddr_reg:x7; val_offset:430*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 430*FLEN/8, x11, x1, x6)

inst_240:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x278 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x278 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a78; op2val:0x7a78;
   valaddr_reg:x7; val_offset:432*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 432*FLEN/8, x11, x1, x6)

inst_241:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x278 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x278 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a78; op2val:0x7a78;
   valaddr_reg:x7; val_offset:434*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 434*FLEN/8, x11, x1, x6)

inst_242:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x278 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x278 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a78; op2val:0x7a78;
   valaddr_reg:x7; val_offset:436*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 436*FLEN/8, x11, x1, x6)

inst_243:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x278 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x278 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a78; op2val:0x7a78;
   valaddr_reg:x7; val_offset:438*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 438*FLEN/8, x11, x1, x6)

inst_244:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x278 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x278 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a78; op2val:0x7a78;
   valaddr_reg:x7; val_offset:440*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 440*FLEN/8, x11, x1, x6)

inst_245:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x07d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x07d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x787d; op2val:0x787d;
   valaddr_reg:x7; val_offset:442*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 442*FLEN/8, x11, x1, x6)

inst_246:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x07d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x07d and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x787d; op2val:0x787d;
   valaddr_reg:x7; val_offset:444*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 444*FLEN/8, x11, x1, x6)

inst_247:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x07d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x07d and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x787d; op2val:0x787d;
   valaddr_reg:x7; val_offset:446*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 446*FLEN/8, x11, x1, x6)

inst_248:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x07d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x07d and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x787d; op2val:0x787d;
   valaddr_reg:x7; val_offset:448*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 448*FLEN/8, x11, x1, x6)

inst_249:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x07d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x07d and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x787d; op2val:0x787d;
   valaddr_reg:x7; val_offset:450*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 450*FLEN/8, x11, x1, x6)

inst_250:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x32e and fs2 == 0 and fe2 == 0x1a and fm2 == 0x32e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6b2e; op2val:0x6b2e;
   valaddr_reg:x7; val_offset:452*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 452*FLEN/8, x11, x1, x6)

inst_251:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x32e and fs2 == 0 and fe2 == 0x1a and fm2 == 0x32e and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6b2e; op2val:0x6b2e;
   valaddr_reg:x7; val_offset:454*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 454*FLEN/8, x11, x1, x6)

inst_252:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x32e and fs2 == 0 and fe2 == 0x1a and fm2 == 0x32e and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6b2e; op2val:0x6b2e;
   valaddr_reg:x7; val_offset:456*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 456*FLEN/8, x11, x1, x6)

inst_253:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x32e and fs2 == 0 and fe2 == 0x1a and fm2 == 0x32e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6b2e; op2val:0x6b2e;
   valaddr_reg:x7; val_offset:458*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 458*FLEN/8, x11, x1, x6)

inst_254:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x32e and fs2 == 0 and fe2 == 0x1a and fm2 == 0x32e and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6b2e; op2val:0x6b2e;
   valaddr_reg:x7; val_offset:460*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 460*FLEN/8, x11, x1, x6)

inst_255:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x08e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x788e; op2val:0x788e;
   valaddr_reg:x7; val_offset:462*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 462*FLEN/8, x11, x1, x6)

inst_256:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x08e and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x788e; op2val:0x788e;
   valaddr_reg:x7; val_offset:464*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 464*FLEN/8, x11, x1, x6)

inst_257:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x08e and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x788e; op2val:0x788e;
   valaddr_reg:x7; val_offset:466*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 466*FLEN/8, x11, x1, x6)

inst_258:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x08e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x788e; op2val:0x788e;
   valaddr_reg:x7; val_offset:468*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 468*FLEN/8, x11, x1, x6)

inst_259:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x08e and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x788e; op2val:0x788e;
   valaddr_reg:x7; val_offset:470*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 470*FLEN/8, x11, x1, x6)

inst_260:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x009 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x009 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7809; op2val:0x7809;
   valaddr_reg:x7; val_offset:472*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 472*FLEN/8, x11, x1, x6)

inst_261:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x009 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x009 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7809; op2val:0x7809;
   valaddr_reg:x7; val_offset:474*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 474*FLEN/8, x11, x1, x6)

inst_262:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x009 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x009 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7809; op2val:0x7809;
   valaddr_reg:x7; val_offset:476*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 476*FLEN/8, x11, x1, x6)

inst_263:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x009 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x009 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7809; op2val:0x7809;
   valaddr_reg:x7; val_offset:478*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 478*FLEN/8, x11, x1, x6)

inst_264:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x009 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x009 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7809; op2val:0x7809;
   valaddr_reg:x7; val_offset:480*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 480*FLEN/8, x11, x1, x6)

inst_265:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1b4 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75b4; op2val:0x75b4;
   valaddr_reg:x7; val_offset:482*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 482*FLEN/8, x11, x1, x6)

inst_266:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1b4 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75b4; op2val:0x75b4;
   valaddr_reg:x7; val_offset:484*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 484*FLEN/8, x11, x1, x6)

inst_267:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1b4 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75b4; op2val:0x75b4;
   valaddr_reg:x7; val_offset:486*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 486*FLEN/8, x11, x1, x6)

inst_268:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1b4 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75b4; op2val:0x75b4;
   valaddr_reg:x7; val_offset:488*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 488*FLEN/8, x11, x1, x6)

inst_269:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1b4 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1b4 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75b4; op2val:0x75b4;
   valaddr_reg:x7; val_offset:490*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 490*FLEN/8, x11, x1, x6)

inst_270:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x04e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x784e; op2val:0x784e;
   valaddr_reg:x7; val_offset:492*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 492*FLEN/8, x11, x1, x6)

inst_271:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x04e and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x784e; op2val:0x784e;
   valaddr_reg:x7; val_offset:494*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 494*FLEN/8, x11, x1, x6)

inst_272:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x04e and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x784e; op2val:0x784e;
   valaddr_reg:x7; val_offset:496*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 496*FLEN/8, x11, x1, x6)

inst_273:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x04e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x784e; op2val:0x784e;
   valaddr_reg:x7; val_offset:498*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 498*FLEN/8, x11, x1, x6)

inst_274:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x04e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x04e and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x784e; op2val:0x784e;
   valaddr_reg:x7; val_offset:500*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 500*FLEN/8, x11, x1, x6)

inst_275:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0e5 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e5; op2val:0x78e5;
   valaddr_reg:x7; val_offset:502*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 502*FLEN/8, x11, x1, x6)

inst_276:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0e5 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e5; op2val:0x78e5;
   valaddr_reg:x7; val_offset:504*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 504*FLEN/8, x11, x1, x6)

inst_277:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0e5 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e5; op2val:0x78e5;
   valaddr_reg:x7; val_offset:506*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 506*FLEN/8, x11, x1, x6)

inst_278:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0e5 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e5; op2val:0x78e5;
   valaddr_reg:x7; val_offset:508*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 508*FLEN/8, x11, x1, x6)

inst_279:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0e5 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x78e5; op2val:0x78e5;
   valaddr_reg:x7; val_offset:510*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 510*FLEN/8, x11, x1, x6)

inst_280:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x329 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x329 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6729; op2val:0x6729;
   valaddr_reg:x7; val_offset:512*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 512*FLEN/8, x11, x1, x6)

inst_281:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x329 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x329 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6729; op2val:0x6729;
   valaddr_reg:x7; val_offset:514*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 514*FLEN/8, x11, x1, x6)
RVTEST_SIGBASE(x1,signature_x1_4)

inst_282:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x329 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x329 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6729; op2val:0x6729;
   valaddr_reg:x7; val_offset:516*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 516*FLEN/8, x11, x1, x6)

inst_283:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x329 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x329 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6729; op2val:0x6729;
   valaddr_reg:x7; val_offset:518*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 518*FLEN/8, x11, x1, x6)

inst_284:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x329 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x329 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6729; op2val:0x6729;
   valaddr_reg:x7; val_offset:520*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 520*FLEN/8, x11, x1, x6)

inst_285:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1ab and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1ab and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x71ab; op2val:0x71ab;
   valaddr_reg:x7; val_offset:522*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 522*FLEN/8, x11, x1, x6)

inst_286:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1ab and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1ab and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x71ab; op2val:0x71ab;
   valaddr_reg:x7; val_offset:524*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 524*FLEN/8, x11, x1, x6)

inst_287:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1ab and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1ab and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x71ab; op2val:0x71ab;
   valaddr_reg:x7; val_offset:526*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 526*FLEN/8, x11, x1, x6)

inst_288:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1ab and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1ab and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x71ab; op2val:0x71ab;
   valaddr_reg:x7; val_offset:528*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 528*FLEN/8, x11, x1, x6)

inst_289:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1ab and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1ab and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x71ab; op2val:0x71ab;
   valaddr_reg:x7; val_offset:530*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 530*FLEN/8, x11, x1, x6)

inst_290:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e2 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ae2; op2val:0x7ae2;
   valaddr_reg:x7; val_offset:532*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 532*FLEN/8, x11, x1, x6)

inst_291:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e2 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ae2; op2val:0x7ae2;
   valaddr_reg:x7; val_offset:534*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 534*FLEN/8, x11, x1, x6)

inst_292:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e2 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ae2; op2val:0x7ae2;
   valaddr_reg:x7; val_offset:536*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 536*FLEN/8, x11, x1, x6)

inst_293:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e2 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ae2; op2val:0x7ae2;
   valaddr_reg:x7; val_offset:538*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 538*FLEN/8, x11, x1, x6)

inst_294:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2e2 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ae2; op2val:0x7ae2;
   valaddr_reg:x7; val_offset:540*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 540*FLEN/8, x11, x1, x6)

inst_295:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x25f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a5f; op2val:0x7a5f;
   valaddr_reg:x7; val_offset:542*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 542*FLEN/8, x11, x1, x6)

inst_296:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x25f and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a5f; op2val:0x7a5f;
   valaddr_reg:x7; val_offset:544*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 544*FLEN/8, x11, x1, x6)

inst_297:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x25f and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a5f; op2val:0x7a5f;
   valaddr_reg:x7; val_offset:546*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 546*FLEN/8, x11, x1, x6)

inst_298:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x25f and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a5f; op2val:0x7a5f;
   valaddr_reg:x7; val_offset:548*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 548*FLEN/8, x11, x1, x6)

inst_299:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x25f and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a5f; op2val:0x7a5f;
   valaddr_reg:x7; val_offset:550*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 550*FLEN/8, x11, x1, x6)

inst_300:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x015 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x015 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7415; op2val:0x7415;
   valaddr_reg:x7; val_offset:552*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 552*FLEN/8, x11, x1, x6)

inst_301:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x015 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x015 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7415; op2val:0x7415;
   valaddr_reg:x7; val_offset:554*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 554*FLEN/8, x11, x1, x6)

inst_302:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x015 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x015 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7415; op2val:0x7415;
   valaddr_reg:x7; val_offset:556*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 556*FLEN/8, x11, x1, x6)

inst_303:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x015 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x015 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7415; op2val:0x7415;
   valaddr_reg:x7; val_offset:558*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 558*FLEN/8, x11, x1, x6)

inst_304:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x015 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x015 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7415; op2val:0x7415;
   valaddr_reg:x7; val_offset:560*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 560*FLEN/8, x11, x1, x6)

inst_305:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x161 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x161 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7961; op2val:0x7961;
   valaddr_reg:x7; val_offset:562*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 562*FLEN/8, x11, x1, x6)

inst_306:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x161 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x161 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7961; op2val:0x7961;
   valaddr_reg:x7; val_offset:564*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 564*FLEN/8, x11, x1, x6)

inst_307:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x161 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x161 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7961; op2val:0x7961;
   valaddr_reg:x7; val_offset:566*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 566*FLEN/8, x11, x1, x6)

inst_308:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x161 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x161 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7961; op2val:0x7961;
   valaddr_reg:x7; val_offset:568*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 568*FLEN/8, x11, x1, x6)

inst_309:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x161 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x161 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7961; op2val:0x7961;
   valaddr_reg:x7; val_offset:570*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 570*FLEN/8, x11, x1, x6)

inst_310:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x046 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x046 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6446; op2val:0x6446;
   valaddr_reg:x7; val_offset:572*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 572*FLEN/8, x11, x1, x6)

inst_311:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x046 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x046 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6446; op2val:0x6446;
   valaddr_reg:x7; val_offset:574*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 574*FLEN/8, x11, x1, x6)

inst_312:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x046 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x046 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6446; op2val:0x6446;
   valaddr_reg:x7; val_offset:576*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 576*FLEN/8, x11, x1, x6)

inst_313:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x046 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x046 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6446; op2val:0x6446;
   valaddr_reg:x7; val_offset:578*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 578*FLEN/8, x11, x1, x6)

inst_314:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x046 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x046 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6446; op2val:0x6446;
   valaddr_reg:x7; val_offset:580*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 580*FLEN/8, x11, x1, x6)

inst_315:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20a and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a0a; op2val:0x7a0a;
   valaddr_reg:x7; val_offset:582*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 582*FLEN/8, x11, x1, x6)

inst_316:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20a and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a0a; op2val:0x7a0a;
   valaddr_reg:x7; val_offset:584*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 584*FLEN/8, x11, x1, x6)

inst_317:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20a and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a0a; op2val:0x7a0a;
   valaddr_reg:x7; val_offset:586*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 586*FLEN/8, x11, x1, x6)

inst_318:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20a and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a0a; op2val:0x7a0a;
   valaddr_reg:x7; val_offset:588*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 588*FLEN/8, x11, x1, x6)

inst_319:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20a and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a0a; op2val:0x7a0a;
   valaddr_reg:x7; val_offset:590*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 590*FLEN/8, x11, x1, x6)

inst_320:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x301 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x301 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f01; op2val:0x6f01;
   valaddr_reg:x7; val_offset:592*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 592*FLEN/8, x11, x1, x6)

inst_321:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x301 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x301 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f01; op2val:0x6f01;
   valaddr_reg:x7; val_offset:594*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 594*FLEN/8, x11, x1, x6)

inst_322:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x301 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x301 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f01; op2val:0x6f01;
   valaddr_reg:x7; val_offset:596*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 596*FLEN/8, x11, x1, x6)

inst_323:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x301 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x301 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f01; op2val:0x6f01;
   valaddr_reg:x7; val_offset:598*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 598*FLEN/8, x11, x1, x6)

inst_324:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x301 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x301 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f01; op2val:0x6f01;
   valaddr_reg:x7; val_offset:600*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 600*FLEN/8, x11, x1, x6)

inst_325:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x182 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x182 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7582; op2val:0x7582;
   valaddr_reg:x7; val_offset:602*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 602*FLEN/8, x11, x1, x6)

inst_326:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x182 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x182 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7582; op2val:0x7582;
   valaddr_reg:x7; val_offset:604*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 604*FLEN/8, x11, x1, x6)

inst_327:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x182 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x182 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7582; op2val:0x7582;
   valaddr_reg:x7; val_offset:606*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 606*FLEN/8, x11, x1, x6)

inst_328:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x182 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x182 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7582; op2val:0x7582;
   valaddr_reg:x7; val_offset:608*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 608*FLEN/8, x11, x1, x6)

inst_329:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x182 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x182 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7582; op2val:0x7582;
   valaddr_reg:x7; val_offset:610*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 610*FLEN/8, x11, x1, x6)

inst_330:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x11b and fs2 == 0 and fe2 == 0x1c and fm2 == 0x11b and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x711b; op2val:0x711b;
   valaddr_reg:x7; val_offset:612*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 612*FLEN/8, x11, x1, x6)

inst_331:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x11b and fs2 == 0 and fe2 == 0x1c and fm2 == 0x11b and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x711b; op2val:0x711b;
   valaddr_reg:x7; val_offset:614*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 614*FLEN/8, x11, x1, x6)

inst_332:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x11b and fs2 == 0 and fe2 == 0x1c and fm2 == 0x11b and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x711b; op2val:0x711b;
   valaddr_reg:x7; val_offset:616*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 616*FLEN/8, x11, x1, x6)

inst_333:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x11b and fs2 == 0 and fe2 == 0x1c and fm2 == 0x11b and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x711b; op2val:0x711b;
   valaddr_reg:x7; val_offset:618*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 618*FLEN/8, x11, x1, x6)

inst_334:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x11b and fs2 == 0 and fe2 == 0x1c and fm2 == 0x11b and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x711b; op2val:0x711b;
   valaddr_reg:x7; val_offset:620*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 620*FLEN/8, x11, x1, x6)

inst_335:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x160 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x160 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7160; op2val:0x7160;
   valaddr_reg:x7; val_offset:622*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 622*FLEN/8, x11, x1, x6)

inst_336:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x160 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x160 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7160; op2val:0x7160;
   valaddr_reg:x7; val_offset:624*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 624*FLEN/8, x11, x1, x6)

inst_337:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x160 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x160 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7160; op2val:0x7160;
   valaddr_reg:x7; val_offset:626*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 626*FLEN/8, x11, x1, x6)

inst_338:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x160 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x160 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7160; op2val:0x7160;
   valaddr_reg:x7; val_offset:628*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 628*FLEN/8, x11, x1, x6)

inst_339:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x160 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x160 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7160; op2val:0x7160;
   valaddr_reg:x7; val_offset:630*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 630*FLEN/8, x11, x1, x6)

inst_340:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1b0 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b0; op2val:0x79b0;
   valaddr_reg:x7; val_offset:632*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 632*FLEN/8, x11, x1, x6)

inst_341:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1b0 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b0; op2val:0x79b0;
   valaddr_reg:x7; val_offset:634*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 634*FLEN/8, x11, x1, x6)

inst_342:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1b0 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b0; op2val:0x79b0;
   valaddr_reg:x7; val_offset:636*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 636*FLEN/8, x11, x1, x6)

inst_343:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1b0 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b0; op2val:0x79b0;
   valaddr_reg:x7; val_offset:638*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 638*FLEN/8, x11, x1, x6)

inst_344:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1b0 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b0; op2val:0x79b0;
   valaddr_reg:x7; val_offset:640*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 640*FLEN/8, x11, x1, x6)

inst_345:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x126 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x126 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7526; op2val:0x7526;
   valaddr_reg:x7; val_offset:642*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 642*FLEN/8, x11, x1, x6)

inst_346:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x126 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x126 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7526; op2val:0x7526;
   valaddr_reg:x7; val_offset:644*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 644*FLEN/8, x11, x1, x6)

inst_347:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x126 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x126 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7526; op2val:0x7526;
   valaddr_reg:x7; val_offset:646*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 646*FLEN/8, x11, x1, x6)

inst_348:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x126 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x126 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7526; op2val:0x7526;
   valaddr_reg:x7; val_offset:648*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 648*FLEN/8, x11, x1, x6)

inst_349:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x126 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x126 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7526; op2val:0x7526;
   valaddr_reg:x7; val_offset:650*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 650*FLEN/8, x11, x1, x6)

inst_350:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x20d and fs2 == 0 and fe2 == 0x19 and fm2 == 0x20d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x660d; op2val:0x660d;
   valaddr_reg:x7; val_offset:652*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 652*FLEN/8, x11, x1, x6)

inst_351:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x20d and fs2 == 0 and fe2 == 0x19 and fm2 == 0x20d and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x660d; op2val:0x660d;
   valaddr_reg:x7; val_offset:654*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 654*FLEN/8, x11, x1, x6)

inst_352:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x20d and fs2 == 0 and fe2 == 0x19 and fm2 == 0x20d and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x660d; op2val:0x660d;
   valaddr_reg:x7; val_offset:656*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 656*FLEN/8, x11, x1, x6)

inst_353:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x20d and fs2 == 0 and fe2 == 0x19 and fm2 == 0x20d and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x660d; op2val:0x660d;
   valaddr_reg:x7; val_offset:658*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 658*FLEN/8, x11, x1, x6)

inst_354:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x20d and fs2 == 0 and fe2 == 0x19 and fm2 == 0x20d and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x660d; op2val:0x660d;
   valaddr_reg:x7; val_offset:660*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 660*FLEN/8, x11, x1, x6)

inst_355:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2bb and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2bb and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x76bb; op2val:0x76bb;
   valaddr_reg:x7; val_offset:662*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 662*FLEN/8, x11, x1, x6)

inst_356:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2bb and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2bb and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x76bb; op2val:0x76bb;
   valaddr_reg:x7; val_offset:664*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 664*FLEN/8, x11, x1, x6)

inst_357:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2bb and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2bb and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x76bb; op2val:0x76bb;
   valaddr_reg:x7; val_offset:666*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 666*FLEN/8, x11, x1, x6)

inst_358:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2bb and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2bb and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x76bb; op2val:0x76bb;
   valaddr_reg:x7; val_offset:668*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 668*FLEN/8, x11, x1, x6)

inst_359:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2bb and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2bb and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x76bb; op2val:0x76bb;
   valaddr_reg:x7; val_offset:670*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 670*FLEN/8, x11, x1, x6)

inst_360:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2f5 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ef5; op2val:0x6ef5;
   valaddr_reg:x7; val_offset:672*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 672*FLEN/8, x11, x1, x6)

inst_361:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2f5 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ef5; op2val:0x6ef5;
   valaddr_reg:x7; val_offset:674*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 674*FLEN/8, x11, x1, x6)

inst_362:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2f5 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ef5; op2val:0x6ef5;
   valaddr_reg:x7; val_offset:676*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 676*FLEN/8, x11, x1, x6)

inst_363:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2f5 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ef5; op2val:0x6ef5;
   valaddr_reg:x7; val_offset:678*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 678*FLEN/8, x11, x1, x6)

inst_364:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2f5 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ef5; op2val:0x6ef5;
   valaddr_reg:x7; val_offset:680*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 680*FLEN/8, x11, x1, x6)

inst_365:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x014 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x014 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7814; op2val:0x7814;
   valaddr_reg:x7; val_offset:682*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 682*FLEN/8, x11, x1, x6)

inst_366:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x014 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x014 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7814; op2val:0x7814;
   valaddr_reg:x7; val_offset:684*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 684*FLEN/8, x11, x1, x6)

inst_367:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x014 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x014 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7814; op2val:0x7814;
   valaddr_reg:x7; val_offset:686*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 686*FLEN/8, x11, x1, x6)

inst_368:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x014 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x014 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7814; op2val:0x7814;
   valaddr_reg:x7; val_offset:688*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 688*FLEN/8, x11, x1, x6)

inst_369:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x014 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x014 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7814; op2val:0x7814;
   valaddr_reg:x7; val_offset:690*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 690*FLEN/8, x11, x1, x6)

inst_370:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d7 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x78d7; op2val:0x78d7;
   valaddr_reg:x7; val_offset:692*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 692*FLEN/8, x11, x1, x6)

inst_371:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d7 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x78d7; op2val:0x78d7;
   valaddr_reg:x7; val_offset:694*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 694*FLEN/8, x11, x1, x6)

inst_372:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d7 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x78d7; op2val:0x78d7;
   valaddr_reg:x7; val_offset:696*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 696*FLEN/8, x11, x1, x6)

inst_373:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d7 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x78d7; op2val:0x78d7;
   valaddr_reg:x7; val_offset:698*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 698*FLEN/8, x11, x1, x6)

inst_374:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0d7 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x78d7; op2val:0x78d7;
   valaddr_reg:x7; val_offset:700*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 700*FLEN/8, x11, x1, x6)

inst_375:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x154 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x154 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6554; op2val:0x6554;
   valaddr_reg:x7; val_offset:702*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 702*FLEN/8, x11, x1, x6)

inst_376:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x154 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x154 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6554; op2val:0x6554;
   valaddr_reg:x7; val_offset:704*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 704*FLEN/8, x11, x1, x6)

inst_377:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x154 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x154 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6554; op2val:0x6554;
   valaddr_reg:x7; val_offset:706*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 706*FLEN/8, x11, x1, x6)

inst_378:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x154 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x154 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6554; op2val:0x6554;
   valaddr_reg:x7; val_offset:708*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 708*FLEN/8, x11, x1, x6)

inst_379:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x154 and fs2 == 0 and fe2 == 0x19 and fm2 == 0x154 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6554; op2val:0x6554;
   valaddr_reg:x7; val_offset:710*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 710*FLEN/8, x11, x1, x6)

inst_380:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0af and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0af and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x70af; op2val:0x70af;
   valaddr_reg:x7; val_offset:712*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 712*FLEN/8, x11, x1, x6)

inst_381:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0af and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0af and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x70af; op2val:0x70af;
   valaddr_reg:x7; val_offset:714*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 714*FLEN/8, x11, x1, x6)

inst_382:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0af and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0af and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x70af; op2val:0x70af;
   valaddr_reg:x7; val_offset:716*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 716*FLEN/8, x11, x1, x6)

inst_383:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0af and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0af and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x70af; op2val:0x70af;
   valaddr_reg:x7; val_offset:718*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 718*FLEN/8, x11, x1, x6)

inst_384:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0af and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0af and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x70af; op2val:0x70af;
   valaddr_reg:x7; val_offset:720*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 720*FLEN/8, x11, x1, x6)

inst_385:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x120 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x120 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7120; op2val:0x7120;
   valaddr_reg:x7; val_offset:722*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 722*FLEN/8, x11, x1, x6)

inst_386:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x120 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x120 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7120; op2val:0x7120;
   valaddr_reg:x7; val_offset:724*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 724*FLEN/8, x11, x1, x6)

inst_387:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x120 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x120 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7120; op2val:0x7120;
   valaddr_reg:x7; val_offset:726*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 726*FLEN/8, x11, x1, x6)

inst_388:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x120 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x120 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7120; op2val:0x7120;
   valaddr_reg:x7; val_offset:728*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 728*FLEN/8, x11, x1, x6)

inst_389:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x120 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x120 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7120; op2val:0x7120;
   valaddr_reg:x7; val_offset:730*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 730*FLEN/8, x11, x1, x6)

inst_390:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x16c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x16c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x796c; op2val:0x796c;
   valaddr_reg:x7; val_offset:732*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 732*FLEN/8, x11, x1, x6)

inst_391:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x16c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x16c and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x796c; op2val:0x796c;
   valaddr_reg:x7; val_offset:734*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 734*FLEN/8, x11, x1, x6)

inst_392:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x16c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x16c and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x796c; op2val:0x796c;
   valaddr_reg:x7; val_offset:736*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 736*FLEN/8, x11, x1, x6)

inst_393:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x16c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x16c and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x796c; op2val:0x796c;
   valaddr_reg:x7; val_offset:738*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 738*FLEN/8, x11, x1, x6)

inst_394:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x16c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x16c and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x796c; op2val:0x796c;
   valaddr_reg:x7; val_offset:740*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 740*FLEN/8, x11, x1, x6)

inst_395:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x30e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x730e; op2val:0x730e;
   valaddr_reg:x7; val_offset:742*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 742*FLEN/8, x11, x1, x6)

inst_396:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x30e and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x730e; op2val:0x730e;
   valaddr_reg:x7; val_offset:744*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 744*FLEN/8, x11, x1, x6)

inst_397:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x30e and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x730e; op2val:0x730e;
   valaddr_reg:x7; val_offset:746*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 746*FLEN/8, x11, x1, x6)

inst_398:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x30e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x730e; op2val:0x730e;
   valaddr_reg:x7; val_offset:748*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 748*FLEN/8, x11, x1, x6)

inst_399:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x30e and fs2 == 0 and fe2 == 0x1c and fm2 == 0x30e and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x730e; op2val:0x730e;
   valaddr_reg:x7; val_offset:750*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 750*FLEN/8, x11, x1, x6)

inst_400:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x261 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x261 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a61; op2val:0x7a61;
   valaddr_reg:x7; val_offset:752*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 752*FLEN/8, x11, x1, x6)

inst_401:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x261 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x261 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a61; op2val:0x7a61;
   valaddr_reg:x7; val_offset:754*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 754*FLEN/8, x11, x1, x6)

inst_402:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x261 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x261 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a61; op2val:0x7a61;
   valaddr_reg:x7; val_offset:756*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 756*FLEN/8, x11, x1, x6)

inst_403:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x261 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x261 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a61; op2val:0x7a61;
   valaddr_reg:x7; val_offset:758*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 758*FLEN/8, x11, x1, x6)

inst_404:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x261 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x261 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a61; op2val:0x7a61;
   valaddr_reg:x7; val_offset:760*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 760*FLEN/8, x11, x1, x6)

inst_405:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x323 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x323 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7323; op2val:0x7323;
   valaddr_reg:x7; val_offset:762*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 762*FLEN/8, x11, x1, x6)

inst_406:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x323 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x323 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7323; op2val:0x7323;
   valaddr_reg:x7; val_offset:764*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 764*FLEN/8, x11, x1, x6)

inst_407:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x323 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x323 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7323; op2val:0x7323;
   valaddr_reg:x7; val_offset:766*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 766*FLEN/8, x11, x1, x6)

inst_408:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x323 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x323 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7323; op2val:0x7323;
   valaddr_reg:x7; val_offset:768*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 768*FLEN/8, x11, x1, x6)

inst_409:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x323 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x323 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7323; op2val:0x7323;
   valaddr_reg:x7; val_offset:770*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 770*FLEN/8, x11, x1, x6)
RVTEST_SIGBASE(x1,signature_x1_5)

inst_410:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x250 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x250 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7650; op2val:0x7650;
   valaddr_reg:x7; val_offset:772*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 772*FLEN/8, x11, x1, x6)

inst_411:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x250 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x250 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7650; op2val:0x7650;
   valaddr_reg:x7; val_offset:774*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 774*FLEN/8, x11, x1, x6)

inst_412:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x250 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x250 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7650; op2val:0x7650;
   valaddr_reg:x7; val_offset:776*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 776*FLEN/8, x11, x1, x6)

inst_413:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x250 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x250 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7650; op2val:0x7650;
   valaddr_reg:x7; val_offset:778*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 778*FLEN/8, x11, x1, x6)

inst_414:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x250 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x250 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7650; op2val:0x7650;
   valaddr_reg:x7; val_offset:780*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 780*FLEN/8, x11, x1, x6)

inst_415:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x123 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x123 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7523; op2val:0x7523;
   valaddr_reg:x7; val_offset:782*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 782*FLEN/8, x11, x1, x6)

inst_416:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x123 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x123 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7523; op2val:0x7523;
   valaddr_reg:x7; val_offset:784*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 784*FLEN/8, x11, x1, x6)

inst_417:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x123 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x123 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7523; op2val:0x7523;
   valaddr_reg:x7; val_offset:786*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 786*FLEN/8, x11, x1, x6)

inst_418:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x123 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x123 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7523; op2val:0x7523;
   valaddr_reg:x7; val_offset:788*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 788*FLEN/8, x11, x1, x6)

inst_419:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x123 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x123 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7523; op2val:0x7523;
   valaddr_reg:x7; val_offset:790*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 790*FLEN/8, x11, x1, x6)

inst_420:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x385 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x385 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6b85; op2val:0x6b85;
   valaddr_reg:x7; val_offset:792*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 792*FLEN/8, x11, x1, x6)

inst_421:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x385 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x385 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6b85; op2val:0x6b85;
   valaddr_reg:x7; val_offset:794*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 794*FLEN/8, x11, x1, x6)

inst_422:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x385 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x385 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6b85; op2val:0x6b85;
   valaddr_reg:x7; val_offset:796*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 796*FLEN/8, x11, x1, x6)

inst_423:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x385 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x385 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6b85; op2val:0x6b85;
   valaddr_reg:x7; val_offset:798*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 798*FLEN/8, x11, x1, x6)

inst_424:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x385 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x385 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6b85; op2val:0x6b85;
   valaddr_reg:x7; val_offset:800*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 800*FLEN/8, x11, x1, x6)

inst_425:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3bd and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3bd and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bbd; op2val:0x7bbd;
   valaddr_reg:x7; val_offset:802*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 802*FLEN/8, x11, x1, x6)

inst_426:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3bd and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3bd and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bbd; op2val:0x7bbd;
   valaddr_reg:x7; val_offset:804*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 804*FLEN/8, x11, x1, x6)

inst_427:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3bd and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3bd and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bbd; op2val:0x7bbd;
   valaddr_reg:x7; val_offset:806*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 806*FLEN/8, x11, x1, x6)

inst_428:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3bd and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3bd and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bbd; op2val:0x7bbd;
   valaddr_reg:x7; val_offset:808*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 808*FLEN/8, x11, x1, x6)

inst_429:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3bd and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3bd and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bbd; op2val:0x7bbd;
   valaddr_reg:x7; val_offset:810*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 810*FLEN/8, x11, x1, x6)

inst_430:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0e6 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0e6 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74e6; op2val:0x74e6;
   valaddr_reg:x7; val_offset:812*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 812*FLEN/8, x11, x1, x6)

inst_431:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0e6 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0e6 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74e6; op2val:0x74e6;
   valaddr_reg:x7; val_offset:814*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 814*FLEN/8, x11, x1, x6)

inst_432:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0e6 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0e6 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74e6; op2val:0x74e6;
   valaddr_reg:x7; val_offset:816*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 816*FLEN/8, x11, x1, x6)

inst_433:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0e6 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0e6 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74e6; op2val:0x74e6;
   valaddr_reg:x7; val_offset:818*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 818*FLEN/8, x11, x1, x6)

inst_434:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0e6 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0e6 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74e6; op2val:0x74e6;
   valaddr_reg:x7; val_offset:820*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 820*FLEN/8, x11, x1, x6)

inst_435:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f6 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0f6 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74f6; op2val:0x74f6;
   valaddr_reg:x7; val_offset:822*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 822*FLEN/8, x11, x1, x6)

inst_436:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f6 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0f6 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74f6; op2val:0x74f6;
   valaddr_reg:x7; val_offset:824*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 824*FLEN/8, x11, x1, x6)

inst_437:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f6 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0f6 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74f6; op2val:0x74f6;
   valaddr_reg:x7; val_offset:826*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 826*FLEN/8, x11, x1, x6)

inst_438:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f6 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0f6 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74f6; op2val:0x74f6;
   valaddr_reg:x7; val_offset:828*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 828*FLEN/8, x11, x1, x6)

inst_439:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f6 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0f6 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74f6; op2val:0x74f6;
   valaddr_reg:x7; val_offset:830*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 830*FLEN/8, x11, x1, x6)

inst_440:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1f2 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f2; op2val:0x79f2;
   valaddr_reg:x7; val_offset:832*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 832*FLEN/8, x11, x1, x6)

inst_441:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1f2 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f2; op2val:0x79f2;
   valaddr_reg:x7; val_offset:834*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 834*FLEN/8, x11, x1, x6)

inst_442:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1f2 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f2; op2val:0x79f2;
   valaddr_reg:x7; val_offset:836*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 836*FLEN/8, x11, x1, x6)

inst_443:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1f2 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f2; op2val:0x79f2;
   valaddr_reg:x7; val_offset:838*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 838*FLEN/8, x11, x1, x6)

inst_444:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1f2 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79f2; op2val:0x79f2;
   valaddr_reg:x7; val_offset:840*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 840*FLEN/8, x11, x1, x6)

inst_445:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x009 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x009 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7409; op2val:0x7409;
   valaddr_reg:x7; val_offset:842*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 842*FLEN/8, x11, x1, x6)

inst_446:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x009 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x009 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7409; op2val:0x7409;
   valaddr_reg:x7; val_offset:844*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 844*FLEN/8, x11, x1, x6)

inst_447:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x009 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x009 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7409; op2val:0x7409;
   valaddr_reg:x7; val_offset:846*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 846*FLEN/8, x11, x1, x6)

inst_448:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x009 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x009 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7409; op2val:0x7409;
   valaddr_reg:x7; val_offset:848*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 848*FLEN/8, x11, x1, x6)

inst_449:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x009 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x009 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7409; op2val:0x7409;
   valaddr_reg:x7; val_offset:850*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 850*FLEN/8, x11, x1, x6)

inst_450:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x306 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x306 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b06; op2val:0x7b06;
   valaddr_reg:x7; val_offset:852*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 852*FLEN/8, x11, x1, x6)

inst_451:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x306 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x306 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b06; op2val:0x7b06;
   valaddr_reg:x7; val_offset:854*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 854*FLEN/8, x11, x1, x6)

inst_452:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x306 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x306 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b06; op2val:0x7b06;
   valaddr_reg:x7; val_offset:856*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 856*FLEN/8, x11, x1, x6)

inst_453:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x306 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x306 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b06; op2val:0x7b06;
   valaddr_reg:x7; val_offset:858*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 858*FLEN/8, x11, x1, x6)

inst_454:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x306 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x306 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b06; op2val:0x7b06;
   valaddr_reg:x7; val_offset:860*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 860*FLEN/8, x11, x1, x6)

inst_455:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x28d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a8d; op2val:0x7a8d;
   valaddr_reg:x7; val_offset:862*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 862*FLEN/8, x11, x1, x6)

inst_456:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x28d and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a8d; op2val:0x7a8d;
   valaddr_reg:x7; val_offset:864*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 864*FLEN/8, x11, x1, x6)

inst_457:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x28d and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a8d; op2val:0x7a8d;
   valaddr_reg:x7; val_offset:866*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 866*FLEN/8, x11, x1, x6)

inst_458:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x28d and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a8d; op2val:0x7a8d;
   valaddr_reg:x7; val_offset:868*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 868*FLEN/8, x11, x1, x6)

inst_459:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x28d and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a8d; op2val:0x7a8d;
   valaddr_reg:x7; val_offset:870*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 870*FLEN/8, x11, x1, x6)

inst_460:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x08f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x788f; op2val:0x788f;
   valaddr_reg:x7; val_offset:872*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 872*FLEN/8, x11, x1, x6)

inst_461:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x08f and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x788f; op2val:0x788f;
   valaddr_reg:x7; val_offset:874*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 874*FLEN/8, x11, x1, x6)

inst_462:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x08f and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x788f; op2val:0x788f;
   valaddr_reg:x7; val_offset:876*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 876*FLEN/8, x11, x1, x6)

inst_463:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x08f and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x788f; op2val:0x788f;
   valaddr_reg:x7; val_offset:878*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 878*FLEN/8, x11, x1, x6)

inst_464:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x08f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x08f and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x788f; op2val:0x788f;
   valaddr_reg:x7; val_offset:880*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 880*FLEN/8, x11, x1, x6)

inst_465:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2f0 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7af0; op2val:0x7af0;
   valaddr_reg:x7; val_offset:882*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 882*FLEN/8, x11, x1, x6)

inst_466:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2f0 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7af0; op2val:0x7af0;
   valaddr_reg:x7; val_offset:884*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 884*FLEN/8, x11, x1, x6)

inst_467:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2f0 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7af0; op2val:0x7af0;
   valaddr_reg:x7; val_offset:886*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 886*FLEN/8, x11, x1, x6)

inst_468:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2f0 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7af0; op2val:0x7af0;
   valaddr_reg:x7; val_offset:888*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 888*FLEN/8, x11, x1, x6)

inst_469:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2f0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2f0 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7af0; op2val:0x7af0;
   valaddr_reg:x7; val_offset:890*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 890*FLEN/8, x11, x1, x6)

inst_470:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1a1 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79a1; op2val:0x79a1;
   valaddr_reg:x7; val_offset:892*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 892*FLEN/8, x11, x1, x6)

inst_471:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1a1 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79a1; op2val:0x79a1;
   valaddr_reg:x7; val_offset:894*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 894*FLEN/8, x11, x1, x6)

inst_472:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1a1 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79a1; op2val:0x79a1;
   valaddr_reg:x7; val_offset:896*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 896*FLEN/8, x11, x1, x6)

inst_473:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1a1 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79a1; op2val:0x79a1;
   valaddr_reg:x7; val_offset:898*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 898*FLEN/8, x11, x1, x6)

inst_474:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1a1 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79a1; op2val:0x79a1;
   valaddr_reg:x7; val_offset:900*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 900*FLEN/8, x11, x1, x6)

inst_475:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20b and fs2 == 0 and fe2 == 0x1d and fm2 == 0x20b and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x760b; op2val:0x760b;
   valaddr_reg:x7; val_offset:902*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 902*FLEN/8, x11, x1, x6)

inst_476:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20b and fs2 == 0 and fe2 == 0x1d and fm2 == 0x20b and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x760b; op2val:0x760b;
   valaddr_reg:x7; val_offset:904*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 904*FLEN/8, x11, x1, x6)

inst_477:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20b and fs2 == 0 and fe2 == 0x1d and fm2 == 0x20b and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x760b; op2val:0x760b;
   valaddr_reg:x7; val_offset:906*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 906*FLEN/8, x11, x1, x6)

inst_478:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20b and fs2 == 0 and fe2 == 0x1d and fm2 == 0x20b and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x760b; op2val:0x760b;
   valaddr_reg:x7; val_offset:908*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 908*FLEN/8, x11, x1, x6)

inst_479:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20b and fs2 == 0 and fe2 == 0x1d and fm2 == 0x20b and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x760b; op2val:0x760b;
   valaddr_reg:x7; val_offset:910*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 910*FLEN/8, x11, x1, x6)

inst_480:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x294 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x294 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7294; op2val:0x7294;
   valaddr_reg:x7; val_offset:912*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 912*FLEN/8, x11, x1, x6)

inst_481:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x294 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x294 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7294; op2val:0x7294;
   valaddr_reg:x7; val_offset:914*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 914*FLEN/8, x11, x1, x6)

inst_482:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x294 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x294 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7294; op2val:0x7294;
   valaddr_reg:x7; val_offset:916*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 916*FLEN/8, x11, x1, x6)

inst_483:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x294 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x294 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7294; op2val:0x7294;
   valaddr_reg:x7; val_offset:918*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 918*FLEN/8, x11, x1, x6)

inst_484:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x294 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x294 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7294; op2val:0x7294;
   valaddr_reg:x7; val_offset:920*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 920*FLEN/8, x11, x1, x6)

inst_485:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ec and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2ec and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x76ec; op2val:0x76ec;
   valaddr_reg:x7; val_offset:922*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 922*FLEN/8, x11, x1, x6)

inst_486:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ec and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2ec and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x76ec; op2val:0x76ec;
   valaddr_reg:x7; val_offset:924*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 924*FLEN/8, x11, x1, x6)

inst_487:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ec and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2ec and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x76ec; op2val:0x76ec;
   valaddr_reg:x7; val_offset:926*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 926*FLEN/8, x11, x1, x6)

inst_488:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ec and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2ec and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x76ec; op2val:0x76ec;
   valaddr_reg:x7; val_offset:928*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 928*FLEN/8, x11, x1, x6)

inst_489:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ec and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2ec and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x76ec; op2val:0x76ec;
   valaddr_reg:x7; val_offset:930*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 930*FLEN/8, x11, x1, x6)

inst_490:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2ae and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6eae; op2val:0x6eae;
   valaddr_reg:x7; val_offset:932*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 932*FLEN/8, x11, x1, x6)

inst_491:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2ae and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6eae; op2val:0x6eae;
   valaddr_reg:x7; val_offset:934*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 934*FLEN/8, x11, x1, x6)

inst_492:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2ae and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6eae; op2val:0x6eae;
   valaddr_reg:x7; val_offset:936*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 936*FLEN/8, x11, x1, x6)

inst_493:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2ae and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6eae; op2val:0x6eae;
   valaddr_reg:x7; val_offset:938*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 938*FLEN/8, x11, x1, x6)

inst_494:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2ae and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6eae; op2val:0x6eae;
   valaddr_reg:x7; val_offset:940*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 940*FLEN/8, x11, x1, x6)

inst_495:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0bc and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0bc and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74bc; op2val:0x74bc;
   valaddr_reg:x7; val_offset:942*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 942*FLEN/8, x11, x1, x6)

inst_496:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0bc and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0bc and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74bc; op2val:0x74bc;
   valaddr_reg:x7; val_offset:944*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 944*FLEN/8, x11, x1, x6)

inst_497:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0bc and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0bc and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74bc; op2val:0x74bc;
   valaddr_reg:x7; val_offset:946*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 946*FLEN/8, x11, x1, x6)

inst_498:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0bc and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0bc and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74bc; op2val:0x74bc;
   valaddr_reg:x7; val_offset:948*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 948*FLEN/8, x11, x1, x6)

inst_499:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0bc and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0bc and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74bc; op2val:0x74bc;
   valaddr_reg:x7; val_offset:950*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 950*FLEN/8, x11, x1, x6)

inst_500:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x134 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x134 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7534; op2val:0x7534;
   valaddr_reg:x7; val_offset:952*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 952*FLEN/8, x11, x1, x6)

inst_501:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x134 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x134 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7534; op2val:0x7534;
   valaddr_reg:x7; val_offset:954*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 954*FLEN/8, x11, x1, x6)

inst_502:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x134 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x134 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7534; op2val:0x7534;
   valaddr_reg:x7; val_offset:956*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 956*FLEN/8, x11, x1, x6)

inst_503:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x134 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x134 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7534; op2val:0x7534;
   valaddr_reg:x7; val_offset:958*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 958*FLEN/8, x11, x1, x6)

inst_504:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x134 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x134 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7534; op2val:0x7534;
   valaddr_reg:x7; val_offset:960*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 960*FLEN/8, x11, x1, x6)

inst_505:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x331 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b31; op2val:0x7b31;
   valaddr_reg:x7; val_offset:962*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 962*FLEN/8, x11, x1, x6)

inst_506:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x331 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b31; op2val:0x7b31;
   valaddr_reg:x7; val_offset:964*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 964*FLEN/8, x11, x1, x6)

inst_507:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x331 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b31; op2val:0x7b31;
   valaddr_reg:x7; val_offset:966*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 966*FLEN/8, x11, x1, x6)

inst_508:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x331 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b31; op2val:0x7b31;
   valaddr_reg:x7; val_offset:968*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 968*FLEN/8, x11, x1, x6)

inst_509:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x331 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b31; op2val:0x7b31;
   valaddr_reg:x7; val_offset:970*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 970*FLEN/8, x11, x1, x6)

inst_510:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x26c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x26c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x726c; op2val:0x726c;
   valaddr_reg:x7; val_offset:972*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 972*FLEN/8, x11, x1, x6)

inst_511:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x26c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x26c and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x726c; op2val:0x726c;
   valaddr_reg:x7; val_offset:974*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 974*FLEN/8, x11, x1, x6)

inst_512:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x26c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x26c and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x726c; op2val:0x726c;
   valaddr_reg:x7; val_offset:976*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 976*FLEN/8, x11, x1, x6)

inst_513:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x26c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x26c and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x726c; op2val:0x726c;
   valaddr_reg:x7; val_offset:978*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 978*FLEN/8, x11, x1, x6)

inst_514:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x26c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x26c and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x726c; op2val:0x726c;
   valaddr_reg:x7; val_offset:980*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 980*FLEN/8, x11, x1, x6)

inst_515:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3e4 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7be4; op2val:0x7be4;
   valaddr_reg:x7; val_offset:982*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 982*FLEN/8, x11, x1, x6)

inst_516:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3e4 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7be4; op2val:0x7be4;
   valaddr_reg:x7; val_offset:984*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 984*FLEN/8, x11, x1, x6)

inst_517:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3e4 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7be4; op2val:0x7be4;
   valaddr_reg:x7; val_offset:986*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 986*FLEN/8, x11, x1, x6)

inst_518:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3e4 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7be4; op2val:0x7be4;
   valaddr_reg:x7; val_offset:988*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 988*FLEN/8, x11, x1, x6)

inst_519:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3e4 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7be4; op2val:0x7be4;
   valaddr_reg:x7; val_offset:990*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 990*FLEN/8, x11, x1, x6)

inst_520:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16c and fs2 == 0 and fe2 == 0x1d and fm2 == 0x16c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x756c; op2val:0x756c;
   valaddr_reg:x7; val_offset:992*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 992*FLEN/8, x11, x1, x6)

inst_521:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16c and fs2 == 0 and fe2 == 0x1d and fm2 == 0x16c and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x756c; op2val:0x756c;
   valaddr_reg:x7; val_offset:994*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 994*FLEN/8, x11, x1, x6)

inst_522:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16c and fs2 == 0 and fe2 == 0x1d and fm2 == 0x16c and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x756c; op2val:0x756c;
   valaddr_reg:x7; val_offset:996*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 996*FLEN/8, x11, x1, x6)

inst_523:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16c and fs2 == 0 and fe2 == 0x1d and fm2 == 0x16c and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x756c; op2val:0x756c;
   valaddr_reg:x7; val_offset:998*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 998*FLEN/8, x11, x1, x6)

inst_524:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16c and fs2 == 0 and fe2 == 0x1d and fm2 == 0x16c and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x756c; op2val:0x756c;
   valaddr_reg:x7; val_offset:1000*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1000*FLEN/8, x11, x1, x6)

inst_525:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x164 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x164 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7964; op2val:0x7964;
   valaddr_reg:x7; val_offset:1002*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1002*FLEN/8, x11, x1, x6)

inst_526:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x164 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x164 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7964; op2val:0x7964;
   valaddr_reg:x7; val_offset:1004*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1004*FLEN/8, x11, x1, x6)

inst_527:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x164 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x164 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7964; op2val:0x7964;
   valaddr_reg:x7; val_offset:1006*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1006*FLEN/8, x11, x1, x6)

inst_528:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x164 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x164 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7964; op2val:0x7964;
   valaddr_reg:x7; val_offset:1008*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1008*FLEN/8, x11, x1, x6)

inst_529:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x164 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x164 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7964; op2val:0x7964;
   valaddr_reg:x7; val_offset:1010*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1010*FLEN/8, x11, x1, x6)

inst_530:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x374 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x374 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b74; op2val:0x7b74;
   valaddr_reg:x7; val_offset:1012*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1012*FLEN/8, x11, x1, x6)

inst_531:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x374 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x374 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b74; op2val:0x7b74;
   valaddr_reg:x7; val_offset:1014*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1014*FLEN/8, x11, x1, x6)

inst_532:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x374 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x374 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b74; op2val:0x7b74;
   valaddr_reg:x7; val_offset:1016*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1016*FLEN/8, x11, x1, x6)

inst_533:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x374 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x374 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b74; op2val:0x7b74;
   valaddr_reg:x7; val_offset:1018*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1018*FLEN/8, x11, x1, x6)

inst_534:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x374 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x374 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b74; op2val:0x7b74;
   valaddr_reg:x7; val_offset:1020*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1020*FLEN/8, x11, x1, x6)

inst_535:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3bf and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3bf and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77bf; op2val:0x77bf;
   valaddr_reg:x7; val_offset:1022*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1022*FLEN/8, x11, x1, x6)

inst_536:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3bf and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3bf and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77bf; op2val:0x77bf;
   valaddr_reg:x7; val_offset:1024*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1024*FLEN/8, x11, x1, x6)

inst_537:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3bf and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3bf and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77bf; op2val:0x77bf;
   valaddr_reg:x7; val_offset:1026*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1026*FLEN/8, x11, x1, x6)
RVTEST_SIGBASE(x1,signature_x1_6)

inst_538:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3bf and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3bf and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77bf; op2val:0x77bf;
   valaddr_reg:x7; val_offset:1028*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1028*FLEN/8, x11, x1, x6)

inst_539:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3bf and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3bf and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77bf; op2val:0x77bf;
   valaddr_reg:x7; val_offset:1030*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1030*FLEN/8, x11, x1, x6)

inst_540:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x381 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x381 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7381; op2val:0x7381;
   valaddr_reg:x7; val_offset:1032*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1032*FLEN/8, x11, x1, x6)

inst_541:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x381 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x381 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7381; op2val:0x7381;
   valaddr_reg:x7; val_offset:1034*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1034*FLEN/8, x11, x1, x6)

inst_542:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x381 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x381 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7381; op2val:0x7381;
   valaddr_reg:x7; val_offset:1036*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1036*FLEN/8, x11, x1, x6)

inst_543:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x381 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x381 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7381; op2val:0x7381;
   valaddr_reg:x7; val_offset:1038*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1038*FLEN/8, x11, x1, x6)

inst_544:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x381 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x381 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7381; op2val:0x7381;
   valaddr_reg:x7; val_offset:1040*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1040*FLEN/8, x11, x1, x6)

inst_545:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x16a and fs2 == 0 and fe2 == 0x1b and fm2 == 0x16a and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d6a; op2val:0x6d6a;
   valaddr_reg:x7; val_offset:1042*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1042*FLEN/8, x11, x1, x6)

inst_546:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x16a and fs2 == 0 and fe2 == 0x1b and fm2 == 0x16a and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d6a; op2val:0x6d6a;
   valaddr_reg:x7; val_offset:1044*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1044*FLEN/8, x11, x1, x6)

inst_547:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x16a and fs2 == 0 and fe2 == 0x1b and fm2 == 0x16a and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d6a; op2val:0x6d6a;
   valaddr_reg:x7; val_offset:1046*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1046*FLEN/8, x11, x1, x6)

inst_548:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x16a and fs2 == 0 and fe2 == 0x1b and fm2 == 0x16a and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d6a; op2val:0x6d6a;
   valaddr_reg:x7; val_offset:1048*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1048*FLEN/8, x11, x1, x6)

inst_549:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x16a and fs2 == 0 and fe2 == 0x1b and fm2 == 0x16a and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d6a; op2val:0x6d6a;
   valaddr_reg:x7; val_offset:1050*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1050*FLEN/8, x11, x1, x6)

inst_550:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x348 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x348 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b48; op2val:0x7b48;
   valaddr_reg:x7; val_offset:1052*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1052*FLEN/8, x11, x1, x6)

inst_551:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x348 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x348 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b48; op2val:0x7b48;
   valaddr_reg:x7; val_offset:1054*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1054*FLEN/8, x11, x1, x6)

inst_552:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x348 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x348 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b48; op2val:0x7b48;
   valaddr_reg:x7; val_offset:1056*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1056*FLEN/8, x11, x1, x6)

inst_553:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x348 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x348 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b48; op2val:0x7b48;
   valaddr_reg:x7; val_offset:1058*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1058*FLEN/8, x11, x1, x6)

inst_554:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x348 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x348 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b48; op2val:0x7b48;
   valaddr_reg:x7; val_offset:1060*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1060*FLEN/8, x11, x1, x6)

inst_555:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x211 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x211 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a11; op2val:0x7a11;
   valaddr_reg:x7; val_offset:1062*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1062*FLEN/8, x11, x1, x6)

inst_556:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x211 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x211 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a11; op2val:0x7a11;
   valaddr_reg:x7; val_offset:1064*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1064*FLEN/8, x11, x1, x6)

inst_557:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x211 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x211 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a11; op2val:0x7a11;
   valaddr_reg:x7; val_offset:1066*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1066*FLEN/8, x11, x1, x6)

inst_558:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x211 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x211 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a11; op2val:0x7a11;
   valaddr_reg:x7; val_offset:1068*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1068*FLEN/8, x11, x1, x6)

inst_559:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x211 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x211 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a11; op2val:0x7a11;
   valaddr_reg:x7; val_offset:1070*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1070*FLEN/8, x11, x1, x6)

inst_560:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b9 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab9; op2val:0x7ab9;
   valaddr_reg:x7; val_offset:1072*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1072*FLEN/8, x11, x1, x6)

inst_561:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b9 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab9; op2val:0x7ab9;
   valaddr_reg:x7; val_offset:1074*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1074*FLEN/8, x11, x1, x6)

inst_562:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b9 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab9; op2val:0x7ab9;
   valaddr_reg:x7; val_offset:1076*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1076*FLEN/8, x11, x1, x6)

inst_563:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b9 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab9; op2val:0x7ab9;
   valaddr_reg:x7; val_offset:1078*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1078*FLEN/8, x11, x1, x6)

inst_564:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2b9 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab9; op2val:0x7ab9;
   valaddr_reg:x7; val_offset:1080*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1080*FLEN/8, x11, x1, x6)

inst_565:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x171 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x171 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7571; op2val:0x7571;
   valaddr_reg:x7; val_offset:1082*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1082*FLEN/8, x11, x1, x6)

inst_566:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x171 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x171 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7571; op2val:0x7571;
   valaddr_reg:x7; val_offset:1084*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1084*FLEN/8, x11, x1, x6)

inst_567:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x171 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x171 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7571; op2val:0x7571;
   valaddr_reg:x7; val_offset:1086*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1086*FLEN/8, x11, x1, x6)

inst_568:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x171 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x171 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7571; op2val:0x7571;
   valaddr_reg:x7; val_offset:1088*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1088*FLEN/8, x11, x1, x6)

inst_569:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x171 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x171 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7571; op2val:0x7571;
   valaddr_reg:x7; val_offset:1090*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1090*FLEN/8, x11, x1, x6)

inst_570:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ef and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aef; op2val:0x7aef;
   valaddr_reg:x7; val_offset:1092*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1092*FLEN/8, x11, x1, x6)

inst_571:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ef and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aef; op2val:0x7aef;
   valaddr_reg:x7; val_offset:1094*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1094*FLEN/8, x11, x1, x6)

inst_572:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ef and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aef; op2val:0x7aef;
   valaddr_reg:x7; val_offset:1096*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1096*FLEN/8, x11, x1, x6)

inst_573:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ef and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aef; op2val:0x7aef;
   valaddr_reg:x7; val_offset:1098*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1098*FLEN/8, x11, x1, x6)

inst_574:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ef and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aef; op2val:0x7aef;
   valaddr_reg:x7; val_offset:1100*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1100*FLEN/8, x11, x1, x6)

inst_575:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a1 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba1; op2val:0x7ba1;
   valaddr_reg:x7; val_offset:1102*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1102*FLEN/8, x11, x1, x6)

inst_576:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a1 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba1; op2val:0x7ba1;
   valaddr_reg:x7; val_offset:1104*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1104*FLEN/8, x11, x1, x6)

inst_577:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a1 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba1; op2val:0x7ba1;
   valaddr_reg:x7; val_offset:1106*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1106*FLEN/8, x11, x1, x6)

inst_578:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a1 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba1; op2val:0x7ba1;
   valaddr_reg:x7; val_offset:1108*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1108*FLEN/8, x11, x1, x6)

inst_579:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3a1 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ba1; op2val:0x7ba1;
   valaddr_reg:x7; val_offset:1110*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1110*FLEN/8, x11, x1, x6)

inst_580:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x054 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x054 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7054; op2val:0x7054;
   valaddr_reg:x7; val_offset:1112*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1112*FLEN/8, x11, x1, x6)

inst_581:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x054 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x054 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7054; op2val:0x7054;
   valaddr_reg:x7; val_offset:1114*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1114*FLEN/8, x11, x1, x6)

inst_582:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x054 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x054 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7054; op2val:0x7054;
   valaddr_reg:x7; val_offset:1116*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1116*FLEN/8, x11, x1, x6)

inst_583:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x054 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x054 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7054; op2val:0x7054;
   valaddr_reg:x7; val_offset:1118*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1118*FLEN/8, x11, x1, x6)

inst_584:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x054 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x054 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7054; op2val:0x7054;
   valaddr_reg:x7; val_offset:1120*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1120*FLEN/8, x11, x1, x6)

inst_585:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2ab and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2ab and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6eab; op2val:0x6eab;
   valaddr_reg:x7; val_offset:1122*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1122*FLEN/8, x11, x1, x6)

inst_586:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2ab and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2ab and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6eab; op2val:0x6eab;
   valaddr_reg:x7; val_offset:1124*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1124*FLEN/8, x11, x1, x6)

inst_587:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2ab and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2ab and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6eab; op2val:0x6eab;
   valaddr_reg:x7; val_offset:1126*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1126*FLEN/8, x11, x1, x6)

inst_588:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2ab and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2ab and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6eab; op2val:0x6eab;
   valaddr_reg:x7; val_offset:1128*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1128*FLEN/8, x11, x1, x6)

inst_589:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2ab and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2ab and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6eab; op2val:0x6eab;
   valaddr_reg:x7; val_offset:1130*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1130*FLEN/8, x11, x1, x6)

inst_590:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0ae and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0ae and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6cae; op2val:0x6cae;
   valaddr_reg:x7; val_offset:1132*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1132*FLEN/8, x11, x1, x6)

inst_591:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0ae and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0ae and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6cae; op2val:0x6cae;
   valaddr_reg:x7; val_offset:1134*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1134*FLEN/8, x11, x1, x6)

inst_592:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0ae and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0ae and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6cae; op2val:0x6cae;
   valaddr_reg:x7; val_offset:1136*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1136*FLEN/8, x11, x1, x6)

inst_593:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0ae and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0ae and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6cae; op2val:0x6cae;
   valaddr_reg:x7; val_offset:1138*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1138*FLEN/8, x11, x1, x6)

inst_594:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0ae and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0ae and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6cae; op2val:0x6cae;
   valaddr_reg:x7; val_offset:1140*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1140*FLEN/8, x11, x1, x6)

inst_595:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x24d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x24d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a4d; op2val:0x7a4d;
   valaddr_reg:x7; val_offset:1142*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1142*FLEN/8, x11, x1, x6)

inst_596:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x24d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x24d and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a4d; op2val:0x7a4d;
   valaddr_reg:x7; val_offset:1144*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1144*FLEN/8, x11, x1, x6)

inst_597:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x24d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x24d and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a4d; op2val:0x7a4d;
   valaddr_reg:x7; val_offset:1146*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1146*FLEN/8, x11, x1, x6)

inst_598:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x24d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x24d and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a4d; op2val:0x7a4d;
   valaddr_reg:x7; val_offset:1148*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1148*FLEN/8, x11, x1, x6)

inst_599:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x24d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x24d and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a4d; op2val:0x7a4d;
   valaddr_reg:x7; val_offset:1150*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1150*FLEN/8, x11, x1, x6)

inst_600:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x173 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x173 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7573; op2val:0x7573;
   valaddr_reg:x7; val_offset:1152*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1152*FLEN/8, x11, x1, x6)

inst_601:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x173 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x173 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7573; op2val:0x7573;
   valaddr_reg:x7; val_offset:1154*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1154*FLEN/8, x11, x1, x6)

inst_602:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x173 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x173 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7573; op2val:0x7573;
   valaddr_reg:x7; val_offset:1156*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1156*FLEN/8, x11, x1, x6)

inst_603:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x173 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x173 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7573; op2val:0x7573;
   valaddr_reg:x7; val_offset:1158*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1158*FLEN/8, x11, x1, x6)

inst_604:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x173 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x173 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7573; op2val:0x7573;
   valaddr_reg:x7; val_offset:1160*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1160*FLEN/8, x11, x1, x6)

inst_605:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x240 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x240 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a40; op2val:0x7a40;
   valaddr_reg:x7; val_offset:1162*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1162*FLEN/8, x11, x1, x6)

inst_606:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x240 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x240 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a40; op2val:0x7a40;
   valaddr_reg:x7; val_offset:1164*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1164*FLEN/8, x11, x1, x6)

inst_607:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x240 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x240 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a40; op2val:0x7a40;
   valaddr_reg:x7; val_offset:1166*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1166*FLEN/8, x11, x1, x6)

inst_608:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x240 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x240 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a40; op2val:0x7a40;
   valaddr_reg:x7; val_offset:1168*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1168*FLEN/8, x11, x1, x6)

inst_609:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x240 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x240 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a40; op2val:0x7a40;
   valaddr_reg:x7; val_offset:1170*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1170*FLEN/8, x11, x1, x6)

inst_610:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x090 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x090 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7890; op2val:0x7890;
   valaddr_reg:x7; val_offset:1172*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1172*FLEN/8, x11, x1, x6)

inst_611:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x090 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x090 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7890; op2val:0x7890;
   valaddr_reg:x7; val_offset:1174*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1174*FLEN/8, x11, x1, x6)

inst_612:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x090 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x090 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7890; op2val:0x7890;
   valaddr_reg:x7; val_offset:1176*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1176*FLEN/8, x11, x1, x6)

inst_613:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x090 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x090 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7890; op2val:0x7890;
   valaddr_reg:x7; val_offset:1178*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1178*FLEN/8, x11, x1, x6)

inst_614:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x090 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x090 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7890; op2val:0x7890;
   valaddr_reg:x7; val_offset:1180*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1180*FLEN/8, x11, x1, x6)

inst_615:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x13a and fs2 == 0 and fe2 == 0x1b and fm2 == 0x13a and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d3a; op2val:0x6d3a;
   valaddr_reg:x7; val_offset:1182*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1182*FLEN/8, x11, x1, x6)

inst_616:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x13a and fs2 == 0 and fe2 == 0x1b and fm2 == 0x13a and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d3a; op2val:0x6d3a;
   valaddr_reg:x7; val_offset:1184*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1184*FLEN/8, x11, x1, x6)

inst_617:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x13a and fs2 == 0 and fe2 == 0x1b and fm2 == 0x13a and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d3a; op2val:0x6d3a;
   valaddr_reg:x7; val_offset:1186*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1186*FLEN/8, x11, x1, x6)

inst_618:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x13a and fs2 == 0 and fe2 == 0x1b and fm2 == 0x13a and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d3a; op2val:0x6d3a;
   valaddr_reg:x7; val_offset:1188*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1188*FLEN/8, x11, x1, x6)

inst_619:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x13a and fs2 == 0 and fe2 == 0x1b and fm2 == 0x13a and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d3a; op2val:0x6d3a;
   valaddr_reg:x7; val_offset:1190*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1190*FLEN/8, x11, x1, x6)

inst_620:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x31f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x31f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b1f; op2val:0x7b1f;
   valaddr_reg:x7; val_offset:1192*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1192*FLEN/8, x11, x1, x6)

inst_621:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x31f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x31f and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b1f; op2val:0x7b1f;
   valaddr_reg:x7; val_offset:1194*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1194*FLEN/8, x11, x1, x6)

inst_622:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x31f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x31f and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b1f; op2val:0x7b1f;
   valaddr_reg:x7; val_offset:1196*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1196*FLEN/8, x11, x1, x6)

inst_623:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x31f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x31f and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b1f; op2val:0x7b1f;
   valaddr_reg:x7; val_offset:1198*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1198*FLEN/8, x11, x1, x6)

inst_624:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x31f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x31f and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b1f; op2val:0x7b1f;
   valaddr_reg:x7; val_offset:1200*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1200*FLEN/8, x11, x1, x6)

inst_625:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x365 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x365 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b65; op2val:0x7b65;
   valaddr_reg:x7; val_offset:1202*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1202*FLEN/8, x11, x1, x6)

inst_626:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x365 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x365 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b65; op2val:0x7b65;
   valaddr_reg:x7; val_offset:1204*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1204*FLEN/8, x11, x1, x6)

inst_627:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x365 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x365 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b65; op2val:0x7b65;
   valaddr_reg:x7; val_offset:1206*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1206*FLEN/8, x11, x1, x6)

inst_628:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x365 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x365 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b65; op2val:0x7b65;
   valaddr_reg:x7; val_offset:1208*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1208*FLEN/8, x11, x1, x6)

inst_629:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x365 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x365 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b65; op2val:0x7b65;
   valaddr_reg:x7; val_offset:1210*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1210*FLEN/8, x11, x1, x6)

inst_630:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x06e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x06e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x746e; op2val:0x746e;
   valaddr_reg:x7; val_offset:1212*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1212*FLEN/8, x11, x1, x6)

inst_631:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x06e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x06e and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x746e; op2val:0x746e;
   valaddr_reg:x7; val_offset:1214*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1214*FLEN/8, x11, x1, x6)

inst_632:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x06e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x06e and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x746e; op2val:0x746e;
   valaddr_reg:x7; val_offset:1216*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1216*FLEN/8, x11, x1, x6)

inst_633:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x06e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x06e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x746e; op2val:0x746e;
   valaddr_reg:x7; val_offset:1218*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1218*FLEN/8, x11, x1, x6)

inst_634:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x06e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x06e and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x746e; op2val:0x746e;
   valaddr_reg:x7; val_offset:1220*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1220*FLEN/8, x11, x1, x6)

inst_635:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x29e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x29e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a9e; op2val:0x7a9e;
   valaddr_reg:x7; val_offset:1222*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1222*FLEN/8, x11, x1, x6)

inst_636:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x29e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x29e and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a9e; op2val:0x7a9e;
   valaddr_reg:x7; val_offset:1224*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1224*FLEN/8, x11, x1, x6)

inst_637:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x29e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x29e and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a9e; op2val:0x7a9e;
   valaddr_reg:x7; val_offset:1226*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1226*FLEN/8, x11, x1, x6)

inst_638:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x29e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x29e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a9e; op2val:0x7a9e;
   valaddr_reg:x7; val_offset:1228*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1228*FLEN/8, x11, x1, x6)

inst_639:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x29e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x29e and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a9e; op2val:0x7a9e;
   valaddr_reg:x7; val_offset:1230*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1230*FLEN/8, x11, x1, x6)

inst_640:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x15c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x795c; op2val:0x795c;
   valaddr_reg:x7; val_offset:1232*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1232*FLEN/8, x11, x1, x6)

inst_641:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x15c and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x795c; op2val:0x795c;
   valaddr_reg:x7; val_offset:1234*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1234*FLEN/8, x11, x1, x6)

inst_642:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x15c and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x795c; op2val:0x795c;
   valaddr_reg:x7; val_offset:1236*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1236*FLEN/8, x11, x1, x6)

inst_643:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x15c and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x795c; op2val:0x795c;
   valaddr_reg:x7; val_offset:1238*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1238*FLEN/8, x11, x1, x6)

inst_644:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x15c and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x795c; op2val:0x795c;
   valaddr_reg:x7; val_offset:1240*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1240*FLEN/8, x11, x1, x6)

inst_645:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x35d and fs2 == 0 and fe2 == 0x1b and fm2 == 0x35d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f5d; op2val:0x6f5d;
   valaddr_reg:x7; val_offset:1242*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1242*FLEN/8, x11, x1, x6)

inst_646:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x35d and fs2 == 0 and fe2 == 0x1b and fm2 == 0x35d and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f5d; op2val:0x6f5d;
   valaddr_reg:x7; val_offset:1244*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1244*FLEN/8, x11, x1, x6)

inst_647:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x35d and fs2 == 0 and fe2 == 0x1b and fm2 == 0x35d and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f5d; op2val:0x6f5d;
   valaddr_reg:x7; val_offset:1246*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1246*FLEN/8, x11, x1, x6)

inst_648:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x35d and fs2 == 0 and fe2 == 0x1b and fm2 == 0x35d and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f5d; op2val:0x6f5d;
   valaddr_reg:x7; val_offset:1248*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1248*FLEN/8, x11, x1, x6)

inst_649:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x35d and fs2 == 0 and fe2 == 0x1b and fm2 == 0x35d and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f5d; op2val:0x6f5d;
   valaddr_reg:x7; val_offset:1250*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1250*FLEN/8, x11, x1, x6)

inst_650:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x11f and fs2 == 0 and fe2 == 0x1a and fm2 == 0x11f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x691f; op2val:0x691f;
   valaddr_reg:x7; val_offset:1252*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1252*FLEN/8, x11, x1, x6)

inst_651:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x11f and fs2 == 0 and fe2 == 0x1a and fm2 == 0x11f and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x691f; op2val:0x691f;
   valaddr_reg:x7; val_offset:1254*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1254*FLEN/8, x11, x1, x6)

inst_652:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x11f and fs2 == 0 and fe2 == 0x1a and fm2 == 0x11f and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x691f; op2val:0x691f;
   valaddr_reg:x7; val_offset:1256*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1256*FLEN/8, x11, x1, x6)

inst_653:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x11f and fs2 == 0 and fe2 == 0x1a and fm2 == 0x11f and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x691f; op2val:0x691f;
   valaddr_reg:x7; val_offset:1258*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1258*FLEN/8, x11, x1, x6)

inst_654:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x11f and fs2 == 0 and fe2 == 0x1a and fm2 == 0x11f and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x691f; op2val:0x691f;
   valaddr_reg:x7; val_offset:1260*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1260*FLEN/8, x11, x1, x6)

inst_655:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3e6 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7be6; op2val:0x7be6;
   valaddr_reg:x7; val_offset:1262*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1262*FLEN/8, x11, x1, x6)

inst_656:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3e6 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7be6; op2val:0x7be6;
   valaddr_reg:x7; val_offset:1264*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1264*FLEN/8, x11, x1, x6)

inst_657:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3e6 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7be6; op2val:0x7be6;
   valaddr_reg:x7; val_offset:1266*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1266*FLEN/8, x11, x1, x6)

inst_658:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3e6 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7be6; op2val:0x7be6;
   valaddr_reg:x7; val_offset:1268*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1268*FLEN/8, x11, x1, x6)

inst_659:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3e6 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7be6; op2val:0x7be6;
   valaddr_reg:x7; val_offset:1270*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1270*FLEN/8, x11, x1, x6)

inst_660:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x364 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x364 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f64; op2val:0x6f64;
   valaddr_reg:x7; val_offset:1272*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1272*FLEN/8, x11, x1, x6)

inst_661:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x364 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x364 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f64; op2val:0x6f64;
   valaddr_reg:x7; val_offset:1274*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1274*FLEN/8, x11, x1, x6)

inst_662:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x364 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x364 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f64; op2val:0x6f64;
   valaddr_reg:x7; val_offset:1276*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1276*FLEN/8, x11, x1, x6)

inst_663:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x364 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x364 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f64; op2val:0x6f64;
   valaddr_reg:x7; val_offset:1278*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1278*FLEN/8, x11, x1, x6)

inst_664:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x364 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x364 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6f64; op2val:0x6f64;
   valaddr_reg:x7; val_offset:1280*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1280*FLEN/8, x11, x1, x6)

inst_665:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3b8 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3b8 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x73b8; op2val:0x73b8;
   valaddr_reg:x7; val_offset:1282*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1282*FLEN/8, x11, x1, x6)
RVTEST_SIGBASE(x1,signature_x1_7)

inst_666:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3b8 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3b8 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x73b8; op2val:0x73b8;
   valaddr_reg:x7; val_offset:1284*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1284*FLEN/8, x11, x1, x6)

inst_667:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3b8 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3b8 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x73b8; op2val:0x73b8;
   valaddr_reg:x7; val_offset:1286*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1286*FLEN/8, x11, x1, x6)

inst_668:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3b8 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3b8 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x73b8; op2val:0x73b8;
   valaddr_reg:x7; val_offset:1288*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1288*FLEN/8, x11, x1, x6)

inst_669:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3b8 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3b8 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x73b8; op2val:0x73b8;
   valaddr_reg:x7; val_offset:1290*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1290*FLEN/8, x11, x1, x6)

inst_670:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x294 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x294 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e94; op2val:0x6e94;
   valaddr_reg:x7; val_offset:1292*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1292*FLEN/8, x11, x1, x6)

inst_671:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x294 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x294 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e94; op2val:0x6e94;
   valaddr_reg:x7; val_offset:1294*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1294*FLEN/8, x11, x1, x6)

inst_672:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x294 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x294 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e94; op2val:0x6e94;
   valaddr_reg:x7; val_offset:1296*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1296*FLEN/8, x11, x1, x6)

inst_673:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x294 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x294 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e94; op2val:0x6e94;
   valaddr_reg:x7; val_offset:1298*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1298*FLEN/8, x11, x1, x6)

inst_674:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x294 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x294 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e94; op2val:0x6e94;
   valaddr_reg:x7; val_offset:1300*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1300*FLEN/8, x11, x1, x6)

inst_675:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20c and fs2 == 0 and fe2 == 0x1d and fm2 == 0x20c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x760c; op2val:0x760c;
   valaddr_reg:x7; val_offset:1302*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1302*FLEN/8, x11, x1, x6)

inst_676:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20c and fs2 == 0 and fe2 == 0x1d and fm2 == 0x20c and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x760c; op2val:0x760c;
   valaddr_reg:x7; val_offset:1304*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1304*FLEN/8, x11, x1, x6)

inst_677:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20c and fs2 == 0 and fe2 == 0x1d and fm2 == 0x20c and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x760c; op2val:0x760c;
   valaddr_reg:x7; val_offset:1306*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1306*FLEN/8, x11, x1, x6)

inst_678:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20c and fs2 == 0 and fe2 == 0x1d and fm2 == 0x20c and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x760c; op2val:0x760c;
   valaddr_reg:x7; val_offset:1308*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1308*FLEN/8, x11, x1, x6)

inst_679:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x20c and fs2 == 0 and fe2 == 0x1d and fm2 == 0x20c and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x760c; op2val:0x760c;
   valaddr_reg:x7; val_offset:1310*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1310*FLEN/8, x11, x1, x6)

inst_680:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x345 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x345 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b45; op2val:0x7b45;
   valaddr_reg:x7; val_offset:1312*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1312*FLEN/8, x11, x1, x6)

inst_681:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x345 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x345 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b45; op2val:0x7b45;
   valaddr_reg:x7; val_offset:1314*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1314*FLEN/8, x11, x1, x6)

inst_682:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x345 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x345 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b45; op2val:0x7b45;
   valaddr_reg:x7; val_offset:1316*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1316*FLEN/8, x11, x1, x6)

inst_683:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x345 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x345 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b45; op2val:0x7b45;
   valaddr_reg:x7; val_offset:1318*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1318*FLEN/8, x11, x1, x6)

inst_684:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x345 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x345 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b45; op2val:0x7b45;
   valaddr_reg:x7; val_offset:1320*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1320*FLEN/8, x11, x1, x6)

inst_685:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x00d and fs2 == 0 and fe2 == 0x1d and fm2 == 0x00d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x740d; op2val:0x740d;
   valaddr_reg:x7; val_offset:1322*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1322*FLEN/8, x11, x1, x6)

inst_686:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x00d and fs2 == 0 and fe2 == 0x1d and fm2 == 0x00d and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x740d; op2val:0x740d;
   valaddr_reg:x7; val_offset:1324*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1324*FLEN/8, x11, x1, x6)

inst_687:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x00d and fs2 == 0 and fe2 == 0x1d and fm2 == 0x00d and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x740d; op2val:0x740d;
   valaddr_reg:x7; val_offset:1326*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1326*FLEN/8, x11, x1, x6)

inst_688:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x00d and fs2 == 0 and fe2 == 0x1d and fm2 == 0x00d and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x740d; op2val:0x740d;
   valaddr_reg:x7; val_offset:1328*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1328*FLEN/8, x11, x1, x6)

inst_689:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x00d and fs2 == 0 and fe2 == 0x1d and fm2 == 0x00d and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x740d; op2val:0x740d;
   valaddr_reg:x7; val_offset:1330*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1330*FLEN/8, x11, x1, x6)

inst_690:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x267 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x267 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e67; op2val:0x6e67;
   valaddr_reg:x7; val_offset:1332*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1332*FLEN/8, x11, x1, x6)

inst_691:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x267 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x267 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e67; op2val:0x6e67;
   valaddr_reg:x7; val_offset:1334*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1334*FLEN/8, x11, x1, x6)

inst_692:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x267 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x267 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e67; op2val:0x6e67;
   valaddr_reg:x7; val_offset:1336*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1336*FLEN/8, x11, x1, x6)

inst_693:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x267 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x267 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e67; op2val:0x6e67;
   valaddr_reg:x7; val_offset:1338*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1338*FLEN/8, x11, x1, x6)

inst_694:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x267 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x267 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6e67; op2val:0x6e67;
   valaddr_reg:x7; val_offset:1340*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1340*FLEN/8, x11, x1, x6)

inst_695:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x112 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x112 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6912; op2val:0x6912;
   valaddr_reg:x7; val_offset:1342*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1342*FLEN/8, x11, x1, x6)

inst_696:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x112 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x112 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6912; op2val:0x6912;
   valaddr_reg:x7; val_offset:1344*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1344*FLEN/8, x11, x1, x6)

inst_697:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x112 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x112 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6912; op2val:0x6912;
   valaddr_reg:x7; val_offset:1346*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1346*FLEN/8, x11, x1, x6)

inst_698:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x112 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x112 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6912; op2val:0x6912;
   valaddr_reg:x7; val_offset:1348*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1348*FLEN/8, x11, x1, x6)

inst_699:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x112 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x112 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6912; op2val:0x6912;
   valaddr_reg:x7; val_offset:1350*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1350*FLEN/8, x11, x1, x6)

inst_700:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3db and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3db and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bdb; op2val:0x7bdb;
   valaddr_reg:x7; val_offset:1352*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1352*FLEN/8, x11, x1, x6)

inst_701:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3db and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3db and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bdb; op2val:0x7bdb;
   valaddr_reg:x7; val_offset:1354*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1354*FLEN/8, x11, x1, x6)

inst_702:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3db and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3db and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bdb; op2val:0x7bdb;
   valaddr_reg:x7; val_offset:1356*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1356*FLEN/8, x11, x1, x6)

inst_703:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3db and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3db and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bdb; op2val:0x7bdb;
   valaddr_reg:x7; val_offset:1358*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1358*FLEN/8, x11, x1, x6)

inst_704:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3db and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3db and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bdb; op2val:0x7bdb;
   valaddr_reg:x7; val_offset:1360*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1360*FLEN/8, x11, x1, x6)

inst_705:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0c5 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c5; op2val:0x78c5;
   valaddr_reg:x7; val_offset:1362*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1362*FLEN/8, x11, x1, x6)

inst_706:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0c5 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c5; op2val:0x78c5;
   valaddr_reg:x7; val_offset:1364*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1364*FLEN/8, x11, x1, x6)

inst_707:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0c5 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c5; op2val:0x78c5;
   valaddr_reg:x7; val_offset:1366*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1366*FLEN/8, x11, x1, x6)

inst_708:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0c5 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c5; op2val:0x78c5;
   valaddr_reg:x7; val_offset:1368*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1368*FLEN/8, x11, x1, x6)

inst_709:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0c5 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x78c5; op2val:0x78c5;
   valaddr_reg:x7; val_offset:1370*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1370*FLEN/8, x11, x1, x6)

inst_710:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x102 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x102 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7502; op2val:0x7502;
   valaddr_reg:x7; val_offset:1372*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1372*FLEN/8, x11, x1, x6)

inst_711:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x102 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x102 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7502; op2val:0x7502;
   valaddr_reg:x7; val_offset:1374*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1374*FLEN/8, x11, x1, x6)

inst_712:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x102 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x102 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7502; op2val:0x7502;
   valaddr_reg:x7; val_offset:1376*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1376*FLEN/8, x11, x1, x6)

inst_713:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x102 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x102 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7502; op2val:0x7502;
   valaddr_reg:x7; val_offset:1378*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1378*FLEN/8, x11, x1, x6)

inst_714:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x102 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x102 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7502; op2val:0x7502;
   valaddr_reg:x7; val_offset:1380*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1380*FLEN/8, x11, x1, x6)

inst_715:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x34d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x34d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b4d; op2val:0x7b4d;
   valaddr_reg:x7; val_offset:1382*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1382*FLEN/8, x11, x1, x6)

inst_716:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x34d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x34d and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b4d; op2val:0x7b4d;
   valaddr_reg:x7; val_offset:1384*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1384*FLEN/8, x11, x1, x6)

inst_717:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x34d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x34d and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b4d; op2val:0x7b4d;
   valaddr_reg:x7; val_offset:1386*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1386*FLEN/8, x11, x1, x6)

inst_718:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x34d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x34d and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b4d; op2val:0x7b4d;
   valaddr_reg:x7; val_offset:1388*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1388*FLEN/8, x11, x1, x6)

inst_719:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x34d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x34d and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b4d; op2val:0x7b4d;
   valaddr_reg:x7; val_offset:1390*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1390*FLEN/8, x11, x1, x6)

inst_720:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3c1 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bc1; op2val:0x7bc1;
   valaddr_reg:x7; val_offset:1392*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1392*FLEN/8, x11, x1, x6)

inst_721:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3c1 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bc1; op2val:0x7bc1;
   valaddr_reg:x7; val_offset:1394*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1394*FLEN/8, x11, x1, x6)

inst_722:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3c1 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bc1; op2val:0x7bc1;
   valaddr_reg:x7; val_offset:1396*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1396*FLEN/8, x11, x1, x6)

inst_723:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3c1 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bc1; op2val:0x7bc1;
   valaddr_reg:x7; val_offset:1398*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1398*FLEN/8, x11, x1, x6)

inst_724:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3c1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3c1 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bc1; op2val:0x7bc1;
   valaddr_reg:x7; val_offset:1400*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1400*FLEN/8, x11, x1, x6)

inst_725:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2e2 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2e2 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72e2; op2val:0x72e2;
   valaddr_reg:x7; val_offset:1402*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1402*FLEN/8, x11, x1, x6)

inst_726:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2e2 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2e2 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72e2; op2val:0x72e2;
   valaddr_reg:x7; val_offset:1404*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1404*FLEN/8, x11, x1, x6)

inst_727:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2e2 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2e2 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72e2; op2val:0x72e2;
   valaddr_reg:x7; val_offset:1406*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1406*FLEN/8, x11, x1, x6)

inst_728:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2e2 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2e2 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72e2; op2val:0x72e2;
   valaddr_reg:x7; val_offset:1408*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1408*FLEN/8, x11, x1, x6)

inst_729:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2e2 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2e2 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72e2; op2val:0x72e2;
   valaddr_reg:x7; val_offset:1410*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1410*FLEN/8, x11, x1, x6)

inst_730:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3d5 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bd5; op2val:0x7bd5;
   valaddr_reg:x7; val_offset:1412*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1412*FLEN/8, x11, x1, x6)

inst_731:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3d5 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bd5; op2val:0x7bd5;
   valaddr_reg:x7; val_offset:1414*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1414*FLEN/8, x11, x1, x6)

inst_732:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3d5 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bd5; op2val:0x7bd5;
   valaddr_reg:x7; val_offset:1416*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1416*FLEN/8, x11, x1, x6)

inst_733:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3d5 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bd5; op2val:0x7bd5;
   valaddr_reg:x7; val_offset:1418*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1418*FLEN/8, x11, x1, x6)

inst_734:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3d5 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bd5; op2val:0x7bd5;
   valaddr_reg:x7; val_offset:1420*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1420*FLEN/8, x11, x1, x6)

inst_735:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x180 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x180 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7980; op2val:0x7980;
   valaddr_reg:x7; val_offset:1422*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1422*FLEN/8, x11, x1, x6)

inst_736:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x180 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x180 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7980; op2val:0x7980;
   valaddr_reg:x7; val_offset:1424*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1424*FLEN/8, x11, x1, x6)

inst_737:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x180 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x180 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7980; op2val:0x7980;
   valaddr_reg:x7; val_offset:1426*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1426*FLEN/8, x11, x1, x6)

inst_738:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x180 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x180 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7980; op2val:0x7980;
   valaddr_reg:x7; val_offset:1428*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1428*FLEN/8, x11, x1, x6)

inst_739:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x180 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x180 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7980; op2val:0x7980;
   valaddr_reg:x7; val_offset:1430*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1430*FLEN/8, x11, x1, x6)

inst_740:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x024 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x024 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7424; op2val:0x7424;
   valaddr_reg:x7; val_offset:1432*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1432*FLEN/8, x11, x1, x6)

inst_741:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x024 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x024 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7424; op2val:0x7424;
   valaddr_reg:x7; val_offset:1434*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1434*FLEN/8, x11, x1, x6)

inst_742:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x024 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x024 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7424; op2val:0x7424;
   valaddr_reg:x7; val_offset:1436*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1436*FLEN/8, x11, x1, x6)

inst_743:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x024 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x024 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7424; op2val:0x7424;
   valaddr_reg:x7; val_offset:1438*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1438*FLEN/8, x11, x1, x6)

inst_744:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x024 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x024 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7424; op2val:0x7424;
   valaddr_reg:x7; val_offset:1440*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1440*FLEN/8, x11, x1, x6)

inst_745:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ea and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0ea and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74ea; op2val:0x74ea;
   valaddr_reg:x7; val_offset:1442*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1442*FLEN/8, x11, x1, x6)

inst_746:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ea and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0ea and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74ea; op2val:0x74ea;
   valaddr_reg:x7; val_offset:1444*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1444*FLEN/8, x11, x1, x6)

inst_747:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ea and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0ea and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74ea; op2val:0x74ea;
   valaddr_reg:x7; val_offset:1446*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1446*FLEN/8, x11, x1, x6)

inst_748:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ea and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0ea and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74ea; op2val:0x74ea;
   valaddr_reg:x7; val_offset:1448*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1448*FLEN/8, x11, x1, x6)

inst_749:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ea and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0ea and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74ea; op2val:0x74ea;
   valaddr_reg:x7; val_offset:1450*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1450*FLEN/8, x11, x1, x6)

inst_750:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x134 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x134 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d34; op2val:0x6d34;
   valaddr_reg:x7; val_offset:1452*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1452*FLEN/8, x11, x1, x6)

inst_751:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x134 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x134 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d34; op2val:0x6d34;
   valaddr_reg:x7; val_offset:1454*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1454*FLEN/8, x11, x1, x6)

inst_752:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x134 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x134 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d34; op2val:0x6d34;
   valaddr_reg:x7; val_offset:1456*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1456*FLEN/8, x11, x1, x6)

inst_753:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x134 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x134 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d34; op2val:0x6d34;
   valaddr_reg:x7; val_offset:1458*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1458*FLEN/8, x11, x1, x6)

inst_754:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x134 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x134 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6d34; op2val:0x6d34;
   valaddr_reg:x7; val_offset:1460*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1460*FLEN/8, x11, x1, x6)

inst_755:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x136 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x136 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7936; op2val:0x7936;
   valaddr_reg:x7; val_offset:1462*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1462*FLEN/8, x11, x1, x6)

inst_756:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x136 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x136 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7936; op2val:0x7936;
   valaddr_reg:x7; val_offset:1464*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1464*FLEN/8, x11, x1, x6)

inst_757:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x136 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x136 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7936; op2val:0x7936;
   valaddr_reg:x7; val_offset:1466*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1466*FLEN/8, x11, x1, x6)

inst_758:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x136 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x136 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7936; op2val:0x7936;
   valaddr_reg:x7; val_offset:1468*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1468*FLEN/8, x11, x1, x6)

inst_759:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x136 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x136 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7936; op2val:0x7936;
   valaddr_reg:x7; val_offset:1470*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1470*FLEN/8, x11, x1, x6)

inst_760:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x385 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x385 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b85; op2val:0x7b85;
   valaddr_reg:x7; val_offset:1472*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1472*FLEN/8, x11, x1, x6)

inst_761:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x385 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x385 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b85; op2val:0x7b85;
   valaddr_reg:x7; val_offset:1474*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1474*FLEN/8, x11, x1, x6)

inst_762:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x385 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x385 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b85; op2val:0x7b85;
   valaddr_reg:x7; val_offset:1476*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1476*FLEN/8, x11, x1, x6)

inst_763:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x385 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x385 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b85; op2val:0x7b85;
   valaddr_reg:x7; val_offset:1478*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1478*FLEN/8, x11, x1, x6)

inst_764:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x385 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x385 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b85; op2val:0x7b85;
   valaddr_reg:x7; val_offset:1480*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1480*FLEN/8, x11, x1, x6)

inst_765:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0e8 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0e8 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74e8; op2val:0x74e8;
   valaddr_reg:x7; val_offset:1482*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1482*FLEN/8, x11, x1, x6)

inst_766:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0e8 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0e8 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74e8; op2val:0x74e8;
   valaddr_reg:x7; val_offset:1484*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1484*FLEN/8, x11, x1, x6)

inst_767:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0e8 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0e8 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74e8; op2val:0x74e8;
   valaddr_reg:x7; val_offset:1486*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1486*FLEN/8, x11, x1, x6)

inst_768:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0e8 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0e8 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74e8; op2val:0x74e8;
   valaddr_reg:x7; val_offset:1488*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1488*FLEN/8, x11, x1, x6)

inst_769:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0e8 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0e8 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74e8; op2val:0x74e8;
   valaddr_reg:x7; val_offset:1490*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1490*FLEN/8, x11, x1, x6)

inst_770:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x110 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x110 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7510; op2val:0x7510;
   valaddr_reg:x7; val_offset:1492*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1492*FLEN/8, x11, x1, x6)

inst_771:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x110 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x110 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7510; op2val:0x7510;
   valaddr_reg:x7; val_offset:1494*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1494*FLEN/8, x11, x1, x6)

inst_772:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x110 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x110 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7510; op2val:0x7510;
   valaddr_reg:x7; val_offset:1496*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1496*FLEN/8, x11, x1, x6)

inst_773:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x110 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x110 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7510; op2val:0x7510;
   valaddr_reg:x7; val_offset:1498*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1498*FLEN/8, x11, x1, x6)

inst_774:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x110 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x110 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7510; op2val:0x7510;
   valaddr_reg:x7; val_offset:1500*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1500*FLEN/8, x11, x1, x6)

inst_775:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x324 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x324 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b24; op2val:0x7b24;
   valaddr_reg:x7; val_offset:1502*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1502*FLEN/8, x11, x1, x6)

inst_776:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x324 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x324 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b24; op2val:0x7b24;
   valaddr_reg:x7; val_offset:1504*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1504*FLEN/8, x11, x1, x6)

inst_777:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x324 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x324 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b24; op2val:0x7b24;
   valaddr_reg:x7; val_offset:1506*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1506*FLEN/8, x11, x1, x6)

inst_778:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x324 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x324 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b24; op2val:0x7b24;
   valaddr_reg:x7; val_offset:1508*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1508*FLEN/8, x11, x1, x6)

inst_779:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x324 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x324 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b24; op2val:0x7b24;
   valaddr_reg:x7; val_offset:1510*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1510*FLEN/8, x11, x1, x6)

inst_780:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x158 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x158 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7558; op2val:0x7558;
   valaddr_reg:x7; val_offset:1512*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1512*FLEN/8, x11, x1, x6)

inst_781:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x158 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x158 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7558; op2val:0x7558;
   valaddr_reg:x7; val_offset:1514*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1514*FLEN/8, x11, x1, x6)

inst_782:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x158 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x158 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7558; op2val:0x7558;
   valaddr_reg:x7; val_offset:1516*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1516*FLEN/8, x11, x1, x6)

inst_783:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x158 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x158 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7558; op2val:0x7558;
   valaddr_reg:x7; val_offset:1518*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1518*FLEN/8, x11, x1, x6)

inst_784:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x158 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x158 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7558; op2val:0x7558;
   valaddr_reg:x7; val_offset:1520*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1520*FLEN/8, x11, x1, x6)

inst_785:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0a1 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x78a1; op2val:0x78a1;
   valaddr_reg:x7; val_offset:1522*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1522*FLEN/8, x11, x1, x6)

inst_786:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0a1 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x78a1; op2val:0x78a1;
   valaddr_reg:x7; val_offset:1524*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1524*FLEN/8, x11, x1, x6)

inst_787:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0a1 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x78a1; op2val:0x78a1;
   valaddr_reg:x7; val_offset:1526*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1526*FLEN/8, x11, x1, x6)

inst_788:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0a1 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x78a1; op2val:0x78a1;
   valaddr_reg:x7; val_offset:1528*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1528*FLEN/8, x11, x1, x6)

inst_789:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x0a1 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x78a1; op2val:0x78a1;
   valaddr_reg:x7; val_offset:1530*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1530*FLEN/8, x11, x1, x6)

inst_790:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3d6 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x73d6; op2val:0x73d6;
   valaddr_reg:x7; val_offset:1532*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1532*FLEN/8, x11, x1, x6)

inst_791:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3d6 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x73d6; op2val:0x73d6;
   valaddr_reg:x7; val_offset:1534*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1534*FLEN/8, x11, x1, x6)

inst_792:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3d6 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x73d6; op2val:0x73d6;
   valaddr_reg:x7; val_offset:1536*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1536*FLEN/8, x11, x1, x6)

inst_793:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3d6 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x73d6; op2val:0x73d6;
   valaddr_reg:x7; val_offset:1538*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1538*FLEN/8, x11, x1, x6)
RVTEST_SIGBASE(x1,signature_x1_8)

inst_794:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3d6 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x73d6; op2val:0x73d6;
   valaddr_reg:x7; val_offset:1540*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1540*FLEN/8, x11, x1, x6)

inst_795:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3cb and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x73cb; op2val:0x73cb;
   valaddr_reg:x7; val_offset:1542*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1542*FLEN/8, x11, x1, x6)

inst_796:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3cb and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x73cb; op2val:0x73cb;
   valaddr_reg:x7; val_offset:1544*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1544*FLEN/8, x11, x1, x6)

inst_797:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3cb and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x73cb; op2val:0x73cb;
   valaddr_reg:x7; val_offset:1546*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1546*FLEN/8, x11, x1, x6)

inst_798:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3cb and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x73cb; op2val:0x73cb;
   valaddr_reg:x7; val_offset:1548*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1548*FLEN/8, x11, x1, x6)

inst_799:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3cb and fs2 == 0 and fe2 == 0x1c and fm2 == 0x3cb and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x73cb; op2val:0x73cb;
   valaddr_reg:x7; val_offset:1550*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1550*FLEN/8, x11, x1, x6)

inst_800:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x068 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x068 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7868; op2val:0x7868;
   valaddr_reg:x7; val_offset:1552*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1552*FLEN/8, x11, x1, x6)

inst_801:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x068 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x068 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7868; op2val:0x7868;
   valaddr_reg:x7; val_offset:1554*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1554*FLEN/8, x11, x1, x6)

inst_802:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x068 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x068 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7868; op2val:0x7868;
   valaddr_reg:x7; val_offset:1556*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1556*FLEN/8, x11, x1, x6)

inst_803:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x068 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x068 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7868; op2val:0x7868;
   valaddr_reg:x7; val_offset:1558*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1558*FLEN/8, x11, x1, x6)

inst_804:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x068 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x068 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7868; op2val:0x7868;
   valaddr_reg:x7; val_offset:1560*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1560*FLEN/8, x11, x1, x6)

inst_805:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0ce and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0ce and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6cce; op2val:0x6cce;
   valaddr_reg:x7; val_offset:1562*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1562*FLEN/8, x11, x1, x6)

inst_806:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0ce and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0ce and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6cce; op2val:0x6cce;
   valaddr_reg:x7; val_offset:1564*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1564*FLEN/8, x11, x1, x6)

inst_807:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0ce and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0ce and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6cce; op2val:0x6cce;
   valaddr_reg:x7; val_offset:1566*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1566*FLEN/8, x11, x1, x6)

inst_808:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0ce and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0ce and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6cce; op2val:0x6cce;
   valaddr_reg:x7; val_offset:1568*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1568*FLEN/8, x11, x1, x6)

inst_809:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x0ce and fs2 == 0 and fe2 == 0x1b and fm2 == 0x0ce and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6cce; op2val:0x6cce;
   valaddr_reg:x7; val_offset:1570*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1570*FLEN/8, x11, x1, x6)

inst_810:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a6 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0a6 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74a6; op2val:0x74a6;
   valaddr_reg:x7; val_offset:1572*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1572*FLEN/8, x11, x1, x6)

inst_811:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a6 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0a6 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74a6; op2val:0x74a6;
   valaddr_reg:x7; val_offset:1574*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1574*FLEN/8, x11, x1, x6)

inst_812:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a6 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0a6 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74a6; op2val:0x74a6;
   valaddr_reg:x7; val_offset:1576*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1576*FLEN/8, x11, x1, x6)

inst_813:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a6 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0a6 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74a6; op2val:0x74a6;
   valaddr_reg:x7; val_offset:1578*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1578*FLEN/8, x11, x1, x6)

inst_814:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a6 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x0a6 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x74a6; op2val:0x74a6;
   valaddr_reg:x7; val_offset:1580*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1580*FLEN/8, x11, x1, x6)

inst_815:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3e3 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3e3 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77e3; op2val:0x77e3;
   valaddr_reg:x7; val_offset:1582*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1582*FLEN/8, x11, x1, x6)

inst_816:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3e3 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3e3 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77e3; op2val:0x77e3;
   valaddr_reg:x7; val_offset:1584*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1584*FLEN/8, x11, x1, x6)

inst_817:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3e3 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3e3 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77e3; op2val:0x77e3;
   valaddr_reg:x7; val_offset:1586*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1586*FLEN/8, x11, x1, x6)

inst_818:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3e3 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3e3 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77e3; op2val:0x77e3;
   valaddr_reg:x7; val_offset:1588*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1588*FLEN/8, x11, x1, x6)

inst_819:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3e3 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3e3 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77e3; op2val:0x77e3;
   valaddr_reg:x7; val_offset:1590*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1590*FLEN/8, x11, x1, x6)

inst_820:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ee and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0ee and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x70ee; op2val:0x70ee;
   valaddr_reg:x7; val_offset:1592*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1592*FLEN/8, x11, x1, x6)

inst_821:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ee and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0ee and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x70ee; op2val:0x70ee;
   valaddr_reg:x7; val_offset:1594*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1594*FLEN/8, x11, x1, x6)

inst_822:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ee and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0ee and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x70ee; op2val:0x70ee;
   valaddr_reg:x7; val_offset:1596*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1596*FLEN/8, x11, x1, x6)

inst_823:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ee and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0ee and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x70ee; op2val:0x70ee;
   valaddr_reg:x7; val_offset:1598*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1598*FLEN/8, x11, x1, x6)

inst_824:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ee and fs2 == 0 and fe2 == 0x1c and fm2 == 0x0ee and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x70ee; op2val:0x70ee;
   valaddr_reg:x7; val_offset:1600*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1600*FLEN/8, x11, x1, x6)

inst_825:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x25b and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a5b; op2val:0x7a5b;
   valaddr_reg:x7; val_offset:1602*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1602*FLEN/8, x11, x1, x6)

inst_826:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x25b and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a5b; op2val:0x7a5b;
   valaddr_reg:x7; val_offset:1604*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1604*FLEN/8, x11, x1, x6)

inst_827:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x25b and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a5b; op2val:0x7a5b;
   valaddr_reg:x7; val_offset:1606*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1606*FLEN/8, x11, x1, x6)

inst_828:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x25b and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a5b; op2val:0x7a5b;
   valaddr_reg:x7; val_offset:1608*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1608*FLEN/8, x11, x1, x6)

inst_829:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x25b and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a5b; op2val:0x7a5b;
   valaddr_reg:x7; val_offset:1610*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1610*FLEN/8, x11, x1, x6)

inst_830:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x395 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0x7b95;
   valaddr_reg:x7; val_offset:1612*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1612*FLEN/8, x11, x1, x6)

inst_831:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x395 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0x7b95;
   valaddr_reg:x7; val_offset:1614*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1614*FLEN/8, x11, x1, x6)

inst_832:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x395 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0x7b95;
   valaddr_reg:x7; val_offset:1616*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1616*FLEN/8, x11, x1, x6)

inst_833:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x395 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0x7b95;
   valaddr_reg:x7; val_offset:1618*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1618*FLEN/8, x11, x1, x6)

inst_834:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x395 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b97; op2val:0x7b95;
   valaddr_reg:x7; val_offset:1620*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1620*FLEN/8, x11, x1, x6)

inst_835:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x234 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x232 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a34; op2val:0x7a32;
   valaddr_reg:x7; val_offset:1622*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1622*FLEN/8, x11, x1, x6)

inst_836:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x234 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x232 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a34; op2val:0x7a32;
   valaddr_reg:x7; val_offset:1624*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1624*FLEN/8, x11, x1, x6)

inst_837:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x234 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x232 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a34; op2val:0x7a32;
   valaddr_reg:x7; val_offset:1626*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1626*FLEN/8, x11, x1, x6)

inst_838:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x234 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x232 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a34; op2val:0x7a32;
   valaddr_reg:x7; val_offset:1628*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1628*FLEN/8, x11, x1, x6)

inst_839:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x234 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x232 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a34; op2val:0x7a32;
   valaddr_reg:x7; val_offset:1630*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1630*FLEN/8, x11, x1, x6)

inst_840:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x291 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x28f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a91; op2val:0x7a8f;
   valaddr_reg:x7; val_offset:1632*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1632*FLEN/8, x11, x1, x6)

inst_841:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x291 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x28f and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a91; op2val:0x7a8f;
   valaddr_reg:x7; val_offset:1634*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1634*FLEN/8, x11, x1, x6)

inst_842:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x291 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x28f and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a91; op2val:0x7a8f;
   valaddr_reg:x7; val_offset:1636*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1636*FLEN/8, x11, x1, x6)

inst_843:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x291 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x28f and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a91; op2val:0x7a8f;
   valaddr_reg:x7; val_offset:1638*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1638*FLEN/8, x11, x1, x6)

inst_844:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x291 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x28f and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a91; op2val:0x7a8f;
   valaddr_reg:x7; val_offset:1640*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1640*FLEN/8, x11, x1, x6)

inst_845:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2d6 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2c6 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ed6; op2val:0x6ec6;
   valaddr_reg:x7; val_offset:1642*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1642*FLEN/8, x11, x1, x6)

inst_846:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2d6 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2c6 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ed6; op2val:0x6ec6;
   valaddr_reg:x7; val_offset:1644*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1644*FLEN/8, x11, x1, x6)

inst_847:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2d6 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2c6 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ed6; op2val:0x6ec6;
   valaddr_reg:x7; val_offset:1646*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1646*FLEN/8, x11, x1, x6)

inst_848:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2d6 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2c6 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ed6; op2val:0x6ec6;
   valaddr_reg:x7; val_offset:1648*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1648*FLEN/8, x11, x1, x6)

inst_849:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2d6 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x2c6 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6ed6; op2val:0x6ec6;
   valaddr_reg:x7; val_offset:1650*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1650*FLEN/8, x11, x1, x6)

inst_850:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x359 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x357 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b59; op2val:0x7b57;
   valaddr_reg:x7; val_offset:1652*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1652*FLEN/8, x11, x1, x6)

inst_851:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x359 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x357 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b59; op2val:0x7b57;
   valaddr_reg:x7; val_offset:1654*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1654*FLEN/8, x11, x1, x6)

inst_852:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x359 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x357 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b59; op2val:0x7b57;
   valaddr_reg:x7; val_offset:1656*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1656*FLEN/8, x11, x1, x6)

inst_853:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x359 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x357 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b59; op2val:0x7b57;
   valaddr_reg:x7; val_offset:1658*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1658*FLEN/8, x11, x1, x6)

inst_854:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x359 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x357 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b59; op2val:0x7b57;
   valaddr_reg:x7; val_offset:1660*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1660*FLEN/8, x11, x1, x6)

inst_855:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x323 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b25; op2val:0x7b23;
   valaddr_reg:x7; val_offset:1662*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1662*FLEN/8, x11, x1, x6)

inst_856:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x323 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b25; op2val:0x7b23;
   valaddr_reg:x7; val_offset:1664*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1664*FLEN/8, x11, x1, x6)

inst_857:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x323 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b25; op2val:0x7b23;
   valaddr_reg:x7; val_offset:1666*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1666*FLEN/8, x11, x1, x6)

inst_858:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x323 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b25; op2val:0x7b23;
   valaddr_reg:x7; val_offset:1668*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1668*FLEN/8, x11, x1, x6)

inst_859:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x323 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b25; op2val:0x7b23;
   valaddr_reg:x7; val_offset:1670*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1670*FLEN/8, x11, x1, x6)

inst_860:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x347 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x345 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b47; op2val:0x7b45;
   valaddr_reg:x7; val_offset:1672*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1672*FLEN/8, x11, x1, x6)

inst_861:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x347 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x345 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b47; op2val:0x7b45;
   valaddr_reg:x7; val_offset:1674*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1674*FLEN/8, x11, x1, x6)

inst_862:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x347 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x345 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b47; op2val:0x7b45;
   valaddr_reg:x7; val_offset:1676*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1676*FLEN/8, x11, x1, x6)

inst_863:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x347 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x345 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b47; op2val:0x7b45;
   valaddr_reg:x7; val_offset:1678*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1678*FLEN/8, x11, x1, x6)

inst_864:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x347 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x345 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b47; op2val:0x7b45;
   valaddr_reg:x7; val_offset:1680*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1680*FLEN/8, x11, x1, x6)

inst_865:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x112 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x750e; op2val:0x7512;
   valaddr_reg:x7; val_offset:1682*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1682*FLEN/8, x11, x1, x6)

inst_866:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x112 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x750e; op2val:0x7512;
   valaddr_reg:x7; val_offset:1684*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1684*FLEN/8, x11, x1, x6)

inst_867:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x112 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x750e; op2val:0x7512;
   valaddr_reg:x7; val_offset:1686*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1686*FLEN/8, x11, x1, x6)

inst_868:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x112 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x750e; op2val:0x7512;
   valaddr_reg:x7; val_offset:1688*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1688*FLEN/8, x11, x1, x6)

inst_869:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x10e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x112 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x750e; op2val:0x7512;
   valaddr_reg:x7; val_offset:1690*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1690*FLEN/8, x11, x1, x6)

inst_870:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x26f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a6d; op2val:0x7a6f;
   valaddr_reg:x7; val_offset:1692*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1692*FLEN/8, x11, x1, x6)

inst_871:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x26f and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a6d; op2val:0x7a6f;
   valaddr_reg:x7; val_offset:1694*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1694*FLEN/8, x11, x1, x6)

inst_872:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x26f and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a6d; op2val:0x7a6f;
   valaddr_reg:x7; val_offset:1696*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1696*FLEN/8, x11, x1, x6)

inst_873:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x26f and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a6d; op2val:0x7a6f;
   valaddr_reg:x7; val_offset:1698*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1698*FLEN/8, x11, x1, x6)

inst_874:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x26d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x26f and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a6d; op2val:0x7a6f;
   valaddr_reg:x7; val_offset:1700*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1700*FLEN/8, x11, x1, x6)

inst_875:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ba and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab8; op2val:0x7aba;
   valaddr_reg:x7; val_offset:1702*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1702*FLEN/8, x11, x1, x6)

inst_876:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ba and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab8; op2val:0x7aba;
   valaddr_reg:x7; val_offset:1704*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1704*FLEN/8, x11, x1, x6)

inst_877:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ba and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab8; op2val:0x7aba;
   valaddr_reg:x7; val_offset:1706*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1706*FLEN/8, x11, x1, x6)

inst_878:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ba and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab8; op2val:0x7aba;
   valaddr_reg:x7; val_offset:1708*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1708*FLEN/8, x11, x1, x6)

inst_879:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ba and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ab8; op2val:0x7aba;
   valaddr_reg:x7; val_offset:1710*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1710*FLEN/8, x11, x1, x6)

inst_880:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x183 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x185 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7983; op2val:0x7985;
   valaddr_reg:x7; val_offset:1712*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1712*FLEN/8, x11, x1, x6)

inst_881:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x183 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x185 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7983; op2val:0x7985;
   valaddr_reg:x7; val_offset:1714*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1714*FLEN/8, x11, x1, x6)

inst_882:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x183 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x185 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7983; op2val:0x7985;
   valaddr_reg:x7; val_offset:1716*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1716*FLEN/8, x11, x1, x6)

inst_883:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x183 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x185 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7983; op2val:0x7985;
   valaddr_reg:x7; val_offset:1718*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1718*FLEN/8, x11, x1, x6)

inst_884:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x183 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x185 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7983; op2val:0x7985;
   valaddr_reg:x7; val_offset:1720*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1720*FLEN/8, x11, x1, x6)

inst_885:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2eb and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2ef and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x76eb; op2val:0x76ef;
   valaddr_reg:x7; val_offset:1722*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1722*FLEN/8, x11, x1, x6)

inst_886:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2eb and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2ef and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x76eb; op2val:0x76ef;
   valaddr_reg:x7; val_offset:1724*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1724*FLEN/8, x11, x1, x6)

inst_887:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2eb and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2ef and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x76eb; op2val:0x76ef;
   valaddr_reg:x7; val_offset:1726*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1726*FLEN/8, x11, x1, x6)

inst_888:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2eb and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2ef and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x76eb; op2val:0x76ef;
   valaddr_reg:x7; val_offset:1728*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1728*FLEN/8, x11, x1, x6)

inst_889:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2eb and fs2 == 0 and fe2 == 0x1d and fm2 == 0x2ef and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x76eb; op2val:0x76ef;
   valaddr_reg:x7; val_offset:1730*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1730*FLEN/8, x11, x1, x6)

inst_890:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1b9 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b7; op2val:0x79b9;
   valaddr_reg:x7; val_offset:1732*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1732*FLEN/8, x11, x1, x6)

inst_891:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1b9 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b7; op2val:0x79b9;
   valaddr_reg:x7; val_offset:1734*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1734*FLEN/8, x11, x1, x6)

inst_892:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1b9 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b7; op2val:0x79b9;
   valaddr_reg:x7; val_offset:1736*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1736*FLEN/8, x11, x1, x6)

inst_893:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1b9 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b7; op2val:0x79b9;
   valaddr_reg:x7; val_offset:1738*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1738*FLEN/8, x11, x1, x6)

inst_894:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1b9 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79b7; op2val:0x79b9;
   valaddr_reg:x7; val_offset:1740*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1740*FLEN/8, x11, x1, x6)

inst_895:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x00e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x740a; op2val:0x740e;
   valaddr_reg:x7; val_offset:1742*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1742*FLEN/8, x11, x1, x6)

inst_896:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x00e and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x740a; op2val:0x740e;
   valaddr_reg:x7; val_offset:1744*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1744*FLEN/8, x11, x1, x6)

inst_897:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x00e and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x740a; op2val:0x740e;
   valaddr_reg:x7; val_offset:1746*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1746*FLEN/8, x11, x1, x6)

inst_898:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x00e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x740a; op2val:0x740e;
   valaddr_reg:x7; val_offset:1748*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1748*FLEN/8, x11, x1, x6)

inst_899:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x00e and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x740a; op2val:0x740e;
   valaddr_reg:x7; val_offset:1750*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1750*FLEN/8, x11, x1, x6)

inst_900:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3b6 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb4; op2val:0x7bb6;
   valaddr_reg:x7; val_offset:1752*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1752*FLEN/8, x11, x1, x6)

inst_901:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3b6 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb4; op2val:0x7bb6;
   valaddr_reg:x7; val_offset:1754*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1754*FLEN/8, x11, x1, x6)

inst_902:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3b6 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb4; op2val:0x7bb6;
   valaddr_reg:x7; val_offset:1756*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1756*FLEN/8, x11, x1, x6)

inst_903:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3b6 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb4; op2val:0x7bb6;
   valaddr_reg:x7; val_offset:1758*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1758*FLEN/8, x11, x1, x6)

inst_904:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3b6 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bb4; op2val:0x7bb6;
   valaddr_reg:x7; val_offset:1760*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1760*FLEN/8, x11, x1, x6)

inst_905:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x064 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x066 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7864; op2val:0x7866;
   valaddr_reg:x7; val_offset:1762*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1762*FLEN/8, x11, x1, x6)

inst_906:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x064 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x066 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7864; op2val:0x7866;
   valaddr_reg:x7; val_offset:1764*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1764*FLEN/8, x11, x1, x6)

inst_907:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x064 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x066 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7864; op2val:0x7866;
   valaddr_reg:x7; val_offset:1766*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1766*FLEN/8, x11, x1, x6)

inst_908:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x064 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x066 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7864; op2val:0x7866;
   valaddr_reg:x7; val_offset:1768*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1768*FLEN/8, x11, x1, x6)

inst_909:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x064 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x066 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7864; op2val:0x7866;
   valaddr_reg:x7; val_offset:1770*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1770*FLEN/8, x11, x1, x6)

inst_910:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ce and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2d0 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ace; op2val:0x7ad0;
   valaddr_reg:x7; val_offset:1772*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1772*FLEN/8, x11, x1, x6)

inst_911:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ce and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2d0 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ace; op2val:0x7ad0;
   valaddr_reg:x7; val_offset:1774*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1774*FLEN/8, x11, x1, x6)

inst_912:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ce and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2d0 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ace; op2val:0x7ad0;
   valaddr_reg:x7; val_offset:1776*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1776*FLEN/8, x11, x1, x6)

inst_913:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ce and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2d0 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ace; op2val:0x7ad0;
   valaddr_reg:x7; val_offset:1778*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1778*FLEN/8, x11, x1, x6)

inst_914:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ce and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2d0 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ace; op2val:0x7ad0;
   valaddr_reg:x7; val_offset:1780*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1780*FLEN/8, x11, x1, x6)

inst_915:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x254 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x258 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7654; op2val:0x7658;
   valaddr_reg:x7; val_offset:1782*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1782*FLEN/8, x11, x1, x6)

inst_916:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x254 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x258 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7654; op2val:0x7658;
   valaddr_reg:x7; val_offset:1784*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1784*FLEN/8, x11, x1, x6)

inst_917:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x254 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x258 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7654; op2val:0x7658;
   valaddr_reg:x7; val_offset:1786*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1786*FLEN/8, x11, x1, x6)

inst_918:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x254 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x258 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7654; op2val:0x7658;
   valaddr_reg:x7; val_offset:1788*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1788*FLEN/8, x11, x1, x6)

inst_919:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x254 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x258 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7654; op2val:0x7658;
   valaddr_reg:x7; val_offset:1790*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1790*FLEN/8, x11, x1, x6)

inst_920:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x020 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x024 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7420; op2val:0x7424;
   valaddr_reg:x7; val_offset:1792*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1792*FLEN/8, x11, x1, x6)

inst_921:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x020 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x024 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7420; op2val:0x7424;
   valaddr_reg:x7; val_offset:1794*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1794*FLEN/8, x11, x1, x6)
RVTEST_SIGBASE(x1,signature_x1_9)

inst_922:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x020 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x024 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7420; op2val:0x7424;
   valaddr_reg:x7; val_offset:1796*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1796*FLEN/8, x11, x1, x6)

inst_923:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x020 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x024 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7420; op2val:0x7424;
   valaddr_reg:x7; val_offset:1798*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1798*FLEN/8, x11, x1, x6)

inst_924:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x020 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x024 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7420; op2val:0x7424;
   valaddr_reg:x7; val_offset:1800*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1800*FLEN/8, x11, x1, x6)

inst_925:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x12d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x792b; op2val:0x792d;
   valaddr_reg:x7; val_offset:1802*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1802*FLEN/8, x11, x1, x6)

inst_926:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x12d and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x792b; op2val:0x792d;
   valaddr_reg:x7; val_offset:1804*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1804*FLEN/8, x11, x1, x6)

inst_927:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x12d and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x792b; op2val:0x792d;
   valaddr_reg:x7; val_offset:1806*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1806*FLEN/8, x11, x1, x6)

inst_928:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x12d and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x792b; op2val:0x792d;
   valaddr_reg:x7; val_offset:1808*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1808*FLEN/8, x11, x1, x6)

inst_929:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x12d and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x792b; op2val:0x792d;
   valaddr_reg:x7; val_offset:1810*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1810*FLEN/8, x11, x1, x6)

inst_930:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x090 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x092 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7890; op2val:0x7892;
   valaddr_reg:x7; val_offset:1812*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1812*FLEN/8, x11, x1, x6)

inst_931:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x090 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x092 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7890; op2val:0x7892;
   valaddr_reg:x7; val_offset:1814*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1814*FLEN/8, x11, x1, x6)

inst_932:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x090 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x092 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7890; op2val:0x7892;
   valaddr_reg:x7; val_offset:1816*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1816*FLEN/8, x11, x1, x6)

inst_933:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x090 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x092 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7890; op2val:0x7892;
   valaddr_reg:x7; val_offset:1818*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1818*FLEN/8, x11, x1, x6)

inst_934:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x090 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x092 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7890; op2val:0x7892;
   valaddr_reg:x7; val_offset:1820*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1820*FLEN/8, x11, x1, x6)

inst_935:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ad and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1a9 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75ad; op2val:0x75a9;
   valaddr_reg:x7; val_offset:1822*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1822*FLEN/8, x11, x1, x6)

inst_936:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ad and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1a9 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75ad; op2val:0x75a9;
   valaddr_reg:x7; val_offset:1824*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1824*FLEN/8, x11, x1, x6)

inst_937:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ad and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1a9 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75ad; op2val:0x75a9;
   valaddr_reg:x7; val_offset:1826*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1826*FLEN/8, x11, x1, x6)

inst_938:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ad and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1a9 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75ad; op2val:0x75a9;
   valaddr_reg:x7; val_offset:1828*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1828*FLEN/8, x11, x1, x6)

inst_939:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ad and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1a9 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75ad; op2val:0x75a9;
   valaddr_reg:x7; val_offset:1830*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1830*FLEN/8, x11, x1, x6)

inst_940:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3f1 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7000; op2val:0x6ff1;
   valaddr_reg:x7; val_offset:1832*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1832*FLEN/8, x11, x1, x6)

inst_941:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3f1 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7000; op2val:0x6ff1;
   valaddr_reg:x7; val_offset:1834*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1834*FLEN/8, x11, x1, x6)

inst_942:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3f1 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7000; op2val:0x6ff1;
   valaddr_reg:x7; val_offset:1836*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1836*FLEN/8, x11, x1, x6)

inst_943:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3f1 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7000; op2val:0x6ff1;
   valaddr_reg:x7; val_offset:1838*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1838*FLEN/8, x11, x1, x6)

inst_944:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1b and fm2 == 0x3f1 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7000; op2val:0x6ff1;
   valaddr_reg:x7; val_offset:1840*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1840*FLEN/8, x11, x1, x6)

inst_945:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x29e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aa0; op2val:0x7a9e;
   valaddr_reg:x7; val_offset:1842*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1842*FLEN/8, x11, x1, x6)

inst_946:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x29e and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aa0; op2val:0x7a9e;
   valaddr_reg:x7; val_offset:1844*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1844*FLEN/8, x11, x1, x6)

inst_947:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x29e and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aa0; op2val:0x7a9e;
   valaddr_reg:x7; val_offset:1846*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1846*FLEN/8, x11, x1, x6)

inst_948:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x29e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aa0; op2val:0x7a9e;
   valaddr_reg:x7; val_offset:1848*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1848*FLEN/8, x11, x1, x6)

inst_949:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x29e and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aa0; op2val:0x7a9e;
   valaddr_reg:x7; val_offset:1850*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1850*FLEN/8, x11, x1, x6)

inst_950:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x266 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x766a; op2val:0x7666;
   valaddr_reg:x7; val_offset:1852*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1852*FLEN/8, x11, x1, x6)

inst_951:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x266 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x766a; op2val:0x7666;
   valaddr_reg:x7; val_offset:1854*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1854*FLEN/8, x11, x1, x6)

inst_952:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x266 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x766a; op2val:0x7666;
   valaddr_reg:x7; val_offset:1856*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1856*FLEN/8, x11, x1, x6)

inst_953:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x266 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x766a; op2val:0x7666;
   valaddr_reg:x7; val_offset:1858*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1858*FLEN/8, x11, x1, x6)

inst_954:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x26a and fs2 == 0 and fe2 == 0x1d and fm2 == 0x266 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x766a; op2val:0x7666;
   valaddr_reg:x7; val_offset:1860*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1860*FLEN/8, x11, x1, x6)

inst_955:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x378 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x370 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7378; op2val:0x7370;
   valaddr_reg:x7; val_offset:1862*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1862*FLEN/8, x11, x1, x6)

inst_956:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x378 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x370 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7378; op2val:0x7370;
   valaddr_reg:x7; val_offset:1864*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1864*FLEN/8, x11, x1, x6)

inst_957:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x378 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x370 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7378; op2val:0x7370;
   valaddr_reg:x7; val_offset:1866*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1866*FLEN/8, x11, x1, x6)

inst_958:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x378 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x370 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7378; op2val:0x7370;
   valaddr_reg:x7; val_offset:1868*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1868*FLEN/8, x11, x1, x6)

inst_959:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x378 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x370 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7378; op2val:0x7370;
   valaddr_reg:x7; val_offset:1870*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1870*FLEN/8, x11, x1, x6)

inst_960:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x038 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x783a; op2val:0x7838;
   valaddr_reg:x7; val_offset:1872*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1872*FLEN/8, x11, x1, x6)

inst_961:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x038 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x783a; op2val:0x7838;
   valaddr_reg:x7; val_offset:1874*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1874*FLEN/8, x11, x1, x6)

inst_962:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x038 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x783a; op2val:0x7838;
   valaddr_reg:x7; val_offset:1876*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1876*FLEN/8, x11, x1, x6)

inst_963:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x038 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x783a; op2val:0x7838;
   valaddr_reg:x7; val_offset:1878*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1878*FLEN/8, x11, x1, x6)

inst_964:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x03a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x038 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x783a; op2val:0x7838;
   valaddr_reg:x7; val_offset:1880*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1880*FLEN/8, x11, x1, x6)

inst_965:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x130 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x12e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7930; op2val:0x792e;
   valaddr_reg:x7; val_offset:1882*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1882*FLEN/8, x11, x1, x6)

inst_966:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x130 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x12e and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7930; op2val:0x792e;
   valaddr_reg:x7; val_offset:1884*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1884*FLEN/8, x11, x1, x6)

inst_967:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x130 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x12e and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7930; op2val:0x792e;
   valaddr_reg:x7; val_offset:1886*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1886*FLEN/8, x11, x1, x6)

inst_968:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x130 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x12e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7930; op2val:0x792e;
   valaddr_reg:x7; val_offset:1888*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1888*FLEN/8, x11, x1, x6)

inst_969:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x130 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x12e and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7930; op2val:0x792e;
   valaddr_reg:x7; val_offset:1890*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1890*FLEN/8, x11, x1, x6)

inst_970:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x17d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x17d and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x797d; op2val:0x797d;
   valaddr_reg:x7; val_offset:1892*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1892*FLEN/8, x11, x1, x6)

inst_971:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x17d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x17d and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x797d; op2val:0x797d;
   valaddr_reg:x7; val_offset:1894*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1894*FLEN/8, x11, x1, x6)

inst_972:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x17d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x17d and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x797d; op2val:0x797d;
   valaddr_reg:x7; val_offset:1896*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1896*FLEN/8, x11, x1, x6)

inst_973:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x17d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x17d and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x797d; op2val:0x797d;
   valaddr_reg:x7; val_offset:1898*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1898*FLEN/8, x11, x1, x6)

inst_974:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x17d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x17d and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x797d; op2val:0x797d;
   valaddr_reg:x7; val_offset:1900*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1900*FLEN/8, x11, x1, x6)

inst_975:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39f and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x739f; op2val:0x739f;
   valaddr_reg:x7; val_offset:1902*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1902*FLEN/8, x11, x1, x6)

inst_976:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39f and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39f and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x739f; op2val:0x739f;
   valaddr_reg:x7; val_offset:1904*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1904*FLEN/8, x11, x1, x6)

inst_977:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39f and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39f and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x739f; op2val:0x739f;
   valaddr_reg:x7; val_offset:1906*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1906*FLEN/8, x11, x1, x6)

inst_978:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39f and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39f and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x739f; op2val:0x739f;
   valaddr_reg:x7; val_offset:1908*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1908*FLEN/8, x11, x1, x6)

inst_979:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x39f and fs2 == 0 and fe2 == 0x1c and fm2 == 0x39f and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x739f; op2val:0x739f;
   valaddr_reg:x7; val_offset:1910*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1910*FLEN/8, x11, x1, x6)

inst_980:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a8 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3a8 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77a8; op2val:0x77a8;
   valaddr_reg:x7; val_offset:1912*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1912*FLEN/8, x11, x1, x6)

inst_981:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a8 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3a8 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77a8; op2val:0x77a8;
   valaddr_reg:x7; val_offset:1914*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1914*FLEN/8, x11, x1, x6)

inst_982:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a8 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3a8 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77a8; op2val:0x77a8;
   valaddr_reg:x7; val_offset:1916*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1916*FLEN/8, x11, x1, x6)

inst_983:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a8 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3a8 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77a8; op2val:0x77a8;
   valaddr_reg:x7; val_offset:1918*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1918*FLEN/8, x11, x1, x6)

inst_984:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a8 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3a8 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x77a8; op2val:0x77a8;
   valaddr_reg:x7; val_offset:1920*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1920*FLEN/8, x11, x1, x6)

inst_985:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x297 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x297 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7697; op2val:0x7697;
   valaddr_reg:x7; val_offset:1922*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1922*FLEN/8, x11, x1, x6)

inst_986:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x297 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x297 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7697; op2val:0x7697;
   valaddr_reg:x7; val_offset:1924*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1924*FLEN/8, x11, x1, x6)

inst_987:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x297 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x297 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7697; op2val:0x7697;
   valaddr_reg:x7; val_offset:1926*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1926*FLEN/8, x11, x1, x6)

inst_988:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x297 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x297 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7697; op2val:0x7697;
   valaddr_reg:x7; val_offset:1928*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1928*FLEN/8, x11, x1, x6)

inst_989:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x297 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x297 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7697; op2val:0x7697;
   valaddr_reg:x7; val_offset:1930*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1930*FLEN/8, x11, x1, x6)

inst_990:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x340 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x340 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b40; op2val:0x7b40;
   valaddr_reg:x7; val_offset:1932*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1932*FLEN/8, x11, x1, x6)

inst_991:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x340 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x340 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b40; op2val:0x7b40;
   valaddr_reg:x7; val_offset:1934*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1934*FLEN/8, x11, x1, x6)

inst_992:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x340 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x340 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b40; op2val:0x7b40;
   valaddr_reg:x7; val_offset:1936*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1936*FLEN/8, x11, x1, x6)

inst_993:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x340 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x340 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b40; op2val:0x7b40;
   valaddr_reg:x7; val_offset:1938*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1938*FLEN/8, x11, x1, x6)

inst_994:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x340 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x340 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b40; op2val:0x7b40;
   valaddr_reg:x7; val_offset:1940*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1940*FLEN/8, x11, x1, x6)

inst_995:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x066 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x066 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7466; op2val:0x7466;
   valaddr_reg:x7; val_offset:1942*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1942*FLEN/8, x11, x1, x6)

inst_996:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x066 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x066 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7466; op2val:0x7466;
   valaddr_reg:x7; val_offset:1944*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1944*FLEN/8, x11, x1, x6)

inst_997:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x066 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x066 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7466; op2val:0x7466;
   valaddr_reg:x7; val_offset:1946*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1946*FLEN/8, x11, x1, x6)

inst_998:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x066 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x066 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7466; op2val:0x7466;
   valaddr_reg:x7; val_offset:1948*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1948*FLEN/8, x11, x1, x6)

inst_999:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x066 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x066 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7466; op2val:0x7466;
   valaddr_reg:x7; val_offset:1950*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1950*FLEN/8, x11, x1, x6)

inst_1000:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x22b and fs2 == 0 and fe2 == 0x1a and fm2 == 0x22b and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6a2b; op2val:0x6a2b;
   valaddr_reg:x7; val_offset:1952*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1952*FLEN/8, x11, x1, x6)

inst_1001:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x22b and fs2 == 0 and fe2 == 0x1a and fm2 == 0x22b and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6a2b; op2val:0x6a2b;
   valaddr_reg:x7; val_offset:1954*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1954*FLEN/8, x11, x1, x6)

inst_1002:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x22b and fs2 == 0 and fe2 == 0x1a and fm2 == 0x22b and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6a2b; op2val:0x6a2b;
   valaddr_reg:x7; val_offset:1956*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1956*FLEN/8, x11, x1, x6)

inst_1003:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x22b and fs2 == 0 and fe2 == 0x1a and fm2 == 0x22b and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6a2b; op2val:0x6a2b;
   valaddr_reg:x7; val_offset:1958*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1958*FLEN/8, x11, x1, x6)

inst_1004:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x22b and fs2 == 0 and fe2 == 0x1a and fm2 == 0x22b and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6a2b; op2val:0x6a2b;
   valaddr_reg:x7; val_offset:1960*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1960*FLEN/8, x11, x1, x6)

inst_1005:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x017 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x017 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7817; op2val:0x7817;
   valaddr_reg:x7; val_offset:1962*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1962*FLEN/8, x11, x1, x6)

inst_1006:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x017 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x017 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7817; op2val:0x7817;
   valaddr_reg:x7; val_offset:1964*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1964*FLEN/8, x11, x1, x6)

inst_1007:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x017 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x017 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7817; op2val:0x7817;
   valaddr_reg:x7; val_offset:1966*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1966*FLEN/8, x11, x1, x6)

inst_1008:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x017 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x017 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7817; op2val:0x7817;
   valaddr_reg:x7; val_offset:1968*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1968*FLEN/8, x11, x1, x6)

inst_1009:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x017 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x017 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7817; op2val:0x7817;
   valaddr_reg:x7; val_offset:1970*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1970*FLEN/8, x11, x1, x6)

inst_1010:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x119 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x119 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7119; op2val:0x7119;
   valaddr_reg:x7; val_offset:1972*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1972*FLEN/8, x11, x1, x6)

inst_1011:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x119 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x119 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7119; op2val:0x7119;
   valaddr_reg:x7; val_offset:1974*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1974*FLEN/8, x11, x1, x6)

inst_1012:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x119 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x119 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7119; op2val:0x7119;
   valaddr_reg:x7; val_offset:1976*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1976*FLEN/8, x11, x1, x6)

inst_1013:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x119 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x119 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7119; op2val:0x7119;
   valaddr_reg:x7; val_offset:1978*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1978*FLEN/8, x11, x1, x6)

inst_1014:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x119 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x119 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7119; op2val:0x7119;
   valaddr_reg:x7; val_offset:1980*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1980*FLEN/8, x11, x1, x6)

inst_1015:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x30f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b0f; op2val:0x7b0f;
   valaddr_reg:x7; val_offset:1982*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1982*FLEN/8, x11, x1, x6)

inst_1016:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x30f and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b0f; op2val:0x7b0f;
   valaddr_reg:x7; val_offset:1984*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1984*FLEN/8, x11, x1, x6)

inst_1017:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x30f and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b0f; op2val:0x7b0f;
   valaddr_reg:x7; val_offset:1986*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1986*FLEN/8, x11, x1, x6)

inst_1018:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x30f and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b0f; op2val:0x7b0f;
   valaddr_reg:x7; val_offset:1988*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1988*FLEN/8, x11, x1, x6)

inst_1019:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x30f and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7b0f; op2val:0x7b0f;
   valaddr_reg:x7; val_offset:1990*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 1990*FLEN/8, x11, x1, x6)

inst_1020:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x189 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x189 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7989; op2val:0x7989;
   valaddr_reg:x7; val_offset:1992*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 1992*FLEN/8, x11, x1, x6)

inst_1021:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x189 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x189 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7989; op2val:0x7989;
   valaddr_reg:x7; val_offset:1994*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 1994*FLEN/8, x11, x1, x6)

inst_1022:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x189 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x189 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7989; op2val:0x7989;
   valaddr_reg:x7; val_offset:1996*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 1996*FLEN/8, x11, x1, x6)

inst_1023:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x189 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x189 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7989; op2val:0x7989;
   valaddr_reg:x7; val_offset:1998*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 1998*FLEN/8, x11, x1, x6)

inst_1024:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x189 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x189 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7989; op2val:0x7989;
   valaddr_reg:x7; val_offset:2000*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 2000*FLEN/8, x11, x1, x6)

inst_1025:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f1 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1f1 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75f1; op2val:0x75f1;
   valaddr_reg:x7; val_offset:2002*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 2002*FLEN/8, x11, x1, x6)

inst_1026:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f1 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1f1 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75f1; op2val:0x75f1;
   valaddr_reg:x7; val_offset:2004*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 2004*FLEN/8, x11, x1, x6)

inst_1027:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f1 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1f1 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75f1; op2val:0x75f1;
   valaddr_reg:x7; val_offset:2006*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 2006*FLEN/8, x11, x1, x6)

inst_1028:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f1 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1f1 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75f1; op2val:0x75f1;
   valaddr_reg:x7; val_offset:2008*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 2008*FLEN/8, x11, x1, x6)

inst_1029:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1f1 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x1f1 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x75f1; op2val:0x75f1;
   valaddr_reg:x7; val_offset:2010*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 2010*FLEN/8, x11, x1, x6)

inst_1030:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1e3 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79e3; op2val:0x79e3;
   valaddr_reg:x7; val_offset:2012*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 2012*FLEN/8, x11, x1, x6)

inst_1031:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1e3 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79e3; op2val:0x79e3;
   valaddr_reg:x7; val_offset:2014*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 2014*FLEN/8, x11, x1, x6)

inst_1032:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1e3 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79e3; op2val:0x79e3;
   valaddr_reg:x7; val_offset:2016*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 2016*FLEN/8, x11, x1, x6)

inst_1033:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1e3 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79e3; op2val:0x79e3;
   valaddr_reg:x7; val_offset:2018*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 2018*FLEN/8, x11, x1, x6)

inst_1034:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x1e3 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x79e3; op2val:0x79e3;
   valaddr_reg:x7; val_offset:2020*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 2020*FLEN/8, x11, x1, x6)

inst_1035:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2d8 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad8; op2val:0x7ad8;
   valaddr_reg:x7; val_offset:2022*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 2022*FLEN/8, x11, x1, x6)

inst_1036:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2d8 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad8; op2val:0x7ad8;
   valaddr_reg:x7; val_offset:2024*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 2024*FLEN/8, x11, x1, x6)

inst_1037:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2d8 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad8; op2val:0x7ad8;
   valaddr_reg:x7; val_offset:2026*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 2026*FLEN/8, x11, x1, x6)

inst_1038:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2d8 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad8; op2val:0x7ad8;
   valaddr_reg:x7; val_offset:2028*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 2028*FLEN/8, x11, x1, x6)

inst_1039:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2d8 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7ad8; op2val:0x7ad8;
   valaddr_reg:x7; val_offset:2030*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 2030*FLEN/8, x11, x1, x6)

inst_1040:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ad and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ad and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bad; op2val:0x7bad;
   valaddr_reg:x7; val_offset:2032*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 2032*FLEN/8, x11, x1, x6)

inst_1041:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ad and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ad and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bad; op2val:0x7bad;
   valaddr_reg:x7; val_offset:2034*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 2034*FLEN/8, x11, x1, x6)

inst_1042:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ad and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ad and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bad; op2val:0x7bad;
   valaddr_reg:x7; val_offset:2036*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 2036*FLEN/8, x11, x1, x6)

inst_1043:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ad and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ad and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bad; op2val:0x7bad;
   valaddr_reg:x7; val_offset:2038*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 2038*FLEN/8, x11, x1, x6)

inst_1044:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ad and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ad and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bad; op2val:0x7bad;
   valaddr_reg:x7; val_offset:2040*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 2040*FLEN/8, x11, x1, x6)

inst_1045:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1a3 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1a3 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x71a3; op2val:0x71a3;
   valaddr_reg:x7; val_offset:2042*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 2042*FLEN/8, x11, x1, x6)

inst_1046:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1a3 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1a3 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x71a3; op2val:0x71a3;
   valaddr_reg:x7; val_offset:2044*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 2044*FLEN/8, x11, x1, x6)

inst_1047:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1a3 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1a3 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x71a3; op2val:0x71a3;
   valaddr_reg:x7; val_offset:2046*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 2046*FLEN/8, x11, x1, x6)

inst_1048:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1a3 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1a3 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x71a3; op2val:0x71a3;
   valaddr_reg:x7; val_offset:2048*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 2048*FLEN/8, x11, x1, x6)

inst_1049:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1a3 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x1a3 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x71a3; op2val:0x71a3;
   valaddr_reg:x7; val_offset:2050*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 2050*FLEN/8, x11, x1, x6)
RVTEST_SIGBASE(x1,signature_x1_10)

inst_1050:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2f5 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72f5; op2val:0x72f5;
   valaddr_reg:x7; val_offset:2052*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 2052*FLEN/8, x11, x1, x6)

inst_1051:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2f5 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72f5; op2val:0x72f5;
   valaddr_reg:x7; val_offset:2054*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 2054*FLEN/8, x11, x1, x6)

inst_1052:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2f5 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72f5; op2val:0x72f5;
   valaddr_reg:x7; val_offset:2056*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 2056*FLEN/8, x11, x1, x6)

inst_1053:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2f5 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72f5; op2val:0x72f5;
   valaddr_reg:x7; val_offset:2058*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 2058*FLEN/8, x11, x1, x6)

inst_1054:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2f5 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x2f5 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x72f5; op2val:0x72f5;
   valaddr_reg:x7; val_offset:2060*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 2060*FLEN/8, x11, x1, x6)

inst_1055:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a0f; op2val:0x7a0f;
   valaddr_reg:x7; val_offset:2062*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 2062*FLEN/8, x11, x1, x6)

inst_1056:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a0f; op2val:0x7a0f;
   valaddr_reg:x7; val_offset:2064*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 2064*FLEN/8, x11, x1, x6)

inst_1057:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a0f; op2val:0x7a0f;
   valaddr_reg:x7; val_offset:2066*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 2066*FLEN/8, x11, x1, x6)

inst_1058:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a0f; op2val:0x7a0f;
   valaddr_reg:x7; val_offset:2068*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 2068*FLEN/8, x11, x1, x6)

inst_1059:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a0f; op2val:0x7a0f;
   valaddr_reg:x7; val_offset:2070*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 2070*FLEN/8, x11, x1, x6)

inst_1060:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x173 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x173 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7973; op2val:0x7973;
   valaddr_reg:x7; val_offset:2072*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 2072*FLEN/8, x11, x1, x6)

inst_1061:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x173 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x173 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7973; op2val:0x7973;
   valaddr_reg:x7; val_offset:2074*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 2074*FLEN/8, x11, x1, x6)

inst_1062:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x173 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x173 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7973; op2val:0x7973;
   valaddr_reg:x7; val_offset:2076*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 2076*FLEN/8, x11, x1, x6)

inst_1063:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x173 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x173 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7973; op2val:0x7973;
   valaddr_reg:x7; val_offset:2078*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 2078*FLEN/8, x11, x1, x6)

inst_1064:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x173 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x173 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7973; op2val:0x7973;
   valaddr_reg:x7; val_offset:2080*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 2080*FLEN/8, x11, x1, x6)

inst_1065:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x190 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x190 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7590; op2val:0x7590;
   valaddr_reg:x7; val_offset:2082*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 2082*FLEN/8, x11, x1, x6)

inst_1066:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x190 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x190 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7590; op2val:0x7590;
   valaddr_reg:x7; val_offset:2084*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 2084*FLEN/8, x11, x1, x6)

inst_1067:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x190 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x190 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7590; op2val:0x7590;
   valaddr_reg:x7; val_offset:2086*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 2086*FLEN/8, x11, x1, x6)

inst_1068:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x190 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x190 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7590; op2val:0x7590;
   valaddr_reg:x7; val_offset:2088*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 2088*FLEN/8, x11, x1, x6)

inst_1069:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x190 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x190 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7590; op2val:0x7590;
   valaddr_reg:x7; val_offset:2090*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 2090*FLEN/8, x11, x1, x6)

inst_1070:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x145 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x145 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7145; op2val:0x7145;
   valaddr_reg:x7; val_offset:2092*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 2092*FLEN/8, x11, x1, x6)

inst_1071:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x145 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x145 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7145; op2val:0x7145;
   valaddr_reg:x7; val_offset:2094*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 2094*FLEN/8, x11, x1, x6)

inst_1072:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x145 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x145 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7145; op2val:0x7145;
   valaddr_reg:x7; val_offset:2096*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 2096*FLEN/8, x11, x1, x6)

inst_1073:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x145 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x145 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7145; op2val:0x7145;
   valaddr_reg:x7; val_offset:2098*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 2098*FLEN/8, x11, x1, x6)

inst_1074:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x145 and fs2 == 0 and fe2 == 0x1c and fm2 == 0x145 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7145; op2val:0x7145;
   valaddr_reg:x7; val_offset:2100*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 2100*FLEN/8, x11, x1, x6)

inst_1075:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x135 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x135 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6935; op2val:0x6935;
   valaddr_reg:x7; val_offset:2102*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 2102*FLEN/8, x11, x1, x6)

inst_1076:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x135 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x135 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6935; op2val:0x6935;
   valaddr_reg:x7; val_offset:2104*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 2104*FLEN/8, x11, x1, x6)

inst_1077:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x135 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x135 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6935; op2val:0x6935;
   valaddr_reg:x7; val_offset:2106*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 2106*FLEN/8, x11, x1, x6)

inst_1078:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x135 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x135 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6935; op2val:0x6935;
   valaddr_reg:x7; val_offset:2108*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 2108*FLEN/8, x11, x1, x6)

inst_1079:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x135 and fs2 == 0 and fe2 == 0x1a and fm2 == 0x135 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x6935; op2val:0x6935;
   valaddr_reg:x7; val_offset:2110*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 2110*FLEN/8, x11, x1, x6)

inst_1080:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x275 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x275 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a75; op2val:0x7a75;
   valaddr_reg:x7; val_offset:2112*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 2112*FLEN/8, x11, x1, x6)

inst_1081:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x275 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x275 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a75; op2val:0x7a75;
   valaddr_reg:x7; val_offset:2114*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 2114*FLEN/8, x11, x1, x6)

inst_1082:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x275 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x275 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a75; op2val:0x7a75;
   valaddr_reg:x7; val_offset:2116*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 2116*FLEN/8, x11, x1, x6)

inst_1083:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x275 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x275 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a75; op2val:0x7a75;
   valaddr_reg:x7; val_offset:2118*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 2118*FLEN/8, x11, x1, x6)

inst_1084:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x275 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x275 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a75; op2val:0x7a75;
   valaddr_reg:x7; val_offset:2120*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 2120*FLEN/8, x11, x1, x6)

inst_1085:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x047 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x047 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7447; op2val:0x7447;
   valaddr_reg:x7; val_offset:2122*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 2122*FLEN/8, x11, x1, x6)

inst_1086:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x047 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x047 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7447; op2val:0x7447;
   valaddr_reg:x7; val_offset:2124*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 2124*FLEN/8, x11, x1, x6)

inst_1087:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x047 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x047 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7447; op2val:0x7447;
   valaddr_reg:x7; val_offset:2126*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 2126*FLEN/8, x11, x1, x6)

inst_1088:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x047 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x047 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7447; op2val:0x7447;
   valaddr_reg:x7; val_offset:2128*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 2128*FLEN/8, x11, x1, x6)

inst_1089:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x047 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x047 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7447; op2val:0x7447;
   valaddr_reg:x7; val_offset:2130*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 2130*FLEN/8, x11, x1, x6)

inst_1090:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ab and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ab and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bab; op2val:0x7bab;
   valaddr_reg:x7; val_offset:2132*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 2132*FLEN/8, x11, x1, x6)

inst_1091:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ab and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ab and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bab; op2val:0x7bab;
   valaddr_reg:x7; val_offset:2134*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 2134*FLEN/8, x11, x1, x6)

inst_1092:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ab and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ab and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bab; op2val:0x7bab;
   valaddr_reg:x7; val_offset:2136*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 2136*FLEN/8, x11, x1, x6)

inst_1093:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ab and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ab and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bab; op2val:0x7bab;
   valaddr_reg:x7; val_offset:2138*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 2138*FLEN/8, x11, x1, x6)

inst_1094:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ab and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ab and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7bab; op2val:0x7bab;
   valaddr_reg:x7; val_offset:2140*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 2140*FLEN/8, x11, x1, x6)

inst_1095:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x233 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x233 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a33; op2val:0x7a33;
   valaddr_reg:x7; val_offset:2142*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 2142*FLEN/8, x11, x1, x6)

inst_1096:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x233 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x233 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a33; op2val:0x7a33;
   valaddr_reg:x7; val_offset:2144*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 2144*FLEN/8, x11, x1, x6)

inst_1097:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x233 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x233 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a33; op2val:0x7a33;
   valaddr_reg:x7; val_offset:2146*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 2146*FLEN/8, x11, x1, x6)

inst_1098:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x233 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x233 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a33; op2val:0x7a33;
   valaddr_reg:x7; val_offset:2148*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 2148*FLEN/8, x11, x1, x6)

inst_1099:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x233 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x233 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7a33; op2val:0x7a33;
   valaddr_reg:x7; val_offset:2150*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 2150*FLEN/8, x11, x1, x6)

inst_1100:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x146 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x146 and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7946; op2val:0x7946;
   valaddr_reg:x7; val_offset:2152*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 2152*FLEN/8, x11, x1, x6)

inst_1101:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x146 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x146 and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7946; op2val:0x7946;
   valaddr_reg:x7; val_offset:2154*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 2154*FLEN/8, x11, x1, x6)

inst_1102:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x146 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x146 and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7946; op2val:0x7946;
   valaddr_reg:x7; val_offset:2156*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 2156*FLEN/8, x11, x1, x6)

inst_1103:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x146 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x146 and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7946; op2val:0x7946;
   valaddr_reg:x7; val_offset:2158*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 2158*FLEN/8, x11, x1, x6)

inst_1104:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x146 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x146 and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7946; op2val:0x7946;
   valaddr_reg:x7; val_offset:2160*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 2160*FLEN/8, x11, x1, x6)

inst_1105:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x31e and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x771e; op2val:0x771e;
   valaddr_reg:x7; val_offset:2162*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 2162*FLEN/8, x11, x1, x6)

inst_1106:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x31e and  fcsr == 0x20 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x771e; op2val:0x771e;
   valaddr_reg:x7; val_offset:2164*FLEN/8; rmval:dyn; fcsr: 32;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 32, 0, x7, 2164*FLEN/8, x11, x1, x6)

inst_1107:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x31e and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x771e; op2val:0x771e;
   valaddr_reg:x7; val_offset:2166*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 2166*FLEN/8, x11, x1, x6)

inst_1108:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x31e and  fcsr == 0x60 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x771e; op2val:0x771e;
   valaddr_reg:x7; val_offset:2168*FLEN/8; rmval:dyn; fcsr: 96;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 96, 0, x7, 2168*FLEN/8, x11, x1, x6)

inst_1109:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x31e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x31e and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x771e; op2val:0x771e;
   valaddr_reg:x7; val_offset:2170*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 2170*FLEN/8, x11, x1, x6)

inst_1110:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and  fcsr == 0x0 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x704c; op2val:0x704c;
   valaddr_reg:x7; val_offset:2172*FLEN/8; rmval:dyn; fcsr: 0;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 0, 0, x7, 2172*FLEN/8, x11, x1, x6)

inst_1111:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1c and fm2 == 0x04c and  fcsr == 0x80 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x704c; op2val:0x704c;
   valaddr_reg:x7; val_offset:2174*FLEN/8; rmval:dyn; fcsr: 128;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 128, 0, x7, 2174*FLEN/8, x11, x1, x6)

inst_1112:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ae and  fcsr == 0x40 and rm_val == 7  and rs1_sgn_prefix == 0x0000 and rs2_sgn_prefix == 0x0000  
/* opcode: fsub.h ; op1:x30; op2:x29; dest:x31; op1val:0x7aae; op2val:0x7aae;
   valaddr_reg:x7; val_offset:2176*FLEN/8; rmval:dyn; fcsr: 64;
   correctval:??; testreg:x6*/
TEST_FPRR_OP(fsub.h, x31, x30, x29, dyn, 64, 0, x7, 2176*FLEN/8, x11, x1, x6)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(28748,32,FLEN)
NAN_BOXED(28748,32,FLEN)
NAN_BOXED(28748,32,FLEN)
NAN_BOXED(28748,32,FLEN)
NAN_BOXED(28748,32,FLEN)
NAN_BOXED(28748,32,FLEN)
NAN_BOXED(28748,32,FLEN)
NAN_BOXED(28748,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(31259,32,FLEN)
NAN_BOXED(31259,32,FLEN)
NAN_BOXED(31259,32,FLEN)
NAN_BOXED(31259,32,FLEN)
NAN_BOXED(31259,32,FLEN)
NAN_BOXED(31259,32,FLEN)
NAN_BOXED(31259,32,FLEN)
NAN_BOXED(31259,32,FLEN)
NAN_BOXED(31259,32,FLEN)
NAN_BOXED(31259,32,FLEN)
NAN_BOXED(30700,32,FLEN)
NAN_BOXED(30700,32,FLEN)
NAN_BOXED(30700,32,FLEN)
NAN_BOXED(30700,32,FLEN)
test_dataset_1:
NAN_BOXED(30700,32,FLEN)
NAN_BOXED(30700,32,FLEN)
NAN_BOXED(30700,32,FLEN)
NAN_BOXED(30700,32,FLEN)
NAN_BOXED(30700,32,FLEN)
NAN_BOXED(30700,32,FLEN)
NAN_BOXED(31029,32,FLEN)
NAN_BOXED(31029,32,FLEN)
NAN_BOXED(31029,32,FLEN)
NAN_BOXED(31029,32,FLEN)
NAN_BOXED(31029,32,FLEN)
NAN_BOXED(31029,32,FLEN)
NAN_BOXED(31029,32,FLEN)
NAN_BOXED(31029,32,FLEN)
NAN_BOXED(31029,32,FLEN)
NAN_BOXED(31029,32,FLEN)
NAN_BOXED(28161,32,FLEN)
NAN_BOXED(28161,32,FLEN)
NAN_BOXED(28161,32,FLEN)
NAN_BOXED(28161,32,FLEN)
NAN_BOXED(28161,32,FLEN)
NAN_BOXED(28161,32,FLEN)
NAN_BOXED(28161,32,FLEN)
NAN_BOXED(28161,32,FLEN)
test_dataset_2:
NAN_BOXED(28161,16,FLEN)
NAN_BOXED(28161,16,FLEN)
NAN_BOXED(31406,16,FLEN)
NAN_BOXED(31406,16,FLEN)
NAN_BOXED(31406,16,FLEN)
NAN_BOXED(31406,16,FLEN)
NAN_BOXED(31406,16,FLEN)
NAN_BOXED(31406,16,FLEN)
NAN_BOXED(31406,16,FLEN)
NAN_BOXED(31406,16,FLEN)
NAN_BOXED(31406,16,FLEN)
NAN_BOXED(31406,16,FLEN)
NAN_BOXED(31256,16,FLEN)
NAN_BOXED(31256,16,FLEN)
NAN_BOXED(31256,16,FLEN)
NAN_BOXED(31256,16,FLEN)
NAN_BOXED(31256,16,FLEN)
NAN_BOXED(31256,16,FLEN)
NAN_BOXED(31256,16,FLEN)
NAN_BOXED(31256,16,FLEN)
NAN_BOXED(31256,16,FLEN)
NAN_BOXED(31256,16,FLEN)
NAN_BOXED(30495,16,FLEN)
NAN_BOXED(30495,16,FLEN)
NAN_BOXED(30495,16,FLEN)
NAN_BOXED(30495,16,FLEN)
NAN_BOXED(30495,16,FLEN)
NAN_BOXED(30495,16,FLEN)
NAN_BOXED(30495,16,FLEN)
NAN_BOXED(30495,16,FLEN)
NAN_BOXED(30495,16,FLEN)
NAN_BOXED(30495,16,FLEN)
NAN_BOXED(29521,16,FLEN)
NAN_BOXED(29521,16,FLEN)
NAN_BOXED(29521,16,FLEN)
NAN_BOXED(29521,16,FLEN)
NAN_BOXED(29521,16,FLEN)
NAN_BOXED(29521,16,FLEN)
NAN_BOXED(29521,16,FLEN)
NAN_BOXED(29521,16,FLEN)
NAN_BOXED(29521,16,FLEN)
NAN_BOXED(29521,16,FLEN)
NAN_BOXED(31541,16,FLEN)
NAN_BOXED(31541,16,FLEN)
NAN_BOXED(31541,16,FLEN)
NAN_BOXED(31541,16,FLEN)
NAN_BOXED(31541,16,FLEN)
NAN_BOXED(31541,16,FLEN)
NAN_BOXED(31541,16,FLEN)
NAN_BOXED(31541,16,FLEN)
NAN_BOXED(31541,16,FLEN)
NAN_BOXED(31541,16,FLEN)
NAN_BOXED(26243,16,FLEN)
NAN_BOXED(26243,16,FLEN)
NAN_BOXED(26243,16,FLEN)
NAN_BOXED(26243,16,FLEN)
NAN_BOXED(26243,16,FLEN)
NAN_BOXED(26243,16,FLEN)
NAN_BOXED(26243,16,FLEN)
NAN_BOXED(26243,16,FLEN)
NAN_BOXED(26243,16,FLEN)
NAN_BOXED(26243,16,FLEN)
NAN_BOXED(31618,16,FLEN)
NAN_BOXED(31618,16,FLEN)
NAN_BOXED(31618,16,FLEN)
NAN_BOXED(31618,16,FLEN)
NAN_BOXED(31618,16,FLEN)
NAN_BOXED(31618,16,FLEN)
NAN_BOXED(31618,16,FLEN)
NAN_BOXED(31618,16,FLEN)
NAN_BOXED(31618,16,FLEN)
NAN_BOXED(31618,16,FLEN)
NAN_BOXED(29421,16,FLEN)
NAN_BOXED(29421,16,FLEN)
NAN_BOXED(29421,16,FLEN)
NAN_BOXED(29421,16,FLEN)
NAN_BOXED(29421,16,FLEN)
NAN_BOXED(29421,16,FLEN)
NAN_BOXED(29421,16,FLEN)
NAN_BOXED(29421,16,FLEN)
NAN_BOXED(29421,16,FLEN)
NAN_BOXED(29421,16,FLEN)
NAN_BOXED(26479,16,FLEN)
NAN_BOXED(26479,16,FLEN)
NAN_BOXED(26479,16,FLEN)
NAN_BOXED(26479,16,FLEN)
NAN_BOXED(26479,16,FLEN)
NAN_BOXED(26479,16,FLEN)
NAN_BOXED(26479,16,FLEN)
NAN_BOXED(26479,16,FLEN)
NAN_BOXED(26479,16,FLEN)
NAN_BOXED(26479,16,FLEN)
NAN_BOXED(30464,16,FLEN)
NAN_BOXED(30464,16,FLEN)
NAN_BOXED(30464,16,FLEN)
NAN_BOXED(30464,16,FLEN)
NAN_BOXED(30464,16,FLEN)
NAN_BOXED(30464,16,FLEN)
NAN_BOXED(30464,16,FLEN)
NAN_BOXED(30464,16,FLEN)
NAN_BOXED(30464,16,FLEN)
NAN_BOXED(30464,16,FLEN)
NAN_BOXED(29556,16,FLEN)
NAN_BOXED(29556,16,FLEN)
NAN_BOXED(29556,16,FLEN)
NAN_BOXED(29556,16,FLEN)
NAN_BOXED(29556,16,FLEN)
NAN_BOXED(29556,16,FLEN)
NAN_BOXED(29556,16,FLEN)
NAN_BOXED(29556,16,FLEN)
NAN_BOXED(29556,16,FLEN)
NAN_BOXED(29556,16,FLEN)
NAN_BOXED(29439,16,FLEN)
NAN_BOXED(29439,16,FLEN)
NAN_BOXED(29439,16,FLEN)
NAN_BOXED(29439,16,FLEN)
NAN_BOXED(29439,16,FLEN)
NAN_BOXED(29439,16,FLEN)
NAN_BOXED(29439,16,FLEN)
NAN_BOXED(29439,16,FLEN)
NAN_BOXED(29439,16,FLEN)
NAN_BOXED(29439,16,FLEN)
NAN_BOXED(29858,16,FLEN)
NAN_BOXED(29858,16,FLEN)
NAN_BOXED(29858,16,FLEN)
NAN_BOXED(29858,16,FLEN)
NAN_BOXED(29858,16,FLEN)
NAN_BOXED(29858,16,FLEN)
NAN_BOXED(29858,16,FLEN)
NAN_BOXED(29858,16,FLEN)
NAN_BOXED(29858,16,FLEN)
NAN_BOXED(29858,16,FLEN)
NAN_BOXED(31410,16,FLEN)
NAN_BOXED(31410,16,FLEN)
NAN_BOXED(31410,16,FLEN)
NAN_BOXED(31410,16,FLEN)
NAN_BOXED(31410,16,FLEN)
NAN_BOXED(31410,16,FLEN)
NAN_BOXED(31410,16,FLEN)
NAN_BOXED(31410,16,FLEN)
NAN_BOXED(31410,16,FLEN)
NAN_BOXED(31410,16,FLEN)
NAN_BOXED(31010,16,FLEN)
NAN_BOXED(31010,16,FLEN)
NAN_BOXED(31010,16,FLEN)
NAN_BOXED(31010,16,FLEN)
NAN_BOXED(31010,16,FLEN)
NAN_BOXED(31010,16,FLEN)
NAN_BOXED(31010,16,FLEN)
NAN_BOXED(31010,16,FLEN)
NAN_BOXED(31010,16,FLEN)
NAN_BOXED(31010,16,FLEN)
NAN_BOXED(31727,16,FLEN)
NAN_BOXED(31727,16,FLEN)
NAN_BOXED(31727,16,FLEN)
NAN_BOXED(31727,16,FLEN)
NAN_BOXED(31727,16,FLEN)
NAN_BOXED(31727,16,FLEN)
NAN_BOXED(31727,16,FLEN)
NAN_BOXED(31727,16,FLEN)
NAN_BOXED(31727,16,FLEN)
NAN_BOXED(31727,16,FLEN)
NAN_BOXED(28603,16,FLEN)
NAN_BOXED(28603,16,FLEN)
NAN_BOXED(28603,16,FLEN)
NAN_BOXED(28603,16,FLEN)
NAN_BOXED(28603,16,FLEN)
NAN_BOXED(28603,16,FLEN)
NAN_BOXED(28603,16,FLEN)
NAN_BOXED(28603,16,FLEN)
NAN_BOXED(28603,16,FLEN)
NAN_BOXED(28603,16,FLEN)
NAN_BOXED(31172,16,FLEN)
NAN_BOXED(31172,16,FLEN)
NAN_BOXED(31172,16,FLEN)
NAN_BOXED(31172,16,FLEN)
NAN_BOXED(31172,16,FLEN)
NAN_BOXED(31172,16,FLEN)
NAN_BOXED(31172,16,FLEN)
NAN_BOXED(31172,16,FLEN)
NAN_BOXED(31172,16,FLEN)
NAN_BOXED(31172,16,FLEN)
NAN_BOXED(31612,16,FLEN)
NAN_BOXED(31612,16,FLEN)
NAN_BOXED(31612,16,FLEN)
NAN_BOXED(31612,16,FLEN)
NAN_BOXED(31612,16,FLEN)
NAN_BOXED(31612,16,FLEN)
NAN_BOXED(31612,16,FLEN)
NAN_BOXED(31612,16,FLEN)
NAN_BOXED(31612,16,FLEN)
NAN_BOXED(31612,16,FLEN)
NAN_BOXED(31395,16,FLEN)
NAN_BOXED(31395,16,FLEN)
NAN_BOXED(31395,16,FLEN)
NAN_BOXED(31395,16,FLEN)
NAN_BOXED(31395,16,FLEN)
NAN_BOXED(31395,16,FLEN)
NAN_BOXED(31395,16,FLEN)
NAN_BOXED(31395,16,FLEN)
NAN_BOXED(31395,16,FLEN)
NAN_BOXED(31395,16,FLEN)
NAN_BOXED(29914,16,FLEN)
NAN_BOXED(29914,16,FLEN)
NAN_BOXED(29914,16,FLEN)
NAN_BOXED(29914,16,FLEN)
NAN_BOXED(29914,16,FLEN)
NAN_BOXED(29914,16,FLEN)
NAN_BOXED(29914,16,FLEN)
NAN_BOXED(29914,16,FLEN)
NAN_BOXED(29914,16,FLEN)
NAN_BOXED(29914,16,FLEN)
NAN_BOXED(31502,16,FLEN)
NAN_BOXED(31502,16,FLEN)
NAN_BOXED(31502,16,FLEN)
NAN_BOXED(31502,16,FLEN)
NAN_BOXED(31502,16,FLEN)
NAN_BOXED(31502,16,FLEN)
NAN_BOXED(31502,16,FLEN)
NAN_BOXED(31502,16,FLEN)
NAN_BOXED(31502,16,FLEN)
NAN_BOXED(31502,16,FLEN)
NAN_BOXED(30730,16,FLEN)
NAN_BOXED(30730,16,FLEN)
NAN_BOXED(30730,16,FLEN)
NAN_BOXED(30730,16,FLEN)
NAN_BOXED(30730,16,FLEN)
NAN_BOXED(30730,16,FLEN)
NAN_BOXED(30730,16,FLEN)
NAN_BOXED(30730,16,FLEN)
NAN_BOXED(30730,16,FLEN)
NAN_BOXED(30730,16,FLEN)
NAN_BOXED(26731,16,FLEN)
NAN_BOXED(26731,16,FLEN)
NAN_BOXED(26731,16,FLEN)
NAN_BOXED(26731,16,FLEN)
NAN_BOXED(26731,16,FLEN)
NAN_BOXED(26731,16,FLEN)
NAN_BOXED(26731,16,FLEN)
NAN_BOXED(26731,16,FLEN)
NAN_BOXED(26731,16,FLEN)
NAN_BOXED(26731,16,FLEN)
NAN_BOXED(31328,16,FLEN)
NAN_BOXED(31328,16,FLEN)
NAN_BOXED(31328,16,FLEN)
NAN_BOXED(31328,16,FLEN)
NAN_BOXED(31328,16,FLEN)
NAN_BOXED(31328,16,FLEN)
NAN_BOXED(31328,16,FLEN)
NAN_BOXED(31328,16,FLEN)
NAN_BOXED(31328,16,FLEN)
NAN_BOXED(31328,16,FLEN)
NAN_BOXED(29064,16,FLEN)
NAN_BOXED(29064,16,FLEN)
NAN_BOXED(29064,16,FLEN)
NAN_BOXED(29064,16,FLEN)
NAN_BOXED(29064,16,FLEN)
NAN_BOXED(29064,16,FLEN)
NAN_BOXED(29064,16,FLEN)
NAN_BOXED(29064,16,FLEN)
NAN_BOXED(29064,16,FLEN)
NAN_BOXED(29064,16,FLEN)
NAN_BOXED(31135,16,FLEN)
NAN_BOXED(31135,16,FLEN)
NAN_BOXED(31135,16,FLEN)
NAN_BOXED(31135,16,FLEN)
NAN_BOXED(31135,16,FLEN)
NAN_BOXED(31135,16,FLEN)
NAN_BOXED(31135,16,FLEN)
NAN_BOXED(31135,16,FLEN)
NAN_BOXED(31135,16,FLEN)
NAN_BOXED(31135,16,FLEN)
NAN_BOXED(30206,16,FLEN)
NAN_BOXED(30206,16,FLEN)
NAN_BOXED(30206,16,FLEN)
NAN_BOXED(30206,16,FLEN)
NAN_BOXED(30206,16,FLEN)
NAN_BOXED(30206,16,FLEN)
NAN_BOXED(30206,16,FLEN)
NAN_BOXED(30206,16,FLEN)
NAN_BOXED(30206,16,FLEN)
NAN_BOXED(30206,16,FLEN)
NAN_BOXED(30736,16,FLEN)
NAN_BOXED(30736,16,FLEN)
NAN_BOXED(30736,16,FLEN)
NAN_BOXED(30736,16,FLEN)
NAN_BOXED(30736,16,FLEN)
NAN_BOXED(30736,16,FLEN)
NAN_BOXED(30736,16,FLEN)
NAN_BOXED(30736,16,FLEN)
NAN_BOXED(30736,16,FLEN)
NAN_BOXED(30736,16,FLEN)
NAN_BOXED(30762,16,FLEN)
NAN_BOXED(30762,16,FLEN)
NAN_BOXED(30762,16,FLEN)
NAN_BOXED(30762,16,FLEN)
NAN_BOXED(30762,16,FLEN)
NAN_BOXED(30762,16,FLEN)
NAN_BOXED(30762,16,FLEN)
NAN_BOXED(30762,16,FLEN)
NAN_BOXED(30762,16,FLEN)
NAN_BOXED(30762,16,FLEN)
NAN_BOXED(30676,16,FLEN)
NAN_BOXED(30676,16,FLEN)
NAN_BOXED(30676,16,FLEN)
NAN_BOXED(30676,16,FLEN)
NAN_BOXED(30676,16,FLEN)
NAN_BOXED(30676,16,FLEN)
NAN_BOXED(30676,16,FLEN)
NAN_BOXED(30676,16,FLEN)
NAN_BOXED(30676,16,FLEN)
NAN_BOXED(30676,16,FLEN)
NAN_BOXED(27024,16,FLEN)
NAN_BOXED(27024,16,FLEN)
NAN_BOXED(27024,16,FLEN)
NAN_BOXED(27024,16,FLEN)
NAN_BOXED(27024,16,FLEN)
NAN_BOXED(27024,16,FLEN)
NAN_BOXED(27024,16,FLEN)
NAN_BOXED(27024,16,FLEN)
NAN_BOXED(27024,16,FLEN)
NAN_BOXED(27024,16,FLEN)
NAN_BOXED(31708,16,FLEN)
NAN_BOXED(31708,16,FLEN)
NAN_BOXED(31708,16,FLEN)
NAN_BOXED(31708,16,FLEN)
NAN_BOXED(31708,16,FLEN)
NAN_BOXED(31708,16,FLEN)
NAN_BOXED(31708,16,FLEN)
NAN_BOXED(31708,16,FLEN)
NAN_BOXED(31708,16,FLEN)
NAN_BOXED(31708,16,FLEN)
NAN_BOXED(30283,16,FLEN)
NAN_BOXED(30283,16,FLEN)
NAN_BOXED(30283,16,FLEN)
NAN_BOXED(30283,16,FLEN)
NAN_BOXED(30283,16,FLEN)
NAN_BOXED(30283,16,FLEN)
NAN_BOXED(30283,16,FLEN)
NAN_BOXED(30283,16,FLEN)
NAN_BOXED(30283,16,FLEN)
NAN_BOXED(30283,16,FLEN)
NAN_BOXED(30724,16,FLEN)
NAN_BOXED(30724,16,FLEN)
NAN_BOXED(30724,16,FLEN)
NAN_BOXED(30724,16,FLEN)
NAN_BOXED(30724,16,FLEN)
NAN_BOXED(30724,16,FLEN)
NAN_BOXED(30724,16,FLEN)
NAN_BOXED(30724,16,FLEN)
NAN_BOXED(30724,16,FLEN)
NAN_BOXED(30724,16,FLEN)
NAN_BOXED(31273,16,FLEN)
NAN_BOXED(31273,16,FLEN)
NAN_BOXED(31273,16,FLEN)
NAN_BOXED(31273,16,FLEN)
NAN_BOXED(31273,16,FLEN)
NAN_BOXED(31273,16,FLEN)
NAN_BOXED(31273,16,FLEN)
NAN_BOXED(31273,16,FLEN)
NAN_BOXED(31273,16,FLEN)
NAN_BOXED(31273,16,FLEN)
NAN_BOXED(31457,16,FLEN)
NAN_BOXED(31457,16,FLEN)
NAN_BOXED(31457,16,FLEN)
NAN_BOXED(31457,16,FLEN)
NAN_BOXED(31457,16,FLEN)
NAN_BOXED(31457,16,FLEN)
NAN_BOXED(31457,16,FLEN)
NAN_BOXED(31457,16,FLEN)
NAN_BOXED(31457,16,FLEN)
NAN_BOXED(31457,16,FLEN)
NAN_BOXED(30747,16,FLEN)
NAN_BOXED(30747,16,FLEN)
NAN_BOXED(30747,16,FLEN)
NAN_BOXED(30747,16,FLEN)
NAN_BOXED(30747,16,FLEN)
NAN_BOXED(30747,16,FLEN)
NAN_BOXED(30747,16,FLEN)
NAN_BOXED(30747,16,FLEN)
NAN_BOXED(30747,16,FLEN)
NAN_BOXED(30747,16,FLEN)
NAN_BOXED(30878,16,FLEN)
NAN_BOXED(30878,16,FLEN)
NAN_BOXED(30878,16,FLEN)
NAN_BOXED(30878,16,FLEN)
NAN_BOXED(30878,16,FLEN)
NAN_BOXED(30878,16,FLEN)
NAN_BOXED(30878,16,FLEN)
NAN_BOXED(30878,16,FLEN)
NAN_BOXED(30878,16,FLEN)
NAN_BOXED(30878,16,FLEN)
NAN_BOXED(29774,16,FLEN)
NAN_BOXED(29774,16,FLEN)
NAN_BOXED(29774,16,FLEN)
NAN_BOXED(29774,16,FLEN)
NAN_BOXED(29774,16,FLEN)
NAN_BOXED(29774,16,FLEN)
NAN_BOXED(29774,16,FLEN)
NAN_BOXED(29774,16,FLEN)
NAN_BOXED(29774,16,FLEN)
NAN_BOXED(29774,16,FLEN)
NAN_BOXED(31655,16,FLEN)
NAN_BOXED(31655,16,FLEN)
NAN_BOXED(31655,16,FLEN)
NAN_BOXED(31655,16,FLEN)
NAN_BOXED(31655,16,FLEN)
NAN_BOXED(31655,16,FLEN)
NAN_BOXED(31655,16,FLEN)
NAN_BOXED(31655,16,FLEN)
NAN_BOXED(31655,16,FLEN)
NAN_BOXED(31655,16,FLEN)
NAN_BOXED(31300,16,FLEN)
NAN_BOXED(31300,16,FLEN)
NAN_BOXED(31300,16,FLEN)
NAN_BOXED(31300,16,FLEN)
NAN_BOXED(31300,16,FLEN)
NAN_BOXED(31300,16,FLEN)
NAN_BOXED(31300,16,FLEN)
NAN_BOXED(31300,16,FLEN)
NAN_BOXED(31300,16,FLEN)
NAN_BOXED(31300,16,FLEN)
NAN_BOXED(31510,16,FLEN)
NAN_BOXED(31510,16,FLEN)
NAN_BOXED(31510,16,FLEN)
NAN_BOXED(31510,16,FLEN)
NAN_BOXED(31510,16,FLEN)
NAN_BOXED(31510,16,FLEN)
NAN_BOXED(31510,16,FLEN)
NAN_BOXED(31510,16,FLEN)
NAN_BOXED(31510,16,FLEN)
NAN_BOXED(31510,16,FLEN)
NAN_BOXED(31352,16,FLEN)
NAN_BOXED(31352,16,FLEN)
NAN_BOXED(31352,16,FLEN)
NAN_BOXED(31352,16,FLEN)
NAN_BOXED(31352,16,FLEN)
NAN_BOXED(31352,16,FLEN)
NAN_BOXED(31352,16,FLEN)
NAN_BOXED(31352,16,FLEN)
NAN_BOXED(31352,16,FLEN)
NAN_BOXED(31352,16,FLEN)
NAN_BOXED(30845,16,FLEN)
NAN_BOXED(30845,16,FLEN)
NAN_BOXED(30845,16,FLEN)
NAN_BOXED(30845,16,FLEN)
NAN_BOXED(30845,16,FLEN)
NAN_BOXED(30845,16,FLEN)
NAN_BOXED(30845,16,FLEN)
NAN_BOXED(30845,16,FLEN)
NAN_BOXED(30845,16,FLEN)
NAN_BOXED(30845,16,FLEN)
NAN_BOXED(27438,16,FLEN)
NAN_BOXED(27438,16,FLEN)
NAN_BOXED(27438,16,FLEN)
NAN_BOXED(27438,16,FLEN)
NAN_BOXED(27438,16,FLEN)
NAN_BOXED(27438,16,FLEN)
NAN_BOXED(27438,16,FLEN)
NAN_BOXED(27438,16,FLEN)
NAN_BOXED(27438,16,FLEN)
NAN_BOXED(27438,16,FLEN)
NAN_BOXED(30862,16,FLEN)
NAN_BOXED(30862,16,FLEN)
NAN_BOXED(30862,16,FLEN)
NAN_BOXED(30862,16,FLEN)
NAN_BOXED(30862,16,FLEN)
NAN_BOXED(30862,16,FLEN)
NAN_BOXED(30862,16,FLEN)
NAN_BOXED(30862,16,FLEN)
NAN_BOXED(30862,16,FLEN)
NAN_BOXED(30862,16,FLEN)
NAN_BOXED(30729,16,FLEN)
NAN_BOXED(30729,16,FLEN)
NAN_BOXED(30729,16,FLEN)
NAN_BOXED(30729,16,FLEN)
NAN_BOXED(30729,16,FLEN)
NAN_BOXED(30729,16,FLEN)
NAN_BOXED(30729,16,FLEN)
NAN_BOXED(30729,16,FLEN)
NAN_BOXED(30729,16,FLEN)
NAN_BOXED(30729,16,FLEN)
NAN_BOXED(30132,16,FLEN)
NAN_BOXED(30132,16,FLEN)
NAN_BOXED(30132,16,FLEN)
NAN_BOXED(30132,16,FLEN)
NAN_BOXED(30132,16,FLEN)
NAN_BOXED(30132,16,FLEN)
NAN_BOXED(30132,16,FLEN)
NAN_BOXED(30132,16,FLEN)
NAN_BOXED(30132,16,FLEN)
NAN_BOXED(30132,16,FLEN)
NAN_BOXED(30798,16,FLEN)
NAN_BOXED(30798,16,FLEN)
NAN_BOXED(30798,16,FLEN)
NAN_BOXED(30798,16,FLEN)
NAN_BOXED(30798,16,FLEN)
NAN_BOXED(30798,16,FLEN)
NAN_BOXED(30798,16,FLEN)
NAN_BOXED(30798,16,FLEN)
NAN_BOXED(30798,16,FLEN)
NAN_BOXED(30798,16,FLEN)
NAN_BOXED(30949,16,FLEN)
NAN_BOXED(30949,16,FLEN)
NAN_BOXED(30949,16,FLEN)
NAN_BOXED(30949,16,FLEN)
NAN_BOXED(30949,16,FLEN)
NAN_BOXED(30949,16,FLEN)
NAN_BOXED(30949,16,FLEN)
NAN_BOXED(30949,16,FLEN)
NAN_BOXED(30949,16,FLEN)
NAN_BOXED(30949,16,FLEN)
NAN_BOXED(26409,16,FLEN)
NAN_BOXED(26409,16,FLEN)
NAN_BOXED(26409,16,FLEN)
NAN_BOXED(26409,16,FLEN)
NAN_BOXED(26409,16,FLEN)
NAN_BOXED(26409,16,FLEN)
NAN_BOXED(26409,16,FLEN)
NAN_BOXED(26409,16,FLEN)
NAN_BOXED(26409,16,FLEN)
NAN_BOXED(26409,16,FLEN)
NAN_BOXED(29099,16,FLEN)
NAN_BOXED(29099,16,FLEN)
NAN_BOXED(29099,16,FLEN)
NAN_BOXED(29099,16,FLEN)
NAN_BOXED(29099,16,FLEN)
NAN_BOXED(29099,16,FLEN)
NAN_BOXED(29099,16,FLEN)
NAN_BOXED(29099,16,FLEN)
NAN_BOXED(29099,16,FLEN)
NAN_BOXED(29099,16,FLEN)
NAN_BOXED(31458,16,FLEN)
NAN_BOXED(31458,16,FLEN)
NAN_BOXED(31458,16,FLEN)
NAN_BOXED(31458,16,FLEN)
NAN_BOXED(31458,16,FLEN)
NAN_BOXED(31458,16,FLEN)
NAN_BOXED(31458,16,FLEN)
NAN_BOXED(31458,16,FLEN)
NAN_BOXED(31458,16,FLEN)
NAN_BOXED(31458,16,FLEN)
NAN_BOXED(31327,16,FLEN)
NAN_BOXED(31327,16,FLEN)
NAN_BOXED(31327,16,FLEN)
NAN_BOXED(31327,16,FLEN)
NAN_BOXED(31327,16,FLEN)
NAN_BOXED(31327,16,FLEN)
NAN_BOXED(31327,16,FLEN)
NAN_BOXED(31327,16,FLEN)
NAN_BOXED(31327,16,FLEN)
NAN_BOXED(31327,16,FLEN)
NAN_BOXED(29717,16,FLEN)
NAN_BOXED(29717,16,FLEN)
NAN_BOXED(29717,16,FLEN)
NAN_BOXED(29717,16,FLEN)
NAN_BOXED(29717,16,FLEN)
NAN_BOXED(29717,16,FLEN)
NAN_BOXED(29717,16,FLEN)
NAN_BOXED(29717,16,FLEN)
NAN_BOXED(29717,16,FLEN)
NAN_BOXED(29717,16,FLEN)
NAN_BOXED(31073,16,FLEN)
NAN_BOXED(31073,16,FLEN)
NAN_BOXED(31073,16,FLEN)
NAN_BOXED(31073,16,FLEN)
NAN_BOXED(31073,16,FLEN)
NAN_BOXED(31073,16,FLEN)
NAN_BOXED(31073,16,FLEN)
NAN_BOXED(31073,16,FLEN)
NAN_BOXED(31073,16,FLEN)
NAN_BOXED(31073,16,FLEN)
NAN_BOXED(25670,16,FLEN)
NAN_BOXED(25670,16,FLEN)
NAN_BOXED(25670,16,FLEN)
NAN_BOXED(25670,16,FLEN)
NAN_BOXED(25670,16,FLEN)
NAN_BOXED(25670,16,FLEN)
NAN_BOXED(25670,16,FLEN)
NAN_BOXED(25670,16,FLEN)
NAN_BOXED(25670,16,FLEN)
NAN_BOXED(25670,16,FLEN)
NAN_BOXED(31242,16,FLEN)
NAN_BOXED(31242,16,FLEN)
NAN_BOXED(31242,16,FLEN)
NAN_BOXED(31242,16,FLEN)
NAN_BOXED(31242,16,FLEN)
NAN_BOXED(31242,16,FLEN)
NAN_BOXED(31242,16,FLEN)
NAN_BOXED(31242,16,FLEN)
NAN_BOXED(31242,16,FLEN)
NAN_BOXED(31242,16,FLEN)
NAN_BOXED(28417,16,FLEN)
NAN_BOXED(28417,16,FLEN)
NAN_BOXED(28417,16,FLEN)
NAN_BOXED(28417,16,FLEN)
NAN_BOXED(28417,16,FLEN)
NAN_BOXED(28417,16,FLEN)
NAN_BOXED(28417,16,FLEN)
NAN_BOXED(28417,16,FLEN)
NAN_BOXED(28417,16,FLEN)
NAN_BOXED(28417,16,FLEN)
NAN_BOXED(30082,16,FLEN)
NAN_BOXED(30082,16,FLEN)
NAN_BOXED(30082,16,FLEN)
NAN_BOXED(30082,16,FLEN)
NAN_BOXED(30082,16,FLEN)
NAN_BOXED(30082,16,FLEN)
NAN_BOXED(30082,16,FLEN)
NAN_BOXED(30082,16,FLEN)
NAN_BOXED(30082,16,FLEN)
NAN_BOXED(30082,16,FLEN)
NAN_BOXED(28955,16,FLEN)
NAN_BOXED(28955,16,FLEN)
NAN_BOXED(28955,16,FLEN)
NAN_BOXED(28955,16,FLEN)
NAN_BOXED(28955,16,FLEN)
NAN_BOXED(28955,16,FLEN)
NAN_BOXED(28955,16,FLEN)
NAN_BOXED(28955,16,FLEN)
NAN_BOXED(28955,16,FLEN)
NAN_BOXED(28955,16,FLEN)
NAN_BOXED(29024,16,FLEN)
NAN_BOXED(29024,16,FLEN)
NAN_BOXED(29024,16,FLEN)
NAN_BOXED(29024,16,FLEN)
NAN_BOXED(29024,16,FLEN)
NAN_BOXED(29024,16,FLEN)
NAN_BOXED(29024,16,FLEN)
NAN_BOXED(29024,16,FLEN)
NAN_BOXED(29024,16,FLEN)
NAN_BOXED(29024,16,FLEN)
NAN_BOXED(31152,16,FLEN)
NAN_BOXED(31152,16,FLEN)
NAN_BOXED(31152,16,FLEN)
NAN_BOXED(31152,16,FLEN)
NAN_BOXED(31152,16,FLEN)
NAN_BOXED(31152,16,FLEN)
NAN_BOXED(31152,16,FLEN)
NAN_BOXED(31152,16,FLEN)
NAN_BOXED(31152,16,FLEN)
NAN_BOXED(31152,16,FLEN)
NAN_BOXED(29990,16,FLEN)
NAN_BOXED(29990,16,FLEN)
NAN_BOXED(29990,16,FLEN)
NAN_BOXED(29990,16,FLEN)
NAN_BOXED(29990,16,FLEN)
NAN_BOXED(29990,16,FLEN)
NAN_BOXED(29990,16,FLEN)
NAN_BOXED(29990,16,FLEN)
NAN_BOXED(29990,16,FLEN)
NAN_BOXED(29990,16,FLEN)
NAN_BOXED(26125,16,FLEN)
NAN_BOXED(26125,16,FLEN)
NAN_BOXED(26125,16,FLEN)
NAN_BOXED(26125,16,FLEN)
NAN_BOXED(26125,16,FLEN)
NAN_BOXED(26125,16,FLEN)
NAN_BOXED(26125,16,FLEN)
NAN_BOXED(26125,16,FLEN)
NAN_BOXED(26125,16,FLEN)
NAN_BOXED(26125,16,FLEN)
NAN_BOXED(30395,16,FLEN)
NAN_BOXED(30395,16,FLEN)
NAN_BOXED(30395,16,FLEN)
NAN_BOXED(30395,16,FLEN)
NAN_BOXED(30395,16,FLEN)
NAN_BOXED(30395,16,FLEN)
NAN_BOXED(30395,16,FLEN)
NAN_BOXED(30395,16,FLEN)
NAN_BOXED(30395,16,FLEN)
NAN_BOXED(30395,16,FLEN)
NAN_BOXED(28405,16,FLEN)
NAN_BOXED(28405,16,FLEN)
NAN_BOXED(28405,16,FLEN)
NAN_BOXED(28405,16,FLEN)
NAN_BOXED(28405,16,FLEN)
NAN_BOXED(28405,16,FLEN)
NAN_BOXED(28405,16,FLEN)
NAN_BOXED(28405,16,FLEN)
NAN_BOXED(28405,16,FLEN)
NAN_BOXED(28405,16,FLEN)
NAN_BOXED(30740,16,FLEN)
NAN_BOXED(30740,16,FLEN)
NAN_BOXED(30740,16,FLEN)
NAN_BOXED(30740,16,FLEN)
NAN_BOXED(30740,16,FLEN)
NAN_BOXED(30740,16,FLEN)
NAN_BOXED(30740,16,FLEN)
NAN_BOXED(30740,16,FLEN)
NAN_BOXED(30740,16,FLEN)
NAN_BOXED(30740,16,FLEN)
NAN_BOXED(30935,16,FLEN)
NAN_BOXED(30935,16,FLEN)
NAN_BOXED(30935,16,FLEN)
NAN_BOXED(30935,16,FLEN)
NAN_BOXED(30935,16,FLEN)
NAN_BOXED(30935,16,FLEN)
NAN_BOXED(30935,16,FLEN)
NAN_BOXED(30935,16,FLEN)
NAN_BOXED(30935,16,FLEN)
NAN_BOXED(30935,16,FLEN)
NAN_BOXED(25940,16,FLEN)
NAN_BOXED(25940,16,FLEN)
NAN_BOXED(25940,16,FLEN)
NAN_BOXED(25940,16,FLEN)
NAN_BOXED(25940,16,FLEN)
NAN_BOXED(25940,16,FLEN)
NAN_BOXED(25940,16,FLEN)
NAN_BOXED(25940,16,FLEN)
NAN_BOXED(25940,16,FLEN)
NAN_BOXED(25940,16,FLEN)
NAN_BOXED(28847,16,FLEN)
NAN_BOXED(28847,16,FLEN)
NAN_BOXED(28847,16,FLEN)
NAN_BOXED(28847,16,FLEN)
NAN_BOXED(28847,16,FLEN)
NAN_BOXED(28847,16,FLEN)
NAN_BOXED(28847,16,FLEN)
NAN_BOXED(28847,16,FLEN)
NAN_BOXED(28847,16,FLEN)
NAN_BOXED(28847,16,FLEN)
NAN_BOXED(28960,16,FLEN)
NAN_BOXED(28960,16,FLEN)
NAN_BOXED(28960,16,FLEN)
NAN_BOXED(28960,16,FLEN)
NAN_BOXED(28960,16,FLEN)
NAN_BOXED(28960,16,FLEN)
NAN_BOXED(28960,16,FLEN)
NAN_BOXED(28960,16,FLEN)
NAN_BOXED(28960,16,FLEN)
NAN_BOXED(28960,16,FLEN)
NAN_BOXED(31084,16,FLEN)
NAN_BOXED(31084,16,FLEN)
NAN_BOXED(31084,16,FLEN)
NAN_BOXED(31084,16,FLEN)
NAN_BOXED(31084,16,FLEN)
NAN_BOXED(31084,16,FLEN)
NAN_BOXED(31084,16,FLEN)
NAN_BOXED(31084,16,FLEN)
NAN_BOXED(31084,16,FLEN)
NAN_BOXED(31084,16,FLEN)
NAN_BOXED(29454,16,FLEN)
NAN_BOXED(29454,16,FLEN)
NAN_BOXED(29454,16,FLEN)
NAN_BOXED(29454,16,FLEN)
NAN_BOXED(29454,16,FLEN)
NAN_BOXED(29454,16,FLEN)
NAN_BOXED(29454,16,FLEN)
NAN_BOXED(29454,16,FLEN)
NAN_BOXED(29454,16,FLEN)
NAN_BOXED(29454,16,FLEN)
NAN_BOXED(31329,16,FLEN)
NAN_BOXED(31329,16,FLEN)
NAN_BOXED(31329,16,FLEN)
NAN_BOXED(31329,16,FLEN)
NAN_BOXED(31329,16,FLEN)
NAN_BOXED(31329,16,FLEN)
NAN_BOXED(31329,16,FLEN)
NAN_BOXED(31329,16,FLEN)
NAN_BOXED(31329,16,FLEN)
NAN_BOXED(31329,16,FLEN)
NAN_BOXED(29475,16,FLEN)
NAN_BOXED(29475,16,FLEN)
NAN_BOXED(29475,16,FLEN)
NAN_BOXED(29475,16,FLEN)
NAN_BOXED(29475,16,FLEN)
NAN_BOXED(29475,16,FLEN)
NAN_BOXED(29475,16,FLEN)
NAN_BOXED(29475,16,FLEN)
NAN_BOXED(29475,16,FLEN)
NAN_BOXED(29475,16,FLEN)
NAN_BOXED(30288,16,FLEN)
NAN_BOXED(30288,16,FLEN)
NAN_BOXED(30288,16,FLEN)
NAN_BOXED(30288,16,FLEN)
NAN_BOXED(30288,16,FLEN)
NAN_BOXED(30288,16,FLEN)
NAN_BOXED(30288,16,FLEN)
NAN_BOXED(30288,16,FLEN)
NAN_BOXED(30288,16,FLEN)
NAN_BOXED(30288,16,FLEN)
NAN_BOXED(29987,16,FLEN)
NAN_BOXED(29987,16,FLEN)
NAN_BOXED(29987,16,FLEN)
NAN_BOXED(29987,16,FLEN)
NAN_BOXED(29987,16,FLEN)
NAN_BOXED(29987,16,FLEN)
NAN_BOXED(29987,16,FLEN)
NAN_BOXED(29987,16,FLEN)
NAN_BOXED(29987,16,FLEN)
NAN_BOXED(29987,16,FLEN)
NAN_BOXED(27525,16,FLEN)
NAN_BOXED(27525,16,FLEN)
NAN_BOXED(27525,16,FLEN)
NAN_BOXED(27525,16,FLEN)
NAN_BOXED(27525,16,FLEN)
NAN_BOXED(27525,16,FLEN)
NAN_BOXED(27525,16,FLEN)
NAN_BOXED(27525,16,FLEN)
NAN_BOXED(27525,16,FLEN)
NAN_BOXED(27525,16,FLEN)
NAN_BOXED(31677,16,FLEN)
NAN_BOXED(31677,16,FLEN)
NAN_BOXED(31677,16,FLEN)
NAN_BOXED(31677,16,FLEN)
NAN_BOXED(31677,16,FLEN)
NAN_BOXED(31677,16,FLEN)
NAN_BOXED(31677,16,FLEN)
NAN_BOXED(31677,16,FLEN)
NAN_BOXED(31677,16,FLEN)
NAN_BOXED(31677,16,FLEN)
NAN_BOXED(29926,16,FLEN)
NAN_BOXED(29926,16,FLEN)
NAN_BOXED(29926,16,FLEN)
NAN_BOXED(29926,16,FLEN)
NAN_BOXED(29926,16,FLEN)
NAN_BOXED(29926,16,FLEN)
NAN_BOXED(29926,16,FLEN)
NAN_BOXED(29926,16,FLEN)
NAN_BOXED(29926,16,FLEN)
NAN_BOXED(29926,16,FLEN)
NAN_BOXED(29942,16,FLEN)
NAN_BOXED(29942,16,FLEN)
NAN_BOXED(29942,16,FLEN)
NAN_BOXED(29942,16,FLEN)
NAN_BOXED(29942,16,FLEN)
NAN_BOXED(29942,16,FLEN)
NAN_BOXED(29942,16,FLEN)
NAN_BOXED(29942,16,FLEN)
NAN_BOXED(29942,16,FLEN)
NAN_BOXED(29942,16,FLEN)
NAN_BOXED(31218,16,FLEN)
NAN_BOXED(31218,16,FLEN)
NAN_BOXED(31218,16,FLEN)
NAN_BOXED(31218,16,FLEN)
NAN_BOXED(31218,16,FLEN)
NAN_BOXED(31218,16,FLEN)
NAN_BOXED(31218,16,FLEN)
NAN_BOXED(31218,16,FLEN)
NAN_BOXED(31218,16,FLEN)
NAN_BOXED(31218,16,FLEN)
NAN_BOXED(29705,16,FLEN)
NAN_BOXED(29705,16,FLEN)
NAN_BOXED(29705,16,FLEN)
NAN_BOXED(29705,16,FLEN)
NAN_BOXED(29705,16,FLEN)
NAN_BOXED(29705,16,FLEN)
NAN_BOXED(29705,16,FLEN)
NAN_BOXED(29705,16,FLEN)
NAN_BOXED(29705,16,FLEN)
NAN_BOXED(29705,16,FLEN)
NAN_BOXED(31494,16,FLEN)
NAN_BOXED(31494,16,FLEN)
NAN_BOXED(31494,16,FLEN)
NAN_BOXED(31494,16,FLEN)
NAN_BOXED(31494,16,FLEN)
NAN_BOXED(31494,16,FLEN)
NAN_BOXED(31494,16,FLEN)
NAN_BOXED(31494,16,FLEN)
NAN_BOXED(31494,16,FLEN)
NAN_BOXED(31494,16,FLEN)
NAN_BOXED(31373,16,FLEN)
NAN_BOXED(31373,16,FLEN)
NAN_BOXED(31373,16,FLEN)
NAN_BOXED(31373,16,FLEN)
NAN_BOXED(31373,16,FLEN)
NAN_BOXED(31373,16,FLEN)
NAN_BOXED(31373,16,FLEN)
NAN_BOXED(31373,16,FLEN)
NAN_BOXED(31373,16,FLEN)
NAN_BOXED(31373,16,FLEN)
NAN_BOXED(30863,16,FLEN)
NAN_BOXED(30863,16,FLEN)
NAN_BOXED(30863,16,FLEN)
NAN_BOXED(30863,16,FLEN)
NAN_BOXED(30863,16,FLEN)
NAN_BOXED(30863,16,FLEN)
NAN_BOXED(30863,16,FLEN)
NAN_BOXED(30863,16,FLEN)
NAN_BOXED(30863,16,FLEN)
NAN_BOXED(30863,16,FLEN)
NAN_BOXED(31472,16,FLEN)
NAN_BOXED(31472,16,FLEN)
NAN_BOXED(31472,16,FLEN)
NAN_BOXED(31472,16,FLEN)
NAN_BOXED(31472,16,FLEN)
NAN_BOXED(31472,16,FLEN)
NAN_BOXED(31472,16,FLEN)
NAN_BOXED(31472,16,FLEN)
NAN_BOXED(31472,16,FLEN)
NAN_BOXED(31472,16,FLEN)
NAN_BOXED(31137,16,FLEN)
NAN_BOXED(31137,16,FLEN)
NAN_BOXED(31137,16,FLEN)
NAN_BOXED(31137,16,FLEN)
NAN_BOXED(31137,16,FLEN)
NAN_BOXED(31137,16,FLEN)
NAN_BOXED(31137,16,FLEN)
NAN_BOXED(31137,16,FLEN)
NAN_BOXED(31137,16,FLEN)
NAN_BOXED(31137,16,FLEN)
NAN_BOXED(30219,16,FLEN)
NAN_BOXED(30219,16,FLEN)
NAN_BOXED(30219,16,FLEN)
NAN_BOXED(30219,16,FLEN)
NAN_BOXED(30219,16,FLEN)
NAN_BOXED(30219,16,FLEN)
NAN_BOXED(30219,16,FLEN)
NAN_BOXED(30219,16,FLEN)
NAN_BOXED(30219,16,FLEN)
NAN_BOXED(30219,16,FLEN)
NAN_BOXED(29332,16,FLEN)
NAN_BOXED(29332,16,FLEN)
NAN_BOXED(29332,16,FLEN)
NAN_BOXED(29332,16,FLEN)
NAN_BOXED(29332,16,FLEN)
NAN_BOXED(29332,16,FLEN)
NAN_BOXED(29332,16,FLEN)
NAN_BOXED(29332,16,FLEN)
NAN_BOXED(29332,16,FLEN)
NAN_BOXED(29332,16,FLEN)
NAN_BOXED(30444,16,FLEN)
NAN_BOXED(30444,16,FLEN)
NAN_BOXED(30444,16,FLEN)
NAN_BOXED(30444,16,FLEN)
NAN_BOXED(30444,16,FLEN)
NAN_BOXED(30444,16,FLEN)
NAN_BOXED(30444,16,FLEN)
NAN_BOXED(30444,16,FLEN)
NAN_BOXED(30444,16,FLEN)
NAN_BOXED(30444,16,FLEN)
NAN_BOXED(28334,16,FLEN)
NAN_BOXED(28334,16,FLEN)
NAN_BOXED(28334,16,FLEN)
NAN_BOXED(28334,16,FLEN)
NAN_BOXED(28334,16,FLEN)
NAN_BOXED(28334,16,FLEN)
NAN_BOXED(28334,16,FLEN)
NAN_BOXED(28334,16,FLEN)
NAN_BOXED(28334,16,FLEN)
NAN_BOXED(28334,16,FLEN)
NAN_BOXED(29884,16,FLEN)
NAN_BOXED(29884,16,FLEN)
NAN_BOXED(29884,16,FLEN)
NAN_BOXED(29884,16,FLEN)
NAN_BOXED(29884,16,FLEN)
NAN_BOXED(29884,16,FLEN)
NAN_BOXED(29884,16,FLEN)
NAN_BOXED(29884,16,FLEN)
NAN_BOXED(29884,16,FLEN)
NAN_BOXED(29884,16,FLEN)
NAN_BOXED(30004,16,FLEN)
NAN_BOXED(30004,16,FLEN)
NAN_BOXED(30004,16,FLEN)
NAN_BOXED(30004,16,FLEN)
NAN_BOXED(30004,16,FLEN)
NAN_BOXED(30004,16,FLEN)
NAN_BOXED(30004,16,FLEN)
NAN_BOXED(30004,16,FLEN)
NAN_BOXED(30004,16,FLEN)
NAN_BOXED(30004,16,FLEN)
NAN_BOXED(31537,16,FLEN)
NAN_BOXED(31537,16,FLEN)
NAN_BOXED(31537,16,FLEN)
NAN_BOXED(31537,16,FLEN)
NAN_BOXED(31537,16,FLEN)
NAN_BOXED(31537,16,FLEN)
NAN_BOXED(31537,16,FLEN)
NAN_BOXED(31537,16,FLEN)
NAN_BOXED(31537,16,FLEN)
NAN_BOXED(31537,16,FLEN)
NAN_BOXED(29292,16,FLEN)
NAN_BOXED(29292,16,FLEN)
NAN_BOXED(29292,16,FLEN)
NAN_BOXED(29292,16,FLEN)
NAN_BOXED(29292,16,FLEN)
NAN_BOXED(29292,16,FLEN)
NAN_BOXED(29292,16,FLEN)
NAN_BOXED(29292,16,FLEN)
NAN_BOXED(29292,16,FLEN)
NAN_BOXED(29292,16,FLEN)
NAN_BOXED(31716,16,FLEN)
NAN_BOXED(31716,16,FLEN)
NAN_BOXED(31716,16,FLEN)
NAN_BOXED(31716,16,FLEN)
NAN_BOXED(31716,16,FLEN)
NAN_BOXED(31716,16,FLEN)
NAN_BOXED(31716,16,FLEN)
NAN_BOXED(31716,16,FLEN)
NAN_BOXED(31716,16,FLEN)
NAN_BOXED(31716,16,FLEN)
NAN_BOXED(30060,16,FLEN)
NAN_BOXED(30060,16,FLEN)
NAN_BOXED(30060,16,FLEN)
NAN_BOXED(30060,16,FLEN)
NAN_BOXED(30060,16,FLEN)
NAN_BOXED(30060,16,FLEN)
NAN_BOXED(30060,16,FLEN)
NAN_BOXED(30060,16,FLEN)
NAN_BOXED(30060,16,FLEN)
NAN_BOXED(30060,16,FLEN)
NAN_BOXED(31076,16,FLEN)
NAN_BOXED(31076,16,FLEN)
NAN_BOXED(31076,16,FLEN)
NAN_BOXED(31076,16,FLEN)
NAN_BOXED(31076,16,FLEN)
NAN_BOXED(31076,16,FLEN)
NAN_BOXED(31076,16,FLEN)
NAN_BOXED(31076,16,FLEN)
NAN_BOXED(31076,16,FLEN)
NAN_BOXED(31076,16,FLEN)
NAN_BOXED(31604,16,FLEN)
NAN_BOXED(31604,16,FLEN)
NAN_BOXED(31604,16,FLEN)
NAN_BOXED(31604,16,FLEN)
NAN_BOXED(31604,16,FLEN)
NAN_BOXED(31604,16,FLEN)
NAN_BOXED(31604,16,FLEN)
NAN_BOXED(31604,16,FLEN)
NAN_BOXED(31604,16,FLEN)
NAN_BOXED(31604,16,FLEN)
NAN_BOXED(30655,16,FLEN)
NAN_BOXED(30655,16,FLEN)
NAN_BOXED(30655,16,FLEN)
NAN_BOXED(30655,16,FLEN)
NAN_BOXED(30655,16,FLEN)
NAN_BOXED(30655,16,FLEN)
NAN_BOXED(30655,16,FLEN)
NAN_BOXED(30655,16,FLEN)
NAN_BOXED(30655,16,FLEN)
NAN_BOXED(30655,16,FLEN)
NAN_BOXED(29569,16,FLEN)
NAN_BOXED(29569,16,FLEN)
NAN_BOXED(29569,16,FLEN)
NAN_BOXED(29569,16,FLEN)
NAN_BOXED(29569,16,FLEN)
NAN_BOXED(29569,16,FLEN)
NAN_BOXED(29569,16,FLEN)
NAN_BOXED(29569,16,FLEN)
NAN_BOXED(29569,16,FLEN)
NAN_BOXED(29569,16,FLEN)
NAN_BOXED(28010,16,FLEN)
NAN_BOXED(28010,16,FLEN)
NAN_BOXED(28010,16,FLEN)
NAN_BOXED(28010,16,FLEN)
NAN_BOXED(28010,16,FLEN)
NAN_BOXED(28010,16,FLEN)
NAN_BOXED(28010,16,FLEN)
NAN_BOXED(28010,16,FLEN)
NAN_BOXED(28010,16,FLEN)
NAN_BOXED(28010,16,FLEN)
NAN_BOXED(31560,16,FLEN)
NAN_BOXED(31560,16,FLEN)
NAN_BOXED(31560,16,FLEN)
NAN_BOXED(31560,16,FLEN)
NAN_BOXED(31560,16,FLEN)
NAN_BOXED(31560,16,FLEN)
NAN_BOXED(31560,16,FLEN)
NAN_BOXED(31560,16,FLEN)
NAN_BOXED(31560,16,FLEN)
NAN_BOXED(31560,16,FLEN)
NAN_BOXED(31249,16,FLEN)
NAN_BOXED(31249,16,FLEN)
NAN_BOXED(31249,16,FLEN)
NAN_BOXED(31249,16,FLEN)
NAN_BOXED(31249,16,FLEN)
NAN_BOXED(31249,16,FLEN)
NAN_BOXED(31249,16,FLEN)
NAN_BOXED(31249,16,FLEN)
NAN_BOXED(31249,16,FLEN)
NAN_BOXED(31249,16,FLEN)
NAN_BOXED(31417,16,FLEN)
NAN_BOXED(31417,16,FLEN)
NAN_BOXED(31417,16,FLEN)
NAN_BOXED(31417,16,FLEN)
NAN_BOXED(31417,16,FLEN)
NAN_BOXED(31417,16,FLEN)
NAN_BOXED(31417,16,FLEN)
NAN_BOXED(31417,16,FLEN)
NAN_BOXED(31417,16,FLEN)
NAN_BOXED(31417,16,FLEN)
NAN_BOXED(30065,16,FLEN)
NAN_BOXED(30065,16,FLEN)
NAN_BOXED(30065,16,FLEN)
NAN_BOXED(30065,16,FLEN)
NAN_BOXED(30065,16,FLEN)
NAN_BOXED(30065,16,FLEN)
NAN_BOXED(30065,16,FLEN)
NAN_BOXED(30065,16,FLEN)
NAN_BOXED(30065,16,FLEN)
NAN_BOXED(30065,16,FLEN)
NAN_BOXED(31471,16,FLEN)
NAN_BOXED(31471,16,FLEN)
NAN_BOXED(31471,16,FLEN)
NAN_BOXED(31471,16,FLEN)
NAN_BOXED(31471,16,FLEN)
NAN_BOXED(31471,16,FLEN)
NAN_BOXED(31471,16,FLEN)
NAN_BOXED(31471,16,FLEN)
NAN_BOXED(31471,16,FLEN)
NAN_BOXED(31471,16,FLEN)
NAN_BOXED(31649,16,FLEN)
NAN_BOXED(31649,16,FLEN)
NAN_BOXED(31649,16,FLEN)
NAN_BOXED(31649,16,FLEN)
NAN_BOXED(31649,16,FLEN)
NAN_BOXED(31649,16,FLEN)
NAN_BOXED(31649,16,FLEN)
NAN_BOXED(31649,16,FLEN)
NAN_BOXED(31649,16,FLEN)
NAN_BOXED(31649,16,FLEN)
NAN_BOXED(28756,16,FLEN)
NAN_BOXED(28756,16,FLEN)
NAN_BOXED(28756,16,FLEN)
NAN_BOXED(28756,16,FLEN)
NAN_BOXED(28756,16,FLEN)
NAN_BOXED(28756,16,FLEN)
NAN_BOXED(28756,16,FLEN)
NAN_BOXED(28756,16,FLEN)
NAN_BOXED(28756,16,FLEN)
NAN_BOXED(28756,16,FLEN)
NAN_BOXED(28331,16,FLEN)
NAN_BOXED(28331,16,FLEN)
NAN_BOXED(28331,16,FLEN)
NAN_BOXED(28331,16,FLEN)
NAN_BOXED(28331,16,FLEN)
NAN_BOXED(28331,16,FLEN)
NAN_BOXED(28331,16,FLEN)
NAN_BOXED(28331,16,FLEN)
NAN_BOXED(28331,16,FLEN)
NAN_BOXED(28331,16,FLEN)
NAN_BOXED(27822,16,FLEN)
NAN_BOXED(27822,16,FLEN)
NAN_BOXED(27822,16,FLEN)
NAN_BOXED(27822,16,FLEN)
NAN_BOXED(27822,16,FLEN)
NAN_BOXED(27822,16,FLEN)
NAN_BOXED(27822,16,FLEN)
NAN_BOXED(27822,16,FLEN)
NAN_BOXED(27822,16,FLEN)
NAN_BOXED(27822,16,FLEN)
NAN_BOXED(31309,16,FLEN)
NAN_BOXED(31309,16,FLEN)
NAN_BOXED(31309,16,FLEN)
NAN_BOXED(31309,16,FLEN)
NAN_BOXED(31309,16,FLEN)
NAN_BOXED(31309,16,FLEN)
NAN_BOXED(31309,16,FLEN)
NAN_BOXED(31309,16,FLEN)
NAN_BOXED(31309,16,FLEN)
NAN_BOXED(31309,16,FLEN)
NAN_BOXED(30067,16,FLEN)
NAN_BOXED(30067,16,FLEN)
NAN_BOXED(30067,16,FLEN)
NAN_BOXED(30067,16,FLEN)
NAN_BOXED(30067,16,FLEN)
NAN_BOXED(30067,16,FLEN)
NAN_BOXED(30067,16,FLEN)
NAN_BOXED(30067,16,FLEN)
NAN_BOXED(30067,16,FLEN)
NAN_BOXED(30067,16,FLEN)
NAN_BOXED(31296,16,FLEN)
NAN_BOXED(31296,16,FLEN)
NAN_BOXED(31296,16,FLEN)
NAN_BOXED(31296,16,FLEN)
NAN_BOXED(31296,16,FLEN)
NAN_BOXED(31296,16,FLEN)
NAN_BOXED(31296,16,FLEN)
NAN_BOXED(31296,16,FLEN)
NAN_BOXED(31296,16,FLEN)
NAN_BOXED(31296,16,FLEN)
NAN_BOXED(30864,16,FLEN)
NAN_BOXED(30864,16,FLEN)
NAN_BOXED(30864,16,FLEN)
NAN_BOXED(30864,16,FLEN)
NAN_BOXED(30864,16,FLEN)
NAN_BOXED(30864,16,FLEN)
NAN_BOXED(30864,16,FLEN)
NAN_BOXED(30864,16,FLEN)
NAN_BOXED(30864,16,FLEN)
NAN_BOXED(30864,16,FLEN)
NAN_BOXED(27962,16,FLEN)
NAN_BOXED(27962,16,FLEN)
NAN_BOXED(27962,16,FLEN)
NAN_BOXED(27962,16,FLEN)
NAN_BOXED(27962,16,FLEN)
NAN_BOXED(27962,16,FLEN)
NAN_BOXED(27962,16,FLEN)
NAN_BOXED(27962,16,FLEN)
NAN_BOXED(27962,16,FLEN)
NAN_BOXED(27962,16,FLEN)
NAN_BOXED(31519,16,FLEN)
NAN_BOXED(31519,16,FLEN)
NAN_BOXED(31519,16,FLEN)
NAN_BOXED(31519,16,FLEN)
NAN_BOXED(31519,16,FLEN)
NAN_BOXED(31519,16,FLEN)
NAN_BOXED(31519,16,FLEN)
NAN_BOXED(31519,16,FLEN)
NAN_BOXED(31519,16,FLEN)
NAN_BOXED(31519,16,FLEN)
NAN_BOXED(31589,16,FLEN)
NAN_BOXED(31589,16,FLEN)
NAN_BOXED(31589,16,FLEN)
NAN_BOXED(31589,16,FLEN)
NAN_BOXED(31589,16,FLEN)
NAN_BOXED(31589,16,FLEN)
NAN_BOXED(31589,16,FLEN)
NAN_BOXED(31589,16,FLEN)
NAN_BOXED(31589,16,FLEN)
NAN_BOXED(31589,16,FLEN)
NAN_BOXED(29806,16,FLEN)
NAN_BOXED(29806,16,FLEN)
NAN_BOXED(29806,16,FLEN)
NAN_BOXED(29806,16,FLEN)
NAN_BOXED(29806,16,FLEN)
NAN_BOXED(29806,16,FLEN)
NAN_BOXED(29806,16,FLEN)
NAN_BOXED(29806,16,FLEN)
NAN_BOXED(29806,16,FLEN)
NAN_BOXED(29806,16,FLEN)
NAN_BOXED(31390,16,FLEN)
NAN_BOXED(31390,16,FLEN)
NAN_BOXED(31390,16,FLEN)
NAN_BOXED(31390,16,FLEN)
NAN_BOXED(31390,16,FLEN)
NAN_BOXED(31390,16,FLEN)
NAN_BOXED(31390,16,FLEN)
NAN_BOXED(31390,16,FLEN)
NAN_BOXED(31390,16,FLEN)
NAN_BOXED(31390,16,FLEN)
NAN_BOXED(31068,16,FLEN)
NAN_BOXED(31068,16,FLEN)
NAN_BOXED(31068,16,FLEN)
NAN_BOXED(31068,16,FLEN)
NAN_BOXED(31068,16,FLEN)
NAN_BOXED(31068,16,FLEN)
NAN_BOXED(31068,16,FLEN)
NAN_BOXED(31068,16,FLEN)
NAN_BOXED(31068,16,FLEN)
NAN_BOXED(31068,16,FLEN)
NAN_BOXED(28509,16,FLEN)
NAN_BOXED(28509,16,FLEN)
NAN_BOXED(28509,16,FLEN)
NAN_BOXED(28509,16,FLEN)
NAN_BOXED(28509,16,FLEN)
NAN_BOXED(28509,16,FLEN)
NAN_BOXED(28509,16,FLEN)
NAN_BOXED(28509,16,FLEN)
NAN_BOXED(28509,16,FLEN)
NAN_BOXED(28509,16,FLEN)
NAN_BOXED(26911,16,FLEN)
NAN_BOXED(26911,16,FLEN)
NAN_BOXED(26911,16,FLEN)
NAN_BOXED(26911,16,FLEN)
NAN_BOXED(26911,16,FLEN)
NAN_BOXED(26911,16,FLEN)
NAN_BOXED(26911,16,FLEN)
NAN_BOXED(26911,16,FLEN)
NAN_BOXED(26911,16,FLEN)
NAN_BOXED(26911,16,FLEN)
NAN_BOXED(31718,16,FLEN)
NAN_BOXED(31718,16,FLEN)
NAN_BOXED(31718,16,FLEN)
NAN_BOXED(31718,16,FLEN)
NAN_BOXED(31718,16,FLEN)
NAN_BOXED(31718,16,FLEN)
NAN_BOXED(31718,16,FLEN)
NAN_BOXED(31718,16,FLEN)
NAN_BOXED(31718,16,FLEN)
NAN_BOXED(31718,16,FLEN)
NAN_BOXED(28516,16,FLEN)
NAN_BOXED(28516,16,FLEN)
NAN_BOXED(28516,16,FLEN)
NAN_BOXED(28516,16,FLEN)
NAN_BOXED(28516,16,FLEN)
NAN_BOXED(28516,16,FLEN)
NAN_BOXED(28516,16,FLEN)
NAN_BOXED(28516,16,FLEN)
NAN_BOXED(28516,16,FLEN)
NAN_BOXED(28516,16,FLEN)
NAN_BOXED(29624,16,FLEN)
NAN_BOXED(29624,16,FLEN)
NAN_BOXED(29624,16,FLEN)
NAN_BOXED(29624,16,FLEN)
NAN_BOXED(29624,16,FLEN)
NAN_BOXED(29624,16,FLEN)
NAN_BOXED(29624,16,FLEN)
NAN_BOXED(29624,16,FLEN)
NAN_BOXED(29624,16,FLEN)
NAN_BOXED(29624,16,FLEN)
NAN_BOXED(28308,16,FLEN)
NAN_BOXED(28308,16,FLEN)
NAN_BOXED(28308,16,FLEN)
NAN_BOXED(28308,16,FLEN)
NAN_BOXED(28308,16,FLEN)
NAN_BOXED(28308,16,FLEN)
NAN_BOXED(28308,16,FLEN)
NAN_BOXED(28308,16,FLEN)
NAN_BOXED(28308,16,FLEN)
NAN_BOXED(28308,16,FLEN)
NAN_BOXED(30220,16,FLEN)
NAN_BOXED(30220,16,FLEN)
NAN_BOXED(30220,16,FLEN)
NAN_BOXED(30220,16,FLEN)
NAN_BOXED(30220,16,FLEN)
NAN_BOXED(30220,16,FLEN)
NAN_BOXED(30220,16,FLEN)
NAN_BOXED(30220,16,FLEN)
NAN_BOXED(30220,16,FLEN)
NAN_BOXED(30220,16,FLEN)
NAN_BOXED(31557,16,FLEN)
NAN_BOXED(31557,16,FLEN)
NAN_BOXED(31557,16,FLEN)
NAN_BOXED(31557,16,FLEN)
NAN_BOXED(31557,16,FLEN)
NAN_BOXED(31557,16,FLEN)
NAN_BOXED(31557,16,FLEN)
NAN_BOXED(31557,16,FLEN)
NAN_BOXED(31557,16,FLEN)
NAN_BOXED(31557,16,FLEN)
NAN_BOXED(29709,16,FLEN)
NAN_BOXED(29709,16,FLEN)
NAN_BOXED(29709,16,FLEN)
NAN_BOXED(29709,16,FLEN)
NAN_BOXED(29709,16,FLEN)
NAN_BOXED(29709,16,FLEN)
NAN_BOXED(29709,16,FLEN)
NAN_BOXED(29709,16,FLEN)
NAN_BOXED(29709,16,FLEN)
NAN_BOXED(29709,16,FLEN)
NAN_BOXED(28263,16,FLEN)
NAN_BOXED(28263,16,FLEN)
NAN_BOXED(28263,16,FLEN)
NAN_BOXED(28263,16,FLEN)
NAN_BOXED(28263,16,FLEN)
NAN_BOXED(28263,16,FLEN)
NAN_BOXED(28263,16,FLEN)
NAN_BOXED(28263,16,FLEN)
NAN_BOXED(28263,16,FLEN)
NAN_BOXED(28263,16,FLEN)
NAN_BOXED(26898,16,FLEN)
NAN_BOXED(26898,16,FLEN)
NAN_BOXED(26898,16,FLEN)
NAN_BOXED(26898,16,FLEN)
NAN_BOXED(26898,16,FLEN)
NAN_BOXED(26898,16,FLEN)
NAN_BOXED(26898,16,FLEN)
NAN_BOXED(26898,16,FLEN)
NAN_BOXED(26898,16,FLEN)
NAN_BOXED(26898,16,FLEN)
NAN_BOXED(31707,16,FLEN)
NAN_BOXED(31707,16,FLEN)
NAN_BOXED(31707,16,FLEN)
NAN_BOXED(31707,16,FLEN)
NAN_BOXED(31707,16,FLEN)
NAN_BOXED(31707,16,FLEN)
NAN_BOXED(31707,16,FLEN)
NAN_BOXED(31707,16,FLEN)
NAN_BOXED(31707,16,FLEN)
NAN_BOXED(31707,16,FLEN)
NAN_BOXED(30917,16,FLEN)
NAN_BOXED(30917,16,FLEN)
NAN_BOXED(30917,16,FLEN)
NAN_BOXED(30917,16,FLEN)
NAN_BOXED(30917,16,FLEN)
NAN_BOXED(30917,16,FLEN)
NAN_BOXED(30917,16,FLEN)
NAN_BOXED(30917,16,FLEN)
NAN_BOXED(30917,16,FLEN)
NAN_BOXED(30917,16,FLEN)
NAN_BOXED(29954,16,FLEN)
NAN_BOXED(29954,16,FLEN)
NAN_BOXED(29954,16,FLEN)
NAN_BOXED(29954,16,FLEN)
NAN_BOXED(29954,16,FLEN)
NAN_BOXED(29954,16,FLEN)
NAN_BOXED(29954,16,FLEN)
NAN_BOXED(29954,16,FLEN)
NAN_BOXED(29954,16,FLEN)
NAN_BOXED(29954,16,FLEN)
NAN_BOXED(31565,16,FLEN)
NAN_BOXED(31565,16,FLEN)
NAN_BOXED(31565,16,FLEN)
NAN_BOXED(31565,16,FLEN)
NAN_BOXED(31565,16,FLEN)
NAN_BOXED(31565,16,FLEN)
NAN_BOXED(31565,16,FLEN)
NAN_BOXED(31565,16,FLEN)
NAN_BOXED(31565,16,FLEN)
NAN_BOXED(31565,16,FLEN)
NAN_BOXED(31681,16,FLEN)
NAN_BOXED(31681,16,FLEN)
NAN_BOXED(31681,16,FLEN)
NAN_BOXED(31681,16,FLEN)
NAN_BOXED(31681,16,FLEN)
NAN_BOXED(31681,16,FLEN)
NAN_BOXED(31681,16,FLEN)
NAN_BOXED(31681,16,FLEN)
NAN_BOXED(31681,16,FLEN)
NAN_BOXED(31681,16,FLEN)
NAN_BOXED(29410,16,FLEN)
NAN_BOXED(29410,16,FLEN)
NAN_BOXED(29410,16,FLEN)
NAN_BOXED(29410,16,FLEN)
NAN_BOXED(29410,16,FLEN)
NAN_BOXED(29410,16,FLEN)
NAN_BOXED(29410,16,FLEN)
NAN_BOXED(29410,16,FLEN)
NAN_BOXED(29410,16,FLEN)
NAN_BOXED(29410,16,FLEN)
NAN_BOXED(31701,16,FLEN)
NAN_BOXED(31701,16,FLEN)
NAN_BOXED(31701,16,FLEN)
NAN_BOXED(31701,16,FLEN)
NAN_BOXED(31701,16,FLEN)
NAN_BOXED(31701,16,FLEN)
NAN_BOXED(31701,16,FLEN)
NAN_BOXED(31701,16,FLEN)
NAN_BOXED(31701,16,FLEN)
NAN_BOXED(31701,16,FLEN)
NAN_BOXED(31104,16,FLEN)
NAN_BOXED(31104,16,FLEN)
NAN_BOXED(31104,16,FLEN)
NAN_BOXED(31104,16,FLEN)
NAN_BOXED(31104,16,FLEN)
NAN_BOXED(31104,16,FLEN)
NAN_BOXED(31104,16,FLEN)
NAN_BOXED(31104,16,FLEN)
NAN_BOXED(31104,16,FLEN)
NAN_BOXED(31104,16,FLEN)
NAN_BOXED(29732,16,FLEN)
NAN_BOXED(29732,16,FLEN)
NAN_BOXED(29732,16,FLEN)
NAN_BOXED(29732,16,FLEN)
NAN_BOXED(29732,16,FLEN)
NAN_BOXED(29732,16,FLEN)
NAN_BOXED(29732,16,FLEN)
NAN_BOXED(29732,16,FLEN)
NAN_BOXED(29732,16,FLEN)
NAN_BOXED(29732,16,FLEN)
NAN_BOXED(29930,16,FLEN)
NAN_BOXED(29930,16,FLEN)
NAN_BOXED(29930,16,FLEN)
NAN_BOXED(29930,16,FLEN)
NAN_BOXED(29930,16,FLEN)
NAN_BOXED(29930,16,FLEN)
NAN_BOXED(29930,16,FLEN)
NAN_BOXED(29930,16,FLEN)
NAN_BOXED(29930,16,FLEN)
NAN_BOXED(29930,16,FLEN)
NAN_BOXED(27956,16,FLEN)
NAN_BOXED(27956,16,FLEN)
NAN_BOXED(27956,16,FLEN)
NAN_BOXED(27956,16,FLEN)
NAN_BOXED(27956,16,FLEN)
NAN_BOXED(27956,16,FLEN)
NAN_BOXED(27956,16,FLEN)
NAN_BOXED(27956,16,FLEN)
NAN_BOXED(27956,16,FLEN)
NAN_BOXED(27956,16,FLEN)
NAN_BOXED(31030,16,FLEN)
NAN_BOXED(31030,16,FLEN)
NAN_BOXED(31030,16,FLEN)
NAN_BOXED(31030,16,FLEN)
NAN_BOXED(31030,16,FLEN)
NAN_BOXED(31030,16,FLEN)
NAN_BOXED(31030,16,FLEN)
NAN_BOXED(31030,16,FLEN)
NAN_BOXED(31030,16,FLEN)
NAN_BOXED(31030,16,FLEN)
NAN_BOXED(31621,16,FLEN)
NAN_BOXED(31621,16,FLEN)
NAN_BOXED(31621,16,FLEN)
NAN_BOXED(31621,16,FLEN)
NAN_BOXED(31621,16,FLEN)
NAN_BOXED(31621,16,FLEN)
NAN_BOXED(31621,16,FLEN)
NAN_BOXED(31621,16,FLEN)
NAN_BOXED(31621,16,FLEN)
NAN_BOXED(31621,16,FLEN)
NAN_BOXED(29928,16,FLEN)
NAN_BOXED(29928,16,FLEN)
NAN_BOXED(29928,16,FLEN)
NAN_BOXED(29928,16,FLEN)
NAN_BOXED(29928,16,FLEN)
NAN_BOXED(29928,16,FLEN)
NAN_BOXED(29928,16,FLEN)
NAN_BOXED(29928,16,FLEN)
NAN_BOXED(29928,16,FLEN)
NAN_BOXED(29928,16,FLEN)
NAN_BOXED(29968,16,FLEN)
NAN_BOXED(29968,16,FLEN)
NAN_BOXED(29968,16,FLEN)
NAN_BOXED(29968,16,FLEN)
NAN_BOXED(29968,16,FLEN)
NAN_BOXED(29968,16,FLEN)
NAN_BOXED(29968,16,FLEN)
NAN_BOXED(29968,16,FLEN)
NAN_BOXED(29968,16,FLEN)
NAN_BOXED(29968,16,FLEN)
NAN_BOXED(31524,16,FLEN)
NAN_BOXED(31524,16,FLEN)
NAN_BOXED(31524,16,FLEN)
NAN_BOXED(31524,16,FLEN)
NAN_BOXED(31524,16,FLEN)
NAN_BOXED(31524,16,FLEN)
NAN_BOXED(31524,16,FLEN)
NAN_BOXED(31524,16,FLEN)
NAN_BOXED(31524,16,FLEN)
NAN_BOXED(31524,16,FLEN)
NAN_BOXED(30040,16,FLEN)
NAN_BOXED(30040,16,FLEN)
NAN_BOXED(30040,16,FLEN)
NAN_BOXED(30040,16,FLEN)
NAN_BOXED(30040,16,FLEN)
NAN_BOXED(30040,16,FLEN)
NAN_BOXED(30040,16,FLEN)
NAN_BOXED(30040,16,FLEN)
NAN_BOXED(30040,16,FLEN)
NAN_BOXED(30040,16,FLEN)
NAN_BOXED(30881,16,FLEN)
NAN_BOXED(30881,16,FLEN)
NAN_BOXED(30881,16,FLEN)
NAN_BOXED(30881,16,FLEN)
NAN_BOXED(30881,16,FLEN)
NAN_BOXED(30881,16,FLEN)
NAN_BOXED(30881,16,FLEN)
NAN_BOXED(30881,16,FLEN)
NAN_BOXED(30881,16,FLEN)
NAN_BOXED(30881,16,FLEN)
NAN_BOXED(29654,16,FLEN)
NAN_BOXED(29654,16,FLEN)
NAN_BOXED(29654,16,FLEN)
NAN_BOXED(29654,16,FLEN)
NAN_BOXED(29654,16,FLEN)
NAN_BOXED(29654,16,FLEN)
NAN_BOXED(29654,16,FLEN)
NAN_BOXED(29654,16,FLEN)
NAN_BOXED(29654,16,FLEN)
NAN_BOXED(29654,16,FLEN)
NAN_BOXED(29643,16,FLEN)
NAN_BOXED(29643,16,FLEN)
NAN_BOXED(29643,16,FLEN)
NAN_BOXED(29643,16,FLEN)
NAN_BOXED(29643,16,FLEN)
NAN_BOXED(29643,16,FLEN)
NAN_BOXED(29643,16,FLEN)
NAN_BOXED(29643,16,FLEN)
NAN_BOXED(29643,16,FLEN)
NAN_BOXED(29643,16,FLEN)
NAN_BOXED(30824,16,FLEN)
NAN_BOXED(30824,16,FLEN)
NAN_BOXED(30824,16,FLEN)
NAN_BOXED(30824,16,FLEN)
NAN_BOXED(30824,16,FLEN)
NAN_BOXED(30824,16,FLEN)
NAN_BOXED(30824,16,FLEN)
NAN_BOXED(30824,16,FLEN)
NAN_BOXED(30824,16,FLEN)
NAN_BOXED(30824,16,FLEN)
NAN_BOXED(27854,16,FLEN)
NAN_BOXED(27854,16,FLEN)
NAN_BOXED(27854,16,FLEN)
NAN_BOXED(27854,16,FLEN)
NAN_BOXED(27854,16,FLEN)
NAN_BOXED(27854,16,FLEN)
NAN_BOXED(27854,16,FLEN)
NAN_BOXED(27854,16,FLEN)
NAN_BOXED(27854,16,FLEN)
NAN_BOXED(27854,16,FLEN)
NAN_BOXED(29862,16,FLEN)
NAN_BOXED(29862,16,FLEN)
NAN_BOXED(29862,16,FLEN)
NAN_BOXED(29862,16,FLEN)
NAN_BOXED(29862,16,FLEN)
NAN_BOXED(29862,16,FLEN)
NAN_BOXED(29862,16,FLEN)
NAN_BOXED(29862,16,FLEN)
NAN_BOXED(29862,16,FLEN)
NAN_BOXED(29862,16,FLEN)
NAN_BOXED(30691,16,FLEN)
NAN_BOXED(30691,16,FLEN)
NAN_BOXED(30691,16,FLEN)
NAN_BOXED(30691,16,FLEN)
NAN_BOXED(30691,16,FLEN)
NAN_BOXED(30691,16,FLEN)
NAN_BOXED(30691,16,FLEN)
NAN_BOXED(30691,16,FLEN)
NAN_BOXED(30691,16,FLEN)
NAN_BOXED(30691,16,FLEN)
NAN_BOXED(28910,16,FLEN)
NAN_BOXED(28910,16,FLEN)
NAN_BOXED(28910,16,FLEN)
NAN_BOXED(28910,16,FLEN)
NAN_BOXED(28910,16,FLEN)
NAN_BOXED(28910,16,FLEN)
NAN_BOXED(28910,16,FLEN)
NAN_BOXED(28910,16,FLEN)
NAN_BOXED(28910,16,FLEN)
NAN_BOXED(28910,16,FLEN)
NAN_BOXED(31323,16,FLEN)
NAN_BOXED(31323,16,FLEN)
NAN_BOXED(31323,16,FLEN)
NAN_BOXED(31323,16,FLEN)
NAN_BOXED(31323,16,FLEN)
NAN_BOXED(31323,16,FLEN)
NAN_BOXED(31323,16,FLEN)
NAN_BOXED(31323,16,FLEN)
NAN_BOXED(31323,16,FLEN)
NAN_BOXED(31323,16,FLEN)
NAN_BOXED(31639,16,FLEN)
NAN_BOXED(31637,16,FLEN)
NAN_BOXED(31639,16,FLEN)
NAN_BOXED(31637,16,FLEN)
NAN_BOXED(31639,16,FLEN)
NAN_BOXED(31637,16,FLEN)
NAN_BOXED(31639,16,FLEN)
NAN_BOXED(31637,16,FLEN)
NAN_BOXED(31639,16,FLEN)
NAN_BOXED(31637,16,FLEN)
NAN_BOXED(31284,16,FLEN)
NAN_BOXED(31282,16,FLEN)
NAN_BOXED(31284,16,FLEN)
NAN_BOXED(31282,16,FLEN)
NAN_BOXED(31284,16,FLEN)
NAN_BOXED(31282,16,FLEN)
NAN_BOXED(31284,16,FLEN)
NAN_BOXED(31282,16,FLEN)
NAN_BOXED(31284,16,FLEN)
NAN_BOXED(31282,16,FLEN)
NAN_BOXED(31377,16,FLEN)
NAN_BOXED(31375,16,FLEN)
NAN_BOXED(31377,16,FLEN)
NAN_BOXED(31375,16,FLEN)
NAN_BOXED(31377,16,FLEN)
NAN_BOXED(31375,16,FLEN)
NAN_BOXED(31377,16,FLEN)
NAN_BOXED(31375,16,FLEN)
NAN_BOXED(31377,16,FLEN)
NAN_BOXED(31375,16,FLEN)
NAN_BOXED(28374,16,FLEN)
NAN_BOXED(28358,16,FLEN)
NAN_BOXED(28374,16,FLEN)
NAN_BOXED(28358,16,FLEN)
NAN_BOXED(28374,16,FLEN)
NAN_BOXED(28358,16,FLEN)
NAN_BOXED(28374,16,FLEN)
NAN_BOXED(28358,16,FLEN)
NAN_BOXED(28374,16,FLEN)
NAN_BOXED(28358,16,FLEN)
NAN_BOXED(31577,16,FLEN)
NAN_BOXED(31575,16,FLEN)
NAN_BOXED(31577,16,FLEN)
NAN_BOXED(31575,16,FLEN)
NAN_BOXED(31577,16,FLEN)
NAN_BOXED(31575,16,FLEN)
NAN_BOXED(31577,16,FLEN)
NAN_BOXED(31575,16,FLEN)
NAN_BOXED(31577,16,FLEN)
NAN_BOXED(31575,16,FLEN)
NAN_BOXED(31525,16,FLEN)
NAN_BOXED(31523,16,FLEN)
NAN_BOXED(31525,16,FLEN)
NAN_BOXED(31523,16,FLEN)
NAN_BOXED(31525,16,FLEN)
NAN_BOXED(31523,16,FLEN)
NAN_BOXED(31525,16,FLEN)
NAN_BOXED(31523,16,FLEN)
NAN_BOXED(31525,16,FLEN)
NAN_BOXED(31523,16,FLEN)
NAN_BOXED(31559,16,FLEN)
NAN_BOXED(31557,16,FLEN)
NAN_BOXED(31559,16,FLEN)
NAN_BOXED(31557,16,FLEN)
NAN_BOXED(31559,16,FLEN)
NAN_BOXED(31557,16,FLEN)
NAN_BOXED(31559,16,FLEN)
NAN_BOXED(31557,16,FLEN)
NAN_BOXED(31559,16,FLEN)
NAN_BOXED(31557,16,FLEN)
NAN_BOXED(29966,16,FLEN)
NAN_BOXED(29970,16,FLEN)
NAN_BOXED(29966,16,FLEN)
NAN_BOXED(29970,16,FLEN)
NAN_BOXED(29966,16,FLEN)
NAN_BOXED(29970,16,FLEN)
NAN_BOXED(29966,16,FLEN)
NAN_BOXED(29970,16,FLEN)
NAN_BOXED(29966,16,FLEN)
NAN_BOXED(29970,16,FLEN)
NAN_BOXED(31341,16,FLEN)
NAN_BOXED(31343,16,FLEN)
NAN_BOXED(31341,16,FLEN)
NAN_BOXED(31343,16,FLEN)
NAN_BOXED(31341,16,FLEN)
NAN_BOXED(31343,16,FLEN)
NAN_BOXED(31341,16,FLEN)
NAN_BOXED(31343,16,FLEN)
NAN_BOXED(31341,16,FLEN)
NAN_BOXED(31343,16,FLEN)
NAN_BOXED(31416,16,FLEN)
NAN_BOXED(31418,16,FLEN)
NAN_BOXED(31416,16,FLEN)
NAN_BOXED(31418,16,FLEN)
NAN_BOXED(31416,16,FLEN)
NAN_BOXED(31418,16,FLEN)
NAN_BOXED(31416,16,FLEN)
NAN_BOXED(31418,16,FLEN)
NAN_BOXED(31416,16,FLEN)
NAN_BOXED(31418,16,FLEN)
NAN_BOXED(31107,16,FLEN)
NAN_BOXED(31109,16,FLEN)
NAN_BOXED(31107,16,FLEN)
NAN_BOXED(31109,16,FLEN)
NAN_BOXED(31107,16,FLEN)
NAN_BOXED(31109,16,FLEN)
NAN_BOXED(31107,16,FLEN)
NAN_BOXED(31109,16,FLEN)
NAN_BOXED(31107,16,FLEN)
NAN_BOXED(31109,16,FLEN)
NAN_BOXED(30443,16,FLEN)
NAN_BOXED(30447,16,FLEN)
NAN_BOXED(30443,16,FLEN)
NAN_BOXED(30447,16,FLEN)
NAN_BOXED(30443,16,FLEN)
NAN_BOXED(30447,16,FLEN)
NAN_BOXED(30443,16,FLEN)
NAN_BOXED(30447,16,FLEN)
NAN_BOXED(30443,16,FLEN)
NAN_BOXED(30447,16,FLEN)
NAN_BOXED(31159,16,FLEN)
NAN_BOXED(31161,16,FLEN)
NAN_BOXED(31159,16,FLEN)
NAN_BOXED(31161,16,FLEN)
NAN_BOXED(31159,16,FLEN)
NAN_BOXED(31161,16,FLEN)
NAN_BOXED(31159,16,FLEN)
NAN_BOXED(31161,16,FLEN)
NAN_BOXED(31159,16,FLEN)
NAN_BOXED(31161,16,FLEN)
NAN_BOXED(29706,16,FLEN)
NAN_BOXED(29710,16,FLEN)
NAN_BOXED(29706,16,FLEN)
NAN_BOXED(29710,16,FLEN)
NAN_BOXED(29706,16,FLEN)
NAN_BOXED(29710,16,FLEN)
NAN_BOXED(29706,16,FLEN)
NAN_BOXED(29710,16,FLEN)
NAN_BOXED(29706,16,FLEN)
NAN_BOXED(29710,16,FLEN)
NAN_BOXED(31668,16,FLEN)
NAN_BOXED(31670,16,FLEN)
NAN_BOXED(31668,16,FLEN)
NAN_BOXED(31670,16,FLEN)
NAN_BOXED(31668,16,FLEN)
NAN_BOXED(31670,16,FLEN)
NAN_BOXED(31668,16,FLEN)
NAN_BOXED(31670,16,FLEN)
NAN_BOXED(31668,16,FLEN)
NAN_BOXED(31670,16,FLEN)
NAN_BOXED(30820,16,FLEN)
NAN_BOXED(30822,16,FLEN)
NAN_BOXED(30820,16,FLEN)
NAN_BOXED(30822,16,FLEN)
NAN_BOXED(30820,16,FLEN)
NAN_BOXED(30822,16,FLEN)
NAN_BOXED(30820,16,FLEN)
NAN_BOXED(30822,16,FLEN)
NAN_BOXED(30820,16,FLEN)
NAN_BOXED(30822,16,FLEN)
NAN_BOXED(31438,16,FLEN)
NAN_BOXED(31440,16,FLEN)
NAN_BOXED(31438,16,FLEN)
NAN_BOXED(31440,16,FLEN)
NAN_BOXED(31438,16,FLEN)
NAN_BOXED(31440,16,FLEN)
NAN_BOXED(31438,16,FLEN)
NAN_BOXED(31440,16,FLEN)
NAN_BOXED(31438,16,FLEN)
NAN_BOXED(31440,16,FLEN)
NAN_BOXED(30292,16,FLEN)
NAN_BOXED(30296,16,FLEN)
NAN_BOXED(30292,16,FLEN)
NAN_BOXED(30296,16,FLEN)
NAN_BOXED(30292,16,FLEN)
NAN_BOXED(30296,16,FLEN)
NAN_BOXED(30292,16,FLEN)
NAN_BOXED(30296,16,FLEN)
NAN_BOXED(30292,16,FLEN)
NAN_BOXED(30296,16,FLEN)
NAN_BOXED(29728,16,FLEN)
NAN_BOXED(29732,16,FLEN)
NAN_BOXED(29728,16,FLEN)
NAN_BOXED(29732,16,FLEN)
NAN_BOXED(29728,16,FLEN)
NAN_BOXED(29732,16,FLEN)
NAN_BOXED(29728,16,FLEN)
NAN_BOXED(29732,16,FLEN)
NAN_BOXED(29728,16,FLEN)
NAN_BOXED(29732,16,FLEN)
NAN_BOXED(31019,16,FLEN)
NAN_BOXED(31021,16,FLEN)
NAN_BOXED(31019,16,FLEN)
NAN_BOXED(31021,16,FLEN)
NAN_BOXED(31019,16,FLEN)
NAN_BOXED(31021,16,FLEN)
NAN_BOXED(31019,16,FLEN)
NAN_BOXED(31021,16,FLEN)
NAN_BOXED(31019,16,FLEN)
NAN_BOXED(31021,16,FLEN)
NAN_BOXED(30864,16,FLEN)
NAN_BOXED(30866,16,FLEN)
NAN_BOXED(30864,16,FLEN)
NAN_BOXED(30866,16,FLEN)
NAN_BOXED(30864,16,FLEN)
NAN_BOXED(30866,16,FLEN)
NAN_BOXED(30864,16,FLEN)
NAN_BOXED(30866,16,FLEN)
NAN_BOXED(30864,16,FLEN)
NAN_BOXED(30866,16,FLEN)
NAN_BOXED(30125,16,FLEN)
NAN_BOXED(30121,16,FLEN)
NAN_BOXED(30125,16,FLEN)
NAN_BOXED(30121,16,FLEN)
NAN_BOXED(30125,16,FLEN)
NAN_BOXED(30121,16,FLEN)
NAN_BOXED(30125,16,FLEN)
NAN_BOXED(30121,16,FLEN)
NAN_BOXED(30125,16,FLEN)
NAN_BOXED(30121,16,FLEN)
NAN_BOXED(28672,16,FLEN)
NAN_BOXED(28657,16,FLEN)
NAN_BOXED(28672,16,FLEN)
NAN_BOXED(28657,16,FLEN)
NAN_BOXED(28672,16,FLEN)
NAN_BOXED(28657,16,FLEN)
NAN_BOXED(28672,16,FLEN)
NAN_BOXED(28657,16,FLEN)
NAN_BOXED(28672,16,FLEN)
NAN_BOXED(28657,16,FLEN)
NAN_BOXED(31392,16,FLEN)
NAN_BOXED(31390,16,FLEN)
NAN_BOXED(31392,16,FLEN)
NAN_BOXED(31390,16,FLEN)
NAN_BOXED(31392,16,FLEN)
NAN_BOXED(31390,16,FLEN)
NAN_BOXED(31392,16,FLEN)
NAN_BOXED(31390,16,FLEN)
NAN_BOXED(31392,16,FLEN)
NAN_BOXED(31390,16,FLEN)
NAN_BOXED(30314,16,FLEN)
NAN_BOXED(30310,16,FLEN)
NAN_BOXED(30314,16,FLEN)
NAN_BOXED(30310,16,FLEN)
NAN_BOXED(30314,16,FLEN)
NAN_BOXED(30310,16,FLEN)
NAN_BOXED(30314,16,FLEN)
NAN_BOXED(30310,16,FLEN)
NAN_BOXED(30314,16,FLEN)
NAN_BOXED(30310,16,FLEN)
NAN_BOXED(29560,16,FLEN)
NAN_BOXED(29552,16,FLEN)
NAN_BOXED(29560,16,FLEN)
NAN_BOXED(29552,16,FLEN)
NAN_BOXED(29560,16,FLEN)
NAN_BOXED(29552,16,FLEN)
NAN_BOXED(29560,16,FLEN)
NAN_BOXED(29552,16,FLEN)
NAN_BOXED(29560,16,FLEN)
NAN_BOXED(29552,16,FLEN)
NAN_BOXED(30778,16,FLEN)
NAN_BOXED(30776,16,FLEN)
NAN_BOXED(30778,16,FLEN)
NAN_BOXED(30776,16,FLEN)
NAN_BOXED(30778,16,FLEN)
NAN_BOXED(30776,16,FLEN)
NAN_BOXED(30778,16,FLEN)
NAN_BOXED(30776,16,FLEN)
NAN_BOXED(30778,16,FLEN)
NAN_BOXED(30776,16,FLEN)
NAN_BOXED(31024,16,FLEN)
NAN_BOXED(31022,16,FLEN)
NAN_BOXED(31024,16,FLEN)
NAN_BOXED(31022,16,FLEN)
NAN_BOXED(31024,16,FLEN)
NAN_BOXED(31022,16,FLEN)
NAN_BOXED(31024,16,FLEN)
NAN_BOXED(31022,16,FLEN)
NAN_BOXED(31024,16,FLEN)
NAN_BOXED(31022,16,FLEN)
NAN_BOXED(31101,16,FLEN)
NAN_BOXED(31101,16,FLEN)
NAN_BOXED(31101,16,FLEN)
NAN_BOXED(31101,16,FLEN)
NAN_BOXED(31101,16,FLEN)
NAN_BOXED(31101,16,FLEN)
NAN_BOXED(31101,16,FLEN)
NAN_BOXED(31101,16,FLEN)
NAN_BOXED(31101,16,FLEN)
NAN_BOXED(31101,16,FLEN)
NAN_BOXED(29599,16,FLEN)
NAN_BOXED(29599,16,FLEN)
NAN_BOXED(29599,16,FLEN)
NAN_BOXED(29599,16,FLEN)
NAN_BOXED(29599,16,FLEN)
NAN_BOXED(29599,16,FLEN)
NAN_BOXED(29599,16,FLEN)
NAN_BOXED(29599,16,FLEN)
NAN_BOXED(29599,16,FLEN)
NAN_BOXED(29599,16,FLEN)
NAN_BOXED(30632,16,FLEN)
NAN_BOXED(30632,16,FLEN)
NAN_BOXED(30632,16,FLEN)
NAN_BOXED(30632,16,FLEN)
NAN_BOXED(30632,16,FLEN)
NAN_BOXED(30632,16,FLEN)
NAN_BOXED(30632,16,FLEN)
NAN_BOXED(30632,16,FLEN)
NAN_BOXED(30632,16,FLEN)
NAN_BOXED(30632,16,FLEN)
NAN_BOXED(30359,16,FLEN)
NAN_BOXED(30359,16,FLEN)
NAN_BOXED(30359,16,FLEN)
NAN_BOXED(30359,16,FLEN)
NAN_BOXED(30359,16,FLEN)
NAN_BOXED(30359,16,FLEN)
NAN_BOXED(30359,16,FLEN)
NAN_BOXED(30359,16,FLEN)
NAN_BOXED(30359,16,FLEN)
NAN_BOXED(30359,16,FLEN)
NAN_BOXED(31552,16,FLEN)
NAN_BOXED(31552,16,FLEN)
NAN_BOXED(31552,16,FLEN)
NAN_BOXED(31552,16,FLEN)
NAN_BOXED(31552,16,FLEN)
NAN_BOXED(31552,16,FLEN)
NAN_BOXED(31552,16,FLEN)
NAN_BOXED(31552,16,FLEN)
NAN_BOXED(31552,16,FLEN)
NAN_BOXED(31552,16,FLEN)
NAN_BOXED(29798,16,FLEN)
NAN_BOXED(29798,16,FLEN)
NAN_BOXED(29798,16,FLEN)
NAN_BOXED(29798,16,FLEN)
NAN_BOXED(29798,16,FLEN)
NAN_BOXED(29798,16,FLEN)
NAN_BOXED(29798,16,FLEN)
NAN_BOXED(29798,16,FLEN)
NAN_BOXED(29798,16,FLEN)
NAN_BOXED(29798,16,FLEN)
NAN_BOXED(27179,16,FLEN)
NAN_BOXED(27179,16,FLEN)
NAN_BOXED(27179,16,FLEN)
NAN_BOXED(27179,16,FLEN)
NAN_BOXED(27179,16,FLEN)
NAN_BOXED(27179,16,FLEN)
NAN_BOXED(27179,16,FLEN)
NAN_BOXED(27179,16,FLEN)
NAN_BOXED(27179,16,FLEN)
NAN_BOXED(27179,16,FLEN)
NAN_BOXED(30743,16,FLEN)
NAN_BOXED(30743,16,FLEN)
NAN_BOXED(30743,16,FLEN)
NAN_BOXED(30743,16,FLEN)
NAN_BOXED(30743,16,FLEN)
NAN_BOXED(30743,16,FLEN)
NAN_BOXED(30743,16,FLEN)
NAN_BOXED(30743,16,FLEN)
NAN_BOXED(30743,16,FLEN)
NAN_BOXED(30743,16,FLEN)
NAN_BOXED(28953,16,FLEN)
NAN_BOXED(28953,16,FLEN)
NAN_BOXED(28953,16,FLEN)
NAN_BOXED(28953,16,FLEN)
NAN_BOXED(28953,16,FLEN)
NAN_BOXED(28953,16,FLEN)
NAN_BOXED(28953,16,FLEN)
NAN_BOXED(28953,16,FLEN)
NAN_BOXED(28953,16,FLEN)
NAN_BOXED(28953,16,FLEN)
NAN_BOXED(31503,16,FLEN)
NAN_BOXED(31503,16,FLEN)
NAN_BOXED(31503,16,FLEN)
NAN_BOXED(31503,16,FLEN)
NAN_BOXED(31503,16,FLEN)
NAN_BOXED(31503,16,FLEN)
NAN_BOXED(31503,16,FLEN)
NAN_BOXED(31503,16,FLEN)
NAN_BOXED(31503,16,FLEN)
NAN_BOXED(31503,16,FLEN)
NAN_BOXED(31113,16,FLEN)
NAN_BOXED(31113,16,FLEN)
NAN_BOXED(31113,16,FLEN)
NAN_BOXED(31113,16,FLEN)
NAN_BOXED(31113,16,FLEN)
NAN_BOXED(31113,16,FLEN)
NAN_BOXED(31113,16,FLEN)
NAN_BOXED(31113,16,FLEN)
NAN_BOXED(31113,16,FLEN)
NAN_BOXED(31113,16,FLEN)
NAN_BOXED(30193,16,FLEN)
NAN_BOXED(30193,16,FLEN)
NAN_BOXED(30193,16,FLEN)
NAN_BOXED(30193,16,FLEN)
NAN_BOXED(30193,16,FLEN)
NAN_BOXED(30193,16,FLEN)
NAN_BOXED(30193,16,FLEN)
NAN_BOXED(30193,16,FLEN)
NAN_BOXED(30193,16,FLEN)
NAN_BOXED(30193,16,FLEN)
NAN_BOXED(31203,16,FLEN)
NAN_BOXED(31203,16,FLEN)
NAN_BOXED(31203,16,FLEN)
NAN_BOXED(31203,16,FLEN)
NAN_BOXED(31203,16,FLEN)
NAN_BOXED(31203,16,FLEN)
NAN_BOXED(31203,16,FLEN)
NAN_BOXED(31203,16,FLEN)
NAN_BOXED(31203,16,FLEN)
NAN_BOXED(31203,16,FLEN)
NAN_BOXED(31448,16,FLEN)
NAN_BOXED(31448,16,FLEN)
NAN_BOXED(31448,16,FLEN)
NAN_BOXED(31448,16,FLEN)
NAN_BOXED(31448,16,FLEN)
NAN_BOXED(31448,16,FLEN)
NAN_BOXED(31448,16,FLEN)
NAN_BOXED(31448,16,FLEN)
NAN_BOXED(31448,16,FLEN)
NAN_BOXED(31448,16,FLEN)
NAN_BOXED(31661,16,FLEN)
NAN_BOXED(31661,16,FLEN)
NAN_BOXED(31661,16,FLEN)
NAN_BOXED(31661,16,FLEN)
NAN_BOXED(31661,16,FLEN)
NAN_BOXED(31661,16,FLEN)
NAN_BOXED(31661,16,FLEN)
NAN_BOXED(31661,16,FLEN)
NAN_BOXED(31661,16,FLEN)
NAN_BOXED(31661,16,FLEN)
NAN_BOXED(29091,16,FLEN)
NAN_BOXED(29091,16,FLEN)
NAN_BOXED(29091,16,FLEN)
NAN_BOXED(29091,16,FLEN)
NAN_BOXED(29091,16,FLEN)
NAN_BOXED(29091,16,FLEN)
NAN_BOXED(29091,16,FLEN)
NAN_BOXED(29091,16,FLEN)
NAN_BOXED(29091,16,FLEN)
NAN_BOXED(29091,16,FLEN)
NAN_BOXED(29429,16,FLEN)
NAN_BOXED(29429,16,FLEN)
NAN_BOXED(29429,16,FLEN)
NAN_BOXED(29429,16,FLEN)
NAN_BOXED(29429,16,FLEN)
NAN_BOXED(29429,16,FLEN)
NAN_BOXED(29429,16,FLEN)
NAN_BOXED(29429,16,FLEN)
NAN_BOXED(29429,16,FLEN)
NAN_BOXED(29429,16,FLEN)
NAN_BOXED(31247,16,FLEN)
NAN_BOXED(31247,16,FLEN)
NAN_BOXED(31247,16,FLEN)
NAN_BOXED(31247,16,FLEN)
NAN_BOXED(31247,16,FLEN)
NAN_BOXED(31247,16,FLEN)
NAN_BOXED(31247,16,FLEN)
NAN_BOXED(31247,16,FLEN)
NAN_BOXED(31247,16,FLEN)
NAN_BOXED(31247,16,FLEN)
NAN_BOXED(31091,16,FLEN)
NAN_BOXED(31091,16,FLEN)
NAN_BOXED(31091,16,FLEN)
NAN_BOXED(31091,16,FLEN)
NAN_BOXED(31091,16,FLEN)
NAN_BOXED(31091,16,FLEN)
NAN_BOXED(31091,16,FLEN)
NAN_BOXED(31091,16,FLEN)
NAN_BOXED(31091,16,FLEN)
NAN_BOXED(31091,16,FLEN)
NAN_BOXED(30096,16,FLEN)
NAN_BOXED(30096,16,FLEN)
NAN_BOXED(30096,16,FLEN)
NAN_BOXED(30096,16,FLEN)
NAN_BOXED(30096,16,FLEN)
NAN_BOXED(30096,16,FLEN)
NAN_BOXED(30096,16,FLEN)
NAN_BOXED(30096,16,FLEN)
NAN_BOXED(30096,16,FLEN)
NAN_BOXED(30096,16,FLEN)
NAN_BOXED(28997,16,FLEN)
NAN_BOXED(28997,16,FLEN)
NAN_BOXED(28997,16,FLEN)
NAN_BOXED(28997,16,FLEN)
NAN_BOXED(28997,16,FLEN)
NAN_BOXED(28997,16,FLEN)
NAN_BOXED(28997,16,FLEN)
NAN_BOXED(28997,16,FLEN)
NAN_BOXED(28997,16,FLEN)
NAN_BOXED(28997,16,FLEN)
NAN_BOXED(26933,16,FLEN)
NAN_BOXED(26933,16,FLEN)
NAN_BOXED(26933,16,FLEN)
NAN_BOXED(26933,16,FLEN)
NAN_BOXED(26933,16,FLEN)
NAN_BOXED(26933,16,FLEN)
NAN_BOXED(26933,16,FLEN)
NAN_BOXED(26933,16,FLEN)
NAN_BOXED(26933,16,FLEN)
NAN_BOXED(26933,16,FLEN)
NAN_BOXED(31349,16,FLEN)
NAN_BOXED(31349,16,FLEN)
NAN_BOXED(31349,16,FLEN)
NAN_BOXED(31349,16,FLEN)
NAN_BOXED(31349,16,FLEN)
NAN_BOXED(31349,16,FLEN)
NAN_BOXED(31349,16,FLEN)
NAN_BOXED(31349,16,FLEN)
NAN_BOXED(31349,16,FLEN)
NAN_BOXED(31349,16,FLEN)
NAN_BOXED(29767,16,FLEN)
NAN_BOXED(29767,16,FLEN)
NAN_BOXED(29767,16,FLEN)
NAN_BOXED(29767,16,FLEN)
NAN_BOXED(29767,16,FLEN)
NAN_BOXED(29767,16,FLEN)
NAN_BOXED(29767,16,FLEN)
NAN_BOXED(29767,16,FLEN)
NAN_BOXED(29767,16,FLEN)
NAN_BOXED(29767,16,FLEN)
NAN_BOXED(31659,16,FLEN)
NAN_BOXED(31659,16,FLEN)
NAN_BOXED(31659,16,FLEN)
NAN_BOXED(31659,16,FLEN)
NAN_BOXED(31659,16,FLEN)
NAN_BOXED(31659,16,FLEN)
NAN_BOXED(31659,16,FLEN)
NAN_BOXED(31659,16,FLEN)
NAN_BOXED(31659,16,FLEN)
NAN_BOXED(31659,16,FLEN)
NAN_BOXED(31283,16,FLEN)
NAN_BOXED(31283,16,FLEN)
NAN_BOXED(31283,16,FLEN)
NAN_BOXED(31283,16,FLEN)
NAN_BOXED(31283,16,FLEN)
NAN_BOXED(31283,16,FLEN)
NAN_BOXED(31283,16,FLEN)
NAN_BOXED(31283,16,FLEN)
NAN_BOXED(31283,16,FLEN)
NAN_BOXED(31283,16,FLEN)
NAN_BOXED(31046,16,FLEN)
NAN_BOXED(31046,16,FLEN)
NAN_BOXED(31046,16,FLEN)
NAN_BOXED(31046,16,FLEN)
NAN_BOXED(31046,16,FLEN)
NAN_BOXED(31046,16,FLEN)
NAN_BOXED(31046,16,FLEN)
NAN_BOXED(31046,16,FLEN)
NAN_BOXED(31046,16,FLEN)
NAN_BOXED(31046,16,FLEN)
NAN_BOXED(30494,16,FLEN)
NAN_BOXED(30494,16,FLEN)
NAN_BOXED(30494,16,FLEN)
NAN_BOXED(30494,16,FLEN)
NAN_BOXED(30494,16,FLEN)
NAN_BOXED(30494,16,FLEN)
NAN_BOXED(30494,16,FLEN)
NAN_BOXED(30494,16,FLEN)
NAN_BOXED(30494,16,FLEN)
NAN_BOXED(30494,16,FLEN)
NAN_BOXED(28748,16,FLEN)
NAN_BOXED(28748,16,FLEN)
NAN_BOXED(28748,16,FLEN)
NAN_BOXED(28748,16,FLEN)
NAN_BOXED(31406,16,FLEN)
NAN_BOXED(31406,16,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;



signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 26*((SIGALIGN)/4),4,0xdeadbeef


signature_x6_0:
    .fill 26*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_2:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_3:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_4:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_5:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_6:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_7:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_8:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_9:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_10:
    .fill 126*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;

mtrap_sigptr:
    .fill 64*XLEN/32,4,0xdeadbeef

tsig_end_canary:
CANARY;
#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif


sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
