
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.11.0
// timestamp : Tue Jan 30 08:45:11 2024 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fnmsub.cgf \
 \
//                  -- xlen 32  \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fnmsub.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV32FD_Zicsr,RV64F_Zicsr_Zfh,RV64FD_Zicsr extension for the fnmsub_b1 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV32IFD_Zicsr,RV64IF_Zicsr_Zfh,RV64IFD_Zicsr")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fnmsub_b1)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_3068:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x83ff;
op3val:0x7c01; valaddr_reg:x3; val_offset:9204*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9204*FLEN/8, x4, x1, x2)

inst_3069:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x83ff;
op3val:0xfd55; valaddr_reg:x3; val_offset:9207*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9207*FLEN/8, x4, x1, x2)

inst_3070:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x83ff;
op3val:0x3c00; valaddr_reg:x3; val_offset:9210*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9210*FLEN/8, x4, x1, x2)

inst_3071:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x83ff;
op3val:0xbc00; valaddr_reg:x3; val_offset:9213*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9213*FLEN/8, x4, x1, x2)

RVTEST_SIGBASE(x1,signature_x1_25)
inst_3072:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x400;
op3val:0x0; valaddr_reg:x3; val_offset:9216*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9216*FLEN/8, x4, x1, x2)

inst_3073:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x400;
op3val:0x8000; valaddr_reg:x3; val_offset:9219*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9219*FLEN/8, x4, x1, x2)

inst_3074:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x400;
op3val:0x1; valaddr_reg:x3; val_offset:9222*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9222*FLEN/8, x4, x1, x2)

inst_3075:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x400;
op3val:0x8001; valaddr_reg:x3; val_offset:9225*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9225*FLEN/8, x4, x1, x2)

inst_3076:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x400;
op3val:0x2; valaddr_reg:x3; val_offset:9228*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9228*FLEN/8, x4, x1, x2)

inst_3077:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x400;
op3val:0x83fe; valaddr_reg:x3; val_offset:9231*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9231*FLEN/8, x4, x1, x2)

inst_3078:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x400;
op3val:0x3ff; valaddr_reg:x3; val_offset:9234*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9234*FLEN/8, x4, x1, x2)

inst_3079:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x400;
op3val:0x83ff; valaddr_reg:x3; val_offset:9237*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9237*FLEN/8, x4, x1, x2)

inst_3080:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x400;
op3val:0x400; valaddr_reg:x3; val_offset:9240*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9240*FLEN/8, x4, x1, x2)

inst_3081:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x400;
op3val:0x8400; valaddr_reg:x3; val_offset:9243*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9243*FLEN/8, x4, x1, x2)

inst_3082:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x400;
op3val:0x401; valaddr_reg:x3; val_offset:9246*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9246*FLEN/8, x4, x1, x2)

inst_3083:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x400;
op3val:0x8455; valaddr_reg:x3; val_offset:9249*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9249*FLEN/8, x4, x1, x2)

inst_3084:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x400;
op3val:0x7bff; valaddr_reg:x3; val_offset:9252*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9252*FLEN/8, x4, x1, x2)

inst_3085:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x400;
op3val:0xfbff; valaddr_reg:x3; val_offset:9255*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9255*FLEN/8, x4, x1, x2)

inst_3086:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x400;
op3val:0x7c00; valaddr_reg:x3; val_offset:9258*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9258*FLEN/8, x4, x1, x2)

inst_3087:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x400;
op3val:0xfc00; valaddr_reg:x3; val_offset:9261*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9261*FLEN/8, x4, x1, x2)

inst_3088:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x400;
op3val:0x7e00; valaddr_reg:x3; val_offset:9264*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9264*FLEN/8, x4, x1, x2)

inst_3089:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x400;
op3val:0xfe00; valaddr_reg:x3; val_offset:9267*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9267*FLEN/8, x4, x1, x2)

inst_3090:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x400;
op3val:0x7e01; valaddr_reg:x3; val_offset:9270*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9270*FLEN/8, x4, x1, x2)

inst_3091:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x400;
op3val:0xfe55; valaddr_reg:x3; val_offset:9273*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9273*FLEN/8, x4, x1, x2)

inst_3092:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x400;
op3val:0x7c01; valaddr_reg:x3; val_offset:9276*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9276*FLEN/8, x4, x1, x2)

inst_3093:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x400;
op3val:0xfd55; valaddr_reg:x3; val_offset:9279*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9279*FLEN/8, x4, x1, x2)

inst_3094:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x400;
op3val:0x3c00; valaddr_reg:x3; val_offset:9282*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9282*FLEN/8, x4, x1, x2)

inst_3095:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x400;
op3val:0xbc00; valaddr_reg:x3; val_offset:9285*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9285*FLEN/8, x4, x1, x2)

inst_3096:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x8400;
op3val:0x0; valaddr_reg:x3; val_offset:9288*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9288*FLEN/8, x4, x1, x2)

inst_3097:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x8400;
op3val:0x8000; valaddr_reg:x3; val_offset:9291*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9291*FLEN/8, x4, x1, x2)

inst_3098:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x8400;
op3val:0x1; valaddr_reg:x3; val_offset:9294*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9294*FLEN/8, x4, x1, x2)

inst_3099:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x8400;
op3val:0x8001; valaddr_reg:x3; val_offset:9297*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9297*FLEN/8, x4, x1, x2)

inst_3100:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x8400;
op3val:0x2; valaddr_reg:x3; val_offset:9300*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9300*FLEN/8, x4, x1, x2)

inst_3101:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x8400;
op3val:0x83fe; valaddr_reg:x3; val_offset:9303*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9303*FLEN/8, x4, x1, x2)

inst_3102:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x8400;
op3val:0x3ff; valaddr_reg:x3; val_offset:9306*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9306*FLEN/8, x4, x1, x2)

inst_3103:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x8400;
op3val:0x83ff; valaddr_reg:x3; val_offset:9309*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9309*FLEN/8, x4, x1, x2)

inst_3104:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x8400;
op3val:0x400; valaddr_reg:x3; val_offset:9312*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9312*FLEN/8, x4, x1, x2)

inst_3105:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x8400;
op3val:0x8400; valaddr_reg:x3; val_offset:9315*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9315*FLEN/8, x4, x1, x2)

inst_3106:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x8400;
op3val:0x401; valaddr_reg:x3; val_offset:9318*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9318*FLEN/8, x4, x1, x2)

inst_3107:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x8400;
op3val:0x8455; valaddr_reg:x3; val_offset:9321*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9321*FLEN/8, x4, x1, x2)

inst_3108:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x8400;
op3val:0x7bff; valaddr_reg:x3; val_offset:9324*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9324*FLEN/8, x4, x1, x2)

inst_3109:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x8400;
op3val:0xfbff; valaddr_reg:x3; val_offset:9327*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9327*FLEN/8, x4, x1, x2)

inst_3110:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x8400;
op3val:0x7c00; valaddr_reg:x3; val_offset:9330*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9330*FLEN/8, x4, x1, x2)

inst_3111:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x8400;
op3val:0xfc00; valaddr_reg:x3; val_offset:9333*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9333*FLEN/8, x4, x1, x2)

inst_3112:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x8400;
op3val:0x7e00; valaddr_reg:x3; val_offset:9336*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9336*FLEN/8, x4, x1, x2)

inst_3113:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x8400;
op3val:0xfe00; valaddr_reg:x3; val_offset:9339*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9339*FLEN/8, x4, x1, x2)

inst_3114:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x8400;
op3val:0x7e01; valaddr_reg:x3; val_offset:9342*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9342*FLEN/8, x4, x1, x2)

inst_3115:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x8400;
op3val:0xfe55; valaddr_reg:x3; val_offset:9345*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9345*FLEN/8, x4, x1, x2)

inst_3116:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x8400;
op3val:0x7c01; valaddr_reg:x3; val_offset:9348*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9348*FLEN/8, x4, x1, x2)

inst_3117:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x8400;
op3val:0xfd55; valaddr_reg:x3; val_offset:9351*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9351*FLEN/8, x4, x1, x2)

inst_3118:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x8400;
op3val:0x3c00; valaddr_reg:x3; val_offset:9354*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9354*FLEN/8, x4, x1, x2)

inst_3119:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x8400;
op3val:0xbc00; valaddr_reg:x3; val_offset:9357*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9357*FLEN/8, x4, x1, x2)

inst_3120:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x401;
op3val:0x0; valaddr_reg:x3; val_offset:9360*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9360*FLEN/8, x4, x1, x2)

inst_3121:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x401;
op3val:0x8000; valaddr_reg:x3; val_offset:9363*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9363*FLEN/8, x4, x1, x2)

inst_3122:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x401;
op3val:0x1; valaddr_reg:x3; val_offset:9366*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9366*FLEN/8, x4, x1, x2)

inst_3123:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x401;
op3val:0x8001; valaddr_reg:x3; val_offset:9369*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9369*FLEN/8, x4, x1, x2)

inst_3124:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x401;
op3val:0x2; valaddr_reg:x3; val_offset:9372*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9372*FLEN/8, x4, x1, x2)

inst_3125:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x401;
op3val:0x83fe; valaddr_reg:x3; val_offset:9375*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9375*FLEN/8, x4, x1, x2)

inst_3126:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x401;
op3val:0x3ff; valaddr_reg:x3; val_offset:9378*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9378*FLEN/8, x4, x1, x2)

inst_3127:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x401;
op3val:0x83ff; valaddr_reg:x3; val_offset:9381*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9381*FLEN/8, x4, x1, x2)

inst_3128:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x401;
op3val:0x400; valaddr_reg:x3; val_offset:9384*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9384*FLEN/8, x4, x1, x2)

inst_3129:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x401;
op3val:0x8400; valaddr_reg:x3; val_offset:9387*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9387*FLEN/8, x4, x1, x2)

inst_3130:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x401;
op3val:0x401; valaddr_reg:x3; val_offset:9390*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9390*FLEN/8, x4, x1, x2)

inst_3131:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x401;
op3val:0x8455; valaddr_reg:x3; val_offset:9393*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9393*FLEN/8, x4, x1, x2)

inst_3132:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x401;
op3val:0x7bff; valaddr_reg:x3; val_offset:9396*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9396*FLEN/8, x4, x1, x2)

inst_3133:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x401;
op3val:0xfbff; valaddr_reg:x3; val_offset:9399*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9399*FLEN/8, x4, x1, x2)

inst_3134:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x401;
op3val:0x7c00; valaddr_reg:x3; val_offset:9402*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9402*FLEN/8, x4, x1, x2)

inst_3135:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x401;
op3val:0xfc00; valaddr_reg:x3; val_offset:9405*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9405*FLEN/8, x4, x1, x2)

inst_3136:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x401;
op3val:0x7e00; valaddr_reg:x3; val_offset:9408*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9408*FLEN/8, x4, x1, x2)

inst_3137:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x401;
op3val:0xfe00; valaddr_reg:x3; val_offset:9411*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9411*FLEN/8, x4, x1, x2)

inst_3138:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x401;
op3val:0x7e01; valaddr_reg:x3; val_offset:9414*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9414*FLEN/8, x4, x1, x2)

inst_3139:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x401;
op3val:0xfe55; valaddr_reg:x3; val_offset:9417*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9417*FLEN/8, x4, x1, x2)

inst_3140:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x401;
op3val:0x7c01; valaddr_reg:x3; val_offset:9420*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9420*FLEN/8, x4, x1, x2)

inst_3141:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x401;
op3val:0xfd55; valaddr_reg:x3; val_offset:9423*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9423*FLEN/8, x4, x1, x2)

inst_3142:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x401;
op3val:0x3c00; valaddr_reg:x3; val_offset:9426*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9426*FLEN/8, x4, x1, x2)

inst_3143:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x401;
op3val:0xbc00; valaddr_reg:x3; val_offset:9429*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9429*FLEN/8, x4, x1, x2)

inst_3144:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x8455;
op3val:0x0; valaddr_reg:x3; val_offset:9432*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9432*FLEN/8, x4, x1, x2)

inst_3145:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x8455;
op3val:0x8000; valaddr_reg:x3; val_offset:9435*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9435*FLEN/8, x4, x1, x2)

inst_3146:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x8455;
op3val:0x1; valaddr_reg:x3; val_offset:9438*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9438*FLEN/8, x4, x1, x2)

inst_3147:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x8455;
op3val:0x8001; valaddr_reg:x3; val_offset:9441*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9441*FLEN/8, x4, x1, x2)

inst_3148:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x8455;
op3val:0x2; valaddr_reg:x3; val_offset:9444*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9444*FLEN/8, x4, x1, x2)

inst_3149:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x8455;
op3val:0x83fe; valaddr_reg:x3; val_offset:9447*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9447*FLEN/8, x4, x1, x2)

inst_3150:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x8455;
op3val:0x3ff; valaddr_reg:x3; val_offset:9450*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9450*FLEN/8, x4, x1, x2)

inst_3151:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x8455;
op3val:0x83ff; valaddr_reg:x3; val_offset:9453*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9453*FLEN/8, x4, x1, x2)

inst_3152:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x8455;
op3val:0x400; valaddr_reg:x3; val_offset:9456*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9456*FLEN/8, x4, x1, x2)

inst_3153:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x8455;
op3val:0x8400; valaddr_reg:x3; val_offset:9459*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9459*FLEN/8, x4, x1, x2)

inst_3154:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x8455;
op3val:0x401; valaddr_reg:x3; val_offset:9462*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9462*FLEN/8, x4, x1, x2)

inst_3155:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x8455;
op3val:0x8455; valaddr_reg:x3; val_offset:9465*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9465*FLEN/8, x4, x1, x2)

inst_3156:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x8455;
op3val:0x7bff; valaddr_reg:x3; val_offset:9468*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9468*FLEN/8, x4, x1, x2)

inst_3157:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x8455;
op3val:0xfbff; valaddr_reg:x3; val_offset:9471*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9471*FLEN/8, x4, x1, x2)

inst_3158:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x8455;
op3val:0x7c00; valaddr_reg:x3; val_offset:9474*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9474*FLEN/8, x4, x1, x2)

inst_3159:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x8455;
op3val:0xfc00; valaddr_reg:x3; val_offset:9477*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9477*FLEN/8, x4, x1, x2)

inst_3160:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x8455;
op3val:0x7e00; valaddr_reg:x3; val_offset:9480*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9480*FLEN/8, x4, x1, x2)

inst_3161:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x8455;
op3val:0xfe00; valaddr_reg:x3; val_offset:9483*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9483*FLEN/8, x4, x1, x2)

inst_3162:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x8455;
op3val:0x7e01; valaddr_reg:x3; val_offset:9486*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9486*FLEN/8, x4, x1, x2)

inst_3163:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x8455;
op3val:0xfe55; valaddr_reg:x3; val_offset:9489*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9489*FLEN/8, x4, x1, x2)

inst_3164:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x8455;
op3val:0x7c01; valaddr_reg:x3; val_offset:9492*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9492*FLEN/8, x4, x1, x2)

inst_3165:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x8455;
op3val:0xfd55; valaddr_reg:x3; val_offset:9495*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9495*FLEN/8, x4, x1, x2)

inst_3166:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x8455;
op3val:0x3c00; valaddr_reg:x3; val_offset:9498*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9498*FLEN/8, x4, x1, x2)

inst_3167:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x8455;
op3val:0xbc00; valaddr_reg:x3; val_offset:9501*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9501*FLEN/8, x4, x1, x2)

inst_3168:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7bff;
op3val:0x0; valaddr_reg:x3; val_offset:9504*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9504*FLEN/8, x4, x1, x2)

inst_3169:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7bff;
op3val:0x8000; valaddr_reg:x3; val_offset:9507*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9507*FLEN/8, x4, x1, x2)

inst_3170:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7bff;
op3val:0x1; valaddr_reg:x3; val_offset:9510*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9510*FLEN/8, x4, x1, x2)

inst_3171:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7bff;
op3val:0x8001; valaddr_reg:x3; val_offset:9513*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9513*FLEN/8, x4, x1, x2)

inst_3172:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7bff;
op3val:0x2; valaddr_reg:x3; val_offset:9516*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9516*FLEN/8, x4, x1, x2)

inst_3173:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7bff;
op3val:0x83fe; valaddr_reg:x3; val_offset:9519*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9519*FLEN/8, x4, x1, x2)

inst_3174:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7bff;
op3val:0x3ff; valaddr_reg:x3; val_offset:9522*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9522*FLEN/8, x4, x1, x2)

inst_3175:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7bff;
op3val:0x83ff; valaddr_reg:x3; val_offset:9525*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9525*FLEN/8, x4, x1, x2)

inst_3176:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7bff;
op3val:0x400; valaddr_reg:x3; val_offset:9528*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9528*FLEN/8, x4, x1, x2)

inst_3177:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7bff;
op3val:0x8400; valaddr_reg:x3; val_offset:9531*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9531*FLEN/8, x4, x1, x2)

inst_3178:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7bff;
op3val:0x401; valaddr_reg:x3; val_offset:9534*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9534*FLEN/8, x4, x1, x2)

inst_3179:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7bff;
op3val:0x8455; valaddr_reg:x3; val_offset:9537*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9537*FLEN/8, x4, x1, x2)

inst_3180:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7bff;
op3val:0x7bff; valaddr_reg:x3; val_offset:9540*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9540*FLEN/8, x4, x1, x2)

inst_3181:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7bff;
op3val:0xfbff; valaddr_reg:x3; val_offset:9543*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9543*FLEN/8, x4, x1, x2)

inst_3182:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7bff;
op3val:0x7c00; valaddr_reg:x3; val_offset:9546*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9546*FLEN/8, x4, x1, x2)

inst_3183:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7bff;
op3val:0xfc00; valaddr_reg:x3; val_offset:9549*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9549*FLEN/8, x4, x1, x2)

inst_3184:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7bff;
op3val:0x7e00; valaddr_reg:x3; val_offset:9552*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9552*FLEN/8, x4, x1, x2)

inst_3185:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7bff;
op3val:0xfe00; valaddr_reg:x3; val_offset:9555*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9555*FLEN/8, x4, x1, x2)

inst_3186:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7bff;
op3val:0x7e01; valaddr_reg:x3; val_offset:9558*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9558*FLEN/8, x4, x1, x2)

inst_3187:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7bff;
op3val:0xfe55; valaddr_reg:x3; val_offset:9561*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9561*FLEN/8, x4, x1, x2)

inst_3188:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7bff;
op3val:0x7c01; valaddr_reg:x3; val_offset:9564*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9564*FLEN/8, x4, x1, x2)

inst_3189:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7bff;
op3val:0xfd55; valaddr_reg:x3; val_offset:9567*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9567*FLEN/8, x4, x1, x2)

inst_3190:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7bff;
op3val:0x3c00; valaddr_reg:x3; val_offset:9570*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9570*FLEN/8, x4, x1, x2)

inst_3191:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7bff;
op3val:0xbc00; valaddr_reg:x3; val_offset:9573*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9573*FLEN/8, x4, x1, x2)

inst_3192:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfbff;
op3val:0x0; valaddr_reg:x3; val_offset:9576*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9576*FLEN/8, x4, x1, x2)

inst_3193:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfbff;
op3val:0x8000; valaddr_reg:x3; val_offset:9579*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9579*FLEN/8, x4, x1, x2)

inst_3194:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfbff;
op3val:0x1; valaddr_reg:x3; val_offset:9582*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9582*FLEN/8, x4, x1, x2)

inst_3195:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfbff;
op3val:0x8001; valaddr_reg:x3; val_offset:9585*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9585*FLEN/8, x4, x1, x2)

inst_3196:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfbff;
op3val:0x2; valaddr_reg:x3; val_offset:9588*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9588*FLEN/8, x4, x1, x2)

inst_3197:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfbff;
op3val:0x83fe; valaddr_reg:x3; val_offset:9591*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9591*FLEN/8, x4, x1, x2)

inst_3198:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfbff;
op3val:0x3ff; valaddr_reg:x3; val_offset:9594*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9594*FLEN/8, x4, x1, x2)

inst_3199:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfbff;
op3val:0x83ff; valaddr_reg:x3; val_offset:9597*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9597*FLEN/8, x4, x1, x2)

RVTEST_SIGBASE(x1,signature_x1_26)
inst_3200:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfbff;
op3val:0x400; valaddr_reg:x3; val_offset:9600*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9600*FLEN/8, x4, x1, x2)

inst_3201:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfbff;
op3val:0x8400; valaddr_reg:x3; val_offset:9603*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9603*FLEN/8, x4, x1, x2)

inst_3202:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfbff;
op3val:0x401; valaddr_reg:x3; val_offset:9606*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9606*FLEN/8, x4, x1, x2)

inst_3203:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfbff;
op3val:0x8455; valaddr_reg:x3; val_offset:9609*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9609*FLEN/8, x4, x1, x2)

inst_3204:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfbff;
op3val:0x7bff; valaddr_reg:x3; val_offset:9612*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9612*FLEN/8, x4, x1, x2)

inst_3205:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfbff;
op3val:0xfbff; valaddr_reg:x3; val_offset:9615*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9615*FLEN/8, x4, x1, x2)

inst_3206:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfbff;
op3val:0x7c00; valaddr_reg:x3; val_offset:9618*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9618*FLEN/8, x4, x1, x2)

inst_3207:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfbff;
op3val:0xfc00; valaddr_reg:x3; val_offset:9621*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9621*FLEN/8, x4, x1, x2)

inst_3208:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfbff;
op3val:0x7e00; valaddr_reg:x3; val_offset:9624*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9624*FLEN/8, x4, x1, x2)

inst_3209:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfbff;
op3val:0xfe00; valaddr_reg:x3; val_offset:9627*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9627*FLEN/8, x4, x1, x2)

inst_3210:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfbff;
op3val:0x7e01; valaddr_reg:x3; val_offset:9630*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9630*FLEN/8, x4, x1, x2)

inst_3211:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfbff;
op3val:0xfe55; valaddr_reg:x3; val_offset:9633*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9633*FLEN/8, x4, x1, x2)

inst_3212:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfbff;
op3val:0x7c01; valaddr_reg:x3; val_offset:9636*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9636*FLEN/8, x4, x1, x2)

inst_3213:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfbff;
op3val:0xfd55; valaddr_reg:x3; val_offset:9639*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9639*FLEN/8, x4, x1, x2)

inst_3214:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfbff;
op3val:0x3c00; valaddr_reg:x3; val_offset:9642*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9642*FLEN/8, x4, x1, x2)

inst_3215:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfbff;
op3val:0xbc00; valaddr_reg:x3; val_offset:9645*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9645*FLEN/8, x4, x1, x2)

inst_3216:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7c00;
op3val:0x0; valaddr_reg:x3; val_offset:9648*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9648*FLEN/8, x4, x1, x2)

inst_3217:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7c00;
op3val:0x8000; valaddr_reg:x3; val_offset:9651*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9651*FLEN/8, x4, x1, x2)

inst_3218:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7c00;
op3val:0x1; valaddr_reg:x3; val_offset:9654*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9654*FLEN/8, x4, x1, x2)

inst_3219:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7c00;
op3val:0x8001; valaddr_reg:x3; val_offset:9657*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9657*FLEN/8, x4, x1, x2)

inst_3220:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7c00;
op3val:0x2; valaddr_reg:x3; val_offset:9660*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9660*FLEN/8, x4, x1, x2)

inst_3221:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7c00;
op3val:0x83fe; valaddr_reg:x3; val_offset:9663*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9663*FLEN/8, x4, x1, x2)

inst_3222:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7c00;
op3val:0x3ff; valaddr_reg:x3; val_offset:9666*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9666*FLEN/8, x4, x1, x2)

inst_3223:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7c00;
op3val:0x83ff; valaddr_reg:x3; val_offset:9669*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9669*FLEN/8, x4, x1, x2)

inst_3224:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7c00;
op3val:0x400; valaddr_reg:x3; val_offset:9672*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9672*FLEN/8, x4, x1, x2)

inst_3225:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7c00;
op3val:0x8400; valaddr_reg:x3; val_offset:9675*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9675*FLEN/8, x4, x1, x2)

inst_3226:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7c00;
op3val:0x401; valaddr_reg:x3; val_offset:9678*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9678*FLEN/8, x4, x1, x2)

inst_3227:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7c00;
op3val:0x8455; valaddr_reg:x3; val_offset:9681*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9681*FLEN/8, x4, x1, x2)

inst_3228:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7c00;
op3val:0x7bff; valaddr_reg:x3; val_offset:9684*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9684*FLEN/8, x4, x1, x2)

inst_3229:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7c00;
op3val:0xfbff; valaddr_reg:x3; val_offset:9687*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9687*FLEN/8, x4, x1, x2)

inst_3230:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7c00;
op3val:0x7c00; valaddr_reg:x3; val_offset:9690*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9690*FLEN/8, x4, x1, x2)

inst_3231:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7c00;
op3val:0xfc00; valaddr_reg:x3; val_offset:9693*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9693*FLEN/8, x4, x1, x2)

inst_3232:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7c00;
op3val:0x7e00; valaddr_reg:x3; val_offset:9696*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9696*FLEN/8, x4, x1, x2)

inst_3233:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7c00;
op3val:0xfe00; valaddr_reg:x3; val_offset:9699*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9699*FLEN/8, x4, x1, x2)

inst_3234:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7c00;
op3val:0x7e01; valaddr_reg:x3; val_offset:9702*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9702*FLEN/8, x4, x1, x2)

inst_3235:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7c00;
op3val:0xfe55; valaddr_reg:x3; val_offset:9705*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9705*FLEN/8, x4, x1, x2)

inst_3236:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7c00;
op3val:0x7c01; valaddr_reg:x3; val_offset:9708*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9708*FLEN/8, x4, x1, x2)

inst_3237:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7c00;
op3val:0xfd55; valaddr_reg:x3; val_offset:9711*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9711*FLEN/8, x4, x1, x2)

inst_3238:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7c00;
op3val:0x3c00; valaddr_reg:x3; val_offset:9714*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9714*FLEN/8, x4, x1, x2)

inst_3239:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7c00;
op3val:0xbc00; valaddr_reg:x3; val_offset:9717*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9717*FLEN/8, x4, x1, x2)

inst_3240:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfc00;
op3val:0x0; valaddr_reg:x3; val_offset:9720*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9720*FLEN/8, x4, x1, x2)

inst_3241:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfc00;
op3val:0x8000; valaddr_reg:x3; val_offset:9723*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9723*FLEN/8, x4, x1, x2)

inst_3242:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfc00;
op3val:0x1; valaddr_reg:x3; val_offset:9726*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9726*FLEN/8, x4, x1, x2)

inst_3243:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfc00;
op3val:0x8001; valaddr_reg:x3; val_offset:9729*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9729*FLEN/8, x4, x1, x2)

inst_3244:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfc00;
op3val:0x2; valaddr_reg:x3; val_offset:9732*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9732*FLEN/8, x4, x1, x2)

inst_3245:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfc00;
op3val:0x83fe; valaddr_reg:x3; val_offset:9735*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9735*FLEN/8, x4, x1, x2)

inst_3246:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfc00;
op3val:0x3ff; valaddr_reg:x3; val_offset:9738*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9738*FLEN/8, x4, x1, x2)

inst_3247:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfc00;
op3val:0x83ff; valaddr_reg:x3; val_offset:9741*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9741*FLEN/8, x4, x1, x2)

inst_3248:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfc00;
op3val:0x400; valaddr_reg:x3; val_offset:9744*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9744*FLEN/8, x4, x1, x2)

inst_3249:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfc00;
op3val:0x8400; valaddr_reg:x3; val_offset:9747*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9747*FLEN/8, x4, x1, x2)

inst_3250:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfc00;
op3val:0x401; valaddr_reg:x3; val_offset:9750*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9750*FLEN/8, x4, x1, x2)

inst_3251:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfc00;
op3val:0x8455; valaddr_reg:x3; val_offset:9753*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9753*FLEN/8, x4, x1, x2)

inst_3252:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfc00;
op3val:0x7bff; valaddr_reg:x3; val_offset:9756*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9756*FLEN/8, x4, x1, x2)

inst_3253:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfc00;
op3val:0xfbff; valaddr_reg:x3; val_offset:9759*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9759*FLEN/8, x4, x1, x2)

inst_3254:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfc00;
op3val:0x7c00; valaddr_reg:x3; val_offset:9762*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9762*FLEN/8, x4, x1, x2)

inst_3255:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfc00;
op3val:0xfc00; valaddr_reg:x3; val_offset:9765*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9765*FLEN/8, x4, x1, x2)

inst_3256:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfc00;
op3val:0x7e00; valaddr_reg:x3; val_offset:9768*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9768*FLEN/8, x4, x1, x2)

inst_3257:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfc00;
op3val:0xfe00; valaddr_reg:x3; val_offset:9771*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9771*FLEN/8, x4, x1, x2)

inst_3258:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfc00;
op3val:0x7e01; valaddr_reg:x3; val_offset:9774*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9774*FLEN/8, x4, x1, x2)

inst_3259:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfc00;
op3val:0xfe55; valaddr_reg:x3; val_offset:9777*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9777*FLEN/8, x4, x1, x2)

inst_3260:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfc00;
op3val:0x7c01; valaddr_reg:x3; val_offset:9780*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9780*FLEN/8, x4, x1, x2)

inst_3261:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfc00;
op3val:0xfd55; valaddr_reg:x3; val_offset:9783*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9783*FLEN/8, x4, x1, x2)

inst_3262:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfc00;
op3val:0x3c00; valaddr_reg:x3; val_offset:9786*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9786*FLEN/8, x4, x1, x2)

inst_3263:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfc00;
op3val:0xbc00; valaddr_reg:x3; val_offset:9789*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9789*FLEN/8, x4, x1, x2)

inst_3264:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7e00;
op3val:0x0; valaddr_reg:x3; val_offset:9792*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9792*FLEN/8, x4, x1, x2)

inst_3265:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7e00;
op3val:0x8000; valaddr_reg:x3; val_offset:9795*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9795*FLEN/8, x4, x1, x2)

inst_3266:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7e00;
op3val:0x1; valaddr_reg:x3; val_offset:9798*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9798*FLEN/8, x4, x1, x2)

inst_3267:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7e00;
op3val:0x8001; valaddr_reg:x3; val_offset:9801*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9801*FLEN/8, x4, x1, x2)

inst_3268:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7e00;
op3val:0x2; valaddr_reg:x3; val_offset:9804*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9804*FLEN/8, x4, x1, x2)

inst_3269:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7e00;
op3val:0x83fe; valaddr_reg:x3; val_offset:9807*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9807*FLEN/8, x4, x1, x2)

inst_3270:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7e00;
op3val:0x3ff; valaddr_reg:x3; val_offset:9810*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9810*FLEN/8, x4, x1, x2)

inst_3271:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7e00;
op3val:0x83ff; valaddr_reg:x3; val_offset:9813*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9813*FLEN/8, x4, x1, x2)

inst_3272:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7e00;
op3val:0x400; valaddr_reg:x3; val_offset:9816*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9816*FLEN/8, x4, x1, x2)

inst_3273:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7e00;
op3val:0x8400; valaddr_reg:x3; val_offset:9819*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9819*FLEN/8, x4, x1, x2)

inst_3274:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7e00;
op3val:0x401; valaddr_reg:x3; val_offset:9822*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9822*FLEN/8, x4, x1, x2)

inst_3275:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7e00;
op3val:0x8455; valaddr_reg:x3; val_offset:9825*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9825*FLEN/8, x4, x1, x2)

inst_3276:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7e00;
op3val:0x7bff; valaddr_reg:x3; val_offset:9828*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9828*FLEN/8, x4, x1, x2)

inst_3277:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7e00;
op3val:0xfbff; valaddr_reg:x3; val_offset:9831*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9831*FLEN/8, x4, x1, x2)

inst_3278:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7e00;
op3val:0x7c00; valaddr_reg:x3; val_offset:9834*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9834*FLEN/8, x4, x1, x2)

inst_3279:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7e00;
op3val:0xfc00; valaddr_reg:x3; val_offset:9837*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9837*FLEN/8, x4, x1, x2)

inst_3280:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7e00;
op3val:0x7e00; valaddr_reg:x3; val_offset:9840*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9840*FLEN/8, x4, x1, x2)

inst_3281:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7e00;
op3val:0xfe00; valaddr_reg:x3; val_offset:9843*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9843*FLEN/8, x4, x1, x2)

inst_3282:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7e00;
op3val:0x7e01; valaddr_reg:x3; val_offset:9846*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9846*FLEN/8, x4, x1, x2)

inst_3283:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7e00;
op3val:0xfe55; valaddr_reg:x3; val_offset:9849*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9849*FLEN/8, x4, x1, x2)

inst_3284:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7e00;
op3val:0x7c01; valaddr_reg:x3; val_offset:9852*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9852*FLEN/8, x4, x1, x2)

inst_3285:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7e00;
op3val:0xfd55; valaddr_reg:x3; val_offset:9855*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9855*FLEN/8, x4, x1, x2)

inst_3286:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7e00;
op3val:0x3c00; valaddr_reg:x3; val_offset:9858*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9858*FLEN/8, x4, x1, x2)

inst_3287:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7e00;
op3val:0xbc00; valaddr_reg:x3; val_offset:9861*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9861*FLEN/8, x4, x1, x2)

inst_3288:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfe00;
op3val:0x0; valaddr_reg:x3; val_offset:9864*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9864*FLEN/8, x4, x1, x2)

inst_3289:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfe00;
op3val:0x8000; valaddr_reg:x3; val_offset:9867*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9867*FLEN/8, x4, x1, x2)

inst_3290:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfe00;
op3val:0x1; valaddr_reg:x3; val_offset:9870*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9870*FLEN/8, x4, x1, x2)

inst_3291:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfe00;
op3val:0x8001; valaddr_reg:x3; val_offset:9873*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9873*FLEN/8, x4, x1, x2)

inst_3292:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfe00;
op3val:0x2; valaddr_reg:x3; val_offset:9876*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9876*FLEN/8, x4, x1, x2)

inst_3293:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfe00;
op3val:0x83fe; valaddr_reg:x3; val_offset:9879*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9879*FLEN/8, x4, x1, x2)

inst_3294:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfe00;
op3val:0x3ff; valaddr_reg:x3; val_offset:9882*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9882*FLEN/8, x4, x1, x2)

inst_3295:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfe00;
op3val:0x83ff; valaddr_reg:x3; val_offset:9885*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9885*FLEN/8, x4, x1, x2)

inst_3296:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfe00;
op3val:0x400; valaddr_reg:x3; val_offset:9888*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9888*FLEN/8, x4, x1, x2)

inst_3297:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfe00;
op3val:0x8400; valaddr_reg:x3; val_offset:9891*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9891*FLEN/8, x4, x1, x2)

inst_3298:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfe00;
op3val:0x401; valaddr_reg:x3; val_offset:9894*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9894*FLEN/8, x4, x1, x2)

inst_3299:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfe00;
op3val:0x8455; valaddr_reg:x3; val_offset:9897*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9897*FLEN/8, x4, x1, x2)

inst_3300:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfe00;
op3val:0x7bff; valaddr_reg:x3; val_offset:9900*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9900*FLEN/8, x4, x1, x2)

inst_3301:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfe00;
op3val:0xfbff; valaddr_reg:x3; val_offset:9903*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9903*FLEN/8, x4, x1, x2)

inst_3302:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfe00;
op3val:0x7c00; valaddr_reg:x3; val_offset:9906*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9906*FLEN/8, x4, x1, x2)

inst_3303:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfe00;
op3val:0xfc00; valaddr_reg:x3; val_offset:9909*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9909*FLEN/8, x4, x1, x2)

inst_3304:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfe00;
op3val:0x7e00; valaddr_reg:x3; val_offset:9912*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9912*FLEN/8, x4, x1, x2)

inst_3305:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfe00;
op3val:0xfe00; valaddr_reg:x3; val_offset:9915*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9915*FLEN/8, x4, x1, x2)

inst_3306:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfe00;
op3val:0x7e01; valaddr_reg:x3; val_offset:9918*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9918*FLEN/8, x4, x1, x2)

inst_3307:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfe00;
op3val:0xfe55; valaddr_reg:x3; val_offset:9921*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9921*FLEN/8, x4, x1, x2)

inst_3308:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfe00;
op3val:0x7c01; valaddr_reg:x3; val_offset:9924*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9924*FLEN/8, x4, x1, x2)

inst_3309:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfe00;
op3val:0xfd55; valaddr_reg:x3; val_offset:9927*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9927*FLEN/8, x4, x1, x2)

inst_3310:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfe00;
op3val:0x3c00; valaddr_reg:x3; val_offset:9930*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9930*FLEN/8, x4, x1, x2)

inst_3311:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x200 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfe00;
op3val:0xbc00; valaddr_reg:x3; val_offset:9933*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9933*FLEN/8, x4, x1, x2)

inst_3312:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7e01;
op3val:0x0; valaddr_reg:x3; val_offset:9936*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9936*FLEN/8, x4, x1, x2)

inst_3313:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7e01;
op3val:0x8000; valaddr_reg:x3; val_offset:9939*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9939*FLEN/8, x4, x1, x2)

inst_3314:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7e01;
op3val:0x1; valaddr_reg:x3; val_offset:9942*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9942*FLEN/8, x4, x1, x2)

inst_3315:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7e01;
op3val:0x8001; valaddr_reg:x3; val_offset:9945*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9945*FLEN/8, x4, x1, x2)

inst_3316:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7e01;
op3val:0x2; valaddr_reg:x3; val_offset:9948*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9948*FLEN/8, x4, x1, x2)

inst_3317:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7e01;
op3val:0x83fe; valaddr_reg:x3; val_offset:9951*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9951*FLEN/8, x4, x1, x2)

inst_3318:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7e01;
op3val:0x3ff; valaddr_reg:x3; val_offset:9954*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9954*FLEN/8, x4, x1, x2)

inst_3319:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7e01;
op3val:0x83ff; valaddr_reg:x3; val_offset:9957*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9957*FLEN/8, x4, x1, x2)

inst_3320:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7e01;
op3val:0x400; valaddr_reg:x3; val_offset:9960*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9960*FLEN/8, x4, x1, x2)

inst_3321:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7e01;
op3val:0x8400; valaddr_reg:x3; val_offset:9963*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9963*FLEN/8, x4, x1, x2)

inst_3322:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7e01;
op3val:0x401; valaddr_reg:x3; val_offset:9966*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9966*FLEN/8, x4, x1, x2)

inst_3323:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7e01;
op3val:0x8455; valaddr_reg:x3; val_offset:9969*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9969*FLEN/8, x4, x1, x2)

inst_3324:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7e01;
op3val:0x7bff; valaddr_reg:x3; val_offset:9972*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9972*FLEN/8, x4, x1, x2)

inst_3325:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7e01;
op3val:0xfbff; valaddr_reg:x3; val_offset:9975*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9975*FLEN/8, x4, x1, x2)

inst_3326:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7e01;
op3val:0x7c00; valaddr_reg:x3; val_offset:9978*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9978*FLEN/8, x4, x1, x2)

inst_3327:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7e01;
op3val:0xfc00; valaddr_reg:x3; val_offset:9981*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9981*FLEN/8, x4, x1, x2)

RVTEST_SIGBASE(x1,signature_x1_27)
inst_3328:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7e01;
op3val:0x7e00; valaddr_reg:x3; val_offset:9984*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9984*FLEN/8, x4, x1, x2)

inst_3329:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7e01;
op3val:0xfe00; valaddr_reg:x3; val_offset:9987*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9987*FLEN/8, x4, x1, x2)

inst_3330:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7e01;
op3val:0x7e01; valaddr_reg:x3; val_offset:9990*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9990*FLEN/8, x4, x1, x2)

inst_3331:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7e01;
op3val:0xfe55; valaddr_reg:x3; val_offset:9993*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9993*FLEN/8, x4, x1, x2)

inst_3332:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7e01;
op3val:0x7c01; valaddr_reg:x3; val_offset:9996*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9996*FLEN/8, x4, x1, x2)

inst_3333:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7e01;
op3val:0xfd55; valaddr_reg:x3; val_offset:9999*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 9999*FLEN/8, x4, x1, x2)

inst_3334:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7e01;
op3val:0x3c00; valaddr_reg:x3; val_offset:10002*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10002*FLEN/8, x4, x1, x2)

inst_3335:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x201 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7e01;
op3val:0xbc00; valaddr_reg:x3; val_offset:10005*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10005*FLEN/8, x4, x1, x2)

inst_3336:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfe55;
op3val:0x0; valaddr_reg:x3; val_offset:10008*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10008*FLEN/8, x4, x1, x2)

inst_3337:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfe55;
op3val:0x8000; valaddr_reg:x3; val_offset:10011*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10011*FLEN/8, x4, x1, x2)

inst_3338:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfe55;
op3val:0x1; valaddr_reg:x3; val_offset:10014*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10014*FLEN/8, x4, x1, x2)

inst_3339:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfe55;
op3val:0x8001; valaddr_reg:x3; val_offset:10017*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10017*FLEN/8, x4, x1, x2)

inst_3340:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfe55;
op3val:0x2; valaddr_reg:x3; val_offset:10020*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10020*FLEN/8, x4, x1, x2)

inst_3341:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfe55;
op3val:0x83fe; valaddr_reg:x3; val_offset:10023*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10023*FLEN/8, x4, x1, x2)

inst_3342:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfe55;
op3val:0x3ff; valaddr_reg:x3; val_offset:10026*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10026*FLEN/8, x4, x1, x2)

inst_3343:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfe55;
op3val:0x83ff; valaddr_reg:x3; val_offset:10029*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10029*FLEN/8, x4, x1, x2)

inst_3344:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfe55;
op3val:0x400; valaddr_reg:x3; val_offset:10032*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10032*FLEN/8, x4, x1, x2)

inst_3345:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfe55;
op3val:0x8400; valaddr_reg:x3; val_offset:10035*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10035*FLEN/8, x4, x1, x2)

inst_3346:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfe55;
op3val:0x401; valaddr_reg:x3; val_offset:10038*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10038*FLEN/8, x4, x1, x2)

inst_3347:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfe55;
op3val:0x8455; valaddr_reg:x3; val_offset:10041*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10041*FLEN/8, x4, x1, x2)

inst_3348:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfe55;
op3val:0x7bff; valaddr_reg:x3; val_offset:10044*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10044*FLEN/8, x4, x1, x2)

inst_3349:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfe55;
op3val:0xfbff; valaddr_reg:x3; val_offset:10047*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10047*FLEN/8, x4, x1, x2)

inst_3350:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfe55;
op3val:0x7c00; valaddr_reg:x3; val_offset:10050*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10050*FLEN/8, x4, x1, x2)

inst_3351:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfe55;
op3val:0xfc00; valaddr_reg:x3; val_offset:10053*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10053*FLEN/8, x4, x1, x2)

inst_3352:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfe55;
op3val:0x7e00; valaddr_reg:x3; val_offset:10056*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10056*FLEN/8, x4, x1, x2)

inst_3353:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfe55;
op3val:0xfe00; valaddr_reg:x3; val_offset:10059*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10059*FLEN/8, x4, x1, x2)

inst_3354:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfe55;
op3val:0x7e01; valaddr_reg:x3; val_offset:10062*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10062*FLEN/8, x4, x1, x2)

inst_3355:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfe55;
op3val:0xfe55; valaddr_reg:x3; val_offset:10065*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10065*FLEN/8, x4, x1, x2)

inst_3356:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfe55;
op3val:0x7c01; valaddr_reg:x3; val_offset:10068*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10068*FLEN/8, x4, x1, x2)

inst_3357:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfe55;
op3val:0xfd55; valaddr_reg:x3; val_offset:10071*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10071*FLEN/8, x4, x1, x2)

inst_3358:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfe55;
op3val:0x3c00; valaddr_reg:x3; val_offset:10074*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10074*FLEN/8, x4, x1, x2)

inst_3359:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x255 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfe55;
op3val:0xbc00; valaddr_reg:x3; val_offset:10077*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10077*FLEN/8, x4, x1, x2)

inst_3360:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7c01;
op3val:0x0; valaddr_reg:x3; val_offset:10080*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10080*FLEN/8, x4, x1, x2)

inst_3361:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7c01;
op3val:0x8000; valaddr_reg:x3; val_offset:10083*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10083*FLEN/8, x4, x1, x2)

inst_3362:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7c01;
op3val:0x1; valaddr_reg:x3; val_offset:10086*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10086*FLEN/8, x4, x1, x2)

inst_3363:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7c01;
op3val:0x8001; valaddr_reg:x3; val_offset:10089*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10089*FLEN/8, x4, x1, x2)

inst_3364:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7c01;
op3val:0x2; valaddr_reg:x3; val_offset:10092*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10092*FLEN/8, x4, x1, x2)

inst_3365:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7c01;
op3val:0x83fe; valaddr_reg:x3; val_offset:10095*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10095*FLEN/8, x4, x1, x2)

inst_3366:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7c01;
op3val:0x3ff; valaddr_reg:x3; val_offset:10098*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10098*FLEN/8, x4, x1, x2)

inst_3367:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7c01;
op3val:0x83ff; valaddr_reg:x3; val_offset:10101*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10101*FLEN/8, x4, x1, x2)

inst_3368:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7c01;
op3val:0x400; valaddr_reg:x3; val_offset:10104*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10104*FLEN/8, x4, x1, x2)

inst_3369:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7c01;
op3val:0x8400; valaddr_reg:x3; val_offset:10107*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10107*FLEN/8, x4, x1, x2)

inst_3370:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7c01;
op3val:0x401; valaddr_reg:x3; val_offset:10110*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10110*FLEN/8, x4, x1, x2)

inst_3371:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7c01;
op3val:0x8455; valaddr_reg:x3; val_offset:10113*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10113*FLEN/8, x4, x1, x2)

inst_3372:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7c01;
op3val:0x7bff; valaddr_reg:x3; val_offset:10116*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10116*FLEN/8, x4, x1, x2)

inst_3373:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7c01;
op3val:0xfbff; valaddr_reg:x3; val_offset:10119*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10119*FLEN/8, x4, x1, x2)

inst_3374:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7c01;
op3val:0x7c00; valaddr_reg:x3; val_offset:10122*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10122*FLEN/8, x4, x1, x2)

inst_3375:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7c01;
op3val:0xfc00; valaddr_reg:x3; val_offset:10125*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10125*FLEN/8, x4, x1, x2)

inst_3376:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7c01;
op3val:0x7e00; valaddr_reg:x3; val_offset:10128*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10128*FLEN/8, x4, x1, x2)

inst_3377:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7c01;
op3val:0xfe00; valaddr_reg:x3; val_offset:10131*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10131*FLEN/8, x4, x1, x2)

inst_3378:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7c01;
op3val:0x7e01; valaddr_reg:x3; val_offset:10134*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10134*FLEN/8, x4, x1, x2)

inst_3379:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7c01;
op3val:0xfe55; valaddr_reg:x3; val_offset:10137*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10137*FLEN/8, x4, x1, x2)

inst_3380:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7c01;
op3val:0x7c01; valaddr_reg:x3; val_offset:10140*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10140*FLEN/8, x4, x1, x2)

inst_3381:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7c01;
op3val:0xfd55; valaddr_reg:x3; val_offset:10143*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10143*FLEN/8, x4, x1, x2)

inst_3382:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7c01;
op3val:0x3c00; valaddr_reg:x3; val_offset:10146*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10146*FLEN/8, x4, x1, x2)

inst_3383:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x1f and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x7c01;
op3val:0xbc00; valaddr_reg:x3; val_offset:10149*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10149*FLEN/8, x4, x1, x2)

inst_3384:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfd55;
op3val:0x0; valaddr_reg:x3; val_offset:10152*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10152*FLEN/8, x4, x1, x2)

inst_3385:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfd55;
op3val:0x8000; valaddr_reg:x3; val_offset:10155*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10155*FLEN/8, x4, x1, x2)

inst_3386:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfd55;
op3val:0x1; valaddr_reg:x3; val_offset:10158*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10158*FLEN/8, x4, x1, x2)

inst_3387:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfd55;
op3val:0x8001; valaddr_reg:x3; val_offset:10161*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10161*FLEN/8, x4, x1, x2)

inst_3388:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfd55;
op3val:0x2; valaddr_reg:x3; val_offset:10164*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10164*FLEN/8, x4, x1, x2)

inst_3389:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfd55;
op3val:0x83fe; valaddr_reg:x3; val_offset:10167*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10167*FLEN/8, x4, x1, x2)

inst_3390:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfd55;
op3val:0x3ff; valaddr_reg:x3; val_offset:10170*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10170*FLEN/8, x4, x1, x2)

inst_3391:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfd55;
op3val:0x83ff; valaddr_reg:x3; val_offset:10173*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10173*FLEN/8, x4, x1, x2)

inst_3392:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfd55;
op3val:0x400; valaddr_reg:x3; val_offset:10176*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10176*FLEN/8, x4, x1, x2)

inst_3393:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfd55;
op3val:0x8400; valaddr_reg:x3; val_offset:10179*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10179*FLEN/8, x4, x1, x2)

inst_3394:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfd55;
op3val:0x401; valaddr_reg:x3; val_offset:10182*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10182*FLEN/8, x4, x1, x2)

inst_3395:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfd55;
op3val:0x8455; valaddr_reg:x3; val_offset:10185*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10185*FLEN/8, x4, x1, x2)

inst_3396:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfd55;
op3val:0x7bff; valaddr_reg:x3; val_offset:10188*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10188*FLEN/8, x4, x1, x2)

inst_3397:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfd55;
op3val:0xfbff; valaddr_reg:x3; val_offset:10191*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10191*FLEN/8, x4, x1, x2)

inst_3398:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfd55;
op3val:0x7c00; valaddr_reg:x3; val_offset:10194*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10194*FLEN/8, x4, x1, x2)

inst_3399:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfd55;
op3val:0xfc00; valaddr_reg:x3; val_offset:10197*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10197*FLEN/8, x4, x1, x2)

inst_3400:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfd55;
op3val:0x7e00; valaddr_reg:x3; val_offset:10200*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10200*FLEN/8, x4, x1, x2)

inst_3401:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfd55;
op3val:0xfe00; valaddr_reg:x3; val_offset:10203*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10203*FLEN/8, x4, x1, x2)

inst_3402:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfd55;
op3val:0x7e01; valaddr_reg:x3; val_offset:10206*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10206*FLEN/8, x4, x1, x2)

inst_3403:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfd55;
op3val:0xfe55; valaddr_reg:x3; val_offset:10209*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10209*FLEN/8, x4, x1, x2)

inst_3404:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfd55;
op3val:0x7c01; valaddr_reg:x3; val_offset:10212*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10212*FLEN/8, x4, x1, x2)

inst_3405:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfd55;
op3val:0xfd55; valaddr_reg:x3; val_offset:10215*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10215*FLEN/8, x4, x1, x2)

inst_3406:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfd55;
op3val:0x3c00; valaddr_reg:x3; val_offset:10218*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10218*FLEN/8, x4, x1, x2)

inst_3407:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x1f and fm2 == 0x155 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xfd55;
op3val:0xbc00; valaddr_reg:x3; val_offset:10221*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10221*FLEN/8, x4, x1, x2)

inst_3408:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x3c00;
op3val:0x0; valaddr_reg:x3; val_offset:10224*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10224*FLEN/8, x4, x1, x2)

inst_3409:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x3c00;
op3val:0x8000; valaddr_reg:x3; val_offset:10227*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10227*FLEN/8, x4, x1, x2)

inst_3410:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x3c00;
op3val:0x1; valaddr_reg:x3; val_offset:10230*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10230*FLEN/8, x4, x1, x2)

inst_3411:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x3c00;
op3val:0x8001; valaddr_reg:x3; val_offset:10233*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10233*FLEN/8, x4, x1, x2)

inst_3412:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x3c00;
op3val:0x2; valaddr_reg:x3; val_offset:10236*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10236*FLEN/8, x4, x1, x2)

inst_3413:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x3c00;
op3val:0x83fe; valaddr_reg:x3; val_offset:10239*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10239*FLEN/8, x4, x1, x2)

inst_3414:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x3c00;
op3val:0x3ff; valaddr_reg:x3; val_offset:10242*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10242*FLEN/8, x4, x1, x2)

inst_3415:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x3c00;
op3val:0x83ff; valaddr_reg:x3; val_offset:10245*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10245*FLEN/8, x4, x1, x2)

inst_3416:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x3c00;
op3val:0x400; valaddr_reg:x3; val_offset:10248*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10248*FLEN/8, x4, x1, x2)

inst_3417:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x3c00;
op3val:0x8400; valaddr_reg:x3; val_offset:10251*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10251*FLEN/8, x4, x1, x2)

inst_3418:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x3c00;
op3val:0x401; valaddr_reg:x3; val_offset:10254*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10254*FLEN/8, x4, x1, x2)

inst_3419:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x3c00;
op3val:0x8455; valaddr_reg:x3; val_offset:10257*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10257*FLEN/8, x4, x1, x2)

inst_3420:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x3c00;
op3val:0x7bff; valaddr_reg:x3; val_offset:10260*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10260*FLEN/8, x4, x1, x2)

inst_3421:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x3c00;
op3val:0xfbff; valaddr_reg:x3; val_offset:10263*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10263*FLEN/8, x4, x1, x2)

inst_3422:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x3c00;
op3val:0x7c00; valaddr_reg:x3; val_offset:10266*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10266*FLEN/8, x4, x1, x2)

inst_3423:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x3c00;
op3val:0xfc00; valaddr_reg:x3; val_offset:10269*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10269*FLEN/8, x4, x1, x2)

inst_3424:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x3c00;
op3val:0x7e00; valaddr_reg:x3; val_offset:10272*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10272*FLEN/8, x4, x1, x2)

inst_3425:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x3c00;
op3val:0xfe00; valaddr_reg:x3; val_offset:10275*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10275*FLEN/8, x4, x1, x2)

inst_3426:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x3c00;
op3val:0x7e01; valaddr_reg:x3; val_offset:10278*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10278*FLEN/8, x4, x1, x2)

inst_3427:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x3c00;
op3val:0xfe55; valaddr_reg:x3; val_offset:10281*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10281*FLEN/8, x4, x1, x2)

inst_3428:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x3c00;
op3val:0x7c01; valaddr_reg:x3; val_offset:10284*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10284*FLEN/8, x4, x1, x2)

inst_3429:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x3c00;
op3val:0xfd55; valaddr_reg:x3; val_offset:10287*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10287*FLEN/8, x4, x1, x2)

inst_3430:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x3c00;
op3val:0x3c00; valaddr_reg:x3; val_offset:10290*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10290*FLEN/8, x4, x1, x2)

inst_3431:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 0 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0x3c00;
op3val:0xbc00; valaddr_reg:x3; val_offset:10293*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10293*FLEN/8, x4, x1, x2)

inst_3432:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xbc00;
op3val:0x0; valaddr_reg:x3; val_offset:10296*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10296*FLEN/8, x4, x1, x2)

inst_3433:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xbc00;
op3val:0x8000; valaddr_reg:x3; val_offset:10299*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10299*FLEN/8, x4, x1, x2)

inst_3434:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xbc00;
op3val:0x1; valaddr_reg:x3; val_offset:10302*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10302*FLEN/8, x4, x1, x2)

inst_3435:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xbc00;
op3val:0x8001; valaddr_reg:x3; val_offset:10305*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10305*FLEN/8, x4, x1, x2)

inst_3436:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xbc00;
op3val:0x2; valaddr_reg:x3; val_offset:10308*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10308*FLEN/8, x4, x1, x2)

inst_3437:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xbc00;
op3val:0x83fe; valaddr_reg:x3; val_offset:10311*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10311*FLEN/8, x4, x1, x2)

inst_3438:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xbc00;
op3val:0x3ff; valaddr_reg:x3; val_offset:10314*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10314*FLEN/8, x4, x1, x2)

inst_3439:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xbc00;
op3val:0x83ff; valaddr_reg:x3; val_offset:10317*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10317*FLEN/8, x4, x1, x2)

inst_3440:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xbc00;
op3val:0x400; valaddr_reg:x3; val_offset:10320*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10320*FLEN/8, x4, x1, x2)

inst_3441:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xbc00;
op3val:0x8400; valaddr_reg:x3; val_offset:10323*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10323*FLEN/8, x4, x1, x2)

inst_3442:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xbc00;
op3val:0x401; valaddr_reg:x3; val_offset:10326*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10326*FLEN/8, x4, x1, x2)

inst_3443:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xbc00;
op3val:0x8455; valaddr_reg:x3; val_offset:10329*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10329*FLEN/8, x4, x1, x2)

inst_3444:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xbc00;
op3val:0x7bff; valaddr_reg:x3; val_offset:10332*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10332*FLEN/8, x4, x1, x2)

inst_3445:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xbc00;
op3val:0xfbff; valaddr_reg:x3; val_offset:10335*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10335*FLEN/8, x4, x1, x2)

inst_3446:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xbc00;
op3val:0x7c00; valaddr_reg:x3; val_offset:10338*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10338*FLEN/8, x4, x1, x2)

inst_3447:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xbc00;
op3val:0xfc00; valaddr_reg:x3; val_offset:10341*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10341*FLEN/8, x4, x1, x2)

inst_3448:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xbc00;
op3val:0x7e00; valaddr_reg:x3; val_offset:10344*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10344*FLEN/8, x4, x1, x2)

inst_3449:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xbc00;
op3val:0xfe00; valaddr_reg:x3; val_offset:10347*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10347*FLEN/8, x4, x1, x2)

inst_3450:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xbc00;
op3val:0x7e01; valaddr_reg:x3; val_offset:10350*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10350*FLEN/8, x4, x1, x2)

inst_3451:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xbc00;
op3val:0xfe55; valaddr_reg:x3; val_offset:10353*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10353*FLEN/8, x4, x1, x2)

inst_3452:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xbc00;
op3val:0x7c01; valaddr_reg:x3; val_offset:10356*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10356*FLEN/8, x4, x1, x2)

inst_3453:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xbc00;
op3val:0xfd55; valaddr_reg:x3; val_offset:10359*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10359*FLEN/8, x4, x1, x2)

inst_3454:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xbc00;
op3val:0x3c00; valaddr_reg:x3; val_offset:10362*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10362*FLEN/8, x4, x1, x2)

inst_3455:
// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x83fe; op2val:0xbc00;
op3val:0xbc00; valaddr_reg:x3; val_offset:10365*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10365*FLEN/8, x4, x1, x2)

RVTEST_SIGBASE(x1,signature_x1_28)
inst_3456:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:10368*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10368*FLEN/8, x4, x1, x2)

inst_3457:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x0;
op3val:0x8000; valaddr_reg:x3; val_offset:10371*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10371*FLEN/8, x4, x1, x2)

inst_3458:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x0;
op3val:0x1; valaddr_reg:x3; val_offset:10374*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10374*FLEN/8, x4, x1, x2)

inst_3459:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x0;
op3val:0x8001; valaddr_reg:x3; val_offset:10377*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10377*FLEN/8, x4, x1, x2)

inst_3460:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x0;
op3val:0x2; valaddr_reg:x3; val_offset:10380*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10380*FLEN/8, x4, x1, x2)

inst_3461:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x0;
op3val:0x83fe; valaddr_reg:x3; val_offset:10383*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10383*FLEN/8, x4, x1, x2)

inst_3462:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x0;
op3val:0x3ff; valaddr_reg:x3; val_offset:10386*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10386*FLEN/8, x4, x1, x2)

inst_3463:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x0;
op3val:0x83ff; valaddr_reg:x3; val_offset:10389*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10389*FLEN/8, x4, x1, x2)

inst_3464:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x0;
op3val:0x400; valaddr_reg:x3; val_offset:10392*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10392*FLEN/8, x4, x1, x2)

inst_3465:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x0;
op3val:0x8400; valaddr_reg:x3; val_offset:10395*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10395*FLEN/8, x4, x1, x2)

inst_3466:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x0;
op3val:0x401; valaddr_reg:x3; val_offset:10398*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10398*FLEN/8, x4, x1, x2)

inst_3467:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x0;
op3val:0x8455; valaddr_reg:x3; val_offset:10401*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10401*FLEN/8, x4, x1, x2)

inst_3468:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x0;
op3val:0x7bff; valaddr_reg:x3; val_offset:10404*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10404*FLEN/8, x4, x1, x2)

inst_3469:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x0;
op3val:0xfbff; valaddr_reg:x3; val_offset:10407*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10407*FLEN/8, x4, x1, x2)

inst_3470:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x0;
op3val:0x7c00; valaddr_reg:x3; val_offset:10410*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10410*FLEN/8, x4, x1, x2)

inst_3471:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x0;
op3val:0xfc00; valaddr_reg:x3; val_offset:10413*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10413*FLEN/8, x4, x1, x2)

inst_3472:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x0;
op3val:0x7e00; valaddr_reg:x3; val_offset:10416*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10416*FLEN/8, x4, x1, x2)

inst_3473:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x0;
op3val:0xfe00; valaddr_reg:x3; val_offset:10419*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10419*FLEN/8, x4, x1, x2)

inst_3474:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x0;
op3val:0x7e01; valaddr_reg:x3; val_offset:10422*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10422*FLEN/8, x4, x1, x2)

inst_3475:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x0;
op3val:0xfe55; valaddr_reg:x3; val_offset:10425*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10425*FLEN/8, x4, x1, x2)

inst_3476:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x0;
op3val:0x7c01; valaddr_reg:x3; val_offset:10428*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10428*FLEN/8, x4, x1, x2)

inst_3477:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x0;
op3val:0xfd55; valaddr_reg:x3; val_offset:10431*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10431*FLEN/8, x4, x1, x2)

inst_3478:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x0;
op3val:0x3c00; valaddr_reg:x3; val_offset:10434*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10434*FLEN/8, x4, x1, x2)

inst_3479:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x0;
op3val:0xbc00; valaddr_reg:x3; val_offset:10437*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10437*FLEN/8, x4, x1, x2)

inst_3480:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8000;
op3val:0x0; valaddr_reg:x3; val_offset:10440*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10440*FLEN/8, x4, x1, x2)

inst_3481:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8000;
op3val:0x8000; valaddr_reg:x3; val_offset:10443*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10443*FLEN/8, x4, x1, x2)

inst_3482:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8000;
op3val:0x1; valaddr_reg:x3; val_offset:10446*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10446*FLEN/8, x4, x1, x2)

inst_3483:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8000;
op3val:0x8001; valaddr_reg:x3; val_offset:10449*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10449*FLEN/8, x4, x1, x2)

inst_3484:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8000;
op3val:0x2; valaddr_reg:x3; val_offset:10452*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10452*FLEN/8, x4, x1, x2)

inst_3485:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8000;
op3val:0x83fe; valaddr_reg:x3; val_offset:10455*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10455*FLEN/8, x4, x1, x2)

inst_3486:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8000;
op3val:0x3ff; valaddr_reg:x3; val_offset:10458*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10458*FLEN/8, x4, x1, x2)

inst_3487:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8000;
op3val:0x83ff; valaddr_reg:x3; val_offset:10461*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10461*FLEN/8, x4, x1, x2)

inst_3488:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8000;
op3val:0x400; valaddr_reg:x3; val_offset:10464*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10464*FLEN/8, x4, x1, x2)

inst_3489:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8000;
op3val:0x8400; valaddr_reg:x3; val_offset:10467*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10467*FLEN/8, x4, x1, x2)

inst_3490:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8000;
op3val:0x401; valaddr_reg:x3; val_offset:10470*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10470*FLEN/8, x4, x1, x2)

inst_3491:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8000;
op3val:0x8455; valaddr_reg:x3; val_offset:10473*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10473*FLEN/8, x4, x1, x2)

inst_3492:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8000;
op3val:0x7bff; valaddr_reg:x3; val_offset:10476*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10476*FLEN/8, x4, x1, x2)

inst_3493:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8000;
op3val:0xfbff; valaddr_reg:x3; val_offset:10479*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10479*FLEN/8, x4, x1, x2)

inst_3494:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8000;
op3val:0x7c00; valaddr_reg:x3; val_offset:10482*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10482*FLEN/8, x4, x1, x2)

inst_3495:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8000;
op3val:0xfc00; valaddr_reg:x3; val_offset:10485*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10485*FLEN/8, x4, x1, x2)

inst_3496:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8000;
op3val:0x7e00; valaddr_reg:x3; val_offset:10488*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10488*FLEN/8, x4, x1, x2)

inst_3497:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8000;
op3val:0xfe00; valaddr_reg:x3; val_offset:10491*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10491*FLEN/8, x4, x1, x2)

inst_3498:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8000;
op3val:0x7e01; valaddr_reg:x3; val_offset:10494*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10494*FLEN/8, x4, x1, x2)

inst_3499:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8000;
op3val:0xfe55; valaddr_reg:x3; val_offset:10497*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10497*FLEN/8, x4, x1, x2)

inst_3500:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8000;
op3val:0x7c01; valaddr_reg:x3; val_offset:10500*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10500*FLEN/8, x4, x1, x2)

inst_3501:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8000;
op3val:0xfd55; valaddr_reg:x3; val_offset:10503*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10503*FLEN/8, x4, x1, x2)

inst_3502:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8000;
op3val:0x3c00; valaddr_reg:x3; val_offset:10506*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10506*FLEN/8, x4, x1, x2)

inst_3503:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8000;
op3val:0xbc00; valaddr_reg:x3; val_offset:10509*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10509*FLEN/8, x4, x1, x2)

inst_3504:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x1;
op3val:0x0; valaddr_reg:x3; val_offset:10512*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10512*FLEN/8, x4, x1, x2)

inst_3505:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x1;
op3val:0x8000; valaddr_reg:x3; val_offset:10515*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10515*FLEN/8, x4, x1, x2)

inst_3506:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x1;
op3val:0x1; valaddr_reg:x3; val_offset:10518*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10518*FLEN/8, x4, x1, x2)

inst_3507:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x1;
op3val:0x8001; valaddr_reg:x3; val_offset:10521*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10521*FLEN/8, x4, x1, x2)

inst_3508:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x1;
op3val:0x2; valaddr_reg:x3; val_offset:10524*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10524*FLEN/8, x4, x1, x2)

inst_3509:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x1;
op3val:0x83fe; valaddr_reg:x3; val_offset:10527*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10527*FLEN/8, x4, x1, x2)

inst_3510:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x1;
op3val:0x3ff; valaddr_reg:x3; val_offset:10530*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10530*FLEN/8, x4, x1, x2)

inst_3511:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x1;
op3val:0x83ff; valaddr_reg:x3; val_offset:10533*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10533*FLEN/8, x4, x1, x2)

inst_3512:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x1;
op3val:0x400; valaddr_reg:x3; val_offset:10536*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10536*FLEN/8, x4, x1, x2)

inst_3513:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x1;
op3val:0x8400; valaddr_reg:x3; val_offset:10539*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10539*FLEN/8, x4, x1, x2)

inst_3514:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x1;
op3val:0x401; valaddr_reg:x3; val_offset:10542*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10542*FLEN/8, x4, x1, x2)

inst_3515:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x1;
op3val:0x8455; valaddr_reg:x3; val_offset:10545*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10545*FLEN/8, x4, x1, x2)

inst_3516:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x1;
op3val:0x7bff; valaddr_reg:x3; val_offset:10548*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10548*FLEN/8, x4, x1, x2)

inst_3517:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x1;
op3val:0xfbff; valaddr_reg:x3; val_offset:10551*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10551*FLEN/8, x4, x1, x2)

inst_3518:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x1;
op3val:0x7c00; valaddr_reg:x3; val_offset:10554*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10554*FLEN/8, x4, x1, x2)

inst_3519:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x1;
op3val:0xfc00; valaddr_reg:x3; val_offset:10557*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10557*FLEN/8, x4, x1, x2)

inst_3520:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x1;
op3val:0x7e00; valaddr_reg:x3; val_offset:10560*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10560*FLEN/8, x4, x1, x2)

inst_3521:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x1;
op3val:0xfe00; valaddr_reg:x3; val_offset:10563*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10563*FLEN/8, x4, x1, x2)

inst_3522:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x1;
op3val:0x7e01; valaddr_reg:x3; val_offset:10566*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10566*FLEN/8, x4, x1, x2)

inst_3523:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x1;
op3val:0xfe55; valaddr_reg:x3; val_offset:10569*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10569*FLEN/8, x4, x1, x2)

inst_3524:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x1;
op3val:0x7c01; valaddr_reg:x3; val_offset:10572*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10572*FLEN/8, x4, x1, x2)

inst_3525:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x1;
op3val:0xfd55; valaddr_reg:x3; val_offset:10575*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10575*FLEN/8, x4, x1, x2)

inst_3526:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x1;
op3val:0x3c00; valaddr_reg:x3; val_offset:10578*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10578*FLEN/8, x4, x1, x2)

inst_3527:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x1;
op3val:0xbc00; valaddr_reg:x3; val_offset:10581*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10581*FLEN/8, x4, x1, x2)

inst_3528:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8001;
op3val:0x0; valaddr_reg:x3; val_offset:10584*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10584*FLEN/8, x4, x1, x2)

inst_3529:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8001;
op3val:0x8000; valaddr_reg:x3; val_offset:10587*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10587*FLEN/8, x4, x1, x2)

inst_3530:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8001;
op3val:0x1; valaddr_reg:x3; val_offset:10590*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10590*FLEN/8, x4, x1, x2)

inst_3531:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8001;
op3val:0x8001; valaddr_reg:x3; val_offset:10593*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10593*FLEN/8, x4, x1, x2)

inst_3532:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8001;
op3val:0x2; valaddr_reg:x3; val_offset:10596*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10596*FLEN/8, x4, x1, x2)

inst_3533:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8001;
op3val:0x83fe; valaddr_reg:x3; val_offset:10599*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10599*FLEN/8, x4, x1, x2)

inst_3534:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8001;
op3val:0x3ff; valaddr_reg:x3; val_offset:10602*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10602*FLEN/8, x4, x1, x2)

inst_3535:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8001;
op3val:0x83ff; valaddr_reg:x3; val_offset:10605*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10605*FLEN/8, x4, x1, x2)

inst_3536:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8001;
op3val:0x400; valaddr_reg:x3; val_offset:10608*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10608*FLEN/8, x4, x1, x2)

inst_3537:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8001;
op3val:0x8400; valaddr_reg:x3; val_offset:10611*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10611*FLEN/8, x4, x1, x2)

inst_3538:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8001;
op3val:0x401; valaddr_reg:x3; val_offset:10614*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10614*FLEN/8, x4, x1, x2)

inst_3539:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8001;
op3val:0x8455; valaddr_reg:x3; val_offset:10617*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10617*FLEN/8, x4, x1, x2)

inst_3540:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8001;
op3val:0x7bff; valaddr_reg:x3; val_offset:10620*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10620*FLEN/8, x4, x1, x2)

inst_3541:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8001;
op3val:0xfbff; valaddr_reg:x3; val_offset:10623*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10623*FLEN/8, x4, x1, x2)

inst_3542:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8001;
op3val:0x7c00; valaddr_reg:x3; val_offset:10626*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10626*FLEN/8, x4, x1, x2)

inst_3543:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8001;
op3val:0xfc00; valaddr_reg:x3; val_offset:10629*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10629*FLEN/8, x4, x1, x2)

inst_3544:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8001;
op3val:0x7e00; valaddr_reg:x3; val_offset:10632*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10632*FLEN/8, x4, x1, x2)

inst_3545:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8001;
op3val:0xfe00; valaddr_reg:x3; val_offset:10635*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10635*FLEN/8, x4, x1, x2)

inst_3546:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8001;
op3val:0x7e01; valaddr_reg:x3; val_offset:10638*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10638*FLEN/8, x4, x1, x2)

inst_3547:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8001;
op3val:0xfe55; valaddr_reg:x3; val_offset:10641*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10641*FLEN/8, x4, x1, x2)

inst_3548:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8001;
op3val:0x7c01; valaddr_reg:x3; val_offset:10644*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10644*FLEN/8, x4, x1, x2)

inst_3549:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8001;
op3val:0xfd55; valaddr_reg:x3; val_offset:10647*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10647*FLEN/8, x4, x1, x2)

inst_3550:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8001;
op3val:0x3c00; valaddr_reg:x3; val_offset:10650*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10650*FLEN/8, x4, x1, x2)

inst_3551:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8001;
op3val:0xbc00; valaddr_reg:x3; val_offset:10653*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10653*FLEN/8, x4, x1, x2)

inst_3552:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x2;
op3val:0x0; valaddr_reg:x3; val_offset:10656*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10656*FLEN/8, x4, x1, x2)

inst_3553:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x2;
op3val:0x8000; valaddr_reg:x3; val_offset:10659*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10659*FLEN/8, x4, x1, x2)

inst_3554:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x2;
op3val:0x1; valaddr_reg:x3; val_offset:10662*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10662*FLEN/8, x4, x1, x2)

inst_3555:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x2;
op3val:0x8001; valaddr_reg:x3; val_offset:10665*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10665*FLEN/8, x4, x1, x2)

inst_3556:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x2;
op3val:0x2; valaddr_reg:x3; val_offset:10668*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10668*FLEN/8, x4, x1, x2)

inst_3557:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x2;
op3val:0x83fe; valaddr_reg:x3; val_offset:10671*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10671*FLEN/8, x4, x1, x2)

inst_3558:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x2;
op3val:0x3ff; valaddr_reg:x3; val_offset:10674*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10674*FLEN/8, x4, x1, x2)

inst_3559:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x2;
op3val:0x83ff; valaddr_reg:x3; val_offset:10677*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10677*FLEN/8, x4, x1, x2)

inst_3560:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x2;
op3val:0x400; valaddr_reg:x3; val_offset:10680*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10680*FLEN/8, x4, x1, x2)

inst_3561:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x2;
op3val:0x8400; valaddr_reg:x3; val_offset:10683*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10683*FLEN/8, x4, x1, x2)

inst_3562:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x2;
op3val:0x401; valaddr_reg:x3; val_offset:10686*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10686*FLEN/8, x4, x1, x2)

inst_3563:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x2;
op3val:0x8455; valaddr_reg:x3; val_offset:10689*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10689*FLEN/8, x4, x1, x2)

inst_3564:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x2;
op3val:0x7bff; valaddr_reg:x3; val_offset:10692*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10692*FLEN/8, x4, x1, x2)

inst_3565:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x2;
op3val:0xfbff; valaddr_reg:x3; val_offset:10695*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10695*FLEN/8, x4, x1, x2)

inst_3566:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x2;
op3val:0x7c00; valaddr_reg:x3; val_offset:10698*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10698*FLEN/8, x4, x1, x2)

inst_3567:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x2;
op3val:0xfc00; valaddr_reg:x3; val_offset:10701*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10701*FLEN/8, x4, x1, x2)

inst_3568:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x2;
op3val:0x7e00; valaddr_reg:x3; val_offset:10704*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10704*FLEN/8, x4, x1, x2)

inst_3569:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x2;
op3val:0xfe00; valaddr_reg:x3; val_offset:10707*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10707*FLEN/8, x4, x1, x2)

inst_3570:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x2;
op3val:0x7e01; valaddr_reg:x3; val_offset:10710*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10710*FLEN/8, x4, x1, x2)

inst_3571:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x2;
op3val:0xfe55; valaddr_reg:x3; val_offset:10713*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10713*FLEN/8, x4, x1, x2)

inst_3572:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x2;
op3val:0x7c01; valaddr_reg:x3; val_offset:10716*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10716*FLEN/8, x4, x1, x2)

inst_3573:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x2;
op3val:0xfd55; valaddr_reg:x3; val_offset:10719*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10719*FLEN/8, x4, x1, x2)

inst_3574:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x2;
op3val:0x3c00; valaddr_reg:x3; val_offset:10722*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10722*FLEN/8, x4, x1, x2)

inst_3575:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x2;
op3val:0xbc00; valaddr_reg:x3; val_offset:10725*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10725*FLEN/8, x4, x1, x2)

inst_3576:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x83fe;
op3val:0x0; valaddr_reg:x3; val_offset:10728*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10728*FLEN/8, x4, x1, x2)

inst_3577:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x83fe;
op3val:0x8000; valaddr_reg:x3; val_offset:10731*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10731*FLEN/8, x4, x1, x2)

inst_3578:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x83fe;
op3val:0x1; valaddr_reg:x3; val_offset:10734*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10734*FLEN/8, x4, x1, x2)

inst_3579:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x83fe;
op3val:0x8001; valaddr_reg:x3; val_offset:10737*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10737*FLEN/8, x4, x1, x2)

inst_3580:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x83fe;
op3val:0x2; valaddr_reg:x3; val_offset:10740*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10740*FLEN/8, x4, x1, x2)

inst_3581:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x83fe;
op3val:0x83fe; valaddr_reg:x3; val_offset:10743*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10743*FLEN/8, x4, x1, x2)

inst_3582:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x83fe;
op3val:0x3ff; valaddr_reg:x3; val_offset:10746*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10746*FLEN/8, x4, x1, x2)

inst_3583:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x83fe;
op3val:0x83ff; valaddr_reg:x3; val_offset:10749*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10749*FLEN/8, x4, x1, x2)

RVTEST_SIGBASE(x1,signature_x1_29)
inst_3584:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x83fe;
op3val:0x400; valaddr_reg:x3; val_offset:10752*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10752*FLEN/8, x4, x1, x2)

inst_3585:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x83fe;
op3val:0x8400; valaddr_reg:x3; val_offset:10755*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10755*FLEN/8, x4, x1, x2)

inst_3586:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x83fe;
op3val:0x401; valaddr_reg:x3; val_offset:10758*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10758*FLEN/8, x4, x1, x2)

inst_3587:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x83fe;
op3val:0x8455; valaddr_reg:x3; val_offset:10761*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10761*FLEN/8, x4, x1, x2)

inst_3588:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x83fe;
op3val:0x7bff; valaddr_reg:x3; val_offset:10764*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10764*FLEN/8, x4, x1, x2)

inst_3589:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x83fe;
op3val:0xfbff; valaddr_reg:x3; val_offset:10767*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10767*FLEN/8, x4, x1, x2)

inst_3590:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x83fe;
op3val:0x7c00; valaddr_reg:x3; val_offset:10770*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10770*FLEN/8, x4, x1, x2)

inst_3591:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x83fe;
op3val:0xfc00; valaddr_reg:x3; val_offset:10773*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10773*FLEN/8, x4, x1, x2)

inst_3592:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x83fe;
op3val:0x7e00; valaddr_reg:x3; val_offset:10776*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10776*FLEN/8, x4, x1, x2)

inst_3593:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x83fe;
op3val:0xfe00; valaddr_reg:x3; val_offset:10779*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10779*FLEN/8, x4, x1, x2)

inst_3594:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x83fe;
op3val:0x7e01; valaddr_reg:x3; val_offset:10782*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10782*FLEN/8, x4, x1, x2)

inst_3595:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x83fe;
op3val:0xfe55; valaddr_reg:x3; val_offset:10785*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10785*FLEN/8, x4, x1, x2)

inst_3596:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x83fe;
op3val:0x7c01; valaddr_reg:x3; val_offset:10788*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10788*FLEN/8, x4, x1, x2)

inst_3597:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x83fe;
op3val:0xfd55; valaddr_reg:x3; val_offset:10791*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10791*FLEN/8, x4, x1, x2)

inst_3598:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x83fe;
op3val:0x3c00; valaddr_reg:x3; val_offset:10794*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10794*FLEN/8, x4, x1, x2)

inst_3599:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3fe and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x83fe;
op3val:0xbc00; valaddr_reg:x3; val_offset:10797*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10797*FLEN/8, x4, x1, x2)

inst_3600:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x3ff;
op3val:0x0; valaddr_reg:x3; val_offset:10800*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10800*FLEN/8, x4, x1, x2)

inst_3601:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x3ff;
op3val:0x8000; valaddr_reg:x3; val_offset:10803*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10803*FLEN/8, x4, x1, x2)

inst_3602:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x3ff;
op3val:0x1; valaddr_reg:x3; val_offset:10806*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10806*FLEN/8, x4, x1, x2)

inst_3603:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x3ff;
op3val:0x8001; valaddr_reg:x3; val_offset:10809*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10809*FLEN/8, x4, x1, x2)

inst_3604:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x3ff;
op3val:0x2; valaddr_reg:x3; val_offset:10812*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10812*FLEN/8, x4, x1, x2)

inst_3605:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x3ff;
op3val:0x83fe; valaddr_reg:x3; val_offset:10815*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10815*FLEN/8, x4, x1, x2)

inst_3606:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x3ff;
op3val:0x3ff; valaddr_reg:x3; val_offset:10818*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10818*FLEN/8, x4, x1, x2)

inst_3607:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x3ff;
op3val:0x83ff; valaddr_reg:x3; val_offset:10821*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10821*FLEN/8, x4, x1, x2)

inst_3608:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x3ff;
op3val:0x400; valaddr_reg:x3; val_offset:10824*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10824*FLEN/8, x4, x1, x2)

inst_3609:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x3ff;
op3val:0x8400; valaddr_reg:x3; val_offset:10827*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10827*FLEN/8, x4, x1, x2)

inst_3610:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x3ff;
op3val:0x401; valaddr_reg:x3; val_offset:10830*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10830*FLEN/8, x4, x1, x2)

inst_3611:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x3ff;
op3val:0x8455; valaddr_reg:x3; val_offset:10833*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10833*FLEN/8, x4, x1, x2)

inst_3612:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x3ff;
op3val:0x7bff; valaddr_reg:x3; val_offset:10836*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10836*FLEN/8, x4, x1, x2)

inst_3613:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x3ff;
op3val:0xfbff; valaddr_reg:x3; val_offset:10839*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10839*FLEN/8, x4, x1, x2)

inst_3614:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x3ff;
op3val:0x7c00; valaddr_reg:x3; val_offset:10842*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10842*FLEN/8, x4, x1, x2)

inst_3615:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x3ff;
op3val:0xfc00; valaddr_reg:x3; val_offset:10845*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10845*FLEN/8, x4, x1, x2)

inst_3616:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x3ff;
op3val:0x7e00; valaddr_reg:x3; val_offset:10848*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10848*FLEN/8, x4, x1, x2)

inst_3617:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x3ff;
op3val:0xfe00; valaddr_reg:x3; val_offset:10851*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10851*FLEN/8, x4, x1, x2)

inst_3618:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x3ff;
op3val:0x7e01; valaddr_reg:x3; val_offset:10854*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10854*FLEN/8, x4, x1, x2)

inst_3619:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x3ff;
op3val:0xfe55; valaddr_reg:x3; val_offset:10857*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10857*FLEN/8, x4, x1, x2)

inst_3620:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x3ff;
op3val:0x7c01; valaddr_reg:x3; val_offset:10860*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10860*FLEN/8, x4, x1, x2)

inst_3621:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x3ff;
op3val:0xfd55; valaddr_reg:x3; val_offset:10863*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10863*FLEN/8, x4, x1, x2)

inst_3622:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x3ff;
op3val:0x3c00; valaddr_reg:x3; val_offset:10866*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10866*FLEN/8, x4, x1, x2)

inst_3623:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x3ff;
op3val:0xbc00; valaddr_reg:x3; val_offset:10869*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10869*FLEN/8, x4, x1, x2)

inst_3624:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x83ff;
op3val:0x0; valaddr_reg:x3; val_offset:10872*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10872*FLEN/8, x4, x1, x2)

inst_3625:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x83ff;
op3val:0x8000; valaddr_reg:x3; val_offset:10875*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10875*FLEN/8, x4, x1, x2)

inst_3626:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x83ff;
op3val:0x1; valaddr_reg:x3; val_offset:10878*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10878*FLEN/8, x4, x1, x2)

inst_3627:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x83ff;
op3val:0x8001; valaddr_reg:x3; val_offset:10881*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10881*FLEN/8, x4, x1, x2)

inst_3628:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x83ff;
op3val:0x2; valaddr_reg:x3; val_offset:10884*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10884*FLEN/8, x4, x1, x2)

inst_3629:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x83ff;
op3val:0x83fe; valaddr_reg:x3; val_offset:10887*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10887*FLEN/8, x4, x1, x2)

inst_3630:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x83ff;
op3val:0x3ff; valaddr_reg:x3; val_offset:10890*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10890*FLEN/8, x4, x1, x2)

inst_3631:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x83ff;
op3val:0x83ff; valaddr_reg:x3; val_offset:10893*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10893*FLEN/8, x4, x1, x2)

inst_3632:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x83ff;
op3val:0x400; valaddr_reg:x3; val_offset:10896*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10896*FLEN/8, x4, x1, x2)

inst_3633:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x83ff;
op3val:0x8400; valaddr_reg:x3; val_offset:10899*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10899*FLEN/8, x4, x1, x2)

inst_3634:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x83ff;
op3val:0x401; valaddr_reg:x3; val_offset:10902*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10902*FLEN/8, x4, x1, x2)

inst_3635:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x83ff;
op3val:0x8455; valaddr_reg:x3; val_offset:10905*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10905*FLEN/8, x4, x1, x2)

inst_3636:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x83ff;
op3val:0x7bff; valaddr_reg:x3; val_offset:10908*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10908*FLEN/8, x4, x1, x2)

inst_3637:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x83ff;
op3val:0xfbff; valaddr_reg:x3; val_offset:10911*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10911*FLEN/8, x4, x1, x2)

inst_3638:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x83ff;
op3val:0x7c00; valaddr_reg:x3; val_offset:10914*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10914*FLEN/8, x4, x1, x2)

inst_3639:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x83ff;
op3val:0xfc00; valaddr_reg:x3; val_offset:10917*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10917*FLEN/8, x4, x1, x2)

inst_3640:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x83ff;
op3val:0x7e00; valaddr_reg:x3; val_offset:10920*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10920*FLEN/8, x4, x1, x2)

inst_3641:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x83ff;
op3val:0xfe00; valaddr_reg:x3; val_offset:10923*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10923*FLEN/8, x4, x1, x2)

inst_3642:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x83ff;
op3val:0x7e01; valaddr_reg:x3; val_offset:10926*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10926*FLEN/8, x4, x1, x2)

inst_3643:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x83ff;
op3val:0xfe55; valaddr_reg:x3; val_offset:10929*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10929*FLEN/8, x4, x1, x2)

inst_3644:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x83ff;
op3val:0x7c01; valaddr_reg:x3; val_offset:10932*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10932*FLEN/8, x4, x1, x2)

inst_3645:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x83ff;
op3val:0xfd55; valaddr_reg:x3; val_offset:10935*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10935*FLEN/8, x4, x1, x2)

inst_3646:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x83ff;
op3val:0x3c00; valaddr_reg:x3; val_offset:10938*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10938*FLEN/8, x4, x1, x2)

inst_3647:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x83ff;
op3val:0xbc00; valaddr_reg:x3; val_offset:10941*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10941*FLEN/8, x4, x1, x2)

inst_3648:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x400;
op3val:0x0; valaddr_reg:x3; val_offset:10944*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10944*FLEN/8, x4, x1, x2)

inst_3649:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x400;
op3val:0x8000; valaddr_reg:x3; val_offset:10947*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10947*FLEN/8, x4, x1, x2)

inst_3650:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x400;
op3val:0x1; valaddr_reg:x3; val_offset:10950*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10950*FLEN/8, x4, x1, x2)

inst_3651:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x400;
op3val:0x8001; valaddr_reg:x3; val_offset:10953*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10953*FLEN/8, x4, x1, x2)

inst_3652:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x400;
op3val:0x2; valaddr_reg:x3; val_offset:10956*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10956*FLEN/8, x4, x1, x2)

inst_3653:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x400;
op3val:0x83fe; valaddr_reg:x3; val_offset:10959*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10959*FLEN/8, x4, x1, x2)

inst_3654:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x400;
op3val:0x3ff; valaddr_reg:x3; val_offset:10962*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10962*FLEN/8, x4, x1, x2)

inst_3655:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x400;
op3val:0x83ff; valaddr_reg:x3; val_offset:10965*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10965*FLEN/8, x4, x1, x2)

inst_3656:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x400;
op3val:0x400; valaddr_reg:x3; val_offset:10968*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10968*FLEN/8, x4, x1, x2)

inst_3657:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x400;
op3val:0x8400; valaddr_reg:x3; val_offset:10971*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10971*FLEN/8, x4, x1, x2)

inst_3658:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x400;
op3val:0x401; valaddr_reg:x3; val_offset:10974*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10974*FLEN/8, x4, x1, x2)

inst_3659:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x400;
op3val:0x8455; valaddr_reg:x3; val_offset:10977*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10977*FLEN/8, x4, x1, x2)

inst_3660:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x400;
op3val:0x7bff; valaddr_reg:x3; val_offset:10980*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10980*FLEN/8, x4, x1, x2)

inst_3661:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x400;
op3val:0xfbff; valaddr_reg:x3; val_offset:10983*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10983*FLEN/8, x4, x1, x2)

inst_3662:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x400;
op3val:0x7c00; valaddr_reg:x3; val_offset:10986*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10986*FLEN/8, x4, x1, x2)

inst_3663:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x400;
op3val:0xfc00; valaddr_reg:x3; val_offset:10989*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10989*FLEN/8, x4, x1, x2)

inst_3664:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x400;
op3val:0x7e00; valaddr_reg:x3; val_offset:10992*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10992*FLEN/8, x4, x1, x2)

inst_3665:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x400;
op3val:0xfe00; valaddr_reg:x3; val_offset:10995*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10995*FLEN/8, x4, x1, x2)

inst_3666:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x400;
op3val:0x7e01; valaddr_reg:x3; val_offset:10998*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 10998*FLEN/8, x4, x1, x2)

inst_3667:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x400;
op3val:0xfe55; valaddr_reg:x3; val_offset:11001*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11001*FLEN/8, x4, x1, x2)

inst_3668:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x400;
op3val:0x7c01; valaddr_reg:x3; val_offset:11004*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11004*FLEN/8, x4, x1, x2)

inst_3669:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x400;
op3val:0xfd55; valaddr_reg:x3; val_offset:11007*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11007*FLEN/8, x4, x1, x2)

inst_3670:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x400;
op3val:0x3c00; valaddr_reg:x3; val_offset:11010*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11010*FLEN/8, x4, x1, x2)

inst_3671:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x400;
op3val:0xbc00; valaddr_reg:x3; val_offset:11013*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11013*FLEN/8, x4, x1, x2)

inst_3672:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8400;
op3val:0x0; valaddr_reg:x3; val_offset:11016*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11016*FLEN/8, x4, x1, x2)

inst_3673:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8400;
op3val:0x8000; valaddr_reg:x3; val_offset:11019*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11019*FLEN/8, x4, x1, x2)

inst_3674:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8400;
op3val:0x1; valaddr_reg:x3; val_offset:11022*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11022*FLEN/8, x4, x1, x2)

inst_3675:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8400;
op3val:0x8001; valaddr_reg:x3; val_offset:11025*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11025*FLEN/8, x4, x1, x2)

inst_3676:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8400;
op3val:0x2; valaddr_reg:x3; val_offset:11028*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11028*FLEN/8, x4, x1, x2)

inst_3677:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8400;
op3val:0x83fe; valaddr_reg:x3; val_offset:11031*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11031*FLEN/8, x4, x1, x2)

inst_3678:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8400;
op3val:0x3ff; valaddr_reg:x3; val_offset:11034*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11034*FLEN/8, x4, x1, x2)

inst_3679:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8400;
op3val:0x83ff; valaddr_reg:x3; val_offset:11037*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11037*FLEN/8, x4, x1, x2)

inst_3680:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8400;
op3val:0x400; valaddr_reg:x3; val_offset:11040*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11040*FLEN/8, x4, x1, x2)

inst_3681:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8400;
op3val:0x8400; valaddr_reg:x3; val_offset:11043*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11043*FLEN/8, x4, x1, x2)

inst_3682:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8400;
op3val:0x401; valaddr_reg:x3; val_offset:11046*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11046*FLEN/8, x4, x1, x2)

inst_3683:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8400;
op3val:0x8455; valaddr_reg:x3; val_offset:11049*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11049*FLEN/8, x4, x1, x2)

inst_3684:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8400;
op3val:0x7bff; valaddr_reg:x3; val_offset:11052*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11052*FLEN/8, x4, x1, x2)

inst_3685:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8400;
op3val:0xfbff; valaddr_reg:x3; val_offset:11055*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11055*FLEN/8, x4, x1, x2)

inst_3686:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8400;
op3val:0x7c00; valaddr_reg:x3; val_offset:11058*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11058*FLEN/8, x4, x1, x2)

inst_3687:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8400;
op3val:0xfc00; valaddr_reg:x3; val_offset:11061*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11061*FLEN/8, x4, x1, x2)

inst_3688:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8400;
op3val:0x7e00; valaddr_reg:x3; val_offset:11064*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11064*FLEN/8, x4, x1, x2)

inst_3689:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8400;
op3val:0xfe00; valaddr_reg:x3; val_offset:11067*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11067*FLEN/8, x4, x1, x2)

inst_3690:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8400;
op3val:0x7e01; valaddr_reg:x3; val_offset:11070*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11070*FLEN/8, x4, x1, x2)

inst_3691:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8400;
op3val:0xfe55; valaddr_reg:x3; val_offset:11073*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11073*FLEN/8, x4, x1, x2)

inst_3692:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8400;
op3val:0x7c01; valaddr_reg:x3; val_offset:11076*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11076*FLEN/8, x4, x1, x2)

inst_3693:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8400;
op3val:0xfd55; valaddr_reg:x3; val_offset:11079*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11079*FLEN/8, x4, x1, x2)

inst_3694:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8400;
op3val:0x3c00; valaddr_reg:x3; val_offset:11082*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11082*FLEN/8, x4, x1, x2)

inst_3695:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8400;
op3val:0xbc00; valaddr_reg:x3; val_offset:11085*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11085*FLEN/8, x4, x1, x2)

inst_3696:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x401;
op3val:0x0; valaddr_reg:x3; val_offset:11088*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11088*FLEN/8, x4, x1, x2)

inst_3697:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x401;
op3val:0x8000; valaddr_reg:x3; val_offset:11091*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11091*FLEN/8, x4, x1, x2)

inst_3698:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x401;
op3val:0x1; valaddr_reg:x3; val_offset:11094*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11094*FLEN/8, x4, x1, x2)

inst_3699:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x401;
op3val:0x8001; valaddr_reg:x3; val_offset:11097*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11097*FLEN/8, x4, x1, x2)

inst_3700:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x401;
op3val:0x2; valaddr_reg:x3; val_offset:11100*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11100*FLEN/8, x4, x1, x2)

inst_3701:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x401;
op3val:0x83fe; valaddr_reg:x3; val_offset:11103*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11103*FLEN/8, x4, x1, x2)

inst_3702:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x401;
op3val:0x3ff; valaddr_reg:x3; val_offset:11106*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11106*FLEN/8, x4, x1, x2)

inst_3703:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x401;
op3val:0x83ff; valaddr_reg:x3; val_offset:11109*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11109*FLEN/8, x4, x1, x2)

inst_3704:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x401;
op3val:0x400; valaddr_reg:x3; val_offset:11112*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11112*FLEN/8, x4, x1, x2)

inst_3705:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x401;
op3val:0x8400; valaddr_reg:x3; val_offset:11115*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11115*FLEN/8, x4, x1, x2)

inst_3706:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x401;
op3val:0x401; valaddr_reg:x3; val_offset:11118*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11118*FLEN/8, x4, x1, x2)

inst_3707:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x401;
op3val:0x8455; valaddr_reg:x3; val_offset:11121*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11121*FLEN/8, x4, x1, x2)

inst_3708:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x401;
op3val:0x7bff; valaddr_reg:x3; val_offset:11124*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11124*FLEN/8, x4, x1, x2)

inst_3709:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x401;
op3val:0xfbff; valaddr_reg:x3; val_offset:11127*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11127*FLEN/8, x4, x1, x2)

inst_3710:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x401;
op3val:0x7c00; valaddr_reg:x3; val_offset:11130*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11130*FLEN/8, x4, x1, x2)

inst_3711:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x401;
op3val:0xfc00; valaddr_reg:x3; val_offset:11133*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11133*FLEN/8, x4, x1, x2)

RVTEST_SIGBASE(x1,signature_x1_30)
inst_3712:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x401;
op3val:0x7e00; valaddr_reg:x3; val_offset:11136*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11136*FLEN/8, x4, x1, x2)

inst_3713:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x401;
op3val:0xfe00; valaddr_reg:x3; val_offset:11139*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11139*FLEN/8, x4, x1, x2)

inst_3714:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x401;
op3val:0x7e01; valaddr_reg:x3; val_offset:11142*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11142*FLEN/8, x4, x1, x2)

inst_3715:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x401;
op3val:0xfe55; valaddr_reg:x3; val_offset:11145*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11145*FLEN/8, x4, x1, x2)

inst_3716:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x401;
op3val:0x7c01; valaddr_reg:x3; val_offset:11148*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11148*FLEN/8, x4, x1, x2)

inst_3717:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x401;
op3val:0xfd55; valaddr_reg:x3; val_offset:11151*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11151*FLEN/8, x4, x1, x2)

inst_3718:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x401;
op3val:0x3c00; valaddr_reg:x3; val_offset:11154*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11154*FLEN/8, x4, x1, x2)

inst_3719:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x001 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x401;
op3val:0xbc00; valaddr_reg:x3; val_offset:11157*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11157*FLEN/8, x4, x1, x2)

inst_3720:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8455;
op3val:0x0; valaddr_reg:x3; val_offset:11160*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11160*FLEN/8, x4, x1, x2)

inst_3721:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8455;
op3val:0x8000; valaddr_reg:x3; val_offset:11163*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11163*FLEN/8, x4, x1, x2)

inst_3722:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8455;
op3val:0x1; valaddr_reg:x3; val_offset:11166*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11166*FLEN/8, x4, x1, x2)

inst_3723:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8455;
op3val:0x8001; valaddr_reg:x3; val_offset:11169*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11169*FLEN/8, x4, x1, x2)

inst_3724:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8455;
op3val:0x2; valaddr_reg:x3; val_offset:11172*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11172*FLEN/8, x4, x1, x2)

inst_3725:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8455;
op3val:0x83fe; valaddr_reg:x3; val_offset:11175*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11175*FLEN/8, x4, x1, x2)

inst_3726:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8455;
op3val:0x3ff; valaddr_reg:x3; val_offset:11178*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11178*FLEN/8, x4, x1, x2)

inst_3727:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8455;
op3val:0x83ff; valaddr_reg:x3; val_offset:11181*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11181*FLEN/8, x4, x1, x2)

inst_3728:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8455;
op3val:0x400; valaddr_reg:x3; val_offset:11184*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11184*FLEN/8, x4, x1, x2)

inst_3729:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8455;
op3val:0x8400; valaddr_reg:x3; val_offset:11187*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11187*FLEN/8, x4, x1, x2)

inst_3730:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8455;
op3val:0x401; valaddr_reg:x3; val_offset:11190*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11190*FLEN/8, x4, x1, x2)

inst_3731:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8455;
op3val:0x8455; valaddr_reg:x3; val_offset:11193*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11193*FLEN/8, x4, x1, x2)

inst_3732:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8455;
op3val:0x7bff; valaddr_reg:x3; val_offset:11196*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11196*FLEN/8, x4, x1, x2)

inst_3733:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8455;
op3val:0xfbff; valaddr_reg:x3; val_offset:11199*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11199*FLEN/8, x4, x1, x2)

inst_3734:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8455;
op3val:0x7c00; valaddr_reg:x3; val_offset:11202*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11202*FLEN/8, x4, x1, x2)

inst_3735:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8455;
op3val:0xfc00; valaddr_reg:x3; val_offset:11205*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11205*FLEN/8, x4, x1, x2)

inst_3736:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8455;
op3val:0x7e00; valaddr_reg:x3; val_offset:11208*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11208*FLEN/8, x4, x1, x2)

inst_3737:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8455;
op3val:0xfe00; valaddr_reg:x3; val_offset:11211*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11211*FLEN/8, x4, x1, x2)

inst_3738:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8455;
op3val:0x7e01; valaddr_reg:x3; val_offset:11214*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11214*FLEN/8, x4, x1, x2)

inst_3739:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8455;
op3val:0xfe55; valaddr_reg:x3; val_offset:11217*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11217*FLEN/8, x4, x1, x2)

inst_3740:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8455;
op3val:0x7c01; valaddr_reg:x3; val_offset:11220*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11220*FLEN/8, x4, x1, x2)

inst_3741:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8455;
op3val:0xfd55; valaddr_reg:x3; val_offset:11223*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11223*FLEN/8, x4, x1, x2)

inst_3742:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8455;
op3val:0x3c00; valaddr_reg:x3; val_offset:11226*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11226*FLEN/8, x4, x1, x2)

inst_3743:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055 and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x8455;
op3val:0xbc00; valaddr_reg:x3; val_offset:11229*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11229*FLEN/8, x4, x1, x2)

inst_3744:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7bff;
op3val:0x0; valaddr_reg:x3; val_offset:11232*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11232*FLEN/8, x4, x1, x2)

inst_3745:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7bff;
op3val:0x8000; valaddr_reg:x3; val_offset:11235*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11235*FLEN/8, x4, x1, x2)

inst_3746:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7bff;
op3val:0x1; valaddr_reg:x3; val_offset:11238*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11238*FLEN/8, x4, x1, x2)

inst_3747:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7bff;
op3val:0x8001; valaddr_reg:x3; val_offset:11241*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11241*FLEN/8, x4, x1, x2)

inst_3748:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7bff;
op3val:0x2; valaddr_reg:x3; val_offset:11244*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11244*FLEN/8, x4, x1, x2)

inst_3749:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7bff;
op3val:0x83fe; valaddr_reg:x3; val_offset:11247*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11247*FLEN/8, x4, x1, x2)

inst_3750:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7bff;
op3val:0x3ff; valaddr_reg:x3; val_offset:11250*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11250*FLEN/8, x4, x1, x2)

inst_3751:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7bff;
op3val:0x83ff; valaddr_reg:x3; val_offset:11253*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11253*FLEN/8, x4, x1, x2)

inst_3752:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7bff;
op3val:0x400; valaddr_reg:x3; val_offset:11256*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11256*FLEN/8, x4, x1, x2)

inst_3753:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7bff;
op3val:0x8400; valaddr_reg:x3; val_offset:11259*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11259*FLEN/8, x4, x1, x2)

inst_3754:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7bff;
op3val:0x401; valaddr_reg:x3; val_offset:11262*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11262*FLEN/8, x4, x1, x2)

inst_3755:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7bff;
op3val:0x8455; valaddr_reg:x3; val_offset:11265*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11265*FLEN/8, x4, x1, x2)

inst_3756:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7bff;
op3val:0x7bff; valaddr_reg:x3; val_offset:11268*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11268*FLEN/8, x4, x1, x2)

inst_3757:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7bff;
op3val:0xfbff; valaddr_reg:x3; val_offset:11271*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11271*FLEN/8, x4, x1, x2)

inst_3758:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7bff;
op3val:0x7c00; valaddr_reg:x3; val_offset:11274*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11274*FLEN/8, x4, x1, x2)

inst_3759:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7bff;
op3val:0xfc00; valaddr_reg:x3; val_offset:11277*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11277*FLEN/8, x4, x1, x2)

inst_3760:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7bff;
op3val:0x7e00; valaddr_reg:x3; val_offset:11280*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11280*FLEN/8, x4, x1, x2)

inst_3761:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7bff;
op3val:0xfe00; valaddr_reg:x3; val_offset:11283*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11283*FLEN/8, x4, x1, x2)

inst_3762:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7bff;
op3val:0x7e01; valaddr_reg:x3; val_offset:11286*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11286*FLEN/8, x4, x1, x2)

inst_3763:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7bff;
op3val:0xfe55; valaddr_reg:x3; val_offset:11289*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11289*FLEN/8, x4, x1, x2)

inst_3764:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7bff;
op3val:0x7c01; valaddr_reg:x3; val_offset:11292*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11292*FLEN/8, x4, x1, x2)

inst_3765:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7bff;
op3val:0xfd55; valaddr_reg:x3; val_offset:11295*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11295*FLEN/8, x4, x1, x2)

inst_3766:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7bff;
op3val:0x3c00; valaddr_reg:x3; val_offset:11298*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11298*FLEN/8, x4, x1, x2)

inst_3767:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7bff;
op3val:0xbc00; valaddr_reg:x3; val_offset:11301*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11301*FLEN/8, x4, x1, x2)

inst_3768:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfbff;
op3val:0x0; valaddr_reg:x3; val_offset:11304*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11304*FLEN/8, x4, x1, x2)

inst_3769:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfbff;
op3val:0x8000; valaddr_reg:x3; val_offset:11307*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11307*FLEN/8, x4, x1, x2)

inst_3770:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfbff;
op3val:0x1; valaddr_reg:x3; val_offset:11310*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11310*FLEN/8, x4, x1, x2)

inst_3771:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfbff;
op3val:0x8001; valaddr_reg:x3; val_offset:11313*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11313*FLEN/8, x4, x1, x2)

inst_3772:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x002 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfbff;
op3val:0x2; valaddr_reg:x3; val_offset:11316*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11316*FLEN/8, x4, x1, x2)

inst_3773:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3fe and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfbff;
op3val:0x83fe; valaddr_reg:x3; val_offset:11319*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11319*FLEN/8, x4, x1, x2)

inst_3774:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfbff;
op3val:0x3ff; valaddr_reg:x3; val_offset:11322*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11322*FLEN/8, x4, x1, x2)

inst_3775:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x00 and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfbff;
op3val:0x83ff; valaddr_reg:x3; val_offset:11325*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11325*FLEN/8, x4, x1, x2)

inst_3776:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfbff;
op3val:0x400; valaddr_reg:x3; val_offset:11328*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11328*FLEN/8, x4, x1, x2)

inst_3777:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfbff;
op3val:0x8400; valaddr_reg:x3; val_offset:11331*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11331*FLEN/8, x4, x1, x2)

inst_3778:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x01 and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfbff;
op3val:0x401; valaddr_reg:x3; val_offset:11334*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11334*FLEN/8, x4, x1, x2)

inst_3779:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x01 and fm3 == 0x055 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfbff;
op3val:0x8455; valaddr_reg:x3; val_offset:11337*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11337*FLEN/8, x4, x1, x2)

inst_3780:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfbff;
op3val:0x7bff; valaddr_reg:x3; val_offset:11340*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11340*FLEN/8, x4, x1, x2)

inst_3781:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfbff;
op3val:0xfbff; valaddr_reg:x3; val_offset:11343*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11343*FLEN/8, x4, x1, x2)

inst_3782:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfbff;
op3val:0x7c00; valaddr_reg:x3; val_offset:11346*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11346*FLEN/8, x4, x1, x2)

inst_3783:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfbff;
op3val:0xfc00; valaddr_reg:x3; val_offset:11349*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11349*FLEN/8, x4, x1, x2)

inst_3784:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfbff;
op3val:0x7e00; valaddr_reg:x3; val_offset:11352*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11352*FLEN/8, x4, x1, x2)

inst_3785:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x200 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfbff;
op3val:0xfe00; valaddr_reg:x3; val_offset:11355*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11355*FLEN/8, x4, x1, x2)

inst_3786:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x201 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfbff;
op3val:0x7e01; valaddr_reg:x3; val_offset:11358*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11358*FLEN/8, x4, x1, x2)

inst_3787:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x255 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfbff;
op3val:0xfe55; valaddr_reg:x3; val_offset:11361*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11361*FLEN/8, x4, x1, x2)

inst_3788:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x1f and fm3 == 0x001 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfbff;
op3val:0x7c01; valaddr_reg:x3; val_offset:11364*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11364*FLEN/8, x4, x1, x2)

inst_3789:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x1f and fm3 == 0x155 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfbff;
op3val:0xfd55; valaddr_reg:x3; val_offset:11367*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11367*FLEN/8, x4, x1, x2)

inst_3790:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfbff;
op3val:0x3c00; valaddr_reg:x3; val_offset:11370*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11370*FLEN/8, x4, x1, x2)

inst_3791:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 1 and fe3 == 0x0f and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0xfbff;
op3val:0xbc00; valaddr_reg:x3; val_offset:11373*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11373*FLEN/8, x4, x1, x2)

inst_3792:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7c00;
op3val:0x0; valaddr_reg:x3; val_offset:11376*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11376*FLEN/8, x4, x1, x2)

inst_3793:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fs2 == 0 and fe2 == 0x1f and fm2 == 0x000 and fs3 == 1 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff  
/* opcode: fnmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x3ff; op2val:0x7c00;
op3val:0x8000; valaddr_reg:x3; val_offset:11379*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fnmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 11379*FLEN/8, x4, x1, x2)

#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(33791,16,FLEN)
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NAN_BOXED(1023,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(64512,16,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;



signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_2:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_3:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_4:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_5:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_6:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_7:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_8:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_9:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_10:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_11:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_12:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_13:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_14:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_15:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_16:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_17:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_18:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_19:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_20:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_21:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_22:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_23:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_24:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_25:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_26:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_27:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_28:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_29:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_30:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_31:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_32:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_33:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_34:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_35:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_36:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_37:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_38:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_39:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_40:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_41:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_42:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_43:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_44:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_45:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_46:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_47:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_48:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_49:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_50:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_51:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_52:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_53:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_54:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_55:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_56:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_57:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_58:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_59:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_60:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_61:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_62:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_63:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_64:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_65:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_66:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_67:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_68:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_69:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_70:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_71:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_72:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_73:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_74:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_75:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_76:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_77:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_78:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_79:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_80:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_81:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_82:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_83:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_84:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_85:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_86:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_87:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_88:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_89:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_90:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_91:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_92:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_93:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_94:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_95:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_96:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_97:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_98:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_99:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_100:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_101:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_102:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_103:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_104:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_105:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_106:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_107:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_108:
    .fill 256*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_109:
    .fill 14*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;

mtrap_sigptr:
    .fill 64*XLEN/32,4,0xdeadbeef

tsig_end_canary:
CANARY;
#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif


sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
